143 lines
5 KiB
C
Executable file
143 lines
5 KiB
C
Executable file
/*
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* core.h - DesignWare USB3 DRD Core Header
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 of
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* the License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DRIVERS_USB_DWC3_CORE_EXYNOS_H
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#define __DRIVERS_USB_DWC3_CORE_EXYNOS_H
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#define DWC3_GDBGLSPMUX_HST 0xc170
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/* LINK Registers */
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#define DWC3_LSKIPFREQ 0xd020
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#define DWC3_LLUCTL 0xd024
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/* Bit fields */
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/* Link Register - LLUCTL */
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#define DWC3_PENDING_HP_TIMER_US(n) ((n) << 16)
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#define DWC3_EN_US_HP_TIMER BIT(15)
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#define DWC3_FORCE_GEN1 BIT(10)
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/* Link Register - LSKIPFREQ */
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#define DWC3_PM_ENTRY_TIMER_US(n) ((n) << 20)
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#define DWC3_PM_LC_TIMER_US(n) ((n) << 24)
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#define DWC3_EN_PM_TIMER_US BIT(27)
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/* Global Debug Queue/FIFO Space Available Register */
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#define DWC3_GSBUSCFG0_INCRBRSTEN (1 << 0)
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#define DWC3_GSBUSCFG0_INCR4BRSTEN (1 << 1)
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#define DWC3_GSBUSCFG0_INCR8BRSTEN (1 << 2)
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#define DWC3_GSBUSCFG0_INCR16BRSTEN (1 << 3)
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#define DWC3_GSBUSCFG0_INCR32BRSTEN (1 << 4)
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#define DWC3_GSBUSCFG0_INCR64BRSTEN (1 << 5)
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#define DWC3_GSBUSCFG0_INCR128BRSTEN (1 << 6)
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#define DWC3_GSBUSCFG0_INCR256BRSTEN (1 << 7)
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#define DWC3_GSBUSCFG0_DESWRREQINFO (2 << 16)
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#define DWC3_GSBUSCFG0_DATWRREQINFO (2 << 20)
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#define DWC3_GSBUSCFG0_DESRDREQINFO (2 << 24)
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#define DWC3_GSBUSCFG0_DATRDREQINFO (2 << 28)
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#define DWC3_GSBUSCFG1_BREQLIMIT(n) ((n) << 8)
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#define DWC3_GSBUSCFG1_BREQLIMIT_SHIFT 8
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#define DWC3_GSBUSCFG1_BREQLIMIT_MASK (0xf << 8)
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#define DWC3_GSBUSCFG1_EN1KPAGE (1 << 12)
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#define DWC3_GRXTHRCFG_USBRXPKTCNTSEL (1 << 29)
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#define DWC3_GRXTHRCFG_USBRXPKTCNT_MASK (0xf << 24)
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#define DWC3_GRXTHRCFG_USBRXPKTCNT_SHIFT 24
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#define DWC3_GRXTHRCFG_USBRXPKTCNT(n) ((n) << 24)
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#define DWC3_GRXTHRCFG_USBMAXRXBURSTSIZE_MASK (0x1f << 19)
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#define DWC3_GRXTHRCFG_USBMAXRXBURSTSIZE_SHIFT 19
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#define DWC3_GRXTHRCFG_USBMAXRXBURSTSIZE(n) ((n) << 19)
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#define DWC3_GCTL_PWRDNSCALE_MASK DWC3_GCTL_PWRDNSCALE(0x1fff)
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#define DWC3_GUCTL_REFCLKPER(n) ((n) << 22)
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#define DWC3_GUCTL_REFCLKPER_MASK DWC3_GUCTL_REFCLKPER(0x3FF)
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#define DWC3_GUCTL_USBHSTINAUTORETRYEN (1 << 14)
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#define DWC3_GUCTL_SPRSCTRLTRANSEN (1 << 17)
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/* Global USB3 PIPE Control Register */
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#define DWC3_GUSB3PIPECTL_U1U2EXITFAIL_TO_RECOV BIT(25)
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#define DWC3_ELASTIC_BUFFER_MODE BIT(0)
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/* Global Frame Length Adjustment Register */
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#define DWC3_GFLADJ_REFCLK_240MHZDECR_PLS1 BIT(31)
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#define DWC3_GFLADJ_REFCLK_240MHZ_DECR(n) ((n) << 24)
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#define DWC3_GFLADJ_REFCLK_240MHZ_DECR_MASK DWC3_GFLADJ_REFCLK_240MHZ_DECR(0x7F)
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#define DWC3_GFLADJ_REFCLK_LPM_SEL BIT(23)
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#define DWC3_GFLADJ_REFCLK_FLADJ(n) ((n) << 8)
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#define DWC3_GFLADJ_REFCLK_FLADJ_MASK DWC3_GFLADJ_REFCLK_FLADJ(0x3FFF)
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#define DWC3_GFLADJ_REFCLK_240MHZDECR_PLS1 BIT(31)
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#define DWC3_GFLADJ_REFCLK_240MHZ_DECR(n) ((n) << 24)
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#define DWC3_GFLADJ_REFCLK_240MHZ_DECR_MASK DWC3_GFLADJ_REFCLK_240MHZ_DECR(0x7F)
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#define DWC3_GFLADJ_REFCLK_LPM_SEL BIT(23)
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#define DWC3_GFLADJ_REFCLK_FLADJ(n) ((n) << 8)
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#define DWC3_GFLADJ_REFCLK_FLADJ_MASK DWC3_GFLADJ_REFCLK_FLADJ(0x3FFF)
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/* Global User Control Register */
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#define DWC3_GUCTL_REFCLKPER(n) ((n) << 22)
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#define DWC3_GUCTL_NOEXTRDL (1 << 21)
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#define DWC3_GUCTL_USBHSTINAUTORETRYEN (1 << 14)
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#define DWC3_GUCTL_SPRSCTRLTRANSEN (1 << 17)
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#define DWC3_GUCTL_RESBWHSEPS (1 << 16)
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#define DWC3_GUCTL_DTOUT(n) (n)
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#define DWC3_GUCTL_DTOUT_MASK (0x7ff)
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#define DWC3_DCFG_FULLSPEED1 (3 << 0)
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#define DWC3_DEVTEN_U3L2_SUSPEN BIT(6)
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#define DWC3_DSTS_FULLSPEED1 (3 << 0)
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/* OTG Control Register */
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#define DWC3_OTG_OCTL_PERIMODE (1 << 6)
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/* OTG Events Register */
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#define DWC3_OEVT_CLEAR_ALL (~DWC3_OEVT_DEVICEMODE)
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#define DWC3_OEVTEN_OTGCONIDSTSCHNGEVNT (1 << 24)
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#define DWC3_OEVTEN_OTGBDEVVBUSCHNGEVNT (1 << 8)
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/* OTG Status Register */
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#define DWC3_OTG_OSTS_BSESVALID (1 << 2)
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#define DWC3_OTG_OSTS_CONIDSTS (1 << 0)
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#define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
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int exynos_usbdrd_phy_tune(struct phy *phy, int phy_state);
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void exynos_usbdrd_phy_conn(struct phy *phy, int is_conn);
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void exynos_usbdrd_phy_vol_set(struct phy *phy, int voltage);
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int exynos_usbdrd_ldo_manual_control(bool on);
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//int exynos_usbdrd_dp_ilbk(struct phy *phy);
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int exynos_usbdrd_phy_set(struct phy *phy, int option, void *info);
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#if IS_ENABLED(CONFIG_OTG_CDP_SUPPORT)
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void exynos_usbdrd_cdp_set(struct phy *phy, int val);
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#endif
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enum dwc3_phy_owner {
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DWC3_PHY_OWNER_SELF = 0,
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DWC3_PHY_OWNER_DP = 1,
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DWC3_PHY_OWNER_EMEG = 8,
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};
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#define CHG_CONNECTED_DELAY_TIME (HZ * 20) /* 20s */
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#define MAX_RETRY_CNT 3
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#define REMOVED_RETRY_CNT 99
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#define MAX_PLATFORM_WAITING_CNT 40
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#endif /* __DRIVERS_USB_DWC3_CORE_H */
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