15298 lines
1.6 MiB
Executable file
15298 lines
1.6 MiB
Executable file
#include "../cmucal.h"
|
|
#include "cmucal-sfr.h"
|
|
|
|
unsigned int cmucal_sfr_block_size = 45;
|
|
struct sfr_block cmucal_sfr_block_list[] = {
|
|
SFR_BLOCK(CMU_AUD, 0x18c00000, 0x8000),
|
|
SFR_BLOCK(CMU_TOP, 0x1a330000, 0x8000),
|
|
SFR_BLOCK(CMU_CPUCL0, 0x1d040000, 0x8000),
|
|
SFR_BLOCK(CMU_CPUCL1, 0x1d050000, 0x8000),
|
|
SFR_BLOCK(CMU_CPUCL2, 0x1d060000, 0x8000),
|
|
SFR_BLOCK(CMU_DSU, 0x1d030000, 0x8000),
|
|
SFR_BLOCK(CMU_MIF, 0x1c000000, 0x8000),
|
|
SFR_BLOCK(CMU_S2D, 0x15a30000, 0x8000),
|
|
SFR_BLOCK(CMU_ALIVE, 0x15800000, 0x8000),
|
|
SFR_BLOCK(CMU_BUS0, 0x1a300000, 0x8000),
|
|
SFR_BLOCK(CMU_BUS1, 0x1a400000, 0x8000),
|
|
SFR_BLOCK(CMU_BUS2, 0x1a600000, 0x8000),
|
|
SFR_BLOCK(CMU_CMGP, 0x14e00000, 0x8000),
|
|
SFR_BLOCK(CMU_CORE, 0x1a030000, 0x8000),
|
|
SFR_BLOCK(CMU_G3D, 0x18400000, 0x8000),
|
|
SFR_BLOCK(CMU_HSI0, 0x10a00000, 0x8000),
|
|
SFR_BLOCK(CMU_PERIC0, 0x10400000, 0x8000),
|
|
SFR_BLOCK(CMU_PERIC1, 0x10700000, 0x8000),
|
|
SFR_BLOCK(CMU_PERIC2, 0x11d00000, 0x8000),
|
|
SFR_BLOCK(CMU_VTS, 0x15500000, 0x8000),
|
|
SFR_BLOCK(CMU_CPUCL0_GLB, 0x1d020000, 0x8000),
|
|
SFR_BLOCK(CMU_CSIS, 0x17000000, 0x8000),
|
|
SFR_BLOCK(CMU_DNS, 0x17500000, 0x8000),
|
|
SFR_BLOCK(CMU_DPUB, 0x19e00000, 0x8000),
|
|
SFR_BLOCK(CMU_DPUF0, 0x19c00000, 0x8000),
|
|
SFR_BLOCK(CMU_DPUF1, 0x1ae00000, 0x8000),
|
|
SFR_BLOCK(CMU_HSI1, 0x11000000, 0x8000),
|
|
SFR_BLOCK(CMU_ITP, 0x17400000, 0x8000),
|
|
SFR_BLOCK(CMU_LME, 0x17700000, 0x8000),
|
|
SFR_BLOCK(CMU_M2M, 0x18900000, 0x8000),
|
|
SFR_BLOCK(CMU_MCFP0, 0x17800000, 0x8000),
|
|
SFR_BLOCK(CMU_MCFP1, 0x17a00000, 0x8000),
|
|
SFR_BLOCK(CMU_MCSC, 0x15c00000, 0x8000),
|
|
SFR_BLOCK(CMU_MFC0, 0x18600000, 0x8000),
|
|
SFR_BLOCK(CMU_MFC1, 0x18800000, 0x8000),
|
|
SFR_BLOCK(CMU_NPU, 0x19800000, 0x8000),
|
|
SFR_BLOCK(CMU_NPU01, 0x19900000, 0x8000),
|
|
SFR_BLOCK(CMU_NPU10, 0x19a00000, 0x8000),
|
|
SFR_BLOCK(CMU_NPUS, 0x17c00000, 0x8000),
|
|
SFR_BLOCK(CMU_PERIS, 0x10020000, 0x8000),
|
|
SFR_BLOCK(CMU_SSP, 0x18200000, 0x8000),
|
|
SFR_BLOCK(CMU_TAA, 0x16e00000, 0x8000),
|
|
SFR_BLOCK(CMU_VPC, 0x16600000, 0x8000),
|
|
SFR_BLOCK(CMU_VPD, 0x16800000, 0x8000),
|
|
SFR_BLOCK(CMU_YUVPP, 0x18000000, 0x8000),
|
|
};
|
|
|
|
unsigned int dbg_offset = 0x4000;
|
|
unsigned int cmucal_sfr_size = 3624;
|
|
struct sfr cmucal_sfr_list[] = {
|
|
SFR(OSC_LOCKTIME_RCO_400, 0x0, CMU_ALIVE),
|
|
SFR(OSC_CON0_RCO_400, 0x100, CMU_ALIVE),
|
|
SFR(OSC_CON1_RCO_400, 0x104, CMU_ALIVE),
|
|
SFR(OSC_CON2_RCO_400, 0x108, CMU_ALIVE),
|
|
SFR(OSC_CON3_RCO_400, 0x10c, CMU_ALIVE),
|
|
SFR(OSC_CON4_RCO_400, 0x110, CMU_ALIVE),
|
|
SFR(PLL_LOCKTIME_PLL_AUD0, 0x0, CMU_AUD),
|
|
SFR(PLL_CON3_PLL_AUD0, 0x10c, CMU_AUD),
|
|
SFR(PLL_CON8_PLL_AUD0, 0x120, CMU_AUD),
|
|
SFR(PLL_LOCKTIME_PLL_AUD1, 0x4, CMU_AUD),
|
|
SFR(PLL_CON3_PLL_AUD1, 0x14c, CMU_AUD),
|
|
SFR(PLL_CON8_PLL_AUD1, 0x160, CMU_AUD),
|
|
SFR(PLL_LOCKTIME_PLL_G3D, 0x0, CMU_TOP),
|
|
SFR(PLL_CON3_PLL_G3D, 0x10c, CMU_TOP),
|
|
SFR(PLL_LOCKTIME_PLL_MMC, 0x4, CMU_TOP),
|
|
SFR(PLL_CON3_PLL_MMC, 0x14c, CMU_TOP),
|
|
SFR(PLL_CON8_PLL_MMC, 0x160, CMU_TOP),
|
|
SFR(PLL_LOCKTIME_PLL_SHARED0, 0x8, CMU_TOP),
|
|
SFR(PLL_CON3_PLL_SHARED0, 0x18c, CMU_TOP),
|
|
SFR(PLL_LOCKTIME_PLL_SHARED1, 0xc, CMU_TOP),
|
|
SFR(PLL_CON3_PLL_SHARED1, 0x1cc, CMU_TOP),
|
|
SFR(PLL_LOCKTIME_PLL_SHARED2, 0x10, CMU_TOP),
|
|
SFR(PLL_CON3_PLL_SHARED2, 0x20c, CMU_TOP),
|
|
SFR(PLL_LOCKTIME_PLL_SHARED3, 0x14, CMU_TOP),
|
|
SFR(PLL_CON3_PLL_SHARED3, 0x24c, CMU_TOP),
|
|
SFR(PLL_LOCKTIME_PLL_SHARED4, 0x18, CMU_TOP),
|
|
SFR(PLL_CON3_PLL_SHARED4, 0x28c, CMU_TOP),
|
|
SFR(PLL_LOCKTIME_PLL_SHARED_MIF, 0x1c, CMU_TOP),
|
|
SFR(PLL_CON3_PLL_SHARED_MIF, 0x2cc, CMU_TOP),
|
|
SFR(PLL_LOCKTIME_PLL_CPUCL0, 0x0, CMU_CPUCL0),
|
|
SFR(PLL_CON3_PLL_CPUCL0, 0x10c, CMU_CPUCL0),
|
|
SFR(PLL_LOCKTIME_PLL_CPUCL1, 0x0, CMU_CPUCL1),
|
|
SFR(PLL_CON3_PLL_CPUCL1, 0x10c, CMU_CPUCL1),
|
|
SFR(PLL_LOCKTIME_PLL_CPUCL2, 0x0, CMU_CPUCL2),
|
|
SFR(PLL_CON3_PLL_CPUCL2, 0x10c, CMU_CPUCL2),
|
|
SFR(PLL_LOCKTIME_PLL_DSU, 0x0, CMU_DSU),
|
|
SFR(PLL_CON3_PLL_DSU, 0x10c, CMU_DSU),
|
|
SFR(PLL_LOCKTIME_PLL_MIF_MAIN, 0x0, CMU_MIF),
|
|
SFR(PLL_CON3_PLL_MIF_MAIN, 0x10c, CMU_MIF),
|
|
SFR(PLL_LOCKTIME_PLL_MIF_SUB, 0x4, CMU_MIF),
|
|
SFR(PLL_CON3_PLL_MIF_SUB, 0x14c, CMU_MIF),
|
|
SFR(PLL_LOCKTIME_PLL_MIF_S2D, 0x0, CMU_S2D),
|
|
SFR(PLL_CON3_PLL_MIF_S2D, 0x10c, CMU_S2D),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS, 0x1000, CMU_ALIVE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_ALIVE_BUS, 0x1008, CMU_ALIVE),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_VTS_BUS, 0x1004, CMU_ALIVE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC, 0x1010, CMU_ALIVE),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI, 0x1020, CMU_ALIVE),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CMGP_ADC, 0x101c, CMU_ALIVE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0x1018, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0x1014, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0x1010, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0x100c, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_CPU, 0x1004, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_DSIF, 0x1008, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0x101c, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0x1020, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0x1024, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_CNT, 0x1000, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_BUS, 0x102c, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_AUD_PCMC, 0x1030, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_BUS0_CMUREF, 0x1000, CMU_BUS0),
|
|
SFR(CLK_CON_MUX_MUX_BUS1_CMUREF, 0x1000, CMU_BUS1),
|
|
SFR(CLK_CON_MUX_MUX_BUS2_CMUREF, 0x1000, CMU_BUS2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMGP_I2C0, 0x100c, CMU_CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI0, 0x101c, CMU_CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI1, 0x1020, CMU_CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI2, 0x1024, CMU_CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI3, 0x1028, CMU_CMGP),
|
|
SFR(CLK_CON_MUX_CLK_CMGP_ADC, 0x1000, CMU_CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMGP_I2C1, 0x1010, CMU_CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMGP_I2C2, 0x1014, CMU_CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMGP_I2C3, 0x1018, CMU_CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CMGP_I3C, 0x1004, CMU_CMGP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0, 0x10b8, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_VPD_BUS, 0x1068, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0x103c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0x1034, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0x10c4, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_TAA_BUS, 0x10a4, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0x10a8, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0x1008, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_HPM, 0x1074, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS, 0x1038, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0x1018, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0x101c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0x1020, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0x1024, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CMU_CMUREF, 0x10f4, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0x10cc, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0x10d4, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0x10dc, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0x1090, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_NPU_BUS, 0x10c8, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS, 0x1004, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0x1088, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 0x1048, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD, 0x10bc, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0x10c0, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0, 0x10d0, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0, 0x10d8, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_DPUF0_BUS, 0x1000, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DPUF0_ALT, 0x1064, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0x1040, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0x1078, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF, 0x10f0, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_YUVPP_BUS, 0x10e8, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0x1028, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DPUF0, 0x1060, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0x1030, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0x1010, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CSIS_CSIS, 0x104c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MCFP0_BUS, 0x10e4, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS, 0x10ac, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0x105c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS, 0x1058, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC, 0x10b0, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU, 0x1050, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_SSP_SSPCORE, 0x10e0, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0x102c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU, 0x108c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_M2M_BUS, 0x1124, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT, 0x10ec, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_DPUB_BUS, 0x100c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DPUB, 0x10b4, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1, 0x1130, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_BUS1_SBIC, 0x1080, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_LME_BUS, 0x1120, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MCFP1_MCFP1, 0x1128, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_VPC_BUS, 0x114c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0x107c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0x1084, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 0x1110, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG, 0x1114, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0x110c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_AUD_BUS, 0x1070, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MCFP1_ORBMCH, 0x112c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CSIS_PDP, 0x10a0, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CP_UCPU_CLK, 0x115c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CP_LCPU_CLK, 0x1158, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CP_HISPEEDY_CLK, 0x1154, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1, 0x1134, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1, 0x1138, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_SSP_BUS, 0x1148, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_YUVPP_FRC, 0x1150, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_G3D_BUS, 0x1104, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_G3D_SHADER, 0x1044, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0, 0x1140, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC2_BUS, 0x113c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1, 0x1144, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DPUF1, 0x10f8, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DPUF1_ALT, 0x10fc, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_DPUF1_BUS, 0x1014, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP, 0x1094, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH, 0x1100, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0x1108, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD, 0x1054, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD, 0x1160, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CORE_CMUREF, 0x1000, CMU_CORE),
|
|
SFR(CLK_CON_MUX_MUX_CPUCL0_CMUREF, 0x100c, CMU_CPUCL0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL0_CORE, 0x1000, CMU_CPUCL0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_DELAY, 0x1004, CMU_CPUCL0),
|
|
SFR(CLK_CON_MUX_MUX_PLL_CPUCL0_DELAY, 0x1010, CMU_CPUCL0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_CORE, 0x1000, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CPUCL1_CMUREF, 0x1004, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CPUCL2_CMUREF, 0x1008, CMU_CPUCL2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL2_CORE, 0x1000, CMU_CPUCL2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_DSU_CLUSTER, 0x1000, CMU_DSU),
|
|
SFR(CLK_CON_MUX_MUX_DSU_CMUREF, 0x100c, CMU_DSU),
|
|
SFR(CLK_CON_MUX_MUX_PLL_DSU_DELAY, 0x1010, CMU_DSU),
|
|
SFR(CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_DELAY, 0x1004, CMU_DSU),
|
|
SFR(CLK_CON_MUX_MUX_CLK_G3D_BUS, 0x1000, CMU_G3D),
|
|
SFR(CLK_CON_MUX_MUX_CLK_HSI0_BUS, 0x1000, CMU_HSI0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD, 0x1004, CMU_HSI0),
|
|
SFR(CLK_CON_MUX_MUX_MIF_CMUREF, 0x1000, CMU_MIF),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0x1004, CMU_PERIC0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0x1014, CMU_PERIC0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0x1028, CMU_PERIC0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC0_USI14_USI, 0x1020, CMU_PERIC0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0x1008, CMU_PERIC0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC0_USI15_USI, 0x1024, CMU_PERIC0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0x1018, CMU_PERIC0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0x1010, CMU_PERIC0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC0_UART_DBG, 0x1000, CMU_PERIC0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0x100c, CMU_PERIC0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC0_USI13_USI, 0x101c, CMU_PERIC0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT, 0x1000, CMU_PERIC1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0x102c, CMU_PERIC1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0x1018, CMU_PERIC1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI, 0x101c, CMU_PERIC1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI, 0x1020, CMU_PERIC1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI, 0x1024, CMU_PERIC1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC1_USI18_USI, 0x1028, CMU_PERIC1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC2_USI07_USI, 0x1008, CMU_PERIC2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC2_USI_I2C, 0x1018, CMU_PERIC2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC2_USI06_USI, 0x1004, CMU_PERIC2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC2_USI08_USI, 0x100c, CMU_PERIC2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC2_USI09_USI, 0x1010, CMU_PERIC2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC2_USI10_USI, 0x1014, CMU_PERIC2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_S2D_CORE, 0x1000, CMU_S2D),
|
|
SFR(CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF, 0x1008, CMU_VTS),
|
|
SFR(CLK_CON_MUX_MUX_CLK_VTS_DMIC_AUD, 0x1004, CMU_VTS),
|
|
SFR(CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF, 0x100c, CMU_VTS),
|
|
SFR(CLK_CON_MUX_MUX_CLK_VTS_DMIC_AHB, 0x1000, CMU_VTS),
|
|
SFR(CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_CORE, 0x1010, CMU_VTS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER, 0x600, CMU_ALIVE),
|
|
SFR(PLL_CON1_MUX_CLKCMU_ALIVE_BUS_USER, 0x604, CMU_ALIVE),
|
|
SFR(PLL_CON0_MUX_CLK_RCO_ALIVE_USER, 0x630, CMU_ALIVE),
|
|
SFR(PLL_CON1_MUX_CLK_RCO_ALIVE_USER, 0x634, CMU_ALIVE),
|
|
SFR(PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER, 0x620, CMU_ALIVE),
|
|
SFR(PLL_CON1_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER, 0x624, CMU_ALIVE),
|
|
SFR(PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 0x600, CMU_AUD),
|
|
SFR(PLL_CON1_MUX_CLKCMU_AUD_CPU_USER, 0x604, CMU_AUD),
|
|
SFR(PLL_CON0_MUX_CLKCMU_AUD_BUS_USER, 0x610, CMU_AUD),
|
|
SFR(PLL_CON1_MUX_CLKCMU_AUD_BUS_USER, 0x614, CMU_AUD),
|
|
SFR(PLL_CON0_MUX_CP_PCMC_CLK_USER, 0x620, CMU_AUD),
|
|
SFR(PLL_CON1_MUX_CP_PCMC_CLK_USER, 0x624, CMU_AUD),
|
|
SFR(PLL_CON0_MUX_CLKCMU_BUS0_BUS_USER, 0x600, CMU_BUS0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_BUS0_BUS_USER, 0x604, CMU_BUS0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER, 0x600, CMU_BUS1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_BUS1_BUS_USER, 0x604, CMU_BUS1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_BUS1_SBIC_USER, 0x620, CMU_BUS1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_BUS1_SBIC_USER, 0x624, CMU_BUS1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_BUS2_BUS_USER, 0x600, CMU_BUS2),
|
|
SFR(PLL_CON1_MUX_CLKCMU_BUS2_BUS_USER, 0x604, CMU_BUS2),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER, 0x600, CMU_CMGP),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CMGP_BUS_USER, 0x604, CMU_CMGP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER, 0x610, CMU_CMGP),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CMGP_PERI_USER, 0x614, CMU_CMGP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CMGP_ADC_USER, 0x620, CMU_CMGP),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CMGP_ADC_USER, 0x624, CMU_CMGP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 0x600, CMU_CORE),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CORE_BUS_USER, 0x604, CMU_CORE),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 0x600, CMU_CPUCL0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER, 0x604, CMU_CPUCL0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER, 0x610, CMU_CPUCL0_GLB),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_BUS_USER, 0x614, CMU_CPUCL0_GLB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER, 0x600, CMU_CPUCL0_GLB),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CPUCL0_BUSP_USER, 0x604, CMU_CPUCL0_GLB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 0x600, CMU_CPUCL1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER, 0x604, CMU_CPUCL1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER, 0x600, CMU_CPUCL2),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER, 0x604, CMU_CPUCL2),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CSIS_CSIS_USER, 0x600, CMU_CSIS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CSIS_CSIS_USER, 0x604, CMU_CSIS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER, 0x610, CMU_CSIS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CSIS_OIS_MCU_USER, 0x614, CMU_CSIS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CSIS_PDP_USER, 0x620, CMU_CSIS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CSIS_PDP_USER, 0x624, CMU_CSIS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DNS_BUS_USER, 0x600, CMU_DNS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_DNS_BUS_USER, 0x604, CMU_DNS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DPUB_BUS_USER, 0x600, CMU_DPUB),
|
|
SFR(PLL_CON1_MUX_CLKCMU_DPUB_BUS_USER, 0x604, CMU_DPUB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DPUF0_BUS_USER, 0x600, CMU_DPUF0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_DPUF0_BUS_USER, 0x604, CMU_DPUF0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DPUF1_BUS_USER, 0x600, CMU_DPUF1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_DPUF1_BUS_USER, 0x604, CMU_DPUF1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER, 0x600, CMU_DSU),
|
|
SFR(PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER, 0x604, CMU_DSU),
|
|
SFR(PLL_CON0_MUX_CLKCMU_G3D_BUS_USER, 0x620, CMU_G3D),
|
|
SFR(PLL_CON1_MUX_CLKCMU_G3D_BUS_USER, 0x624, CMU_G3D),
|
|
SFR(PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_SHADER_USER, 0x600, CMU_G3D),
|
|
SFR(PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_SHADER_USER, 0x604, CMU_G3D),
|
|
SFR(PLL_CON0_MUX_CLKCMU_G3D_SHADER_USER, 0x610, CMU_G3D),
|
|
SFR(PLL_CON1_MUX_CLKCMU_G3D_SHADER_USER, 0x614, CMU_G3D),
|
|
SFR(PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER, 0x630, CMU_G3D),
|
|
SFR(PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER, 0x634, CMU_G3D),
|
|
SFR(PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER, 0x600, CMU_HSI0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER, 0x604, CMU_HSI0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER, 0x620, CMU_HSI0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER, 0x624, CMU_HSI0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER, 0x630, CMU_HSI0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER, 0x634, CMU_HSI0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER, 0x610, CMU_HSI0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER, 0x614, CMU_HSI0),
|
|
SFR(PLL_CON0_MUX_CLKAUD_HSI0_BUS_USER, 0x640, CMU_HSI0),
|
|
SFR(PLL_CON1_MUX_CLKAUD_HSI0_BUS_USER, 0x644, CMU_HSI0),
|
|
SFR(PLL_CON0_MUX_CLKAUD_HSI0_USB31DRD_USER, 0x650, CMU_HSI0),
|
|
SFR(PLL_CON1_MUX_CLKAUD_HSI0_USB31DRD_USER, 0x654, CMU_HSI0),
|
|
SFR(PLL_CON0_MUX_CLK_USB20PHY_USER, 0x660, CMU_HSI0),
|
|
SFR(PLL_CON1_MUX_CLK_USB20PHY_USER, 0x664, CMU_HSI0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_HSI1_BUS_USER, 0x600, CMU_HSI1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_HSI1_BUS_USER, 0x604, CMU_HSI1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER, 0x620, CMU_HSI1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER, 0x624, CMU_HSI1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER, 0x610, CMU_HSI1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_HSI1_MMC_CARD_USER, 0x614, CMU_HSI1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_HSI1_UFS_EMBD_USER, 0x640, CMU_HSI1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_HSI1_UFS_EMBD_USER, 0x644, CMU_HSI1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_ITP_BUS_USER, 0x600, CMU_ITP),
|
|
SFR(PLL_CON1_MUX_CLKCMU_ITP_BUS_USER, 0x604, CMU_ITP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_LME_BUS_USER, 0x600, CMU_LME),
|
|
SFR(PLL_CON1_MUX_CLKCMU_LME_BUS_USER, 0x604, CMU_LME),
|
|
SFR(PLL_CON0_MUX_CLKCMU_M2M_BUS_USER, 0x600, CMU_M2M),
|
|
SFR(PLL_CON1_MUX_CLKCMU_M2M_BUS_USER, 0x604, CMU_M2M),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MCFP0_BUS_USER, 0x600, CMU_MCFP0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MCFP0_BUS_USER, 0x604, CMU_MCFP0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MCFP1_MCFP1_USER, 0x600, CMU_MCFP1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MCFP1_MCFP1_USER, 0x604, CMU_MCFP1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MCFP1_ORBMCH_USER, 0x610, CMU_MCFP1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MCFP1_ORBMCH_USER, 0x614, CMU_MCFP1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER, 0x600, CMU_MCSC),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MCSC_BUS_USER, 0x604, CMU_MCSC),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER, 0x610, CMU_MCSC),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MCSC_GDC_USER, 0x614, CMU_MCSC),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER, 0x600, CMU_MFC0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MFC0_MFC0_USER, 0x604, CMU_MFC0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER, 0x610, CMU_MFC0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MFC0_WFD_USER, 0x614, CMU_MFC0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER, 0x600, CMU_MFC1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MFC1_MFC1_USER, 0x604, CMU_MFC1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER, 0x610, CMU_MIF),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MIF_BUSP_USER, 0x614, CMU_MIF),
|
|
SFR(PLL_CON0_CLKMUX_MIF_DDRPHY2X, 0x600, CMU_MIF),
|
|
SFR(PLL_CON1_CLKMUX_MIF_DDRPHY2X, 0x604, CMU_MIF),
|
|
SFR(PLL_CON0_MUX_CLKCMU_NPU_BUS_USER, 0x600, CMU_NPU),
|
|
SFR(PLL_CON1_MUX_CLKCMU_NPU_BUS_USER, 0x604, CMU_NPU),
|
|
SFR(PLL_CON0_MUX_CLKCMU_NPU01_BUS_USER, 0x600, CMU_NPU01),
|
|
SFR(PLL_CON1_MUX_CLKCMU_NPU01_BUS_USER, 0x604, CMU_NPU01),
|
|
SFR(PLL_CON0_MUX_CLKCMU_NPU10_BUS_USER, 0x600, CMU_NPU10),
|
|
SFR(PLL_CON1_MUX_CLKCMU_NPU10_BUS_USER, 0x604, CMU_NPU10),
|
|
SFR(PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER, 0x600, CMU_NPUS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_NPUS_BUS_USER, 0x604, CMU_NPUS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 0x600, CMU_PERIC0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER, 0x604, CMU_PERIC0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER, 0x620, CMU_PERIC0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIC0_IP0_USER, 0x624, CMU_PERIC0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER, 0x610, CMU_PERIC0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIC0_IP1_USER, 0x614, CMU_PERIC0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 0x600, CMU_PERIC1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER, 0x604, CMU_PERIC1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER, 0x610, CMU_PERIC1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIC1_IP0_USER, 0x614, CMU_PERIC1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER, 0x620, CMU_PERIC1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIC1_IP1_USER, 0x624, CMU_PERIC1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER, 0x610, CMU_PERIC2),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIC2_IP0_USER, 0x614, CMU_PERIC2),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER, 0x620, CMU_PERIC2),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIC2_IP1_USER, 0x624, CMU_PERIC2),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC2_BUS_USER, 0x600, CMU_PERIC2),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIC2_BUS_USER, 0x604, CMU_PERIC2),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER, 0x600, CMU_PERIS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIS_BUS_USER, 0x604, CMU_PERIS),
|
|
SFR(PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D, 0x600, CMU_S2D),
|
|
SFR(PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D, 0x604, CMU_S2D),
|
|
SFR(PLL_CON0_MUX_CLKCMU_SSP_BUS_USER, 0x600, CMU_SSP),
|
|
SFR(PLL_CON1_MUX_CLKCMU_SSP_BUS_USER, 0x604, CMU_SSP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_SSP_SSPCORE_USER, 0x610, CMU_SSP),
|
|
SFR(PLL_CON1_MUX_CLKCMU_SSP_SSPCORE_USER, 0x614, CMU_SSP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_TAA_BUS_USER, 0x600, CMU_TAA),
|
|
SFR(PLL_CON1_MUX_CLKCMU_TAA_BUS_USER, 0x604, CMU_TAA),
|
|
SFR(PLL_CON0_MUX_CLKCMU_VPC_BUS_USER, 0x610, CMU_VPC),
|
|
SFR(PLL_CON1_MUX_CLKCMU_VPC_BUS_USER, 0x614, CMU_VPC),
|
|
SFR(PLL_CON0_MUX_CLKCMU_VPD_BUS_USER, 0x600, CMU_VPD),
|
|
SFR(PLL_CON1_MUX_CLKCMU_VPD_BUS_USER, 0x604, CMU_VPD),
|
|
SFR(PLL_CON0_MUX_CLKCMU_VTS_BUS_USER, 0x620, CMU_VTS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_VTS_BUS_USER, 0x624, CMU_VTS),
|
|
SFR(PLL_CON0_MUX_CLKAUD_VTS_DMIC0_USER, 0x600, CMU_VTS),
|
|
SFR(PLL_CON1_MUX_CLKAUD_VTS_DMIC0_USER, 0x604, CMU_VTS),
|
|
SFR(PLL_CON0_MUX_CLKAUD_VTS_DMIC1_USER, 0x610, CMU_VTS),
|
|
SFR(PLL_CON1_MUX_CLKAUD_VTS_DMIC1_USER, 0x614, CMU_VTS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER, 0x630, CMU_VTS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_VTS_DMIC_USER, 0x634, CMU_VTS),
|
|
SFR(PLL_CON0_MUX_CLK_RCO_VTS_USER, 0x640, CMU_VTS),
|
|
SFR(PLL_CON1_MUX_CLK_RCO_VTS_USER, 0x644, CMU_VTS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_YUVPP_BUS_USER, 0x600, CMU_YUVPP),
|
|
SFR(PLL_CON1_MUX_CLKCMU_YUVPP_BUS_USER, 0x604, CMU_YUVPP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_YUVPP_FRC_USER, 0x610, CMU_YUVPP),
|
|
SFR(PLL_CON1_MUX_CLKCMU_YUVPP_FRC_USER, 0x614, CMU_YUVPP),
|
|
SFR(CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU, 0x1028, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_STR, 0x1008, CMU_CPUCL0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_CORE_STR, 0x1008, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL2_CORE_STR, 0x1004, CMU_CPUCL2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_STR, 0x1008, CMU_DSU),
|
|
SFR(CLK_CON_MUX_MUX_CLK_G3D_SHADER_STR, 0x1004, CMU_G3D),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIS_GIC, 0x1000, CMU_PERIS),
|
|
SFR(CLK_CON_DIV_CLKCMU_VTS_BUS, 0x1804, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_ALIVE_BUS, 0x1808, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_CLKCMU_CMGP_BUS, 0x1800, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC, 0x1810, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_CLKCMU_CMGP_PERI, 0x181c, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_CLKCMU_CMGP_ADC, 0x1818, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART, 0x1820, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_CPU, 0x1824, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0x1800, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0x1814, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_DSIF, 0x1820, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0x182c, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0x1830, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0x1834, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0x1838, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0x1810, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_BUS, 0x1804, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0x1808, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_CNT, 0x180c, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0x183c, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0x1840, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_SCLK, 0x1828, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_DMIC1, 0x181c, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0x1844, CMU_AUD),
|
|
SFR(CLK_CON_DIV_CLKAUD_VTS_DMIC0, 0x1818, CMU_AUD),
|
|
SFR(CLK_CON_DIV_CLKAUD_HSI0_BUS, 0x1848, CMU_AUD),
|
|
SFR(CLK_CON_DIV_CLKAUD_HSI0_USB31DRD, 0x184c, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_PCMC, 0x1850, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_BUS0_BUSP, 0x1800, CMU_BUS0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_BUS1_BUSP, 0x1800, CMU_BUS1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_BUS2_BUSP, 0x1800, CMU_BUS2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_I2C0, 0x180c, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI1, 0x1820, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI0, 0x181c, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI2, 0x1824, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI3, 0x1828, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_I2C1, 0x1810, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_I2C2, 0x1814, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_I2C3, 0x1818, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_I3C, 0x1804, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_CLKCMU_ALIVE_BUS, 0x1800, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH, 0x1868, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0x18c4, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIS_BUS, 0x18d4, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_DPUF0_ALT, 0x18ec, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MFC0_MFC0, 0x18b0, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_VPD_BUS, 0x185c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0x18cc, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0x1844, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0x1838, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CORE_BUS, 0x1830, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_TAA_BUS, 0x189c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_ITP_BUS, 0x18a0, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_AUD_CPU, 0x1804, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_HPM, 0x186c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS, 0x1834, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK0, 0x1814, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK1, 0x1818, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK2, 0x181c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK3, 0x1820, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF, 0x18f0, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_NPU_BUS, 0x18bc, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MFC0_WFD, 0x18b4, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MIF_BUSP, 0x18b8, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC0_IP0, 0x18c8, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC1_IP0, 0x18d0, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_DPUF0, 0x18e8, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0x183c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_HSI0_BUS, 0x1870, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_YUVPP_BUS, 0x18e0, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK4, 0x1824, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CMU_BOOST, 0x182c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_BUS1_BUS, 0x180c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CSIS_CSIS, 0x1848, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MCFP0_BUS, 0x18dc, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MCSC_BUS, 0x18a4, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_DNS_BUS, 0x1858, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_NPUS_BUS, 0x1854, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_HSI1_BUS, 0x1880, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MCSC_GDC, 0x18a8, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU, 0x184c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_SSP_SSPCORE, 0x18d8, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CIS_CLK5, 0x1828, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU, 0x1864, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_M2M_BUS, 0x18f8, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT, 0x193c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_DPUB, 0x1938, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MFC1_MFC1, 0x1904, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_BUS1_SBIC, 0x1840, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_LME_BUS, 0x18f4, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MCFP1_MCFP1, 0x18fc, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_VPC_BUS, 0x1920, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_BUS0_BUS, 0x1810, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_BUS2_BUS, 0x1850, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0x1898, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0x188c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_AUD_BUS, 0x1808, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MCFP1_ORBMCH, 0x1900, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CSIS_PDP, 0x1878, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CP_SHARED0_CLK, 0x192c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CP_SHARED1_CLK, 0x1930, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CP_SHARED2_CLK, 0x1934, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CP_HISPEEDY_CLK, 0x1928, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC0_IP1, 0x1908, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC1_IP1, 0x190c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_SSP_BUS, 0x191c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_YUVPP_FRC, 0x1924, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_G3D_BUS, 0x1884, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC2_BUS, 0x1910, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC2_IP0, 0x1914, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC2_IP1, 0x1918, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_DPUF1, 0x1940, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_DPUF1_ALT, 0x1944, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CPUCL0_BUSP, 0x1874, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_DSU_SWITCH, 0x187c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD, 0x1860, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD, 0x194c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0x1800, CMU_CORE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_CORE, 0x1804, CMU_CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_BUS, 0x1804, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG, 0x1808, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_CORE, 0x1800, CMU_CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_HTU, 0x1808, CMU_CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL2_SHORTSTOP_CORE, 0x1808, CMU_CPUCL2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL2_HTU, 0x1804, CMU_CPUCL2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CSIS_BUSP, 0x1800, CMU_CSIS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DNS_BUSP, 0x1800, CMU_DNS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DPUB_BUSP, 0x1800, CMU_DPUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DPUF0_BUSP, 0x1800, CMU_DPUF0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DPUF1_BUSP, 0x1800, CMU_DPUF1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_CLUSTER, 0x1818, CMU_DSU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK, 0x1800, CMU_DSU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER_PCLK, 0x180c, CMU_DSU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER_PERIPHCLK, 0x1810, CMU_DSU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK, 0x1804, CMU_DSU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER_BCLK, 0x1808, CMU_DSU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0x1808, CMU_G3D),
|
|
SFR(CLK_CON_DIV_DIV_CLK_ITP_BUSP, 0x1800, CMU_ITP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_LME_BUSP, 0x1804, CMU_LME),
|
|
SFR(CLK_CON_DIV_DIV_CLK_M2M_BUSP, 0x1800, CMU_M2M),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MCFP0_BUSP, 0x1800, CMU_MCFP0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MCFP1_BUSP, 0x1800, CMU_MCFP1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MCSC_BUSP, 0x1800, CMU_MCSC),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MFC0_BUSP, 0x1800, CMU_MFC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MFC1_BUSP, 0x1800, CMU_MFC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_NPU_BUSP, 0x1800, CMU_NPU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_NPU01_BUSP, 0x1800, CMU_NPU01),
|
|
SFR(CLK_CON_DIV_DIV_CLK_NPU10_BUSP, 0x1800, CMU_NPU10),
|
|
SFR(CLK_CON_DIV_DIV_CLK_NPUS_BUSP, 0x1808, CMU_NPUS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI, 0x1804, CMU_PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI, 0x1808, CMU_PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI, 0x180c, CMU_PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI, 0x1810, CMU_PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI, 0x1814, CMU_PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI, 0x1818, CMU_PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0x1828, CMU_PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG, 0x1800, CMU_PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI, 0x181c, CMU_PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0x1820, CMU_PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI, 0x1824, CMU_PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT, 0x1800, CMU_PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0x182c, CMU_PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI, 0x1828, CMU_PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0x181c, CMU_PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0x1818, CMU_PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI, 0x1820, CMU_PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI, 0x1824, CMU_PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC2_USI08_USI, 0x180c, CMU_PERIC2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC2_USI_I2C, 0x181c, CMU_PERIC2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC2_USI06_USI, 0x1804, CMU_PERIC2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC2_USI07_USI, 0x1808, CMU_PERIC2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC2_USI09_USI, 0x1810, CMU_PERIC2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC2_USI10_USI, 0x1814, CMU_PERIC2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIS_BUSP, 0x1804, CMU_PERIS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_SSP_BUSP, 0x1800, CMU_SSP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_TAA_BUSP, 0x1800, CMU_TAA),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VPC_BUSP, 0x1800, CMU_VPC),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VPD_BUSP, 0x1800, CMU_VPD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF, 0x1810, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2, 0x1814, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_BUS, 0x1800, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD, 0x1804, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_DIV2, 0x1808, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF, 0x181c, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_DMIC_AHB, 0x180c, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE, 0x1818, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_YUVPP_BUSP, 0x1800, CMU_YUVPP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_CORE, 0x1800, CMU_CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_CORE, 0x1804, CMU_CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL2_CORE, 0x1800, CMU_CPUCL2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CSIS_CSIS, 0x1804, CMU_CSIS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CSIS_PDP, 0x1808, CMU_CSIS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DNS_BUS, 0x1804, CMU_DNS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DSU_CLUSTER, 0x1814, CMU_DSU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_G3D_SHADER, 0x1804, CMU_G3D),
|
|
SFR(CLK_CON_DIV_DIV_CLK_G3D_BUSD, 0x180c, CMU_G3D),
|
|
SFR(CLK_CON_DIV_DIV_CLK_ITP_BUS, 0x1804, CMU_ITP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_LME_BUS, 0x1800, CMU_LME),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MCFP0_BUS, 0x1804, CMU_MCFP0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MCFP1_MCFP1, 0x1804, CMU_MCFP1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MCFP1_ORBMCH, 0x1808, CMU_MCFP1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MCSC_BUS, 0x1808, CMU_MCSC),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MCSC_GDC, 0x180c, CMU_MCSC),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MFC0_MFC0, 0x1804, CMU_MFC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MFC1_MFC1, 0x1804, CMU_MFC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_NPU_BUS, 0x1804, CMU_NPU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_NPU01_BUS, 0x1804, CMU_NPU01),
|
|
SFR(CLK_CON_DIV_DIV_CLK_NPU10_BUS, 0x1804, CMU_NPU10),
|
|
SFR(CLK_CON_DIV_DIV_CLK_NPUS_BUS, 0x1804, CMU_NPUS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_TAA_BUS, 0x1808, CMU_TAA),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VPC_BUS, 0x1808, CMU_VPC),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VPD_BUS, 0x1804, CMU_VPD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_YUVPP_BUS, 0x1804, CMU_YUVPP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_YUVPP_FRC, 0x1808, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, 0x2050, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK, 0x2048, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK, 0x2008, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK, 0x207c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK, 0x209c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK, 0x2094, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, 0x2060, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_VTS_BUS, 0x2010, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, 0x2018, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK, 0x203c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK, 0x2040, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, 0x2058, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, 0x2070, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PEM_IPCLKPORT_I_CLK, 0x206c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK, 0x20a0, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK, 0x2000, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_IPCLKPORT_CLK, 0x2004, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, 0x2028, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GPIO_ALIVE_IPCLKPORT_PCLK, 0x2014, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK, 0x2020, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, 0x2090, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK, 0x2024, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, 0x2068, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_LP_VTS_IPCLKPORT_I_CLK, 0x205c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, 0x2054, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK, 0x201c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_C_CMGP_IPCLKPORT_I_CLK, 0x204c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS, 0x200c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK, 0x2098, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, 0x2078, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, 0x2074, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK, 0x2084, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_PCLK, 0x2034, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_SCLK, 0x2038, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_MODEM_IPCLKPORT_I_CLK, 0x20b0, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI, 0x2044, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CMGP_ADC, 0x2030, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLKCMU_VTS_DMIC, 0x202c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK, 0x20b8, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK, 0x20bc, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK, 0x20c0, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_VTS_IPCLKPORT_I_CLK, 0x20b4, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK, 0x20d4, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK, 0x20dc, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK, 0x20d8, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK, 0x20d0, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK, 0x2064, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK, 0x2088, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK, 0x20c4, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK, 0x2080, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_APM, 0x208c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_CPU, 0x20a4, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_SEMA, 0x20a8, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK, 0x20ac, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK, 0x20cc, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK, 0x20c8, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK, 0x2008, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUD_IPCLKPORT_I_CLK, 0x205c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK, 0x2068, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK, 0x206c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK, 0x20bc, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0, 0x2020, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1, 0x2024, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3, 0x202c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF, 0x201c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK, 0x2074, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK, 0x208c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK, 0x2090, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK, 0x200c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK, 0x2098, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK, 0x209c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK, 0x20a0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK, 0x20a4, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK, 0x2084, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2, 0x2028, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK, 0x2058, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK, 0x2070, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK, 0x2064, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK, 0x20c4, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1, 0x20b4, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK, 0x2088, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM, 0x204c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK, 0x2010, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM, 0x2054, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP, 0x2044, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK, 0x20c0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ, 0x2014, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT, 0x2018, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK, 0x2078, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM, 0x2060, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4, 0x2030, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5, 0x2034, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM, 0x2050, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK, 0x20a8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK, 0x20ac, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB, 0x203c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32, 0x2040, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_SCLK, 0x2048, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SCLK_IPCLKPORT_CLK, 0x2094, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLKAUD_VTS_DMIC1, 0x2004, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2, 0x20b8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6, 0x2038, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK, 0x20b0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GATE_CLKAUD_VTS_DMIC0, 0x2000, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK, 0x207c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK, 0x2080, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK, 0x2100, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK, 0x2104, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK, 0x20e0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_D_HSI0AUD_IPCLKPORT_I_CLK, 0x20ec, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDHSI0_IPCLKPORT_I_CLK, 0x20f8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDVTS_IPCLKPORT_I_CLK, 0x20fc, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK, 0x20d8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK, 0x20d4, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK, 0x2114, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK, 0x2118, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GATE_CLKAUD_HSI0_BUS, 0x20c8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GATE_CLKAUD_HSI0_USB31DRD, 0x20cc, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK, 0x2110, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK, 0x20d0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK, 0x2108, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK, 0x210c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_BAAW_D_AUDVTS_IPCLKPORT_I_PCLK, 0x20dc, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK, 0x20e8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK, 0x20e4, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BUS0_UID_BUS0_CMU_BUS0_IPCLKPORT_PCLK, 0x2000, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_SYSREG_BUS0_IPCLKPORT_PCLK, 0x2088, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_PCLK, 0x2090, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK, 0x2058, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK, 0x205c, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK, 0x2060, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK, 0x2064, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSD_IPCLKPORT_CLK, 0x2080, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSP_IPCLKPORT_CLK, 0x2084, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU10_IPCLKPORT_I_CLK, 0x2054, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_VPC_IPCLKPORT_I_CLK, 0x2044, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPUS_IPCLKPORT_I_CLK, 0x2078, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU01_IPCLKPORT_I_CLK, 0x2050, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERISGIC_IPCLKPORT_I_CLK, 0x2074, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU00_IPCLKPORT_I_CLK, 0x2048, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_ACLK, 0x208c, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_ACLK_BUS0, 0x209c, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_BUS0, 0x20a4, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_ACLK, 0x2094, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_PCLK, 0x2098, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D1_VPC_IPCLKPORT_I_CLK, 0x2014, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D2_VPC_IPCLKPORT_I_CLK, 0x201c, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D0_NPUS_IPCLKPORT_I_CLK, 0x2038, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK, 0x20a0, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_D_TZPC_BUS0_IPCLKPORT_PCLK, 0x2010, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_DBG_G_BUS0_IPCLKPORT_I_CLK, 0x207c, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D2_NPUS_IPCLKPORT_I_CLK, 0x2024, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D0_VPC_IPCLKPORT_I_CLK, 0x2018, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D1_NPUS_IPCLKPORT_I_CLK, 0x2020, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK, 0x2004, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_ACLK, 0x2008, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_PCLK, 0x200c, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_BAAW_P_VPC_IPCLKPORT_I_PCLK, 0x202c, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK, 0x2030, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC2_IPCLKPORT_I_CLK, 0x2034, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK, 0x2028, CMU_BUS0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK, 0x2000, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_DIT_IPCLKPORT_PCLKM, 0x200c, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_D_TZPC_BUS1_IPCLKPORT_PCLK, 0x2044, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_DIT_IPCLKPORT_ICLKL2A, 0x2040, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUB_IPCLKPORT_I_CLK, 0x2090, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_HSI0_IPCLKPORT_I_CLK, 0x209c, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK, 0x20b4, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_DBG_G_BUS1_IPCLKPORT_I_CLK, 0x20b8, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_ACLK, 0x20c4, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_PCLK, 0x20c8, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_PDMA_IPCLKPORT_ACLK, 0x20bc, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_ACLK, 0x20d4, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_PCLK, 0x20d8, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SPDMA_IPCLKPORT_ACLK, 0x20fc, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK, 0x2114, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK, 0x2118, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK, 0x211c, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1, 0x212c, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK, 0x2128, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_CLK, 0x2130, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_PCLK, 0x2134, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D0_BUS1_IPCLKPORT_ACLK, 0x2140, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF0_IPCLKPORT_I_CLK, 0x2050, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_HSI0_IPCLKPORT_I_CLK, 0x2060, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF0_IPCLKPORT_I_CLK, 0x2058, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK, 0x207c, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK, 0x2084, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM, 0x2028, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_PDMA_IPCLKPORT_PCLKM, 0x2010, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM, 0x2018, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK, 0x20e4, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK, 0x20e8, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_ACVPS_IPCLKPORT_PCLKM, 0x201c, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM, 0x2020, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_SBIC_IPCLKPORT_PCLKM, 0x2024, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_LITE_BUS1_IPCLKPORT_CLK, 0x2138, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_VTS_IPCLKPORT_I_PCLK, 0x2034, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_ACVPS_IPCLKPORT_CLK_S2, 0x2108, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2, 0x210c, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_SBIC_IPCLKPORT_CLK_S2, 0x2110, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF0_IPCLKPORT_I_CLK, 0x2094, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_PDMA_IPCLKPORT_CLK, 0x213c, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_SBIC_IPCLKPORT_CLK, 0x203c, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_SBIC_IPCLKPORT_I_CLK, 0x202c, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_SBIC_IPCLKPORT_I_CLK, 0x2030, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SBIC_IPCLKPORT_PCLKM, 0x2004, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SBIC_IPCLKPORT_I_CLK, 0x2048, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF1_IPCLKPORT_I_CLK, 0x2008, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF1_IPCLKPORT_I_CLK, 0x2014, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF1_IPCLKPORT_I_CLK, 0x2038, CMU_BUS1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BUS2_UID_BUS2_CMU_BUS2_IPCLKPORT_PCLK, 0x2000, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_ITP_IPCLKPORT_I_CLK, 0x2078, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_LME_IPCLKPORT_I_CLK, 0x205c, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_PCLK, 0x20b4, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_ACLK, 0x20b0, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MCFP0_IPCLKPORT_I_CLK, 0x2020, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_YUVPP_IPCLKPORT_I_CLK, 0x2068, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_DNS_IPCLKPORT_I_CLK, 0x201c, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCFP0_IPCLKPORT_I_CLK, 0x2080, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCSC_IPCLKPORT_I_CLK, 0x2084, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK, 0x20b8, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_BUS2, 0x20bc, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCFP0_IPCLKPORT_I_CLK, 0x2038, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_LME_IPCLKPORT_I_CLK, 0x207c, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCSC_IPCLKPORT_I_CLK, 0x203c, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_DBG_G_BUS2_IPCLKPORT_I_CLK, 0x20a0, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_TAA_IPCLKPORT_I_CLK, 0x2064, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_D_TZPC_BUS2_IPCLKPORT_PCLK, 0x2008, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_SYSREG_BUS2_IPCLKPORT_PCLK, 0x20ac, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_CSIS_IPCLKPORT_I_CLK, 0x206c, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_CSIS_IPCLKPORT_I_CLK, 0x2030, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_HSI1_IPCLKPORT_I_CLK, 0x2070, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D0_MCSC_IPCLKPORT_I_CLK, 0x2010, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_TAA_IPCLKPORT_I_CLK, 0x2098, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_HSI1_IPCLKPORT_I_CLK, 0x200c, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_CSIS_IPCLKPORT_I_CLK, 0x2018, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_YUVPP_IPCLKPORT_I_CLK, 0x209c, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSD_IPCLKPORT_CLK, 0x20a4, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSP_IPCLKPORT_CLK, 0x20a8, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_CSIS_IPCLKPORT_I_CLK, 0x2048, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_MCFP1_IPCLKPORT_I_CLK, 0x2060, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_DNS_IPCLKPORT_I_CLK, 0x2034, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCSC_IPCLKPORT_I_CLK, 0x2050, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC0_IPCLKPORT_I_CLK, 0x2028, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC1_IPCLKPORT_I_CLK, 0x202c, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC0_IPCLKPORT_I_CLK, 0x2040, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC1_IPCLKPORT_I_CLK, 0x2044, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCFP0_IPCLKPORT_I_CLK, 0x204c, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_CSIS_IPCLKPORT_I_CLK, 0x2054, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_MCFP0_IPCLKPORT_I_CLK, 0x2058, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_M2M_IPCLKPORT_I_CLK, 0x20d4, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC0_IPCLKPORT_I_CLK, 0x2088, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC1_IPCLKPORT_I_CLK, 0x208c, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_SSP_IPCLKPORT_I_CLK, 0x2094, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_SSP_IPCLKPORT_I_CLK, 0x2014, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_M2M_IPCLKPORT_I_CLK, 0x2024, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK, 0x2090, CMU_BUS2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK, 0x2004, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0, 0x200c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1, 0x2010, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK, 0x2020, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK, 0x2028, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK, 0x2030, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK, 0x2038, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK, 0x2040, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK, 0x2078, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK, 0x2080, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK, 0x2088, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK, 0x2090, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK, 0x2098, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C0_IPCLKPORT_CLK, 0x2050, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK, 0x2048, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK, 0x2060, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK, 0x2064, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK, 0x2068, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK, 0x206c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK, 0x2024, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK, 0x207c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK, 0x208c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK, 0x2094, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK, 0x2084, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK, 0x2074, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK, 0x201c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_C_CMGP_IPCLKPORT_I_CLK, 0x2044, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK, 0x202c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK, 0x203c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK, 0x2034, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C1_IPCLKPORT_CLK, 0x2054, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C2_IPCLKPORT_CLK, 0x2058, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C3_IPCLKPORT_CLK, 0x205c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK, 0x2070, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK, 0x2008, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_I_OSCCLK, 0x2000, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK, 0x204c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK, 0x2018, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK, 0x209c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK, 0x20a4, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK, 0x2014, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS, 0x2008, CMU_TOP),
|
|
SFR(CLK_CON_GAT_CLKCMU_MIF01_SWITCH, 0x2004, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0, 0x20bc, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 0x208c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DPUF0_BUS, 0x2064, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 0x2074, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS, 0x20dc, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_VPD_BUS, 0x2068, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 0x20cc, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 0x20d4, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 0x2048, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 0x203c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 0x2034, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_TAA_BUS, 0x20a8, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 0x20ac, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 0x200c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_HPM, 0x2078, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 0x2094, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 0x2038, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 0x201c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 0x2020, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 0x2028, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 0x2024, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_NPU_BUS, 0x20c8, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD, 0x20c0, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 0x20c4, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0, 0x20d0, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0, 0x20d8, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DPUF0, 0x2060, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 0x2040, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 0x207c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_YUVPP_BUS, 0x20e8, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 0x202c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 0x2014, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CSIS_CSIS, 0x204c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MCFP0_BUS, 0x20e4, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS, 0x20b0, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 0x205c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS, 0x2058, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC, 0x20b4, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU, 0x2050, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_SSP_SSPCORE, 0x20e0, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 0x2030, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_M2M_BUS, 0x210c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DPUB_BUS, 0x2098, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DPUB, 0x2090, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1, 0x2118, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_BUS1_SBIC, 0x2070, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_LME_BUS, 0x2108, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MCFP1_MCFP1, 0x214c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_VPC_BUS, 0x2134, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 0x2054, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 0x2080, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG_CPY, 0x20fc, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_CPY, 0x20f8, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CPY, 0x20f4, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_AUD_BUS, 0x2044, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MCFP1_ORBMCH, 0x2114, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CSIS_PDP, 0x2088, CMU_TOP),
|
|
SFR(CLK_CON_GAT_CP_UCPU_CLK, 0x2018, CMU_TOP),
|
|
SFR(CLK_CON_GAT_CP_LCPU_CLK, 0x2010, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CP_SHARED0_CLK, 0x2140, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CP_SHARED1_CLK, 0x2144, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CP_SHARED2_CLK, 0x2148, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CP_HISPEEDY_CLK, 0x213c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1, 0x211c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1, 0x2120, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_SSP_BUS, 0x2130, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_YUVPP_FRC, 0x2138, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_G3D_BUS, 0x20f0, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0, 0x2128, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC2_BUS, 0x2124, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1, 0x212c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_CLKCMU_MIF23_SWITCH, 0x2000, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DPUF1_BUS, 0x20b8, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DPUF1, 0x20a4, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP, 0x2084, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH, 0x20ec, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD, 0x2110, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD, 0x2100, CMU_TOP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK, 0x200c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, 0x2008, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK, 0x2164, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK, 0x206c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK, 0x2070, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK, 0x20ac, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK, 0x20b0, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE, 0x2170, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK, 0x2174, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK, 0x2148, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK, 0x2150, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK, 0x2054, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK, 0x2024, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK, 0x217c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK, 0x2068, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK, 0x2060, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK, 0x2034, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK, 0x203c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK, 0x2040, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK, 0x2044, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK, 0x216c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK, 0x2084, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK, 0x2088, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE, 0x2178, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE, 0x2180, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK, 0x205c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK, 0x2168, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK, 0x202c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_ACLK, 0x20b4, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_PCLK, 0x20b8, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_ACLK, 0x20bc, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_PCLK, 0x20c0, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_ACLK, 0x20c4, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_PCLK, 0x20c8, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_ACLK, 0x20cc, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_PCLK, 0x20d0, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_ACLK, 0x20d4, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_PCLK, 0x20d8, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_ACLK, 0x20dc, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_PCLK, 0x20e0, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK, 0x2074, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK, 0x2078, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK, 0x207c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK, 0x2080, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_PCLK, 0x2020, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK, 0x2048, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKM, 0x2018, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKS, 0x201c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK, 0x2004, CMU_CORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK, 0x2000, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK, 0x2108, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_ACLK, 0x2104, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK, 0x2110, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_ACLK, 0x210c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK, 0x2118, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_ACLK, 0x2114, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK, 0x2120, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_ACLK, 0x211c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D0_IPCLKPORT_CLK_S2, 0x2154, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D1_IPCLKPORT_CLK_S2, 0x2158, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D2_IPCLKPORT_CLK_S2, 0x215c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D3_IPCLKPORT_CLK_S2, 0x2160, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK, 0x2184, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_SYSMMU_G3D0_IPCLKPORT_PCLKM, 0x2014, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D0_IPCLKPORT_I_CLK, 0x2028, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D1_IPCLKPORT_I_CLK, 0x2030, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D2_IPCLKPORT_I_CLK, 0x2038, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D3_IPCLKPORT_I_CLK, 0x204c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK, 0x2094, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK, 0x2098, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D2_MODEM_IPCLKPORT_I_CLK, 0x2064, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_AUD_IPCLKPORT_I_CLK, 0x209c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_AUD_IPCLKPORT_I_CLK, 0x20a0, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK, 0x20a4, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_ACLK, 0x20f4, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_PCLK, 0x20f8, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_ACLK, 0x20fc, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_PCLK, 0x2100, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK, 0x2058, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_ACLK, 0x20e4, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_PCLK, 0x20e8, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_ACLK, 0x20ec, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_PCLK, 0x20f0, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK, 0x2124, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK, 0x2128, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK, 0x212c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK, 0x2130, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK, 0x208c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK, 0x2090, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK, 0x2050, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2, 0x2144, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK, 0x20a8, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF0_IPCLKPORT_ACLK, 0x2134, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF1_IPCLKPORT_ACLK, 0x2138, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF2_IPCLKPORT_ACLK, 0x213c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF3_IPCLKPORT_ACLK, 0x2140, CMU_CORE),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK, 0x214c, CMU_CORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, 0x2018, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK, 0x2004, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE, 0x202c, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK, 0x200c, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_CK_IN, 0x2030, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK, 0x2010, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE, 0x2034, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK, 0x2014, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK, 0x2020, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK, 0x2038, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HWACG_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK, 0x2024, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK, 0x2008, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DDD_CPUCL0_0_IPCLKPORT_CK_IN, 0x201c, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM, 0x2000, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_ETR_IPCLKPORT_I_CLK, 0x2074, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK, 0x2080, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_STM_IPCLKPORT_I_CLK, 0x2078, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK, 0x207c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK, 0x20c4, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK, 0x20c8, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK, 0x20bc, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK, 0x2030, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK, 0x206c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK, 0x2064, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK, 0x20d0, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK, 0x2040, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, 0x20c0, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_DBGCORE_IPCLKPORT_I_CLK, 0x2068, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BUSIF_HPM_CPUCL0_IPCLKPORT_PCLK, 0x2034, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK, 0x20cc, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_STM_IPCLKPORT_I_CLK, 0x2090, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK, 0x2070, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM, 0x202c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK, 0x2038, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG, 0x203c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK, 0x2084, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_ETR_IPCLKPORT_I_CLK, 0x208c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK, 0x2088, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK, 0x2004, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK, 0x20ac, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK, 0x20b0, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK, 0x20b8, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK, 0x2024, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK, 0x20a4, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C, 0x2008, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C, 0x200c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_2_IPCLKPORT_HPM_TARGETCLK_C, 0x2010, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK, 0x2044, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK, 0x2048, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK, 0x204c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK, 0x2050, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK, 0x2054, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK, 0x2058, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK, 0x205c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK, 0x2060, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK, 0x20a8, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK, 0x20b4, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, 0x2000, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK, 0x2008, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK, 0x2014, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE, 0x2040, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_CK_IN, 0x2044, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_CK_IN, 0x2048, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_CK_IN, 0x204c, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK, 0x2018, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK, 0x201c, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK, 0x2020, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE, 0x2050, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK, 0x2024, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK, 0x2034, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK, 0x2054, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_IPCLKPORT_CLK, 0x2060, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK, 0x205c, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK, 0x2038, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK, 0x203c, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK, 0x200c, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC0, 0x2028, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC1, 0x202c, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC2, 0x2030, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK, 0x2058, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK, 0x2018, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK, 0x2014, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE, 0x2034, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK, 0x2004, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK, 0x200c, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE, 0x202c, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK, 0x2010, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_CK_IN, 0x2030, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK, 0x2020, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK, 0x2038, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_IPCLKPORT_CLK, 0x2040, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_DIV_IPCLKPORT_CLK, 0x203c, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HWACG_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK, 0x2024, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK, 0x2008, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DDD_CPUCL0_1_IPCLKPORT_CK_IN, 0x201c, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0, 0x2130, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1, 0x2134, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2, 0x2138, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3, 0x213c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4, 0x2140, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5, 0x2144, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_CLK, 0x214c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_C2CLK, 0x2148, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK, 0x218c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK, 0x2164, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_ACLK, 0x21e0, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK, 0x2174, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK, 0x2190, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK, 0x2198, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK, 0x216c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK, 0x21a8, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK, 0x21a0, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK, 0x2168, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_PCLK, 0x21e4, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK, 0x2178, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK, 0x2194, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK, 0x219c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK, 0x2170, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK, 0x21ac, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK, 0x21a4, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_PDP_CORE_IPCLKPORT_PCLKM, 0x201c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK, 0x21cc, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D2_IPCLKPORT_CLK, 0x21d0, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK, 0x2114, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK, 0x2118, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK, 0x211c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK, 0x21e8, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK, 0x2000, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D0_CSIS_IPCLKPORT_I_CLK, 0x2068, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D1_CSIS_IPCLKPORT_I_CLK, 0x206c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OSCCLK_IPCLKPORT_CLK, 0x2004, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_CSIS_IPCLKPORT_CLK, 0x20d4, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK, 0x20d8, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK, 0x2034, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF0, 0x2010, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_DMA, 0x202c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK, 0x2084, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK, 0x208c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1, 0x20e4, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1, 0x20ec, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK, 0x2088, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK, 0x2090, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK, 0x20f4, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK, 0x20f8, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AXI_P_CSIS_IPCLKPORT_I_CLK, 0x2054, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK, 0x2300, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK, 0x2048, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK, 0x204c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK, 0x2050, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM, 0x2008, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK, 0x20fc, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK, 0x2100, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK, 0x20b8, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK, 0x20d0, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK, 0x20c8, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK, 0x20c0, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK, 0x2038, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK, 0x203c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK, 0x2040, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2, 0x20e8, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2, 0x20f0, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK, 0x20dc, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_PCLK, 0x2098, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK, 0x2074, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_OIS_MCU_TOP_IPCLKPORT_ACLKM, 0x200c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK, 0x20b0, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK, 0x20ac, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK, 0x20b4, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK, 0x20c4, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK, 0x20cc, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK, 0x2070, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_IPCLKPORT_CLK, 0x20e0, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_PDP_IPCLKPORT_CLK, 0x21b8, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK, 0x2120, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK, 0x2094, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK, 0x2080, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK, 0x207c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK, 0x2110, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK, 0x21d4, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_ACLK, 0x2150, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_ACLK, 0x2154, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_PCLK, 0x2158, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1, 0x21bc, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2, 0x21c0, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1, 0x21c4, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2, 0x21c8, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK, 0x215c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK, 0x2160, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D2_CSIS_IPCLKPORT_I_CLK, 0x2128, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D3_CSIS_IPCLKPORT_I_CLK, 0x212c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK, 0x21ec, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK, 0x2124, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK, 0x217c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK, 0x2180, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK, 0x21dc, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK, 0x21d8, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_STRP_IPCLKPORT_ACLKM, 0x2020, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK, 0x2024, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK, 0x2030, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK, 0x205c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK, 0x2064, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK, 0x209c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK, 0x20a4, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK, 0x20bc, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK, 0x2108, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK, 0x2028, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK, 0x2058, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK, 0x2060, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK, 0x2078, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK, 0x20a0, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK, 0x20a8, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK, 0x2104, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK, 0x210c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_MCB, 0x21f0, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_ACLK, 0x2184, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_PCLK, 0x2188, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_ACLK, 0x21b0, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_PCLK, 0x21b4, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF1, 0x2044, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK, 0x2000, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK, 0x2030, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D0_DNS_IPCLKPORT_ACLK, 0x20bc, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_TAADNS_IPCLKPORT_I_CLK, 0x2038, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S2, 0x20ac, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S1, 0x20a8, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AXI_P_ITPDNS_IPCLKPORT_I_CLK, 0x2048, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK, 0x202c, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK, 0x2018, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK, 0x2034, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK, 0x2028, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS0_IPCLKPORT_PCLKM, 0x2008, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK, 0x2010, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK, 0x2020, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK, 0x2024, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D1_DNS_IPCLKPORT_ACLK, 0x20c0, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF9_DNSITP_IPCLKPORT_I_CLK, 0x2074, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF8_DNSITP_IPCLKPORT_I_CLK, 0x2070, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK, 0x20b0, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D0_DNS_IPCLKPORT_I_CLK, 0x2080, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK, 0x208c, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK, 0x2088, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF5_DNSITP_IPCLKPORT_I_CLK, 0x2064, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF4_DNSITP_IPCLKPORT_I_CLK, 0x2060, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF6_DNSITP_IPCLKPORT_I_CLK, 0x2068, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF0_DNSITP_IPCLKPORT_I_CLK, 0x2050, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF1_DNSITP_IPCLKPORT_I_CLK, 0x2054, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF2_DNSITP_IPCLKPORT_I_CLK, 0x2058, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF3_DNSITP_IPCLKPORT_I_CLK, 0x205c, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF7_DNSITP_IPCLKPORT_I_CLK, 0x206c, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D1_DNS_IPCLKPORT_I_CLK, 0x2084, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_CTL_ITPDNS_IPCLKPORT_I_CLK, 0x201c, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK, 0x2094, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK, 0x2090, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S2, 0x20a4, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S1, 0x20a0, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_CTL_DNSITP_IPCLKPORT_I_CLK, 0x204c, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D0_DNS_IPCLKPORT_CLK, 0x20b4, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSD_IPCLKPORT_CLK, 0x2098, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSP_IPCLKPORT_CLK, 0x209c, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D1_DNS_IPCLKPORT_CLK, 0x20b8, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF0, 0x2014, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF1, 0x20f4, CMU_DNS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF2, 0x2040, CMU_DNS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK, 0x2000, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUB_UID_LHM_AXI_P_DPUB_IPCLKPORT_I_CLK, 0x2018, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK, 0x2010, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK, 0x2024, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON, 0x200c, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM, 0x2008, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSD_IPCLKPORT_CLK, 0x201c, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSP_IPCLKPORT_CLK, 0x2020, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF0_UID_DPUF0_CMU_DPUF0_IPCLKPORT_PCLK, 0x2000, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSREG_DPUF0_IPCLKPORT_PCLK, 0x2068, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S1, 0x2050, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_P_DPUF0_IPCLKPORT_I_CLK, 0x2020, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D1_DPUF0_IPCLKPORT_I_CLK, 0x2028, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM, 0x2008, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S1, 0x2058, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_ACLK, 0x2030, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_PCLK, 0x2034, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_ACLK, 0x2038, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_PCLK, 0x203c, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSD_IPCLKPORT_CLK, 0x2048, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSP_IPCLKPORT_CLK, 0x204c, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D0_DPUF0_IPCLKPORT_I_CLK, 0x2024, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DMA, 0x2010, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DPP, 0x2014, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_D_TZPC_DPUF0_IPCLKPORT_PCLK, 0x201c, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S2, 0x2054, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S2, 0x205c, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_C2SERV, 0x2064, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK, 0x200c, CMU_DPUF0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK, 0x2000, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM, 0x2008, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D1_DPUF1_IPCLKPORT_I_CLK, 0x202c, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DMA, 0x2010, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPP, 0x2014, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK, 0x2034, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK, 0x2030, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK, 0x203c, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK, 0x2038, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK, 0x2018, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D0_DPUF1_IPCLKPORT_I_CLK, 0x2028, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHM_AXI_P_DPUF1_IPCLKPORT_I_CLK, 0x2020, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2, 0x204c, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1, 0x2048, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2, 0x2054, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1, 0x2050, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK, 0x2058, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSD_IPCLKPORT_CLK, 0x2040, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSP_IPCLKPORT_CLK, 0x2044, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_C2SERV, 0x200c, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK, 0x2024, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK, 0x2010, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK, 0x2014, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK, 0x2084, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK, 0x2090, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK, 0x201c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK, 0x2098, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK, 0x2094, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK, 0x2088, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHM_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK, 0x2044, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK, 0x2050, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK, 0x2018, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK, 0x2054, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK, 0x2058, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK, 0x205c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK, 0x2060, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK, 0x2064, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK, 0x2068, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK, 0x206c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK, 0x2070, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK, 0x200c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE, 0x2040, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK, 0x2008, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK, 0x2020, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK, 0x209c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK, 0x2024, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK, 0x2028, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK, 0x202c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK, 0x2030, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK, 0x2074, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK, 0x2078, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK, 0x207c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK, 0x2080, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_BCLK_IPCLKPORT_CLK, 0x208c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D0_CLUSTER0_IPCLKPORT_ACLK, 0x2038, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D1_CLUSTER0_IPCLKPORT_ACLK, 0x203c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK, 0x2048, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK, 0x204c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK, 0x2034, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK, 0x2028, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C, 0x2014, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, 0x204c, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK, 0x2048, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK, 0x201c, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, 0x200c, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK, 0x203c, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK, 0x2050, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK, 0x2038, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK, 0x2030, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK, 0x202c, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK, 0x2044, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK, 0x2024, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CLK, 0x2004, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK, 0x2000, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK, 0x2078, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE, 0x2058, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_CK_IN, 0x2064, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK, 0x2008, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP, 0x2010, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS, 0x2018, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_PCLK, 0x2060, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_CLK_CORE, 0x205c, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_G3D_IPCLKPORT_CK_IN, 0x206c, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_PCLK, 0x2068, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK, 0x2070, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK, 0x2074, CMU_G3D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL, 0x2038, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40, 0x2034, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK, 0x2004, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK, 0x2018, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK, 0x2014, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK, 0x2020, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK, 0x2044, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK, 0x2008, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK, 0x200c, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK, 0x2010, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK, 0x201c, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2, 0x2024, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK, 0x2028, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL, 0x202c, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK, 0x203c, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK, 0x2040, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY, 0x2030, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK, 0x2000, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK, 0x205c, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_D_AUDHSI0_IPCLKPORT_I_CLK, 0x2048, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AUD_IPCLKPORT_I_CLK, 0x204c, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK, 0x2050, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK, 0x2054, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK, 0x2058, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2, 0x206c, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK, 0x2010, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK, 0x2028, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK, 0x2070, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK, 0x200c, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK, 0x2018, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK, 0x2014, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK, 0x2090, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK, 0x2094, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK, 0x205c, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK, 0x2060, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN, 0x2000, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK, 0x2038, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK, 0x2024, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 0x2030, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL, 0x2034, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK, 0x2064, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK, 0x208c, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK, 0x202c, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK, 0x2054, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK, 0x2008, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 0x2048, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, 0x2004, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, 0x203c, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, 0x2040, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, 0x2044, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK, 0x204c, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK, 0x2058, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, 0x2050, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK, 0x201c, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK, 0x2084, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, 0x2098, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, 0x2088, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK, 0x2020, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN, 0x2068, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_MMC_CARD_IPCLKPORT_CLK, 0x2078, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_UFS_EMBD_IPCLKPORT_CLK, 0x2080, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK, 0x2074, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK, 0x2000, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK, 0x2070, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK, 0x200c, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_CTL_ITPDNS_IPCLKPORT_I_CLK, 0x2048, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK, 0x2010, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK, 0x205c, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_CTL_DNSITP_IPCLKPORT_I_CLK, 0x2014, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF4_DNSITP_IPCLKPORT_I_CLK, 0x2028, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF3_DNSITP_IPCLKPORT_I_CLK, 0x2024, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF5_DNSITP_IPCLKPORT_I_CLK, 0x202c, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF6_DNSITP_IPCLKPORT_I_CLK, 0x2030, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF7_DNSITP_IPCLKPORT_I_CLK, 0x2034, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF8_DNSITP_IPCLKPORT_I_CLK, 0x2038, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF9_DNSITP_IPCLKPORT_I_CLK, 0x203c, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF2_DNSITP_IPCLKPORT_I_CLK, 0x2020, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AXI_P_ITP_IPCLKPORT_I_CLK, 0x2044, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF0_DNSITP_IPCLKPORT_I_CLK, 0x2018, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF1_DNSITP_IPCLKPORT_I_CLK, 0x201c, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK, 0x2050, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK, 0x2054, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK, 0x2058, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP0_IPCLKPORT_PCLKM, 0x2008, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK, 0x204c, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AXI_P_ITPDNS_IPCLKPORT_I_CLK, 0x2064, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK, 0x2040, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSD_IPCLKPORT_CLK, 0x2068, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSP_IPCLKPORT_CLK, 0x206c, CMU_ITP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK, 0x2060, CMU_ITP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK, 0x2004, CMU_LME),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2, 0x2040, CMU_LME),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1, 0x203c, CMU_LME),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK, 0x2044, CMU_LME),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK, 0x200c, CMU_LME),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_C2CLK, 0x2024, CMU_LME),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_CLK, 0x2028, CMU_LME),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_PCLK, 0x2030, CMU_LME),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_ACLK, 0x202c, CMU_LME),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_LME_UID_LHS_AXI_D_LME_IPCLKPORT_I_CLK, 0x2020, CMU_LME),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM, 0x2008, CMU_LME),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_LME_UID_VGEN_LITE_LME_IPCLKPORT_CLK, 0x2048, CMU_LME),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_LME_UID_LHM_AXI_P_LME_IPCLKPORT_I_CLK, 0x2014, CMU_LME),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSD_IPCLKPORT_CLK, 0x2034, CMU_LME),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSP_IPCLKPORT_CLK, 0x2038, CMU_LME),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK, 0x204c, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK, 0x2000, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_LHS_ACEL_D_M2M_IPCLKPORT_I_CLK, 0x2024, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM, 0x2008, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2, 0x206c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1, 0x2068, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK, 0x2078, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK, 0x2044, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK, 0x2040, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK, 0x200c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK, 0x202c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK, 0x2054, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK, 0x2050, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK, 0x205c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK, 0x2058, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_LHM_AXI_P_M2M_IPCLKPORT_I_CLK, 0x2020, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_PCLK, 0x203c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_ACLK, 0x2038, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK, 0x2074, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK, 0x2034, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK, 0x2030, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK, 0x2070, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_IPCLKPORT_CLK, 0x2060, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK, 0x2064, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_ASTC_IPCLKPORT_ACLK, 0x2004, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK, 0x2010, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK, 0x2018, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK, 0x2014, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK, 0x2048, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK, 0x204c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF, 0x2088, CMU_M2M),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1, 0x20a8, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCFP0_UID_MCFP0_CMU_MCFP0_IPCLKPORT_PCLK, 0x2000, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSD_IPCLKPORT_CLK, 0x2028, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSP_IPCLKPORT_CLK, 0x202c, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D0_MCFP0_IPCLKPORT_I_CLK, 0x201c, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AXI_P_MCFP0_IPCLKPORT_I_CLK, 0x2010, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK, 0x200c, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK, 0x2018, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK, 0x2014, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSREG_MCFP0_IPCLKPORT_PCLK, 0x2038, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_D_TZPC_MCFP0_IPCLKPORT_PCLK, 0x2008, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_VGEN_LITE_MCFP0_IPCLKPORT_CLK, 0x2040, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_PCLK, 0x2024, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_ACLK, 0x2020, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S1, 0x2030, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_APB_ASYNC_MCFP0_0_IPCLKPORT_PCLKM, 0x2004, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S2, 0x2034, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_MCFP0_IPCLKPORT_ACLK, 0x203c, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D1_MCFP0_IPCLKPORT_I_CLK, 0x2068, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK, 0x2058, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_PCLK, 0x2080, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_ACLK, 0x207c, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S1, 0x20b4, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S2, 0x20b8, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_OSCCLK_IPCLKPORT_CLK, 0x204c, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK, 0x2078, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK, 0x205c, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK, 0x2060, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_ACLK, 0x2094, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_ACLK, 0x209c, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_ACLK, 0x20a4, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_ACLK, 0x20ac, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_PCLK, 0x2098, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_PCLK, 0x20a0, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_PCLK, 0x20a8, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_PCLK, 0x20b0, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_XIU_D0_MCFP0_IPCLKPORT_ACLK, 0x20cc, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_ACLK, 0x2084, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_PCLK, 0x2088, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_ACLK, 0x208c, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_PCLK, 0x2090, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S1, 0x20bc, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S2, 0x20c0, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S1, 0x20c4, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S2, 0x20c8, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D2_MCFP0_IPCLKPORT_I_CLK, 0x206c, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D3_MCFP0_IPCLKPORT_I_CLK, 0x2070, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK, 0x2054, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK, 0x2064, CMU_MCFP0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCFP1_UID_MCFP1_CMU_MCFP1_IPCLKPORT_PCLK, 0x2008, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_MCFP1_0_IPCLKPORT_PCLKM, 0x200c, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_PCLK, 0x207c, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_ACLK, 0x2078, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D0_MCFP1_IPCLKPORT_CLK, 0x2100, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_PCLK, 0x2064, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_ACLK, 0x2060, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_PCLK, 0x206c, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_ACLK, 0x2068, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK, 0x2020, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK, 0x202c, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_MCFP1_IPCLKPORT_ACLK, 0x2054, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AXI_D_MCFP1_IPCLKPORT_I_CLK, 0x2050, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK, 0x2048, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK, 0x2024, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK, 0x2044, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_C2CLK, 0x205c, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_ACLK, 0x2058, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSREG_MCFP1_IPCLKPORT_PCLK, 0x209c, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK, 0x204c, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S2, 0x2098, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S1, 0x2094, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_D_TZPC_MCFP1_IPCLKPORT_PCLK, 0x2014, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_XIU_D_MCFP1_IPCLKPORT_ACLK, 0x20a4, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_PCLK, 0x2074, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_ACLK, 0x2070, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK, 0x2034, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK, 0x201c, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK, 0x2038, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_ORBMCH0_IPCLKPORT_PCLKM, 0x2010, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_BUSP_IPCLKPORT_CLK, 0x2088, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_MCFP1_IPCLKPORT_CLK, 0x208c, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_ORBMCH_IPCLKPORT_CLK, 0x2090, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK, 0x203c, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK, 0x2040, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_ACLK, 0x2080, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_PCLK, 0x2084, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK, 0x2018, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK, 0x2030, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_ACLK, 0x20f0, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_C2CLK, 0x20d0, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_ACLK, 0x20b8, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_ACLK, 0x20c0, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_PCLK, 0x20c4, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_PCLK, 0x20bc, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D1_MCFP1_IPCLKPORT_CLK, 0x2104, CMU_MCFP1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK, 0x2000, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK, 0x20b0, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK, 0x20b4, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_P_MCSC_IPCLKPORT_I_CLK, 0x2048, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK, 0x20d0, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK, 0x2064, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK, 0x2084, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK, 0x201c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK, 0x20d4, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_0_IPCLKPORT_PCLKM, 0x2008, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK, 0x2074, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK, 0x20b8, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK, 0x2024, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM, 0x2004, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK, 0x2068, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_M, 0x2020, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK, 0x20e8, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1, 0x2100, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2, 0x2104, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1, 0x20f0, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2, 0x20f4, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D2_MCSC_IPCLKPORT_I_CLK, 0x20dc, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_ACEL_D0_MCSC_IPCLKPORT_I_CLK, 0x206c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK, 0x2094, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_HPM_MCSC_IPCLKPORT_HPM_TARGETCLK_C, 0x202c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_PCLK, 0x204c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_PCLK, 0x2054, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CH_CLK, 0x2014, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_HPM_MCSC_IPCLKPORT_PCLK, 0x2058, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_CLK_CORE, 0x2044, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_CK_IN, 0x2050, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK, 0x2114, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_OSCCLK_IPCLKPORT_CLK, 0x2030, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_HTU_IPCLKPORT_CLK, 0x20ec, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK, 0x2108, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D0_MCSC_IPCLKPORT_ACLK, 0x210c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK, 0x20e0, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK, 0x20e4, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CLK, 0x2018, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_DDD_MCSC_IPCLKPORT_CK_IN, 0x2028, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK, 0x20a8, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK, 0x2110, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D1_MCSC_IPCLKPORT_I_CLK, 0x20d8, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1, 0x20f8, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2, 0x20fc, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK, 0x2070, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_S, 0x205c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK, 0x2060, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK, 0x2078, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK, 0x2000, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM, 0x2004, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK, 0x206c, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D0_MFC0_IPCLKPORT_I_CLK, 0x2014, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D1_MFC0_IPCLKPORT_I_CLK, 0x2018, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AXI_P_MFC0_IPCLKPORT_I_CLK, 0x2010, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1, 0x205c, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1, 0x2064, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK, 0x2028, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK, 0x202c, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK, 0x2030, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK, 0x2034, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_IPCLKPORT_CLK, 0x2048, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSP_IPCLKPORT_CLK, 0x2058, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_AXI_WFD_IPCLKPORT_ACLKM, 0x2008, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK, 0x203c, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_IPCLKPORT_CLK, 0x2050, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK, 0x2078, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_VGEN_MFC0_IPCLKPORT_CLK, 0x2070, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK, 0x2024, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK, 0x2074, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_IPCLKPORT_CLK, 0x204c, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK, 0x2044, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK, 0x2040, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_IPCLKPORT_CLK, 0x2054, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK, 0x2038, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI, 0x201c, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI, 0x2020, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK, 0x200c, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2, 0x2060, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2, 0x2068, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM, 0x2084, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK, 0x2088, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK, 0x208c, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK, 0x2090, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK, 0x2094, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK, 0x209c, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK, 0x20a0, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK, 0x20a4, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK, 0x20a8, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS, 0x2080, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK, 0x20b4, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK, 0x20b8, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK, 0x20bc, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK, 0x20c0, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK, 0x20c8, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK, 0x20cc, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK, 0x20d0, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK, 0x20d4, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK, 0x20b0, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK, 0x2004, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM, 0x200c, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK, 0x2040, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_IPCLKPORT_CLK, 0x2078, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK, 0x2050, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK, 0x204c, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK, 0x2048, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK, 0x2044, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D0_MFC1_IPCLKPORT_I_CLK, 0x2038, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK, 0x2098, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AXI_P_MFC1_IPCLKPORT_I_CLK, 0x2024, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2, 0x2088, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1, 0x2084, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2, 0x2090, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1, 0x208c, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK, 0x2094, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK, 0x2010, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D1_MFC1_IPCLKPORT_I_CLK, 0x203c, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSP_IPCLKPORT_CLK, 0x207c, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_IPCLKPORT_CLK, 0x2074, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM, 0x2008, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK, 0x2014, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK, 0x2018, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK, 0x201c, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK, 0x2020, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK, 0x2028, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK, 0x202c, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK, 0x2030, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK, 0x2034, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK, 0x2054, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK, 0x2058, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK, 0x205c, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK, 0x2060, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK, 0x2064, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK, 0x2068, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK, 0x206c, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK, 0x2070, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, 0x2004, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK, 0x2024, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, 0x2044, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK, 0x2034, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK, 0x201c, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK, 0x2020, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK, 0x2028, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK, 0x2040, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK, 0x2014, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK, 0x2038, CMU_MIF),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK, 0x2030, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK, 0x2008, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK, 0x2010, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NPU_UID_NPU_CMU_NPU_IPCLKPORT_PCLK, 0x2000, CMU_NPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_PCLK, 0x2010, CMU_NPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_CLK, 0x200c, CMU_NPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK, 0x2018, CMU_NPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK, 0x2028, CMU_NPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK, 0x2020, CMU_NPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK, 0x2014, CMU_NPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU_UID_D_TZPC_NPU_IPCLKPORT_PCLK, 0x2008, CMU_NPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK, 0x2024, CMU_NPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU_UID_SYSREG_NPU_IPCLKPORT_PCLK, 0x2034, CMU_NPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK, 0x202c, CMU_NPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK, 0x2030, CMU_NPU),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK, 0x201c, CMU_NPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NPU01_UID_NPU_CMU_NPU_IPCLKPORT_PCLK, 0x2000, CMU_NPU01),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_PCLK, 0x2010, CMU_NPU01),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_CLK, 0x200c, CMU_NPU01),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK, 0x2018, CMU_NPU01),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK, 0x2028, CMU_NPU01),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK, 0x2020, CMU_NPU01),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK, 0x2014, CMU_NPU01),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU01_UID_D_TZPC_NPU_IPCLKPORT_PCLK, 0x2008, CMU_NPU01),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK, 0x2024, CMU_NPU01),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU01_UID_SYSREG_NPU_IPCLKPORT_PCLK, 0x2034, CMU_NPU01),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK, 0x202c, CMU_NPU01),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK, 0x2030, CMU_NPU01),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK, 0x201c, CMU_NPU01),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NPU10_UID_NPU_CMU_NPU_IPCLKPORT_PCLK, 0x2000, CMU_NPU10),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_PCLK, 0x2010, CMU_NPU10),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_CLK, 0x200c, CMU_NPU10),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK, 0x2018, CMU_NPU10),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK, 0x2028, CMU_NPU10),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK, 0x2020, CMU_NPU10),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK, 0x2014, CMU_NPU10),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU10_UID_D_TZPC_NPU_IPCLKPORT_PCLK, 0x2008, CMU_NPU10),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK, 0x2024, CMU_NPU10),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU10_UID_SYSREG_NPU_IPCLKPORT_PCLK, 0x2034, CMU_NPU10),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK, 0x202c, CMU_NPU10),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK, 0x2030, CMU_NPU10),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK, 0x201c, CMU_NPU10),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK, 0x2014, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2, 0x210c, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1, 0x2108, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S2, 0x211c, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S1, 0x2118, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2, 0x2114, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1, 0x2110, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU10_IPCLKPORT_I_CLK, 0x20ac, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPUS_IPCLKPORT_I_CLK, 0x20b4, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU10_IPCLKPORT_I_CLK, 0x20d8, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU01_IPCLKPORT_I_CLK, 0x20a8, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK, 0x2124, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU00_IPCLKPORT_I_CLK, 0x20a4, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_NPUS_IPCLKPORT_I_CLK, 0x2094, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU01_IPCLKPORT_I_CLK, 0x2074, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU00_IPCLKPORT_I_CLK, 0x2070, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU00_IPCLKPORT_I_CLK, 0x20d0, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPUS_IPCLKPORT_I_CLK, 0x20c8, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU01_IPCLKPORT_I_CLK, 0x20d4, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU10_IPCLKPORT_I_CLK, 0x2088, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU00_IPCLKPORT_I_CLK, 0x20b8, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU01_IPCLKPORT_I_CLK, 0x20bc, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU10_IPCLKPORT_I_CLK, 0x2078, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK, 0x2120, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK, 0x2038, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK, 0x2060, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK, 0x2044, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D2_NPUS_IPCLKPORT_I_CLK, 0x20cc, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_PCLK, 0x20f8, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_ACLK, 0x20f4, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK, 0x20f0, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK, 0x20ec, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK, 0x20e8, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK, 0x20e4, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU00_IPCLKPORT_I_CLK, 0x2080, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU01_IPCLKPORT_I_CLK, 0x2084, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU10_IPCLKPORT_I_CLK, 0x20c0, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK, 0x20fc, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK, 0x2100, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_P0_NPUS_IPCLKPORT_PCLKM, 0x2020, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_P_INT_NPUS_IPCLKPORT_I_CLK, 0x20e0, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_INT_NPUS_IPCLKPORT_I_CLK, 0x2090, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK, 0x2018, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NPUS_UID_HPM_NPUS_IPCLKPORT_HPM_TARGETCLK_C, 0x2010, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CH_CLK, 0x2004, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_HPM_NPUS_IPCLKPORT_PCLK, 0x2034, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_PCLK, 0x2028, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_CLK_CORE, 0x2024, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_PCLK, 0x2030, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_CK_IN, 0x202c, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK, 0x2104, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK, 0x205c, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK, 0x2040, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK, 0x203c, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CLK, 0x2008, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NPUS_UID_DDD_NPUS_IPCLKPORT_CK_IN, 0x200c, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM, 0x201c, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK, 0x2048, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK, 0x204c, CMU_NPUS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, 0x2010, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, 0x20e4, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, 0x2004, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, 0x20b4, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, 0x2008, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK, 0x20bc, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK, 0x20e0, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK, 0x20c0, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK, 0x20c4, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK, 0x20c8, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK, 0x20cc, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK, 0x20d0, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK, 0x20b8, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, 0x2014, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK, 0x20d4, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, 0x20d8, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, 0x200c, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK, 0x20dc, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, 0x2030, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, 0x2060, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, 0x2064, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, 0x2068, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, 0x206c, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, 0x2070, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, 0x2074, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, 0x2048, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, 0x204c, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, 0x2050, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, 0x2054, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, 0x2058, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, 0x205c, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, 0x2034, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, 0x2038, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, 0x203c, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, 0x2040, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, 0x2044, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, 0x2018, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, 0x201c, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, 0x2020, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, 0x2024, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, 0x2028, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, 0x202c, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, 0x2094, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3, 0x209c, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4, 0x20a0, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5, 0x20a4, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6, 0x20a8, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7, 0x20ac, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8, 0x20b0, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15, 0x2098, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, 0x2078, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3, 0x207c, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4, 0x2080, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5, 0x2084, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6, 0x2088, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7, 0x208c, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8, 0x2090, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, 0x2018, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, 0x2108, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, 0x2004, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, 0x20dc, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK, 0x2104, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK, 0x2008, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, 0x2020, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, 0x20f8, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, 0x2014, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK, 0x20fc, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK, 0x2100, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, 0x2058, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, 0x203c, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4, 0x20c4, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5, 0x20c8, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6, 0x20cc, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7, 0x20d0, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9, 0x20d8, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10, 0x20a4, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4, 0x2084, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5, 0x2088, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6, 0x208c, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7, 0x2090, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9, 0x2098, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10, 0x2064, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, 0x20e0, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK, 0x201c, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK, 0x211c, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12, 0x206c, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12, 0x20ac, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13, 0x20b0, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14, 0x20b4, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15, 0x20b8, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13, 0x2070, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14, 0x2074, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15, 0x2078, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK, 0x210c, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK, 0x2110, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK, 0x2118, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK, 0x2114, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, 0x2000, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK, 0x200c, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_11, 0x2030, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_10, 0x202c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_13, 0x2038, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_12, 0x2034, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_15, 0x2028, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_14, 0x2024, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_15, 0x2040, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_13, 0x2020, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_14, 0x203c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_12, 0x201c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_11, 0x2018, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_10, 0x2014, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK, 0x2058, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK, 0x2008, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_LHM_AXI_P_PERIC2_IPCLKPORT_I_CLK, 0x2010, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK, 0x200c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_BUSP_IPCLKPORT_CLK, 0x2044, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_OSCCLK_IPCLKPORT_CLK, 0x2004, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI06_USI_IPCLKPORT_CLK, 0x2048, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI07_USI_IPCLKPORT_CLK, 0x204c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI08_USI_IPCLKPORT_CLK, 0x2050, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI_I2C_IPCLKPORT_CLK, 0x2054, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK, 0x2000, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI09_USI_IPCLKPORT_CLK, 0x2084, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI10_USI_IPCLKPORT_CLK, 0x2088, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_0, 0x2064, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_0, 0x208c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_1, 0x206c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_1, 0x2094, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_2, 0x2074, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_2, 0x205c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_3, 0x207c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_3, 0x2060, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK, 0x203c, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK, 0x204c, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK, 0x2048, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK, 0x200c, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK, 0x2034, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK, 0x2010, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK, 0x2038, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, 0x2028, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK, 0x201c, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK, 0x2020, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK, 0x2024, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK, 0x2030, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK, 0x2018, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK, 0x2040, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK, 0x2044, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, 0x2000, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 0x2008, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERISGIC_IPCLKPORT_I_CLK, 0x2058, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_BC_EMUL_IPCLKPORT_PCLK, 0x2014, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK, 0x202c, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHS_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK, 0x205c, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_PCLK, 0x2068, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, 0x2004, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK, 0x2008, CMU_S2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK, 0x2018, CMU_S2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK, 0x2010, CMU_S2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_S2D_UID_LHM_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, 0x2014, CMU_S2D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK, 0x2004, CMU_S2D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK, 0x2000, CMU_S2D),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_SYSMMU_RTIC_IPCLKPORT_PCLKM, 0x2010, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSMMU_RTIC_IPCLKPORT_CLK_S2, 0x2070, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_ACLK, 0x205c, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSD_IPCLKPORT_CLK, 0x2050, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK, 0x2080, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_LHS_ACEL_D_SSP_IPCLKPORT_I_CLK, 0x2028, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_PUF_IPCLKPORT_PCLKM, 0x200c, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_PUF_IPCLKPORT_I_CLK, 0x2034, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK, 0x2064, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSP_IPCLKPORT_CLK, 0x2054, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_P_SSP_IPCLKPORT_I_CLK, 0x2024, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK, 0x201c, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK, 0x2014, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_PCLK, 0x2060, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK, 0x2068, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_D_SSPCORE_IPCLKPORT_I_CLK, 0x2020, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK, 0x202c, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK, 0x2030, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_OSCCLK_IPCLKPORT_CLK, 0x2000, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_SSPCORE_IPCLKPORT_CLK, 0x2058, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_USS_SSPCORE_IPCLKPORT_SS_SSPCORE_IPCLKPORT_ACLK, 0x2078, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_ACLK, 0x2038, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_PCLK, 0x203c, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_ACLK, 0x2040, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_PCLK, 0x2044, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK, 0x2048, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK, 0x204c, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_VGEN_LITE_RTIC_IPCLKPORT_CLK, 0x207c, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSREG_SSPCTRL_IPCLKPORT_PCLK, 0x2074, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_SWEEPER_D_SSP_IPCLKPORT_ACLK, 0x206c, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_BPS_AXI_P_SSP_IPCLKPORT_I_CLK, 0x2018, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_SSP_UID_ADM_DAP_SSS_IPCLKPORT_DAPCLKM, 0x2008, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK, 0x2004, CMU_SSP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AXI_D_TAA_IPCLKPORT_I_CLK, 0x2044, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AXI_P_TAA_IPCLKPORT_I_CLK, 0x201c, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK, 0x206c, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK, 0x2050, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK, 0x2054, CMU_TAA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK, 0x2000, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_OTF_TAADNS_IPCLKPORT_I_CLK, 0x2020, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK, 0x2008, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK, 0x200c, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK, 0x2058, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK, 0x205c, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM, 0x2004, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK, 0x2038, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK, 0x203c, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK, 0x2040, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK, 0x2048, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S1, 0x2064, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA0_IPCLKPORT_CLK, 0x2070, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK, 0x204c, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK, 0x2010, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK, 0x2014, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK, 0x2028, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK, 0x202c, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK, 0x2030, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S2, 0x2068, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT, 0x2060, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS, 0x20c0, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK, 0x20a0, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK, 0x20ac, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK, 0x20b8, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK, 0x20a8, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK, 0x20b4, CMU_TAA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_TAA_UID_HPM_TAA_IPCLKPORT_HPM_TARGETCLK_C, 0x2080, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_HPM_TAA_IPCLKPORT_PCLK, 0x2094, CMU_TAA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CH_CLK, 0x2074, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_PCLK, 0x2088, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_PCLK, 0x2090, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_CLK_CORE, 0x2084, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_HTU_IPCLKPORT_CLK, 0x20bc, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA1_IPCLKPORT_CLK, 0x20c4, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_CK_IN, 0x208c, CMU_TAA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CLK, 0x2078, CMU_TAA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_TAA_UID_DDD_TAA_IPCLKPORT_CK_IN, 0x207c, CMU_TAA),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK, 0x20b0, CMU_TAA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VPC_UID_VPC_CMU_VPC_IPCLKPORT_PCLK, 0x2000, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_D_TZPC_VPC_IPCLKPORT_PCLK, 0x2010, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSD_IPCLKPORT_CLK, 0x20b0, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSP_IPCLKPORT_CLK, 0x20b8, CMU_VPC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VPC_UID_RSTNSYNC_CLK_VPC_OSCCLK_IPCLKPORT_CLK, 0x2004, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD0_IPCLKPORT_I_CLK, 0x208c, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD1_IPCLKPORT_I_CLK, 0x2090, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_SFR_IPCLKPORT_I_CLK, 0x2078, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_IPCLKPORT_I_CLK, 0x2050, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_SFR_IPCLKPORT_I_CLK, 0x203c, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_SFR_IPCLKPORT_I_CLK, 0x2044, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_PCLK, 0x209c, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_PCLK, 0x20a4, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_PCLK, 0x20ac, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_CLK, 0x2014, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSREG_VPC_IPCLKPORT_PCLK, 0x20d4, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_SFR_IPCLKPORT_I_CLK, 0x2080, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPC_200_IPCLKPORT_I_CLK, 0x2094, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_800_IPCLKPORT_I_CLK, 0x2054, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S1, 0x20fc, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S2, 0x2100, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D2_VPC_IPCLKPORT_I_CLK, 0x20a8, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_ACLK, 0x20e4, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_CACHE_IPCLKPORT_I_CLK, 0x207c, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_CACHE_IPCLKPORT_I_CLK, 0x2074, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_AD_APB_VPC0_IPCLKPORT_PCLKM, 0x2028, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S1, 0x20ec, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S2, 0x20f0, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S1, 0x20f4, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S2, 0x20f8, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_ACLK, 0x20dc, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_ACLK, 0x20e0, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D0_VPC_IPCLKPORT_I_CLK, 0x2098, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D1_VPC_IPCLKPORT_I_CLK, 0x20a0, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_DMA_IPCLKPORT_I_CLK, 0x20c4, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_DMA_IPCLKPORT_I_CLK, 0x20c8, CMU_VPC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VPC_UID_HPM_VPC_IPCLKPORT_HPM_TARGETCLK_C, 0x2020, CMU_VPC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CH_CLK, 0x200c, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_HPM_VPC_IPCLKPORT_PCLK, 0x2040, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_PCLK, 0x2030, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_CLK_CORE, 0x202c, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_PCLK, 0x2038, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_CK_IN, 0x2034, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_HTU_IPCLKPORT_CLK, 0x20e8, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_ADM_DAP_VPC_IPCLKPORT_DAPCLKM, 0x2024, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_DAP_CLK, 0x2058, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_CLK, 0x2048, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_PCLK, 0x204c, CMU_VPC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CLK, 0x2018, CMU_VPC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VPC_UID_DDD_VPC_IPCLKPORT_CK_IN, 0x201c, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_VGEN_LITE_VPC_IPCLKPORT_CLK, 0x2104, CMU_VPC),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPC_UID_XIU_VPC_VOTF_IPCLKPORT_ACLK, 0x2108, CMU_VPC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VPD_UID_VPD_CMU_VPD_IPCLKPORT_PCLK, 0x2000, CMU_VPD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPD_UID_SYSREG_VPD_IPCLKPORT_PCLK, 0x2038, CMU_VPD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_SFR_IPCLKPORT_I_CLK, 0x202c, CMU_VPD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSD_IPCLKPORT_CLK, 0x2030, CMU_VPD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSP_IPCLKPORT_CLK, 0x2034, CMU_VPD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPD_UID_IP_VPD_IPCLKPORT_CLK, 0x200c, CMU_VPD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_CACHE_IPCLKPORT_I_CLK, 0x2028, CMU_VPD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_P_VPCVPD_IPCLKPORT_I_CLK, 0x2024, CMU_VPD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_SFR_IPCLKPORT_I_CLK, 0x2018, CMU_VPD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPD_UID_D_TZPC_VPD_IPCLKPORT_PCLK, 0x2008, CMU_VPD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_DMA_IPCLKPORT_I_CLK, 0x2010, CMU_VPD),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK, 0x200c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK, 0x2100, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK, 0x2004, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK, 0x207c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK, 0x2000, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK, 0x2138, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK, 0x2008, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK, 0x20e0, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK, 0x20a0, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK, 0x214c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK, 0x202c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_PCLK, 0x2034, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK, 0x2080, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_IPCLKPORT_CLK, 0x2010, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU, 0x2118, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK, 0x2024, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK, 0x20e8, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_D_TZPC_VTS_IPCLKPORT_PCLK, 0x209c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK, 0x20f8, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_VGEN_LITE_IPCLKPORT_CLK, 0x2148, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_LP_VTS_IPCLKPORT_I_CLK, 0x201c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_P_VTS_IPCLKPORT_I_CLK, 0x2020, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_D_VTS_IPCLKPORT_ACLK, 0x2134, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_D_VTS_IPCLKPORT_I_PCLK, 0x2018, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK, 0x20ec, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK, 0x203c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_PCLK, 0x2044, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK, 0x2098, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK, 0x2090, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK, 0x2094, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_APM_VTS1_IPCLKPORT_PCLK, 0x20f0, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK, 0x2144, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_PDMA_VTS_IPCLKPORT_ACLK, 0x20f4, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_PCLK, 0x204c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_PCLK, 0x2054, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK, 0x2060, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK, 0x2084, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK, 0x2088, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK, 0x208c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK, 0x206c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_PCLK, 0x2078, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_PCLK, 0x2114, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK, 0x2058, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK, 0x205c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK, 0x2064, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK, 0x2068, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK, 0x2070, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK, 0x2074, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0, 0x211c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0, 0x2128, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK, 0x20fc, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK, 0x2104, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_BCLK, 0x2108, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_HCLK, 0x2110, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1, 0x2120, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK2, 0x2124, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1, 0x212c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2, 0x2130, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK, 0x213c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK, 0x2140, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_PCLK, 0x21dc, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_BCLK, 0x21d4, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_PCLK, 0x21cc, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_BCLK, 0x21c4, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_D_AUDVTS_IPCLKPORT_I_CLK, 0x21ac, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK, 0x21b4, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_C_VTS_IPCLKPORT_I_PCLK, 0x20e4, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_C_VTS_IPCLKPORT_I_CLK, 0x21b0, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_C_VTS_IPCLKPORT_ACLK, 0x21e4, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK, 0x21bc, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AHB_IPCLKPORT_CLK, 0x21b8, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK, 0x210c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_HCLK, 0x2150, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK, 0x2154, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_HCLK, 0x2158, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_HCLK, 0x215c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_HCLK, 0x2160, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK, 0x2164, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK, 0x216c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK, 0x2174, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK, 0x217c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK, 0x2184, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK, 0x218c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_CLK, 0x21e0, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_CLK, 0x21d8, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_CLK, 0x21c8, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKS, 0x2030, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKS, 0x2040, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKS, 0x2050, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKS, 0x20a8, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKS, 0x20b0, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKS, 0x20b8, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKM, 0x2028, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKM, 0x2038, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKM, 0x2048, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKM, 0x20a4, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKM, 0x20ac, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKM, 0x20b4, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS, 0x2168, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS, 0x2170, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS, 0x2178, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_BUS, 0x2180, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_BUS, 0x2188, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_BUS, 0x2190, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_HPM_VTS_IPCLKPORT_HPM_TARGETCLK_C, 0x2014, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNC_APB_VTS_IPCLKPORT_PCLKM, 0x20bc, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_BUSIF_HPM_VTS_IPCLKPORT_PCLK, 0x20c4, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_PCLK, 0x20d4, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_ACLK, 0x20c8, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CLK, 0x20d0, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_DIV2_IPCLKPORT_CLK, 0x21a4, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CCLK, 0x20cc, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS, 0x2198, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK, 0x2194, CMU_VTS),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_LP_VTS_IPCLKPORT_I_CLK, 0x20dc, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVPP_UID_YUVPP_CMU_YUVPP_IPCLKPORT_PCLK, 0x2000, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_YUVPP0_IPCLKPORT_PCLKM, 0x2008, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_D_TZPC_YUVPP_IPCLKPORT_PCLK, 0x2010, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHM_AXI_P_YUVPP_IPCLKPORT_I_CLK, 0x2014, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSREG_YUVPP_IPCLKPORT_PCLK, 0x2054, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP0_IPCLKPORT_CLK, 0x2058, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSD_IPCLKPORT_CLK, 0x203c, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSP_IPCLKPORT_CLK, 0x2040, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S1, 0x204c, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_PCLK, 0x2030, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_PCLK, 0x2020, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_ACLK, 0x202c, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S2, 0x2050, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D0_YUVPP_IPCLKPORT_ACLK, 0x2060, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPP_IPCLKPORT_I_CLK, 0x2018, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_ACLK, 0x2064, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_PCLK, 0x2068, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_ACLK, 0x205c, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK, 0x20b8, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_C2COM, 0x20bc, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_ACLK, 0x206c, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_ACLK, 0x2074, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_ACLK, 0x207c, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_ACLK, 0x2084, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_PCLK, 0x2070, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_PCLK, 0x2078, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_PCLK, 0x2080, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_PCLK, 0x2088, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK, 0x2038, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_FRC_IPCLKPORT_CLK, 0x20ac, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_FRC_MC_IPCLKPORT_I_CLK, 0x2028, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP1_IPCLKPORT_CLK, 0x20b0, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_ACLK, 0x208c, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_PCLK, 0x2090, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_ACLK, 0x2094, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_PCLK, 0x2098, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_ACLK, 0x209c, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_PCLK, 0x20a0, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_ACLK, 0x20a4, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_PCLK, 0x20a8, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D1_YUVPP_IPCLKPORT_ACLK, 0x20b4, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_FRC_MC_IPCLKPORT_PCLKM, 0x201c, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK, 0x2048, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_AXI_FRC_MC_IPCLKPORT_ACLKM, 0x2024, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP2_IPCLKPORT_CLK, 0x20c4, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_ACLK, 0x20cc, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_PCLK, 0x20c8, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_ACLK, 0x20d0, CMU_YUVPP),
|
|
SFR(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_PCLK, 0x20c0, CMU_YUVPP),
|
|
SFR(CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0x1888, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG, 0x18ac, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK, 0x1800, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_DIV_CLK_G3D_ADD_CH_CLK, 0x1800, CMU_G3D),
|
|
SFR(CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD, 0x1800, CMU_HSI0),
|
|
SFR(CLK_CON_DIV_CLK_MCSC_ADD_CH_CLK, 0x1804, CMU_MCSC),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MIF_BUSD, 0x1800, CMU_MIF),
|
|
SFR(CLK_CON_DIV_CLK_NPUS_ADD_CH_CLK, 0x1800, CMU_NPUS),
|
|
SFR(CLK_CON_DIV_CLKCMU_OTP, 0x1800, CMU_PERIS),
|
|
SFR(CLK_CON_DIV_CLK_MIF_BUSD_S2D, 0x1800, CMU_S2D),
|
|
SFR(CLK_CON_DIV_CLK_TAA_ADD_CH_CLK, 0x1804, CMU_TAA),
|
|
SFR(CLK_CON_DIV_CLK_VPC_ADD_CH_CLK, 0x1804, CMU_VPC),
|
|
SFR(QCH_CON_ALIVE_CMU_ALIVE_QCH, 0x3044, CMU_ALIVE),
|
|
SFR(QCH_CON_APBIF_PMU_ALIVE_QCH, 0x3038, CMU_ALIVE),
|
|
SFR(QCH_CON_APBIF_RTC_QCH, 0x303c, CMU_ALIVE),
|
|
SFR(QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH, 0x30d8, CMU_ALIVE),
|
|
SFR(QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH, 0x30d4, CMU_ALIVE),
|
|
SFR(QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH, 0x30d0, CMU_ALIVE),
|
|
SFR(QCH_CON_APBIF_TOP_RTC_QCH, 0x3040, CMU_ALIVE),
|
|
SFR(QCH_CON_CLKMON_QCH, 0x3018, CMU_ALIVE),
|
|
SFR(QCH_CON_DBGCORE_UART_QCH, 0x3054, CMU_ALIVE),
|
|
SFR(QCH_CON_DOUBLE_IP_BATCHER_QCH_APM, 0x3060, CMU_ALIVE),
|
|
SFR(QCH_CON_DOUBLE_IP_BATCHER_QCH_CPU, 0x3080, CMU_ALIVE),
|
|
SFR(QCH_CON_DOUBLE_IP_BATCHER_QCH_SEMA, 0x3094, CMU_ALIVE),
|
|
SFR(QCH_CON_DTZPC_ALIVE_QCH, 0x3048, CMU_ALIVE),
|
|
SFR(QCH_CON_GPIO_ALIVE_QCH, 0x3034, CMU_ALIVE),
|
|
SFR(QCH_CON_GREBEINTEGRATION_QCH_GREBE, 0x3050, CMU_ALIVE),
|
|
SFR(QCH_CON_GREBEINTEGRATION_QCH_DBG, 0x304c, CMU_ALIVE),
|
|
SFR(QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH, 0x3098, CMU_ALIVE),
|
|
SFR(QCH_CON_I3C_PMIC_QCH_P, 0x3058, CMU_ALIVE),
|
|
SFR(DMYQCH_CON_I3C_PMIC_QCH_S, 0x3004, CMU_ALIVE),
|
|
SFR(QCH_CON_INTMEM_QCH, 0x305c, CMU_ALIVE),
|
|
SFR(QCH_CON_LHM_AXI_C_MODEM_QCH, 0x309c, CMU_ALIVE),
|
|
SFR(QCH_CON_LHM_AXI_C_VTS_QCH, 0x30a0, CMU_ALIVE),
|
|
SFR(QCH_CON_LHM_AXI_P_APM_QCH, 0x3064, CMU_ALIVE),
|
|
SFR(QCH_CON_LHS_AXI_C_CMGP_QCH, 0x3068, CMU_ALIVE),
|
|
SFR(QCH_CON_LHS_AXI_D_APM_QCH, 0x306c, CMU_ALIVE),
|
|
SFR(QCH_CON_LHS_AXI_G_DBGCORE_QCH, 0x3070, CMU_ALIVE),
|
|
SFR(QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH, 0x3074, CMU_ALIVE),
|
|
SFR(QCH_CON_LHS_AXI_LP_VTS_QCH, 0x3078, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_APM_AP_QCH, 0x307c, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_APM_CP_QCH, 0x30b8, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_AP_CP_QCH, 0x30bc, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_AP_CP_S_QCH, 0x30c0, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_AP_DBGCORE_QCH, 0x3084, CMU_ALIVE),
|
|
SFR(QCH_CON_PEM_QCH, 0x3088, CMU_ALIVE),
|
|
SFR(QCH_CON_PMU_INTR_GEN_QCH, 0x308c, CMU_ALIVE),
|
|
SFR(QCH_CON_ROM_CRC32_HOST_QCH, 0x3090, CMU_ALIVE),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH, 0x30c8, CMU_ALIVE),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH, 0x30c4, CMU_ALIVE),
|
|
SFR(QCH_CON_SS_DBGCORE_QCH_GREBE, 0x30a8, CMU_ALIVE),
|
|
SFR(QCH_CON_SS_DBGCORE_QCH_DBG, 0x30a4, CMU_ALIVE),
|
|
SFR(QCH_CON_SWEEPER_P_ALIVE_QCH, 0x30cc, CMU_ALIVE),
|
|
SFR(QCH_CON_SYSREG_ALIVE_QCH, 0x30ac, CMU_ALIVE),
|
|
SFR(QCH_CON_VGEN_LITE_ALIVE_QCH, 0x30b0, CMU_ALIVE),
|
|
SFR(QCH_CON_WDT_ALIVE_QCH, 0x30b4, CMU_ALIVE),
|
|
SFR(QCH_CON_ABOX_QCH_ACLK, 0x301c, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK_DSIF, 0x303c, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK0, 0x3020, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK1, 0x3024, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK2, 0x3028, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK3, 0x302c, CMU_AUD),
|
|
SFR(DMYQCH_CON_ABOX_QCH_CPU, 0x3000, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK4, 0x3030, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_CNT, 0x3044, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK5, 0x3034, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_CCLK_ASB, 0x3040, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_SCLK, 0x3048, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK6, 0x3038, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_XCLK, 0x30c0, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_PCMC_CLK, 0x30bc, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_C2A0, 0x30ac, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_C2A1, 0x30b0, CMU_AUD),
|
|
SFR(QCH_CON_AUD_CMU_AUD_QCH, 0x304c, CMU_AUD),
|
|
SFR(QCH_CON_BAAW_D_AUDVTS_QCH, 0x30c4, CMU_AUD),
|
|
SFR(QCH_CON_D_TZPC_AUD_QCH, 0x30c8, CMU_AUD),
|
|
SFR(QCH_CON_LHM_AXI_D_HSI0AUD_QCH, 0x30d4, CMU_AUD),
|
|
SFR(QCH_CON_LHM_AXI_P_AUD_QCH, 0x3050, CMU_AUD),
|
|
SFR(QCH_CON_LHS_AXI_D_AUD_QCH, 0x3054, CMU_AUD),
|
|
SFR(QCH_CON_LHS_AXI_D_AUDHSI0_QCH, 0x30e0, CMU_AUD),
|
|
SFR(QCH_CON_LHS_AXI_D_AUDVTS_QCH, 0x30e4, CMU_AUD),
|
|
SFR(QCH_CON_MAILBOX_AUD0_QCH, 0x30e8, CMU_AUD),
|
|
SFR(QCH_CON_MAILBOX_AUD1_QCH, 0x30ec, CMU_AUD),
|
|
SFR(QCH_CON_MAILBOX_AUD2_QCH, 0x30f0, CMU_AUD),
|
|
SFR(QCH_CON_MAILBOX_AUD3_QCH, 0x30f4, CMU_AUD),
|
|
SFR(QCH_CON_PPMU_AUD_QCH, 0x3058, CMU_AUD),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH, 0x305c, CMU_AUD),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH, 0x3060, CMU_AUD),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH, 0x3064, CMU_AUD),
|
|
SFR(QCH_CON_SMMU_AUD_QCH_S1, 0x3068, CMU_AUD),
|
|
SFR(QCH_CON_SMMU_AUD_QCH_S2, 0x306c, CMU_AUD),
|
|
SFR(QCH_CON_SYSREG_AUD_QCH, 0x3070, CMU_AUD),
|
|
SFR(QCH_CON_TREX_AUD_QCH, 0x30f8, CMU_AUD),
|
|
SFR(QCH_CON_VGEN_LITE_AUD_QCH, 0x3074, CMU_AUD),
|
|
SFR(QCH_CON_WDT_AUD_QCH, 0x3078, CMU_AUD),
|
|
SFR(QCH_CON_ASYNCSFR_WR_SMC_QCH, 0x3024, CMU_BUS0),
|
|
SFR(QCH_CON_BAAW_P_VPC_QCH, 0x302c, CMU_BUS0),
|
|
SFR(QCH_CON_BUS0_CMU_BUS0_QCH, 0x3074, CMU_BUS0),
|
|
SFR(QCH_CON_BUSIF_CMUTOPC_QCH, 0x3078, CMU_BUS0),
|
|
SFR(QCH_CON_CACHEAID_BUS0_QCH, 0x307c, CMU_BUS0),
|
|
SFR(DMYQCH_CON_CMU_BUS0_CMUREF_QCH, 0x3000, CMU_BUS0),
|
|
SFR(QCH_CON_D_TZPC_BUS0_QCH, 0x3080, CMU_BUS0),
|
|
SFR(QCH_CON_LHM_ACEL_D0_VPC_QCH, 0x3088, CMU_BUS0),
|
|
SFR(QCH_CON_LHM_ACEL_D1_VPC_QCH, 0x3084, CMU_BUS0),
|
|
SFR(QCH_CON_LHM_ACEL_D2_VPC_QCH, 0x308c, CMU_BUS0),
|
|
SFR(QCH_CON_LHM_AXI_D0_NPUS_QCH, 0x30a8, CMU_BUS0),
|
|
SFR(QCH_CON_LHM_AXI_D1_NPUS_QCH, 0x3090, CMU_BUS0),
|
|
SFR(QCH_CON_LHM_AXI_D2_NPUS_QCH, 0x3094, CMU_BUS0),
|
|
SFR(QCH_CON_LHS_AXI_P_MIF0_QCH, 0x30c8, CMU_BUS0),
|
|
SFR(QCH_CON_LHS_AXI_P_MIF1_QCH, 0x30cc, CMU_BUS0),
|
|
SFR(QCH_CON_LHS_AXI_P_MIF2_QCH, 0x30d0, CMU_BUS0),
|
|
SFR(QCH_CON_LHS_AXI_P_MIF3_QCH, 0x30d4, CMU_BUS0),
|
|
SFR(QCH_CON_LHS_AXI_P_NPU00_QCH, 0x30b8, CMU_BUS0),
|
|
SFR(QCH_CON_LHS_AXI_P_NPU01_QCH, 0x30c0, CMU_BUS0),
|
|
SFR(QCH_CON_LHS_AXI_P_NPU10_QCH, 0x30c4, CMU_BUS0),
|
|
SFR(QCH_CON_LHS_AXI_P_NPUS_QCH, 0x30e8, CMU_BUS0),
|
|
SFR(QCH_CON_LHS_AXI_P_PERIC0_QCH, 0x3030, CMU_BUS0),
|
|
SFR(QCH_CON_LHS_AXI_P_PERIC2_QCH, 0x3058, CMU_BUS0),
|
|
SFR(QCH_CON_LHS_AXI_P_PERISGIC_QCH, 0x30e4, CMU_BUS0),
|
|
SFR(QCH_CON_LHS_AXI_P_VPC_QCH, 0x30b4, CMU_BUS0),
|
|
SFR(QCH_CON_SYSREG_BUS0_QCH, 0x30ec, CMU_BUS0),
|
|
SFR(QCH_CON_TREX_D0_BUS0_QCH, 0x30f0, CMU_BUS0),
|
|
SFR(QCH_CON_TREX_D1_BUS0_QCH, 0x30f4, CMU_BUS0),
|
|
SFR(QCH_CON_TREX_P_BUS0_QCH, 0x30f8, CMU_BUS0),
|
|
SFR(QCH_CON_BAAW_P_VTS_QCH, 0x3088, CMU_BUS1),
|
|
SFR(QCH_CON_BUS1_CMU_BUS1_QCH, 0x308c, CMU_BUS1),
|
|
SFR(DMYQCH_CON_CMU_BUS1_CMUREF_QCH, 0x3000, CMU_BUS1),
|
|
SFR(QCH_CON_DIT_QCH, 0x3094, CMU_BUS1),
|
|
SFR(QCH_CON_D_TZPC_BUS1_QCH, 0x3098, CMU_BUS1),
|
|
SFR(QCH_CON_LHM_ACEL_D_HSI0_QCH, 0x30b4, CMU_BUS1),
|
|
SFR(QCH_CON_LHM_AXI_D0_DPUF0_QCH, 0x30a4, CMU_BUS1),
|
|
SFR(QCH_CON_LHM_AXI_D0_DPUF1_QCH, 0x3030, CMU_BUS1),
|
|
SFR(QCH_CON_LHM_AXI_D1_DPUF0_QCH, 0x30ac, CMU_BUS1),
|
|
SFR(QCH_CON_LHM_AXI_D1_DPUF1_QCH, 0x3034, CMU_BUS1),
|
|
SFR(QCH_CON_LHM_AXI_D_APM_QCH, 0x30d0, CMU_BUS1),
|
|
SFR(QCH_CON_LHM_AXI_D_SBIC_QCH, 0x303c, CMU_BUS1),
|
|
SFR(QCH_CON_LHM_AXI_D_VTS_QCH, 0x30d8, CMU_BUS1),
|
|
SFR(QCH_CON_LHS_AXI_D_SBIC_QCH, 0x3044, CMU_BUS1),
|
|
SFR(QCH_CON_LHS_AXI_P_DPUB_QCH, 0x30e4, CMU_BUS1),
|
|
SFR(QCH_CON_LHS_AXI_P_DPUF0_QCH, 0x30e8, CMU_BUS1),
|
|
SFR(QCH_CON_LHS_AXI_P_DPUF1_QCH, 0x3048, CMU_BUS1),
|
|
SFR(QCH_CON_LHS_AXI_P_HSI0_QCH, 0x30f0, CMU_BUS1),
|
|
SFR(QCH_CON_LHS_AXI_P_VTS_QCH, 0x3108, CMU_BUS1),
|
|
SFR(QCH_CON_PDMA_QCH, 0x310c, CMU_BUS1),
|
|
SFR(QCH_CON_QE_PDMA_QCH, 0x3110, CMU_BUS1),
|
|
SFR(QCH_CON_QE_SPDMA_QCH, 0x3118, CMU_BUS1),
|
|
SFR(QCH_CON_SBIC_QCH, 0x3124, CMU_BUS1),
|
|
SFR(QCH_CON_SPDMA_QCH, 0x3128, CMU_BUS1),
|
|
SFR(QCH_CON_SYSMMU_S2_ACVPS_QCH, 0x3130, CMU_BUS1),
|
|
SFR(QCH_CON_SYSMMU_S2_DIT_QCH, 0x3134, CMU_BUS1),
|
|
SFR(QCH_CON_SYSMMU_S2_SBIC_QCH, 0x3138, CMU_BUS1),
|
|
SFR(QCH_CON_SYSREG_BUS1_QCH, 0x313c, CMU_BUS1),
|
|
SFR(QCH_CON_TREX_D_BUS1_QCH, 0x3140, CMU_BUS1),
|
|
SFR(QCH_CON_TREX_P_BUS1_QCH, 0x3148, CMU_BUS1),
|
|
SFR(QCH_CON_TREX_RB_BUS1_QCH, 0x314c, CMU_BUS1),
|
|
SFR(QCH_CON_VGEN_LITE_BUS1_QCH, 0x3150, CMU_BUS1),
|
|
SFR(QCH_CON_VGEN_PDMA_QCH, 0x3154, CMU_BUS1),
|
|
SFR(QCH_CON_BUS2_CMU_BUS2_QCH, 0x30a4, CMU_BUS2),
|
|
SFR(DMYQCH_CON_CMU_BUS2_CMUREF_QCH, 0x3000, CMU_BUS2),
|
|
SFR(QCH_CON_D_TZPC_BUS2_QCH, 0x30a8, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_ACEL_D0_MCSC_QCH, 0x30c4, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_ACEL_D_HSI1_QCH, 0x30ac, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_ACEL_D_M2M_QCH, 0x316c, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_ACEL_D_SSP_QCH, 0x30b4, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D0_CSIS_QCH, 0x30b8, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D0_DNS_QCH, 0x30bc, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D0_MCFP0_QCH, 0x30c0, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D0_MFC0_QCH, 0x30c8, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D0_MFC1_QCH, 0x30cc, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D1_CSIS_QCH, 0x30d0, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D1_DNS_QCH, 0x30d4, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D1_MCFP0_QCH, 0x30d8, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D1_MCSC_QCH, 0x30dc, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D1_MFC0_QCH, 0x30e0, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D1_MFC1_QCH, 0x30e4, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D2_CSIS_QCH, 0x30e8, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D2_MCFP0_QCH, 0x30ec, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D2_MCSC_QCH, 0x30f0, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D3_CSIS_QCH, 0x30f4, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D3_MCFP0_QCH, 0x30f8, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D_LME_QCH, 0x30fc, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D_MCFP1_QCH, 0x3100, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D_TAA_QCH, 0x3104, CMU_BUS2),
|
|
SFR(QCH_CON_LHM_AXI_D_YUVPP_QCH, 0x3108, CMU_BUS2),
|
|
SFR(QCH_CON_LHS_AXI_P_CSIS_QCH, 0x310c, CMU_BUS2),
|
|
SFR(QCH_CON_LHS_AXI_P_HSI1_QCH, 0x3110, CMU_BUS2),
|
|
SFR(QCH_CON_LHS_AXI_P_ITP_QCH, 0x3118, CMU_BUS2),
|
|
SFR(QCH_CON_LHS_AXI_P_LME_QCH, 0x311c, CMU_BUS2),
|
|
SFR(QCH_CON_LHS_AXI_P_M2M_QCH, 0x317c, CMU_BUS2),
|
|
SFR(QCH_CON_LHS_AXI_P_MCFP0_QCH, 0x3120, CMU_BUS2),
|
|
SFR(QCH_CON_LHS_AXI_P_MCSC_QCH, 0x3124, CMU_BUS2),
|
|
SFR(QCH_CON_LHS_AXI_P_MFC0_QCH, 0x3128, CMU_BUS2),
|
|
SFR(QCH_CON_LHS_AXI_P_MFC1_QCH, 0x312c, CMU_BUS2),
|
|
SFR(QCH_CON_LHS_AXI_P_PERIC1_QCH, 0x3130, CMU_BUS2),
|
|
SFR(QCH_CON_LHS_AXI_P_SSP_QCH, 0x3134, CMU_BUS2),
|
|
SFR(QCH_CON_LHS_AXI_P_TAA_QCH, 0x3138, CMU_BUS2),
|
|
SFR(QCH_CON_LHS_AXI_P_YUVPP_QCH, 0x313c, CMU_BUS2),
|
|
SFR(QCH_CON_SYSREG_BUS2_QCH, 0x3140, CMU_BUS2),
|
|
SFR(QCH_CON_TREX_D_BUS2_QCH, 0x3144, CMU_BUS2),
|
|
SFR(QCH_CON_TREX_P_BUS2_QCH, 0x3148, CMU_BUS2),
|
|
SFR(QCH_CON_ADC_CMGP_QCH_S0, 0x3008, CMU_CMGP),
|
|
SFR(QCH_CON_ADC_CMGP_QCH_S1, 0x300c, CMU_CMGP),
|
|
SFR(DMYQCH_CON_ADC_CMGP_QCH_OSC, 0x3000, CMU_CMGP),
|
|
SFR(QCH_CON_APBIF_GPIO_CMGP_QCH, 0x3050, CMU_CMGP),
|
|
SFR(QCH_CON_CMGP_CMU_CMGP_QCH, 0x3010, CMU_CMGP),
|
|
SFR(QCH_CON_D_TZPC_CMGP_QCH, 0x3018, CMU_CMGP),
|
|
SFR(QCH_CON_GPIO_CMGP_QCH, 0x301c, CMU_CMGP),
|
|
SFR(QCH_CON_I2C_CMGP0_QCH, 0x3020, CMU_CMGP),
|
|
SFR(QCH_CON_I2C_CMGP1_QCH, 0x3024, CMU_CMGP),
|
|
SFR(QCH_CON_I2C_CMGP2_QCH, 0x3028, CMU_CMGP),
|
|
SFR(QCH_CON_I2C_CMGP3_QCH, 0x302c, CMU_CMGP),
|
|
SFR(QCH_CON_I3C_CMGP_QCH_P, 0x3058, CMU_CMGP),
|
|
SFR(DMYQCH_CON_I3C_CMGP_QCH_S, 0x3014, CMU_CMGP),
|
|
SFR(QCH_CON_LHM_AXI_C_CMGP_QCH, 0x3030, CMU_CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP_QCH, 0x303c, CMU_CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2APM_QCH, 0x3034, CMU_CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2CP_QCH, 0x3060, CMU_CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2PMU_AP_QCH, 0x3038, CMU_CMGP),
|
|
SFR(QCH_CON_USI_CMGP0_QCH, 0x3040, CMU_CMGP),
|
|
SFR(QCH_CON_USI_CMGP1_QCH, 0x3044, CMU_CMGP),
|
|
SFR(QCH_CON_USI_CMGP2_QCH, 0x3048, CMU_CMGP),
|
|
SFR(QCH_CON_USI_CMGP3_QCH, 0x304c, CMU_CMGP),
|
|
SFR(DMYQCH_CON_CMU_TOP_CMUREF_QCH, 0x3000, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0, 0x3004, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1, 0x3008, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2, 0x300c, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3, 0x3010, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4, 0x3014, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5, 0x3018, CMU_TOP),
|
|
SFR(QCH_CON_ACE_SLICE_G3D0_QCH, 0x3090, CMU_CORE),
|
|
SFR(QCH_CON_ACE_SLICE_G3D1_QCH, 0x30a4, CMU_CORE),
|
|
SFR(QCH_CON_ACE_SLICE_G3D2_QCH, 0x30a8, CMU_CORE),
|
|
SFR(QCH_CON_ACE_SLICE_G3D3_QCH, 0x30cc, CMU_CORE),
|
|
SFR(QCH_CON_BAAW_CP_QCH, 0x30d0, CMU_CORE),
|
|
SFR(QCH_CON_BDU_QCH, 0x3050, CMU_CORE),
|
|
SFR(DMYQCH_CON_CCI_QCH, 0x3000, CMU_CORE),
|
|
SFR(DMYQCH_CON_CMU_CORE_CMUREF_QCH, 0x3004, CMU_CORE),
|
|
SFR(QCH_CON_CORE_CMU_CORE_QCH, 0x3054, CMU_CORE),
|
|
SFR(QCH_CON_D_TZPC_CORE_QCH, 0x3058, CMU_CORE),
|
|
SFR(QCH_CON_LHM_ACEL_D2_MODEM_QCH, 0x30e4, CMU_CORE),
|
|
SFR(QCH_CON_LHM_ACE_D0_CLUSTER0_QCH, 0x305c, CMU_CORE),
|
|
SFR(QCH_CON_LHM_ACE_D0_G3D_QCH, 0x3060, CMU_CORE),
|
|
SFR(QCH_CON_LHM_ACE_D1_CLUSTER0_QCH, 0x3064, CMU_CORE),
|
|
SFR(QCH_CON_LHM_ACE_D1_G3D_QCH, 0x3068, CMU_CORE),
|
|
SFR(QCH_CON_LHM_ACE_D2_G3D_QCH, 0x306c, CMU_CORE),
|
|
SFR(QCH_CON_LHM_ACE_D3_G3D_QCH, 0x3070, CMU_CORE),
|
|
SFR(QCH_CON_LHM_AXI_D0_MODEM_QCH, 0x30e8, CMU_CORE),
|
|
SFR(QCH_CON_LHM_AXI_D1_MODEM_QCH, 0x30ec, CMU_CORE),
|
|
SFR(QCH_CON_LHM_AXI_D_AUD_QCH, 0x30f0, CMU_CORE),
|
|
SFR(QCH_CON_LHM_AXI_G_CSSYS_QCH, 0x3074, CMU_CORE),
|
|
SFR(QCH_CON_LHS_ATB_T_BDU_QCH, 0x3080, CMU_CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_APM_QCH, 0x3088, CMU_CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_AUD_QCH, 0x3114, CMU_CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_CPUCL0_QCH, 0x308c, CMU_CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_G3D_QCH, 0x3094, CMU_CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_MODEM_QCH, 0x3118, CMU_CORE),
|
|
SFR(QCH_CON_LHS_AXI_P_PERIS_QCH, 0x311c, CMU_CORE),
|
|
SFR(QCH_CON_PPCFW_G3D_QCH, 0x3098, CMU_CORE),
|
|
SFR(QCH_CON_PPC_CPUCL0_0_QCH, 0x309c, CMU_CORE),
|
|
SFR(QCH_CON_PPC_CPUCL0_1_QCH, 0x30a0, CMU_CORE),
|
|
SFR(QCH_CON_PPC_G3D0_QCH, 0x30ac, CMU_CORE),
|
|
SFR(QCH_CON_PPC_G3D1_QCH, 0x30b0, CMU_CORE),
|
|
SFR(QCH_CON_PPC_G3D2_QCH, 0x30b4, CMU_CORE),
|
|
SFR(QCH_CON_PPC_G3D3_QCH, 0x30b8, CMU_CORE),
|
|
SFR(QCH_CON_PPC_IRPS0_QCH, 0x30bc, CMU_CORE),
|
|
SFR(QCH_CON_PPC_IRPS1_QCH, 0x30c0, CMU_CORE),
|
|
SFR(QCH_CON_PPC_IRPS2_QCH, 0x3120, CMU_CORE),
|
|
SFR(QCH_CON_PPC_IRPS3_QCH, 0x3124, CMU_CORE),
|
|
SFR(QCH_CON_PPMU_CPUCL0_0_QCH, 0x30c4, CMU_CORE),
|
|
SFR(QCH_CON_PPMU_CPUCL0_1_QCH, 0x30c8, CMU_CORE),
|
|
SFR(QCH_CON_PPMU_G3D0_QCH, 0x30d4, CMU_CORE),
|
|
SFR(QCH_CON_PPMU_G3D1_QCH, 0x30d8, CMU_CORE),
|
|
SFR(QCH_CON_PPMU_G3D2_QCH, 0x30dc, CMU_CORE),
|
|
SFR(QCH_CON_PPMU_G3D3_QCH, 0x30e0, CMU_CORE),
|
|
SFR(QCH_CON_SYSMMU_G3D0_QCH, 0x30f4, CMU_CORE),
|
|
SFR(QCH_CON_SYSMMU_G3D1_QCH, 0x30f8, CMU_CORE),
|
|
SFR(QCH_CON_SYSMMU_G3D2_QCH, 0x30fc, CMU_CORE),
|
|
SFR(QCH_CON_SYSMMU_G3D3_QCH, 0x3100, CMU_CORE),
|
|
SFR(QCH_CON_SYSMMU_MODEM_QCH, 0x3128, CMU_CORE),
|
|
SFR(QCH_CON_SYSREG_CORE_QCH, 0x3104, CMU_CORE),
|
|
SFR(QCH_CON_TREX_D_CORE_QCH, 0x3108, CMU_CORE),
|
|
SFR(QCH_CON_TREX_P0_CORE_QCH, 0x310c, CMU_CORE),
|
|
SFR(QCH_CON_TREX_P1_CORE_QCH, 0x3110, CMU_CORE),
|
|
SFR(QCH_CON_VGEN_LITE_MODEM_QCH, 0x312c, CMU_CORE),
|
|
SFR(DMYQCH_CON_ADD_CPUCL0_0_QCH, 0x3000, CMU_CPUCL0),
|
|
SFR(QCH_CON_BUSIF_ADD_CPUCL0_0_QCH, 0x3010, CMU_CPUCL0),
|
|
SFR(QCH_CON_BUSIF_STR_CPUCL0_0_QCH, 0x3014, CMU_CPUCL0),
|
|
SFR(QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE, 0x3028, CMU_CPUCL0),
|
|
SFR(DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH, 0x3004, CMU_CPUCL0),
|
|
SFR(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH, 0x3018, CMU_CPUCL0),
|
|
SFR(DMYQCH_CON_CPUCL0_QCH, 0x3008, CMU_CPUCL0),
|
|
SFR(QCH_CON_CPUCL0_CMU_CPUCL0_QCH, 0x301c, CMU_CPUCL0),
|
|
SFR(DMYQCH_CON_DDD_CPUCL0_0_QCH, 0x300c, CMU_CPUCL0),
|
|
SFR(QCH_CON_HTU_CPUCL0_QCH, 0x3020, CMU_CPUCL0),
|
|
SFR(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_0_QCH, 0x3024, CMU_CPUCL0),
|
|
SFR(QCH_CON_BPS_CPUCL0_QCH, 0x3088, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_BUSIF_HPM_CPUCL0_QCH, 0x3098, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH, 0x30ac, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_CSSYS_QCH, 0x30b0, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_D_TZPC_CPUCL0_QCH, 0x30b4, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHM_ATB_T0_CLUSTER0_QCH, 0x30c8, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHM_ATB_T1_CLUSTER0_QCH, 0x30cc, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHM_ATB_T2_CLUSTER0_QCH, 0x30d0, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHM_ATB_T3_CLUSTER0_QCH, 0x30d4, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHM_ATB_T4_CLUSTER0_QCH, 0x30d8, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHM_ATB_T5_CLUSTER0_QCH, 0x30dc, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHM_ATB_T6_CLUSTER0_QCH, 0x30e0, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHM_ATB_T7_CLUSTER0_QCH, 0x30e4, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHM_ATB_T_BDU_QCH, 0x30e8, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHM_AXI_G_DBGCORE_QCH, 0x30ec, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHM_AXI_G_INT_CSSYS_QCH, 0x30f0, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH, 0x30f4, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHM_AXI_G_INT_ETR_QCH, 0x30f8, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHM_AXI_G_INT_STM_QCH, 0x30fc, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHM_AXI_P_CPUCL0_QCH, 0x3100, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHS_AXI_G_CSSYS_QCH, 0x3104, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHS_AXI_G_INT_CSSYS_QCH, 0x3108, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH, 0x310c, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHS_AXI_G_INT_ETR_QCH, 0x3110, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LHS_AXI_G_INT_STM_QCH, 0x3114, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH, 0x3128, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH, 0x312c, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SECJTAG_QCH, 0x3130, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SYSREG_CPUCL0_QCH, 0x3134, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_TREX_CPUCL0_QCH, 0x3138, CMU_CPUCL0_GLB),
|
|
SFR(DMYQCH_CON_ADD_CPUCL0_1_QCH, 0x3008, CMU_CPUCL1),
|
|
SFR(QCH_CON_BUSIF_ADD_CPUCL0_1_QCH, 0x3018, CMU_CPUCL1),
|
|
SFR(QCH_CON_BUSIF_STR_CPUCL0_1_QCH, 0x301c, CMU_CPUCL1),
|
|
SFR(QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE, 0x3038, CMU_CPUCL1),
|
|
SFR(DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH, 0x3000, CMU_CPUCL1),
|
|
SFR(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH, 0x3010, CMU_CPUCL1),
|
|
SFR(DMYQCH_CON_CPUCL1_QCH, 0x3004, CMU_CPUCL1),
|
|
SFR(DMYQCH_CON_CPUCL1_QCH_DDD_HC0, 0x300c, CMU_CPUCL1),
|
|
SFR(DMYQCH_CON_CPUCL1_QCH_DDD_HC1, 0x3020, CMU_CPUCL1),
|
|
SFR(DMYQCH_CON_CPUCL1_QCH_DDD_HC2, 0x3034, CMU_CPUCL1),
|
|
SFR(QCH_CON_CPUCL1_CMU_CPUCL1_QCH, 0x3014, CMU_CPUCL1),
|
|
SFR(QCH_CON_HTU_CPUCL1_QCH_PCLK, 0x3030, CMU_CPUCL1),
|
|
SFR(QCH_CON_HTU_CPUCL1_QCH_CLK, 0x303c, CMU_CPUCL1),
|
|
SFR(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_2_QCH, 0x3024, CMU_CPUCL1),
|
|
SFR(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_3_QCH, 0x3028, CMU_CPUCL1),
|
|
SFR(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_4_QCH, 0x302c, CMU_CPUCL1),
|
|
SFR(DMYQCH_CON_ADD_CPUCL0_2_QCH, 0x3000, CMU_CPUCL2),
|
|
SFR(QCH_CON_BUSIF_ADD_CPUCL0_2_QCH, 0x3010, CMU_CPUCL2),
|
|
SFR(QCH_CON_BUSIF_STR_CPUCL0_2_QCH, 0x3014, CMU_CPUCL2),
|
|
SFR(QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE, 0x3020, CMU_CPUCL2),
|
|
SFR(DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH, 0x3004, CMU_CPUCL2),
|
|
SFR(QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH, 0x3018, CMU_CPUCL2),
|
|
SFR(DMYQCH_CON_CPUCL2_QCH, 0x3008, CMU_CPUCL2),
|
|
SFR(QCH_CON_CPUCL2_CMU_CPUCL2_QCH, 0x301c, CMU_CPUCL2),
|
|
SFR(DMYQCH_CON_DDD_CPUCL0_1_QCH, 0x300c, CMU_CPUCL2),
|
|
SFR(QCH_CON_HTU_CPUCL2_QCH_PCLK, 0x3028, CMU_CPUCL2),
|
|
SFR(QCH_CON_HTU_CPUCL2_QCH_CLK, 0x302c, CMU_CPUCL2),
|
|
SFR(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_1_QCH, 0x3024, CMU_CPUCL2),
|
|
SFR(QCH_CON_CSISX6_QCH_VOTF0, 0x321c, CMU_CSIS),
|
|
SFR(QCH_CON_CSISX6_QCH_DMA, 0x3254, CMU_CSIS),
|
|
SFR(QCH_CON_CSISX6_QCH_MCB, 0x3224, CMU_CSIS),
|
|
SFR(QCH_CON_CSISX6_QCH_VOTF1, 0x30b0, CMU_CSIS),
|
|
SFR(QCH_CON_CSIS_CMU_CSIS_QCH, 0x3058, CMU_CSIS),
|
|
SFR(QCH_CON_D_TZPC_CSIS_QCH, 0x3080, CMU_CSIS),
|
|
SFR(QCH_CON_LHM_AST_INT_OTF0_CSISPDP_QCH, 0x314c, CMU_CSIS),
|
|
SFR(QCH_CON_LHM_AST_INT_OTF0_PDPCSIS_QCH, 0x3150, CMU_CSIS),
|
|
SFR(QCH_CON_LHM_AST_INT_OTF1_CSISPDP_QCH, 0x3154, CMU_CSIS),
|
|
SFR(QCH_CON_LHM_AST_INT_OTF1_PDPCSIS_QCH, 0x3158, CMU_CSIS),
|
|
SFR(QCH_CON_LHM_AST_INT_OTF2_CSISPDP_QCH, 0x315c, CMU_CSIS),
|
|
SFR(QCH_CON_LHM_AST_INT_OTF2_PDPCSIS_QCH, 0x3160, CMU_CSIS),
|
|
SFR(QCH_CON_LHM_AST_INT_OTF3_CSISPDP_QCH, 0x3164, CMU_CSIS),
|
|
SFR(QCH_CON_LHM_AST_INT_OTF3_PDPCSIS_QCH, 0x3168, CMU_CSIS),
|
|
SFR(QCH_CON_LHM_AST_INT_VO_CSISPDP_QCH, 0x316c, CMU_CSIS),
|
|
SFR(QCH_CON_LHM_AST_INT_VO_PDPCSIS_QCH, 0x330c, CMU_CSIS),
|
|
SFR(QCH_CON_LHM_AST_SOTF0_TAACSIS_QCH, 0x3084, CMU_CSIS),
|
|
SFR(QCH_CON_LHM_AST_SOTF1_TAACSIS_QCH, 0x3088, CMU_CSIS),
|
|
SFR(QCH_CON_LHM_AST_SOTF2_TAACSIS_QCH, 0x308c, CMU_CSIS),
|
|
SFR(QCH_CON_LHM_AST_SOTF3_TAACSIS_QCH, 0x3170, CMU_CSIS),
|
|
SFR(QCH_CON_LHM_AST_ZOTF0_TAACSIS_QCH, 0x3094, CMU_CSIS),
|
|
SFR(QCH_CON_LHM_AST_ZOTF1_TAACSIS_QCH, 0x3098, CMU_CSIS),
|
|
SFR(QCH_CON_LHM_AST_ZOTF2_TAACSIS_QCH, 0x309c, CMU_CSIS),
|
|
SFR(QCH_CON_LHM_AST_ZOTF3_TAACSIS_QCH, 0x3174, CMU_CSIS),
|
|
SFR(QCH_CON_LHM_AXI_P_CSIS_QCH, 0x30a0, CMU_CSIS),
|
|
SFR(QCH_CON_LHS_AST_INT_OTF0_CSISPDP_QCH, 0x3178, CMU_CSIS),
|
|
SFR(QCH_CON_LHS_AST_INT_OTF0_PDPCSIS_QCH, 0x317c, CMU_CSIS),
|
|
SFR(QCH_CON_LHS_AST_INT_OTF1_CSISPDP_QCH, 0x3180, CMU_CSIS),
|
|
SFR(QCH_CON_LHS_AST_INT_OTF1_PDPCSIS_QCH, 0x3184, CMU_CSIS),
|
|
SFR(QCH_CON_LHS_AST_INT_OTF2_CSISPDP_QCH, 0x3188, CMU_CSIS),
|
|
SFR(QCH_CON_LHS_AST_INT_OTF2_PDPCSIS_QCH, 0x318c, CMU_CSIS),
|
|
SFR(QCH_CON_LHS_AST_INT_OTF3_CSISPDP_QCH, 0x3190, CMU_CSIS),
|
|
SFR(QCH_CON_LHS_AST_INT_OTF3_PDPCSIS_QCH, 0x3194, CMU_CSIS),
|
|
SFR(QCH_CON_LHS_AST_INT_VO_CSISPDP_QCH, 0x3198, CMU_CSIS),
|
|
SFR(QCH_CON_LHS_AST_INT_VO_PDPCSIS_QCH, 0x3220, CMU_CSIS),
|
|
SFR(QCH_CON_LHS_AST_OTF0_CSISTAA_QCH, 0x30a4, CMU_CSIS),
|
|
SFR(QCH_CON_LHS_AST_OTF1_CSISTAA_QCH, 0x30a8, CMU_CSIS),
|
|
SFR(QCH_CON_LHS_AST_OTF2_CSISTAA_QCH, 0x30ac, CMU_CSIS),
|
|
SFR(QCH_CON_LHS_AST_OTF3_CSISTAA_QCH, 0x319c, CMU_CSIS),
|
|
SFR(QCH_CON_LHS_AXI_D0_CSIS_QCH, 0x30b4, CMU_CSIS),
|
|
SFR(QCH_CON_LHS_AXI_D1_CSIS_QCH, 0x30b8, CMU_CSIS),
|
|
SFR(QCH_CON_LHS_AXI_D2_CSIS_QCH, 0x31a0, CMU_CSIS),
|
|
SFR(QCH_CON_LHS_AXI_D3_CSIS_QCH, 0x31a4, CMU_CSIS),
|
|
SFR(QCH_CON_LHS_AXI_P_CSISPERIC1_QCH, 0x30bc, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0, 0x31a8, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1, 0x31ac, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2, 0x31b0, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3, 0x31b4, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4, 0x31b8, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5, 0x31bc, CMU_CSIS),
|
|
SFR(QCH_CON_OIS_MCU_TOP_QCH, 0x30c0, CMU_CSIS),
|
|
SFR(QCH_CON_PDP_TOP_QCH_PDP_TOP, 0x31c4, CMU_CSIS),
|
|
SFR(QCH_CON_PDP_TOP_QCH_C2_PDP, 0x31c0, CMU_CSIS),
|
|
SFR(QCH_CON_PPMU_D0_QCH, 0x30d0, CMU_CSIS),
|
|
SFR(QCH_CON_PPMU_D1_QCH, 0x30d4, CMU_CSIS),
|
|
SFR(QCH_CON_PPMU_D2_QCH, 0x30d8, CMU_CSIS),
|
|
SFR(QCH_CON_PPMU_D3_QCH, 0x31c8, CMU_CSIS),
|
|
SFR(QCH_CON_QE_CSIS_DMA0_QCH, 0x30e4, CMU_CSIS),
|
|
SFR(QCH_CON_QE_CSIS_DMA1_QCH, 0x30e8, CMU_CSIS),
|
|
SFR(QCH_CON_QE_CSIS_DMA2_QCH, 0x31cc, CMU_CSIS),
|
|
SFR(QCH_CON_QE_CSIS_DMA3_QCH, 0x31d0, CMU_CSIS),
|
|
SFR(QCH_CON_QE_PDP_AF1_QCH, 0x31d8, CMU_CSIS),
|
|
SFR(QCH_CON_QE_PDP_AF2_QCH, 0x31dc, CMU_CSIS),
|
|
SFR(QCH_CON_QE_PDP_STAT_AF0_QCH, 0x31d4, CMU_CSIS),
|
|
SFR(QCH_CON_QE_PDP_STAT_IMG0_QCH, 0x30ec, CMU_CSIS),
|
|
SFR(QCH_CON_QE_PDP_STAT_IMG1_QCH, 0x31e4, CMU_CSIS),
|
|
SFR(QCH_CON_QE_PDP_STAT_IMG2_QCH, 0x31e0, CMU_CSIS),
|
|
SFR(QCH_CON_QE_STRP0_QCH, 0x30f0, CMU_CSIS),
|
|
SFR(QCH_CON_QE_STRP1_QCH, 0x31e8, CMU_CSIS),
|
|
SFR(QCH_CON_QE_STRP2_QCH, 0x31ec, CMU_CSIS),
|
|
SFR(QCH_CON_QE_STRP3_QCH, 0x31f4, CMU_CSIS),
|
|
SFR(QCH_CON_QE_ZSL0_QCH, 0x30f4, CMU_CSIS),
|
|
SFR(QCH_CON_QE_ZSL1_QCH, 0x31f0, CMU_CSIS),
|
|
SFR(QCH_CON_QE_ZSL2_QCH, 0x3218, CMU_CSIS),
|
|
SFR(QCH_CON_QE_ZSL3_QCH, 0x3214, CMU_CSIS),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH, 0x31f8, CMU_CSIS),
|
|
SFR(QCH_CON_SYSMMU_D0_CSIS_QCH_S1, 0x30fc, CMU_CSIS),
|
|
SFR(QCH_CON_SYSMMU_D0_CSIS_QCH_S2, 0x3100, CMU_CSIS),
|
|
SFR(QCH_CON_SYSMMU_D1_CSIS_QCH_S1, 0x3104, CMU_CSIS),
|
|
SFR(QCH_CON_SYSMMU_D1_CSIS_QCH_S2, 0x3108, CMU_CSIS),
|
|
SFR(QCH_CON_SYSMMU_D2_CSIS_QCH_S1, 0x31fc, CMU_CSIS),
|
|
SFR(QCH_CON_SYSMMU_D2_CSIS_QCH_S2, 0x3200, CMU_CSIS),
|
|
SFR(QCH_CON_SYSMMU_D3_CSIS_QCH_S1, 0x3204, CMU_CSIS),
|
|
SFR(QCH_CON_SYSMMU_D3_CSIS_QCH_S2, 0x3208, CMU_CSIS),
|
|
SFR(QCH_CON_SYSREG_CSIS_QCH, 0x310c, CMU_CSIS),
|
|
SFR(QCH_CON_VGEN_LITE_D0_QCH, 0x3110, CMU_CSIS),
|
|
SFR(QCH_CON_VGEN_LITE_D1_QCH, 0x320c, CMU_CSIS),
|
|
SFR(QCH_CON_VGEN_LITE_D2_QCH, 0x3210, CMU_CSIS),
|
|
SFR(QCH_CON_DNS_QCH, 0x3088, CMU_DNS),
|
|
SFR(QCH_CON_DNS_QCH_VOTF0, 0x3074, CMU_DNS),
|
|
SFR(QCH_CON_DNS_QCH_VOTF1, 0x3078, CMU_DNS),
|
|
SFR(QCH_CON_DNS_QCH_VOTF2, 0x3084, CMU_DNS),
|
|
SFR(QCH_CON_DNS_CMU_DNS_QCH, 0x3048, CMU_DNS),
|
|
SFR(QCH_CON_D_TZPC_DNS_QCH, 0x3090, CMU_DNS),
|
|
SFR(QCH_CON_LHM_AST_CTL_ITPDNS_QCH, 0x3094, CMU_DNS),
|
|
SFR(QCH_CON_LHM_AST_OTF0_ITPDNS_QCH, 0x3098, CMU_DNS),
|
|
SFR(QCH_CON_LHM_AST_OTF1_ITPDNS_QCH, 0x309c, CMU_DNS),
|
|
SFR(QCH_CON_LHM_AST_OTF2_ITPDNS_QCH, 0x30a0, CMU_DNS),
|
|
SFR(QCH_CON_LHM_AST_OTF3_ITPDNS_QCH, 0x30a4, CMU_DNS),
|
|
SFR(QCH_CON_LHM_AST_OTF4_ITPDNS_QCH, 0x30a8, CMU_DNS),
|
|
SFR(QCH_CON_LHM_AST_OTF_MCFP1DNS_QCH, 0x30ac, CMU_DNS),
|
|
SFR(QCH_CON_LHM_AST_OTF_TAADNS_QCH, 0x30b0, CMU_DNS),
|
|
SFR(QCH_CON_LHM_AXI_P_ITPDNS_QCH, 0x30c0, CMU_DNS),
|
|
SFR(QCH_CON_LHS_AST_CTL_DNSITP_QCH, 0x30c4, CMU_DNS),
|
|
SFR(QCH_CON_LHS_AST_OTF0_DNSITP_QCH, 0x30c8, CMU_DNS),
|
|
SFR(QCH_CON_LHS_AST_OTF1_DNSITP_QCH, 0x30cc, CMU_DNS),
|
|
SFR(QCH_CON_LHS_AST_OTF2_DNSITP_QCH, 0x30d0, CMU_DNS),
|
|
SFR(QCH_CON_LHS_AST_OTF3_DNSITP_QCH, 0x30d4, CMU_DNS),
|
|
SFR(QCH_CON_LHS_AST_OTF4_DNSITP_QCH, 0x30d8, CMU_DNS),
|
|
SFR(QCH_CON_LHS_AST_OTF5_DNSITP_QCH, 0x30dc, CMU_DNS),
|
|
SFR(QCH_CON_LHS_AST_OTF6_DNSITP_QCH, 0x30e0, CMU_DNS),
|
|
SFR(QCH_CON_LHS_AST_OTF7_DNSITP_QCH, 0x30e4, CMU_DNS),
|
|
SFR(QCH_CON_LHS_AST_OTF8_DNSITP_QCH, 0x30e8, CMU_DNS),
|
|
SFR(QCH_CON_LHS_AST_OTF9_DNSITP_QCH, 0x30ec, CMU_DNS),
|
|
SFR(QCH_CON_LHS_AXI_D0_DNS_QCH, 0x30f8, CMU_DNS),
|
|
SFR(QCH_CON_LHS_AXI_D1_DNS_QCH, 0x30fc, CMU_DNS),
|
|
SFR(QCH_CON_PPMU_D0_DNS_QCH, 0x3100, CMU_DNS),
|
|
SFR(QCH_CON_PPMU_D1_DNS_QCH, 0x3104, CMU_DNS),
|
|
SFR(QCH_CON_SYSMMU_D0_DNS_QCH_S2, 0x310c, CMU_DNS),
|
|
SFR(QCH_CON_SYSMMU_D0_DNS_QCH_S1, 0x3108, CMU_DNS),
|
|
SFR(QCH_CON_SYSMMU_D1_DNS_QCH_S2, 0x3114, CMU_DNS),
|
|
SFR(QCH_CON_SYSMMU_D1_DNS_QCH_S1, 0x3110, CMU_DNS),
|
|
SFR(QCH_CON_SYSREG_DNS_QCH, 0x3118, CMU_DNS),
|
|
SFR(QCH_CON_VGEN_LITE_D0_DNS_QCH, 0x311c, CMU_DNS),
|
|
SFR(QCH_CON_VGEN_LITE_D1_DNS_QCH, 0x3120, CMU_DNS),
|
|
SFR(QCH_CON_DPUB_QCH, 0x3018, CMU_DPUB),
|
|
SFR(QCH_CON_DPUB_CMU_DPUB_QCH, 0x3014, CMU_DPUB),
|
|
SFR(QCH_CON_D_TZPC_DPUB_QCH, 0x301c, CMU_DPUB),
|
|
SFR(QCH_CON_LHM_AXI_P_DPUB_QCH, 0x3020, CMU_DPUB),
|
|
SFR(QCH_CON_SYSREG_DPUB_QCH, 0x3024, CMU_DPUB),
|
|
SFR(QCH_CON_DPUF0_QCH_DMA, 0x3040, CMU_DPUF0),
|
|
SFR(QCH_CON_DPUF0_QCH_DPP, 0x3044, CMU_DPUF0),
|
|
SFR(QCH_CON_DPUF0_QCH_C2SERV, 0x30a0, CMU_DPUF0),
|
|
SFR(QCH_CON_DPUF0_CMU_DPUF0_QCH, 0x3038, CMU_DPUF0),
|
|
SFR(QCH_CON_D_TZPC_DPUF0_QCH, 0x304c, CMU_DPUF0),
|
|
SFR(QCH_CON_LHM_AXI_D_DPUF1DPUF0_QCH, 0x3020, CMU_DPUF0),
|
|
SFR(QCH_CON_LHM_AXI_P_DPUF0_QCH, 0x3050, CMU_DPUF0),
|
|
SFR(QCH_CON_LHS_AXI_D0_DPUF0_QCH, 0x3054, CMU_DPUF0),
|
|
SFR(QCH_CON_LHS_AXI_D1_DPUF0_QCH, 0x3058, CMU_DPUF0),
|
|
SFR(QCH_CON_PPMU_DPUF0D0_QCH, 0x3060, CMU_DPUF0),
|
|
SFR(QCH_CON_PPMU_DPUF0D1_QCH, 0x3064, CMU_DPUF0),
|
|
SFR(QCH_CON_SYSMMU_DPUF0D0_QCH_S1, 0x306c, CMU_DPUF0),
|
|
SFR(QCH_CON_SYSMMU_DPUF0D0_QCH_S2, 0x3070, CMU_DPUF0),
|
|
SFR(QCH_CON_SYSMMU_DPUF0D1_QCH_S1, 0x3074, CMU_DPUF0),
|
|
SFR(QCH_CON_SYSMMU_DPUF0D1_QCH_S2, 0x3078, CMU_DPUF0),
|
|
SFR(QCH_CON_SYSREG_DPUF0_QCH, 0x3084, CMU_DPUF0),
|
|
SFR(QCH_CON_DPUF1_QCH_DMA, 0x3034, CMU_DPUF1),
|
|
SFR(QCH_CON_DPUF1_QCH_DPP, 0x3038, CMU_DPUF1),
|
|
SFR(QCH_CON_DPUF1_QCH_C2SERV, 0x3030, CMU_DPUF1),
|
|
SFR(QCH_CON_DPUF1_CMU_DPUF1_QCH, 0x302c, CMU_DPUF1),
|
|
SFR(QCH_CON_D_TZPC_DPUF1_QCH, 0x303c, CMU_DPUF1),
|
|
SFR(QCH_CON_LHM_AXI_P_DPUF1_QCH, 0x3044, CMU_DPUF1),
|
|
SFR(QCH_CON_LHS_AXI_D0_DPUF1_QCH, 0x304c, CMU_DPUF1),
|
|
SFR(QCH_CON_LHS_AXI_D1_DPUF1_QCH, 0x3050, CMU_DPUF1),
|
|
SFR(QCH_CON_LHS_AXI_D_DPUF1DPUF0_QCH, 0x307c, CMU_DPUF1),
|
|
SFR(QCH_CON_PPMU_DPUF1D0_QCH, 0x3054, CMU_DPUF1),
|
|
SFR(QCH_CON_PPMU_DPUF1D1_QCH, 0x3058, CMU_DPUF1),
|
|
SFR(QCH_CON_SYSMMU_DPUF1D0_QCH_S2, 0x3060, CMU_DPUF1),
|
|
SFR(QCH_CON_SYSMMU_DPUF1D0_QCH_S1, 0x305c, CMU_DPUF1),
|
|
SFR(QCH_CON_SYSMMU_DPUF1D1_QCH_S2, 0x3068, CMU_DPUF1),
|
|
SFR(QCH_CON_SYSMMU_DPUF1D1_QCH_S1, 0x3064, CMU_DPUF1),
|
|
SFR(QCH_CON_SYSREG_DPUF1_QCH, 0x306c, CMU_DPUF1),
|
|
SFR(QCH_CON_ACE_US_128TO256_D0_CLUSTER0_QCH, 0x3038, CMU_DSU),
|
|
SFR(QCH_CON_ACE_US_128TO256_D1_CLUSTER0_QCH, 0x303c, CMU_DSU),
|
|
SFR(QCH_CON_BUSIF_STR_CPUCL0_3_QCH, 0x3040, CMU_DSU),
|
|
SFR(QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE, 0x30a8, CMU_DSU),
|
|
SFR(QCH_CON_CLUSTER0_QCH_SCLK, 0x3058, CMU_DSU),
|
|
SFR(QCH_CON_CLUSTER0_QCH_ATCLK, 0x3044, CMU_DSU),
|
|
SFR(QCH_CON_CLUSTER0_QCH_PDBGCLK, 0x3054, CMU_DSU),
|
|
SFR(QCH_CON_CLUSTER0_QCH_GICCLK, 0x304c, CMU_DSU),
|
|
SFR(QCH_CON_CLUSTER0_QCH_DBG_PD, 0x3048, CMU_DSU),
|
|
SFR(QCH_CON_CLUSTER0_QCH_PCLK, 0x3050, CMU_DSU),
|
|
SFR(DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK, 0x3000, CMU_DSU),
|
|
SFR(DMYQCH_CON_CMU_DSU_CMUREF_QCH, 0x3004, CMU_DSU),
|
|
SFR(QCH_CON_CMU_DSU_SHORTSTOP_QCH, 0x305c, CMU_DSU),
|
|
SFR(QCH_CON_DSU_CMU_DSU_QCH, 0x3060, CMU_DSU),
|
|
SFR(QCH_CON_HTU_DSU_QCH, 0x3064, CMU_DSU),
|
|
SFR(QCH_CON_LHM_AST_IRI_GICCPU_CLUSTER0_QCH, 0x3068, CMU_DSU),
|
|
SFR(QCH_CON_LHS_ACE_D0_CLUSTER0_QCH, 0x306c, CMU_DSU),
|
|
SFR(QCH_CON_LHS_ACE_D1_CLUSTER0_QCH, 0x3070, CMU_DSU),
|
|
SFR(QCH_CON_LHS_AST_ICC_CPUGIC_CLUSTER0_QCH, 0x3074, CMU_DSU),
|
|
SFR(QCH_CON_LHS_ATB_T0_CLUSTER0_QCH, 0x3078, CMU_DSU),
|
|
SFR(QCH_CON_LHS_ATB_T1_CLUSTER0_QCH, 0x307c, CMU_DSU),
|
|
SFR(QCH_CON_LHS_ATB_T2_CLUSTER0_QCH, 0x3080, CMU_DSU),
|
|
SFR(QCH_CON_LHS_ATB_T3_CLUSTER0_QCH, 0x3084, CMU_DSU),
|
|
SFR(QCH_CON_LHS_ATB_T4_CLUSTER0_QCH, 0x3088, CMU_DSU),
|
|
SFR(QCH_CON_LHS_ATB_T5_CLUSTER0_QCH, 0x308c, CMU_DSU),
|
|
SFR(QCH_CON_LHS_ATB_T6_CLUSTER0_QCH, 0x3090, CMU_DSU),
|
|
SFR(QCH_CON_LHS_ATB_T7_CLUSTER0_QCH, 0x3094, CMU_DSU),
|
|
SFR(QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH, 0x3098, CMU_DSU),
|
|
SFR(QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH, 0x309c, CMU_DSU),
|
|
SFR(QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH, 0x30a0, CMU_DSU),
|
|
SFR(QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH, 0x30a4, CMU_DSU),
|
|
SFR(QCH_CON_ADD_APBIF_G3D_QCH, 0x3020, CMU_G3D),
|
|
SFR(DMYQCH_CON_ADD_G3D_QCH, 0x3000, CMU_G3D),
|
|
SFR(QCH_CON_ASB_G3D_QCH_LH_D0_G3D, 0x3024, CMU_G3D),
|
|
SFR(QCH_CON_ASB_G3D_QCH_LH_D1_G3D, 0x3028, CMU_G3D),
|
|
SFR(QCH_CON_ASB_G3D_QCH_LH_D2_G3D, 0x302c, CMU_G3D),
|
|
SFR(QCH_CON_ASB_G3D_QCH_LH_D3_G3D, 0x3030, CMU_G3D),
|
|
SFR(QCH_CON_BUSIF_HPMG3D_QCH, 0x3034, CMU_G3D),
|
|
SFR(QCH_CON_BUSIF_STR_G3D_QCH, 0x3050, CMU_G3D),
|
|
SFR(QCH_CON_BUSIF_STR_G3D_QCH_CORE, 0x3060, CMU_G3D),
|
|
SFR(QCH_CON_D_TZPC_G3D_QCH, 0x3038, CMU_G3D),
|
|
SFR(QCH_CON_G3D_CMU_G3D_QCH, 0x303c, CMU_G3D),
|
|
SFR(QCH_CON_GPU_QCH, 0x3040, CMU_G3D),
|
|
SFR(QCH_CON_HTU_G3D_QCH_PCLK, 0x3068, CMU_G3D),
|
|
SFR(QCH_CON_HTU_G3D_QCH_CLK, 0x3064, CMU_G3D),
|
|
SFR(QCH_CON_LHM_AXI_P_G3D_QCH, 0x3044, CMU_G3D),
|
|
SFR(QCH_CON_LHM_AXI_P_INT_G3D_QCH, 0x3048, CMU_G3D),
|
|
SFR(QCH_CON_LHS_AXI_P_INT_G3D_QCH, 0x304c, CMU_G3D),
|
|
SFR(QCH_CON_SYSREG_G3D_QCH, 0x3058, CMU_G3D),
|
|
SFR(QCH_CON_VGEN_LITE_G3D_QCH, 0x305c, CMU_G3D),
|
|
SFR(QCH_CON_DP_LINK_QCH_PCLK, 0x3018, CMU_HSI0),
|
|
SFR(QCH_CON_DP_LINK_QCH_GTC_CLK, 0x3014, CMU_HSI0),
|
|
SFR(QCH_CON_D_TZPC_HSI0_QCH, 0x301c, CMU_HSI0),
|
|
SFR(QCH_CON_HSI0_CMU_HSI0_QCH, 0x3020, CMU_HSI0),
|
|
SFR(QCH_CON_LHM_AXI_D_AUDHSI0_QCH, 0x3054, CMU_HSI0),
|
|
SFR(QCH_CON_LHM_AXI_P_HSI0_QCH, 0x3024, CMU_HSI0),
|
|
SFR(QCH_CON_LHS_ACEL_D_HSI0_QCH, 0x3028, CMU_HSI0),
|
|
SFR(QCH_CON_LHS_AXI_D_HSI0AUD_QCH, 0x3058, CMU_HSI0),
|
|
SFR(QCH_CON_PPMU_HSI0_BUS1_QCH, 0x302c, CMU_HSI0),
|
|
SFR(QCH_CON_SYSMMU_USB_QCH, 0x3030, CMU_HSI0),
|
|
SFR(QCH_CON_SYSREG_HSI0_QCH, 0x3034, CMU_HSI0),
|
|
SFR(DMYQCH_CON_USB31DRD_QCH_REF, 0x3000, CMU_HSI0),
|
|
SFR(QCH_CON_USB31DRD_QCH_SLV_CTRL, 0x3040, CMU_HSI0),
|
|
SFR(QCH_CON_USB31DRD_QCH_SLV_LINK, 0x3044, CMU_HSI0),
|
|
SFR(QCH_CON_USB31DRD_QCH_APB, 0x3038, CMU_HSI0),
|
|
SFR(QCH_CON_USB31DRD_QCH_PCS, 0x303c, CMU_HSI0),
|
|
SFR(QCH_CON_USB31DRD_QCH_DBG, 0x305c, CMU_HSI0),
|
|
SFR(QCH_CON_VGEN_LITE_HSI0_QCH, 0x3048, CMU_HSI0),
|
|
SFR(QCH_CON_D_TZPC_HSI1_QCH, 0x3024, CMU_HSI1),
|
|
SFR(QCH_CON_GPIO_HSI1_QCH, 0x3028, CMU_HSI1),
|
|
SFR(QCH_CON_HSI1_CMU_HSI1_QCH, 0x302c, CMU_HSI1),
|
|
SFR(QCH_CON_LHM_AXI_P_HSI1_QCH, 0x3030, CMU_HSI1),
|
|
SFR(QCH_CON_LHS_ACEL_D_HSI1_QCH, 0x3034, CMU_HSI1),
|
|
SFR(QCH_CON_MMC_CARD_QCH, 0x3038, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN2_QCH_MSTR, 0x3044, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN2_QCH_PCS, 0x3048, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN2_QCH_PHY, 0x304c, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN2_QCH_DBI, 0x3040, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN2_QCH_APB, 0x303c, CMU_HSI1),
|
|
SFR(DMYQCH_CON_PCIE_GEN2_QCH_REF, 0x3000, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN4_0_QCH_APB, 0x3050, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN4_0_QCH_DBI, 0x3058, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN4_0_QCH_AXI, 0x3054, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN4_0_QCH_PCS_APB, 0x305c, CMU_HSI1),
|
|
SFR(DMYQCH_CON_PCIE_GEN4_0_QCH_REF, 0x3004, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN4_0_QCH_PMA_APB, 0x3060, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN4_0_QCH_UDBG_APB, 0x3008, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_IA_GEN2_QCH, 0x3064, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_IA_GEN4_0_QCH, 0x3068, CMU_HSI1),
|
|
SFR(QCH_CON_PPMU_HSI1_QCH, 0x306c, CMU_HSI1),
|
|
SFR(QCH_CON_SYSMMU_HSI1_QCH, 0x3070, CMU_HSI1),
|
|
SFR(QCH_CON_SYSREG_HSI1_QCH, 0x3074, CMU_HSI1),
|
|
SFR(QCH_CON_UFS_EMBD_QCH, 0x309c, CMU_HSI1),
|
|
SFR(QCH_CON_UFS_EMBD_QCH_FMP, 0x3098, CMU_HSI1),
|
|
SFR(QCH_CON_VGEN_LITE_HSI1_QCH, 0x3088, CMU_HSI1),
|
|
SFR(QCH_CON_D_TZPC_ITP_QCH, 0x3058, CMU_ITP),
|
|
SFR(QCH_CON_ITP_QCH, 0x305c, CMU_ITP),
|
|
SFR(QCH_CON_ITP_CMU_ITP_QCH, 0x3040, CMU_ITP),
|
|
SFR(QCH_CON_LHM_AST_CTL_DNSITP_QCH, 0x3060, CMU_ITP),
|
|
SFR(QCH_CON_LHM_AST_OTF0_DNSITP_QCH, 0x3064, CMU_ITP),
|
|
SFR(QCH_CON_LHM_AST_OTF1_DNSITP_QCH, 0x3068, CMU_ITP),
|
|
SFR(QCH_CON_LHM_AST_OTF2_DNSITP_QCH, 0x306c, CMU_ITP),
|
|
SFR(QCH_CON_LHM_AST_OTF3_DNSITP_QCH, 0x3070, CMU_ITP),
|
|
SFR(QCH_CON_LHM_AST_OTF4_DNSITP_QCH, 0x3074, CMU_ITP),
|
|
SFR(QCH_CON_LHM_AST_OTF5_DNSITP_QCH, 0x3078, CMU_ITP),
|
|
SFR(QCH_CON_LHM_AST_OTF6_DNSITP_QCH, 0x307c, CMU_ITP),
|
|
SFR(QCH_CON_LHM_AST_OTF7_DNSITP_QCH, 0x3080, CMU_ITP),
|
|
SFR(QCH_CON_LHM_AST_OTF8_DNSITP_QCH, 0x3084, CMU_ITP),
|
|
SFR(QCH_CON_LHM_AST_OTF9_DNSITP_QCH, 0x3088, CMU_ITP),
|
|
SFR(QCH_CON_LHM_AST_OTF_MCFP1ITP_QCH, 0x308c, CMU_ITP),
|
|
SFR(QCH_CON_LHM_AXI_P_ITP_QCH, 0x3090, CMU_ITP),
|
|
SFR(QCH_CON_LHS_AST_CTL_ITPDNS_QCH, 0x3094, CMU_ITP),
|
|
SFR(QCH_CON_LHS_AST_OTF0_ITPDNS_QCH, 0x3098, CMU_ITP),
|
|
SFR(QCH_CON_LHS_AST_OTF1_ITPDNS_QCH, 0x309c, CMU_ITP),
|
|
SFR(QCH_CON_LHS_AST_OTF2_ITPDNS_QCH, 0x30a0, CMU_ITP),
|
|
SFR(QCH_CON_LHS_AST_OTF3_ITPDNS_QCH, 0x30a4, CMU_ITP),
|
|
SFR(QCH_CON_LHS_AST_OTF4_ITPDNS_QCH, 0x30a8, CMU_ITP),
|
|
SFR(QCH_CON_LHS_AST_OTF_ITPMCSC_QCH, 0x30b8, CMU_ITP),
|
|
SFR(QCH_CON_LHS_AXI_P_ITPDNS_QCH, 0x30ac, CMU_ITP),
|
|
SFR(QCH_CON_SYSREG_ITP_QCH, 0x30b0, CMU_ITP),
|
|
SFR(QCH_CON_D_TZPC_LME_QCH, 0x3020, CMU_LME),
|
|
SFR(QCH_CON_LHM_AXI_P_LME_QCH, 0x3028, CMU_LME),
|
|
SFR(QCH_CON_LHS_AXI_D_LME_QCH, 0x3034, CMU_LME),
|
|
SFR(QCH_CON_LME_QCH, 0x303c, CMU_LME),
|
|
SFR(QCH_CON_LME_QCH_C2, 0x3040, CMU_LME),
|
|
SFR(QCH_CON_LME_CMU_LME_QCH, 0x3038, CMU_LME),
|
|
SFR(QCH_CON_PPMU_LME_QCH, 0x3044, CMU_LME),
|
|
SFR(QCH_CON_SYSMMU_D_LME_QCH_S2, 0x304c, CMU_LME),
|
|
SFR(QCH_CON_SYSMMU_D_LME_QCH_S1, 0x3048, CMU_LME),
|
|
SFR(QCH_CON_SYSREG_LME_QCH, 0x3050, CMU_LME),
|
|
SFR(QCH_CON_VGEN_LITE_LME_QCH, 0x3054, CMU_LME),
|
|
SFR(QCH_CON_ASTC_QCH, 0x302c, CMU_M2M),
|
|
SFR(QCH_CON_D_TZPC_M2M_QCH, 0x3030, CMU_M2M),
|
|
SFR(QCH_CON_JPEG0_QCH, 0x3034, CMU_M2M),
|
|
SFR(QCH_CON_JPEG1_QCH, 0x3038, CMU_M2M),
|
|
SFR(QCH_CON_JSQZ_QCH, 0x303c, CMU_M2M),
|
|
SFR(QCH_CON_LHM_AXI_P_M2M_QCH, 0x3044, CMU_M2M),
|
|
SFR(QCH_CON_LHS_ACEL_D_M2M_QCH, 0x3048, CMU_M2M),
|
|
SFR(QCH_CON_M2M_QCH, 0x3054, CMU_M2M),
|
|
SFR(QCH_CON_M2M_QCH_VOTF, 0x3094, CMU_M2M),
|
|
SFR(QCH_CON_M2M_CMU_M2M_QCH, 0x3050, CMU_M2M),
|
|
SFR(QCH_CON_PPMU_D_M2M_QCH, 0x3058, CMU_M2M),
|
|
SFR(QCH_CON_QE_ASTC_QCH, 0x305c, CMU_M2M),
|
|
SFR(QCH_CON_QE_JPEG0_QCH, 0x3060, CMU_M2M),
|
|
SFR(QCH_CON_QE_JPEG1_QCH, 0x3064, CMU_M2M),
|
|
SFR(QCH_CON_QE_JSQZ_QCH, 0x3068, CMU_M2M),
|
|
SFR(QCH_CON_QE_M2M_QCH, 0x306c, CMU_M2M),
|
|
SFR(QCH_CON_SYSMMU_D_M2M_QCH_S2, 0x3074, CMU_M2M),
|
|
SFR(QCH_CON_SYSMMU_D_M2M_QCH_S1, 0x3070, CMU_M2M),
|
|
SFR(QCH_CON_SYSREG_M2M_QCH, 0x3078, CMU_M2M),
|
|
SFR(QCH_CON_VGEN_LITE_M2M_QCH, 0x307c, CMU_M2M),
|
|
SFR(QCH_CON_D_TZPC_MCFP0_QCH, 0x3020, CMU_MCFP0),
|
|
SFR(QCH_CON_LHM_AST_CTL_MCFP1MCFP0_QCH, 0x3098, CMU_MCFP0),
|
|
SFR(QCH_CON_LHM_AST_OTF0_MCFP1MCFP0_QCH, 0x302c, CMU_MCFP0),
|
|
SFR(QCH_CON_LHM_AST_OTF1_MCFP1MCFP0_QCH, 0x309c, CMU_MCFP0),
|
|
SFR(QCH_CON_LHM_AST_OTF2_MCFP1MCFP0_QCH, 0x30a0, CMU_MCFP0),
|
|
SFR(QCH_CON_LHM_AST_OTF3_MCFP1MCFP0_QCH, 0x30a4, CMU_MCFP0),
|
|
SFR(QCH_CON_LHM_AXI_P_MCFP0_QCH, 0x3028, CMU_MCFP0),
|
|
SFR(QCH_CON_LHS_AST_CTL_MCFP0MCFP1_QCH, 0x30a8, CMU_MCFP0),
|
|
SFR(QCH_CON_LHS_AST_OTF0_MCFP0MCFP1_QCH, 0x3024, CMU_MCFP0),
|
|
SFR(QCH_CON_LHS_AST_OTF1_MCFP0MCFP1_QCH, 0x3030, CMU_MCFP0),
|
|
SFR(QCH_CON_LHS_AXI_D0_MCFP0_QCH, 0x3034, CMU_MCFP0),
|
|
SFR(QCH_CON_LHS_AXI_D1_MCFP0_QCH, 0x30ac, CMU_MCFP0),
|
|
SFR(QCH_CON_LHS_AXI_D2_MCFP0_QCH, 0x30b0, CMU_MCFP0),
|
|
SFR(QCH_CON_LHS_AXI_D3_MCFP0_QCH, 0x30b4, CMU_MCFP0),
|
|
SFR(QCH_CON_LHS_AXI_P_MCFP0MCFP1_QCH, 0x30bc, CMU_MCFP0),
|
|
SFR(QCH_CON_MCFP0_QCH, 0x304c, CMU_MCFP0),
|
|
SFR(QCH_CON_MCFP0_CMU_MCFP0_QCH, 0x3048, CMU_MCFP0),
|
|
SFR(QCH_CON_PPMU_D0_MCFP0_QCH, 0x3038, CMU_MCFP0),
|
|
SFR(QCH_CON_PPMU_D1_MCFP0_QCH, 0x30c0, CMU_MCFP0),
|
|
SFR(QCH_CON_PPMU_D2_MCFP0_QCH, 0x30c4, CMU_MCFP0),
|
|
SFR(QCH_CON_PPMU_D3_MCFP0_QCH, 0x30c8, CMU_MCFP0),
|
|
SFR(QCH_CON_QE_D0_MCFP0_QCH, 0x30cc, CMU_MCFP0),
|
|
SFR(QCH_CON_QE_D1_MCFP0_QCH, 0x30d0, CMU_MCFP0),
|
|
SFR(QCH_CON_QE_D2_MCFP0_QCH, 0x30d4, CMU_MCFP0),
|
|
SFR(QCH_CON_QE_D3_MCFP0_QCH, 0x30d8, CMU_MCFP0),
|
|
SFR(QCH_CON_SYSMMU_D0_MCFP0_QCH_S1, 0x303c, CMU_MCFP0),
|
|
SFR(QCH_CON_SYSMMU_D0_MCFP0_QCH_S2, 0x3040, CMU_MCFP0),
|
|
SFR(QCH_CON_SYSMMU_D1_MCFP0_QCH_S1, 0x30dc, CMU_MCFP0),
|
|
SFR(QCH_CON_SYSMMU_D1_MCFP0_QCH_S2, 0x30e0, CMU_MCFP0),
|
|
SFR(QCH_CON_SYSMMU_D2_MCFP0_QCH_S1, 0x30e4, CMU_MCFP0),
|
|
SFR(QCH_CON_SYSMMU_D2_MCFP0_QCH_S2, 0x30e8, CMU_MCFP0),
|
|
SFR(QCH_CON_SYSMMU_D3_MCFP0_QCH_S1, 0x30ec, CMU_MCFP0),
|
|
SFR(QCH_CON_SYSMMU_D3_MCFP0_QCH_S2, 0x30f0, CMU_MCFP0),
|
|
SFR(QCH_CON_SYSREG_MCFP0_QCH, 0x3044, CMU_MCFP0),
|
|
SFR(QCH_CON_VGEN_LITE_MCFP0_QCH, 0x3050, CMU_MCFP0),
|
|
SFR(QCH_CON_D_TZPC_MCFP1_QCH, 0x304c, CMU_MCFP1),
|
|
SFR(QCH_CON_LHM_AST_CTL_MCFP0MCFP1_QCH, 0x3050, CMU_MCFP1),
|
|
SFR(QCH_CON_LHM_AST_OTF0_MCFP0MCFP1_QCH, 0x3054, CMU_MCFP1),
|
|
SFR(QCH_CON_LHM_AST_OTF1_MCFP0MCFP1_QCH, 0x3058, CMU_MCFP1),
|
|
SFR(QCH_CON_LHM_AST_VO_TAAMCFP1_QCH, 0x305c, CMU_MCFP1),
|
|
SFR(QCH_CON_LHM_AXI_P_MCFP0MCFP1_QCH, 0x3064, CMU_MCFP1),
|
|
SFR(QCH_CON_LHS_AST_CTL_MCFP1MCFP0_QCH, 0x3068, CMU_MCFP1),
|
|
SFR(QCH_CON_LHS_AST_OTF0_MCFP1MCFP0_QCH, 0x306c, CMU_MCFP1),
|
|
SFR(QCH_CON_LHS_AST_OTF1_MCFP1MCFP0_QCH, 0x3070, CMU_MCFP1),
|
|
SFR(QCH_CON_LHS_AST_OTF2_MCFP1MCFP0_QCH, 0x3074, CMU_MCFP1),
|
|
SFR(QCH_CON_LHS_AST_OTF3_MCFP1MCFP0_QCH, 0x3078, CMU_MCFP1),
|
|
SFR(QCH_CON_LHS_AST_OTF_MCFP1DNS_QCH, 0x307c, CMU_MCFP1),
|
|
SFR(QCH_CON_LHS_AST_OTF_MCFP1ITP_QCH, 0x3080, CMU_MCFP1),
|
|
SFR(QCH_CON_LHS_AST_VO_MCFP1TAA_QCH, 0x3084, CMU_MCFP1),
|
|
SFR(QCH_CON_LHS_AXI_D_MCFP1_QCH, 0x3088, CMU_MCFP1),
|
|
SFR(QCH_CON_MCFP1_QCH, 0x3090, CMU_MCFP1),
|
|
SFR(QCH_CON_MCFP1_CMU_MCFP1_QCH, 0x308c, CMU_MCFP1),
|
|
SFR(QCH_CON_ORBMCH0_QCH_C2, 0x3120, CMU_MCFP1),
|
|
SFR(QCH_CON_ORBMCH0_QCH, 0x311c, CMU_MCFP1),
|
|
SFR(QCH_CON_ORBMCH1_QCH, 0x3124, CMU_MCFP1),
|
|
SFR(QCH_CON_ORBMCH1_QCH_C2, 0x3128, CMU_MCFP1),
|
|
SFR(QCH_CON_PPMU_ORBMCH_QCH, 0x309c, CMU_MCFP1),
|
|
SFR(QCH_CON_QE_D0_ORBMCH_QCH, 0x30a0, CMU_MCFP1),
|
|
SFR(QCH_CON_QE_D1_ORBMCH_QCH, 0x30a4, CMU_MCFP1),
|
|
SFR(QCH_CON_QE_D2_ORBMCH_QCH, 0x30a8, CMU_MCFP1),
|
|
SFR(QCH_CON_QE_D3_ORBMCH_QCH, 0x30ac, CMU_MCFP1),
|
|
SFR(QCH_CON_QE_D4_ORBMCH_QCH, 0x3154, CMU_MCFP1),
|
|
SFR(QCH_CON_QE_D5_ORBMCH_QCH, 0x3158, CMU_MCFP1),
|
|
SFR(QCH_CON_SYSMMU_D_MCFP1_QCH_S2, 0x30b4, CMU_MCFP1),
|
|
SFR(QCH_CON_SYSMMU_D_MCFP1_QCH_S1, 0x30b0, CMU_MCFP1),
|
|
SFR(QCH_CON_SYSREG_MCFP1_QCH, 0x30b8, CMU_MCFP1),
|
|
SFR(QCH_CON_VGEN_LITE_D0_MCFP1_QCH, 0x3178, CMU_MCFP1),
|
|
SFR(QCH_CON_VGEN_LITE_D1_MCFP1_QCH, 0x317c, CMU_MCFP1),
|
|
SFR(DMYQCH_CON_ADD_MCSC_QCH, 0x3004, CMU_MCSC),
|
|
SFR(QCH_CON_BUSIF_ADD_MCSC_QCH, 0x307c, CMU_MCSC),
|
|
SFR(QCH_CON_BUSIF_HPM_MCSC_QCH, 0x308c, CMU_MCSC),
|
|
SFR(QCH_CON_D_TZPC_MCSC_QCH, 0x3058, CMU_MCSC),
|
|
SFR(QCH_CON_GDC_QCH, 0x305c, CMU_MCSC),
|
|
SFR(QCH_CON_GDC_QCH_C2_M, 0x3060, CMU_MCSC),
|
|
SFR(QCH_CON_GDC_QCH_C2_S, 0x3040, CMU_MCSC),
|
|
SFR(QCH_CON_LHM_AST_OTF_ITPMCSC_QCH, 0x3044, CMU_MCSC),
|
|
SFR(QCH_CON_LHM_AST_OTF_YUVPPMCSC_QCH, 0x30cc, CMU_MCSC),
|
|
SFR(QCH_CON_LHM_AXI_D_YUVPPMCSC_QCH, 0x30f4, CMU_MCSC),
|
|
SFR(QCH_CON_LHM_AXI_P_MCSC_QCH, 0x3084, CMU_MCSC),
|
|
SFR(QCH_CON_LHS_ACEL_D0_MCSC_QCH, 0x3094, CMU_MCSC),
|
|
SFR(QCH_CON_LHS_AXI_D1_MCSC_QCH, 0x3098, CMU_MCSC),
|
|
SFR(QCH_CON_LHS_AXI_D2_MCSC_QCH, 0x3104, CMU_MCSC),
|
|
SFR(QCH_CON_MCSC_QCH, 0x30a0, CMU_MCSC),
|
|
SFR(QCH_CON_MCSC_QCH_C2_W, 0x30a4, CMU_MCSC),
|
|
SFR(QCH_CON_MCSC_QCH_C2_R, 0x3068, CMU_MCSC),
|
|
SFR(QCH_CON_MCSC_CMU_MCSC_QCH, 0x309c, CMU_MCSC),
|
|
SFR(QCH_CON_PPMU_D0_MCSC_QCH, 0x30b8, CMU_MCSC),
|
|
SFR(QCH_CON_PPMU_D1_MCSC_QCH, 0x30b0, CMU_MCSC),
|
|
SFR(QCH_CON_PPMU_D2_MCSC_QCH, 0x3108, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D0_MCSC_QCH_S1, 0x30d0, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D0_MCSC_QCH_S2, 0x30d4, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D1_MCSC_QCH_S1, 0x30d8, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D1_MCSC_QCH_S2, 0x30dc, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D2_MCSC_QCH_S1, 0x310c, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D2_MCSC_QCH_S2, 0x3110, CMU_MCSC),
|
|
SFR(QCH_CON_SYSREG_MCSC_QCH, 0x30e0, CMU_MCSC),
|
|
SFR(QCH_CON_VGEN_LITE_D0_MCSC_QCH, 0x30e4, CMU_MCSC),
|
|
SFR(QCH_CON_VGEN_LITE_D1_MCSC_QCH, 0x3114, CMU_MCSC),
|
|
SFR(QCH_CON_D_TZPC_MFC0_QCH, 0x3024, CMU_MFC0),
|
|
SFR(QCH_CON_LHM_AST_OTF0_MFC1MFC0_QCH, 0x30a4, CMU_MFC0),
|
|
SFR(QCH_CON_LHM_AST_OTF1_MFC1MFC0_QCH, 0x30a8, CMU_MFC0),
|
|
SFR(QCH_CON_LHM_AST_OTF2_MFC1MFC0_QCH, 0x30ac, CMU_MFC0),
|
|
SFR(QCH_CON_LHM_AST_OTF3_MFC1MFC0_QCH, 0x30b0, CMU_MFC0),
|
|
SFR(QCH_CON_LHM_AXI_P_MFC0_QCH, 0x3028, CMU_MFC0),
|
|
SFR(QCH_CON_LHS_AST_OTF0_MFC0MFC1_QCH, 0x30b8, CMU_MFC0),
|
|
SFR(QCH_CON_LHS_AST_OTF1_MFC0MFC1_QCH, 0x30bc, CMU_MFC0),
|
|
SFR(QCH_CON_LHS_AST_OTF2_MFC0MFC1_QCH, 0x30c0, CMU_MFC0),
|
|
SFR(QCH_CON_LHS_AST_OTF3_MFC0MFC1_QCH, 0x30c4, CMU_MFC0),
|
|
SFR(QCH_CON_LHS_AXI_D0_MFC0_QCH, 0x302c, CMU_MFC0),
|
|
SFR(QCH_CON_LHS_AXI_D1_MFC0_QCH, 0x3030, CMU_MFC0),
|
|
SFR(QCH_CON_LH_ATB_MFC0_QCH_MI, 0x3034, CMU_MFC0),
|
|
SFR(QCH_CON_LH_ATB_MFC0_QCH_SI, 0x3038, CMU_MFC0),
|
|
SFR(QCH_CON_MFC0_QCH, 0x3040, CMU_MFC0),
|
|
SFR(QCH_CON_MFC0_QCH_VOTF, 0x30cc, CMU_MFC0),
|
|
SFR(QCH_CON_MFC0_CMU_MFC0_QCH, 0x303c, CMU_MFC0),
|
|
SFR(QCH_CON_PPMU_MFC0D0_QCH, 0x3044, CMU_MFC0),
|
|
SFR(QCH_CON_PPMU_MFC0D1_QCH, 0x3048, CMU_MFC0),
|
|
SFR(QCH_CON_PPMU_WFD_QCH, 0x304c, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH, 0x30d0, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH, 0x30d4, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH, 0x30d8, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH, 0x30dc, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH, 0x30e4, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH, 0x30e8, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH, 0x30ec, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH, 0x30f0, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH, 0x3050, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH, 0x3054, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH, 0x3058, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH, 0x305c, CMU_MFC0),
|
|
SFR(QCH_CON_SYSMMU_MFC0D0_QCH_S1, 0x3060, CMU_MFC0),
|
|
SFR(QCH_CON_SYSMMU_MFC0D0_QCH_S2, 0x3064, CMU_MFC0),
|
|
SFR(QCH_CON_SYSMMU_MFC0D1_QCH_S1, 0x3068, CMU_MFC0),
|
|
SFR(QCH_CON_SYSMMU_MFC0D1_QCH_S2, 0x306c, CMU_MFC0),
|
|
SFR(QCH_CON_SYSREG_MFC0_QCH, 0x3070, CMU_MFC0),
|
|
SFR(QCH_CON_VGEN_MFC0_QCH, 0x3074, CMU_MFC0),
|
|
SFR(QCH_CON_WFD_QCH, 0x3078, CMU_MFC0),
|
|
SFR(DMYQCH_CON_ADM_APB_MFC0MFC1_QCH, 0x3000, CMU_MFC1),
|
|
SFR(QCH_CON_D_TZPC_MFC1_QCH, 0x3044, CMU_MFC1),
|
|
SFR(QCH_CON_LHM_AST_OTF0_MFC0MFC1_QCH, 0x3048, CMU_MFC1),
|
|
SFR(QCH_CON_LHM_AST_OTF1_MFC0MFC1_QCH, 0x304c, CMU_MFC1),
|
|
SFR(QCH_CON_LHM_AST_OTF2_MFC0MFC1_QCH, 0x3050, CMU_MFC1),
|
|
SFR(QCH_CON_LHM_AST_OTF3_MFC0MFC1_QCH, 0x3054, CMU_MFC1),
|
|
SFR(QCH_CON_LHM_AXI_P_MFC1_QCH, 0x3058, CMU_MFC1),
|
|
SFR(QCH_CON_LHS_AST_OTF0_MFC1MFC0_QCH, 0x305c, CMU_MFC1),
|
|
SFR(QCH_CON_LHS_AST_OTF1_MFC1MFC0_QCH, 0x3060, CMU_MFC1),
|
|
SFR(QCH_CON_LHS_AST_OTF2_MFC1MFC0_QCH, 0x3064, CMU_MFC1),
|
|
SFR(QCH_CON_LHS_AST_OTF3_MFC1MFC0_QCH, 0x3068, CMU_MFC1),
|
|
SFR(QCH_CON_LHS_AXI_D0_MFC1_QCH, 0x306c, CMU_MFC1),
|
|
SFR(QCH_CON_LHS_AXI_D1_MFC1_QCH, 0x3070, CMU_MFC1),
|
|
SFR(QCH_CON_MFC1_QCH, 0x3078, CMU_MFC1),
|
|
SFR(QCH_CON_MFC1_CMU_MFC1_QCH, 0x3074, CMU_MFC1),
|
|
SFR(QCH_CON_PPMU_MFC1D0_QCH, 0x307c, CMU_MFC1),
|
|
SFR(QCH_CON_PPMU_MFC1D1_QCH, 0x3080, CMU_MFC1),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH, 0x3084, CMU_MFC1),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH, 0x3088, CMU_MFC1),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH, 0x308c, CMU_MFC1),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH, 0x3090, CMU_MFC1),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH, 0x3094, CMU_MFC1),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH, 0x3098, CMU_MFC1),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH, 0x309c, CMU_MFC1),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH, 0x30a0, CMU_MFC1),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH, 0x30a4, CMU_MFC1),
|
|
SFR(QCH_CON_SYSMMU_MFC1D0_QCH_S2, 0x30ac, CMU_MFC1),
|
|
SFR(QCH_CON_SYSMMU_MFC1D0_QCH_S1, 0x30a8, CMU_MFC1),
|
|
SFR(QCH_CON_SYSMMU_MFC1D1_QCH_S2, 0x30b4, CMU_MFC1),
|
|
SFR(QCH_CON_SYSMMU_MFC1D1_QCH_S1, 0x30b0, CMU_MFC1),
|
|
SFR(QCH_CON_SYSREG_MFC1_QCH, 0x30b8, CMU_MFC1),
|
|
SFR(QCH_CON_VGEN_MFC1_QCH, 0x30bc, CMU_MFC1),
|
|
SFR(QCH_CON_APBBR_DDRPHY_QCH, 0x3008, CMU_MIF),
|
|
SFR(QCH_CON_APBBR_DMC_QCH, 0x300c, CMU_MIF),
|
|
SFR(DMYQCH_CON_CMU_MIF_CMUREF_QCH, 0x3000, CMU_MIF),
|
|
SFR(QCH_CON_DMC_QCH, 0x3010, CMU_MIF),
|
|
SFR(QCH_CON_D_TZPC_MIF_QCH, 0x3014, CMU_MIF),
|
|
SFR(QCH_CON_LHM_AXI_P_MIF_QCH, 0x3018, CMU_MIF),
|
|
SFR(QCH_CON_MIF_CMU_MIF_QCH, 0x301c, CMU_MIF),
|
|
SFR(QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH, 0x3020, CMU_MIF),
|
|
SFR(QCH_CON_SYSREG_MIF_QCH, 0x3028, CMU_MIF),
|
|
SFR(QCH_CON_D_TZPC_NPU_QCH, 0x301c, CMU_NPU),
|
|
SFR(QCH_CON_IP_NPUCORE_QCH_PCLK, 0x3024, CMU_NPU),
|
|
SFR(QCH_CON_IP_NPUCORE_QCH_ACLK, 0x3020, CMU_NPU),
|
|
SFR(QCH_CON_LHM_AXI_D0_NPU_QCH, 0x3028, CMU_NPU),
|
|
SFR(QCH_CON_LHM_AXI_D1_NPU_QCH, 0x302c, CMU_NPU),
|
|
SFR(QCH_CON_LHM_AXI_D_CTRL_NPU_QCH, 0x3030, CMU_NPU),
|
|
SFR(QCH_CON_LHM_AXI_P_NPU_QCH, 0x3034, CMU_NPU),
|
|
SFR(QCH_CON_LHS_AXI_D_CMDQ_NPU_QCH, 0x3038, CMU_NPU),
|
|
SFR(QCH_CON_LHS_AXI_D_RQ_NPU_QCH, 0x303c, CMU_NPU),
|
|
SFR(QCH_CON_NPU_CMU_NPU_QCH, 0x3144, CMU_NPU),
|
|
SFR(QCH_CON_SYSREG_NPU_QCH, 0x3040, CMU_NPU),
|
|
SFR(QCH_CON_D_TZPC_NPU01_QCH, 0x301c, CMU_NPU01),
|
|
SFR(QCH_CON_IP_NPU01CORE_QCH_PCLK, 0x3024, CMU_NPU01),
|
|
SFR(QCH_CON_IP_NPU01CORE_QCH_ACLK, 0x3020, CMU_NPU01),
|
|
SFR(QCH_CON_LHM_AXI_D0_NPU01_QCH, 0x3028, CMU_NPU01),
|
|
SFR(QCH_CON_LHM_AXI_D1_NPU01_QCH, 0x302c, CMU_NPU01),
|
|
SFR(QCH_CON_LHM_AXI_D_CTRL_NPU01_QCH, 0x3030, CMU_NPU01),
|
|
SFR(QCH_CON_LHM_AXI_P_NPU01_QCH, 0x3034, CMU_NPU01),
|
|
SFR(QCH_CON_LHS_AXI_D_CMDQ_NPU01_QCH, 0x3038, CMU_NPU01),
|
|
SFR(QCH_CON_LHS_AXI_D_RQ_NPU01_QCH, 0x303c, CMU_NPU01),
|
|
SFR(QCH_CON_NPU01_CMU_NPU_QCH, 0x3144, CMU_NPU01),
|
|
SFR(QCH_CON_SYSREG_NPU01_QCH, 0x3040, CMU_NPU01),
|
|
SFR(QCH_CON_D_TZPC_NPU10_QCH, 0x301c, CMU_NPU10),
|
|
SFR(QCH_CON_IP_NPU10CORE_QCH_PCLK, 0x3024, CMU_NPU10),
|
|
SFR(QCH_CON_IP_NPU10CORE_QCH_ACLK, 0x3020, CMU_NPU10),
|
|
SFR(QCH_CON_LHM_AXI_D0_NPU10_QCH, 0x3028, CMU_NPU10),
|
|
SFR(QCH_CON_LHM_AXI_D1_NPU10_QCH, 0x302c, CMU_NPU10),
|
|
SFR(QCH_CON_LHM_AXI_D_CTRL_NPU10_QCH, 0x3030, CMU_NPU10),
|
|
SFR(QCH_CON_LHM_AXI_P_NPU10_QCH, 0x3034, CMU_NPU10),
|
|
SFR(QCH_CON_LHS_AXI_D_CMDQ_NPU10_QCH, 0x3038, CMU_NPU10),
|
|
SFR(QCH_CON_LHS_AXI_D_RQ_NPU10_QCH, 0x303c, CMU_NPU10),
|
|
SFR(QCH_CON_NPU10_CMU_NPU_QCH, 0x3144, CMU_NPU10),
|
|
SFR(QCH_CON_SYSREG_NPU10_QCH, 0x3040, CMU_NPU10),
|
|
SFR(DMYQCH_CON_ADD_NPUS_QCH, 0x3000, CMU_NPUS),
|
|
SFR(DMYQCH_CON_ADM_DAP_NPUS_QCH, 0x3004, CMU_NPUS),
|
|
SFR(QCH_CON_BUSIF_ADD_NPUS_QCH, 0x30a4, CMU_NPUS),
|
|
SFR(QCH_CON_BUSIF_HPM_NPUS_QCH, 0x30a8, CMU_NPUS),
|
|
SFR(QCH_CON_D_TZPC_NPUS_QCH, 0x30ac, CMU_NPUS),
|
|
SFR(QCH_CON_HTU_NPUS_QCH_PCLK, 0x309c, CMU_NPUS),
|
|
SFR(QCH_CON_HTU_NPUS_QCH_CLK, 0x3084, CMU_NPUS),
|
|
SFR(QCH_CON_IP_NPUS_QCH, 0x30b4, CMU_NPUS),
|
|
SFR(QCH_CON_IP_NPUS_QCH_C2A0, 0x30b0, CMU_NPUS),
|
|
SFR(QCH_CON_IP_NPUS_QCH_C2A1, 0x30b8, CMU_NPUS),
|
|
SFR(QCH_CON_IP_NPUS_QCH_CPU, 0x30bc, CMU_NPUS),
|
|
SFR(QCH_CON_IP_NPUS_QCH_NEON, 0x30c0, CMU_NPUS),
|
|
SFR(QCH_CON_LHM_AXI_D_CMDQ_NPU00_QCH, 0x30d8, CMU_NPUS),
|
|
SFR(QCH_CON_LHM_AXI_D_CMDQ_NPU01_QCH, 0x30dc, CMU_NPUS),
|
|
SFR(QCH_CON_LHM_AXI_D_CMDQ_NPU10_QCH, 0x30e0, CMU_NPUS),
|
|
SFR(QCH_CON_LHM_AXI_D_RQ_NPU00_QCH, 0x30e8, CMU_NPUS),
|
|
SFR(QCH_CON_LHM_AXI_D_RQ_NPU01_QCH, 0x30ec, CMU_NPUS),
|
|
SFR(QCH_CON_LHM_AXI_D_RQ_NPU10_QCH, 0x30f0, CMU_NPUS),
|
|
SFR(QCH_CON_LHM_AXI_P_INT_NPUS_QCH, 0x30f8, CMU_NPUS),
|
|
SFR(QCH_CON_LHM_AXI_P_NPUS_QCH, 0x30fc, CMU_NPUS),
|
|
SFR(QCH_CON_LHS_AXI_D0_NPU00_QCH, 0x310c, CMU_NPUS),
|
|
SFR(QCH_CON_LHS_AXI_D0_NPU01_QCH, 0x3110, CMU_NPUS),
|
|
SFR(QCH_CON_LHS_AXI_D0_NPU10_QCH, 0x3114, CMU_NPUS),
|
|
SFR(QCH_CON_LHS_AXI_D0_NPUS_QCH, 0x311c, CMU_NPUS),
|
|
SFR(QCH_CON_LHS_AXI_D1_NPU00_QCH, 0x3120, CMU_NPUS),
|
|
SFR(QCH_CON_LHS_AXI_D1_NPU01_QCH, 0x3124, CMU_NPUS),
|
|
SFR(QCH_CON_LHS_AXI_D1_NPU10_QCH, 0x3128, CMU_NPUS),
|
|
SFR(QCH_CON_LHS_AXI_D1_NPUS_QCH, 0x3130, CMU_NPUS),
|
|
SFR(QCH_CON_LHS_AXI_D2_NPUS_QCH, 0x3134, CMU_NPUS),
|
|
SFR(QCH_CON_LHS_AXI_D_CTRL_NPU00_QCH, 0x3138, CMU_NPUS),
|
|
SFR(QCH_CON_LHS_AXI_D_CTRL_NPU01_QCH, 0x313c, CMU_NPUS),
|
|
SFR(QCH_CON_LHS_AXI_D_CTRL_NPU10_QCH, 0x3140, CMU_NPUS),
|
|
SFR(QCH_CON_LHS_AXI_P_INT_NPUS_QCH, 0x3148, CMU_NPUS),
|
|
SFR(QCH_CON_NPUS_CMU_NPUS_QCH, 0x314c, CMU_NPUS),
|
|
SFR(QCH_CON_PPMU_NPUS_0_QCH, 0x3150, CMU_NPUS),
|
|
SFR(QCH_CON_PPMU_NPUS_1_QCH, 0x3154, CMU_NPUS),
|
|
SFR(QCH_CON_PPMU_NPUS_2_QCH, 0x3158, CMU_NPUS),
|
|
SFR(QCH_CON_SYSMMU_D0_NPUS_QCH_S2, 0x3160, CMU_NPUS),
|
|
SFR(QCH_CON_SYSMMU_D0_NPUS_QCH_S1, 0x315c, CMU_NPUS),
|
|
SFR(QCH_CON_SYSMMU_D1_NPUS_QCH_S2, 0x3168, CMU_NPUS),
|
|
SFR(QCH_CON_SYSMMU_D1_NPUS_QCH_S1, 0x3164, CMU_NPUS),
|
|
SFR(QCH_CON_SYSMMU_D2_NPUS_QCH_S2, 0x3170, CMU_NPUS),
|
|
SFR(QCH_CON_SYSMMU_D2_NPUS_QCH_S1, 0x316c, CMU_NPUS),
|
|
SFR(QCH_CON_SYSREG_NPUS_QCH, 0x3174, CMU_NPUS),
|
|
SFR(QCH_CON_VGEN_LITE_NPUS_QCH, 0x3178, CMU_NPUS),
|
|
SFR(QCH_CON_D_TZPC_PERIC0_QCH, 0x3004, CMU_PERIC0),
|
|
SFR(QCH_CON_GPIO_PERIC0_QCH, 0x3008, CMU_PERIC0),
|
|
SFR(QCH_CON_LHM_AXI_P_PERIC0_QCH, 0x300c, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_CMU_PERIC0_QCH, 0x3010, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP0_QCH_UART_DBG, 0x3014, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP0_QCH_USI00_USI, 0x301c, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP0_QCH_USI00_I2C, 0x3018, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP0_QCH_USI01_USI, 0x3024, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP0_QCH_USI01_I2C, 0x3020, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP0_QCH_USI02_USI, 0x302c, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP0_QCH_USI02_I2C, 0x3028, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP0_QCH_USI03_USI, 0x3034, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP0_QCH_USI03_I2C, 0x3030, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP0_QCH_USI04_USI, 0x303c, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP0_QCH_USI04_I2C, 0x3038, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP0_QCH_USI05_USI, 0x3040, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP1_QCH_USI05_I2C, 0x3048, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP1_QCH_USI13_USI, 0x3050, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP1_QCH_USI13_I2C, 0x304c, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP1_QCH_USI14_USI, 0x3058, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP1_QCH_USI14_I2C, 0x3054, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP1_QCH_USI15_USI, 0x3060, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP1_QCH_USI15_I2C, 0x305c, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_TOP1_QCH_PWM, 0x3044, CMU_PERIC0),
|
|
SFR(QCH_CON_SYSREG_PERIC0_QCH, 0x3064, CMU_PERIC0),
|
|
SFR(QCH_CON_D_TZPC_PERIC1_QCH, 0x3018, CMU_PERIC1),
|
|
SFR(QCH_CON_GPIO_PERIC1_QCH, 0x301c, CMU_PERIC1),
|
|
SFR(QCH_CON_LHM_AXI_P_CSISPERIC1_QCH, 0x3020, CMU_PERIC1),
|
|
SFR(QCH_CON_LHM_AXI_P_PERIC1_QCH, 0x3024, CMU_PERIC1),
|
|
SFR(QCH_CON_PERIC1_CMU_PERIC1_QCH, 0x3028, CMU_PERIC1),
|
|
SFR(QCH_CON_PERIC1_TOP0_QCH_UART_BT, 0x302c, CMU_PERIC1),
|
|
SFR(QCH_CON_PERIC1_TOP1_QCH_USI11_USI, 0x305c, CMU_PERIC1),
|
|
SFR(QCH_CON_PERIC1_TOP1_QCH_USI11_I2C, 0x3058, CMU_PERIC1),
|
|
SFR(QCH_CON_PERIC1_TOP1_QCH_USI16_USI, 0x3070, CMU_PERIC1),
|
|
SFR(QCH_CON_PERIC1_TOP1_QCH_USI16_I2C, 0x3068, CMU_PERIC1),
|
|
SFR(QCH_CON_PERIC1_TOP1_QCH_USI17_USI, 0x307c, CMU_PERIC1),
|
|
SFR(QCH_CON_PERIC1_TOP1_QCH_USI17_I2C, 0x3074, CMU_PERIC1),
|
|
SFR(QCH_CON_PERIC1_TOP1_QCH_USI12_USI, 0x3064, CMU_PERIC1),
|
|
SFR(QCH_CON_PERIC1_TOP1_QCH_USI12_I2C, 0x3060, CMU_PERIC1),
|
|
SFR(QCH_CON_PERIC1_TOP1_QCH_USI18_USI, 0x3084, CMU_PERIC1),
|
|
SFR(QCH_CON_PERIC1_TOP1_QCH_USI18_I2C, 0x3080, CMU_PERIC1),
|
|
SFR(QCH_CON_SYSREG_PERIC1_QCH, 0x3088, CMU_PERIC1),
|
|
SFR(QCH_CON_USI16_I3C_QCH_P, 0x308c, CMU_PERIC1),
|
|
SFR(DMYQCH_CON_USI16_I3C_QCH_S, 0x3008, CMU_PERIC1),
|
|
SFR(QCH_CON_USI17_I3C_QCH_P, 0x3090, CMU_PERIC1),
|
|
SFR(DMYQCH_CON_USI17_I3C_QCH_S, 0x300c, CMU_PERIC1),
|
|
SFR(QCH_CON_D_TZPC_PERIC2_QCH, 0x3004, CMU_PERIC2),
|
|
SFR(QCH_CON_GPIO_PERIC2_QCH, 0x3008, CMU_PERIC2),
|
|
SFR(QCH_CON_LHM_AXI_P_PERIC2_QCH, 0x300c, CMU_PERIC2),
|
|
SFR(QCH_CON_PERIC2_CMU_PERIC2_QCH, 0x3010, CMU_PERIC2),
|
|
SFR(QCH_CON_PERIC2_TOP0_QCH_USI06_USI, 0x3018, CMU_PERIC2),
|
|
SFR(QCH_CON_PERIC2_TOP0_QCH_USI07_USI, 0x3020, CMU_PERIC2),
|
|
SFR(QCH_CON_PERIC2_TOP0_QCH_USI08_USI, 0x3028, CMU_PERIC2),
|
|
SFR(QCH_CON_PERIC2_TOP0_QCH_USI08_I2C, 0x3024, CMU_PERIC2),
|
|
SFR(QCH_CON_PERIC2_TOP0_QCH_USI06_I2C, 0x3014, CMU_PERIC2),
|
|
SFR(QCH_CON_PERIC2_TOP0_QCH_USI07_I2C, 0x301c, CMU_PERIC2),
|
|
SFR(QCH_CON_PERIC2_TOP1_QCH_USI09_USI, 0x3030, CMU_PERIC2),
|
|
SFR(QCH_CON_PERIC2_TOP1_QCH_USI09_I2C, 0x303c, CMU_PERIC2),
|
|
SFR(QCH_CON_PERIC2_TOP1_QCH_USI10_USI, 0x3038, CMU_PERIC2),
|
|
SFR(QCH_CON_PERIC2_TOP1_QCH_USI10_I2C, 0x3034, CMU_PERIC2),
|
|
SFR(QCH_CON_SYSREG_PERIC2_QCH, 0x302c, CMU_PERIC2),
|
|
SFR(QCH_CON_BC_EMUL_QCH, 0x3054, CMU_PERIS),
|
|
SFR(QCH_CON_D_TZPC_PERIS_QCH, 0x3004, CMU_PERIS),
|
|
SFR(QCH_CON_GIC_QCH, 0x3008, CMU_PERIS),
|
|
SFR(QCH_CON_LHM_AST_ICC_CPUGIC_CLUSTER0_QCH, 0x3058, CMU_PERIS),
|
|
SFR(QCH_CON_LHM_AXI_P_PERIS_QCH, 0x300c, CMU_PERIS),
|
|
SFR(QCH_CON_LHM_AXI_P_PERISGIC_QCH, 0x3064, CMU_PERIS),
|
|
SFR(QCH_CON_LHS_AST_IRI_GICCPU_CLUSTER0_QCH, 0x3068, CMU_PERIS),
|
|
SFR(QCH_CON_MCT_QCH, 0x3010, CMU_PERIS),
|
|
SFR(DMYQCH_CON_OTP_QCH, 0x3018, CMU_PERIS),
|
|
SFR(QCH_CON_OTP_CON_BIRA_QCH, 0x3014, CMU_PERIS),
|
|
SFR(QCH_CON_OTP_CON_BISR_QCH, 0x3074, CMU_PERIS),
|
|
SFR(QCH_CON_OTP_CON_TOP_QCH, 0x301c, CMU_PERIS),
|
|
SFR(QCH_CON_PERIS_CMU_PERIS_QCH, 0x3020, CMU_PERIS),
|
|
SFR(QCH_CON_SYSREG_PERIS_QCH, 0x3024, CMU_PERIS),
|
|
SFR(QCH_CON_TMU_SUB_QCH, 0x3028, CMU_PERIS),
|
|
SFR(QCH_CON_TMU_TOP_QCH, 0x302c, CMU_PERIS),
|
|
SFR(QCH_CON_WDT0_QCH, 0x3030, CMU_PERIS),
|
|
SFR(QCH_CON_WDT1_QCH, 0x3034, CMU_PERIS),
|
|
SFR(DMYQCH_CON_BIS_S2D_QCH, 0x3000, CMU_S2D),
|
|
SFR(QCH_CON_LHM_AXI_G_SCAN2DRAM_QCH, 0x3008, CMU_S2D),
|
|
SFR(QCH_CON_S2D_CMU_S2D_QCH, 0x300c, CMU_S2D),
|
|
SFR(DMYQCH_CON_ADM_DAP_SSS_QCH, 0x3018, CMU_SSP),
|
|
SFR(QCH_CON_BAAW_SSS_QCH, 0x3034, CMU_SSP),
|
|
SFR(QCH_CON_D_TZPC_SSP_QCH, 0x3008, CMU_SSP),
|
|
SFR(QCH_CON_LHM_AXI_D_SSPCORE_QCH, 0x3038, CMU_SSP),
|
|
SFR(QCH_CON_LHM_AXI_P_SSP_QCH, 0x300c, CMU_SSP),
|
|
SFR(QCH_CON_LHS_ACEL_D_SSP_QCH, 0x303c, CMU_SSP),
|
|
SFR(QCH_CON_PPMU_SSP_QCH, 0x3040, CMU_SSP),
|
|
SFR(QCH_CON_QE_RTIC_QCH, 0x3044, CMU_SSP),
|
|
SFR(QCH_CON_QE_SSPCORE_QCH, 0x3048, CMU_SSP),
|
|
SFR(QCH_CON_QE_SSS_QCH, 0x304c, CMU_SSP),
|
|
SFR(QCH_CON_RTIC_QCH, 0x3050, CMU_SSP),
|
|
SFR(QCH_CON_SSP_CMU_SSP_QCH, 0x3010, CMU_SSP),
|
|
SFR(QCH_CON_SSS_QCH, 0x3054, CMU_SSP),
|
|
SFR(QCH_CON_SWEEPER_D_SSP_QCH, 0x3058, CMU_SSP),
|
|
SFR(QCH_CON_SYSMMU_RTIC_QCH, 0x305c, CMU_SSP),
|
|
SFR(QCH_CON_SYSREG_SSPCTRL_QCH, 0x3014, CMU_SSP),
|
|
SFR(QCH_CON_VGEN_LITE_RTIC_QCH, 0x3060, CMU_SSP),
|
|
SFR(QCH_CON_USS_SSPCORE_QCH, 0x3000, CMU_SSP),
|
|
SFR(DMYQCH_CON_ADD_TAA_QCH, 0x3024, CMU_TAA),
|
|
SFR(QCH_CON_BUSIF_ADD_TAA_QCH, 0x30c0, CMU_TAA),
|
|
SFR(QCH_CON_BUSIF_HPM_TAA_QCH, 0x30c4, CMU_TAA),
|
|
SFR(QCH_CON_D_TZPC_TAA_QCH, 0x3048, CMU_TAA),
|
|
SFR(QCH_CON_LHM_AST_OTF0_CSISTAA_QCH, 0x3050, CMU_TAA),
|
|
SFR(QCH_CON_LHM_AST_OTF1_CSISTAA_QCH, 0x3054, CMU_TAA),
|
|
SFR(QCH_CON_LHM_AST_OTF2_CSISTAA_QCH, 0x3058, CMU_TAA),
|
|
SFR(QCH_CON_LHM_AST_OTF3_CSISTAA_QCH, 0x30d0, CMU_TAA),
|
|
SFR(QCH_CON_LHM_AST_VO_MCFP1TAA_QCH, 0x30d8, CMU_TAA),
|
|
SFR(QCH_CON_LHM_AXI_P_TAA_QCH, 0x3060, CMU_TAA),
|
|
SFR(QCH_CON_LHS_AST_OTF_TAADNS_QCH, 0x3064, CMU_TAA),
|
|
SFR(QCH_CON_LHS_AST_SOTF0_TAACSIS_QCH, 0x306c, CMU_TAA),
|
|
SFR(QCH_CON_LHS_AST_SOTF1_TAACSIS_QCH, 0x3070, CMU_TAA),
|
|
SFR(QCH_CON_LHS_AST_SOTF2_TAACSIS_QCH, 0x3074, CMU_TAA),
|
|
SFR(QCH_CON_LHS_AST_SOTF3_TAACSIS_QCH, 0x30dc, CMU_TAA),
|
|
SFR(QCH_CON_LHS_AST_VO_TAAMCFP1_QCH, 0x30e4, CMU_TAA),
|
|
SFR(QCH_CON_LHS_AST_ZOTF0_TAACSIS_QCH, 0x307c, CMU_TAA),
|
|
SFR(QCH_CON_LHS_AST_ZOTF1_TAACSIS_QCH, 0x3080, CMU_TAA),
|
|
SFR(QCH_CON_LHS_AST_ZOTF2_TAACSIS_QCH, 0x3084, CMU_TAA),
|
|
SFR(QCH_CON_LHS_AST_ZOTF3_TAACSIS_QCH, 0x30e8, CMU_TAA),
|
|
SFR(QCH_CON_LHS_AXI_D_TAA_QCH, 0x3088, CMU_TAA),
|
|
SFR(QCH_CON_PPMU_TAA_QCH, 0x308c, CMU_TAA),
|
|
SFR(QCH_CON_SIPU_TAA_QCH, 0x3090, CMU_TAA),
|
|
SFR(QCH_CON_SIPU_TAA_QCH_C2_STAT, 0x3094, CMU_TAA),
|
|
SFR(QCH_CON_SIPU_TAA_QCH_C2_YDS, 0x30ec, CMU_TAA),
|
|
SFR(QCH_CON_SYSMMU_D_TAA_QCH_S1, 0x3098, CMU_TAA),
|
|
SFR(QCH_CON_SYSMMU_D_TAA_QCH_S2, 0x309c, CMU_TAA),
|
|
SFR(QCH_CON_SYSREG_TAA_QCH, 0x30a0, CMU_TAA),
|
|
SFR(QCH_CON_TAA_CMU_TAA_QCH, 0x304c, CMU_TAA),
|
|
SFR(QCH_CON_VGEN_LITE_TAA0_QCH, 0x30a4, CMU_TAA),
|
|
SFR(QCH_CON_VGEN_LITE_TAA1_QCH, 0x30f0, CMU_TAA),
|
|
SFR(DMYQCH_CON_ADD_VPC_QCH, 0x3008, CMU_VPC),
|
|
SFR(DMYQCH_CON_ADM_DAP_VPC_QCH, 0x3000, CMU_VPC),
|
|
SFR(QCH_CON_BUSIF_ADD_VPC_QCH, 0x30a8, CMU_VPC),
|
|
SFR(QCH_CON_BUSIF_HPM_VPC_QCH, 0x30ac, CMU_VPC),
|
|
SFR(QCH_CON_D_TZPC_VPC_QCH, 0x3098, CMU_VPC),
|
|
SFR(QCH_CON_HTU_VPC_QCH_PCLK, 0x30b4, CMU_VPC),
|
|
SFR(QCH_CON_HTU_VPC_QCH_CLK, 0x30b0, CMU_VPC),
|
|
SFR(QCH_CON_IP_VPC_QCH, 0x309c, CMU_VPC),
|
|
SFR(QCH_CON_LHM_AXI_D_VPD0VPC_CACHE_QCH, 0x30b8, CMU_VPC),
|
|
SFR(QCH_CON_LHM_AXI_D_VPD0VPC_SFR_QCH, 0x30bc, CMU_VPC),
|
|
SFR(QCH_CON_LHM_AXI_D_VPD1VPC_CACHE_QCH, 0x30c0, CMU_VPC),
|
|
SFR(QCH_CON_LHM_AXI_D_VPD1VPC_SFR_QCH, 0x30c4, CMU_VPC),
|
|
SFR(QCH_CON_LHM_AXI_P_VPC_QCH, 0x30d0, CMU_VPC),
|
|
SFR(QCH_CON_LHM_AXI_P_VPC_800_QCH, 0x30d4, CMU_VPC),
|
|
SFR(QCH_CON_LHS_ACEL_D0_VPC_QCH, 0x30d8, CMU_VPC),
|
|
SFR(QCH_CON_LHS_ACEL_D1_VPC_QCH, 0x30dc, CMU_VPC),
|
|
SFR(QCH_CON_LHS_ACEL_D2_VPC_QCH, 0x30e0, CMU_VPC),
|
|
SFR(QCH_CON_LHS_AXI_D_VPCVPD0_DMA_QCH, 0x30f4, CMU_VPC),
|
|
SFR(QCH_CON_LHS_AXI_D_VPCVPD0_SFR_QCH, 0x30f8, CMU_VPC),
|
|
SFR(QCH_CON_LHS_AXI_D_VPCVPD1_DMA_QCH, 0x30fc, CMU_VPC),
|
|
SFR(QCH_CON_LHS_AXI_D_VPCVPD1_SFR_QCH, 0x3100, CMU_VPC),
|
|
SFR(QCH_CON_LHS_AXI_P_VPCVPD0_QCH, 0x310c, CMU_VPC),
|
|
SFR(QCH_CON_LHS_AXI_P_VPCVPD1_QCH, 0x3110, CMU_VPC),
|
|
SFR(QCH_CON_LHS_AXI_P_VPC_200_QCH, 0x3114, CMU_VPC),
|
|
SFR(QCH_CON_PPMU_VPC0_QCH, 0x3118, CMU_VPC),
|
|
SFR(QCH_CON_PPMU_VPC1_QCH, 0x311c, CMU_VPC),
|
|
SFR(QCH_CON_PPMU_VPC2_QCH, 0x3120, CMU_VPC),
|
|
SFR(QCH_CON_SYSMMU_VPC0_QCH_S1, 0x3124, CMU_VPC),
|
|
SFR(QCH_CON_SYSMMU_VPC0_QCH_S2, 0x3128, CMU_VPC),
|
|
SFR(QCH_CON_SYSMMU_VPC1_QCH_S1, 0x312c, CMU_VPC),
|
|
SFR(QCH_CON_SYSMMU_VPC1_QCH_S2, 0x3130, CMU_VPC),
|
|
SFR(QCH_CON_SYSMMU_VPC2_QCH_S1, 0x3134, CMU_VPC),
|
|
SFR(QCH_CON_SYSMMU_VPC2_QCH_S2, 0x3138, CMU_VPC),
|
|
SFR(QCH_CON_SYSREG_VPC_QCH, 0x313c, CMU_VPC),
|
|
SFR(QCH_CON_VGEN_LITE_VPC_QCH, 0x3140, CMU_VPC),
|
|
SFR(QCH_CON_VPC_CMU_VPC_QCH, 0x3094, CMU_VPC),
|
|
SFR(QCH_CON_D_TZPC_VPD_QCH, 0x3028, CMU_VPD),
|
|
SFR(QCH_CON_IP_VPD_QCH, 0x302c, CMU_VPD),
|
|
SFR(QCH_CON_LHM_AXI_D_VPCVPD_DMA_QCH, 0x3030, CMU_VPD),
|
|
SFR(QCH_CON_LHM_AXI_D_VPCVPD_SFR_QCH, 0x3034, CMU_VPD),
|
|
SFR(QCH_CON_LHM_AXI_P_VPCVPD_QCH, 0x3040, CMU_VPD),
|
|
SFR(QCH_CON_LHS_AXI_D_VPDVPC_CACHE_QCH, 0x3044, CMU_VPD),
|
|
SFR(QCH_CON_LHS_AXI_D_VPDVPC_SFR_QCH, 0x3048, CMU_VPD),
|
|
SFR(QCH_CON_SYSREG_VPD_QCH, 0x304c, CMU_VPD),
|
|
SFR(QCH_CON_VPD_CMU_VPD_QCH, 0x3024, CMU_VPD),
|
|
SFR(QCH_CON_BAAW_C_VTS_QCH, 0x3100, CMU_VTS),
|
|
SFR(QCH_CON_BAAW_D_VTS_QCH, 0x305c, CMU_VTS),
|
|
SFR(QCH_CON_BUSIF_HPM_VTS_QCH, 0x310c, CMU_VTS),
|
|
SFR(QCH_CON_CORTEXM4INTEGRATION_QCH_CPU, 0x3060, CMU_VTS),
|
|
SFR(QCH_CON_DMAILBOX_TEST_QCH_ACLK, 0x311c, CMU_VTS),
|
|
SFR(QCH_CON_DMAILBOX_TEST_QCH_PCLK, 0x312c, CMU_VTS),
|
|
SFR(DMYQCH_CON_DMAILBOX_TEST_QCH_LIF, 0x3038, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_AHB0_QCH_PCLK, 0x3064, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_AHB1_QCH_PCLK, 0x3068, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_AHB2_QCH_PCLK, 0x306c, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_AHB3_QCH_PCLK, 0x3070, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_AHB4_QCH_PCLK, 0x3074, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_AHB5_QCH_PCLK, 0x3078, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_AUD0_QCH_PCLK, 0x307c, CMU_VTS),
|
|
SFR(DMYQCH_CON_DMIC_AUD0_QCH_DMIC, 0x3000, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_AUD1_QCH_PCLK, 0x3080, CMU_VTS),
|
|
SFR(DMYQCH_CON_DMIC_AUD1_QCH_DMIC, 0x3004, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_AUD2_QCH_PCLK, 0x3084, CMU_VTS),
|
|
SFR(DMYQCH_CON_DMIC_AUD2_QCH_DMIC, 0x3008, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_IF0_QCH_PCLK, 0x3088, CMU_VTS),
|
|
SFR(DMYQCH_CON_DMIC_IF0_QCH_DMIC, 0x300c, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_IF1_QCH_PCLK, 0x308c, CMU_VTS),
|
|
SFR(DMYQCH_CON_DMIC_IF1_QCH_DMIC, 0x3010, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_IF2_QCH_PCLK, 0x3090, CMU_VTS),
|
|
SFR(DMYQCH_CON_DMIC_IF2_QCH_DMIC, 0x3014, CMU_VTS),
|
|
SFR(QCH_CON_D_TZPC_VTS_QCH, 0x3094, CMU_VTS),
|
|
SFR(QCH_CON_GPIO_VTS_QCH, 0x3098, CMU_VTS),
|
|
SFR(QCH_CON_HWACG_SYS_DMIC0_QCH, 0x309c, CMU_VTS),
|
|
SFR(QCH_CON_HWACG_SYS_DMIC1_QCH, 0x30a0, CMU_VTS),
|
|
SFR(QCH_CON_HWACG_SYS_DMIC2_QCH, 0x30a4, CMU_VTS),
|
|
SFR(QCH_CON_HWACG_SYS_DMIC3_QCH, 0x30a8, CMU_VTS),
|
|
SFR(QCH_CON_HWACG_SYS_DMIC4_QCH, 0x30ac, CMU_VTS),
|
|
SFR(QCH_CON_HWACG_SYS_DMIC5_QCH, 0x30b0, CMU_VTS),
|
|
SFR(QCH_CON_HWACG_SYS_SERIAL_LIF_QCH, 0x3124, CMU_VTS),
|
|
SFR(QCH_CON_LHM_AXI_D_AUDVTS_QCH, 0x3110, CMU_VTS),
|
|
SFR(QCH_CON_LHM_AXI_LP_VTS_QCH, 0x30b8, CMU_VTS),
|
|
SFR(QCH_CON_LHM_AXI_P_VTS_QCH, 0x30bc, CMU_VTS),
|
|
SFR(QCH_CON_LHS_AXI_C_VTS_QCH, 0x3114, CMU_VTS),
|
|
SFR(QCH_CON_LHS_AXI_D_VTS_QCH, 0x30c4, CMU_VTS),
|
|
SFR(QCH_CON_MAILBOX_ABOX_VTS_QCH, 0x30c8, CMU_VTS),
|
|
SFR(QCH_CON_MAILBOX_APM_VTS1_QCH, 0x30cc, CMU_VTS),
|
|
SFR(QCH_CON_MAILBOX_AP_VTS_QCH, 0x3118, CMU_VTS),
|
|
SFR(QCH_CON_PDMA_VTS_QCH, 0x30d0, CMU_VTS),
|
|
SFR(QCH_CON_SERIAL_LIF_QCH_PCLK, 0x30d4, CMU_VTS),
|
|
SFR(DMYQCH_CON_SERIAL_LIF_QCH_LIF, 0x301c, CMU_VTS),
|
|
SFR(DMYQCH_CON_SERIAL_LIF_QCH_HCLK, 0x3058, CMU_VTS),
|
|
SFR(QCH_CON_SERIAL_LIF_DEBUG_US_QCH_PCLK, 0x3120, CMU_VTS),
|
|
SFR(DMYQCH_CON_SERIAL_LIF_DEBUG_US_QCH_LIF, 0x3018, CMU_VTS),
|
|
SFR(QCH_CON_SERIAL_LIF_DEBUG_VT_QCH_PCLK, 0x3128, CMU_VTS),
|
|
SFR(DMYQCH_CON_SERIAL_LIF_DEBUG_VT_QCH_LIF, 0x3050, CMU_VTS),
|
|
SFR(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0, 0x3020, CMU_VTS),
|
|
SFR(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0, 0x302c, CMU_VTS),
|
|
SFR(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1, 0x3024, CMU_VTS),
|
|
SFR(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1, 0x3030, CMU_VTS),
|
|
SFR(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD2, 0x3028, CMU_VTS),
|
|
SFR(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2, 0x3034, CMU_VTS),
|
|
SFR(QCH_CON_SWEEPER_D_VTS_QCH, 0x30d8, CMU_VTS),
|
|
SFR(QCH_CON_SYSREG_VTS_QCH, 0x30dc, CMU_VTS),
|
|
SFR(QCH_CON_TIMER_QCH, 0x30e8, CMU_VTS),
|
|
SFR(QCH_CON_TIMER1_QCH, 0x30e0, CMU_VTS),
|
|
SFR(QCH_CON_TIMER2_QCH, 0x30e4, CMU_VTS),
|
|
SFR(QCH_CON_VGEN_LITE_QCH, 0x30ec, CMU_VTS),
|
|
SFR(QCH_CON_VTS_CMU_VTS_QCH, 0x30f0, CMU_VTS),
|
|
SFR(QCH_CON_WDT_VTS_QCH, 0x30f4, CMU_VTS),
|
|
SFR(QCH_CON_D_TZPC_YUVPP_QCH, 0x3018, CMU_YUVPP),
|
|
SFR(QCH_CON_FRC_MC_QCH, 0x3054, CMU_YUVPP),
|
|
SFR(QCH_CON_LHM_AXI_P_YUVPP_QCH, 0x301c, CMU_YUVPP),
|
|
SFR(QCH_CON_LHS_AST_OTF_YUVPPMCSC_QCH, 0x305c, CMU_YUVPP),
|
|
SFR(QCH_CON_LHS_AXI_D_YUVPP_QCH, 0x3020, CMU_YUVPP),
|
|
SFR(QCH_CON_LHS_AXI_D_YUVPPMCSC_QCH, 0x3064, CMU_YUVPP),
|
|
SFR(QCH_CON_PPMU_YUVPP_QCH, 0x3024, CMU_YUVPP),
|
|
SFR(QCH_CON_QE_D0_YUVPP_QCH, 0x302c, CMU_YUVPP),
|
|
SFR(QCH_CON_QE_D10_YUVPP_QCH, 0x3058, CMU_YUVPP),
|
|
SFR(QCH_CON_QE_D11_YUVPP_QCH, 0x3060, CMU_YUVPP),
|
|
SFR(QCH_CON_QE_D1_YUVPP_QCH, 0x3068, CMU_YUVPP),
|
|
SFR(QCH_CON_QE_D2_YUVPP_QCH, 0x306c, CMU_YUVPP),
|
|
SFR(QCH_CON_QE_D3_YUVPP_QCH, 0x3070, CMU_YUVPP),
|
|
SFR(QCH_CON_QE_D4_YUVPP_QCH, 0x3074, CMU_YUVPP),
|
|
SFR(QCH_CON_QE_D5_YUVPP_QCH, 0x3078, CMU_YUVPP),
|
|
SFR(QCH_CON_QE_D6_YUVPP_QCH, 0x307c, CMU_YUVPP),
|
|
SFR(QCH_CON_QE_D7_YUVPP_QCH, 0x3080, CMU_YUVPP),
|
|
SFR(QCH_CON_QE_D8_YUVPP_QCH, 0x3084, CMU_YUVPP),
|
|
SFR(QCH_CON_QE_D9_YUVPP_QCH, 0x3088, CMU_YUVPP),
|
|
SFR(QCH_CON_SYSMMU_D_YUVPP_QCH_S1, 0x3038, CMU_YUVPP),
|
|
SFR(QCH_CON_SYSMMU_D_YUVPP_QCH_S2, 0x303c, CMU_YUVPP),
|
|
SFR(QCH_CON_SYSREG_YUVPP_QCH, 0x3040, CMU_YUVPP),
|
|
SFR(QCH_CON_VGEN_LITE_YUVPP0_QCH, 0x3044, CMU_YUVPP),
|
|
SFR(QCH_CON_VGEN_LITE_YUVPP1_QCH, 0x308c, CMU_YUVPP),
|
|
SFR(QCH_CON_VGEN_LITE_YUVPP2_QCH, 0x3094, CMU_YUVPP),
|
|
SFR(QCH_CON_YUVPP_CMU_YUVPP_QCH, 0x3048, CMU_YUVPP),
|
|
SFR(QCH_CON_YUVPP_TOP_QCH, 0x3034, CMU_YUVPP),
|
|
SFR(QCH_CON_YUVPP_TOP_QCH_C2COM, 0x3090, CMU_YUVPP),
|
|
SFR(ALIVE_CMU_ALIVE_CONTROLLER_OPTION, 0x800, CMU_ALIVE),
|
|
SFR(AUD_CMU_AUD_CONTROLLER_OPTION, 0x800, CMU_AUD),
|
|
SFR(BUS0_CMU_BUS0_CONTROLLER_OPTION, 0x800, CMU_BUS0),
|
|
SFR(BUS1_CMU_BUS1_CONTROLLER_OPTION, 0x800, CMU_BUS1),
|
|
SFR(BUS2_CMU_BUS2_CONTROLLER_OPTION, 0x800, CMU_BUS2),
|
|
SFR(CMGP_CMU_CMGP_CONTROLLER_OPTION, 0x800, CMU_CMGP),
|
|
SFR(CMU_CMU_TOP_CONTROLLER_OPTION, 0x800, CMU_TOP),
|
|
SFR(CORE_CMU_CORE_CONTROLLER_OPTION, 0x800, CMU_CORE),
|
|
SFR(CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION, 0x800, CMU_CPUCL0),
|
|
SFR(CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION, 0x800, CMU_CPUCL0_GLB),
|
|
SFR(CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION, 0x800, CMU_CPUCL1),
|
|
SFR(CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION, 0x800, CMU_CPUCL2),
|
|
SFR(CSIS_CMU_CSIS_CONTROLLER_OPTION, 0x800, CMU_CSIS),
|
|
SFR(DNS_CMU_DNS_CONTROLLER_OPTION, 0x800, CMU_DNS),
|
|
SFR(DPUB_CMU_DPUB_CONTROLLER_OPTION, 0x800, CMU_DPUB),
|
|
SFR(DPUF0_CMU_DPUF0_CONTROLLER_OPTION, 0x800, CMU_DPUF0),
|
|
SFR(DPUF1_CMU_DPUF1_CONTROLLER_OPTION, 0x800, CMU_DPUF1),
|
|
SFR(DSU_CMU_DSU_CONTROLLER_OPTION, 0x800, CMU_DSU),
|
|
SFR(G3D_CMU_G3D_CONTROLLER_OPTION, 0x800, CMU_G3D),
|
|
SFR(G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION, 0x804, CMU_G3D),
|
|
SFR(HSI0_CMU_HSI0_CONTROLLER_OPTION, 0x800, CMU_HSI0),
|
|
SFR(HSI1_CMU_HSI1_CONTROLLER_OPTION, 0x800, CMU_HSI1),
|
|
SFR(ITP_CMU_ITP_CONTROLLER_OPTION, 0x800, CMU_ITP),
|
|
SFR(LME_CMU_LME_CONTROLLER_OPTION, 0x800, CMU_LME),
|
|
SFR(M2M_CMU_M2M_CONTROLLER_OPTION, 0x800, CMU_M2M),
|
|
SFR(MCFP0_CMU_MCFP0_CONTROLLER_OPTION, 0x800, CMU_MCFP0),
|
|
SFR(MCFP1_CMU_MCFP1_CONTROLLER_OPTION, 0x800, CMU_MCFP1),
|
|
SFR(MCSC_CMU_MCSC_CONTROLLER_OPTION, 0x800, CMU_MCSC),
|
|
SFR(MFC0_CMU_MFC0_CONTROLLER_OPTION, 0x800, CMU_MFC0),
|
|
SFR(MFC1_CMU_MFC1_CONTROLLER_OPTION, 0x800, CMU_MFC1),
|
|
SFR(MIF_CMU_MIF_CONTROLLER_OPTION, 0x800, CMU_MIF),
|
|
SFR(NPU_CMU_NPU_CONTROLLER_OPTION, 0x800, CMU_NPU),
|
|
SFR(NPU01_CMU_NPU_CONTROLLER_OPTION, 0x800, CMU_NPU01),
|
|
SFR(NPU10_CMU_NPU_CONTROLLER_OPTION, 0x800, CMU_NPU10),
|
|
SFR(NPUS_CMU_NPUS_CONTROLLER_OPTION, 0x800, CMU_NPUS),
|
|
SFR(PERIC0_CMU_PERIC0_CONTROLLER_OPTION, 0x800, CMU_PERIC0),
|
|
SFR(PERIC1_CMU_PERIC1_CONTROLLER_OPTION, 0x800, CMU_PERIC1),
|
|
SFR(PERIC2_CMU_PERIC2_CONTROLLER_OPTION, 0x800, CMU_PERIC2),
|
|
SFR(PERIS_CMU_PERIS_CONTROLLER_OPTION, 0x800, CMU_PERIS),
|
|
SFR(S2D_CMU_S2D_CONTROLLER_OPTION, 0x800, CMU_S2D),
|
|
SFR(SSP_CMU_SSP_CONTROLLER_OPTION, 0x800, CMU_SSP),
|
|
SFR(SSP_EMBEDDED_CMU_SSP_CONTROLLER_OPTION, 0x804, CMU_SSP),
|
|
SFR(TAA_CMU_TAA_CONTROLLER_OPTION, 0x800, CMU_TAA),
|
|
SFR(VPC_CMU_VPC_CONTROLLER_OPTION, 0x800, CMU_VPC),
|
|
SFR(VPD_CMU_VPD_CONTROLLER_OPTION, 0x800, CMU_VPD),
|
|
SFR(VTS_CMU_VTS_CONTROLLER_OPTION, 0x800, CMU_VTS),
|
|
SFR(YUVPP_CMU_YUVPP_CONTROLLER_OPTION, 0x800, CMU_YUVPP),
|
|
};
|
|
|
|
unsigned int cmucal_sfr_access_size = 11613;
|
|
struct sfr_access cmucal_sfr_access_list[] = {
|
|
SFR_ACCESS(OSC_LOCKTIME_RCO_400_OSC_LOCK_TIME, 0, 8, OSC_LOCKTIME_RCO_400),
|
|
SFR_ACCESS(OSC_CON0_RCO_400_MUX_BUSY, 16, 1, OSC_CON0_RCO_400),
|
|
SFR_ACCESS(OSC_CON0_RCO_400_MUX_SEL, 4, 1, OSC_CON0_RCO_400),
|
|
SFR_ACCESS(OSC_CON1_RCO_400_ENABLE_AUTOMATIC_CLKGATING, 28, 1, OSC_CON1_RCO_400),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_AUD0_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_AUD0),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD0_ENABLE, 31, 1, PLL_CON3_PLL_AUD0),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD0_STABLE, 29, 1, PLL_CON3_PLL_AUD0),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD0_DIV_P, 8, 6, PLL_CON3_PLL_AUD0),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD0_DIV_M, 16, 10, PLL_CON3_PLL_AUD0),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD0_DIV_S, 0, 3, PLL_CON3_PLL_AUD0),
|
|
SFR_ACCESS(PLL_CON8_PLL_AUD0_DIV_F, 0, 32, PLL_CON8_PLL_AUD0),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_AUD1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_AUD1),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD1_ENABLE, 31, 1, PLL_CON3_PLL_AUD1),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD1_STABLE, 29, 1, PLL_CON3_PLL_AUD1),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD1_DIV_P, 8, 6, PLL_CON3_PLL_AUD1),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD1_DIV_M, 16, 10, PLL_CON3_PLL_AUD1),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD1_DIV_S, 0, 3, PLL_CON3_PLL_AUD1),
|
|
SFR_ACCESS(PLL_CON8_PLL_AUD1_DIV_F, 0, 32, PLL_CON8_PLL_AUD1),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D_ENABLE, 31, 1, PLL_CON3_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D_STABLE, 29, 1, PLL_CON3_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D_DIV_P, 8, 6, PLL_CON3_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D_DIV_M, 16, 10, PLL_CON3_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D_DIV_S, 0, 3, PLL_CON3_PLL_G3D),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_MMC_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_ENABLE, 31, 1, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_STABLE, 29, 1, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_DIV_P, 8, 6, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_DIV_M, 16, 10, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_DIV_S, 0, 3, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON8_PLL_MMC_DIV_F, 0, 32, PLL_CON8_PLL_MMC),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED0_ENABLE, 31, 1, PLL_CON3_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED0_STABLE, 29, 1, PLL_CON3_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED0_DIV_P, 8, 6, PLL_CON3_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED0_DIV_M, 16, 10, PLL_CON3_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED0_DIV_S, 0, 3, PLL_CON3_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED1_ENABLE, 31, 1, PLL_CON3_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED1_STABLE, 29, 1, PLL_CON3_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED1_DIV_P, 8, 6, PLL_CON3_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED1_DIV_M, 16, 10, PLL_CON3_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED1_DIV_S, 0, 3, PLL_CON3_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED2_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED2_ENABLE, 31, 1, PLL_CON3_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED2_STABLE, 29, 1, PLL_CON3_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED2_DIV_P, 8, 6, PLL_CON3_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED2_DIV_M, 16, 10, PLL_CON3_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED2_DIV_S, 0, 3, PLL_CON3_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED3_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED3),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED3_ENABLE, 31, 1, PLL_CON3_PLL_SHARED3),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED3_STABLE, 29, 1, PLL_CON3_PLL_SHARED3),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED3_DIV_P, 8, 6, PLL_CON3_PLL_SHARED3),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED3_DIV_M, 16, 10, PLL_CON3_PLL_SHARED3),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED3_DIV_S, 0, 3, PLL_CON3_PLL_SHARED3),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED4_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED4),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED4_ENABLE, 31, 1, PLL_CON3_PLL_SHARED4),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED4_STABLE, 29, 1, PLL_CON3_PLL_SHARED4),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED4_DIV_P, 8, 6, PLL_CON3_PLL_SHARED4),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED4_DIV_M, 16, 10, PLL_CON3_PLL_SHARED4),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED4_DIV_S, 0, 3, PLL_CON3_PLL_SHARED4),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED_MIF_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED_MIF),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED_MIF_ENABLE, 31, 1, PLL_CON3_PLL_SHARED_MIF),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED_MIF_STABLE, 29, 1, PLL_CON3_PLL_SHARED_MIF),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED_MIF_DIV_P, 8, 6, PLL_CON3_PLL_SHARED_MIF),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED_MIF_DIV_M, 16, 10, PLL_CON3_PLL_SHARED_MIF),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED_MIF_DIV_S, 0, 3, PLL_CON3_PLL_SHARED_MIF),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL0_ENABLE, 31, 1, PLL_CON3_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL0_STABLE, 29, 1, PLL_CON3_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL0_DIV_P, 8, 6, PLL_CON3_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL0_DIV_M, 16, 10, PLL_CON3_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL0_DIV_S, 0, 3, PLL_CON3_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL1_ENABLE, 31, 1, PLL_CON3_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL1_STABLE, 29, 1, PLL_CON3_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL1_DIV_P, 8, 6, PLL_CON3_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL1_DIV_M, 16, 10, PLL_CON3_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL1_DIV_S, 0, 3, PLL_CON3_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL2_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_CPUCL2),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL2_ENABLE, 31, 1, PLL_CON3_PLL_CPUCL2),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL2_STABLE, 29, 1, PLL_CON3_PLL_CPUCL2),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL2_DIV_P, 8, 6, PLL_CON3_PLL_CPUCL2),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL2_DIV_M, 16, 10, PLL_CON3_PLL_CPUCL2),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL2_DIV_S, 0, 3, PLL_CON3_PLL_CPUCL2),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_DSU_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON3_PLL_DSU_ENABLE, 31, 1, PLL_CON3_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON3_PLL_DSU_STABLE, 29, 1, PLL_CON3_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON3_PLL_DSU_DIV_P, 8, 6, PLL_CON3_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON3_PLL_DSU_DIV_M, 16, 10, PLL_CON3_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON3_PLL_DSU_DIV_S, 0, 3, PLL_CON3_PLL_DSU),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_MAIN_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MIF_MAIN),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_MAIN_ENABLE, 31, 1, PLL_CON3_PLL_MIF_MAIN),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_MAIN_STABLE, 29, 1, PLL_CON3_PLL_MIF_MAIN),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_MAIN_DIV_P, 8, 6, PLL_CON3_PLL_MIF_MAIN),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_MAIN_DIV_M, 16, 10, PLL_CON3_PLL_MIF_MAIN),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_MAIN_DIV_S, 0, 3, PLL_CON3_PLL_MIF_MAIN),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_SUB_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MIF_SUB),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_SUB_ENABLE, 31, 1, PLL_CON3_PLL_MIF_SUB),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_SUB_STABLE, 29, 1, PLL_CON3_PLL_MIF_SUB),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_SUB_DIV_P, 8, 6, PLL_CON3_PLL_MIF_SUB),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_SUB_DIV_M, 16, 10, PLL_CON3_PLL_MIF_SUB),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_SUB_DIV_S, 0, 3, PLL_CON3_PLL_MIF_SUB),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_S2D_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_ENABLE, 31, 1, PLL_CON3_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_STABLE, 29, 1, PLL_CON3_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_DIV_P, 8, 6, PLL_CON3_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_DIV_M, 16, 10, PLL_CON3_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_DIV_S, 0, 3, PLL_CON3_PLL_MIF_S2D),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_ADC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CMGP_ADC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_ADC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CMGP_ADC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CMGP_ADC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF3_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF3_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF2_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF1_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF0_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_DSIF_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_DSIF_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF4_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF4_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF5_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF5_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF6_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF6_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CNT_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_CNT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CNT_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_CNT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CNT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_CNT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_PCMC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_PCMC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_PCMC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_BUS0_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_BUS0_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_BUS0_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_BUS0_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_BUS0_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_BUS0_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_BUS1_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_BUS1_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_BUS1_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_BUS1_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_BUS1_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_BUS1_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_BUS2_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_BUS2_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_BUS2_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_BUS2_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_BUS2_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_BUS2_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI3_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI3_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_MUX_CLK_CMGP_ADC_SELECT, 0, 1, CLK_CON_MUX_CLK_CMGP_ADC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLK_CMGP_ADC_BUSY, 16, 1, CLK_CON_MUX_CLK_CMGP_ADC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLK_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLK_CMGP_ADC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C3_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C3_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I3C_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_I3C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I3C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_I3C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I3C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_I3C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VPD_BUS_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_VPD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VPD_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_VPD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VPD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_VPD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ITP_BUS_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_ITP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ITP_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_ITP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ITP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_ITP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HPM_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HPM_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NPU_BUS_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_NPU_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NPU_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_NPU_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NPU_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_NPU_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DPUF0_BUS_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_DPUF0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DPUF0_BUS_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_DPUF0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DPUF0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_DPUF0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUF0_ALT_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DPUF0_ALT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUF0_ALT_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DPUF0_ALT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUF0_ALT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DPUF0_ALT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_YUVPP_BUS_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_YUVPP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_YUVPP_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_YUVPP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_YUVPP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_YUVPP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUF0_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DPUF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUF0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DPUF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DPUF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_CSIS_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CSIS_CSIS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_CSIS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_CSIS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_CSIS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_CSIS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCFP0_BUS_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MCFP0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCFP0_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MCFP0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCFP0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MCFP0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DNS_BUS_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_DNS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DNS_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DNS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DNS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DNS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SSP_SSPCORE_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_SSP_SSPCORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SSP_SSPCORE_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_SSP_SSPCORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SSP_SSPCORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_SSP_SSPCORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_M2M_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_M2M_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_M2M_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_M2M_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_M2M_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_M2M_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DPUB_BUS_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_DPUB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DPUB_BUS_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_DPUB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DPUB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_DPUB_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUB_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DPUB),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUB_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DPUB),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DPUB),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUS1_SBIC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_BUS1_SBIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUS1_SBIC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_BUS1_SBIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUS1_SBIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_BUS1_SBIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_LME_BUS_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_LME_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_LME_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_LME_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_LME_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_LME_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCFP1_MCFP1_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MCFP1_MCFP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCFP1_MCFP1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MCFP1_MCFP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCFP1_MCFP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MCFP1_MCFP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VPC_BUS_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_VPC_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VPC_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_VPC_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VPC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_VPC_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCFP1_ORBMCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MCFP1_ORBMCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCFP1_ORBMCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MCFP1_ORBMCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCFP1_ORBMCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MCFP1_ORBMCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_PDP_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CSIS_PDP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_PDP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_PDP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_PDP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_PDP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_UCPU_CLK_SELECT, 0, 1, CLK_CON_MUX_MUX_CP_UCPU_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_UCPU_CLK_BUSY, 16, 1, CLK_CON_MUX_MUX_CP_UCPU_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_UCPU_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CP_UCPU_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_LCPU_CLK_SELECT, 0, 1, CLK_CON_MUX_MUX_CP_LCPU_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_LCPU_CLK_BUSY, 16, 1, CLK_CON_MUX_MUX_CP_LCPU_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_LCPU_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CP_LCPU_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_HISPEEDY_CLK_SELECT, 0, 1, CLK_CON_MUX_MUX_CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_HISPEEDY_CLK_BUSY, 16, 1, CLK_CON_MUX_MUX_CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SSP_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_SSP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SSP_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_SSP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SSP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_SSP_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_YUVPP_FRC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_YUVPP_FRC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_YUVPP_FRC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_YUVPP_FRC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_YUVPP_FRC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_YUVPP_FRC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_BUS_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_G3D_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_G3D_SHADER_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_G3D_SHADER),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_G3D_SHADER_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_G3D_SHADER),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_G3D_SHADER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_G3D_SHADER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC2_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC2_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC2_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC2_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC2_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC2_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUF1_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DPUF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUF1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DPUF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DPUF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUF1_ALT_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DPUF1_ALT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUF1_ALT_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DPUF1_ALT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUF1_ALT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DPUF1_ALT),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DPUF1_BUS_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_DPUF1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DPUF1_BUS_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_DPUF1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DPUF1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_DPUF1_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CORE_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CORE_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CORE_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CORE_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CORE_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CORE_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL0_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CPUCL0_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL0_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CPUCL0_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CPUCL0_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL0_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_DELAY_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_DELAY),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_DELAY_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_DELAY),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_DELAY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_DELAY),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_PLL_CPUCL0_DELAY_SELECT, 0, 2, CLK_CON_MUX_MUX_PLL_CPUCL0_DELAY),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_PLL_CPUCL0_DELAY_BUSY, 16, 1, CLK_CON_MUX_MUX_PLL_CPUCL0_DELAY),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_PLL_CPUCL0_DELAY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_PLL_CPUCL0_DELAY),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_CORE_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL1_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_CORE_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL1_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CPUCL1_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL1_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CPUCL1_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CPUCL1_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL2_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CPUCL2_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL2_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CPUCL2_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL2_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CPUCL2_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_CORE_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL2_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_CORE_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_DSU_CLUSTER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_DSU_CLUSTER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_DSU_CLUSTER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_DSU_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_DSU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_DSU_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_DSU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_DSU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_DSU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_PLL_DSU_DELAY_SELECT, 0, 2, CLK_CON_MUX_MUX_PLL_DSU_DELAY),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_PLL_DSU_DELAY_BUSY, 16, 1, CLK_CON_MUX_MUX_PLL_DSU_DELAY),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_PLL_DSU_DELAY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_PLL_DSU_DELAY),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_DELAY_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_DELAY),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_DELAY_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_DELAY),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_DELAY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_DELAY),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_G3D_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_G3D_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_G3D_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_HSI0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_HSI0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_HSI0_BUS),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_MIF_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_MIF_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_MIF_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI14_USI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC0_USI14_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI14_USI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI14_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI14_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI14_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI15_USI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC0_USI15_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI15_USI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI15_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI15_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI15_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_UART_DBG_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC0_UART_DBG),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_UART_DBG_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC0_UART_DBG),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC0_UART_DBG),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI13_USI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC0_USI13_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI13_USI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI13_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI13_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI13_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI18_USI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC1_USI18_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI18_USI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI18_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI18_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI18_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI07_USI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC2_USI07_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI07_USI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI07_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI07_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI07_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI_I2C_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC2_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI_I2C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI06_USI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC2_USI06_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI06_USI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI06_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI06_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI06_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI08_USI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC2_USI08_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI08_USI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI08_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI08_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI08_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI09_USI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC2_USI09_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI09_USI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI09_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI09_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI09_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI10_USI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC2_USI10_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI10_USI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI10_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI10_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI10_USI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_S2D_CORE_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_S2D_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_S2D_CORE_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_S2D_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_S2D_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_S2D_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_DMIC_AUD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_VTS_DMIC_AUD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_DMIC_AUD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_VTS_DMIC_AUD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_DMIC_AUD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_VTS_DMIC_AUD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_DMIC_AHB_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_VTS_DMIC_AHB),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_DMIC_AHB_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_VTS_DMIC_AHB),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_DMIC_AHB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_VTS_DMIC_AHB),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_CORE_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_CORE_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_VTS_SERIAL_LIF_CORE),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_ALIVE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_ALIVE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLK_RCO_ALIVE_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLK_RCO_ALIVE_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLK_RCO_ALIVE_USER_BUSY, 16, 1, PLL_CON0_MUX_CLK_RCO_ALIVE_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLK_RCO_ALIVE_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLK_RCO_ALIVE_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUD_CPU_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_AUD_CPU_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_AUD_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_AUD_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUD_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_AUD_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CP_PCMC_CLK_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CP_PCMC_CLK_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CP_PCMC_CLK_USER_BUSY, 16, 1, PLL_CON0_MUX_CP_PCMC_CLK_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CP_PCMC_CLK_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CP_PCMC_CLK_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUS0_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_BUS0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUS0_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_BUS0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_BUS0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_BUS0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_BUS1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_BUS1_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUS1_SBIC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_BUS1_SBIC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUS1_SBIC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_BUS1_SBIC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_BUS1_SBIC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_BUS1_SBIC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUS2_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_BUS2_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUS2_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_BUS2_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_BUS2_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_BUS2_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CMGP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CMGP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CMGP_PERI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CMGP_PERI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CMGP_ADC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CMGP_ADC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CMGP_ADC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CMGP_ADC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CMGP_ADC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CMGP_ADC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CORE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CORE_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_BUSP_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CSIS_CSIS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CSIS_CSIS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CSIS_CSIS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CSIS_CSIS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CSIS_CSIS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CSIS_CSIS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CSIS_OIS_MCU_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CSIS_OIS_MCU_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CSIS_PDP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CSIS_PDP_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CSIS_PDP_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CSIS_PDP_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CSIS_PDP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CSIS_PDP_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DNS_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DNS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DNS_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_DNS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DNS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_DNS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPUB_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DPUB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPUB_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_DPUB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DPUB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_DPUB_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPUF0_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DPUF0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPUF0_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_DPUF0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DPUF0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_DPUF0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPUF1_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DPUF1_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPUF1_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_DPUF1_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DPUF1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_DPUF1_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G3D_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_G3D_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G3D_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_G3D_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_SHADER_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_SHADER_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_SHADER_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_SHADER_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_SHADER_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_SHADER_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_SHADER_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G3D_SHADER_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_SHADER_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_G3D_SHADER_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G3D_SHADER_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_G3D_SHADER_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_BUSD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKAUD_HSI0_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKAUD_HSI0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKAUD_HSI0_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKAUD_HSI0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKAUD_HSI0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKAUD_HSI0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKAUD_HSI0_USB31DRD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKAUD_HSI0_USB31DRD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKAUD_HSI0_USB31DRD_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKAUD_HSI0_USB31DRD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKAUD_HSI0_USB31DRD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKAUD_HSI0_USB31DRD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLK_USB20PHY_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLK_USB20PHY_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLK_USB20PHY_USER_BUSY, 16, 1, PLL_CON0_MUX_CLK_USB20PHY_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLK_USB20PHY_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLK_USB20PHY_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI1_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI1_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI1_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI1_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI1_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI1_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI1_MMC_CARD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI1_UFS_EMBD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI1_UFS_EMBD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI1_UFS_EMBD_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI1_UFS_EMBD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI1_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI1_UFS_EMBD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ITP_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_ITP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ITP_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_ITP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_ITP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_ITP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_LME_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_LME_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_LME_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_LME_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_LME_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_LME_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_M2M_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_M2M_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_M2M_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_M2M_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_M2M_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_M2M_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCFP0_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MCFP0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCFP0_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MCFP0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCFP0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MCFP0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCFP1_MCFP1_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MCFP1_MCFP1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCFP1_MCFP1_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MCFP1_MCFP1_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCFP1_MCFP1_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MCFP1_MCFP1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCFP1_ORBMCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MCFP1_ORBMCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCFP1_ORBMCH_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MCFP1_ORBMCH_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCFP1_ORBMCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MCFP1_ORBMCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCSC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MCSC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCSC_GDC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MCSC_GDC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MFC0_MFC0_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MFC0_MFC0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MFC0_WFD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MFC0_WFD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MFC1_MFC1_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MFC1_MFC1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MIF_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MIF_BUSP_USER),
|
|
SFR_ACCESS(PLL_CON0_CLKMUX_MIF_DDRPHY2X_MUX_SEL, 4, 2, PLL_CON0_CLKMUX_MIF_DDRPHY2X),
|
|
SFR_ACCESS(PLL_CON0_CLKMUX_MIF_DDRPHY2X_BUSY, 16, 1, PLL_CON0_CLKMUX_MIF_DDRPHY2X),
|
|
SFR_ACCESS(PLL_CON1_CLKMUX_MIF_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_CLKMUX_MIF_DDRPHY2X),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NPU_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_NPU_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NPU_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_NPU_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NPU_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_NPU_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NPU01_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_NPU01_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NPU01_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_NPU01_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NPU01_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_NPU01_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NPU10_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_NPU10_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NPU10_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_NPU10_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NPU10_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_NPU10_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NPUS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_NPUS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_IP0_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC0_IP0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_IP1_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC0_IP1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_IP0_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC1_IP0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_IP1_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC1_IP1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC2_IP0_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC2_IP0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC2_IP1_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC2_IP1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC2_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC2_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC2_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC2_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC2_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC2_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_MUX_SEL, 4, 2, PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D),
|
|
SFR_ACCESS(PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_BUSY, 16, 1, PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D),
|
|
SFR_ACCESS(PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_SSP_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_SSP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_SSP_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_SSP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_SSP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_SSP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_SSP_SSPCORE_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_SSP_SSPCORE_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_SSP_SSPCORE_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_SSP_SSPCORE_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_SSP_SSPCORE_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_SSP_SSPCORE_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_TAA_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_TAA_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_TAA_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_TAA_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TAA_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_TAA_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VPC_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_VPC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VPC_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_VPC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_VPC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_VPC_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VPD_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_VPD_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VPD_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_VPD_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_VPD_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_VPD_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_VTS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_VTS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_VTS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_VTS_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKAUD_VTS_DMIC0_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKAUD_VTS_DMIC0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKAUD_VTS_DMIC0_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKAUD_VTS_DMIC0_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKAUD_VTS_DMIC0_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKAUD_VTS_DMIC0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKAUD_VTS_DMIC1_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKAUD_VTS_DMIC1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKAUD_VTS_DMIC1_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKAUD_VTS_DMIC1_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKAUD_VTS_DMIC1_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKAUD_VTS_DMIC1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_VTS_DMIC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_VTS_DMIC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLK_RCO_VTS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLK_RCO_VTS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLK_RCO_VTS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLK_RCO_VTS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLK_RCO_VTS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLK_RCO_VTS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_YUVPP_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_YUVPP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_YUVPP_BUS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_YUVPP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_YUVPP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_YUVPP_BUS_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_YUVPP_FRC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_YUVPP_FRC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_YUVPP_FRC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_YUVPP_FRC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_YUVPP_FRC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_YUVPP_FRC_USER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_BUSY, 16, 1, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_STR_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_STR),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_STR_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_CORE_STR),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_CORE_STR_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_CORE_STR),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_CORE_STR_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_CORE_STR),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_CORE_STR_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_CORE_STR),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_CORE_STR_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_CORE_STR),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_STR_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_STR),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_STR_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_DSU_CLUSTER_STR),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_SHADER_STR_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_G3D_SHADER_STR),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_SHADER_STR_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_G3D_SHADER_STR),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIS_GIC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIS_GIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIS_GIC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VTS_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VTS_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_PERI_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_PERI_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_ADC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CMGP_ADC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_ADC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CMGP_ADC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CMGP_ADC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_AUDIF_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_AUDIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_AUDIF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_AUDIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_AUDIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DSIF_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DSIF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF0_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF1_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF2_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF3_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF3_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUSP_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_AUD_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CNT_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_CNT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CNT_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CNT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CNT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CNT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF4_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF4_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF5_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF5_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_SCLK_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_SCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_SCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_SCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_SCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DMIC1_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_AUD_DMIC1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DMIC1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_DMIC1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DMIC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_DMIC1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF6_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF6_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_VTS_DMIC0_DIVRATIO, 0, 5, CLK_CON_DIV_CLKAUD_VTS_DMIC0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_VTS_DMIC0_BUSY, 16, 1, CLK_CON_DIV_CLKAUD_VTS_DMIC0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_VTS_DMIC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKAUD_VTS_DMIC0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_HSI0_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKAUD_HSI0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_HSI0_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKAUD_HSI0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_HSI0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKAUD_HSI0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_HSI0_USB31DRD_DIVRATIO, 0, 6, CLK_CON_DIV_CLKAUD_HSI0_USB31DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_HSI0_USB31DRD_BUSY, 16, 1, CLK_CON_DIV_CLKAUD_HSI0_USB31DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKAUD_HSI0_USB31DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_PCMC_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_PCMC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_PCMC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUS0_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_BUS0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUS0_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_BUS0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUS0_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_BUS0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUS1_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_BUS1_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUS1_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_BUS1_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUS1_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_BUS1_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUS2_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_BUS2_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUS2_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_BUS2_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUS2_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_BUS2_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C0_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_I2C0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_I2C0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_I2C0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI1_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI0_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI2_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI3_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI3_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C1_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_I2C1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_I2C1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_I2C1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C2_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_I2C2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_I2C2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_I2C2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C3_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_I2C3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C3_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_I2C3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_I2C3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I3C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_I3C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I3C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_I3C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I3C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_I3C),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ALIVE_BUS_DIVRATIO, 0, 2, CLK_CON_DIV_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ALIVE_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIS_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIS_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUF0_ALT_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_DPUF0_ALT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUF0_ALT_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_DPUF0_ALT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUF0_ALT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_DPUF0_ALT),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC0_MFC0_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MFC0_MFC0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC0_MFC0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MFC0_MFC0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MFC0_MFC0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VPD_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_VPD_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VPD_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_VPD_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VPD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_VPD_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_TAA_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_TAA_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ITP_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_ITP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ITP_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_ITP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ITP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_ITP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_CPU_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_CPU_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HPM_DIVRATIO, 0, 2, CLK_CON_DIV_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HPM_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_NPU_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_NPU_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_NPU_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_NPU_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_NPU_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_NPU_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC0_WFD_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MFC0_WFD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC0_WFD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MFC0_WFD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC0_WFD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MFC0_WFD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_BUSP_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_BUSP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_IP0_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC0_IP0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_IP0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC0_IP0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_IP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC0_IP0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_IP0_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_IP0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_IP0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_IP0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_IP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_IP0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUF0_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_DPUF0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUF0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_DPUF0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_DPUF0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_HSI0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_YUVPP_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_YUVPP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_YUVPP_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_YUVPP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_YUVPP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_YUVPP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK4_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK4_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUS1_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_BUS1_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUS1_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_BUS1_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_BUS1_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_CSIS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CSIS_CSIS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_CSIS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CSIS_CSIS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_CSIS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CSIS_CSIS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCFP0_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MCFP0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCFP0_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MCFP0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCFP0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MCFP0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DNS_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DNS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DNS_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DNS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DNS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DNS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_NPUS_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_NPUS_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_HSI1_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI1_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI1_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_GDC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_GDC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_SSP_SSPCORE_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_SSP_SSPCORE),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_SSP_SSPCORE_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_SSP_SSPCORE),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_SSP_SSPCORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_SSP_SSPCORE),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK5_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK5_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_M2M_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_M2M_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_M2M_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_M2M_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_M2M_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_M2M_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUB_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_DPUB),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUB_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_DPUB),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_DPUB),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC1_MFC1_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MFC1_MFC1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC1_MFC1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MFC1_MFC1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MFC1_MFC1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUS1_SBIC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_BUS1_SBIC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUS1_SBIC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_BUS1_SBIC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUS1_SBIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_BUS1_SBIC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_LME_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_LME_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_LME_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_LME_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_LME_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_LME_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCFP1_MCFP1_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MCFP1_MCFP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCFP1_MCFP1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MCFP1_MCFP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCFP1_MCFP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MCFP1_MCFP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VPC_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_VPC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VPC_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_VPC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VPC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_VPC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUS0_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_BUS0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUS0_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_BUS0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUS0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_BUS0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUS2_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_BUS2_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUS2_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_BUS2_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUS2_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_BUS2_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_HSI0_USB31DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI0_USB31DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI0_USB31DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_DPGTC_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_HSI0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_DPGTC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCFP1_ORBMCH_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MCFP1_ORBMCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCFP1_ORBMCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MCFP1_ORBMCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCFP1_ORBMCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MCFP1_ORBMCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_PDP_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CSIS_PDP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_PDP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CSIS_PDP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_PDP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CSIS_PDP),
|
|
SFR_ACCESS(CLK_CON_DIV_CP_SHARED0_CLK_DIVRATIO, 0, 3, CLK_CON_DIV_CP_SHARED0_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CP_SHARED0_CLK_BUSY, 16, 1, CLK_CON_DIV_CP_SHARED0_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CP_SHARED0_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CP_SHARED1_CLK_DIVRATIO, 0, 3, CLK_CON_DIV_CP_SHARED1_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CP_SHARED1_CLK_BUSY, 16, 1, CLK_CON_DIV_CP_SHARED1_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CP_SHARED1_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CP_SHARED1_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CP_SHARED2_CLK_DIVRATIO, 0, 3, CLK_CON_DIV_CP_SHARED2_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CP_SHARED2_CLK_BUSY, 16, 1, CLK_CON_DIV_CP_SHARED2_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CP_SHARED2_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CP_HISPEEDY_CLK_DIVRATIO, 0, 4, CLK_CON_DIV_CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CP_HISPEEDY_CLK_BUSY, 16, 1, CLK_CON_DIV_CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_IP1_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC0_IP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_IP1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC0_IP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_IP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC0_IP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_IP1_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_IP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_IP1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_IP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_IP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_IP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_SSP_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_SSP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_SSP_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_SSP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_SSP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_SSP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_YUVPP_FRC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_YUVPP_FRC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_YUVPP_FRC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_YUVPP_FRC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_YUVPP_FRC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_YUVPP_FRC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_G3D_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_G3D_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_G3D_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC2_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC2_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC2_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC2_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC2_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC2_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC2_IP0_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC2_IP0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC2_IP0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC2_IP0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC2_IP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC2_IP0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC2_IP1_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC2_IP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC2_IP1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC2_IP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC2_IP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC2_IP1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUF1_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_DPUF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUF1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_DPUF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_DPUF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUF1_ALT_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_DPUF1_ALT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUF1_ALT_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_DPUF1_ALT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUF1_ALT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_DPUF1_ALT),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DSU_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DSU_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD_DIVRATIO, 0, 9, CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CORE_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CORE_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CORE_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CORE_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CORE_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CORE_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_CORE_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_CORE_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_CORE_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_CORE_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL1_HTU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_HTU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_HTU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL2_SHORTSTOP_CORE_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL2_SHORTSTOP_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL2_SHORTSTOP_CORE_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL2_SHORTSTOP_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL2_SHORTSTOP_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL2_SHORTSTOP_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL2_HTU_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL2_HTU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL2_HTU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL2_HTU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL2_HTU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL2_HTU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CSIS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CSIS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CSIS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DNS_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DNS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DNS_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DNS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DNS_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DNS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPUB_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DPUB_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPUB_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DPUB_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPUB_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DPUB_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPUF0_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DPUF0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPUF0_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DPUF0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPUF0_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DPUF0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPUF1_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DPUF1_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPUF1_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DPUF1_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPUF1_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DPUF1_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_CLUSTER_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_CLUSTER),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_CLUSTER_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_CLUSTER),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_CLUSTER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_CLUSTER),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_PCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER_PCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_PCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_PCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_PCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_PERIPHCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER_PERIPHCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_PERIPHCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_PERIPHCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_PERIPHCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_BCLK_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_BCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_BCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_BCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_BCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_BCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_G3D_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ITP_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_ITP_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ITP_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ITP_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ITP_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ITP_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_LME_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_LME_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_LME_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_LME_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_LME_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_LME_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_M2M_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_M2M_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_M2M_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_M2M_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_M2M_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_M2M_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCFP0_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MCFP0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCFP0_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MCFP0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCFP0_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MCFP0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCFP1_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MCFP1_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCFP1_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MCFP1_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCFP1_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MCFP1_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MCSC_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MCSC_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MCSC_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC0_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MFC0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC0_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MFC0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC0_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MFC0_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC1_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MFC1_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC1_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MFC1_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC1_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MFC1_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_NPU_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NPU_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NPU_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU01_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_NPU01_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU01_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NPU01_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU01_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NPU01_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU10_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_NPU10_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU10_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NPU10_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU10_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NPU10_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPUS_BUSP_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_NPUS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPUS_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NPUS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPUS_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NPUS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_UART_DBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI13_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI15_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI18_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI08_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC2_USI08_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI08_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI08_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI08_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI08_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC2_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI06_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC2_USI06_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI06_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI06_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI06_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI06_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI07_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC2_USI07_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI07_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI07_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI07_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI07_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI09_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC2_USI09_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI09_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI09_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI09_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI09_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI10_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC2_USI10_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI10_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI10_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI10_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI10_USI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIS_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_PERIS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIS_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIS_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIS_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SSP_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_SSP_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SSP_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_SSP_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SSP_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_SSP_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TAA_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_TAA_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TAA_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_TAA_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TAA_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_TAA_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VPC_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_VPC_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VPC_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VPC_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VPC_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VPC_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VPD_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_VPD_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VPD_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VPD_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VPD_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VPD_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_DIVRATIO, 0, 8, CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_DIV2_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_DIV2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_AUD_DIV2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_AHB_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_VTS_DMIC_AHB),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_AHB_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_AHB),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_AHB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_AHB),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_YUVPP_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_YUVPP_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_YUVPP_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_YUVPP_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_YUVPP_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_YUVPP_BUSP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CORE_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL2_CORE_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL2_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL2_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL2_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_CSIS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CSIS_CSIS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_CSIS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CSIS_CSIS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_PDP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CSIS_PDP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_PDP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CSIS_PDP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DNS_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DNS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DNS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DNS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DSU_CLUSTER),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DSU_CLUSTER),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_SHADER_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G3D_SHADER),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_SHADER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G3D_SHADER),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSD_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ITP_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ITP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ITP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ITP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_LME_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_LME_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_LME_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_LME_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCFP0_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MCFP0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCFP0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MCFP0_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCFP1_MCFP1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MCFP1_MCFP1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCFP1_MCFP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MCFP1_MCFP1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCFP1_ORBMCH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MCFP1_ORBMCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCFP1_ORBMCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MCFP1_ORBMCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_GDC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC0_MFC0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MFC0_MFC0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MFC0_MFC0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC1_MFC1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MFC1_MFC1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MFC1_MFC1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NPU_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NPU_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU01_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NPU01_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU01_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NPU01_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU10_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NPU10_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPU10_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NPU10_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPUS_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TAA_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VPC_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VPC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VPC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VPC_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VPD_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VPD_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VPD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VPD_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_YUVPP_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_YUVPP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_YUVPP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_YUVPP_BUS),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_YUVPP_FRC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_YUVPP_FRC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_YUVPP_FRC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_YUVPP_FRC),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VTS_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VTS_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_VTS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GPIO_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GPIO_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GPIO_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_LP_VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_LP_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_LP_VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_LP_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_LP_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_LP_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_C_CMGP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_C_CMGP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_C_CMGP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_C_CMGP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_C_CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHS_AXI_C_CMGP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_PMIC_IPCLKPORT_I_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_MODEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_MODEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMGP_ADC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CMGP_ADC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMGP_ADC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CMGP_ADC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMGP_ADC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CMGP_ADC),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_VTS_DMIC_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_VTS_DMIC),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_VTS_DMIC_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_VTS_DMIC),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_VTS_DMIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_VTS_DMIC),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_LHM_AXI_C_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_APM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_APM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_APM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_APM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_APM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_APM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_CPU_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_CPU_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_SEMA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_SEMA),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_SEMA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_SEMA),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_SEMA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DOUBLE_IP_BATCHER_IPCLKPORT_I_PCLK_SEMA),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_SCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKAUD_VTS_DMIC1_CG_VAL, 21, 1, CLK_CON_GAT_CLKAUD_VTS_DMIC1),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKAUD_VTS_DMIC1_MANUAL, 20, 1, CLK_CON_GAT_CLKAUD_VTS_DMIC1),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKAUD_VTS_DMIC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKAUD_VTS_DMIC1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKAUD_VTS_DMIC0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKAUD_VTS_DMIC0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKAUD_VTS_DMIC0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKAUD_VTS_DMIC0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKAUD_VTS_DMIC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKAUD_VTS_DMIC0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_D_HSI0AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_D_HSI0AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_D_HSI0AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_D_HSI0AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_D_HSI0AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHM_AXI_D_HSI0AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDHSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDHSI0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDHSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDHSI0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDHSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDHSI0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDVTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDVTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_LHS_AXI_D_AUDVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKAUD_HSI0_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKAUD_HSI0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKAUD_HSI0_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKAUD_HSI0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKAUD_HSI0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKAUD_HSI0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKAUD_HSI0_USB31DRD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKAUD_HSI0_USB31DRD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKAUD_HSI0_USB31DRD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKAUD_HSI0_USB31DRD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKAUD_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKAUD_HSI0_USB31DRD),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_BAAW_D_AUDVTS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_BAAW_D_AUDVTS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_BAAW_D_AUDVTS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_BAAW_D_AUDVTS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_BAAW_D_AUDVTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_BAAW_D_AUDVTS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUS0_UID_BUS0_CMU_BUS0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BUS0_UID_BUS0_CMU_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUS0_UID_BUS0_CMU_BUS0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BUS0_UID_BUS0_CMU_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUS0_UID_BUS0_CMU_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BUS0_UID_BUS0_CMU_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_SYSREG_BUS0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_SYSREG_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_SYSREG_BUS0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_SYSREG_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_SYSREG_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_SYSREG_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_RSTNSYNC_CLK_BUS0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU10_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU10_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU10_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU10_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU10_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU10_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_VPC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_VPC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU01_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU01_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU01_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU01_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU01_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU01_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERISGIC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERISGIC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERISGIC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERISGIC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERISGIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERISGIC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU00_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU00_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU00_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU00_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU00_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_NPU00_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D0_BUS0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_ACLK_BUS0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_ACLK_BUS0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_ACLK_BUS0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_ACLK_BUS0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_ACLK_BUS0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_ACLK_BUS0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_BUS0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_BUS0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_BUS0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_BUS0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_BUS0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_BUS0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_D1_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D1_VPC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D1_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D1_VPC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D1_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D1_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D1_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D2_VPC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D2_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D2_VPC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D2_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D2_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D2_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D0_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D0_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D0_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D0_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D0_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D0_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_TREX_P_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_D_TZPC_BUS0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_D_TZPC_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_D_TZPC_BUS0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_D_TZPC_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_D_TZPC_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_D_TZPC_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_DBG_G_BUS0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_DBG_G_BUS0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_DBG_G_BUS0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_DBG_G_BUS0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_DBG_G_BUS0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_DBG_G_BUS0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D2_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D2_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D2_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D2_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D2_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D2_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D0_VPC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D0_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D0_VPC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D0_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D0_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_ACEL_D0_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D1_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D1_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D1_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D1_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D1_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHM_AXI_D1_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_CACHEAID_BUS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_BAAW_P_VPC_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_BAAW_P_VPC_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_BAAW_P_VPC_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_BAAW_P_VPC_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_BAAW_P_VPC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_BAAW_P_VPC_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_LHS_AXI_P_PERIC2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_DIT_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_DIT_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_DIT_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_DIT_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_DIT_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_D_TZPC_BUS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_D_TZPC_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_D_TZPC_BUS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_D_TZPC_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_D_TZPC_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_D_TZPC_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_DIT_IPCLKPORT_ICLKL2A_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_DIT_IPCLKPORT_ICLKL2A),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_DIT_IPCLKPORT_ICLKL2A_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_DIT_IPCLKPORT_ICLKL2A),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_DIT_IPCLKPORT_ICLKL2A_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_DIT_IPCLKPORT_ICLKL2A),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_HSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_HSI0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_HSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_HSI0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_HSI0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_DBG_G_BUS1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_DBG_G_BUS1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_DBG_G_BUS1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_DBG_G_BUS1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_DBG_G_BUS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_DBG_G_BUS1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_PDMA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_PDMA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_PDMA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_PDMA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_PDMA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_PDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_PDMA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_QE_SPDMA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SPDMA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SPDMA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SPDMA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SPDMA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SPDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SPDMA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_RB_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D0_BUS1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D0_BUS1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D0_BUS1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D0_BUS1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D0_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_XIU_D0_BUS1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_HSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_HSI0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_HSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_HSI0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_HSI0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_PDMA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_PDMA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_PDMA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_ACVPS_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_ACVPS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_ACVPS_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_ACVPS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_ACVPS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_ACVPS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_SBIC_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_SBIC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_SBIC_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_SBIC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_SBIC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SYSMMU_SBIC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_LITE_BUS1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_LITE_BUS1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_LITE_BUS1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_LITE_BUS1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_LITE_BUS1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_LITE_BUS1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_VTS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_VTS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_VTS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_VTS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_VTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BAAW_P_VTS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_ACVPS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_ACVPS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_ACVPS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_ACVPS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_ACVPS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_ACVPS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_SBIC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_SBIC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_SBIC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_SBIC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_SBIC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSMMU_S2_SBIC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_PDMA_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_PDMA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_PDMA_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_PDMA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_PDMA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_VGEN_PDMA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_SBIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_SBIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_SBIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_SBIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_SBIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_SBIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_SBIC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_SBIC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_SBIC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_SBIC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_SBIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_SBIC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_SBIC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_SBIC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_SBIC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_SBIC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_SBIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_D_SBIC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SBIC_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SBIC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SBIC_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SBIC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SBIC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AD_APB_SBIC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SBIC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SBIC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SBIC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SBIC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SBIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SBIC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D0_DPUF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D1_DPUF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_DPUF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUS2_UID_BUS2_CMU_BUS2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BUS2_UID_BUS2_CMU_BUS2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUS2_UID_BUS2_CMU_BUS2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BUS2_UID_BUS2_CMU_BUS2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUS2_UID_BUS2_CMU_BUS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BUS2_UID_BUS2_CMU_BUS2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_ITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_ITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_ITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_ITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_ITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_LME_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_LME_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_LME_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_LME_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_LME_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_D_BUS2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_YUVPP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_YUVPP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_YUVPP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_YUVPP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_YUVPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_YUVPP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_BUS2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_BUS2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_BUS2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_BUS2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_BUS2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_TREX_P_BUS2_IPCLKPORT_PCLK_BUS2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_LME_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_LME_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_LME_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_LME_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_LME_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_DBG_G_BUS2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_DBG_G_BUS2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_DBG_G_BUS2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_DBG_G_BUS2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_DBG_G_BUS2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_DBG_G_BUS2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_TAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_TAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_D_TZPC_BUS2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_D_TZPC_BUS2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_D_TZPC_BUS2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_D_TZPC_BUS2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_D_TZPC_BUS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_D_TZPC_BUS2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_SYSREG_BUS2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_SYSREG_BUS2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_SYSREG_BUS2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_SYSREG_BUS2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_SYSREG_BUS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_SYSREG_BUS2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_HSI1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_HSI1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_HSI1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_HSI1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_HSI1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D0_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D0_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D0_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D0_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D0_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D0_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_TAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_TAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_HSI1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_HSI1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_HSI1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_HSI1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_HSI1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_YUVPP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_YUVPP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_YUVPP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_YUVPP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_YUVPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_YUVPP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_RSTNSYNC_CLK_BUS2_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_MCFP1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_MCFP1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D_MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D0_MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D1_MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D2_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_AXI_D3_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_M2M_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_M2M_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_SSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_SSP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_SSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_SSP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_SSP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_SSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_SSP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_SSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_SSP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_SSP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_M2M_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_M2M_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHM_ACEL_D_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS2_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_C_CMGP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_C_CMGP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_C_CMGP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_C_CMGP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_C_CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_LHM_AXI_C_CMGP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C3_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C3_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C3_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C3_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C3_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_I_OSCCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_I_OSCCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_I_OSCCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_I_OSCCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_I_OSCCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF01_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_MIF01_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF01_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_MIF01_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF01_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_MIF01_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUF0_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DPUF0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUF0_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DPUF0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUF0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DPUF0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VPD_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_VPD_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VPD_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_VPD_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VPD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_VPD_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TAA_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TAA_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_TAA_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ITP_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_ITP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ITP_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_ITP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ITP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_ITP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HPM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HPM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HPM),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NPU_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_NPU_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NPU_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_NPU_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NPU_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_NPU_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUF0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DPUF0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUF0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DPUF0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DPUF0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_YUVPP_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_YUVPP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_YUVPP_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_YUVPP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_YUVPP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_YUVPP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_CSIS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_CSIS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_CSIS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_CSIS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_CSIS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_CSIS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCFP0_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MCFP0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCFP0_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MCFP0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCFP0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MCFP0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DNS_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DNS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DNS_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DNS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DNS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DNS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SSP_SSPCORE_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_SSP_SSPCORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SSP_SSPCORE_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_SSP_SSPCORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SSP_SSPCORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_SSP_SSPCORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_M2M_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_M2M_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_M2M_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_M2M_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_M2M_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_M2M_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUB_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DPUB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUB_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DPUB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUB_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DPUB_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUB_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DPUB),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUB_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DPUB),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DPUB),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUS1_SBIC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_BUS1_SBIC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUS1_SBIC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_BUS1_SBIC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUS1_SBIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_BUS1_SBIC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_LME_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_LME_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_LME_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_LME_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_LME_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_LME_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCFP1_MCFP1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MCFP1_MCFP1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCFP1_MCFP1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MCFP1_MCFP1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCFP1_MCFP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MCFP1_MCFP1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VPC_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_VPC_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VPC_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_VPC_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VPC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_VPC_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG_CPY_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG_CPY),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG_CPY_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG_CPY),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG_CPY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG_CPY),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_CPY_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_CPY),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_CPY_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_CPY),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_CPY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_CPY),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CPY_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CPY),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CPY_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CPY),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CPY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CPY),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCFP1_ORBMCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MCFP1_ORBMCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCFP1_ORBMCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MCFP1_ORBMCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCFP1_ORBMCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MCFP1_ORBMCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_PDP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_PDP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_PDP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_PDP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_PDP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_PDP),
|
|
SFR_ACCESS(CLK_CON_GAT_CP_UCPU_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CP_UCPU_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CP_UCPU_CLK_MANUAL, 20, 1, CLK_CON_GAT_CP_UCPU_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CP_UCPU_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CP_UCPU_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CP_LCPU_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CP_LCPU_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CP_LCPU_CLK_MANUAL, 20, 1, CLK_CON_GAT_CP_LCPU_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CP_LCPU_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CP_LCPU_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED0_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CP_SHARED0_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED0_CLK_MANUAL, 20, 1, CLK_CON_GAT_GATE_CP_SHARED0_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CP_SHARED0_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED1_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CP_SHARED1_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED1_CLK_MANUAL, 20, 1, CLK_CON_GAT_GATE_CP_SHARED1_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED1_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CP_SHARED1_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CP_SHARED2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED2_CLK_MANUAL, 20, 1, CLK_CON_GAT_GATE_CP_SHARED2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CP_SHARED2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_MANUAL, 20, 1, CLK_CON_GAT_GATE_CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SSP_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_SSP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SSP_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_SSP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SSP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_SSP_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_YUVPP_FRC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_YUVPP_FRC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_YUVPP_FRC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_YUVPP_FRC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_YUVPP_FRC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_YUVPP_FRC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC2_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC2_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC2_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF23_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_MIF23_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF23_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_MIF23_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF23_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_MIF23_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUF1_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DPUF1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUF1_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DPUF1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUF1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DPUF1_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUF1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DPUF1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUF1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DPUF1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DPUF1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_G3D3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D0_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D0_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D1_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D1_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D2_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D2_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D2_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D2_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D2_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D2_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D3_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D3_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D3_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D3_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D3_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_G3D3_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_D_CORE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_SYSMMU_G3D0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_SYSMMU_G3D0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_SYSMMU_G3D0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_SYSMMU_G3D0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_SYSMMU_G3D0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_APB_ASYNC_SYSMMU_G3D0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D3_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D3_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D3_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D3_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ACE_SLICE_G3D3_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D0_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D1_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D2_MODEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D2_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D2_MODEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D2_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D2_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACEL_D2_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_MODEM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_IRPS3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPMU_MIF3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HWACG_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HWACG_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HWACG_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HWACG_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HWACG_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HWACG_BUSIF_DDD_CPUCL0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DDD_CPUCL0_0_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DDD_CPUCL0_0_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DDD_CPUCL0_0_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DDD_CPUCL0_0_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DDD_CPUCL0_0_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DDD_CPUCL0_0_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_ETR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_ETR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_ETR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_ETR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_ETR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_STM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_STM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_STM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_STM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_STM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_STM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_DBGCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BUSIF_HPM_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BUSIF_HPM_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BUSIF_HPM_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BUSIF_HPM_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BUSIF_HPM_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BUSIF_HPM_CPUCL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_STM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_STM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_STM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_STM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_STM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_STM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_ETR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_ETR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_ETR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_ETR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_ETR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHS_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_2_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_2_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_2_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_2_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_2_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_HPM_CPUCL0_2_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_LHM_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_4_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC0),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC0),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC0),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC1),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC1),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC1),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC2),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC2),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_HHA11STQ_DDD_CK_IN_HC2),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HWACG_BUSIF_DDD_CPUCL0_3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_BUSIF_DDD_CPUCL0_1_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_DIV_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_DIV_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_DIV_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_DIV_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_DIV_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_HTU_DIV_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HWACG_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HWACG_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HWACG_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HWACG_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HWACG_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HWACG_BUSIF_DDD_CPUCL0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DDD_CPUCL0_1_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DDD_CPUCL0_1_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DDD_CPUCL0_1_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DDD_CPUCL0_1_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DDD_CPUCL0_1_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DDD_CPUCL0_1_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_C2CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_C2CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PDP_TOP_IPCLKPORT_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_AF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_PDP_CORE_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_PDP_CORE_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_PDP_CORE_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_PDP_CORE_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_PDP_CORE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_PDP_CORE_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D0_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D0_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D0_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D1_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D1_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D1_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_CSIS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_CSIS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_CSIS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_CSIS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_CSIS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_CSIS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_DMA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_DMA),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_DMA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_DMA),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_DMA),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AXI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AXI_P_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AXI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AXI_P_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AXI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AXI_P_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_OIS_MCU_TOP_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_OIS_MCU_TOP_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_OIS_MCU_TOP_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_OIS_MCU_TOP_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_OIS_MCU_TOP_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_OIS_MCU_TOP_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_OIS_MCU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_PDP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_PDP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_PDP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_PDP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_PDP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_PDP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_VO_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D2_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D2_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D2_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D2_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D2_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D2_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D3_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D3_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D3_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D3_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D3_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AXI_D3_CSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_STRP_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_STRP_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_STRP_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_STRP_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_STRP_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_AXI_STRP_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_CSISPDP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHM_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF0_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF1_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF2_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LHS_AST_INT_OTF3_PDPCSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_MCB_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_MCB),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_MCB_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_MCB),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_MCB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_MCB),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX6_IPCLKPORT_ACLK_VOTF1),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D0_DNS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D0_DNS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D0_DNS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D0_DNS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D0_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D0_DNS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_TAADNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_TAADNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_TAADNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_TAADNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_TAADNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_TAADNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D1_DNS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AXI_P_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AXI_P_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AXI_P_ITPDNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AXI_P_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AXI_P_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AXI_P_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D1_DNS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D1_DNS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D1_DNS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D1_DNS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D1_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D1_DNS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF9_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF9_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF9_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF9_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF9_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF9_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF8_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF8_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF8_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF8_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF8_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF8_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D0_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D0_DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D0_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D0_DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D0_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D0_DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF5_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF5_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF5_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF5_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF5_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF5_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF4_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF4_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF4_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF4_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF4_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF4_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF6_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF6_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF6_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF6_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF6_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF6_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF0_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF0_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF0_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF0_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF0_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF0_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF1_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF1_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF1_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF1_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF1_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF1_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF2_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF2_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF2_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF2_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF2_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF2_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF3_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF3_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF3_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF3_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF3_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF3_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF7_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF7_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF7_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF7_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF7_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_OTF7_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D1_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D1_DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D1_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D1_DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D1_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AXI_D1_DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_CTL_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_CTL_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_CTL_ITPDNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_CTL_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_CTL_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHM_AST_CTL_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_D0_DNS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_CTL_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_CTL_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_CTL_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_CTL_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_CTL_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LHS_AST_CTL_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D0_DNS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D0_DNS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D0_DNS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D0_DNS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D0_DNS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D0_DNS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D1_DNS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D1_DNS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D1_DNS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D1_DNS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D1_DNS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_VGEN_LITE_D1_DNS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_VOTF2),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_LHM_AXI_P_DPUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_LHM_AXI_P_DPUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_LHM_AXI_P_DPUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_LHM_AXI_P_DPUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_LHM_AXI_P_DPUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_LHM_AXI_P_DPUB_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF0_UID_DPUF0_CMU_DPUF0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF0_UID_DPUF0_CMU_DPUF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF0_UID_DPUF0_CMU_DPUF0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF0_UID_DPUF0_CMU_DPUF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF0_UID_DPUF0_CMU_DPUF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF0_UID_DPUF0_CMU_DPUF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSREG_DPUF0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSREG_DPUF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSREG_DPUF0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSREG_DPUF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSREG_DPUF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSREG_DPUF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_P_DPUF0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_P_DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_P_DPUF0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_P_DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_P_DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_P_DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D1_DPUF0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D1_DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D1_DPUF0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D1_DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D1_DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D1_DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_PPMU_DPUF0D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_RSTNSYNC_CLK_DPUF0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D0_DPUF0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D0_DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D0_DPUF0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D0_DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D0_DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHS_AXI_D0_DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DMA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DMA),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DMA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DMA),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DMA),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DPP_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DPP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DPP_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DPP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DPP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_DPP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_D_TZPC_DPUF0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_D_TZPC_DPUF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_D_TZPC_DPUF0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_D_TZPC_DPUF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_D_TZPC_DPUF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_D_TZPC_DPUF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_SYSMMU_DPUF0D1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_C2SERV_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_C2SERV),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_C2SERV_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_C2SERV),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_C2SERV_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_DPUF0_IPCLKPORT_ACLK_C2SERV),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF0_UID_LHM_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D1_DPUF1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D1_DPUF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D1_DPUF1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D1_DPUF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D1_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D1_DPUF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DMA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DMA),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DMA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DMA),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DMA),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPP_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPP_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPP),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D0_DPUF1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D0_DPUF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D0_DPUF1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D0_DPUF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D0_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D0_DPUF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHM_AXI_P_DPUF1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHM_AXI_P_DPUF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHM_AXI_P_DPUF1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHM_AXI_P_DPUF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHM_AXI_P_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHM_AXI_P_DPUF1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_C2SERV_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_C2SERV),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_C2SERV_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_C2SERV),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_C2SERV_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_C2SERV),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPUF1_UID_LHS_AXI_D_DPUF1DPUF0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHM_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHM_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHM_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHM_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHM_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHM_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T6_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ATB_T7_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_BCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_BCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_BCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_BCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_BCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_BCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D0_CLUSTER0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D0_CLUSTER0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D0_CLUSTER0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D0_CLUSTER0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D0_CLUSTER0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D0_CLUSTER0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D1_CLUSTER0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D1_CLUSTER0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D1_CLUSTER0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D1_CLUSTER0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D1_CLUSTER0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_ACE_US_128TO256_D1_CLUSTER0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSU_UID_LHS_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_STR_G3D_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_G3D_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_G3D_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_G3D_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_G3D_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_G3D_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_G3D_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_DDD_APBIF_G3D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_D_AUDHSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_D_AUDHSI0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_D_AUDHSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_D_AUDHSI0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_D_AUDHSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_D_AUDHSI0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AUD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHS_ACEL_D_HSI1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LHM_AXI_P_HSI1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4_0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_MMC_CARD_IPCLKPORT_SDCLKIN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_MMC_CARD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_MMC_CARD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_MMC_CARD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_MMC_CARD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_MMC_CARD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_MMC_CARD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_UFS_EMBD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_UFS_EMBD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_UFS_EMBD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_UFS_EMBD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_UFS_EMBD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_UFS_EMBD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_CTL_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_CTL_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_CTL_ITPDNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_CTL_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_CTL_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_CTL_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF4_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_CTL_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_CTL_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_CTL_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_CTL_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_CTL_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_CTL_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF4_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF4_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF4_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF4_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF4_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF4_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF3_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF3_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF3_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF3_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF3_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF3_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF5_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF5_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF5_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF5_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF5_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF5_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF6_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF6_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF6_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF6_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF6_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF6_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF7_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF7_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF7_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF7_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF7_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF7_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF8_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF8_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF8_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF8_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF8_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF8_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF9_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF9_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF9_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF9_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF9_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF9_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF2_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF2_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF2_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF2_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF2_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF2_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AXI_P_ITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AXI_P_ITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AXI_P_ITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AXI_P_ITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AXI_P_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AXI_P_ITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF0_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF0_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF0_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF0_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF0_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF0_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF1_DNSITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF1_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF1_DNSITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF1_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF1_DNSITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF1_DNSITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF1_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF2_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF3_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF0_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AXI_P_ITPDNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AXI_P_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AXI_P_ITPDNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AXI_P_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AXI_P_ITPDNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AXI_P_ITPDNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHM_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LHS_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_C2CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_C2CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_LME_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_PPMU_LME_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_LHS_AXI_D_LME_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_LHS_AXI_D_LME_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_LHS_AXI_D_LME_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_LHS_AXI_D_LME_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_LHS_AXI_D_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_LHS_AXI_D_LME_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_VGEN_LITE_LME_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_VGEN_LITE_LME_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_VGEN_LITE_LME_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_VGEN_LITE_LME_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_VGEN_LITE_LME_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_VGEN_LITE_LME_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_LHM_AXI_P_LME_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_LHM_AXI_P_LME_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_LHM_AXI_P_LME_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_LHM_AXI_P_LME_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_LHM_AXI_P_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_LHM_AXI_P_LME_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_RSTNSYNC_CLK_LME_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_LHS_ACEL_D_M2M_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_LHS_ACEL_D_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_LHS_ACEL_D_M2M_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_LHS_ACEL_D_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_LHS_ACEL_D_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_LHS_ACEL_D_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_LHM_AXI_P_M2M_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_LHM_AXI_P_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_LHM_AXI_P_M2M_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_LHM_AXI_P_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_LHM_AXI_P_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_LHM_AXI_P_M2M_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_ASTC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_ASTC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_ASTC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_ASTC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_ASTC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_ASTC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_ASTC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCFP0_UID_MCFP0_CMU_MCFP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCFP0_UID_MCFP0_CMU_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCFP0_UID_MCFP0_CMU_MCFP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCFP0_UID_MCFP0_CMU_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCFP0_UID_MCFP0_CMU_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCFP0_UID_MCFP0_CMU_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D0_MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D0_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D0_MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D0_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D0_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D0_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AXI_P_MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AXI_P_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AXI_P_MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AXI_P_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AXI_P_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AXI_P_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSREG_MCFP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSREG_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSREG_MCFP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSREG_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSREG_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSREG_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_D_TZPC_MCFP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_D_TZPC_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_D_TZPC_MCFP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_D_TZPC_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_D_TZPC_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_D_TZPC_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_VGEN_LITE_MCFP0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_VGEN_LITE_MCFP0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_VGEN_LITE_MCFP0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_VGEN_LITE_MCFP0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_VGEN_LITE_MCFP0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_VGEN_LITE_MCFP0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D0_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_APB_ASYNC_MCFP0_0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_APB_ASYNC_MCFP0_0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_APB_ASYNC_MCFP0_0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_APB_ASYNC_MCFP0_0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_APB_ASYNC_MCFP0_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_APB_ASYNC_MCFP0_0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D0_MCFP0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_MCFP0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_MCFP0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D1_MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D1_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D1_MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D1_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D1_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D1_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D1_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D1_MCFP0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCFP0_UID_RSTNSYNC_CLK_MCFP0_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D0_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D1_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D2_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_QE_D3_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_XIU_D0_MCFP0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_XIU_D0_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_XIU_D0_MCFP0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_XIU_D0_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_XIU_D0_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_XIU_D0_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D2_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_PPMU_D3_MCFP0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D2_MCFP0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_SYSMMU_D3_MCFP0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D2_MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D2_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D2_MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D2_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D2_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D2_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D3_MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D3_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D3_MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D3_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D3_MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AXI_D3_MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHM_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP0_UID_LHS_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCFP1_UID_MCFP1_CMU_MCFP1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCFP1_UID_MCFP1_CMU_MCFP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCFP1_UID_MCFP1_CMU_MCFP1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCFP1_UID_MCFP1_CMU_MCFP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCFP1_UID_MCFP1_CMU_MCFP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCFP1_UID_MCFP1_CMU_MCFP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_MCFP1_0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_MCFP1_0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_MCFP1_0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_MCFP1_0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_MCFP1_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_MCFP1_0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D2_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D0_MCFP1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D0_MCFP1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D0_MCFP1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D0_MCFP1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D0_MCFP1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D0_MCFP1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_PPMU_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D0_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF1_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AXI_P_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_MCFP1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_MCFP1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_MCFP1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_MCFP1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_MCFP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_MCFP1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AXI_D_MCFP1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AXI_D_MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AXI_D_MCFP1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AXI_D_MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AXI_D_MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AXI_D_MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1ITP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF_MCFP1DNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_C2CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_C2CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSREG_MCFP1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSREG_MCFP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSREG_MCFP1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSREG_MCFP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSREG_MCFP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSREG_MCFP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_SYSMMU_D_MCFP1_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_D_TZPC_MCFP1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_D_TZPC_MCFP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_D_TZPC_MCFP1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_D_TZPC_MCFP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_D_TZPC_MCFP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_D_TZPC_MCFP1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_XIU_D_MCFP1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_XIU_D_MCFP1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_XIU_D_MCFP1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_XIU_D_MCFP1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_XIU_D_MCFP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_XIU_D_MCFP1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D1_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF0_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_OTF0_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF1_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_ORBMCH0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_ORBMCH0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_ORBMCH0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_ORBMCH0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_ORBMCH0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_AD_APB_ORBMCH0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_MCFP1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_MCFP1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_MCFP1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_MCFP1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_MCFP1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_MCFP1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_ORBMCH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_ORBMCH_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_ORBMCH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_ORBMCH_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_ORBMCH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_RSTNSYNC_CLK_MCFP1_ORBMCH_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF2_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_OTF3_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D3_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHM_AST_CTL_MCFP0MCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_LHS_AST_CTL_MCFP1MCFP0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_C2CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_C2CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_ORBMCH1_IPCLKPORT_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D5_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_QE_D4_ORBMCH_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D1_MCFP1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D1_MCFP1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D1_MCFP1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D1_MCFP1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D1_MCFP1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCFP1_UID_VGEN_LITE_D1_MCFP1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_P_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_P_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_P_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_M_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_M),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_M_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_M),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_M_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_M),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D2_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D2_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D2_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D2_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D2_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D2_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_ACEL_D0_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_ACEL_D0_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_ACEL_D0_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_ACEL_D0_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_ACEL_D0_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_ACEL_D0_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_HPM_MCSC_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_HPM_MCSC_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_HPM_MCSC_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_HPM_MCSC_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_HPM_MCSC_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_HPM_MCSC_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CH_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CH_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_HPM_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_HPM_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_HPM_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_HPM_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_HPM_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_HPM_MCSC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_ADD_MCSC_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_BUSIF_DDD_MCSC_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_HTU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_HTU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D0_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D0_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D0_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D0_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D0_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D0_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_ADD_MCSC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_DDD_MCSC_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_DDD_MCSC_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_DDD_MCSC_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_DDD_MCSC_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_DDD_MCSC_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_DDD_MCSC_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D1_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D1_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D1_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D1_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D1_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHS_AXI_D1_MCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_S_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_S),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_S_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_S),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_S_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_C2CLK_S),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LHM_AST_OTF_ITPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D0_MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D0_MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D0_MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D0_MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D0_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D0_MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D1_MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D1_MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D1_MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D1_MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D1_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AXI_D1_MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AXI_P_MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AXI_P_MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AXI_P_MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AXI_P_MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AXI_P_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AXI_P_MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_AXI_WFD_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_AXI_WFD_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_AXI_WFD_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_AXI_WFD_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_VGEN_MFC0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_VGEN_MFC0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_VGEN_MFC0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_VGEN_MFC0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_VGEN_MFC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_VGEN_MFC0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHM_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_LHS_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D0_MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D0_MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D0_MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D0_MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D0_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D0_MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AXI_P_MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AXI_P_MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AXI_P_MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AXI_P_MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AXI_P_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AXI_P_MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D1_MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D1_MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D1_MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D1_MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D1_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AXI_D1_MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_MFC1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF0_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF1_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF2_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHM_AST_OTF3_MFC0MFC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF0_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF1_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF2_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_LHS_AST_OTF3_MFC1MFC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPU_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NPU_UID_NPU_CMU_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPU_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NPU_UID_NPU_CMU_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPU_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NPU_UID_NPU_CMU_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_IP_NPUCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_D_TZPC_NPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_D_TZPC_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_D_TZPC_NPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_D_TZPC_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_D_TZPC_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_D_TZPC_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_SYSREG_NPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_SYSREG_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_SYSREG_NPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_SYSREG_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_SYSREG_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_SYSREG_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPU01_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NPU01_UID_NPU_CMU_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPU01_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NPU01_UID_NPU_CMU_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPU01_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NPU01_UID_NPU_CMU_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_IP_NPUCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_D_TZPC_NPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_D_TZPC_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_D_TZPC_NPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_D_TZPC_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_D_TZPC_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_D_TZPC_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_SYSREG_NPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_SYSREG_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_SYSREG_NPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_SYSREG_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_SYSREG_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_SYSREG_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU01_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPU10_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NPU10_UID_NPU_CMU_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPU10_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NPU10_UID_NPU_CMU_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPU10_UID_NPU_CMU_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NPU10_UID_NPU_CMU_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_IP_NPUCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D1_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_RQ_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D0_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_D_TZPC_NPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_D_TZPC_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_D_TZPC_NPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_D_TZPC_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_D_TZPC_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_D_TZPC_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHS_AXI_D_CMDQ_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_SYSREG_NPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_SYSREG_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_SYSREG_NPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_SYSREG_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_SYSREG_NPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_SYSREG_NPU_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_RSTNSYNC_CLK_NPU_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPU10_UID_LHM_AXI_D_CTRL_NPU_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D2_NPUS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU10_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU10_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU10_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU10_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU10_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU10_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU10_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU10_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU10_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU10_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU10_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU10_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU01_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU01_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU01_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU01_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU01_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU01_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU00_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU00_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU00_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU00_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU00_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D0_NPU00_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU01_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU01_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU01_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU01_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU01_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU01_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU00_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU00_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU00_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU00_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU00_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU00_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU00_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU00_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU00_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU00_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU00_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU00_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU01_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU01_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU01_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU01_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU01_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D_CTRL_NPU01_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU10_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU10_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU10_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU10_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU10_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU10_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU00_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU00_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU00_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU00_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU00_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU00_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU01_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU01_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU01_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU01_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU01_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU01_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU10_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU10_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU10_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU10_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU10_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_CMDQ_NPU10_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D2_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D2_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D2_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D2_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D2_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D2_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU00_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU00_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU00_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU00_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU00_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU00_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU01_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU01_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU01_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU01_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU01_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_D_RQ_NPU01_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU10_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU10_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU10_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU10_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU10_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_D1_NPU10_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_P0_NPUS_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_P0_NPUS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_P0_NPUS_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_P0_NPUS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_P0_NPUS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_P0_NPUS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_P_INT_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_P_INT_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_P_INT_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_P_INT_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_P_INT_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHS_AXI_P_INT_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_INT_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_INT_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_INT_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_INT_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_INT_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LHM_AXI_P_INT_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_HPM_NPUS_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_HPM_NPUS_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_HPM_NPUS_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_HPM_NPUS_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_HPM_NPUS_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_HPM_NPUS_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CH_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CH_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_HPM_NPUS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_HPM_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_HPM_NPUS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_HPM_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_HPM_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_HPM_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_ADD_NPUS_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_BUSIF_DDD_NPUS_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_ADD_NPUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_DDD_NPUS_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_DDD_NPUS_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_DDD_NPUS_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_DDD_NPUS_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NPUS_UID_DDD_NPUS_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NPUS_UID_DDD_NPUS_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_7),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_8),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_7),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_8),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_7),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_9),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_10),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_4),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_5),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_6),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_7),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_9),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_10),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_CSISPERIC1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_12),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_12),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_13),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_14),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_PCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_13),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_14),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP1_IPCLKPORT_IPCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI17_I3C_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI18_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_11_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_11),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_11_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_11),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_11_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_11),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_10_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_10),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_10_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_10),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_10_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_10),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_13_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_13),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_13_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_13),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_13_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_13),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_12_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_12),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_12_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_12),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_12_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_12),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_15_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_15_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_15_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_14_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_14),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_14_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_14),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_14_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_14),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_15_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_15_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_15_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_15),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_13_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_13),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_13_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_13),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_13_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_13),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_14_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_14),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_14_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_14),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_14_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_PCLK_14),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_12_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_12),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_12_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_12),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_12_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_12),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_11_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_11),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_11_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_11),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_11_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_11),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_10_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_10),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_10_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_10),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_10_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP0_IPCLKPORT_IPCLK_10),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_LHM_AXI_P_PERIC2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_LHM_AXI_P_PERIC2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_LHM_AXI_P_PERIC2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_LHM_AXI_P_PERIC2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_LHM_AXI_P_PERIC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_LHM_AXI_P_PERIC2_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI06_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI06_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI06_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI06_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI06_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI06_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI07_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI07_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI07_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI07_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI07_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI07_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI08_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI08_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI08_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI08_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI08_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI08_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI_I2C_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI09_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI09_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI09_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI09_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI09_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI09_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI10_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI10_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI10_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI10_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI10_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_USI10_USI_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_3_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_3_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_IPCLK_3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_3_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_3_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC2_UID_PERIC2_TOP1_IPCLKPORT_PCLK_3),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERISGIC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERISGIC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERISGIC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERISGIC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERISGIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERISGIC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_BC_EMUL_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BC_EMUL_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_BC_EMUL_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BC_EMUL_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_BC_EMUL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BC_EMUL_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AST_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHS_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHS_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHS_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHS_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHS_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHS_AST_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_LHM_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_LHM_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_LHM_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_LHM_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_LHM_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_LHM_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_SYSMMU_RTIC_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_SYSMMU_RTIC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_SYSMMU_RTIC_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_SYSMMU_RTIC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_SYSMMU_RTIC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_SYSMMU_RTIC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSMMU_RTIC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSMMU_RTIC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSMMU_RTIC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSMMU_RTIC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSMMU_RTIC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSMMU_RTIC_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_LHS_ACEL_D_SSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_LHS_ACEL_D_SSP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_LHS_ACEL_D_SSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_LHS_ACEL_D_SSP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_LHS_ACEL_D_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_LHS_ACEL_D_SSP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_PUF_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_PUF_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_PUF_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_PUF_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_PUF_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_AD_APB_PUF_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_PUF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_PUF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_PUF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_PUF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_PUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_PUF_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_P_SSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_P_SSP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_P_SSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_P_SSP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_P_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_P_SSP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_RTIC_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_D_SSPCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_D_SSPCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_D_SSPCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_D_SSPCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_D_SSPCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_LHM_AXI_D_SSPCORE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_SSPCORE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_SSPCORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_SSPCORE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_SSPCORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_SSPCORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_RSTNSYNC_CLK_SSP_SSPCORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_USS_SSPCORE_IPCLKPORT_SS_SSPCORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_USS_SSPCORE_IPCLKPORT_SS_SSPCORE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_USS_SSPCORE_IPCLKPORT_SS_SSPCORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_USS_SSPCORE_IPCLKPORT_SS_SSPCORE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_USS_SSPCORE_IPCLKPORT_SS_SSPCORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_USS_SSPCORE_IPCLKPORT_SS_SSPCORE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_RTIC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSPCORE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_VGEN_LITE_RTIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_VGEN_LITE_RTIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_VGEN_LITE_RTIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_VGEN_LITE_RTIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_VGEN_LITE_RTIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_VGEN_LITE_RTIC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSREG_SSPCTRL_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSREG_SSPCTRL_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSREG_SSPCTRL_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSREG_SSPCTRL_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSREG_SSPCTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_SYSREG_SSPCTRL_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_SWEEPER_D_SSP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_SWEEPER_D_SSP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_SWEEPER_D_SSP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_SWEEPER_D_SSP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_SWEEPER_D_SSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_SWEEPER_D_SSP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_BPS_AXI_P_SSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_BPS_AXI_P_SSP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_BPS_AXI_P_SSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_BPS_AXI_P_SSP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_BPS_AXI_P_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_BPS_AXI_P_SSP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_ADM_DAP_SSS_IPCLKPORT_DAPCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_ADM_DAP_SSS_IPCLKPORT_DAPCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_ADM_DAP_SSS_IPCLKPORT_DAPCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_ADM_DAP_SSS_IPCLKPORT_DAPCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SSP_UID_ADM_DAP_SSS_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SSP_UID_ADM_DAP_SSS_IPCLKPORT_DAPCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AXI_D_TAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AXI_D_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AXI_D_TAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AXI_D_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AXI_D_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AXI_D_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AXI_P_TAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AXI_P_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AXI_P_TAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AXI_P_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AXI_P_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AXI_P_TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_OTF_TAADNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_OTF_TAADNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_OTF_TAADNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_OTF_TAADNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_OTF_TAADNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_OTF_TAADNS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF0_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF1_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF2_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF0_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF1_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF2_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_D_TAA_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_OTF3_CSISTAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_SOTF3_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_ZOTF3_TAACSIS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHM_AST_VO_MCFP1TAA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_LHS_AST_VO_TAAMCFP1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TAA_UID_HPM_TAA_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TAA_UID_HPM_TAA_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TAA_UID_HPM_TAA_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TAA_UID_HPM_TAA_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TAA_UID_HPM_TAA_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TAA_UID_HPM_TAA_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_HPM_TAA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_HPM_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_HPM_TAA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_HPM_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_HPM_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_HPM_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CH_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CH_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_ADD_TAA_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_HTU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_HTU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE_TAA1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_BUSIF_DDD_TAA_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TAA_UID_ADD_TAA_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TAA_UID_DDD_TAA_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TAA_UID_DDD_TAA_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TAA_UID_DDD_TAA_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TAA_UID_DDD_TAA_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TAA_UID_DDD_TAA_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TAA_UID_DDD_TAA_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPC_UID_VPC_CMU_VPC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VPC_UID_VPC_CMU_VPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPC_UID_VPC_CMU_VPC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VPC_UID_VPC_CMU_VPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPC_UID_VPC_CMU_VPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VPC_UID_VPC_CMU_VPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_D_TZPC_VPC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_D_TZPC_VPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_D_TZPC_VPC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_D_TZPC_VPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_D_TZPC_VPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_D_TZPC_VPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPC_UID_RSTNSYNC_CLK_VPC_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VPC_UID_RSTNSYNC_CLK_VPC_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPC_UID_RSTNSYNC_CLK_VPC_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VPC_UID_RSTNSYNC_CLK_VPC_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPC_UID_RSTNSYNC_CLK_VPC_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VPC_UID_RSTNSYNC_CLK_VPC_OSCCLK_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD0_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPCVPD1_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_SFR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_SFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_SFR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_SFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_SFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_SFR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_SFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_SFR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_SFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_SFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_SFR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_SFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_SFR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_SFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_SFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSREG_VPC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSREG_VPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSREG_VPC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSREG_VPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSREG_VPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSREG_VPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_SFR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_SFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_SFR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_SFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_SFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPC_200_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPC_200_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPC_200_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPC_200_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPC_200_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_P_VPC_200_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_800_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_800_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_800_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_800_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_800_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_P_VPC_800_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC2_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D2_VPC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D2_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D2_VPC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D2_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D2_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D2_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC2_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_CACHE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_CACHE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_CACHE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_CACHE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_CACHE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD1VPC_CACHE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_CACHE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_CACHE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_CACHE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_CACHE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_CACHE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHM_AXI_D_VPD0VPC_CACHE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_AD_APB_VPC0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_AD_APB_VPC0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_AD_APB_VPC0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_AD_APB_VPC0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_AD_APB_VPC0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_AD_APB_VPC0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC0_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_SYSMMU_VPC1_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC0_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_PPMU_VPC1_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D0_VPC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D0_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D0_VPC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D0_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D0_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D0_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D1_VPC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D1_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D1_VPC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D1_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D1_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_ACEL_D1_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_DMA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_DMA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_DMA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_DMA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_DMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD0_DMA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_DMA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_DMA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_DMA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_DMA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_DMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_LHS_AXI_D_VPCVPD1_DMA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPC_UID_HPM_VPC_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VPC_UID_HPM_VPC_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPC_UID_HPM_VPC_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VPC_UID_HPM_VPC_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPC_UID_HPM_VPC_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VPC_UID_HPM_VPC_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CH_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CH_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_HPM_VPC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_HPM_VPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_HPM_VPC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_HPM_VPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_HPM_VPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_HPM_VPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_ADD_VPC_IPCLKPORT_CLK_CORE),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_BUSIF_DDD_VPC_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_HTU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_HTU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_RSTNSYNC_CLK_VPC_HTU_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_ADM_DAP_VPC_IPCLKPORT_DAPCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_ADM_DAP_VPC_IPCLKPORT_DAPCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_ADM_DAP_VPC_IPCLKPORT_DAPCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_ADM_DAP_VPC_IPCLKPORT_DAPCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_ADM_DAP_VPC_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_ADM_DAP_VPC_IPCLKPORT_DAPCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_DAP_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_DAP_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_DAP_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_DAP_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_DAP_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_IP_VPC_IPCLKPORT_DAP_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_HTU_VPC_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VPC_UID_ADD_VPC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPC_UID_DDD_VPC_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VPC_UID_DDD_VPC_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPC_UID_DDD_VPC_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VPC_UID_DDD_VPC_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPC_UID_DDD_VPC_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VPC_UID_DDD_VPC_IPCLKPORT_CK_IN),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_VGEN_LITE_VPC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_VGEN_LITE_VPC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_VGEN_LITE_VPC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_VGEN_LITE_VPC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_VGEN_LITE_VPC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_VGEN_LITE_VPC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_XIU_VPC_VOTF_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_XIU_VPC_VOTF_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_XIU_VPC_VOTF_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_XIU_VPC_VOTF_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPC_UID_XIU_VPC_VOTF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPC_UID_XIU_VPC_VOTF_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPD_UID_VPD_CMU_VPD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VPD_UID_VPD_CMU_VPD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPD_UID_VPD_CMU_VPD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VPD_UID_VPD_CMU_VPD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPD_UID_VPD_CMU_VPD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VPD_UID_VPD_CMU_VPD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_SYSREG_VPD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_SYSREG_VPD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_SYSREG_VPD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_SYSREG_VPD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_SYSREG_VPD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_SYSREG_VPD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_SFR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_SFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_SFR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_SFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_SFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_RSTNSYNC_CLK_VPD_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_IP_VPD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_IP_VPD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_IP_VPD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_IP_VPD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_IP_VPD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_IP_VPD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_CACHE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_CACHE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_CACHE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_CACHE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_CACHE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHS_AXI_D_VPDVPC_CACHE_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_P_VPCVPD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_P_VPCVPD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_P_VPCVPD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_P_VPCVPD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_P_VPCVPD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_P_VPCVPD_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_SFR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_SFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_SFR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_SFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_SFR_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_D_TZPC_VPD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_D_TZPC_VPD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_D_TZPC_VPD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_D_TZPC_VPD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_D_TZPC_VPD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_D_TZPC_VPD_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_DMA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_DMA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_DMA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_DMA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_DMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPD_UID_LHM_AXI_D_VPCVPD_DMA_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_D_TZPC_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_D_TZPC_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_D_TZPC_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_D_TZPC_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_D_TZPC_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_D_TZPC_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_VGEN_LITE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_VGEN_LITE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_VGEN_LITE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_VGEN_LITE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_VGEN_LITE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_VGEN_LITE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_LP_VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_LP_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_LP_VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_LP_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_LP_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_LP_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_P_VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_P_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_P_VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_P_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_P_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_BPS_P_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_D_VTS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_D_VTS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_D_VTS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_D_VTS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_D_VTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_D_VTS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_D_VTS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_D_VTS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_D_VTS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_D_VTS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_D_VTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_D_VTS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_APM_VTS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_APM_VTS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_APM_VTS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_APM_VTS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_APM_VTS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_APM_VTS1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_PDMA_VTS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_PDMA_VTS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_PDMA_VTS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_PDMA_VTS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_PDMA_VTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_PDMA_VTS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_BCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_BCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_BCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_BCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_BCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_BCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_BCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_BCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_BCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_BCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_BCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_BCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_BCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_BCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_BCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_BCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_BCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_BCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_D_AUDVTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_D_AUDVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_D_AUDVTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_D_AUDVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_D_AUDVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_D_AUDVTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_C_VTS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_C_VTS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_C_VTS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_C_VTS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_C_VTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_BAAW_C_VTS_IPCLKPORT_I_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_C_VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_C_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_C_VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_C_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_C_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_C_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_C_VTS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_C_VTS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_C_VTS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_C_VTS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_C_VTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SWEEPER_C_VTS_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AHB_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AHB_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AHB_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AHB_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AHB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AHB_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB4_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB5_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_VT_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_DEBUG_US_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB0_IPCLKPORT_HCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB1_IPCLKPORT_HCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB2_IPCLKPORT_HCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB3_IPCLKPORT_HCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB4_IPCLKPORT_HCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCAHB5_IPCLKPORT_HCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_BUS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_BUS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC4_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_BUS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC5_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_HPM_VTS_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_HPM_VTS_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_HPM_VTS_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_HPM_VTS_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_HPM_VTS_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_HPM_VTS_IPCLKPORT_HPM_TARGETCLK_C),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNC_APB_VTS_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNC_APB_VTS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNC_APB_VTS_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNC_APB_VTS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNC_APB_VTS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNC_APB_VTS_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_BUSIF_HPM_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_BUSIF_HPM_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_BUSIF_HPM_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_BUSIF_HPM_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_BUSIF_HPM_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_BUSIF_HPM_VTS_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_DIV2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_DIV2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_DIV2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_DIV2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_DIV2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_DIV2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMAILBOX_TEST_IPCLKPORT_CCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_LP_VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_LP_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_LP_VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_LP_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_LP_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_LP_VTS_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVPP_UID_YUVPP_CMU_YUVPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVPP_UID_YUVPP_CMU_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVPP_UID_YUVPP_CMU_YUVPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVPP_UID_YUVPP_CMU_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVPP_UID_YUVPP_CMU_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVPP_UID_YUVPP_CMU_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_YUVPP0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_YUVPP0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_YUVPP0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_YUVPP0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_YUVPP0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_YUVPP0_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_D_TZPC_YUVPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_D_TZPC_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_D_TZPC_YUVPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_D_TZPC_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_D_TZPC_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_D_TZPC_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHM_AXI_P_YUVPP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHM_AXI_P_YUVPP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHM_AXI_P_YUVPP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHM_AXI_P_YUVPP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHM_AXI_P_YUVPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHM_AXI_P_YUVPP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSREG_YUVPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSREG_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSREG_YUVPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSREG_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSREG_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSREG_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP0_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSD_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_BUSP_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S1),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D0_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_SYSMMU_D_YUVPP_IPCLKPORT_CLK_S2),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D0_YUVPP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D0_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D0_YUVPP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D0_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D0_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D0_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D1_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_PPMU_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_C2COM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_C2COM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_C2COM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_C2COM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_C2COM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_YUVPP_TOP_IPCLKPORT_I_CLK_C2COM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D2_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D3_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D4_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D5_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AST_OTF_YUVPPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_FRC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_FRC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_FRC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_FRC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_FRC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_RSTNSYNC_CLK_YUVPP_FRC_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_FRC_MC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_FRC_MC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_FRC_MC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_FRC_MC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_FRC_MC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_FRC_MC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP1_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D6_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D7_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D8_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D9_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D1_YUVPP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D1_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D1_YUVPP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D1_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D1_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_XIU_D1_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_FRC_MC_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_FRC_MC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_FRC_MC_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_FRC_MC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_FRC_MC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_APB_FRC_MC_IPCLKPORT_PCLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_LHS_AXI_D_YUVPPMCSC_IPCLKPORT_I_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_AXI_FRC_MC_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_AXI_FRC_MC_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_AXI_FRC_MC_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_AXI_FRC_MC_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_AXI_FRC_MC_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_AD_AXI_FRC_MC_IPCLKPORT_ACLKM),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_VGEN_LITE_YUVPP2_IPCLKPORT_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D10_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_ACLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_YUVPP_UID_QE_D11_YUVPP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI1_PCIE),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_G3D_ADD_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_MCSC_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_MCSC_ADD_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF_BUSD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_NPUS_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_NPUS_ADD_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_OTP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_MIF_BUSD_S2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_MIF_BUSD_S2D),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_TAA_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_TAA_ADD_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_VPC_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_VPC_ADD_CH_CLK),
|
|
SFR_ACCESS(QCH_CON_ALIVE_CMU_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_ALIVE_CMU_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_ALIVE_CMU_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_ALIVE_CMU_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_ALIVE_CMU_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ALIVE_CMU_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_ALIVE_CMU_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ALIVE_CMU_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_APBIF_PMU_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_PMU_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_PMU_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_PMU_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_ENABLE, 0, 1, QCH_CON_APBIF_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_ENABLE, 0, 1, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_ENABLE, 0, 1, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_ENABLE, 0, 1, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_TOP_RTC_QCH_ENABLE, 0, 1, QCH_CON_APBIF_TOP_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_TOP_RTC_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_TOP_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_TOP_RTC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_TOP_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_TOP_RTC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_TOP_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_CLKMON_QCH_ENABLE, 0, 1, QCH_CON_CLKMON_QCH),
|
|
SFR_ACCESS(QCH_CON_CLKMON_QCH_CLOCK_REQ, 1, 1, QCH_CON_CLKMON_QCH),
|
|
SFR_ACCESS(QCH_CON_CLKMON_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CLKMON_QCH),
|
|
SFR_ACCESS(QCH_CON_CLKMON_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLKMON_QCH),
|
|
SFR_ACCESS(QCH_CON_DBGCORE_UART_QCH_ENABLE, 0, 1, QCH_CON_DBGCORE_UART_QCH),
|
|
SFR_ACCESS(QCH_CON_DBGCORE_UART_QCH_CLOCK_REQ, 1, 1, QCH_CON_DBGCORE_UART_QCH),
|
|
SFR_ACCESS(QCH_CON_DBGCORE_UART_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DBGCORE_UART_QCH),
|
|
SFR_ACCESS(QCH_CON_DBGCORE_UART_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DBGCORE_UART_QCH),
|
|
SFR_ACCESS(QCH_CON_DOUBLE_IP_BATCHER_QCH_APM_ENABLE, 0, 1, QCH_CON_DOUBLE_IP_BATCHER_QCH_APM),
|
|
SFR_ACCESS(QCH_CON_DOUBLE_IP_BATCHER_QCH_APM_CLOCK_REQ, 1, 1, QCH_CON_DOUBLE_IP_BATCHER_QCH_APM),
|
|
SFR_ACCESS(QCH_CON_DOUBLE_IP_BATCHER_QCH_APM_EXPIRE_VAL, 16, 10, QCH_CON_DOUBLE_IP_BATCHER_QCH_APM),
|
|
SFR_ACCESS(QCH_CON_DOUBLE_IP_BATCHER_QCH_APM_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DOUBLE_IP_BATCHER_QCH_APM),
|
|
SFR_ACCESS(QCH_CON_DOUBLE_IP_BATCHER_QCH_CPU_ENABLE, 0, 1, QCH_CON_DOUBLE_IP_BATCHER_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_DOUBLE_IP_BATCHER_QCH_CPU_CLOCK_REQ, 1, 1, QCH_CON_DOUBLE_IP_BATCHER_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_DOUBLE_IP_BATCHER_QCH_CPU_EXPIRE_VAL, 16, 10, QCH_CON_DOUBLE_IP_BATCHER_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_DOUBLE_IP_BATCHER_QCH_CPU_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DOUBLE_IP_BATCHER_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_DOUBLE_IP_BATCHER_QCH_SEMA_ENABLE, 0, 1, QCH_CON_DOUBLE_IP_BATCHER_QCH_SEMA),
|
|
SFR_ACCESS(QCH_CON_DOUBLE_IP_BATCHER_QCH_SEMA_CLOCK_REQ, 1, 1, QCH_CON_DOUBLE_IP_BATCHER_QCH_SEMA),
|
|
SFR_ACCESS(QCH_CON_DOUBLE_IP_BATCHER_QCH_SEMA_EXPIRE_VAL, 16, 10, QCH_CON_DOUBLE_IP_BATCHER_QCH_SEMA),
|
|
SFR_ACCESS(QCH_CON_DOUBLE_IP_BATCHER_QCH_SEMA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DOUBLE_IP_BATCHER_QCH_SEMA),
|
|
SFR_ACCESS(QCH_CON_DTZPC_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_DTZPC_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_DTZPC_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_DTZPC_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_DTZPC_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DTZPC_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_DTZPC_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DTZPC_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_GPIO_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_ENABLE, 0, 1, QCH_CON_GREBEINTEGRATION_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_CLOCK_REQ, 1, 1, QCH_CON_GREBEINTEGRATION_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_EXPIRE_VAL, 16, 10, QCH_CON_GREBEINTEGRATION_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GREBEINTEGRATION_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_ENABLE, 0, 1, QCH_CON_GREBEINTEGRATION_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_CLOCK_REQ, 1, 1, QCH_CON_GREBEINTEGRATION_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_EXPIRE_VAL, 16, 10, QCH_CON_GREBEINTEGRATION_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GREBEINTEGRATION_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_ENABLE, 0, 1, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH),
|
|
SFR_ACCESS(QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_CLOCK_REQ, 1, 1, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH),
|
|
SFR_ACCESS(QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH),
|
|
SFR_ACCESS(QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH),
|
|
SFR_ACCESS(QCH_CON_I3C_PMIC_QCH_P_ENABLE, 0, 1, QCH_CON_I3C_PMIC_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C_PMIC_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_I3C_PMIC_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C_PMIC_QCH_P_EXPIRE_VAL, 16, 10, QCH_CON_I3C_PMIC_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C_PMIC_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C_PMIC_QCH_P),
|
|
SFR_ACCESS(DMYQCH_CON_I3C_PMIC_QCH_S_ENABLE, 0, 1, DMYQCH_CON_I3C_PMIC_QCH_S),
|
|
SFR_ACCESS(DMYQCH_CON_I3C_PMIC_QCH_S_CLOCK_REQ, 1, 1, DMYQCH_CON_I3C_PMIC_QCH_S),
|
|
SFR_ACCESS(DMYQCH_CON_I3C_PMIC_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_I3C_PMIC_QCH_S),
|
|
SFR_ACCESS(QCH_CON_INTMEM_QCH_ENABLE, 0, 1, QCH_CON_INTMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_INTMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_INTMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_INTMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_C_MODEM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_C_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_C_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_C_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_C_MODEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_C_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_C_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_C_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_C_VTS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_C_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_C_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_C_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_C_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_C_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_C_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_C_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_C_CMGP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_C_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_C_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_C_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_C_CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_C_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_C_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_C_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_APM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_LP_VTS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_LP_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_LP_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_LP_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_LP_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_LP_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_LP_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_LP_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_AP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_AP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_AP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_S_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_CP_S_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_S_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_CP_S_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_S_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_CP_S_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_S_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_CP_S_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_PEM_QCH_ENABLE, 0, 1, QCH_CON_PEM_QCH),
|
|
SFR_ACCESS(QCH_CON_PEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_PEM_QCH),
|
|
SFR_ACCESS(QCH_CON_PEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PEM_QCH),
|
|
SFR_ACCESS(QCH_CON_PEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PEM_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_ENABLE, 0, 1, QCH_CON_PMU_INTR_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_INTR_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_INTR_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PMU_INTR_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_ROM_CRC32_HOST_QCH_ENABLE, 0, 1, QCH_CON_ROM_CRC32_HOST_QCH),
|
|
SFR_ACCESS(QCH_CON_ROM_CRC32_HOST_QCH_CLOCK_REQ, 1, 1, QCH_CON_ROM_CRC32_HOST_QCH),
|
|
SFR_ACCESS(QCH_CON_ROM_CRC32_HOST_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ROM_CRC32_HOST_QCH),
|
|
SFR_ACCESS(QCH_CON_ROM_CRC32_HOST_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ROM_CRC32_HOST_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_GREBE_ENABLE, 0, 1, QCH_CON_SS_DBGCORE_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_GREBE_CLOCK_REQ, 1, 1, QCH_CON_SS_DBGCORE_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_GREBE_EXPIRE_VAL, 16, 10, QCH_CON_SS_DBGCORE_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_GREBE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SS_DBGCORE_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_DBG_ENABLE, 0, 1, QCH_CON_SS_DBGCORE_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_DBG_CLOCK_REQ, 1, 1, QCH_CON_SS_DBGCORE_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_DBG_EXPIRE_VAL, 16, 10, QCH_CON_SS_DBGCORE_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_DBG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SS_DBGCORE_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_P_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_SWEEPER_P_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_P_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SWEEPER_P_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_P_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SWEEPER_P_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_P_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SWEEPER_P_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_WDT_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_ENABLE, 0, 1, QCH_CON_ABOX_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK_DSIF_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK_DSIF),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK_DSIF_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK_DSIF),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK_DSIF_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK_DSIF),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK_DSIF_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK_DSIF),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK0_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK0_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK0_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK1_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK1_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK1_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK2_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK2_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK2_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK3_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK3),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK3_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK3),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK3_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK3),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK3_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK3),
|
|
SFR_ACCESS(DMYQCH_CON_ABOX_QCH_CPU_ENABLE, 0, 1, DMYQCH_CON_ABOX_QCH_CPU),
|
|
SFR_ACCESS(DMYQCH_CON_ABOX_QCH_CPU_CLOCK_REQ, 1, 1, DMYQCH_CON_ABOX_QCH_CPU),
|
|
SFR_ACCESS(DMYQCH_CON_ABOX_QCH_CPU_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ABOX_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK4_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK4),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK4_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK4),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK4_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK4),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK4_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK4),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CNT_ENABLE, 0, 1, QCH_CON_ABOX_QCH_CNT),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CNT_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_CNT),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CNT_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_CNT),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CNT_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_CNT),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK5_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK5),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK5_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK5),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK5_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK5),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK5_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK5),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ASB_ENABLE, 0, 1, QCH_CON_ABOX_QCH_CCLK_ASB),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ASB_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_CCLK_ASB),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ASB_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_CCLK_ASB),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ASB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_CCLK_ASB),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_SCLK_ENABLE, 0, 1, QCH_CON_ABOX_QCH_SCLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_SCLK_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_SCLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_SCLK_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_SCLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_SCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_SCLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK6_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK6),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK6_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK6),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK6_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_BCLK6),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK6_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK6),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK_ENABLE, 0, 1, QCH_CON_ABOX_QCH_XCLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_XCLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_XCLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_XCLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_PCMC_CLK_ENABLE, 0, 1, QCH_CON_ABOX_QCH_PCMC_CLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_PCMC_CLK_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_PCMC_CLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_PCMC_CLK_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_PCMC_CLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_PCMC_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_PCMC_CLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A0_ENABLE, 0, 1, QCH_CON_ABOX_QCH_C2A0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A0_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_C2A0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A0_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_C2A0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_C2A0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A1_ENABLE, 0, 1, QCH_CON_ABOX_QCH_C2A1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A1_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_C2A1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A1_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_QCH_C2A1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_C2A1),
|
|
SFR_ACCESS(QCH_CON_AUD_CMU_AUD_QCH_ENABLE, 0, 1, QCH_CON_AUD_CMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_AUD_CMU_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_AUD_CMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_AUD_CMU_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_AUD_CMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_AUD_CMU_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_AUD_CMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_AUDVTS_QCH_ENABLE, 0, 1, QCH_CON_BAAW_D_AUDVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_AUDVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_D_AUDVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_AUDVTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_D_AUDVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_AUDVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_D_AUDVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_AUD_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_HSI0AUD_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_HSI0AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_HSI0AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_HSI0AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_HSI0AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_HSI0AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_HSI0AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_HSI0AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_AUD_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_AUD_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_AUDHSI0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_AUDHSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_AUDHSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_AUDHSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_AUDHSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_AUDHSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_AUDHSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_AUDHSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_AUDVTS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_AUDVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_AUDVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_AUDVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_AUDVTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_AUDVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_AUDVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_AUDVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD0_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AUD0_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AUD0_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AUD0_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AUD0_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD1_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AUD1_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AUD1_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AUD1_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AUD1_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD2_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AUD2_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD2_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AUD2_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AUD2_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AUD2_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD3_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AUD3_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD3_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AUD3_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AUD3_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AUD3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_AUD_QCH_ENABLE, 0, 1, QCH_CON_PPMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH),
|
|
SFR_ACCESS(QCH_CON_SMMU_AUD_QCH_S1_ENABLE, 0, 1, QCH_CON_SMMU_AUD_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SMMU_AUD_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SMMU_AUD_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SMMU_AUD_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_AUD_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SMMU_AUD_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SMMU_AUD_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SMMU_AUD_QCH_S2_ENABLE, 0, 1, QCH_CON_SMMU_AUD_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SMMU_AUD_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SMMU_AUD_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SMMU_AUD_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_AUD_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SMMU_AUD_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SMMU_AUD_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_AUD_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_AUD_QCH_ENABLE, 0, 1, QCH_CON_TREX_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_AUD_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_AUD_QCH_ENABLE, 0, 1, QCH_CON_WDT_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_ASYNCSFR_WR_SMC_QCH_ENABLE, 0, 1, QCH_CON_ASYNCSFR_WR_SMC_QCH),
|
|
SFR_ACCESS(QCH_CON_ASYNCSFR_WR_SMC_QCH_CLOCK_REQ, 1, 1, QCH_CON_ASYNCSFR_WR_SMC_QCH),
|
|
SFR_ACCESS(QCH_CON_ASYNCSFR_WR_SMC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ASYNCSFR_WR_SMC_QCH),
|
|
SFR_ACCESS(QCH_CON_ASYNCSFR_WR_SMC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASYNCSFR_WR_SMC_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_VPC_QCH_ENABLE, 0, 1, QCH_CON_BAAW_P_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_VPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_P_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_VPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_P_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_VPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_P_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUS0_CMU_BUS0_QCH_ENABLE, 0, 1, QCH_CON_BUS0_CMU_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUS0_CMU_BUS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUS0_CMU_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUS0_CMU_BUS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUS0_CMU_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUS0_CMU_BUS0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUS0_CMU_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_CMUTOPC_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_CMUTOPC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_CMUTOPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_CMUTOPC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_CMUTOPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_CMUTOPC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_CMUTOPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_CMUTOPC_QCH),
|
|
SFR_ACCESS(QCH_CON_CACHEAID_BUS0_QCH_ENABLE, 0, 1, QCH_CON_CACHEAID_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_CACHEAID_BUS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_CACHEAID_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_CACHEAID_BUS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CACHEAID_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_CACHEAID_BUS0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CACHEAID_BUS0_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_BUS0_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_BUS0_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_BUS0_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_BUS0_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_BUS0_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_BUS0_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_BUS0_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_BUS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_BUS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_BUS0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D0_VPC_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D0_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D0_VPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D0_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D0_VPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D0_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D0_VPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D0_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D1_VPC_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D1_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D1_VPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D1_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D1_VPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D1_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D1_VPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D1_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D2_VPC_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D2_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D2_VPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D2_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D2_VPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D2_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D2_VPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D2_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_NPUS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D0_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_NPUS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D1_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_NPUS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D2_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D2_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D2_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D2_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MIF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MIF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MIF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_MIF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF2_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MIF2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MIF2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MIF2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_MIF2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF3_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MIF3_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF3_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MIF3_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MIF3_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_MIF3_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_NPU00_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_NPU00_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_NPU00_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_NPU00_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_NPU01_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_NPU01_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_NPU01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_NPU01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_NPU10_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_NPU10_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_NPU10_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_NPU10_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_NPUS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC2_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERISGIC_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_PERISGIC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERISGIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_PERISGIC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERISGIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_PERISGIC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERISGIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_PERISGIC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VPC_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUS0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUS0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D0_BUS0_QCH_ENABLE, 0, 1, QCH_CON_TREX_D0_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D0_BUS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D0_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D0_BUS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D0_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D0_BUS0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D0_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D1_BUS0_QCH_ENABLE, 0, 1, QCH_CON_TREX_D1_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D1_BUS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D1_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D1_BUS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D1_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D1_BUS0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D1_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_BUS0_QCH_ENABLE, 0, 1, QCH_CON_TREX_P_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_BUS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_BUS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_BUS0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_P_BUS0_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_VTS_QCH_ENABLE, 0, 1, QCH_CON_BAAW_P_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_P_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_P_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_P_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BUS1_CMU_BUS1_QCH_ENABLE, 0, 1, QCH_CON_BUS1_CMU_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUS1_CMU_BUS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUS1_CMU_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUS1_CMU_BUS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUS1_CMU_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUS1_CMU_BUS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUS1_CMU_BUS1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_BUS1_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_BUS1_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_BUS1_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_BUS1_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_BUS1_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_BUS1_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_DIT_QCH_ENABLE, 0, 1, QCH_CON_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_DIT_QCH_CLOCK_REQ, 1, 1, QCH_CON_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_DIT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_DIT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_BUS1_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_BUS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_BUS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_BUS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_HSI0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_DPUF0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_DPUF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_DPUF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_DPUF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D0_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_DPUF1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_DPUF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_DPUF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_DPUF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D0_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_DPUF0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_DPUF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_DPUF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_DPUF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D1_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_DPUF1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_DPUF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_DPUF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_DPUF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D1_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_APM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_SBIC_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_SBIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_SBIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_SBIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VTS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_SBIC_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_SBIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_SBIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_SBIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DPUB_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DPUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DPUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DPUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DPUF0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DPUF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DPUF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DPUF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DPUF1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DPUF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DPUF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_DPUF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_HSI0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VTS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_QCH_ENABLE, 0, 1, QCH_CON_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDMA_QCH_ENABLE, 0, 1, QCH_CON_QE_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDMA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_SPDMA_QCH_ENABLE, 0, 1, QCH_CON_QE_SPDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_SPDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_SPDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_SPDMA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_SPDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_SPDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_SPDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SBIC_QCH_ENABLE, 0, 1, QCH_CON_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SBIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SBIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SBIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SPDMA_QCH_ENABLE, 0, 1, QCH_CON_SPDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SPDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SPDMA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SPDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_S2_ACVPS_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_S2_ACVPS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_S2_ACVPS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_S2_ACVPS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_S2_ACVPS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_S2_ACVPS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_S2_ACVPS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_S2_ACVPS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_S2_DIT_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_S2_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_S2_DIT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_S2_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_S2_DIT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_S2_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_S2_DIT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_S2_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_S2_SBIC_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_S2_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_S2_SBIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_S2_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_S2_SBIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_S2_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_S2_SBIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_S2_SBIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUS1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_BUS1_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_BUS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_BUS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_BUS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_BUS1_QCH_ENABLE, 0, 1, QCH_CON_TREX_P_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_BUS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_BUS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_BUS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_P_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_RB_BUS1_QCH_ENABLE, 0, 1, QCH_CON_TREX_RB_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_RB_BUS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_RB_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_RB_BUS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_RB_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_RB_BUS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_RB_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_BUS1_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_BUS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_BUS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_BUS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_PDMA_QCH_ENABLE, 0, 1, QCH_CON_VGEN_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_PDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_PDMA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_PDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_BUS2_CMU_BUS2_QCH_ENABLE, 0, 1, QCH_CON_BUS2_CMU_BUS2_QCH),
|
|
SFR_ACCESS(QCH_CON_BUS2_CMU_BUS2_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUS2_CMU_BUS2_QCH),
|
|
SFR_ACCESS(QCH_CON_BUS2_CMU_BUS2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUS2_CMU_BUS2_QCH),
|
|
SFR_ACCESS(QCH_CON_BUS2_CMU_BUS2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUS2_CMU_BUS2_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_BUS2_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_BUS2_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_BUS2_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_BUS2_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_BUS2_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_BUS2_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_BUS2_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_BUS2_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_BUS2_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_BUS2_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_BUS2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_BUS2_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_BUS2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_BUS2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D0_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D0_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D0_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D0_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D0_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D0_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D0_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D0_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_HSI1_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_M2M_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_SSP_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_SSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_DNS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D0_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D0_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MFC0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MFC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D0_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MFC1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MFC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D0_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_DNS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D1_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D1_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MFC0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MFC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D1_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MFC1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MFC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D1_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D2_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D2_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D2_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D2_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D2_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D2_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D2_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D2_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D2_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D3_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D3_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D3_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D3_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D3_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D3_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D3_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D3_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D3_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D3_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D3_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D3_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D3_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D3_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D3_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D3_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_LME_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_LME_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_MCFP1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_MCFP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_MCFP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_MCFP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_TAA_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_HSI1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ITP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_LME_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_LME_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_M2M_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MFC0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MFC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MFC1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MFC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_SSP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_SSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_TAA_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUS2_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_BUS2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUS2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_BUS2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUS2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_BUS2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BUS2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_BUS2_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_BUS2_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_BUS2_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_BUS2_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_BUS2_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_BUS2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D_BUS2_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_BUS2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_BUS2_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_BUS2_QCH_ENABLE, 0, 1, QCH_CON_TREX_P_BUS2_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_BUS2_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P_BUS2_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_BUS2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P_BUS2_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_BUS2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_P_BUS2_QCH),
|
|
SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S0_ENABLE, 0, 1, QCH_CON_ADC_CMGP_QCH_S0),
|
|
SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S0_CLOCK_REQ, 1, 1, QCH_CON_ADC_CMGP_QCH_S0),
|
|
SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S0_EXPIRE_VAL, 16, 10, QCH_CON_ADC_CMGP_QCH_S0),
|
|
SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ADC_CMGP_QCH_S0),
|
|
SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S1_ENABLE, 0, 1, QCH_CON_ADC_CMGP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_ADC_CMGP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_ADC_CMGP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_ADC_CMGP_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ADC_CMGP_QCH_S1),
|
|
SFR_ACCESS(DMYQCH_CON_ADC_CMGP_QCH_OSC_ENABLE, 0, 1, DMYQCH_CON_ADC_CMGP_QCH_OSC),
|
|
SFR_ACCESS(DMYQCH_CON_ADC_CMGP_QCH_OSC_CLOCK_REQ, 1, 1, DMYQCH_CON_ADC_CMGP_QCH_OSC),
|
|
SFR_ACCESS(DMYQCH_CON_ADC_CMGP_QCH_OSC_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADC_CMGP_QCH_OSC),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_CMGP_QCH_ENABLE, 0, 1, QCH_CON_APBIF_GPIO_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_GPIO_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_GPIO_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_GPIO_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMGP_CMU_CMGP_QCH_ENABLE, 0, 1, QCH_CON_CMGP_CMU_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMGP_CMU_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMGP_CMU_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMGP_CMU_CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMGP_CMU_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMGP_CMU_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMGP_CMU_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CMGP_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_CMGP_QCH_ENABLE, 0, 1, QCH_CON_GPIO_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP0_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP1_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP2_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP2_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP3_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP3_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_I2C_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_I3C_CMGP_QCH_P_ENABLE, 0, 1, QCH_CON_I3C_CMGP_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C_CMGP_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_I3C_CMGP_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C_CMGP_QCH_P_EXPIRE_VAL, 16, 10, QCH_CON_I3C_CMGP_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C_CMGP_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C_CMGP_QCH_P),
|
|
SFR_ACCESS(DMYQCH_CON_I3C_CMGP_QCH_S_ENABLE, 0, 1, DMYQCH_CON_I3C_CMGP_QCH_S),
|
|
SFR_ACCESS(DMYQCH_CON_I3C_CMGP_QCH_S_CLOCK_REQ, 1, 1, DMYQCH_CON_I3C_CMGP_QCH_S),
|
|
SFR_ACCESS(DMYQCH_CON_I3C_CMGP_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_I3C_CMGP_QCH_S),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_C_CMGP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_C_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_C_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_C_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_C_CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_C_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_C_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_C_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2APM_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_AP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2PMU_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2PMU_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_AP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CMGP2PMU_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_AP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2PMU_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP0_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP1_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP2_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP2_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP3_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP3_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP3_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_TOP_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_TOP_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_TOP_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_TOP_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_TOP_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_TOP_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5),
|
|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D0_QCH_ENABLE, 0, 1, QCH_CON_ACE_SLICE_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_ACE_SLICE_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ACE_SLICE_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ACE_SLICE_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D1_QCH_ENABLE, 0, 1, QCH_CON_ACE_SLICE_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_ACE_SLICE_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ACE_SLICE_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ACE_SLICE_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D2_QCH_ENABLE, 0, 1, QCH_CON_ACE_SLICE_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D2_QCH_CLOCK_REQ, 1, 1, QCH_CON_ACE_SLICE_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ACE_SLICE_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ACE_SLICE_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D3_QCH_ENABLE, 0, 1, QCH_CON_ACE_SLICE_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D3_QCH_CLOCK_REQ, 1, 1, QCH_CON_ACE_SLICE_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ACE_SLICE_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_SLICE_G3D3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ACE_SLICE_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_CP_QCH_ENABLE, 0, 1, QCH_CON_BAAW_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_BDU_QCH_ENABLE, 0, 1, QCH_CON_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_BDU_QCH_CLOCK_REQ, 1, 1, QCH_CON_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_BDU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_BDU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BDU_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CCI_QCH_ENABLE, 0, 1, DMYQCH_CON_CCI_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CCI_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CCI_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CCI_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CCI_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CORE_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_CORE_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CORE_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_CORE_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CORE_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_CORE_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_CORE_CMU_CORE_QCH_ENABLE, 0, 1, QCH_CON_CORE_CMU_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_CORE_CMU_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_CORE_CMU_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_CORE_CMU_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CORE_CMU_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_CORE_CMU_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CORE_CMU_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CORE_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D2_MODEM_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D2_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D2_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D2_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D2_MODEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D2_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACEL_D2_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACEL_D2_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D0_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D0_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D0_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACE_D0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D0_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D0_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D0_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D0_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D0_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D0_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D0_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACE_D0_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D1_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D1_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D1_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACE_D1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D1_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D1_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D1_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D1_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D1_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D1_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D1_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACE_D1_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D2_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D2_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D2_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D2_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D2_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D2_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D2_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACE_D2_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D3_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D3_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D3_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D3_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D3_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D3_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ACE_D3_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ACE_D3_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MODEM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MODEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D0_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MODEM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MODEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D1_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_AUD_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T_BDU_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_T_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T_BDU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_T_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T_BDU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_T_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T_BDU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_T_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_AUD_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MODEM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MODEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_PPCFW_G3D_QCH_ENABLE, 0, 1, QCH_CON_PPCFW_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPCFW_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPCFW_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPCFW_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPCFW_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPCFW_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPCFW_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_CPUCL0_0_QCH_ENABLE, 0, 1, QCH_CON_PPC_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_CPUCL0_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_CPUCL0_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_CPUCL0_1_QCH_ENABLE, 0, 1, QCH_CON_PPC_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_CPUCL0_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_CPUCL0_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_G3D0_QCH_ENABLE, 0, 1, QCH_CON_PPC_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_G3D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_G3D0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_G3D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_G3D1_QCH_ENABLE, 0, 1, QCH_CON_PPC_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_G3D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_G3D1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_G3D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_G3D2_QCH_ENABLE, 0, 1, QCH_CON_PPC_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_G3D2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_G3D2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_G3D2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_G3D3_QCH_ENABLE, 0, 1, QCH_CON_PPC_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_G3D3_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_G3D3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_G3D3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_IRPS0_QCH_ENABLE, 0, 1, QCH_CON_PPC_IRPS0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_IRPS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_IRPS0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_IRPS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_IRPS0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_IRPS0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_IRPS0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_IRPS1_QCH_ENABLE, 0, 1, QCH_CON_PPC_IRPS1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_IRPS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_IRPS1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_IRPS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_IRPS1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_IRPS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_IRPS1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_IRPS2_QCH_ENABLE, 0, 1, QCH_CON_PPC_IRPS2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_IRPS2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_IRPS2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_IRPS2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_IRPS2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_IRPS2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_IRPS2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_IRPS3_QCH_ENABLE, 0, 1, QCH_CON_PPC_IRPS3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_IRPS3_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_IRPS3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_IRPS3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_IRPS3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_IRPS3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_IRPS3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D2_QCH_ENABLE, 0, 1, QCH_CON_PPMU_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D3_QCH_ENABLE, 0, 1, QCH_CON_PPMU_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D3_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G3D0_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G3D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G3D0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G3D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G3D1_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G3D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G3D1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G3D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G3D2_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G3D2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G3D2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G3D2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G3D3_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G3D3_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G3D3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_G3D3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MODEM_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MODEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CORE_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P0_CORE_QCH_ENABLE, 0, 1, QCH_CON_TREX_P0_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P0_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P0_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P0_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P0_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P0_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_P0_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P1_CORE_QCH_ENABLE, 0, 1, QCH_CON_TREX_P1_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P1_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P1_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P1_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P1_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P1_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_P1_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_MODEM_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_MODEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_MODEM_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_CPUCL0_0_QCH_ENABLE, 0, 1, DMYQCH_CON_ADD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_CPUCL0_0_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_ADD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_ADD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_ADD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_ADD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_0_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_STR_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_STR_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_STR_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_STR_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_ENABLE, 0, 1, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE, 0, 1, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL0_QCH_ENABLE, 0, 1, DMYQCH_CON_CPUCL0_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL0_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CPUCL0_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CPUCL0_CMU_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DDD_CPUCL0_0_QCH_ENABLE, 0, 1, DMYQCH_CON_DDD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DDD_CPUCL0_0_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_DDD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DDD_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DDD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_HTU_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_HTU_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HTU_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_0_QCH_ENABLE, 0, 1, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BPS_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_BPS_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_BPS_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BPS_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_BPS_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BPS_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_BPS_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BPS_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPM_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPM_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPM_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPM_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_ENABLE, 0, 1, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH),
|
|
SFR_ACCESS(QCH_CON_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T4_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T4_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T4_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T4_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T4_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T4_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T4_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_T4_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T5_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T5_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T5_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T5_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T5_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T5_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T5_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_T5_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T6_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T6_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T6_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T6_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T6_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T6_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T6_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_T6_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T7_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T7_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T7_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T7_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T7_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T7_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T7_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_T7_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T_BDU_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T_BDU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T_BDU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_ATB_T_BDU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_ATB_T_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_INT_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_G_INT_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_INT_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_G_INT_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_INT_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_G_INT_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_INT_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_G_INT_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_INT_ETR_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_G_INT_ETR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_INT_ETR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_G_INT_ETR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_INT_ETR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_G_INT_ETR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_INT_ETR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_G_INT_ETR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_INT_STM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_G_INT_STM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_INT_STM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_G_INT_STM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_INT_STM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_G_INT_STM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_INT_STM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_G_INT_STM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_INT_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_G_INT_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_INT_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_G_INT_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_INT_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_G_INT_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_INT_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_G_INT_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_INT_ETR_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_G_INT_ETR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_INT_ETR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_G_INT_ETR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_INT_ETR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_G_INT_ETR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_INT_ETR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_G_INT_ETR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_INT_STM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_G_INT_STM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_INT_STM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_G_INT_STM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_INT_STM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_G_INT_STM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_G_INT_STM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_G_INT_STM_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SECJTAG_QCH_ENABLE, 0, 1, QCH_CON_SECJTAG_QCH),
|
|
SFR_ACCESS(QCH_CON_SECJTAG_QCH_CLOCK_REQ, 1, 1, QCH_CON_SECJTAG_QCH),
|
|
SFR_ACCESS(QCH_CON_SECJTAG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SECJTAG_QCH),
|
|
SFR_ACCESS(QCH_CON_SECJTAG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SECJTAG_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_TREX_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_CPUCL0_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_CPUCL0_1_QCH_ENABLE, 0, 1, DMYQCH_CON_ADD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_CPUCL0_1_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_ADD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_ADD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_ADD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_ADD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_1_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_STR_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_STR_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_STR_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_STR_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_ENABLE, 0, 1, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE, 0, 1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_ENABLE, 0, 1, DMYQCH_CON_CPUCL1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CPUCL1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CPUCL1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_DDD_HC0_ENABLE, 0, 1, DMYQCH_CON_CPUCL1_QCH_DDD_HC0),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_DDD_HC0_CLOCK_REQ, 1, 1, DMYQCH_CON_CPUCL1_QCH_DDD_HC0),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_DDD_HC0_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CPUCL1_QCH_DDD_HC0),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_DDD_HC1_ENABLE, 0, 1, DMYQCH_CON_CPUCL1_QCH_DDD_HC1),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_DDD_HC1_CLOCK_REQ, 1, 1, DMYQCH_CON_CPUCL1_QCH_DDD_HC1),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_DDD_HC1_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CPUCL1_QCH_DDD_HC1),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_DDD_HC2_ENABLE, 0, 1, DMYQCH_CON_CPUCL1_QCH_DDD_HC2),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_DDD_HC2_CLOCK_REQ, 1, 1, DMYQCH_CON_CPUCL1_QCH_DDD_HC2),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_DDD_HC2_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CPUCL1_QCH_DDD_HC2),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CPUCL1_CMU_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_QCH_PCLK_ENABLE, 0, 1, QCH_CON_HTU_CPUCL1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_CPUCL1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_CPUCL1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_CPUCL1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_QCH_CLK_ENABLE, 0, 1, QCH_CON_HTU_CPUCL1_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_CPUCL1_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_QCH_CLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_CPUCL1_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_CPUCL1_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_2_QCH_ENABLE, 0, 1, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_2_QCH_CLOCK_REQ, 1, 1, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_3_QCH_ENABLE, 0, 1, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_3_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_3_QCH_CLOCK_REQ, 1, 1, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_3_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_3_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_3_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_4_QCH_ENABLE, 0, 1, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_4_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_4_QCH_CLOCK_REQ, 1, 1, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_4_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_4_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_4_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_4_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_4_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_CPUCL0_2_QCH_ENABLE, 0, 1, DMYQCH_CON_ADD_CPUCL0_2_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_CPUCL0_2_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADD_CPUCL0_2_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADD_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_ADD_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_ADD_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_ADD_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_ADD_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_2_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_STR_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_STR_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_STR_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_STR_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_ENABLE, 0, 1, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_ENABLE, 0, 1, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL2_QCH_ENABLE, 0, 1, DMYQCH_CON_CPUCL2_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL2_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CPUCL2_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CPUCL2_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CPUCL2_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL2_CMU_CPUCL2_QCH_ENABLE, 0, 1, QCH_CON_CPUCL2_CMU_CPUCL2_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL2_CMU_CPUCL2_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL2_CMU_CPUCL2_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL2_CMU_CPUCL2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CPUCL2_CMU_CPUCL2_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL2_CMU_CPUCL2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL2_CMU_CPUCL2_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DDD_CPUCL0_1_QCH_ENABLE, 0, 1, DMYQCH_CON_DDD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DDD_CPUCL0_1_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_DDD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DDD_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DDD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL2_QCH_PCLK_ENABLE, 0, 1, QCH_CON_HTU_CPUCL2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL2_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_CPUCL2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL2_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_CPUCL2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL2_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_CPUCL2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL2_QCH_CLK_ENABLE, 0, 1, QCH_CON_HTU_CPUCL2_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL2_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_CPUCL2_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL2_QCH_CLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_CPUCL2_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL2_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_CPUCL2_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_1_QCH_ENABLE, 0, 1, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_BUSIF_DDD_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HWACG_BUSIF_DDD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_CSISX6_QCH_VOTF0_ENABLE, 0, 1, QCH_CON_CSISX6_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_CSISX6_QCH_VOTF0_CLOCK_REQ, 1, 1, QCH_CON_CSISX6_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_CSISX6_QCH_VOTF0_EXPIRE_VAL, 16, 10, QCH_CON_CSISX6_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_CSISX6_QCH_VOTF0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSISX6_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_CSISX6_QCH_DMA_ENABLE, 0, 1, QCH_CON_CSISX6_QCH_DMA),
|
|
SFR_ACCESS(QCH_CON_CSISX6_QCH_DMA_CLOCK_REQ, 1, 1, QCH_CON_CSISX6_QCH_DMA),
|
|
SFR_ACCESS(QCH_CON_CSISX6_QCH_DMA_EXPIRE_VAL, 16, 10, QCH_CON_CSISX6_QCH_DMA),
|
|
SFR_ACCESS(QCH_CON_CSISX6_QCH_DMA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSISX6_QCH_DMA),
|
|
SFR_ACCESS(QCH_CON_CSISX6_QCH_MCB_ENABLE, 0, 1, QCH_CON_CSISX6_QCH_MCB),
|
|
SFR_ACCESS(QCH_CON_CSISX6_QCH_MCB_CLOCK_REQ, 1, 1, QCH_CON_CSISX6_QCH_MCB),
|
|
SFR_ACCESS(QCH_CON_CSISX6_QCH_MCB_EXPIRE_VAL, 16, 10, QCH_CON_CSISX6_QCH_MCB),
|
|
SFR_ACCESS(QCH_CON_CSISX6_QCH_MCB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSISX6_QCH_MCB),
|
|
SFR_ACCESS(QCH_CON_CSISX6_QCH_VOTF1_ENABLE, 0, 1, QCH_CON_CSISX6_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_CSISX6_QCH_VOTF1_CLOCK_REQ, 1, 1, QCH_CON_CSISX6_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_CSISX6_QCH_VOTF1_EXPIRE_VAL, 16, 10, QCH_CON_CSISX6_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_CSISX6_QCH_VOTF1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSISX6_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_CSIS_CMU_CSIS_QCH_ENABLE, 0, 1, QCH_CON_CSIS_CMU_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_CSIS_CMU_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_CSIS_CMU_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_CSIS_CMU_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CSIS_CMU_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_CSIS_CMU_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSIS_CMU_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CSIS_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF0_CSISPDP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_INT_OTF0_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF0_CSISPDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_INT_OTF0_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF0_CSISPDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_INT_OTF0_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF0_CSISPDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_INT_OTF0_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF0_PDPCSIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_INT_OTF0_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF0_PDPCSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_INT_OTF0_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF0_PDPCSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_INT_OTF0_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF0_PDPCSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_INT_OTF0_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF1_CSISPDP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_INT_OTF1_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF1_CSISPDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_INT_OTF1_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF1_CSISPDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_INT_OTF1_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF1_CSISPDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_INT_OTF1_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF1_PDPCSIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_INT_OTF1_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF1_PDPCSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_INT_OTF1_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF1_PDPCSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_INT_OTF1_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF1_PDPCSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_INT_OTF1_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF2_CSISPDP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_INT_OTF2_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF2_CSISPDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_INT_OTF2_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF2_CSISPDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_INT_OTF2_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF2_CSISPDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_INT_OTF2_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF2_PDPCSIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_INT_OTF2_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF2_PDPCSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_INT_OTF2_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF2_PDPCSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_INT_OTF2_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF2_PDPCSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_INT_OTF2_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF3_CSISPDP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_INT_OTF3_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF3_CSISPDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_INT_OTF3_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF3_CSISPDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_INT_OTF3_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF3_CSISPDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_INT_OTF3_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF3_PDPCSIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_INT_OTF3_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF3_PDPCSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_INT_OTF3_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF3_PDPCSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_INT_OTF3_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_OTF3_PDPCSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_INT_OTF3_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_VO_CSISPDP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_INT_VO_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_VO_CSISPDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_INT_VO_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_VO_CSISPDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_INT_VO_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_VO_CSISPDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_INT_VO_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_VO_PDPCSIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_INT_VO_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_VO_PDPCSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_INT_VO_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_VO_PDPCSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_INT_VO_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_INT_VO_PDPCSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_INT_VO_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_SOTF0_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_SOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_SOTF0_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_SOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_SOTF0_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_SOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_SOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_SOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_SOTF1_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_SOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_SOTF1_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_SOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_SOTF1_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_SOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_SOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_SOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_SOTF2_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_SOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_SOTF2_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_SOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_SOTF2_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_SOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_SOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_SOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_SOTF3_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_SOTF3_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_SOTF3_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_SOTF3_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_SOTF3_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_SOTF3_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_SOTF3_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_SOTF3_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ZOTF0_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_ZOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ZOTF0_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_ZOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ZOTF0_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_ZOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ZOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_ZOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ZOTF1_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_ZOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ZOTF1_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_ZOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ZOTF1_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_ZOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ZOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_ZOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ZOTF2_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_ZOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ZOTF2_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_ZOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ZOTF2_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_ZOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ZOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_ZOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ZOTF3_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_ZOTF3_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ZOTF3_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_ZOTF3_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ZOTF3_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_ZOTF3_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ZOTF3_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_ZOTF3_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF0_CSISPDP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_INT_OTF0_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF0_CSISPDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_INT_OTF0_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF0_CSISPDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_INT_OTF0_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF0_CSISPDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_INT_OTF0_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF0_PDPCSIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_INT_OTF0_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF0_PDPCSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_INT_OTF0_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF0_PDPCSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_INT_OTF0_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF0_PDPCSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_INT_OTF0_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF1_CSISPDP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_INT_OTF1_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF1_CSISPDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_INT_OTF1_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF1_CSISPDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_INT_OTF1_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF1_CSISPDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_INT_OTF1_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF1_PDPCSIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_INT_OTF1_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF1_PDPCSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_INT_OTF1_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF1_PDPCSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_INT_OTF1_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF1_PDPCSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_INT_OTF1_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF2_CSISPDP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_INT_OTF2_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF2_CSISPDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_INT_OTF2_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF2_CSISPDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_INT_OTF2_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF2_CSISPDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_INT_OTF2_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF2_PDPCSIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_INT_OTF2_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF2_PDPCSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_INT_OTF2_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF2_PDPCSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_INT_OTF2_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF2_PDPCSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_INT_OTF2_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF3_CSISPDP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_INT_OTF3_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF3_CSISPDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_INT_OTF3_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF3_CSISPDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_INT_OTF3_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF3_CSISPDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_INT_OTF3_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF3_PDPCSIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_INT_OTF3_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF3_PDPCSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_INT_OTF3_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF3_PDPCSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_INT_OTF3_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_OTF3_PDPCSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_INT_OTF3_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_VO_CSISPDP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_INT_VO_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_VO_CSISPDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_INT_VO_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_VO_CSISPDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_INT_VO_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_VO_CSISPDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_INT_VO_CSISPDP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_VO_PDPCSIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_INT_VO_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_VO_PDPCSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_INT_VO_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_VO_PDPCSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_INT_VO_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_INT_VO_PDPCSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_INT_VO_PDPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_CSISTAA_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF0_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_CSISTAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF0_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_CSISTAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF0_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_CSISTAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF0_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_CSISTAA_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF1_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_CSISTAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF1_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_CSISTAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF1_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_CSISTAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF1_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_CSISTAA_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF2_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_CSISTAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF2_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_CSISTAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF2_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_CSISTAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF2_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_CSISTAA_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF3_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_CSISTAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF3_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_CSISTAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF3_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_CSISTAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF3_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D2_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D2_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D2_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D2_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D3_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D3_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D3_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D3_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D3_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D3_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D3_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D3_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CSISPERIC1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_CSISPERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CSISPERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_CSISPERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CSISPERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_CSISPERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_CSISPERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_CSISPERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5),
|
|
SFR_ACCESS(QCH_CON_OIS_MCU_TOP_QCH_ENABLE, 0, 1, QCH_CON_OIS_MCU_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_OIS_MCU_TOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_OIS_MCU_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_OIS_MCU_TOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_OIS_MCU_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_OIS_MCU_TOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_OIS_MCU_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_PDP_TOP_QCH_PDP_TOP_ENABLE, 0, 1, QCH_CON_PDP_TOP_QCH_PDP_TOP),
|
|
SFR_ACCESS(QCH_CON_PDP_TOP_QCH_PDP_TOP_CLOCK_REQ, 1, 1, QCH_CON_PDP_TOP_QCH_PDP_TOP),
|
|
SFR_ACCESS(QCH_CON_PDP_TOP_QCH_PDP_TOP_EXPIRE_VAL, 16, 10, QCH_CON_PDP_TOP_QCH_PDP_TOP),
|
|
SFR_ACCESS(QCH_CON_PDP_TOP_QCH_PDP_TOP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PDP_TOP_QCH_PDP_TOP),
|
|
SFR_ACCESS(QCH_CON_PDP_TOP_QCH_C2_PDP_ENABLE, 0, 1, QCH_CON_PDP_TOP_QCH_C2_PDP),
|
|
SFR_ACCESS(QCH_CON_PDP_TOP_QCH_C2_PDP_CLOCK_REQ, 1, 1, QCH_CON_PDP_TOP_QCH_C2_PDP),
|
|
SFR_ACCESS(QCH_CON_PDP_TOP_QCH_C2_PDP_EXPIRE_VAL, 16, 10, QCH_CON_PDP_TOP_QCH_C2_PDP),
|
|
SFR_ACCESS(QCH_CON_PDP_TOP_QCH_C2_PDP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PDP_TOP_QCH_C2_PDP),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D2_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D3_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D3_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA0_QCH_ENABLE, 0, 1, QCH_CON_QE_CSIS_DMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_CSIS_DMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_CSIS_DMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_CSIS_DMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA1_QCH_ENABLE, 0, 1, QCH_CON_QE_CSIS_DMA1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_CSIS_DMA1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_CSIS_DMA1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_CSIS_DMA1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA2_QCH_ENABLE, 0, 1, QCH_CON_QE_CSIS_DMA2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_CSIS_DMA2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_CSIS_DMA2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_CSIS_DMA2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA3_QCH_ENABLE, 0, 1, QCH_CON_QE_CSIS_DMA3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA3_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_CSIS_DMA3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_CSIS_DMA3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_DMA3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_CSIS_DMA3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF1_QCH_ENABLE, 0, 1, QCH_CON_QE_PDP_AF1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDP_AF1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PDP_AF1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDP_AF1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF2_QCH_ENABLE, 0, 1, QCH_CON_QE_PDP_AF2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDP_AF2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PDP_AF2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_AF2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDP_AF2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_AF0_QCH_ENABLE, 0, 1, QCH_CON_QE_PDP_STAT_AF0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_AF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDP_STAT_AF0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_AF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PDP_STAT_AF0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_AF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDP_STAT_AF0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG0_QCH_ENABLE, 0, 1, QCH_CON_QE_PDP_STAT_IMG0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDP_STAT_IMG0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PDP_STAT_IMG0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDP_STAT_IMG0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG1_QCH_ENABLE, 0, 1, QCH_CON_QE_PDP_STAT_IMG1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDP_STAT_IMG1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PDP_STAT_IMG1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDP_STAT_IMG1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG2_QCH_ENABLE, 0, 1, QCH_CON_QE_PDP_STAT_IMG2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDP_STAT_IMG2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PDP_STAT_IMG2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_STAT_IMG2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDP_STAT_IMG2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP0_QCH_ENABLE, 0, 1, QCH_CON_QE_STRP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_STRP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_STRP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_STRP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP1_QCH_ENABLE, 0, 1, QCH_CON_QE_STRP1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_STRP1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_STRP1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_STRP1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP2_QCH_ENABLE, 0, 1, QCH_CON_QE_STRP2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_STRP2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_STRP2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_STRP2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP3_QCH_ENABLE, 0, 1, QCH_CON_QE_STRP3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP3_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_STRP3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_STRP3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRP3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_STRP3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL0_QCH_ENABLE, 0, 1, QCH_CON_QE_ZSL0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_ZSL0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_ZSL0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_ZSL0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL1_QCH_ENABLE, 0, 1, QCH_CON_QE_ZSL1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_ZSL1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_ZSL1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_ZSL1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL2_QCH_ENABLE, 0, 1, QCH_CON_QE_ZSL2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_ZSL2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_ZSL2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_ZSL2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL3_QCH_ENABLE, 0, 1, QCH_CON_QE_ZSL3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL3_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_ZSL3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_ZSL3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ZSL3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_ZSL3_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D2_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D2_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_CSIS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D3_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_CSIS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D3_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_CSIS_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D3_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_CSIS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D3_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_CSIS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D3_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_CSIS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D3_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_CSIS_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D3_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_CSIS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D3_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CSIS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_D1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D2_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D2_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D2_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D2_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_D2_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D2_QCH),
|
|
SFR_ACCESS(QCH_CON_DNS_QCH_ENABLE, 0, 1, QCH_CON_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_DNS_QCH_VOTF0_ENABLE, 0, 1, QCH_CON_DNS_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_DNS_QCH_VOTF0_CLOCK_REQ, 1, 1, QCH_CON_DNS_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_DNS_QCH_VOTF0_EXPIRE_VAL, 16, 10, QCH_CON_DNS_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_DNS_QCH_VOTF0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DNS_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_DNS_QCH_VOTF1_ENABLE, 0, 1, QCH_CON_DNS_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_DNS_QCH_VOTF1_CLOCK_REQ, 1, 1, QCH_CON_DNS_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_DNS_QCH_VOTF1_EXPIRE_VAL, 16, 10, QCH_CON_DNS_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_DNS_QCH_VOTF1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DNS_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_DNS_QCH_VOTF2_ENABLE, 0, 1, QCH_CON_DNS_QCH_VOTF2),
|
|
SFR_ACCESS(QCH_CON_DNS_QCH_VOTF2_CLOCK_REQ, 1, 1, QCH_CON_DNS_QCH_VOTF2),
|
|
SFR_ACCESS(QCH_CON_DNS_QCH_VOTF2_EXPIRE_VAL, 16, 10, QCH_CON_DNS_QCH_VOTF2),
|
|
SFR_ACCESS(QCH_CON_DNS_QCH_VOTF2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DNS_QCH_VOTF2),
|
|
SFR_ACCESS(QCH_CON_DNS_CMU_DNS_QCH_ENABLE, 0, 1, QCH_CON_DNS_CMU_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_DNS_CMU_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_DNS_CMU_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_DNS_CMU_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DNS_CMU_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_DNS_CMU_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DNS_CMU_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DNS_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_CTL_ITPDNS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_CTL_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_CTL_ITPDNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_CTL_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_CTL_ITPDNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_CTL_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_CTL_ITPDNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_CTL_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_ITPDNS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF0_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_ITPDNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF0_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_ITPDNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF0_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_ITPDNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF0_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_ITPDNS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF1_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_ITPDNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF1_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_ITPDNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF1_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_ITPDNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF1_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_ITPDNS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF2_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_ITPDNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF2_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_ITPDNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF2_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_ITPDNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF2_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_ITPDNS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF3_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_ITPDNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF3_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_ITPDNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF3_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_ITPDNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF3_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF4_ITPDNS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF4_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF4_ITPDNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF4_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF4_ITPDNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF4_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF4_ITPDNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF4_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_MCFP1DNS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF_MCFP1DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_MCFP1DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF_MCFP1DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_MCFP1DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF_MCFP1DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_MCFP1DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF_MCFP1DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_TAADNS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF_TAADNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_TAADNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF_TAADNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_TAADNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF_TAADNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_TAADNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF_TAADNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ITPDNS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ITPDNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ITPDNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ITPDNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_CTL_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_CTL_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_CTL_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_CTL_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_CTL_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_CTL_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_CTL_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_CTL_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF0_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF0_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF0_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF0_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF1_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF1_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF1_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF1_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF2_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF2_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF2_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF2_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF3_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF3_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF3_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF3_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF4_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF4_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF4_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF4_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF4_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF4_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF4_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF4_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF5_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF5_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF5_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF5_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF5_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF5_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF5_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF5_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF6_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF6_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF6_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF6_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF6_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF6_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF6_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF6_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF7_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF7_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF7_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF7_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF7_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF7_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF7_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF7_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF8_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF8_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF8_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF8_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF8_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF8_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF8_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF8_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF9_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF9_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF9_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF9_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF9_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF9_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF9_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF9_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_DNS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D0_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_DNS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_DNS_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D0_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_DNS_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D1_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DNS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_DNS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DNS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_DNS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DNS_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_DNS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DNS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_DNS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DNS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_DNS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DNS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_DNS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DNS_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_DNS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DNS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_DNS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DNS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_DNS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DNS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_DNS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DNS_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_DNS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DNS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_DNS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DNS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_DNS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DNS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_DNS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DNS_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_DNS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DNS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_DNS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DNS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_DNS_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D0_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D0_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_D0_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D0_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_DNS_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D1_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D1_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_D1_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D1_DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_ENABLE, 0, 1, QCH_CON_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUB_CMU_DPUB_QCH_ENABLE, 0, 1, QCH_CON_DPUB_CMU_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUB_CMU_DPUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_DPUB_CMU_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUB_CMU_DPUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DPUB_CMU_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUB_CMU_DPUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUB_CMU_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUB_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DPUB_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DPUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DPUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DPUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUB_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUF0_QCH_DMA_ENABLE, 0, 1, QCH_CON_DPUF0_QCH_DMA),
|
|
SFR_ACCESS(QCH_CON_DPUF0_QCH_DMA_CLOCK_REQ, 1, 1, QCH_CON_DPUF0_QCH_DMA),
|
|
SFR_ACCESS(QCH_CON_DPUF0_QCH_DMA_EXPIRE_VAL, 16, 10, QCH_CON_DPUF0_QCH_DMA),
|
|
SFR_ACCESS(QCH_CON_DPUF0_QCH_DMA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUF0_QCH_DMA),
|
|
SFR_ACCESS(QCH_CON_DPUF0_QCH_DPP_ENABLE, 0, 1, QCH_CON_DPUF0_QCH_DPP),
|
|
SFR_ACCESS(QCH_CON_DPUF0_QCH_DPP_CLOCK_REQ, 1, 1, QCH_CON_DPUF0_QCH_DPP),
|
|
SFR_ACCESS(QCH_CON_DPUF0_QCH_DPP_EXPIRE_VAL, 16, 10, QCH_CON_DPUF0_QCH_DPP),
|
|
SFR_ACCESS(QCH_CON_DPUF0_QCH_DPP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUF0_QCH_DPP),
|
|
SFR_ACCESS(QCH_CON_DPUF0_QCH_C2SERV_ENABLE, 0, 1, QCH_CON_DPUF0_QCH_C2SERV),
|
|
SFR_ACCESS(QCH_CON_DPUF0_QCH_C2SERV_CLOCK_REQ, 1, 1, QCH_CON_DPUF0_QCH_C2SERV),
|
|
SFR_ACCESS(QCH_CON_DPUF0_QCH_C2SERV_EXPIRE_VAL, 16, 10, QCH_CON_DPUF0_QCH_C2SERV),
|
|
SFR_ACCESS(QCH_CON_DPUF0_QCH_C2SERV_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUF0_QCH_C2SERV),
|
|
SFR_ACCESS(QCH_CON_DPUF0_CMU_DPUF0_QCH_ENABLE, 0, 1, QCH_CON_DPUF0_CMU_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUF0_CMU_DPUF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_DPUF0_CMU_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUF0_CMU_DPUF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DPUF0_CMU_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUF0_CMU_DPUF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUF0_CMU_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUF0_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_DPUF1DPUF0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_DPUF1DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_DPUF1DPUF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_DPUF1DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_DPUF1DPUF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_DPUF1DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_DPUF1DPUF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_DPUF1DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DPUF0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DPUF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DPUF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DPUF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_DPUF0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_DPUF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_DPUF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_DPUF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D0_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_DPUF0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_DPUF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_DPUF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_DPUF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF0D0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_DPUF0D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF0D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_DPUF0D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF0D0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_DPUF0D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF0D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_DPUF0D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF0D1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_DPUF0D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF0D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_DPUF0D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF0D1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_DPUF0D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF0D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_DPUF0D1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF0D0_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUF0D0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF0D0_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUF0D0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF0D0_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUF0D0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF0D0_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUF0D0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF0D0_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUF0D0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF0D0_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUF0D0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF0D0_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUF0D0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF0D0_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUF0D0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF0D1_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUF0D1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF0D1_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUF0D1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF0D1_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUF0D1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF0D1_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUF0D1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF0D1_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUF0D1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF0D1_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUF0D1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF0D1_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUF0D1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF0D1_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUF0D1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUF0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUF1_QCH_DMA_ENABLE, 0, 1, QCH_CON_DPUF1_QCH_DMA),
|
|
SFR_ACCESS(QCH_CON_DPUF1_QCH_DMA_CLOCK_REQ, 1, 1, QCH_CON_DPUF1_QCH_DMA),
|
|
SFR_ACCESS(QCH_CON_DPUF1_QCH_DMA_EXPIRE_VAL, 16, 10, QCH_CON_DPUF1_QCH_DMA),
|
|
SFR_ACCESS(QCH_CON_DPUF1_QCH_DMA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUF1_QCH_DMA),
|
|
SFR_ACCESS(QCH_CON_DPUF1_QCH_DPP_ENABLE, 0, 1, QCH_CON_DPUF1_QCH_DPP),
|
|
SFR_ACCESS(QCH_CON_DPUF1_QCH_DPP_CLOCK_REQ, 1, 1, QCH_CON_DPUF1_QCH_DPP),
|
|
SFR_ACCESS(QCH_CON_DPUF1_QCH_DPP_EXPIRE_VAL, 16, 10, QCH_CON_DPUF1_QCH_DPP),
|
|
SFR_ACCESS(QCH_CON_DPUF1_QCH_DPP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUF1_QCH_DPP),
|
|
SFR_ACCESS(QCH_CON_DPUF1_QCH_C2SERV_ENABLE, 0, 1, QCH_CON_DPUF1_QCH_C2SERV),
|
|
SFR_ACCESS(QCH_CON_DPUF1_QCH_C2SERV_CLOCK_REQ, 1, 1, QCH_CON_DPUF1_QCH_C2SERV),
|
|
SFR_ACCESS(QCH_CON_DPUF1_QCH_C2SERV_EXPIRE_VAL, 16, 10, QCH_CON_DPUF1_QCH_C2SERV),
|
|
SFR_ACCESS(QCH_CON_DPUF1_QCH_C2SERV_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUF1_QCH_C2SERV),
|
|
SFR_ACCESS(QCH_CON_DPUF1_CMU_DPUF1_QCH_ENABLE, 0, 1, QCH_CON_DPUF1_CMU_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUF1_CMU_DPUF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_DPUF1_CMU_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUF1_CMU_DPUF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DPUF1_CMU_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUF1_CMU_DPUF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUF1_CMU_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUF1_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DPUF1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DPUF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DPUF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_DPUF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_DPUF1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_DPUF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_DPUF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_DPUF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D0_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_DPUF1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_DPUF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_DPUF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_DPUF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_DPUF1DPUF0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_DPUF1DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_DPUF1DPUF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_DPUF1DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_DPUF1DPUF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_DPUF1DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_DPUF1DPUF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_DPUF1DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF1D0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_DPUF1D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF1D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_DPUF1D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF1D0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_DPUF1D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF1D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_DPUF1D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF1D1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_DPUF1D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF1D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_DPUF1D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF1D1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_DPUF1D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF1D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_DPUF1D1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D0_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUF1D0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D0_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUF1D0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D0_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUF1D0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D0_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUF1D0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D0_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUF1D0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D0_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUF1D0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D0_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUF1D0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D0_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUF1D0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D1_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUF1D1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D1_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUF1D1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D1_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUF1D1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D1_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUF1D1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D1_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUF1D1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D1_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUF1D1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D1_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUF1D1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D1_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUF1D1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUF1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_US_128TO256_D0_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_ACE_US_128TO256_D0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_US_128TO256_D0_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_ACE_US_128TO256_D0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_US_128TO256_D0_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ACE_US_128TO256_D0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_US_128TO256_D0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ACE_US_128TO256_D0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_US_128TO256_D1_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_ACE_US_128TO256_D1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_US_128TO256_D1_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_ACE_US_128TO256_D1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_US_128TO256_D1_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ACE_US_128TO256_D1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_ACE_US_128TO256_D1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ACE_US_128TO256_D1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_3_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_STR_CPUCL0_3_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_STR_CPUCL0_3_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_STR_CPUCL0_3_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_STR_CPUCL0_3_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_ENABLE, 0, 1, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_SCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_SCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_SCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_SCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_SCLK_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_SCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_SCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_SCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_ATCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_ATCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_ATCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_ATCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_ATCLK_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_ATCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_ATCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_ATCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PDBGCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_PDBGCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PDBGCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_PDBGCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PDBGCLK_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_PDBGCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PDBGCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_PDBGCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_GICCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_GICCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_GICCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_GICCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_GICCLK_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_GICCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_GICCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_GICCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_DBG_PD_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_DBG_PD),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_DBG_PD_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_DBG_PD),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_DBG_PD_EXPIRE_VAL, 16, 4, QCH_CON_CLUSTER0_QCH_DBG_PD),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_DBG_PD_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_DBG_PD),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_ENABLE, 0, 1, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK),
|
|
SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK),
|
|
SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_DSU_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_DSU_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_DSU_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_DSU_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_DSU_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_DSU_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_DSU_SHORTSTOP_QCH_ENABLE, 0, 1, QCH_CON_CMU_DSU_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_DSU_SHORTSTOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMU_DSU_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_DSU_SHORTSTOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMU_DSU_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMU_DSU_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMU_DSU_SHORTSTOP_QCH),
|
|
SFR_ACCESS(QCH_CON_DSU_CMU_DSU_QCH_ENABLE, 0, 1, QCH_CON_DSU_CMU_DSU_QCH),
|
|
SFR_ACCESS(QCH_CON_DSU_CMU_DSU_QCH_CLOCK_REQ, 1, 1, QCH_CON_DSU_CMU_DSU_QCH),
|
|
SFR_ACCESS(QCH_CON_DSU_CMU_DSU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DSU_CMU_DSU_QCH),
|
|
SFR_ACCESS(QCH_CON_DSU_CMU_DSU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DSU_CMU_DSU_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_DSU_QCH_ENABLE, 0, 1, QCH_CON_HTU_DSU_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_DSU_QCH_CLOCK_REQ, 1, 1, QCH_CON_HTU_DSU_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_DSU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HTU_DSU_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_DSU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_DSU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_IRI_GICCPU_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_IRI_GICCPU_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_IRI_GICCPU_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_IRI_GICCPU_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_IRI_GICCPU_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_IRI_GICCPU_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_IRI_GICCPU_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_IRI_GICCPU_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D0_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACE_D0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D0_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACE_D0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D0_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACE_D0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACE_D0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D1_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACE_D1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D1_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACE_D1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D1_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACE_D1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACE_D1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACE_D1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ICC_CPUGIC_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_ICC_CPUGIC_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ICC_CPUGIC_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_ICC_CPUGIC_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ICC_CPUGIC_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_ICC_CPUGIC_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ICC_CPUGIC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_ICC_CPUGIC_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T4_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_T4_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T4_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_T4_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T4_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_T4_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T4_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_T4_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T5_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_T5_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T5_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_T5_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T5_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_T5_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T5_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_T5_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T6_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_T6_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T6_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_T6_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T6_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_T6_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T6_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_T6_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T7_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_T7_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T7_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_T7_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T7_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_T7_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ATB_T7_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ATB_T7_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_ENABLE, 0, 1, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_ENABLE, 0, 1, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_ENABLE, 0, 1, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_ENABLE, 0, 1, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_ADD_APBIF_G3D_QCH_ENABLE, 0, 1, QCH_CON_ADD_APBIF_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_ADD_APBIF_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_ADD_APBIF_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_ADD_APBIF_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ADD_APBIF_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_ADD_APBIF_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ADD_APBIF_G3D_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_G3D_QCH_ENABLE, 0, 1, DMYQCH_CON_ADD_G3D_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_G3D_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADD_G3D_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADD_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D0_G3D_ENABLE, 0, 1, QCH_CON_ASB_G3D_QCH_LH_D0_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D0_G3D_CLOCK_REQ, 1, 1, QCH_CON_ASB_G3D_QCH_LH_D0_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D0_G3D_EXPIRE_VAL, 16, 10, QCH_CON_ASB_G3D_QCH_LH_D0_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D0_G3D_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASB_G3D_QCH_LH_D0_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D1_G3D_ENABLE, 0, 1, QCH_CON_ASB_G3D_QCH_LH_D1_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D1_G3D_CLOCK_REQ, 1, 1, QCH_CON_ASB_G3D_QCH_LH_D1_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D1_G3D_EXPIRE_VAL, 16, 10, QCH_CON_ASB_G3D_QCH_LH_D1_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D1_G3D_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASB_G3D_QCH_LH_D1_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D2_G3D_ENABLE, 0, 1, QCH_CON_ASB_G3D_QCH_LH_D2_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D2_G3D_CLOCK_REQ, 1, 1, QCH_CON_ASB_G3D_QCH_LH_D2_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D2_G3D_EXPIRE_VAL, 16, 10, QCH_CON_ASB_G3D_QCH_LH_D2_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D2_G3D_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASB_G3D_QCH_LH_D2_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D3_G3D_ENABLE, 0, 1, QCH_CON_ASB_G3D_QCH_LH_D3_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D3_G3D_CLOCK_REQ, 1, 1, QCH_CON_ASB_G3D_QCH_LH_D3_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D3_G3D_EXPIRE_VAL, 16, 10, QCH_CON_ASB_G3D_QCH_LH_D3_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D3_G3D_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASB_G3D_QCH_LH_D3_G3D),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPMG3D_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMG3D_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPMG3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMG3D_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPMG3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMG3D_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPMG3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPMG3D_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_G3D_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_STR_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_STR_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_STR_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_STR_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_G3D_QCH_CORE_ENABLE, 0, 1, QCH_CON_BUSIF_STR_G3D_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_G3D_QCH_CORE_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_STR_G3D_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_G3D_QCH_CORE_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_STR_G3D_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_G3D_QCH_CORE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_STR_G3D_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_G3D_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_ENABLE, 0, 1, QCH_CON_G3D_CMU_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_G3D_CMU_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_G3D_CMU_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_G3D_CMU_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_GPU_QCH_ENABLE, 0, 1, QCH_CON_GPU_QCH),
|
|
SFR_ACCESS(QCH_CON_GPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPU_QCH),
|
|
SFR_ACCESS(QCH_CON_GPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPU_QCH),
|
|
SFR_ACCESS(QCH_CON_GPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPU_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_PCLK_ENABLE, 0, 1, QCH_CON_HTU_G3D_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_G3D_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_G3D_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_G3D_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_CLK_ENABLE, 0, 1, QCH_CON_HTU_G3D_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_G3D_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_CLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_G3D_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_G3D_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_INT_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_INT_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_INT_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_INT_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_INT_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_INT_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_INT_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_INT_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_INT_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_INT_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_INT_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_INT_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_INT_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_INT_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_INT_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_INT_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_G3D_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DP_LINK_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DP_LINK_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DP_LINK_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DP_LINK_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_GTC_CLK_ENABLE, 0, 1, QCH_CON_DP_LINK_QCH_GTC_CLK),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_GTC_CLK_CLOCK_REQ, 1, 1, QCH_CON_DP_LINK_QCH_GTC_CLK),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_GTC_CLK_EXPIRE_VAL, 16, 10, QCH_CON_DP_LINK_QCH_GTC_CLK),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_GTC_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DP_LINK_QCH_GTC_CLK),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_HSI0_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_HSI0_CMU_HSI0_QCH_ENABLE, 0, 1, QCH_CON_HSI0_CMU_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_HSI0_CMU_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_HSI0_CMU_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_HSI0_CMU_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HSI0_CMU_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_HSI0_CMU_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HSI0_CMU_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_AUDHSI0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_AUDHSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_AUDHSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_AUDHSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_AUDHSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_AUDHSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_AUDHSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_AUDHSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_HSI0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_HSI0_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_HSI0AUD_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_HSI0AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_HSI0AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_HSI0AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_HSI0AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_HSI0AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_HSI0AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_HSI0AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_HSI0_BUS1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_HSI0_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_HSI0_BUS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_HSI0_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_HSI0_BUS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_HSI0_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_HSI0_BUS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_HSI0_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_USB_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_USB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_HSI0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_HSI0_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_USB31DRD_QCH_REF_ENABLE, 0, 1, DMYQCH_CON_USB31DRD_QCH_REF),
|
|
SFR_ACCESS(DMYQCH_CON_USB31DRD_QCH_REF_CLOCK_REQ, 1, 1, DMYQCH_CON_USB31DRD_QCH_REF),
|
|
SFR_ACCESS(DMYQCH_CON_USB31DRD_QCH_REF_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_USB31DRD_QCH_REF),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_SLV_CTRL_ENABLE, 0, 1, QCH_CON_USB31DRD_QCH_SLV_CTRL),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_SLV_CTRL_CLOCK_REQ, 1, 1, QCH_CON_USB31DRD_QCH_SLV_CTRL),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_SLV_CTRL_EXPIRE_VAL, 16, 10, QCH_CON_USB31DRD_QCH_SLV_CTRL),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_SLV_CTRL_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB31DRD_QCH_SLV_CTRL),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_SLV_LINK_ENABLE, 0, 1, QCH_CON_USB31DRD_QCH_SLV_LINK),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_SLV_LINK_CLOCK_REQ, 1, 1, QCH_CON_USB31DRD_QCH_SLV_LINK),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_SLV_LINK_EXPIRE_VAL, 16, 10, QCH_CON_USB31DRD_QCH_SLV_LINK),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_SLV_LINK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB31DRD_QCH_SLV_LINK),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_APB_ENABLE, 0, 1, QCH_CON_USB31DRD_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_APB_CLOCK_REQ, 1, 1, QCH_CON_USB31DRD_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_APB_EXPIRE_VAL, 16, 10, QCH_CON_USB31DRD_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB31DRD_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_PCS_ENABLE, 0, 1, QCH_CON_USB31DRD_QCH_PCS),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_PCS_CLOCK_REQ, 1, 1, QCH_CON_USB31DRD_QCH_PCS),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_PCS_EXPIRE_VAL, 16, 10, QCH_CON_USB31DRD_QCH_PCS),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_PCS_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB31DRD_QCH_PCS),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_DBG_ENABLE, 0, 1, QCH_CON_USB31DRD_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_DBG_CLOCK_REQ, 1, 1, QCH_CON_USB31DRD_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_DBG_EXPIRE_VAL, 16, 10, QCH_CON_USB31DRD_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_USB31DRD_QCH_DBG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB31DRD_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_HSI0_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_HSI1_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_HSI1_QCH_ENABLE, 0, 1, QCH_CON_GPIO_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_HSI1_CMU_HSI1_QCH_ENABLE, 0, 1, QCH_CON_HSI1_CMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_HSI1_CMU_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_HSI1_CMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_HSI1_CMU_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HSI1_CMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_HSI1_CMU_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HSI1_CMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_HSI1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_HSI1_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_MMC_CARD_QCH_ENABLE, 0, 1, QCH_CON_MMC_CARD_QCH),
|
|
SFR_ACCESS(QCH_CON_MMC_CARD_QCH_CLOCK_REQ, 1, 1, QCH_CON_MMC_CARD_QCH),
|
|
SFR_ACCESS(QCH_CON_MMC_CARD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MMC_CARD_QCH),
|
|
SFR_ACCESS(QCH_CON_MMC_CARD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MMC_CARD_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_MSTR_ENABLE, 0, 1, QCH_CON_PCIE_GEN2_QCH_MSTR),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_MSTR_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN2_QCH_MSTR),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_MSTR_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN2_QCH_MSTR),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_MSTR_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN2_QCH_MSTR),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PCS_ENABLE, 0, 1, QCH_CON_PCIE_GEN2_QCH_PCS),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PCS_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN2_QCH_PCS),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PCS_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN2_QCH_PCS),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PCS_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN2_QCH_PCS),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PHY_ENABLE, 0, 1, QCH_CON_PCIE_GEN2_QCH_PHY),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PHY_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN2_QCH_PHY),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PHY_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN2_QCH_PHY),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PHY_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN2_QCH_PHY),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_DBI_ENABLE, 0, 1, QCH_CON_PCIE_GEN2_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_DBI_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN2_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_DBI_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN2_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_DBI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN2_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_APB_ENABLE, 0, 1, QCH_CON_PCIE_GEN2_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN2_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_APB_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN2_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN2_QCH_APB),
|
|
SFR_ACCESS(DMYQCH_CON_PCIE_GEN2_QCH_REF_ENABLE, 0, 1, DMYQCH_CON_PCIE_GEN2_QCH_REF),
|
|
SFR_ACCESS(DMYQCH_CON_PCIE_GEN2_QCH_REF_CLOCK_REQ, 1, 1, DMYQCH_CON_PCIE_GEN2_QCH_REF),
|
|
SFR_ACCESS(DMYQCH_CON_PCIE_GEN2_QCH_REF_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_PCIE_GEN2_QCH_REF),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_APB_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_0_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_0_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_APB_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_0_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_0_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_DBI_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_0_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_DBI_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_0_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_DBI_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_0_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_DBI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_0_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_AXI_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_0_QCH_AXI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_AXI_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_0_QCH_AXI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_AXI_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_0_QCH_AXI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_AXI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_0_QCH_AXI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_0_QCH_PCS_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_0_QCH_PCS_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_0_QCH_PCS_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_0_QCH_PCS_APB),
|
|
SFR_ACCESS(DMYQCH_CON_PCIE_GEN4_0_QCH_REF_ENABLE, 0, 1, DMYQCH_CON_PCIE_GEN4_0_QCH_REF),
|
|
SFR_ACCESS(DMYQCH_CON_PCIE_GEN4_0_QCH_REF_CLOCK_REQ, 1, 1, DMYQCH_CON_PCIE_GEN4_0_QCH_REF),
|
|
SFR_ACCESS(DMYQCH_CON_PCIE_GEN4_0_QCH_REF_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_PCIE_GEN4_0_QCH_REF),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_0_QCH_PMA_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_0_QCH_PMA_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_0_QCH_PMA_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_0_QCH_PMA_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_UDBG_APB_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_0_QCH_UDBG_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_UDBG_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_0_QCH_UDBG_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_UDBG_APB_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_0_QCH_UDBG_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_UDBG_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_0_QCH_UDBG_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN2_QCH_ENABLE, 0, 1, QCH_CON_PCIE_IA_GEN2_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PCIE_IA_GEN2_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_IA_GEN2_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_IA_GEN2_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN4_0_QCH_ENABLE, 0, 1, QCH_CON_PCIE_IA_GEN4_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN4_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PCIE_IA_GEN4_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN4_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_IA_GEN4_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN4_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_IA_GEN4_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_HSI1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_HSI1_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_HSI1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_ENABLE, 0, 1, QCH_CON_UFS_EMBD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_CLOCK_REQ, 1, 1, QCH_CON_UFS_EMBD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UFS_EMBD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UFS_EMBD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_ENABLE, 0, 1, QCH_CON_UFS_EMBD_QCH_FMP),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ, 1, 1, QCH_CON_UFS_EMBD_QCH_FMP),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_EXPIRE_VAL, 16, 10, QCH_CON_UFS_EMBD_QCH_FMP),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UFS_EMBD_QCH_FMP),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_HSI1_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_ITP_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_ITP_QCH_ENABLE, 0, 1, QCH_CON_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_ITP_CMU_ITP_QCH_ENABLE, 0, 1, QCH_CON_ITP_CMU_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_ITP_CMU_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_ITP_CMU_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_ITP_CMU_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ITP_CMU_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_ITP_CMU_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ITP_CMU_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_CTL_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_CTL_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_CTL_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_CTL_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_CTL_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_CTL_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_CTL_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_CTL_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF0_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF0_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF0_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF0_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF1_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF1_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF1_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF1_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF2_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF2_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF2_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF2_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF3_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF3_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF3_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF3_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF4_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF4_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF4_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF4_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF4_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF4_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF4_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF4_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF5_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF5_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF5_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF5_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF5_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF5_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF5_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF5_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF6_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF6_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF6_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF6_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF6_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF6_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF6_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF6_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF7_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF7_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF7_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF7_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF7_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF7_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF7_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF7_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF8_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF8_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF8_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF8_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF8_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF8_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF8_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF8_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF9_DNSITP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF9_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF9_DNSITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF9_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF9_DNSITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF9_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF9_DNSITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF9_DNSITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_MCFP1ITP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF_MCFP1ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_MCFP1ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF_MCFP1ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_MCFP1ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF_MCFP1ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_MCFP1ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF_MCFP1ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ITP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_CTL_ITPDNS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_CTL_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_CTL_ITPDNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_CTL_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_CTL_ITPDNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_CTL_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_CTL_ITPDNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_CTL_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_ITPDNS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF0_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_ITPDNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF0_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_ITPDNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF0_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_ITPDNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF0_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_ITPDNS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF1_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_ITPDNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF1_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_ITPDNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF1_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_ITPDNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF1_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_ITPDNS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF2_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_ITPDNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF2_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_ITPDNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF2_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_ITPDNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF2_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_ITPDNS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF3_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_ITPDNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF3_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_ITPDNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF3_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_ITPDNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF3_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF4_ITPDNS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF4_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF4_ITPDNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF4_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF4_ITPDNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF4_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF4_ITPDNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF4_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_ITPMCSC_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF_ITPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_ITPMCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF_ITPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_ITPMCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF_ITPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_ITPMCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF_ITPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ITPDNS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ITPDNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ITPDNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_ITPDNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_ITPDNS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ITP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_LME_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_LME_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_LME_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_LME_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_LME_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_LME_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LME_QCH_ENABLE, 0, 1, QCH_CON_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LME_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LME_QCH_C2_ENABLE, 0, 1, QCH_CON_LME_QCH_C2),
|
|
SFR_ACCESS(QCH_CON_LME_QCH_C2_CLOCK_REQ, 1, 1, QCH_CON_LME_QCH_C2),
|
|
SFR_ACCESS(QCH_CON_LME_QCH_C2_EXPIRE_VAL, 16, 10, QCH_CON_LME_QCH_C2),
|
|
SFR_ACCESS(QCH_CON_LME_QCH_C2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LME_QCH_C2),
|
|
SFR_ACCESS(QCH_CON_LME_CMU_LME_QCH_ENABLE, 0, 1, QCH_CON_LME_CMU_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LME_CMU_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_LME_CMU_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LME_CMU_LME_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LME_CMU_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LME_CMU_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LME_CMU_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_LME_QCH_ENABLE, 0, 1, QCH_CON_PPMU_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_LME_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_LME_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D_LME_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_LME_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_LME_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_LME_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D_LME_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_LME_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_LME_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_LME_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D_LME_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_LME_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_LME_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_LME_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D_LME_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_LME_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_LME_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSREG_LME_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_LME_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_LME_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_LME_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_ASTC_QCH_ENABLE, 0, 1, QCH_CON_ASTC_QCH),
|
|
SFR_ACCESS(QCH_CON_ASTC_QCH_CLOCK_REQ, 1, 1, QCH_CON_ASTC_QCH),
|
|
SFR_ACCESS(QCH_CON_ASTC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ASTC_QCH),
|
|
SFR_ACCESS(QCH_CON_ASTC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASTC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_M2M_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_JPEG0_QCH_ENABLE, 0, 1, QCH_CON_JPEG0_QCH),
|
|
SFR_ACCESS(QCH_CON_JPEG0_QCH_CLOCK_REQ, 1, 1, QCH_CON_JPEG0_QCH),
|
|
SFR_ACCESS(QCH_CON_JPEG0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_JPEG0_QCH),
|
|
SFR_ACCESS(QCH_CON_JPEG0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_JPEG0_QCH),
|
|
SFR_ACCESS(QCH_CON_JPEG1_QCH_ENABLE, 0, 1, QCH_CON_JPEG1_QCH),
|
|
SFR_ACCESS(QCH_CON_JPEG1_QCH_CLOCK_REQ, 1, 1, QCH_CON_JPEG1_QCH),
|
|
SFR_ACCESS(QCH_CON_JPEG1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_JPEG1_QCH),
|
|
SFR_ACCESS(QCH_CON_JPEG1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_JPEG1_QCH),
|
|
SFR_ACCESS(QCH_CON_JSQZ_QCH_ENABLE, 0, 1, QCH_CON_JSQZ_QCH),
|
|
SFR_ACCESS(QCH_CON_JSQZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_JSQZ_QCH),
|
|
SFR_ACCESS(QCH_CON_JSQZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_JSQZ_QCH),
|
|
SFR_ACCESS(QCH_CON_JSQZ_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_JSQZ_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_M2M_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_M2M_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_M2M_QCH_ENABLE, 0, 1, QCH_CON_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_M2M_QCH_VOTF_ENABLE, 0, 1, QCH_CON_M2M_QCH_VOTF),
|
|
SFR_ACCESS(QCH_CON_M2M_QCH_VOTF_CLOCK_REQ, 1, 1, QCH_CON_M2M_QCH_VOTF),
|
|
SFR_ACCESS(QCH_CON_M2M_QCH_VOTF_EXPIRE_VAL, 16, 10, QCH_CON_M2M_QCH_VOTF),
|
|
SFR_ACCESS(QCH_CON_M2M_QCH_VOTF_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_M2M_QCH_VOTF),
|
|
SFR_ACCESS(QCH_CON_M2M_CMU_M2M_QCH_ENABLE, 0, 1, QCH_CON_M2M_CMU_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_M2M_CMU_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_M2M_CMU_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_M2M_CMU_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_M2M_CMU_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_M2M_CMU_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_M2M_CMU_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D_M2M_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ASTC_QCH_ENABLE, 0, 1, QCH_CON_QE_ASTC_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ASTC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_ASTC_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ASTC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_ASTC_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_ASTC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_ASTC_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_JPEG0_QCH_ENABLE, 0, 1, QCH_CON_QE_JPEG0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_JPEG0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_JPEG0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_JPEG0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_JPEG0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_JPEG0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_JPEG0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_JPEG1_QCH_ENABLE, 0, 1, QCH_CON_QE_JPEG1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_JPEG1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_JPEG1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_JPEG1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_JPEG1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_JPEG1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_JPEG1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_JSQZ_QCH_ENABLE, 0, 1, QCH_CON_QE_JSQZ_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_JSQZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_JSQZ_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_JSQZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_JSQZ_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_JSQZ_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_JSQZ_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_M2M_QCH_ENABLE, 0, 1, QCH_CON_QE_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D_M2M_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_M2M_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D_M2M_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_M2M_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D_M2M_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_M2M_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D_M2M_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_M2M_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSREG_M2M_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_M2M_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_M2M_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_CTL_MCFP1MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_CTL_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_CTL_MCFP1MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_CTL_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_CTL_MCFP1MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_CTL_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_CTL_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_CTL_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_MCFP1MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF0_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_MCFP1MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF0_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_MCFP1MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF0_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF0_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_MCFP1MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF1_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_MCFP1MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF1_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_MCFP1MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF1_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF1_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_MCFP1MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF2_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_MCFP1MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF2_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_MCFP1MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF2_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF2_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_MCFP1MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF3_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_MCFP1MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF3_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_MCFP1MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF3_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF3_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_CTL_MCFP0MCFP1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_CTL_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_CTL_MCFP0MCFP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_CTL_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_CTL_MCFP0MCFP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_CTL_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_CTL_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_CTL_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_MCFP0MCFP1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF0_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_MCFP0MCFP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF0_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_MCFP0MCFP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF0_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF0_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_MCFP0MCFP1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF1_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_MCFP0MCFP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF1_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_MCFP0MCFP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF1_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF1_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D0_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D2_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D2_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D2_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D2_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D2_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D2_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D2_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D2_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D3_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D3_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D3_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D3_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D3_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D3_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D3_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D3_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MCFP0MCFP1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MCFP0MCFP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MCFP0MCFP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_MCFP0_CMU_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_MCFP0_CMU_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_MCFP0_CMU_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCFP0_CMU_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_MCFP0_CMU_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MCFP0_CMU_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_MCFP0_CMU_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCFP0_CMU_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D0_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D1_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D2_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D2_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D2_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D2_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D2_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D2_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D2_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D2_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D3_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D3_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D3_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D3_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D3_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D3_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D3_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D3_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D0_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_QE_D0_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D0_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D0_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D0_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D0_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D0_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D0_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D1_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_QE_D1_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D1_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D1_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D1_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D1_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D1_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D1_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D2_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_QE_D2_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D2_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D2_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D2_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D2_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D2_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D2_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D3_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_QE_D3_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D3_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D3_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D3_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D3_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D3_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D3_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCFP0_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_MCFP0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCFP0_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_MCFP0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCFP0_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_MCFP0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCFP0_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_MCFP0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCFP0_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_MCFP0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCFP0_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_MCFP0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCFP0_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_MCFP0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCFP0_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_MCFP0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCFP0_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_MCFP0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCFP0_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_MCFP0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCFP0_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_MCFP0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCFP0_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_MCFP0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCFP0_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_MCFP0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCFP0_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_MCFP0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCFP0_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_MCFP0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCFP0_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_MCFP0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_MCFP0_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_MCFP0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_MCFP0_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_MCFP0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_MCFP0_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D2_MCFP0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_MCFP0_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_MCFP0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_MCFP0_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_MCFP0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_MCFP0_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_MCFP0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_MCFP0_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D2_MCFP0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_MCFP0_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_MCFP0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_MCFP0_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D3_MCFP0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_MCFP0_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D3_MCFP0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_MCFP0_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D3_MCFP0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_MCFP0_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D3_MCFP0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_MCFP0_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D3_MCFP0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_MCFP0_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D3_MCFP0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_MCFP0_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D3_MCFP0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D3_MCFP0_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D3_MCFP0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_MCFP0_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MCFP1_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MCFP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MCFP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MCFP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_CTL_MCFP0MCFP1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_CTL_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_CTL_MCFP0MCFP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_CTL_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_CTL_MCFP0MCFP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_CTL_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_CTL_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_CTL_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_MCFP0MCFP1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF0_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_MCFP0MCFP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF0_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_MCFP0MCFP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF0_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF0_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_MCFP0MCFP1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF1_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_MCFP0MCFP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF1_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_MCFP0MCFP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF1_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF1_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_VO_TAAMCFP1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_VO_TAAMCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_VO_TAAMCFP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_VO_TAAMCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_VO_TAAMCFP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_VO_TAAMCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_VO_TAAMCFP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_VO_TAAMCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MCFP0MCFP1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MCFP0MCFP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MCFP0MCFP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MCFP0MCFP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_MCFP0MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_CTL_MCFP1MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_CTL_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_CTL_MCFP1MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_CTL_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_CTL_MCFP1MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_CTL_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_CTL_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_CTL_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_MCFP1MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF0_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_MCFP1MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF0_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_MCFP1MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF0_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF0_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_MCFP1MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF1_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_MCFP1MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF1_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_MCFP1MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF1_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF1_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_MCFP1MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF2_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_MCFP1MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF2_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_MCFP1MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF2_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF2_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_MCFP1MCFP0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF3_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_MCFP1MCFP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF3_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_MCFP1MCFP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF3_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_MCFP1MCFP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF3_MCFP1MCFP0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_MCFP1DNS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF_MCFP1DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_MCFP1DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF_MCFP1DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_MCFP1DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF_MCFP1DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_MCFP1DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF_MCFP1DNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_MCFP1ITP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF_MCFP1ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_MCFP1ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF_MCFP1ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_MCFP1ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF_MCFP1ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_MCFP1ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF_MCFP1ITP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_VO_MCFP1TAA_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_VO_MCFP1TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_VO_MCFP1TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_VO_MCFP1TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_VO_MCFP1TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_VO_MCFP1TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_VO_MCFP1TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_VO_MCFP1TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_MCFP1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_MCFP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_MCFP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_MCFP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_MCFP1_QCH_ENABLE, 0, 1, QCH_CON_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_MCFP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_MCFP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_MCFP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_MCFP1_CMU_MCFP1_QCH_ENABLE, 0, 1, QCH_CON_MCFP1_CMU_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_MCFP1_CMU_MCFP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCFP1_CMU_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_MCFP1_CMU_MCFP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MCFP1_CMU_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_MCFP1_CMU_MCFP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCFP1_CMU_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_ORBMCH0_QCH_C2_ENABLE, 0, 1, QCH_CON_ORBMCH0_QCH_C2),
|
|
SFR_ACCESS(QCH_CON_ORBMCH0_QCH_C2_CLOCK_REQ, 1, 1, QCH_CON_ORBMCH0_QCH_C2),
|
|
SFR_ACCESS(QCH_CON_ORBMCH0_QCH_C2_EXPIRE_VAL, 16, 10, QCH_CON_ORBMCH0_QCH_C2),
|
|
SFR_ACCESS(QCH_CON_ORBMCH0_QCH_C2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ORBMCH0_QCH_C2),
|
|
SFR_ACCESS(QCH_CON_ORBMCH0_QCH_ENABLE, 0, 1, QCH_CON_ORBMCH0_QCH),
|
|
SFR_ACCESS(QCH_CON_ORBMCH0_QCH_CLOCK_REQ, 1, 1, QCH_CON_ORBMCH0_QCH),
|
|
SFR_ACCESS(QCH_CON_ORBMCH0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ORBMCH0_QCH),
|
|
SFR_ACCESS(QCH_CON_ORBMCH0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ORBMCH0_QCH),
|
|
SFR_ACCESS(QCH_CON_ORBMCH1_QCH_ENABLE, 0, 1, QCH_CON_ORBMCH1_QCH),
|
|
SFR_ACCESS(QCH_CON_ORBMCH1_QCH_CLOCK_REQ, 1, 1, QCH_CON_ORBMCH1_QCH),
|
|
SFR_ACCESS(QCH_CON_ORBMCH1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ORBMCH1_QCH),
|
|
SFR_ACCESS(QCH_CON_ORBMCH1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ORBMCH1_QCH),
|
|
SFR_ACCESS(QCH_CON_ORBMCH1_QCH_C2_ENABLE, 0, 1, QCH_CON_ORBMCH1_QCH_C2),
|
|
SFR_ACCESS(QCH_CON_ORBMCH1_QCH_C2_CLOCK_REQ, 1, 1, QCH_CON_ORBMCH1_QCH_C2),
|
|
SFR_ACCESS(QCH_CON_ORBMCH1_QCH_C2_EXPIRE_VAL, 16, 10, QCH_CON_ORBMCH1_QCH_C2),
|
|
SFR_ACCESS(QCH_CON_ORBMCH1_QCH_C2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ORBMCH1_QCH_C2),
|
|
SFR_ACCESS(QCH_CON_PPMU_ORBMCH_QCH_ENABLE, 0, 1, QCH_CON_PPMU_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_ORBMCH_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_ORBMCH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_ORBMCH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D0_ORBMCH_QCH_ENABLE, 0, 1, QCH_CON_QE_D0_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D0_ORBMCH_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D0_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D0_ORBMCH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D0_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D0_ORBMCH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D0_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D1_ORBMCH_QCH_ENABLE, 0, 1, QCH_CON_QE_D1_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D1_ORBMCH_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D1_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D1_ORBMCH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D1_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D1_ORBMCH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D1_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D2_ORBMCH_QCH_ENABLE, 0, 1, QCH_CON_QE_D2_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D2_ORBMCH_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D2_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D2_ORBMCH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D2_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D2_ORBMCH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D2_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D3_ORBMCH_QCH_ENABLE, 0, 1, QCH_CON_QE_D3_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D3_ORBMCH_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D3_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D3_ORBMCH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D3_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D3_ORBMCH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D3_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D4_ORBMCH_QCH_ENABLE, 0, 1, QCH_CON_QE_D4_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D4_ORBMCH_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D4_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D4_ORBMCH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D4_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D4_ORBMCH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D4_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D5_ORBMCH_QCH_ENABLE, 0, 1, QCH_CON_QE_D5_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D5_ORBMCH_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D5_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D5_ORBMCH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D5_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D5_ORBMCH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D5_ORBMCH_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_MCFP1_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D_MCFP1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_MCFP1_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_MCFP1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_MCFP1_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D_MCFP1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_MCFP1_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_MCFP1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_MCFP1_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D_MCFP1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_MCFP1_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_MCFP1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_MCFP1_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D_MCFP1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_MCFP1_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_MCFP1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MCFP1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MCFP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MCFP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MCFP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_MCFP1_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D0_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_MCFP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D0_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_MCFP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_D0_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_MCFP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D0_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_MCFP1_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D1_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_MCFP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D1_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_MCFP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_D1_MCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_MCFP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D1_MCFP1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_MCSC_QCH_ENABLE, 0, 1, DMYQCH_CON_ADD_MCSC_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_MCSC_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADD_MCSC_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADD_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_MCSC_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_ADD_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_ADD_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_ADD_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_ADD_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_MCSC_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPM_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPM_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPM_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPM_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MCSC_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_ENABLE, 0, 1, QCH_CON_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_C2_M_ENABLE, 0, 1, QCH_CON_GDC_QCH_C2_M),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_C2_M_CLOCK_REQ, 1, 1, QCH_CON_GDC_QCH_C2_M),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_C2_M_EXPIRE_VAL, 16, 10, QCH_CON_GDC_QCH_C2_M),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_C2_M_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GDC_QCH_C2_M),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_C2_S_ENABLE, 0, 1, QCH_CON_GDC_QCH_C2_S),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_C2_S_CLOCK_REQ, 1, 1, QCH_CON_GDC_QCH_C2_S),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_C2_S_EXPIRE_VAL, 16, 10, QCH_CON_GDC_QCH_C2_S),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_C2_S_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GDC_QCH_C2_S),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_ITPMCSC_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF_ITPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_ITPMCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF_ITPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_ITPMCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF_ITPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_ITPMCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF_ITPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_YUVPPMCSC_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF_YUVPPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_YUVPPMCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF_YUVPPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_YUVPPMCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF_YUVPPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF_YUVPPMCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF_YUVPPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_YUVPPMCSC_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_YUVPPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_YUVPPMCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_YUVPPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_YUVPPMCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_YUVPPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_YUVPPMCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_YUVPPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D0_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D0_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D0_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D0_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D0_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D0_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D0_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D0_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D2_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D2_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D2_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D2_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D2_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D2_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D2_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D2_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_ENABLE, 0, 1, QCH_CON_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_C2_W_ENABLE, 0, 1, QCH_CON_MCSC_QCH_C2_W),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_C2_W_CLOCK_REQ, 1, 1, QCH_CON_MCSC_QCH_C2_W),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_C2_W_EXPIRE_VAL, 16, 10, QCH_CON_MCSC_QCH_C2_W),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_C2_W_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCSC_QCH_C2_W),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_C2_R_ENABLE, 0, 1, QCH_CON_MCSC_QCH_C2_R),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_C2_R_CLOCK_REQ, 1, 1, QCH_CON_MCSC_QCH_C2_R),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_C2_R_EXPIRE_VAL, 16, 10, QCH_CON_MCSC_QCH_C2_R),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_C2_R_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCSC_QCH_C2_R),
|
|
SFR_ACCESS(QCH_CON_MCSC_CMU_MCSC_QCH_ENABLE, 0, 1, QCH_CON_MCSC_CMU_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_CMU_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCSC_CMU_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_CMU_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MCSC_CMU_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_CMU_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCSC_CMU_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_MCSC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D0_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_MCSC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D2_MCSC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D2_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D2_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D2_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D2_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D2_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D2_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D2_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D2_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_MCSC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D2_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_MCSC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MCSC_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_MCSC_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D0_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D0_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_D0_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D0_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_MCSC_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MFC0_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MFC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_MFC1MFC0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF0_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_MFC1MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF0_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_MFC1MFC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF0_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF0_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_MFC1MFC0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF1_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_MFC1MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF1_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_MFC1MFC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF1_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF1_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_MFC1MFC0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF2_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_MFC1MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF2_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_MFC1MFC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF2_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF2_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_MFC1MFC0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF3_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_MFC1MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF3_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_MFC1MFC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF3_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF3_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MFC0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MFC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_MFC0MFC1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF0_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_MFC0MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF0_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_MFC0MFC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF0_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF0_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_MFC0MFC1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF1_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_MFC0MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF1_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_MFC0MFC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF1_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF1_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_MFC0MFC1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF2_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_MFC0MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF2_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_MFC0MFC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF2_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF2_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_MFC0MFC1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF3_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_MFC0MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF3_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_MFC0MFC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF3_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF3_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MFC0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MFC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D0_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MFC0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MFC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MFC0_QCH_MI_ENABLE, 0, 1, QCH_CON_LH_ATB_MFC0_QCH_MI),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MFC0_QCH_MI_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MFC0_QCH_MI),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MFC0_QCH_MI_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MFC0_QCH_MI),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MFC0_QCH_MI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MFC0_QCH_MI),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MFC0_QCH_SI_ENABLE, 0, 1, QCH_CON_LH_ATB_MFC0_QCH_SI),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MFC0_QCH_SI_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MFC0_QCH_SI),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MFC0_QCH_SI_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MFC0_QCH_SI),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MFC0_QCH_SI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MFC0_QCH_SI),
|
|
SFR_ACCESS(QCH_CON_MFC0_QCH_ENABLE, 0, 1, QCH_CON_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC0_QCH_VOTF_ENABLE, 0, 1, QCH_CON_MFC0_QCH_VOTF),
|
|
SFR_ACCESS(QCH_CON_MFC0_QCH_VOTF_CLOCK_REQ, 1, 1, QCH_CON_MFC0_QCH_VOTF),
|
|
SFR_ACCESS(QCH_CON_MFC0_QCH_VOTF_EXPIRE_VAL, 16, 10, QCH_CON_MFC0_QCH_VOTF),
|
|
SFR_ACCESS(QCH_CON_MFC0_QCH_VOTF_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MFC0_QCH_VOTF),
|
|
SFR_ACCESS(QCH_CON_MFC0_CMU_MFC0_QCH_ENABLE, 0, 1, QCH_CON_MFC0_CMU_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC0_CMU_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFC0_CMU_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC0_CMU_MFC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MFC0_CMU_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC0_CMU_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MFC0_CMU_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC0D0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_MFC0D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC0D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_MFC0D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC0D0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_MFC0D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC0D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_MFC0D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC0D1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_MFC0D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC0D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_MFC0D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC0D1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_MFC0D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC0D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_MFC0D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_WFD_QCH_ENABLE, 0, 1, QCH_CON_PPMU_WFD_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_WFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_WFD_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_WFD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_WFD_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_WFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_WFD_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC0D0_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_MFC0D0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC0D0_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFC0D0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC0D0_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_MFC0D0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC0D0_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFC0D0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC0D0_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_MFC0D0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC0D0_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFC0D0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC0D0_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_MFC0D0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC0D0_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFC0D0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC0D1_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_MFC0D1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC0D1_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFC0D1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC0D1_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_MFC0D1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC0D1_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFC0D1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC0D1_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_MFC0D1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC0D1_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFC0D1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC0D1_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_MFC0D1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC0D1_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFC0D1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MFC0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MFC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_MFC0_QCH_ENABLE, 0, 1, QCH_CON_VGEN_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_MFC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_WFD_QCH_ENABLE, 0, 1, QCH_CON_WFD_QCH),
|
|
SFR_ACCESS(QCH_CON_WFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_WFD_QCH),
|
|
SFR_ACCESS(QCH_CON_WFD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WFD_QCH),
|
|
SFR_ACCESS(QCH_CON_WFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WFD_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_APB_MFC0MFC1_QCH_ENABLE, 0, 1, DMYQCH_CON_ADM_APB_MFC0MFC1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_APB_MFC0MFC1_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADM_APB_MFC0MFC1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_APB_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADM_APB_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MFC1_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MFC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_MFC0MFC1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF0_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_MFC0MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF0_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_MFC0MFC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF0_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF0_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_MFC0MFC1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF1_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_MFC0MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF1_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_MFC0MFC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF1_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF1_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_MFC0MFC1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF2_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_MFC0MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF2_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_MFC0MFC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF2_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF2_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_MFC0MFC1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF3_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_MFC0MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF3_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_MFC0MFC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF3_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF3_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MFC1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MFC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_MFC1MFC0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF0_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_MFC1MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF0_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_MFC1MFC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF0_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF0_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF0_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_MFC1MFC0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF1_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_MFC1MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF1_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_MFC1MFC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF1_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF1_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF1_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_MFC1MFC0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF2_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_MFC1MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF2_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_MFC1MFC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF2_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF2_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF2_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_MFC1MFC0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF3_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_MFC1MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF3_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_MFC1MFC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF3_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF3_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF3_MFC1MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MFC1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MFC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D0_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MFC1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MFC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC1_QCH_ENABLE, 0, 1, QCH_CON_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC1_CMU_MFC1_QCH_ENABLE, 0, 1, QCH_CON_MFC1_CMU_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC1_CMU_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFC1_CMU_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC1_CMU_MFC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MFC1_CMU_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC1_CMU_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MFC1_CMU_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC1D0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_MFC1D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC1D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_MFC1D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC1D0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_MFC1D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC1D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_MFC1D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC1D1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_MFC1D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC1D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_MFC1D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC1D1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_MFC1D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_MFC1D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_MFC1D1_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC1D0_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_MFC1D0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC1D0_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFC1D0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC1D0_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_MFC1D0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC1D0_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFC1D0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC1D0_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_MFC1D0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC1D0_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFC1D0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC1D0_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_MFC1D0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC1D0_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFC1D0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC1D1_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_MFC1D1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC1D1_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFC1D1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC1D1_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_MFC1D1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC1D1_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFC1D1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC1D1_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_MFC1D1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC1D1_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFC1D1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC1D1_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_MFC1D1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MFC1D1_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFC1D1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MFC1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MFC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_MFC1_QCH_ENABLE, 0, 1, QCH_CON_VGEN_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_MFC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_APBBR_DDRPHY_QCH_ENABLE, 0, 1, QCH_CON_APBBR_DDRPHY_QCH),
|
|
SFR_ACCESS(QCH_CON_APBBR_DDRPHY_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_DDRPHY_QCH),
|
|
SFR_ACCESS(QCH_CON_APBBR_DDRPHY_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_DDRPHY_QCH),
|
|
SFR_ACCESS(QCH_CON_APBBR_DDRPHY_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBBR_DDRPHY_QCH),
|
|
SFR_ACCESS(QCH_CON_APBBR_DMC_QCH_ENABLE, 0, 1, QCH_CON_APBBR_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBBR_DMC_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBBR_DMC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBBR_DMC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBBR_DMC_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_DMC_QCH_ENABLE, 0, 1, QCH_CON_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_DMC_QCH_CLOCK_REQ, 1, 1, QCH_CON_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_DMC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_DMC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MIF_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_ENABLE, 0, 1, QCH_CON_MIF_CMU_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_MIF_CMU_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MIF_CMU_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIF_CMU_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_ENABLE, 0, 1, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH),
|
|
SFR_ACCESS(QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_CLOCK_REQ, 1, 1, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH),
|
|
SFR_ACCESS(QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH),
|
|
SFR_ACCESS(QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPU_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_PCLK_ENABLE, 0, 1, QCH_CON_IP_NPUCORE_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_IP_NPUCORE_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_IP_NPUCORE_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPUCORE_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_ACLK_ENABLE, 0, 1, QCH_CON_IP_NPUCORE_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_ACLK_CLOCK_REQ, 1, 1, QCH_CON_IP_NPUCORE_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_ACLK_EXPIRE_VAL, 16, 10, QCH_CON_IP_NPUCORE_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_ACLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPUCORE_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_NPU_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_NPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_NPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_NPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D0_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_NPU_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_NPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_NPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_NPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D1_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CTRL_NPU_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_CTRL_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CTRL_NPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_CTRL_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CTRL_NPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_CTRL_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CTRL_NPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_CTRL_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_NPU_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_NPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_NPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_NPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CMDQ_NPU_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_CMDQ_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CMDQ_NPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_CMDQ_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CMDQ_NPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_CMDQ_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CMDQ_NPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_CMDQ_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_RQ_NPU_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_RQ_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_RQ_NPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_RQ_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_RQ_NPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_RQ_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_RQ_NPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_RQ_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_NPU_CMU_NPU_QCH_ENABLE, 0, 1, QCH_CON_NPU_CMU_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_NPU_CMU_NPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_NPU_CMU_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_NPU_CMU_NPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_NPU_CMU_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_NPU_CMU_NPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_NPU_CMU_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPU_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPU01_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPU01_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPU01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPU01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_NPU01CORE_QCH_PCLK_ENABLE, 0, 1, QCH_CON_IP_NPU01CORE_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPU01CORE_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_IP_NPU01CORE_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPU01CORE_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_IP_NPU01CORE_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPU01CORE_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPU01CORE_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPU01CORE_QCH_ACLK_ENABLE, 0, 1, QCH_CON_IP_NPU01CORE_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPU01CORE_QCH_ACLK_CLOCK_REQ, 1, 1, QCH_CON_IP_NPU01CORE_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPU01CORE_QCH_ACLK_EXPIRE_VAL, 16, 10, QCH_CON_IP_NPU01CORE_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPU01CORE_QCH_ACLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPU01CORE_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_NPU01_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_NPU01_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_NPU01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_NPU01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D0_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_NPU01_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_NPU01_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_NPU01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_NPU01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D1_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CTRL_NPU01_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_CTRL_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CTRL_NPU01_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_CTRL_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CTRL_NPU01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_CTRL_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CTRL_NPU01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_CTRL_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_NPU01_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_NPU01_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_NPU01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_NPU01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CMDQ_NPU01_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_CMDQ_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CMDQ_NPU01_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_CMDQ_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CMDQ_NPU01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_CMDQ_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CMDQ_NPU01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_CMDQ_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_RQ_NPU01_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_RQ_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_RQ_NPU01_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_RQ_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_RQ_NPU01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_RQ_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_RQ_NPU01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_RQ_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_NPU01_CMU_NPU_QCH_ENABLE, 0, 1, QCH_CON_NPU01_CMU_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_NPU01_CMU_NPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_NPU01_CMU_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_NPU01_CMU_NPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_NPU01_CMU_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_NPU01_CMU_NPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_NPU01_CMU_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPU01_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPU01_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPU01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPU01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPU10_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPU10_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPU10_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPU10_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_NPU10CORE_QCH_PCLK_ENABLE, 0, 1, QCH_CON_IP_NPU10CORE_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPU10CORE_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_IP_NPU10CORE_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPU10CORE_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_IP_NPU10CORE_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPU10CORE_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPU10CORE_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPU10CORE_QCH_ACLK_ENABLE, 0, 1, QCH_CON_IP_NPU10CORE_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPU10CORE_QCH_ACLK_CLOCK_REQ, 1, 1, QCH_CON_IP_NPU10CORE_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPU10CORE_QCH_ACLK_EXPIRE_VAL, 16, 10, QCH_CON_IP_NPU10CORE_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPU10CORE_QCH_ACLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPU10CORE_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_NPU10_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_NPU10_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_NPU10_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D0_NPU10_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D0_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_NPU10_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_NPU10_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_NPU10_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D1_NPU10_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D1_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CTRL_NPU10_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_CTRL_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CTRL_NPU10_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_CTRL_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CTRL_NPU10_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_CTRL_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CTRL_NPU10_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_CTRL_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_NPU10_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_NPU10_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_NPU10_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_NPU10_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CMDQ_NPU10_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_CMDQ_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CMDQ_NPU10_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_CMDQ_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CMDQ_NPU10_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_CMDQ_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CMDQ_NPU10_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_CMDQ_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_RQ_NPU10_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_RQ_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_RQ_NPU10_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_RQ_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_RQ_NPU10_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_RQ_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_RQ_NPU10_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_RQ_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_NPU10_CMU_NPU_QCH_ENABLE, 0, 1, QCH_CON_NPU10_CMU_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_NPU10_CMU_NPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_NPU10_CMU_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_NPU10_CMU_NPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_NPU10_CMU_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_NPU10_CMU_NPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_NPU10_CMU_NPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPU10_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPU10_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPU10_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPU10_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_NPU10_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_NPUS_QCH_ENABLE, 0, 1, DMYQCH_CON_ADD_NPUS_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_NPUS_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADD_NPUS_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADD_NPUS_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_DAP_NPUS_QCH_ENABLE, 0, 1, DMYQCH_CON_ADM_DAP_NPUS_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_DAP_NPUS_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADM_DAP_NPUS_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_DAP_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADM_DAP_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_NPUS_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_ADD_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_ADD_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_ADD_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_ADD_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_NPUS_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPM_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPM_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPM_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPM_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPUS_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_NPUS_QCH_PCLK_ENABLE, 0, 1, QCH_CON_HTU_NPUS_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_NPUS_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_NPUS_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_NPUS_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_NPUS_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_NPUS_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_NPUS_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_NPUS_QCH_CLK_ENABLE, 0, 1, QCH_CON_HTU_NPUS_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_NPUS_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_NPUS_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_NPUS_QCH_CLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_NPUS_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_NPUS_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_NPUS_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_ENABLE, 0, 1, QCH_CON_IP_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_IP_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_IP_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_C2A0_ENABLE, 0, 1, QCH_CON_IP_NPUS_QCH_C2A0),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_C2A0_CLOCK_REQ, 1, 1, QCH_CON_IP_NPUS_QCH_C2A0),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_C2A0_EXPIRE_VAL, 16, 10, QCH_CON_IP_NPUS_QCH_C2A0),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_C2A0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPUS_QCH_C2A0),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_C2A1_ENABLE, 0, 1, QCH_CON_IP_NPUS_QCH_C2A1),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_C2A1_CLOCK_REQ, 1, 1, QCH_CON_IP_NPUS_QCH_C2A1),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_C2A1_EXPIRE_VAL, 16, 10, QCH_CON_IP_NPUS_QCH_C2A1),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_C2A1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPUS_QCH_C2A1),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_CPU_ENABLE, 0, 1, QCH_CON_IP_NPUS_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_CPU_CLOCK_REQ, 1, 1, QCH_CON_IP_NPUS_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_CPU_EXPIRE_VAL, 16, 10, QCH_CON_IP_NPUS_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_CPU_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPUS_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_NEON_ENABLE, 0, 1, QCH_CON_IP_NPUS_QCH_NEON),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_NEON_CLOCK_REQ, 1, 1, QCH_CON_IP_NPUS_QCH_NEON),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_NEON_EXPIRE_VAL, 16, 10, QCH_CON_IP_NPUS_QCH_NEON),
|
|
SFR_ACCESS(QCH_CON_IP_NPUS_QCH_NEON_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPUS_QCH_NEON),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CMDQ_NPU00_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_CMDQ_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CMDQ_NPU00_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_CMDQ_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CMDQ_NPU00_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_CMDQ_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CMDQ_NPU00_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_CMDQ_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CMDQ_NPU01_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_CMDQ_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CMDQ_NPU01_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_CMDQ_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CMDQ_NPU01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_CMDQ_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CMDQ_NPU01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_CMDQ_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CMDQ_NPU10_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_CMDQ_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CMDQ_NPU10_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_CMDQ_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CMDQ_NPU10_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_CMDQ_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_CMDQ_NPU10_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_CMDQ_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_RQ_NPU00_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_RQ_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_RQ_NPU00_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_RQ_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_RQ_NPU00_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_RQ_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_RQ_NPU00_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_RQ_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_RQ_NPU01_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_RQ_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_RQ_NPU01_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_RQ_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_RQ_NPU01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_RQ_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_RQ_NPU01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_RQ_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_RQ_NPU10_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_RQ_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_RQ_NPU10_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_RQ_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_RQ_NPU10_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_RQ_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_RQ_NPU10_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_RQ_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_INT_NPUS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_INT_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_INT_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_INT_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_INT_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_INT_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_INT_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_INT_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_NPUS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_NPU00_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_NPU00_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_NPU00_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_NPU00_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D0_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_NPU01_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_NPU01_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_NPU01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_NPU01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D0_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_NPU10_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_NPU10_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_NPU10_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_NPU10_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D0_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_NPUS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D0_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D0_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_NPU00_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_NPU00_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_NPU00_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_NPU00_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_NPU01_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_NPU01_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_NPU01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_NPU01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_NPU10_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_NPU10_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_NPU10_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_NPU10_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_NPUS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D1_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D1_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D2_NPUS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D2_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D2_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D2_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D2_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D2_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D2_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D2_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CTRL_NPU00_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_CTRL_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CTRL_NPU00_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_CTRL_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CTRL_NPU00_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_CTRL_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CTRL_NPU00_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_CTRL_NPU00_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CTRL_NPU01_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_CTRL_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CTRL_NPU01_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_CTRL_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CTRL_NPU01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_CTRL_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CTRL_NPU01_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_CTRL_NPU01_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CTRL_NPU10_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_CTRL_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CTRL_NPU10_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_CTRL_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CTRL_NPU10_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_CTRL_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_CTRL_NPU10_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_CTRL_NPU10_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_INT_NPUS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_INT_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_INT_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_INT_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_INT_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_INT_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_INT_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_INT_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_NPUS_CMU_NPUS_QCH_ENABLE, 0, 1, QCH_CON_NPUS_CMU_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_NPUS_CMU_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_NPUS_CMU_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_NPUS_CMU_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_NPUS_CMU_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_NPUS_CMU_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_NPUS_CMU_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_NPUS_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_NPUS_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_NPUS_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_NPUS_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_NPUS_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_NPUS_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_NPUS_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_NPUS_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_2_QCH_ENABLE, 0, 1, QCH_CON_PPMU_NPUS_2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_NPUS_2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_NPUS_2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_NPUS_2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_NPUS_2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_NPUS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_NPUS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_NPUS_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_NPUS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_NPUS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_NPUS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_NPUS_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_NPUS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_NPUS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_NPUS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_NPUS_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_NPUS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_NPUS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_NPUS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_NPUS_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_NPUS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_NPUS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_NPUS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_NPUS_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D2_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_NPUS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_NPUS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_NPUS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_NPUS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_NPUS_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D2_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_NPUS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_NPUS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPUS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_NPUS_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_NPUS_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_NPUS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_NPUS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_NPUS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_GPIO_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC0_CMU_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_PERIC0_CMU_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC0_CMU_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_CMU_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC0_CMU_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_CMU_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC0_CMU_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_CMU_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_UART_DBG_ENABLE, 0, 1, QCH_CON_PERIC0_TOP0_QCH_UART_DBG),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_UART_DBG_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP0_QCH_UART_DBG),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_UART_DBG_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP0_QCH_UART_DBG),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_UART_DBG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP0_QCH_UART_DBG),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI00_USI_ENABLE, 0, 1, QCH_CON_PERIC0_TOP0_QCH_USI00_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI00_USI_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP0_QCH_USI00_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI00_USI_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP0_QCH_USI00_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI00_USI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP0_QCH_USI00_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI00_I2C_ENABLE, 0, 1, QCH_CON_PERIC0_TOP0_QCH_USI00_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI00_I2C_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP0_QCH_USI00_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI00_I2C_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP0_QCH_USI00_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI00_I2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP0_QCH_USI00_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI01_USI_ENABLE, 0, 1, QCH_CON_PERIC0_TOP0_QCH_USI01_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI01_USI_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP0_QCH_USI01_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI01_USI_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP0_QCH_USI01_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI01_USI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP0_QCH_USI01_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI01_I2C_ENABLE, 0, 1, QCH_CON_PERIC0_TOP0_QCH_USI01_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI01_I2C_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP0_QCH_USI01_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI01_I2C_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP0_QCH_USI01_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI01_I2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP0_QCH_USI01_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI02_USI_ENABLE, 0, 1, QCH_CON_PERIC0_TOP0_QCH_USI02_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI02_USI_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP0_QCH_USI02_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI02_USI_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP0_QCH_USI02_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI02_USI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP0_QCH_USI02_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI02_I2C_ENABLE, 0, 1, QCH_CON_PERIC0_TOP0_QCH_USI02_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI02_I2C_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP0_QCH_USI02_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI02_I2C_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP0_QCH_USI02_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI02_I2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP0_QCH_USI02_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI03_USI_ENABLE, 0, 1, QCH_CON_PERIC0_TOP0_QCH_USI03_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI03_USI_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP0_QCH_USI03_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI03_USI_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP0_QCH_USI03_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI03_USI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP0_QCH_USI03_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI03_I2C_ENABLE, 0, 1, QCH_CON_PERIC0_TOP0_QCH_USI03_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI03_I2C_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP0_QCH_USI03_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI03_I2C_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP0_QCH_USI03_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI03_I2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP0_QCH_USI03_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI04_USI_ENABLE, 0, 1, QCH_CON_PERIC0_TOP0_QCH_USI04_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI04_USI_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP0_QCH_USI04_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI04_USI_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP0_QCH_USI04_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI04_USI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP0_QCH_USI04_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI04_I2C_ENABLE, 0, 1, QCH_CON_PERIC0_TOP0_QCH_USI04_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI04_I2C_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP0_QCH_USI04_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI04_I2C_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP0_QCH_USI04_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI04_I2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP0_QCH_USI04_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI05_USI_ENABLE, 0, 1, QCH_CON_PERIC0_TOP0_QCH_USI05_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI05_USI_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP0_QCH_USI05_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI05_USI_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP0_QCH_USI05_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP0_QCH_USI05_USI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP0_QCH_USI05_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI05_I2C_ENABLE, 0, 1, QCH_CON_PERIC0_TOP1_QCH_USI05_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI05_I2C_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP1_QCH_USI05_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI05_I2C_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP1_QCH_USI05_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI05_I2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP1_QCH_USI05_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI13_USI_ENABLE, 0, 1, QCH_CON_PERIC0_TOP1_QCH_USI13_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI13_USI_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP1_QCH_USI13_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI13_USI_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP1_QCH_USI13_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI13_USI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP1_QCH_USI13_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI13_I2C_ENABLE, 0, 1, QCH_CON_PERIC0_TOP1_QCH_USI13_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI13_I2C_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP1_QCH_USI13_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI13_I2C_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP1_QCH_USI13_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI13_I2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP1_QCH_USI13_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI14_USI_ENABLE, 0, 1, QCH_CON_PERIC0_TOP1_QCH_USI14_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI14_USI_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP1_QCH_USI14_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI14_USI_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP1_QCH_USI14_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI14_USI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP1_QCH_USI14_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI14_I2C_ENABLE, 0, 1, QCH_CON_PERIC0_TOP1_QCH_USI14_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI14_I2C_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP1_QCH_USI14_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI14_I2C_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP1_QCH_USI14_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI14_I2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP1_QCH_USI14_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI15_USI_ENABLE, 0, 1, QCH_CON_PERIC0_TOP1_QCH_USI15_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI15_USI_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP1_QCH_USI15_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI15_USI_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP1_QCH_USI15_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI15_USI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP1_QCH_USI15_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI15_I2C_ENABLE, 0, 1, QCH_CON_PERIC0_TOP1_QCH_USI15_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI15_I2C_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP1_QCH_USI15_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI15_I2C_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP1_QCH_USI15_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_USI15_I2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP1_QCH_USI15_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_PWM_ENABLE, 0, 1, QCH_CON_PERIC0_TOP1_QCH_PWM),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_PWM_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_TOP1_QCH_PWM),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_PWM_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_TOP1_QCH_PWM),
|
|
SFR_ACCESS(QCH_CON_PERIC0_TOP1_QCH_PWM_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_TOP1_QCH_PWM),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_GPIO_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CSISPERIC1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_CSISPERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CSISPERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_CSISPERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CSISPERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_CSISPERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_CSISPERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_CSISPERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC1_CMU_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_PERIC1_CMU_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC1_CMU_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PERIC1_CMU_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC1_CMU_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PERIC1_CMU_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC1_CMU_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC1_CMU_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP0_QCH_UART_BT_ENABLE, 0, 1, QCH_CON_PERIC1_TOP0_QCH_UART_BT),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP0_QCH_UART_BT_CLOCK_REQ, 1, 1, QCH_CON_PERIC1_TOP0_QCH_UART_BT),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP0_QCH_UART_BT_EXPIRE_VAL, 16, 10, QCH_CON_PERIC1_TOP0_QCH_UART_BT),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP0_QCH_UART_BT_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC1_TOP0_QCH_UART_BT),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI11_USI_ENABLE, 0, 1, QCH_CON_PERIC1_TOP1_QCH_USI11_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI11_USI_CLOCK_REQ, 1, 1, QCH_CON_PERIC1_TOP1_QCH_USI11_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI11_USI_EXPIRE_VAL, 16, 10, QCH_CON_PERIC1_TOP1_QCH_USI11_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI11_USI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC1_TOP1_QCH_USI11_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI11_I2C_ENABLE, 0, 1, QCH_CON_PERIC1_TOP1_QCH_USI11_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI11_I2C_CLOCK_REQ, 1, 1, QCH_CON_PERIC1_TOP1_QCH_USI11_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI11_I2C_EXPIRE_VAL, 16, 10, QCH_CON_PERIC1_TOP1_QCH_USI11_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI11_I2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC1_TOP1_QCH_USI11_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI16_USI_ENABLE, 0, 1, QCH_CON_PERIC1_TOP1_QCH_USI16_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI16_USI_CLOCK_REQ, 1, 1, QCH_CON_PERIC1_TOP1_QCH_USI16_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI16_USI_EXPIRE_VAL, 16, 10, QCH_CON_PERIC1_TOP1_QCH_USI16_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI16_USI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC1_TOP1_QCH_USI16_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI16_I2C_ENABLE, 0, 1, QCH_CON_PERIC1_TOP1_QCH_USI16_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI16_I2C_CLOCK_REQ, 1, 1, QCH_CON_PERIC1_TOP1_QCH_USI16_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI16_I2C_EXPIRE_VAL, 16, 10, QCH_CON_PERIC1_TOP1_QCH_USI16_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI16_I2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC1_TOP1_QCH_USI16_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI17_USI_ENABLE, 0, 1, QCH_CON_PERIC1_TOP1_QCH_USI17_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI17_USI_CLOCK_REQ, 1, 1, QCH_CON_PERIC1_TOP1_QCH_USI17_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI17_USI_EXPIRE_VAL, 16, 10, QCH_CON_PERIC1_TOP1_QCH_USI17_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI17_USI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC1_TOP1_QCH_USI17_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI17_I2C_ENABLE, 0, 1, QCH_CON_PERIC1_TOP1_QCH_USI17_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI17_I2C_CLOCK_REQ, 1, 1, QCH_CON_PERIC1_TOP1_QCH_USI17_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI17_I2C_EXPIRE_VAL, 16, 10, QCH_CON_PERIC1_TOP1_QCH_USI17_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI17_I2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC1_TOP1_QCH_USI17_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI12_USI_ENABLE, 0, 1, QCH_CON_PERIC1_TOP1_QCH_USI12_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI12_USI_CLOCK_REQ, 1, 1, QCH_CON_PERIC1_TOP1_QCH_USI12_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI12_USI_EXPIRE_VAL, 16, 10, QCH_CON_PERIC1_TOP1_QCH_USI12_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI12_USI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC1_TOP1_QCH_USI12_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI12_I2C_ENABLE, 0, 1, QCH_CON_PERIC1_TOP1_QCH_USI12_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI12_I2C_CLOCK_REQ, 1, 1, QCH_CON_PERIC1_TOP1_QCH_USI12_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI12_I2C_EXPIRE_VAL, 16, 10, QCH_CON_PERIC1_TOP1_QCH_USI12_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI12_I2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC1_TOP1_QCH_USI12_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI18_USI_ENABLE, 0, 1, QCH_CON_PERIC1_TOP1_QCH_USI18_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI18_USI_CLOCK_REQ, 1, 1, QCH_CON_PERIC1_TOP1_QCH_USI18_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI18_USI_EXPIRE_VAL, 16, 10, QCH_CON_PERIC1_TOP1_QCH_USI18_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI18_USI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC1_TOP1_QCH_USI18_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI18_I2C_ENABLE, 0, 1, QCH_CON_PERIC1_TOP1_QCH_USI18_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI18_I2C_CLOCK_REQ, 1, 1, QCH_CON_PERIC1_TOP1_QCH_USI18_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI18_I2C_EXPIRE_VAL, 16, 10, QCH_CON_PERIC1_TOP1_QCH_USI18_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC1_TOP1_QCH_USI18_I2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC1_TOP1_QCH_USI18_I2C),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI16_I3C_QCH_P_ENABLE, 0, 1, QCH_CON_USI16_I3C_QCH_P),
|
|
SFR_ACCESS(QCH_CON_USI16_I3C_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_USI16_I3C_QCH_P),
|
|
SFR_ACCESS(QCH_CON_USI16_I3C_QCH_P_EXPIRE_VAL, 16, 10, QCH_CON_USI16_I3C_QCH_P),
|
|
SFR_ACCESS(QCH_CON_USI16_I3C_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI16_I3C_QCH_P),
|
|
SFR_ACCESS(DMYQCH_CON_USI16_I3C_QCH_S_ENABLE, 0, 1, DMYQCH_CON_USI16_I3C_QCH_S),
|
|
SFR_ACCESS(DMYQCH_CON_USI16_I3C_QCH_S_CLOCK_REQ, 1, 1, DMYQCH_CON_USI16_I3C_QCH_S),
|
|
SFR_ACCESS(DMYQCH_CON_USI16_I3C_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_USI16_I3C_QCH_S),
|
|
SFR_ACCESS(QCH_CON_USI17_I3C_QCH_P_ENABLE, 0, 1, QCH_CON_USI17_I3C_QCH_P),
|
|
SFR_ACCESS(QCH_CON_USI17_I3C_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_USI17_I3C_QCH_P),
|
|
SFR_ACCESS(QCH_CON_USI17_I3C_QCH_P_EXPIRE_VAL, 16, 10, QCH_CON_USI17_I3C_QCH_P),
|
|
SFR_ACCESS(QCH_CON_USI17_I3C_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI17_I3C_QCH_P),
|
|
SFR_ACCESS(DMYQCH_CON_USI17_I3C_QCH_S_ENABLE, 0, 1, DMYQCH_CON_USI17_I3C_QCH_S),
|
|
SFR_ACCESS(DMYQCH_CON_USI17_I3C_QCH_S_CLOCK_REQ, 1, 1, DMYQCH_CON_USI17_I3C_QCH_S),
|
|
SFR_ACCESS(DMYQCH_CON_USI17_I3C_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_USI17_I3C_QCH_S),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC2_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC2_QCH_ENABLE, 0, 1, QCH_CON_GPIO_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC2_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC2_CMU_PERIC2_QCH_ENABLE, 0, 1, QCH_CON_PERIC2_CMU_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC2_CMU_PERIC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PERIC2_CMU_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC2_CMU_PERIC2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PERIC2_CMU_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC2_CMU_PERIC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC2_CMU_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI06_USI_ENABLE, 0, 1, QCH_CON_PERIC2_TOP0_QCH_USI06_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI06_USI_CLOCK_REQ, 1, 1, QCH_CON_PERIC2_TOP0_QCH_USI06_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI06_USI_EXPIRE_VAL, 16, 10, QCH_CON_PERIC2_TOP0_QCH_USI06_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI06_USI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC2_TOP0_QCH_USI06_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI07_USI_ENABLE, 0, 1, QCH_CON_PERIC2_TOP0_QCH_USI07_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI07_USI_CLOCK_REQ, 1, 1, QCH_CON_PERIC2_TOP0_QCH_USI07_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI07_USI_EXPIRE_VAL, 16, 10, QCH_CON_PERIC2_TOP0_QCH_USI07_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI07_USI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC2_TOP0_QCH_USI07_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI08_USI_ENABLE, 0, 1, QCH_CON_PERIC2_TOP0_QCH_USI08_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI08_USI_CLOCK_REQ, 1, 1, QCH_CON_PERIC2_TOP0_QCH_USI08_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI08_USI_EXPIRE_VAL, 16, 10, QCH_CON_PERIC2_TOP0_QCH_USI08_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI08_USI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC2_TOP0_QCH_USI08_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI08_I2C_ENABLE, 0, 1, QCH_CON_PERIC2_TOP0_QCH_USI08_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI08_I2C_CLOCK_REQ, 1, 1, QCH_CON_PERIC2_TOP0_QCH_USI08_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI08_I2C_EXPIRE_VAL, 16, 10, QCH_CON_PERIC2_TOP0_QCH_USI08_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI08_I2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC2_TOP0_QCH_USI08_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI06_I2C_ENABLE, 0, 1, QCH_CON_PERIC2_TOP0_QCH_USI06_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI06_I2C_CLOCK_REQ, 1, 1, QCH_CON_PERIC2_TOP0_QCH_USI06_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI06_I2C_EXPIRE_VAL, 16, 10, QCH_CON_PERIC2_TOP0_QCH_USI06_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI06_I2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC2_TOP0_QCH_USI06_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI07_I2C_ENABLE, 0, 1, QCH_CON_PERIC2_TOP0_QCH_USI07_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI07_I2C_CLOCK_REQ, 1, 1, QCH_CON_PERIC2_TOP0_QCH_USI07_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI07_I2C_EXPIRE_VAL, 16, 10, QCH_CON_PERIC2_TOP0_QCH_USI07_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP0_QCH_USI07_I2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC2_TOP0_QCH_USI07_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP1_QCH_USI09_USI_ENABLE, 0, 1, QCH_CON_PERIC2_TOP1_QCH_USI09_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP1_QCH_USI09_USI_CLOCK_REQ, 1, 1, QCH_CON_PERIC2_TOP1_QCH_USI09_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP1_QCH_USI09_USI_EXPIRE_VAL, 16, 10, QCH_CON_PERIC2_TOP1_QCH_USI09_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP1_QCH_USI09_USI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC2_TOP1_QCH_USI09_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP1_QCH_USI09_I2C_ENABLE, 0, 1, QCH_CON_PERIC2_TOP1_QCH_USI09_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP1_QCH_USI09_I2C_CLOCK_REQ, 1, 1, QCH_CON_PERIC2_TOP1_QCH_USI09_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP1_QCH_USI09_I2C_EXPIRE_VAL, 16, 10, QCH_CON_PERIC2_TOP1_QCH_USI09_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP1_QCH_USI09_I2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC2_TOP1_QCH_USI09_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP1_QCH_USI10_USI_ENABLE, 0, 1, QCH_CON_PERIC2_TOP1_QCH_USI10_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP1_QCH_USI10_USI_CLOCK_REQ, 1, 1, QCH_CON_PERIC2_TOP1_QCH_USI10_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP1_QCH_USI10_USI_EXPIRE_VAL, 16, 10, QCH_CON_PERIC2_TOP1_QCH_USI10_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP1_QCH_USI10_USI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC2_TOP1_QCH_USI10_USI),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP1_QCH_USI10_I2C_ENABLE, 0, 1, QCH_CON_PERIC2_TOP1_QCH_USI10_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP1_QCH_USI10_I2C_CLOCK_REQ, 1, 1, QCH_CON_PERIC2_TOP1_QCH_USI10_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP1_QCH_USI10_I2C_EXPIRE_VAL, 16, 10, QCH_CON_PERIC2_TOP1_QCH_USI10_I2C),
|
|
SFR_ACCESS(QCH_CON_PERIC2_TOP1_QCH_USI10_I2C_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC2_TOP1_QCH_USI10_I2C),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC2_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_BC_EMUL_QCH_ENABLE, 0, 1, QCH_CON_BC_EMUL_QCH),
|
|
SFR_ACCESS(QCH_CON_BC_EMUL_QCH_CLOCK_REQ, 1, 1, QCH_CON_BC_EMUL_QCH),
|
|
SFR_ACCESS(QCH_CON_BC_EMUL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BC_EMUL_QCH),
|
|
SFR_ACCESS(QCH_CON_BC_EMUL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BC_EMUL_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIS_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_GIC_QCH_ENABLE, 0, 1, QCH_CON_GIC_QCH),
|
|
SFR_ACCESS(QCH_CON_GIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_GIC_QCH),
|
|
SFR_ACCESS(QCH_CON_GIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GIC_QCH),
|
|
SFR_ACCESS(QCH_CON_GIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GIC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ICC_CPUGIC_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_ICC_CPUGIC_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ICC_CPUGIC_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_ICC_CPUGIC_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ICC_CPUGIC_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_ICC_CPUGIC_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_ICC_CPUGIC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_ICC_CPUGIC_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERISGIC_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_PERISGIC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERISGIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_PERISGIC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERISGIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_PERISGIC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_PERISGIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_PERISGIC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_IRI_GICCPU_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_IRI_GICCPU_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_IRI_GICCPU_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_IRI_GICCPU_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_IRI_GICCPU_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_IRI_GICCPU_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_IRI_GICCPU_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_IRI_GICCPU_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_MCT_QCH_ENABLE, 0, 1, QCH_CON_MCT_QCH),
|
|
SFR_ACCESS(QCH_CON_MCT_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCT_QCH),
|
|
SFR_ACCESS(QCH_CON_MCT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MCT_QCH),
|
|
SFR_ACCESS(QCH_CON_MCT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCT_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_OTP_QCH_ENABLE, 0, 1, DMYQCH_CON_OTP_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_OTP_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_OTP_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_OTP_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_OTP_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_BIRA_QCH_ENABLE, 0, 1, QCH_CON_OTP_CON_BIRA_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_BIRA_QCH_CLOCK_REQ, 1, 1, QCH_CON_OTP_CON_BIRA_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_BIRA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_OTP_CON_BIRA_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_BIRA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_OTP_CON_BIRA_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_BISR_QCH_ENABLE, 0, 1, QCH_CON_OTP_CON_BISR_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_BISR_QCH_CLOCK_REQ, 1, 1, QCH_CON_OTP_CON_BISR_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_BISR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_OTP_CON_BISR_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_BISR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_OTP_CON_BISR_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_ENABLE, 0, 1, QCH_CON_OTP_CON_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_OTP_CON_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_OTP_CON_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_OTP_CON_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIS_CMU_PERIS_QCH_ENABLE, 0, 1, QCH_CON_PERIS_CMU_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIS_CMU_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_PERIS_CMU_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIS_CMU_PERIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PERIS_CMU_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIS_CMU_PERIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIS_CMU_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_TMU_SUB_QCH_ENABLE, 0, 1, QCH_CON_TMU_SUB_QCH),
|
|
SFR_ACCESS(QCH_CON_TMU_SUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_TMU_SUB_QCH),
|
|
SFR_ACCESS(QCH_CON_TMU_SUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TMU_SUB_QCH),
|
|
SFR_ACCESS(QCH_CON_TMU_SUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TMU_SUB_QCH),
|
|
SFR_ACCESS(QCH_CON_TMU_TOP_QCH_ENABLE, 0, 1, QCH_CON_TMU_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_TMU_TOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_TMU_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_TMU_TOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TMU_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_TMU_TOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TMU_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT0_QCH_ENABLE, 0, 1, QCH_CON_WDT0_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT0_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT0_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT0_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT0_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT1_QCH_ENABLE, 0, 1, QCH_CON_WDT1_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT1_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT1_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT1_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_BIS_S2D_QCH_ENABLE, 0, 1, DMYQCH_CON_BIS_S2D_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_BIS_S2D_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_BIS_S2D_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_BIS_S2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_BIS_S2D_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_SCAN2DRAM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_SCAN2DRAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_SCAN2DRAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_S2D_CMU_S2D_QCH_ENABLE, 0, 1, QCH_CON_S2D_CMU_S2D_QCH),
|
|
SFR_ACCESS(QCH_CON_S2D_CMU_S2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_S2D_CMU_S2D_QCH),
|
|
SFR_ACCESS(QCH_CON_S2D_CMU_S2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_S2D_CMU_S2D_QCH),
|
|
SFR_ACCESS(QCH_CON_S2D_CMU_S2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_S2D_CMU_S2D_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_DAP_SSS_QCH_ENABLE, 0, 1, DMYQCH_CON_ADM_DAP_SSS_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_DAP_SSS_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADM_DAP_SSS_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_DAP_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADM_DAP_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_SSS_QCH_ENABLE, 0, 1, QCH_CON_BAAW_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_SSP_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_SSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_SSPCORE_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_SSPCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_SSPCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_SSPCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_SSPCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_SSPCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_SSPCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_SSPCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_SSP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_SSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_SSP_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_SSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_SSP_QCH_ENABLE, 0, 1, QCH_CON_PPMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_SSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_RTIC_QCH_ENABLE, 0, 1, QCH_CON_QE_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_RTIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_RTIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_RTIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_SSPCORE_QCH_ENABLE, 0, 1, QCH_CON_QE_SSPCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_SSPCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_SSPCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_SSPCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_SSPCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_SSPCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_SSPCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_SSS_QCH_ENABLE, 0, 1, QCH_CON_QE_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_RTIC_QCH_ENABLE, 0, 1, QCH_CON_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_RTIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_RTIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_RTIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SSP_CMU_SSP_QCH_ENABLE, 0, 1, QCH_CON_SSP_CMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SSP_CMU_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSP_CMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SSP_CMU_SSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSP_CMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SSP_CMU_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSP_CMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SSS_QCH_ENABLE, 0, 1, QCH_CON_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_D_SSP_QCH_ENABLE, 0, 1, QCH_CON_SWEEPER_D_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_D_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SWEEPER_D_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_D_SSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SWEEPER_D_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_D_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SWEEPER_D_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_RTIC_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_RTIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_RTIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_RTIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_SSPCTRL_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_SSPCTRL_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_SSPCTRL_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_SSPCTRL_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_SSPCTRL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_SSPCTRL_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_SSPCTRL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_SSPCTRL_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_RTIC_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_RTIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_RTIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_RTIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_RTIC_QCH),
|
|
SFR_ACCESS(QCH_CON_USS_SSPCORE_QCH_ENABLE, 0, 1, QCH_CON_USS_SSPCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_USS_SSPCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_USS_SSPCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_USS_SSPCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USS_SSPCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_USS_SSPCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USS_SSPCORE_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_TAA_QCH_ENABLE, 0, 1, DMYQCH_CON_ADD_TAA_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_TAA_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADD_TAA_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADD_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_TAA_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_ADD_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_ADD_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_ADD_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_ADD_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_TAA_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPM_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPM_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPM_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPM_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_TAA_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_CSISTAA_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF0_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_CSISTAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF0_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_CSISTAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF0_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF0_CSISTAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF0_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_CSISTAA_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF1_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_CSISTAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF1_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_CSISTAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF1_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF1_CSISTAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF1_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_CSISTAA_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF2_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_CSISTAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF2_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_CSISTAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF2_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF2_CSISTAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF2_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_CSISTAA_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_OTF3_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_CSISTAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_OTF3_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_CSISTAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_OTF3_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_OTF3_CSISTAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_OTF3_CSISTAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_VO_MCFP1TAA_QCH_ENABLE, 0, 1, QCH_CON_LHM_AST_VO_MCFP1TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_VO_MCFP1TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AST_VO_MCFP1TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_VO_MCFP1TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AST_VO_MCFP1TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AST_VO_MCFP1TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AST_VO_MCFP1TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_TAA_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_TAADNS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF_TAADNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_TAADNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF_TAADNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_TAADNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF_TAADNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_TAADNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF_TAADNS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_SOTF0_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_SOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_SOTF0_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_SOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_SOTF0_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_SOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_SOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_SOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_SOTF1_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_SOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_SOTF1_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_SOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_SOTF1_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_SOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_SOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_SOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_SOTF2_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_SOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_SOTF2_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_SOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_SOTF2_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_SOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_SOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_SOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_SOTF3_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_SOTF3_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_SOTF3_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_SOTF3_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_SOTF3_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_SOTF3_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_SOTF3_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_SOTF3_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_VO_TAAMCFP1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_VO_TAAMCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_VO_TAAMCFP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_VO_TAAMCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_VO_TAAMCFP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_VO_TAAMCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_VO_TAAMCFP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_VO_TAAMCFP1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ZOTF0_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_ZOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ZOTF0_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_ZOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ZOTF0_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_ZOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ZOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_ZOTF0_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ZOTF1_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_ZOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ZOTF1_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_ZOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ZOTF1_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_ZOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ZOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_ZOTF1_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ZOTF2_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_ZOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ZOTF2_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_ZOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ZOTF2_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_ZOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ZOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_ZOTF2_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ZOTF3_TAACSIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_ZOTF3_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ZOTF3_TAACSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_ZOTF3_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ZOTF3_TAACSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_ZOTF3_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_ZOTF3_TAACSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_ZOTF3_TAACSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_TAA_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_TAA_QCH_ENABLE, 0, 1, QCH_CON_PPMU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_ENABLE, 0, 1, QCH_CON_SIPU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIPU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SIPU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIPU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_C2_STAT_ENABLE, 0, 1, QCH_CON_SIPU_TAA_QCH_C2_STAT),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_C2_STAT_CLOCK_REQ, 1, 1, QCH_CON_SIPU_TAA_QCH_C2_STAT),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_C2_STAT_EXPIRE_VAL, 16, 10, QCH_CON_SIPU_TAA_QCH_C2_STAT),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_C2_STAT_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIPU_TAA_QCH_C2_STAT),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_C2_YDS_ENABLE, 0, 1, QCH_CON_SIPU_TAA_QCH_C2_YDS),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_C2_YDS_CLOCK_REQ, 1, 1, QCH_CON_SIPU_TAA_QCH_C2_YDS),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_C2_YDS_EXPIRE_VAL, 16, 10, QCH_CON_SIPU_TAA_QCH_C2_YDS),
|
|
SFR_ACCESS(QCH_CON_SIPU_TAA_QCH_C2_YDS_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIPU_TAA_QCH_C2_YDS),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_TAA_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D_TAA_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_TAA_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_TAA_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_TAA_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D_TAA_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_TAA_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_TAA_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_TAA_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D_TAA_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_TAA_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_TAA_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_TAA_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D_TAA_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_TAA_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_TAA_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_TAA_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_TAA_CMU_TAA_QCH_ENABLE, 0, 1, QCH_CON_TAA_CMU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_TAA_CMU_TAA_QCH_CLOCK_REQ, 1, 1, QCH_CON_TAA_CMU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_TAA_CMU_TAA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TAA_CMU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_TAA_CMU_TAA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TAA_CMU_TAA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_TAA0_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_TAA0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_TAA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_TAA0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_TAA0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_TAA0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_TAA0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_TAA0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_TAA1_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_TAA1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_TAA1_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_TAA1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_TAA1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_TAA1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_TAA1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_TAA1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_VPC_QCH_ENABLE, 0, 1, DMYQCH_CON_ADD_VPC_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_VPC_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADD_VPC_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_VPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADD_VPC_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_DAP_VPC_QCH_ENABLE, 0, 1, DMYQCH_CON_ADM_DAP_VPC_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_DAP_VPC_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADM_DAP_VPC_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_DAP_VPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADM_DAP_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_VPC_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_ADD_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_VPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_ADD_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_VPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_ADD_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_VPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_ADD_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_VPC_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPM_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_VPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPM_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_VPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPM_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_VPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPM_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_VPC_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_VPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_VPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_VPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_VPC_QCH_PCLK_ENABLE, 0, 1, QCH_CON_HTU_VPC_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_VPC_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_VPC_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_VPC_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_VPC_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_VPC_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_VPC_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_VPC_QCH_CLK_ENABLE, 0, 1, QCH_CON_HTU_VPC_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_VPC_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_VPC_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_VPC_QCH_CLK_EXPIRE_VAL, 16, 10, QCH_CON_HTU_VPC_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_VPC_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_VPC_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_IP_VPC_QCH_ENABLE, 0, 1, QCH_CON_IP_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_VPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_IP_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_VPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_IP_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_VPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPD0VPC_CACHE_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_VPD0VPC_CACHE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPD0VPC_CACHE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_VPD0VPC_CACHE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPD0VPC_CACHE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_VPD0VPC_CACHE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPD0VPC_CACHE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_VPD0VPC_CACHE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPD0VPC_SFR_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_VPD0VPC_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPD0VPC_SFR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_VPD0VPC_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPD0VPC_SFR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_VPD0VPC_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPD0VPC_SFR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_VPD0VPC_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPD1VPC_CACHE_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_VPD1VPC_CACHE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPD1VPC_CACHE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_VPD1VPC_CACHE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPD1VPC_CACHE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_VPD1VPC_CACHE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPD1VPC_CACHE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_VPD1VPC_CACHE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPD1VPC_SFR_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_VPD1VPC_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPD1VPC_SFR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_VPD1VPC_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPD1VPC_SFR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_VPD1VPC_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPD1VPC_SFR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_VPD1VPC_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_VPC_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_VPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_VPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_VPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_VPC_800_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_VPC_800_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_VPC_800_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_VPC_800_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_VPC_800_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_VPC_800_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_VPC_800_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_VPC_800_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D0_VPC_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D0_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D0_VPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D0_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D0_VPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D0_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D0_VPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D0_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D1_VPC_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D1_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D1_VPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D1_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D1_VPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D1_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D1_VPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D1_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D2_VPC_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D2_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D2_VPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D2_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D2_VPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D2_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_ACEL_D2_VPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_ACEL_D2_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPCVPD0_DMA_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_VPCVPD0_DMA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPCVPD0_DMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_VPCVPD0_DMA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPCVPD0_DMA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_VPCVPD0_DMA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPCVPD0_DMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_VPCVPD0_DMA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPCVPD0_SFR_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_VPCVPD0_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPCVPD0_SFR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_VPCVPD0_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPCVPD0_SFR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_VPCVPD0_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPCVPD0_SFR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_VPCVPD0_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPCVPD1_DMA_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_VPCVPD1_DMA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPCVPD1_DMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_VPCVPD1_DMA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPCVPD1_DMA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_VPCVPD1_DMA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPCVPD1_DMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_VPCVPD1_DMA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPCVPD1_SFR_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_VPCVPD1_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPCVPD1_SFR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_VPCVPD1_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPCVPD1_SFR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_VPCVPD1_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPCVPD1_SFR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_VPCVPD1_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VPCVPD0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_VPCVPD0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VPCVPD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_VPCVPD0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VPCVPD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_VPCVPD0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VPCVPD0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_VPCVPD0_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VPCVPD1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_VPCVPD1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VPCVPD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_VPCVPD1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VPCVPD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_VPCVPD1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VPCVPD1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_VPCVPD1_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VPC_200_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_VPC_200_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VPC_200_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_VPC_200_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VPC_200_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_VPC_200_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_P_VPC_200_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_P_VPC_200_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_VPC0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_VPC0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_VPC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_VPC0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_VPC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_VPC0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_VPC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_VPC0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_VPC1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_VPC1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_VPC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_VPC1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_VPC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_VPC1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_VPC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_VPC1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_VPC2_QCH_ENABLE, 0, 1, QCH_CON_PPMU_VPC2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_VPC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_VPC2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_VPC2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_VPC2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_VPC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_VPC2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC0_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_VPC0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC0_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_VPC0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC0_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_VPC0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC0_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_VPC0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC0_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_VPC0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC0_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_VPC0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC0_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_VPC0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC0_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_VPC0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC1_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_VPC1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC1_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_VPC1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC1_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_VPC1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC1_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_VPC1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC1_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_VPC1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC1_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_VPC1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC1_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_VPC1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC1_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_VPC1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC2_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_VPC2_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC2_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_VPC2_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC2_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_VPC2_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC2_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_VPC2_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC2_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_VPC2_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC2_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_VPC2_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC2_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_VPC2_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_VPC2_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_VPC2_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_VPC_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_VPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_VPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_VPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_VPC_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_VPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_VPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_VPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_VPC_CMU_VPC_QCH_ENABLE, 0, 1, QCH_CON_VPC_CMU_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_VPC_CMU_VPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_VPC_CMU_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_VPC_CMU_VPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VPC_CMU_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_VPC_CMU_VPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VPC_CMU_VPC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_VPD_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_VPD_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_VPD_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_VPD_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_VPD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_VPD_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_VPD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_VPD_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_VPD_QCH_ENABLE, 0, 1, QCH_CON_IP_VPD_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_VPD_QCH_CLOCK_REQ, 1, 1, QCH_CON_IP_VPD_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_VPD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_IP_VPD_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_VPD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_VPD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPCVPD_DMA_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_VPCVPD_DMA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPCVPD_DMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_VPCVPD_DMA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPCVPD_DMA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_VPCVPD_DMA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPCVPD_DMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_VPCVPD_DMA_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPCVPD_SFR_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_VPCVPD_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPCVPD_SFR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_VPCVPD_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPCVPD_SFR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_VPCVPD_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_VPCVPD_SFR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_VPCVPD_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_VPCVPD_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_VPCVPD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_VPCVPD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_VPCVPD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_VPCVPD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_VPCVPD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_VPCVPD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_VPCVPD_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPDVPC_CACHE_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_VPDVPC_CACHE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPDVPC_CACHE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_VPDVPC_CACHE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPDVPC_CACHE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_VPDVPC_CACHE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPDVPC_CACHE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_VPDVPC_CACHE_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPDVPC_SFR_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_VPDVPC_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPDVPC_SFR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_VPDVPC_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPDVPC_SFR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_VPDVPC_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VPDVPC_SFR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_VPDVPC_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_VPD_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_VPD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_VPD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_VPD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_VPD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_VPD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_VPD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_VPD_QCH),
|
|
SFR_ACCESS(QCH_CON_VPD_CMU_VPD_QCH_ENABLE, 0, 1, QCH_CON_VPD_CMU_VPD_QCH),
|
|
SFR_ACCESS(QCH_CON_VPD_CMU_VPD_QCH_CLOCK_REQ, 1, 1, QCH_CON_VPD_CMU_VPD_QCH),
|
|
SFR_ACCESS(QCH_CON_VPD_CMU_VPD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VPD_CMU_VPD_QCH),
|
|
SFR_ACCESS(QCH_CON_VPD_CMU_VPD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VPD_CMU_VPD_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_C_VTS_QCH_ENABLE, 0, 1, QCH_CON_BAAW_C_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_C_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_C_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_C_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_C_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_C_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_C_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_VTS_QCH_ENABLE, 0, 1, QCH_CON_BAAW_D_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_D_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_D_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_D_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_VTS_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPM_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPM_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPM_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_HPM_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPM_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_ENABLE, 0, 1, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_CLOCK_REQ, 1, 1, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_EXPIRE_VAL, 16, 10, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_TEST_QCH_ACLK_ENABLE, 0, 1, QCH_CON_DMAILBOX_TEST_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_TEST_QCH_ACLK_CLOCK_REQ, 1, 1, QCH_CON_DMAILBOX_TEST_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_TEST_QCH_ACLK_EXPIRE_VAL, 16, 10, QCH_CON_DMAILBOX_TEST_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_TEST_QCH_ACLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMAILBOX_TEST_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_TEST_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMAILBOX_TEST_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_TEST_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMAILBOX_TEST_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_TEST_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMAILBOX_TEST_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_TEST_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMAILBOX_TEST_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMAILBOX_TEST_QCH_LIF_ENABLE, 0, 1, DMYQCH_CON_DMAILBOX_TEST_QCH_LIF),
|
|
SFR_ACCESS(DMYQCH_CON_DMAILBOX_TEST_QCH_LIF_CLOCK_REQ, 1, 1, DMYQCH_CON_DMAILBOX_TEST_QCH_LIF),
|
|
SFR_ACCESS(DMYQCH_CON_DMAILBOX_TEST_QCH_LIF_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DMAILBOX_TEST_QCH_LIF),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB0_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_AHB0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB0_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_AHB0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB0_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_AHB0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB0_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_AHB0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB1_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_AHB1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB1_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_AHB1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB1_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_AHB1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB1_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_AHB1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB2_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_AHB2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB2_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_AHB2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB2_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_AHB2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB2_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_AHB2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB3_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_AHB3_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB3_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_AHB3_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB3_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_AHB3_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB3_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_AHB3_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB4_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_AHB4_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB4_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_AHB4_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB4_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_AHB4_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB4_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_AHB4_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB5_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_AHB5_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB5_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_AHB5_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB5_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_AHB5_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AHB5_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_AHB5_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD0_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_AUD0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD0_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_AUD0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD0_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_AUD0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD0_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_AUD0_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD0_QCH_DMIC_ENABLE, 0, 1, DMYQCH_CON_DMIC_AUD0_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD0_QCH_DMIC_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_AUD0_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD0_QCH_DMIC_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DMIC_AUD0_QCH_DMIC),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD1_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_AUD1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD1_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_AUD1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD1_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_AUD1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD1_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_AUD1_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD1_QCH_DMIC_ENABLE, 0, 1, DMYQCH_CON_DMIC_AUD1_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD1_QCH_DMIC_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_AUD1_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD1_QCH_DMIC_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DMIC_AUD1_QCH_DMIC),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD2_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_AUD2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD2_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_AUD2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD2_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_AUD2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD2_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_AUD2_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD2_QCH_DMIC_ENABLE, 0, 1, DMYQCH_CON_DMIC_AUD2_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD2_QCH_DMIC_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_AUD2_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD2_QCH_DMIC_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DMIC_AUD2_QCH_DMIC),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF0_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_IF0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF0_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_IF0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF0_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_IF0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF0_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_IF0_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF0_QCH_DMIC_ENABLE, 0, 1, DMYQCH_CON_DMIC_IF0_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF0_QCH_DMIC_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_IF0_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF0_QCH_DMIC_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DMIC_IF0_QCH_DMIC),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF1_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_IF1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF1_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_IF1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF1_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_IF1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF1_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_IF1_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF1_QCH_DMIC_ENABLE, 0, 1, DMYQCH_CON_DMIC_IF1_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF1_QCH_DMIC_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_IF1_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF1_QCH_DMIC_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DMIC_IF1_QCH_DMIC),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF2_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_IF2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF2_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_IF2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF2_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_IF2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF2_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_IF2_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF2_QCH_DMIC_ENABLE, 0, 1, DMYQCH_CON_DMIC_IF2_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF2_QCH_DMIC_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_IF2_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF2_QCH_DMIC_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DMIC_IF2_QCH_DMIC),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_VTS_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_VTS_QCH_ENABLE, 0, 1, QCH_CON_GPIO_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC0_QCH_ENABLE, 0, 1, QCH_CON_HWACG_SYS_DMIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_HWACG_SYS_DMIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HWACG_SYS_DMIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HWACG_SYS_DMIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC1_QCH_ENABLE, 0, 1, QCH_CON_HWACG_SYS_DMIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_HWACG_SYS_DMIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HWACG_SYS_DMIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HWACG_SYS_DMIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC2_QCH_ENABLE, 0, 1, QCH_CON_HWACG_SYS_DMIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_HWACG_SYS_DMIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HWACG_SYS_DMIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HWACG_SYS_DMIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC3_QCH_ENABLE, 0, 1, QCH_CON_HWACG_SYS_DMIC3_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC3_QCH_CLOCK_REQ, 1, 1, QCH_CON_HWACG_SYS_DMIC3_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HWACG_SYS_DMIC3_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HWACG_SYS_DMIC3_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC4_QCH_ENABLE, 0, 1, QCH_CON_HWACG_SYS_DMIC4_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC4_QCH_CLOCK_REQ, 1, 1, QCH_CON_HWACG_SYS_DMIC4_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC4_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HWACG_SYS_DMIC4_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC4_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HWACG_SYS_DMIC4_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC5_QCH_ENABLE, 0, 1, QCH_CON_HWACG_SYS_DMIC5_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC5_QCH_CLOCK_REQ, 1, 1, QCH_CON_HWACG_SYS_DMIC5_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC5_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HWACG_SYS_DMIC5_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_DMIC5_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HWACG_SYS_DMIC5_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_ENABLE, 0, 1, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH),
|
|
SFR_ACCESS(QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_AUDVTS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_AUDVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_AUDVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_AUDVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_AUDVTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_AUDVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_D_AUDVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_D_AUDVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_LP_VTS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_LP_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_LP_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_LP_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_LP_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_LP_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_LP_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_LP_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_VTS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_C_VTS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_C_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_C_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_C_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_C_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_C_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_C_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_C_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VTS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_ABOX_VTS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_ABOX_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_ABOX_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_ABOX_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_ABOX_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_ABOX_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_ABOX_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_ABOX_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_VTS1_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_VTS1_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_VTS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_VTS1_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_VTS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM_VTS1_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_VTS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_VTS1_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_VTS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_VTS_QCH_ENABLE, 0, 1, QCH_CON_PDMA_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_PDMA_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PDMA_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PDMA_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_QCH_PCLK_ENABLE, 0, 1, QCH_CON_SERIAL_LIF_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_SERIAL_LIF_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_SERIAL_LIF_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SERIAL_LIF_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_SERIAL_LIF_QCH_LIF_ENABLE, 0, 1, DMYQCH_CON_SERIAL_LIF_QCH_LIF),
|
|
SFR_ACCESS(DMYQCH_CON_SERIAL_LIF_QCH_LIF_CLOCK_REQ, 1, 1, DMYQCH_CON_SERIAL_LIF_QCH_LIF),
|
|
SFR_ACCESS(DMYQCH_CON_SERIAL_LIF_QCH_LIF_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SERIAL_LIF_QCH_LIF),
|
|
SFR_ACCESS(DMYQCH_CON_SERIAL_LIF_QCH_HCLK_ENABLE, 0, 1, DMYQCH_CON_SERIAL_LIF_QCH_HCLK),
|
|
SFR_ACCESS(DMYQCH_CON_SERIAL_LIF_QCH_HCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_SERIAL_LIF_QCH_HCLK),
|
|
SFR_ACCESS(DMYQCH_CON_SERIAL_LIF_QCH_HCLK_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SERIAL_LIF_QCH_HCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_DEBUG_US_QCH_PCLK_ENABLE, 0, 1, QCH_CON_SERIAL_LIF_DEBUG_US_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_DEBUG_US_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_SERIAL_LIF_DEBUG_US_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_DEBUG_US_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_SERIAL_LIF_DEBUG_US_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_DEBUG_US_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SERIAL_LIF_DEBUG_US_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_SERIAL_LIF_DEBUG_US_QCH_LIF_ENABLE, 0, 1, DMYQCH_CON_SERIAL_LIF_DEBUG_US_QCH_LIF),
|
|
SFR_ACCESS(DMYQCH_CON_SERIAL_LIF_DEBUG_US_QCH_LIF_CLOCK_REQ, 1, 1, DMYQCH_CON_SERIAL_LIF_DEBUG_US_QCH_LIF),
|
|
SFR_ACCESS(DMYQCH_CON_SERIAL_LIF_DEBUG_US_QCH_LIF_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SERIAL_LIF_DEBUG_US_QCH_LIF),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_DEBUG_VT_QCH_PCLK_ENABLE, 0, 1, QCH_CON_SERIAL_LIF_DEBUG_VT_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_DEBUG_VT_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_SERIAL_LIF_DEBUG_VT_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_DEBUG_VT_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_SERIAL_LIF_DEBUG_VT_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_DEBUG_VT_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SERIAL_LIF_DEBUG_VT_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_SERIAL_LIF_DEBUG_VT_QCH_LIF_ENABLE, 0, 1, DMYQCH_CON_SERIAL_LIF_DEBUG_VT_QCH_LIF),
|
|
SFR_ACCESS(DMYQCH_CON_SERIAL_LIF_DEBUG_VT_QCH_LIF_CLOCK_REQ, 1, 1, DMYQCH_CON_SERIAL_LIF_DEBUG_VT_QCH_LIF),
|
|
SFR_ACCESS(DMYQCH_CON_SERIAL_LIF_DEBUG_VT_QCH_LIF_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SERIAL_LIF_DEBUG_VT_QCH_LIF),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0_ENABLE, 0, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0_CLOCK_REQ, 1, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_ENABLE, 0, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_CLOCK_REQ, 1, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1_ENABLE, 0, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1_CLOCK_REQ, 1, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_ENABLE, 0, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_CLOCK_REQ, 1, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD2_ENABLE, 0, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD2),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD2_CLOCK_REQ, 1, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD2),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD2_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD2),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2_ENABLE, 0, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2_CLOCK_REQ, 1, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_D_VTS_QCH_ENABLE, 0, 1, QCH_CON_SWEEPER_D_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_D_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SWEEPER_D_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_D_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SWEEPER_D_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_D_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SWEEPER_D_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_VTS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_QCH_ENABLE, 0, 1, QCH_CON_TIMER_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_QCH_CLOCK_REQ, 1, 1, QCH_CON_TIMER_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TIMER_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TIMER_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER1_QCH_ENABLE, 0, 1, QCH_CON_TIMER1_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER1_QCH_CLOCK_REQ, 1, 1, QCH_CON_TIMER1_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TIMER1_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TIMER1_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER2_QCH_ENABLE, 0, 1, QCH_CON_TIMER2_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER2_QCH_CLOCK_REQ, 1, 1, QCH_CON_TIMER2_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TIMER2_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TIMER2_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_QCH),
|
|
SFR_ACCESS(QCH_CON_VTS_CMU_VTS_QCH_ENABLE, 0, 1, QCH_CON_VTS_CMU_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_VTS_CMU_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_VTS_CMU_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_VTS_CMU_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VTS_CMU_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_VTS_CMU_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VTS_CMU_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_VTS_QCH_ENABLE, 0, 1, QCH_CON_WDT_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_FRC_MC_QCH_ENABLE, 0, 1, QCH_CON_FRC_MC_QCH),
|
|
SFR_ACCESS(QCH_CON_FRC_MC_QCH_CLOCK_REQ, 1, 1, QCH_CON_FRC_MC_QCH),
|
|
SFR_ACCESS(QCH_CON_FRC_MC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_FRC_MC_QCH),
|
|
SFR_ACCESS(QCH_CON_FRC_MC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_FRC_MC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHM_AXI_P_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHM_AXI_P_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_YUVPPMCSC_QCH_ENABLE, 0, 1, QCH_CON_LHS_AST_OTF_YUVPPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_YUVPPMCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AST_OTF_YUVPPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_YUVPPMCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AST_OTF_YUVPPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AST_OTF_YUVPPMCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AST_OTF_YUVPPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_YUVPPMCSC_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_YUVPPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_YUVPPMCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_YUVPPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_YUVPPMCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_YUVPPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LHS_AXI_D_YUVPPMCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LHS_AXI_D_YUVPPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_PPMU_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D0_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_QE_D0_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D0_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D0_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D0_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D0_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D0_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D0_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D10_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_QE_D10_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D10_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D10_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D10_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D10_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D10_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D10_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D11_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_QE_D11_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D11_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D11_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D11_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D11_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D11_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D11_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D1_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_QE_D1_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D1_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D1_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D1_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D1_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D1_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D1_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D2_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_QE_D2_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D2_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D2_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D2_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D2_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D2_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D2_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D3_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_QE_D3_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D3_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D3_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D3_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D3_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D3_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D3_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D4_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_QE_D4_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D4_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D4_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D4_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D4_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D4_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D4_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D5_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_QE_D5_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D5_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D5_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D5_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D5_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D5_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D5_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D6_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_QE_D6_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D6_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D6_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D6_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D6_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D6_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D6_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D7_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_QE_D7_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D7_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D7_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D7_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D7_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D7_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D7_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D8_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_QE_D8_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D8_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D8_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D8_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D8_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D8_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D8_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D9_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_QE_D9_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D9_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D9_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D9_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D9_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D9_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D9_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_YUVPP_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D_YUVPP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_YUVPP_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_YUVPP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_YUVPP_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D_YUVPP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_YUVPP_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_YUVPP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_YUVPP_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D_YUVPP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_YUVPP_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_YUVPP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_YUVPP_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D_YUVPP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_YUVPP_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_YUVPP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_YUVPP0_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_YUVPP0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_YUVPP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_YUVPP0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_YUVPP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_YUVPP0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_YUVPP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_YUVPP0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_YUVPP1_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_YUVPP1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_YUVPP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_YUVPP1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_YUVPP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_YUVPP1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_YUVPP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_YUVPP1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_YUVPP2_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_YUVPP2_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_YUVPP2_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_YUVPP2_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_YUVPP2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VGEN_LITE_YUVPP2_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_YUVPP2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_YUVPP2_QCH),
|
|
SFR_ACCESS(QCH_CON_YUVPP_CMU_YUVPP_QCH_ENABLE, 0, 1, QCH_CON_YUVPP_CMU_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_YUVPP_CMU_YUVPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_YUVPP_CMU_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_YUVPP_CMU_YUVPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_YUVPP_CMU_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_YUVPP_CMU_YUVPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_YUVPP_CMU_YUVPP_QCH),
|
|
SFR_ACCESS(QCH_CON_YUVPP_TOP_QCH_ENABLE, 0, 1, QCH_CON_YUVPP_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_YUVPP_TOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_YUVPP_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_YUVPP_TOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_YUVPP_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_YUVPP_TOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_YUVPP_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_YUVPP_TOP_QCH_C2COM_ENABLE, 0, 1, QCH_CON_YUVPP_TOP_QCH_C2COM),
|
|
SFR_ACCESS(QCH_CON_YUVPP_TOP_QCH_C2COM_CLOCK_REQ, 1, 1, QCH_CON_YUVPP_TOP_QCH_C2COM),
|
|
SFR_ACCESS(QCH_CON_YUVPP_TOP_QCH_C2COM_EXPIRE_VAL, 16, 10, QCH_CON_YUVPP_TOP_QCH_C2COM),
|
|
SFR_ACCESS(QCH_CON_YUVPP_TOP_QCH_C2COM_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_YUVPP_TOP_QCH_C2COM),
|
|
SFR_ACCESS(ALIVE_CMU_ALIVE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, ALIVE_CMU_ALIVE_CONTROLLER_OPTION),
|
|
SFR_ACCESS(ALIVE_CMU_ALIVE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, ALIVE_CMU_ALIVE_CONTROLLER_OPTION),
|
|
SFR_ACCESS(AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, AUD_CMU_AUD_CONTROLLER_OPTION),
|
|
SFR_ACCESS(AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, AUD_CMU_AUD_CONTROLLER_OPTION),
|
|
SFR_ACCESS(BUS0_CMU_BUS0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, BUS0_CMU_BUS0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(BUS0_CMU_BUS0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, BUS0_CMU_BUS0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(BUS1_CMU_BUS1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, BUS1_CMU_BUS1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(BUS1_CMU_BUS1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, BUS1_CMU_BUS1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(BUS2_CMU_BUS2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, BUS2_CMU_BUS2_CONTROLLER_OPTION),
|
|
SFR_ACCESS(BUS2_CMU_BUS2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, BUS2_CMU_BUS2_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CMGP_CMU_CMGP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CMGP_CMU_CMGP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CMU_CMU_TOP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CMU_CMU_TOP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CORE_CMU_CORE_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CORE_CMU_CORE_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CSIS_CMU_CSIS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CSIS_CMU_CSIS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DNS_CMU_DNS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, DNS_CMU_DNS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DNS_CMU_DNS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DNS_CMU_DNS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DPUB_CMU_DPUB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, DPUB_CMU_DPUB_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DPUB_CMU_DPUB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DPUB_CMU_DPUB_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DPUF0_CMU_DPUF0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, DPUF0_CMU_DPUF0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DPUF0_CMU_DPUF0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DPUF0_CMU_DPUF0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DPUF1_CMU_DPUF1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, DPUF1_CMU_DPUF1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DPUF1_CMU_DPUF1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DPUF1_CMU_DPUF1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DSU_CMU_DSU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, DSU_CMU_DSU_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DSU_CMU_DSU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DSU_CMU_DSU_CONTROLLER_OPTION),
|
|
SFR_ACCESS(G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, G3D_CMU_G3D_CONTROLLER_OPTION),
|
|
SFR_ACCESS(G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, G3D_CMU_G3D_CONTROLLER_OPTION),
|
|
SFR_ACCESS(G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION),
|
|
SFR_ACCESS(G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION),
|
|
SFR_ACCESS(HSI0_CMU_HSI0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, HSI0_CMU_HSI0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(HSI0_CMU_HSI0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, HSI0_CMU_HSI0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(HSI1_CMU_HSI1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, HSI1_CMU_HSI1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(HSI1_CMU_HSI1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, HSI1_CMU_HSI1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(ITP_CMU_ITP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, ITP_CMU_ITP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(ITP_CMU_ITP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, ITP_CMU_ITP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(LME_CMU_LME_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, LME_CMU_LME_CONTROLLER_OPTION),
|
|
SFR_ACCESS(LME_CMU_LME_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, LME_CMU_LME_CONTROLLER_OPTION),
|
|
SFR_ACCESS(M2M_CMU_M2M_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, M2M_CMU_M2M_CONTROLLER_OPTION),
|
|
SFR_ACCESS(M2M_CMU_M2M_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, M2M_CMU_M2M_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MCFP0_CMU_MCFP0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MCFP0_CMU_MCFP0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MCFP0_CMU_MCFP0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MCFP0_CMU_MCFP0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MCFP1_CMU_MCFP1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MCFP1_CMU_MCFP1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MCFP1_CMU_MCFP1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MCFP1_CMU_MCFP1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MCSC_CMU_MCSC_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MCSC_CMU_MCSC_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MFC0_CMU_MFC0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MFC0_CMU_MFC0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MFC0_CMU_MFC0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MFC0_CMU_MFC0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MFC1_CMU_MFC1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MFC1_CMU_MFC1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MFC1_CMU_MFC1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MFC1_CMU_MFC1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MIF_CMU_MIF_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MIF_CMU_MIF_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NPU_CMU_NPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, NPU_CMU_NPU_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NPU_CMU_NPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, NPU_CMU_NPU_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NPU01_CMU_NPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, NPU01_CMU_NPU_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NPU01_CMU_NPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, NPU01_CMU_NPU_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NPU10_CMU_NPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, NPU10_CMU_NPU_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NPU10_CMU_NPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, NPU10_CMU_NPU_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NPUS_CMU_NPUS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, NPUS_CMU_NPUS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NPUS_CMU_NPUS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, NPUS_CMU_NPUS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, PERIC0_CMU_PERIC0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PERIC0_CMU_PERIC0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, PERIC1_CMU_PERIC1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PERIC1_CMU_PERIC1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(PERIC2_CMU_PERIC2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, PERIC2_CMU_PERIC2_CONTROLLER_OPTION),
|
|
SFR_ACCESS(PERIC2_CMU_PERIC2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PERIC2_CMU_PERIC2_CONTROLLER_OPTION),
|
|
SFR_ACCESS(PERIS_CMU_PERIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, PERIS_CMU_PERIS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(PERIS_CMU_PERIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PERIS_CMU_PERIS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, S2D_CMU_S2D_CONTROLLER_OPTION),
|
|
SFR_ACCESS(S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, S2D_CMU_S2D_CONTROLLER_OPTION),
|
|
SFR_ACCESS(SSP_CMU_SSP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, SSP_CMU_SSP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(SSP_CMU_SSP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, SSP_CMU_SSP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(SSP_EMBEDDED_CMU_SSP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, SSP_EMBEDDED_CMU_SSP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(SSP_EMBEDDED_CMU_SSP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, SSP_EMBEDDED_CMU_SSP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(TAA_CMU_TAA_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, TAA_CMU_TAA_CONTROLLER_OPTION),
|
|
SFR_ACCESS(TAA_CMU_TAA_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, TAA_CMU_TAA_CONTROLLER_OPTION),
|
|
SFR_ACCESS(VPC_CMU_VPC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, VPC_CMU_VPC_CONTROLLER_OPTION),
|
|
SFR_ACCESS(VPC_CMU_VPC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, VPC_CMU_VPC_CONTROLLER_OPTION),
|
|
SFR_ACCESS(VPD_CMU_VPD_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, VPD_CMU_VPD_CONTROLLER_OPTION),
|
|
SFR_ACCESS(VPD_CMU_VPD_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, VPD_CMU_VPD_CONTROLLER_OPTION),
|
|
SFR_ACCESS(VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, VTS_CMU_VTS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, VTS_CMU_VTS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(YUVPP_CMU_YUVPP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, YUVPP_CMU_YUVPP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(YUVPP_CMU_YUVPP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, YUVPP_CMU_YUVPP_CONTROLLER_OPTION),
|
|
};
|
|
|