293 lines
8.3 KiB
C
Executable file
293 lines
8.3 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/**
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*
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* Copyright (c) 2021 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 of
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* the License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __PHY_SAMSUNG_USB_FW_CAL_H__
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#define __PHY_SAMSUNG_USB_FW_CAL_H__
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//#include <lk/list.h>
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#define EXYNOS_USBCON_VER_01_0_0 0x0100 /* Istor */
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#define EXYNOS_USBCON_VER_01_0_1 0x0101 /* JF 3.0 */
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#define EXYNOS_USBCON_VER_01_1_1 0x0111 /* KC */
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#define EXYNOS_USBCON_VER_01_MAX 0x01FF
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#define EXYNOS_USBCON_VER_02_0_0 0x0200 /* Insel-D, Island */
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#define EXYNOS_USBCON_VER_02_0_1 0x0201 /* JF EVT0 2.0 Host */
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#define EXYNOS_USBCON_VER_02_1_0 0x0210
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#define EXYNOS_USBCON_VER_02_1_1 0x0211 /* JF EVT1 2.0 Host */
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#define EXYNOS_USBCON_VER_02_1_2 0x0212 /* Katmai EVT0 */
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#define EXYNOS_USBCON_VER_02_MAX 0x02FF
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#define EXYNOS_USBCON_VER_03_0_0 0x0300 /* Lhotse, Lassen HS */
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#define EXYNOS_USBCON_VER_03_0_1 0x0301 /* Super Speed */
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#define EXYNOS_USBCON_VER_03_MAX 0x03FF
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/* Samsung phy */
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#define EXYNOS_USBCON_VER_04_0_0 0x0400 /* Exynos 9810 */
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#define EXYNOS_USBCON_VER_04_0_1 0x0401 /* Exynos 9820 */
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#define EXYNOS_USBCON_VER_04_0_2 0x0402 /* Exynos 9830 */
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#define EXYNOS_USBCON_VER_04_0_3 0x0403 /* Exynos 9630 */
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#define EXYNOS_USBCON_VER_04_0_4 0x0404 /* Exynos 9840 */
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#define EXYNOS_USBCON_VER_04_MAX 0x04FF
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/* Sub phy control - not include System/Link control */
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#define EXYNOS_USBCON_VER_05_0_0 0x0500 /* High Speed Only */
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#define EXYNOS_USBCON_VER_05_1_0 0x0510 /* Super Speed */
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#define EXYNOS_USBCON_VER_05_3_0 0x0530 /* Super Speed Dual PHY */
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#define EXYNOS_USBCON_VER_05_MAX 0x05FF
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/* block control version */
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#define EXYNOS_USBCON_VER_06_0_0 0x0600 /* link control only */
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#define EXYNOS_USBCON_VER_06_4_0 0x0610 /* link + usb2.0 phy */
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#define EXYNOS_USBCON_VER_06_2_0 0x0620 /* link + usb3.0 phy */
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#define EXYNOS_USBCON_VER_06_3_0 0x0630 /* link + usb2.0 + usb3.0 phy */
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#define EXYNOS_USBCON_VER_06_MAX 0x06FF
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/* eUSB phy contorller */
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#define EXYNOS_USBCON_VER_07_0_0 0x0700 /* eUSB PHY controller */
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#define EXYNOS_USBCON_VER_07_8_0 0x0780 /* dwc eUSB PHY register interface */
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/* synopsys usbdp phy contorller */
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#define EXYNOS_USBCON_VER_08_0_0 0x0800 /* dwc usb3p2/dp PHY controller */
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#define EXYNOS_USBCON_VER_F2_0_0 0xF200
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#define EXYNOS_USBCON_VER_F2_MAX 0xF2FF
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#define EXYNOS_USBCON_VER_MAJOR_VER_MASK 0xFF00
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#define EXYNOS_USBCON_VER_SS_ONLY_CAP 0x0010
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#define EXYNOS_USBCON_VER_SS_CAP 0x0040
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#define EXYNOS_USBCON_VER_SS_HS_CAP 0x0080
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#define EXYNOS_USBCON_VER_MINOR(_x) ((_x) &0xf)
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#define EXYNOS_USBCON_VER_MID(_x) ((_x) &0xf0)
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#define EXYNOS_USBCON_VER_MAJOR(_x) ((_x) &0xff00)
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#define EXYNOS_BLKCON_VER_HS_CAP 0x0010
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#define EXYNOS_BLKCON_VER_SS_CAP 0x0020
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#define HS_REWA_EN_STS_ENALBED 0
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#define HS_REWA_EN_STS_DISABLED 1
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#define HS_REWA_EN_STS_DISCONNECT 2
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#define HS_REWA_EN_STS_NOT_SUSPEND -1
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enum exynos_usbphy_mode {
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USBPHY_MODE_DEV = 0,
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USBPHY_MODE_HOST = 1,
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/* usb phy for uart bypass mode */
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USBPHY_MODE_BYPASS = 0x10,
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};
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// typedef unsigned char unsigned char;
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#ifndef __iomem
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#define __iomem
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#endif
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enum exynos_usbphy_refclk {
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USBPHY_REFCLK_DIFF_100MHZ = 0x80 | 0x27,
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USBPHY_REFCLK_DIFF_52MHZ = 0x80 | 0x02 | 0x40,
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USBPHY_REFCLK_DIFF_48MHZ = 0x80 | 0x2a | 0x40,
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USBPHY_REFCLK_DIFF_26MHZ = 0x80 | 0x02,
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USBPHY_REFCLK_DIFF_24MHZ = 0x80 | 0x2a,
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USBPHY_REFCLK_DIFF_20MHZ = 0x80 | 0x31,
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USBPHY_REFCLK_DIFF_19_2MHZ = 0x80 | 0x38,
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USBPHY_REFCLK_EXT_50MHZ = 0x07,
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USBPHY_REFCLK_EXT_48MHZ = 0x08,
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USBPHY_REFCLK_EXT_26MHZ = 0x06,
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USBPHY_REFCLK_EXT_24MHZ = 0x05,
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USBPHY_REFCLK_EXT_20MHZ = 0x04,
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USBPHY_REFCLK_EXT_19P2MHZ = 0x01,
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USBPHY_REFCLK_EXT_12MHZ = 0x02,
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};
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enum exynos_usbphy_refsel {
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USBPHY_REFSEL_CLKCORE = 0x2,
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USBPHY_REFSEL_EXT_OSC = 0x1,
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USBPHY_REFSEL_EXT_XTAL = 0x0,
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USBPHY_REFSEL_DIFF_PAD = 0x6,
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USBPHY_REFSEL_DIFF_INTERNAL = 0x4,
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USBPHY_REFSEL_DIFF_SINGLE = 0x3,
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};
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enum exynos_usbphy_utmi {
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USBPHY_UTMI_FREECLOCK,
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USBPHY_UTMI_PHYCLOCK,
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};
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enum exynos_usbphy_tune_para {
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USBPHY_TUNE_HS_COMPDIS = 0x0,
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USBPHY_TUNE_HS_OTG = 0x1,
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USBPHY_TUNE_HS_SQRX = 0x2,
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USBPHY_TUNE_HS_TXFSLS = 0x3,
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USBPHY_TUNE_HS_TXHSXV = 0x4,
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USBPHY_TUNE_HS_TXPREEMP = 0x5,
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USBPHY_TUNE_HS_TXPREEMP_PLUS = 0x6,
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USBPHY_TUNE_HS_TXRES = 0x7,
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USBPHY_TUNE_HS_TXRISE = 0x8,
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USBPHY_TUNE_HS_TXVREF = 0x9,
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USBPHY_TUNE_SS_TX_BOOST = 0x0 | 0x10000,
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USBPHY_TUNE_SS_TX_SWING = 0x1 | 0x10000,
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USBPHY_TUNE_SS_TX_DEEMPHASIS = 0x2 | 0x10000,
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USBPHY_TUNE_SS_LOS_BIAS = 0x3 | 0x10000,
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USBPHY_TUNE_SS_LOS_MASK_VAL = 0x4 | 0x10000,
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USBPHY_TUNE_SS_FIX_EQ = 0x5 | 0x10000,
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USBPHY_TUNE_SS_RX_EQ = 0x6 | 0x10000,
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USBPHY_TUNE_COMBO = 0x20000,
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USBPHY_TUNE_COMBO_TX_AMP = USBPHY_TUNE_COMBO | 0x0,
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USBPHY_TUNE_COMBO_TX_EMPHASIS = USBPHY_TUNE_COMBO | 0x1,
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USBPHY_TUNE_COMBO_TX_IDRV = USBPHY_TUNE_COMBO | 0x2,
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USBPHY_TUNE_COMBO_TX_ACCDRV = USBPHY_TUNE_COMBO | 0x3,
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};
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enum exynos_usb_bc {
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BC_NO_CHARGER,
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BC_SDP,
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BC_DCP,
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BC_CDP,
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BC_ACA_DOCK,
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BC_ACA_A,
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BC_ACA_B,
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BC_ACA_C,
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};
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struct exynos_usb_tune_param {
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char name[32];
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unsigned int value;
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};
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#define EXYNOS_USB_TUNE_LAST 0x4C415354
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/* HS PHY tune parameter */
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struct exynos_usbphy_hs_tune {
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unsigned char tx_vref;
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unsigned char tx_pre_emp;
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unsigned char tx_pre_emp_plus;
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unsigned char tx_res;
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unsigned char tx_rise;
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unsigned char tx_hsxv;
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unsigned char tx_fsls;
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unsigned char rx_sqrx;
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unsigned char compdis;
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unsigned char otg;
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unsigned char enable_user_imp;
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unsigned char user_imp_value;
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enum exynos_usbphy_utmi utmi_clk;
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};
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/* SS PHY tune parameter */
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struct exynos_usbphy_ss_tune {
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/* TX Swing Level*/
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unsigned char tx_boost_level;
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unsigned char tx_swing_level;
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unsigned char tx_swing_full;
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unsigned char tx_swing_low;
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/* TX De-Emphasis */
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unsigned char tx_deemphasis_mode;
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unsigned char tx_deemphasis_3p5db;
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unsigned char tx_deemphasis_6db;
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/* SSC Operation*/
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unsigned char enable_ssc;
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unsigned char ssc_range;
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/* Loss-of-Signal detector threshold level */
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unsigned char los_bias;
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/* Loss-of-Signal mask width */
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unsigned short los_mask_val;
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/* RX equalizer mode */
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unsigned char enable_fixed_rxeq_mode;
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unsigned char fix_rxeq_value;
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/* Decrease TX Impedance */
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unsigned char decrease_ss_tx_imp;
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unsigned char set_crport_level_en;
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unsigned char set_crport_mpll_charge_pump;
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/* RX LFPS(decode) mode */
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unsigned char rx_decode_mode;
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};
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/**
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* struct exynos_usbphy_info : USBPHY information to share USBPHY CAL code
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* @version: PHY controller version
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* 0x0100 - for EXYNOS_USB3 : EXYNOS7420, EXYNOS7890
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* 0x0101 - EXYNOS8890
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* 0x0111 - EXYNOS8895
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* 0x0200 - for EXYNOS_USB2 : EXYNOS7580, EXYNOS3475
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* 0x0210 - EXYNOS8890_EVT1
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* 0xF200 - for EXT : EXYNOS7420_HSIC
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* @refclk: reference clock frequency for USBPHY
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* @refsrc: reference clock source path for USBPHY
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* @use_io_for_ovc: use over-current notification io for USBLINK
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* @regs_base: base address of PHY control register *
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*/
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struct exynos_usbphy_info {
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/* Device Information */
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struct device *dev;
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u32 version;
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enum exynos_usbphy_refclk refclk;
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enum exynos_usbphy_refsel refsel;
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bool use_io_for_ovc;
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bool common_block_disable;
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bool not_used_vbus_pad;
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void __iomem *regs_base;
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/* HS PHY tune parameter */
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struct exynos_usbphy_hs_tune *hs_tune;
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/* SS PHY tune parameter */
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struct exynos_usbphy_ss_tune *ss_tune;
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/* Tune Parma list */
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struct exynos_usb_tune_param *tune_param;
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/* multiple phy */
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int hw_version;
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void __iomem *regs_base_2nd;
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void __iomem *pma_base;
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void __iomem *pcs_base;
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void __iomem *ctrl_base;
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void __iomem *link_base;
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int used_phy_port;
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/* Alternative PHY REF_CLK source */
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bool alt_ref_clk;
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/* Remote Wake-up Advisor */
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unsigned hs_rewa : 1;
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unsigned hs_rewa_src;
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unsigned u3_rewa;
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/* Dual PHY */
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bool dual_phy;
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};
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struct usb_eom_result_s {
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u32 phase;
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u32 vref;
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u64 err;
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};
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#define EOM_PH_SEL_MAX 72
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#define EOM_DEF_VREF_MAX 256
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void phy_usb_exynos_register_cal_infor(struct exynos_usbphy_info *cal_info);
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#endif /* __PHY_SAMSUNG_USB_FW_CAL_H__ */
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