266 lines
5.5 KiB
C
Executable file
266 lines
5.5 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/**
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*
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* Copyright (c) 2021 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 of
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* the License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _USB_USBPHY_CAL_EUSB_CON_REG_H_
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#define _USB_USBPHY_CAL_EUSB_CON_REG_H_
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#define EUSBCON_REG_RST_CTRL 0x0000
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/* Offset : 0x0000
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* Description: Control eUSB PHY Reset pins
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*/
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typedef union {
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u32 data;
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struct {
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// bit[0] :
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unsigned phy_reset : 1;
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// bit[1] :
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unsigned phy_reset_ovrd_en : 1;
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// bit[3:2]
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unsigned RSVD3_2 : 2;
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// bit[4] :
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unsigned utmi_port_reset : 1;
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// bit[5] :
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unsigned utmi_port_reset_ovrd_en : 1;
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// bit[31:6]
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unsigned RSVD31_6 : 26;
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} b;
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} EUSBCON_REG_RST_CTRL_o, *EUSBPHY_REG_RST_CTRL_p;
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#define EUSBCON_REG_CMN_CTRL 0x0004
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/* Offset : 0x0004
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* Description: common block control signals
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*/
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typedef union {
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u32 data;
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struct {
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// bit[0] :
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unsigned phy_enable : 1;
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// bit[1] :
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unsigned retenable_n : 1;
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// bit[3:2]
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unsigned RSVD3_2 : 2;
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// bit[6:4] :
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unsigned ref_freq_sel : 3;
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// bit[7]
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unsigned RSVD7 : 1;
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// bit[8] :
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unsigned phy_cfg_cr_clk_sel : 1;
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// bit[9] :
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unsigned phy_cfg_port_in_lx : 1;
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// bit[10] :
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unsigned phy_cfg_rptr_mode : 1;
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// bit[31:11]
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unsigned RSVD31_11 : 21;
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} b;
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} EUSBCON_REG_CMN_CTRL_o, *EUSBPHY_REG_CMN_CTRL_p;
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#define EUSBCON_REG_PLLCFG0 0x0008
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/* Offset : 0x0008
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* Description: configure phy pll
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*/
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typedef union {
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u32 data;
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struct {
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// bit[6:0] :
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unsigned pll_cpbias_cntrl : 7;
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// bit[7] :
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unsigned RSVD7 : 1;
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// bit[19:8] :
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unsigned pll_fb_div : 12;
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// bit[21:20]
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unsigned pll_gmp_cntrl : 2;
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// bit[23:22] :
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unsigned RSVD23_22 : 2;
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// bit[29:24] :
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unsigned pll_int_cntrl : 6;
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// bit[31:30]
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unsigned RSVD31_30 : 2;
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} b;
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} EUSBCON_REG_PLLCFG0_o, *EUSBPHY_REG_PLLCFG0_p;
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#define EUSBCON_REG_PLLCFG1 0x000C
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/* Offset : 0x000c
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* Description: configure phy pll
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*/
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typedef union {
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u32 data;
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struct {
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// bit[5:0] :
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unsigned pll_prop_cntrl : 6;
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// bit[7:6] :
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unsigned RSVD7_6 : 2;
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// bit[11:8] :
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unsigned pll_ref_div : 4;
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// bit[14:12]
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unsigned pll_vco_cntrl : 3;
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// bit[15] :
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unsigned RSVD15 : 1;
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// bit[17:16] :
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unsigned pll_vref_tune : 2;
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// bit[31:18]
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unsigned RSVD31_30 : 14;
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} b;
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} EUSBCON_REG_PLLCFG1_o, *EUSBPHY_REG_PLLCFG1_p;
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#define EUSBCON_REG_RCAL 0x0010
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/* Offset : 0x0010
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* Description: control external register calibration(rcal)
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*/
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typedef union {
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u32 data;
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struct {
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// bit[0] :
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unsigned rcal_bypass : 1;
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// bit[3:1] :
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unsigned RSVD3_1 : 3;
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// bit[7:4] :
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unsigned rcal_code : 4;
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// bit[11:8]
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unsigned rcal_offset : 4;
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// bit[31:12]
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unsigned RSVD31_12 : 20;
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} b;
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} EUSBCON_REG_RCAL_o, *EUSBPHY_REG_RCAL_p;
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#define EUSBCON_REG_TXTUNE 0x0014
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/* Offset : 0x0014
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* Description: tune register of tx driver
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*/
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typedef union {
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u32 data;
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struct {
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// bit[0] :
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unsigned fsls_slew_rate : 1;
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// bit[2:1] :
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unsigned fsls_vref_tune : 2;
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// bit[3] :
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unsigned fsls_vreg_bypass : 1;
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// bit[6:4]
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unsigned hs_vref_tune : 3;
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// bit [8:7]
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unsigned hs_xv : 2;
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// bit [11:9]
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unsigned preemp : 3;
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// bit [13:12]
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unsigned res : 2;
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// bit [15:14]
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unsigned rise : 2;
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// bit[31:16]
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unsigned RSVD31_16 : 16;
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} b;
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} EUSBCON_REG_TXTUNE_o, *EUSBPHY_REG_TXTUNE_p;
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#define EUSBCON_REG_RXTUNE 0x0018
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/* Offset : 0x0018
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* Description: tune register of rx driver
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*/
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typedef union {
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u32 data;
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struct {
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// bit[1:0] :
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unsigned eq_ctle : 2;
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// bit[3:2] :
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unsigned RSVD3_2 : 2;
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// bit[3] :
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unsigned hs_term_en : 1;
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// bit[7:5]
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unsigned RSVD7_5 : 3;
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// bit [10:8]
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unsigned hs_tune : 3;
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// bit[31:11]
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unsigned RSVD31_16 : 21;
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} b;
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} EUSBCON_REG_RXTUNE_o, *EUSBPHY_REG_RXTUNE_p;
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#define EUSBCON_REG_UTMI 0x001C
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/* Offset : 0x001C
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* Description: control utmi interface signal
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*/
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typedef union {
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u32 data;
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struct {
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// bit[0] :
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unsigned clk_force_en : 1;
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// bit[1] :
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unsigned dm_pulldown : 1;
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// bit[2] :
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unsigned dm_pulldown_ovrd_en : 1;
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// bit[3] :
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unsigned dp_pulldown : 1;
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// bit[4] :
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unsigned dp_pulldown_ovrd_en : 1;
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// bit[5] :
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unsigned sleep_n : 1;
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// bit[6] :
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unsigned sleep_n_ovrd_en : 1;
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// bit[7] :
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unsigned suspend_n : 1;
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// bit[8] :
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unsigned suspend_n_ovrd_en : 1;
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// bit[9] :
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unsigned txbitstuffen : 1;
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// bit[10] :
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unsigned txbitstuffen_ovrd_en : 1;
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// bit[11] :
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unsigned vbus_valid_ext : 1;
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// bit[12] :
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unsigned vbus_valid_ext_ovrd_en : 1;
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// bit[31:13]
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unsigned RSVD31_13 : 17;
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} b;
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} EUSBCON_REG_UTMI_o, *EUSBPHY_REG_UTMI_p;
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#define EUSBCON_REG_TESTSE 0x0020
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/* Offset : 0x0020
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* Description: control test pin
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*/
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typedef union {
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u32 data;
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struct {
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// bit[0] :
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unsigned test_loopback_en : 1;
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// bit[1] :
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unsigned test_stop_clk_en : 1;
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// bit[2] :
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unsigned tx_se_dp_en : 1;
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// bit[3] :
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unsigned tx_se_dm_en : 1;
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// bit[4] :
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unsigned tx_dig_bypass_sel : 1;
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// bit[5] :
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unsigned tx_se_test_en : 1;
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// bit[6] :
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unsigned test_iddq : 1;
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// bit[7] :
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unsigned mon_phy_rx_se_dp : 1;
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// bit[8] :
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unsigned mon_phy_rx_se_dm : 1;
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// bit[31:9]
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unsigned RSVD31_13 : 23;
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} b;
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} EUSBCON_REG_TESTSE_o, *EUSBPHY_REG_TESTSE_p;
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#endif
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