231 lines
6.2 KiB
C
Executable file
231 lines
6.2 KiB
C
Executable file
/* linux/drivers/media/platform/exynos/mmsqz-regs.h
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*
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* Register definition file for Samsung JPEG Squeezer driver
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*
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* Copyright (c) 2018 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Jungik Seo <jungik.seo@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef JSQZ_REGS_H_
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#define JSQZ_REGS_H_
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include "jsqz-core.h"
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// SFR
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#define REG_0_Y_ADDR 0x000
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#define REG_1_U_ADDR 0x004
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#define REG_2_V_ADDR 0x008
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#define REG_3_INPUT_SIZE 0x00C
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#define REG_4_INPUT_TYPE 0x010
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#define REG_5_OP_MODE 0x014
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#define REG_6_CONFIG_DC 0x018
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#define REG_7_TO_22_Y_Q_MAT 0x01C
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#define REG_23_TO_38_C_Q_MAT 0x05C
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#define REG_39_SW_RESET 0x09C
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#define REG_40_INTERRUPT_EN 0x0A0
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#define REG_41_INTERRUPT_CLEAR 0x0A4
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#define REG_42_MMSQZ_HW_START 0x0A8
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#define REG_43_MMSQZ_HW_DONE 0x0AC
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#define REG_44_CONFIG_STRIDE 0x0B0
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#define REG_45_CONFIG_TIMEOUT 0x0B4
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#define REG_46_HW_DEBUG 0x0B8
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#define REG_47_ERROR_FLAG 0x0BC
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#define REG_48_TO_63_INIT_Y_Q 0x0C0
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#define REG_64_TO_79_INIT_C_Q 0x100
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#define REG_80_VELOCITY 0x140
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#define REG_81_TUNE_DC 0x144
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#define REG_82_TUNE_ALPHA 0x148
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#define REG_83_TUNE_DQP 0x14C
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#define REG_84_FRM_AVG_DQP 0x150
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#define REG_85_DQP_ADDR 0x154
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// define APIs
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static inline void jsqz_sw_reset(void __iomem *base)
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{
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writel(0x0, base + REG_39_SW_RESET);
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writel(0x1, base + REG_39_SW_RESET);
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}
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static inline void jsqz_interrupt_enable(void __iomem *base)
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{
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writel(0x1, base + REG_40_INTERRUPT_EN);
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//writel(0x0, base + REG_41_INTERRUPT_CLEAR);
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}
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static inline void jsqz_interrupt_disable(void __iomem *base)
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{
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writel(0x0, base + REG_40_INTERRUPT_EN);
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}
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static inline void jsqz_interrupt_clear(void __iomem *base)
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{
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writel(0x1, base + REG_41_INTERRUPT_CLEAR);
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}
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static inline u32 jsqz_get_interrupt_status(void __iomem *base)
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{
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return readl(base + REG_41_INTERRUPT_CLEAR);
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}
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static inline void jsqz_hw_start(void __iomem *base)
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{
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writel(0x1, base + REG_42_MMSQZ_HW_START);
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}
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static inline u32 jsqz_check_done(void __iomem *base)
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{
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return readl(base + REG_43_MMSQZ_HW_DONE) & 0x1;
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}
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static inline void jsqz_on_off_time_out(void __iomem *base, u32 time)
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{
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u32 sfr = 0;
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if (time == 0)
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writel(0x0, base + REG_45_CONFIG_TIMEOUT);
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else {
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sfr = (time * 533) >> 7;
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writel((sfr | 0x00020000), base + REG_45_CONFIG_TIMEOUT);
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}
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}
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static inline void jsqz_set_stride_on_n_value(void __iomem *base, u32 value)
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{
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if (value == 0)
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writel(0x0, base + REG_44_CONFIG_STRIDE);
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else
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writel((value | 0x00010000), base + REG_44_CONFIG_STRIDE);
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}
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static inline void jsqz_set_input_size(void __iomem *base, u32 size)
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{
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writel(size, base + REG_3_INPUT_SIZE);
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}
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static inline void jsqz_set_input_configs(void __iomem *base, u32 type, u32 mode, u32 use_dc)
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{
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writel(type, base + REG_4_INPUT_TYPE);
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writel(mode, base + REG_5_OP_MODE);
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writel(use_dc, base + REG_6_CONFIG_DC);
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}
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static inline void jsqz_set_input_addr_luma(void __iomem *base, dma_addr_t y_addr)
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{
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writel(y_addr, base + REG_0_Y_ADDR);
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}
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static inline void jsqz_set_input_addr_chroma(void __iomem *base, dma_addr_t u_addr, dma_addr_t v_addr)
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{
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writel(u_addr, base + REG_1_U_ADDR);
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writel(v_addr, base + REG_2_V_ADDR);
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}
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static inline void jsqz_set_input_qtbl(void __iomem *base, u32 * input_qt)
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{
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int i;
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for (i = 0; i < 16; i++)
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{
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writel(input_qt[i], base + REG_48_TO_63_INIT_Y_Q + (i * 0x4));
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writel(input_qt[i+16], base + REG_64_TO_79_INIT_C_Q + (i * 0x4));
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}
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}
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static inline u32 jsqz_get_error_flags(void __iomem *base)
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{
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return readl(base + REG_47_ERROR_FLAG);
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}
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static inline void jsqz_get_init_qtbl(void __iomem *base, u32 * init_qt)
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{
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int i;
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for (i = 0; i < 16; i++)
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{
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init_qt[i] = readl(base + REG_48_TO_63_INIT_Y_Q + (i * 0x4));
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init_qt[i+16] = readl(base + REG_64_TO_79_INIT_C_Q + (i * 0x4));
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}
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}
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static inline void jsqz_get_output_regs(void __iomem *base, u32 * output_qt)
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{
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int i;
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for (i = 0; i < 16; i++)
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{
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output_qt[i] = readl(base + REG_7_TO_22_Y_Q_MAT + (i * 0x4));
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output_qt[i+16] = readl(base + REG_23_TO_38_C_Q_MAT + (i * 0x4));
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}
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}
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static inline void jsqz_set_output_addr(void __iomem *base, dma_addr_t dqp_addr)
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{
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writel(dqp_addr, base + REG_85_DQP_ADDR);
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}
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static inline void jsqz_set_velocity(void __iomem *base, u32 vel_xy)
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{
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writel(vel_xy, base + REG_80_VELOCITY);
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}
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static inline void jsqz_set_tune_dc(void __iomem *base, u32 dc)
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{
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writel(dc, base + REG_81_TUNE_DC);
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}
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static inline void jsqz_set_tune_alpha(void __iomem *base, u32 alpha)
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{
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writel(alpha, base + REG_82_TUNE_ALPHA);
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}
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static inline void jsqz_set_tune_dqp(void __iomem *base, u32 dqp)
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{
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writel(dqp, base + REG_83_TUNE_DQP);
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}
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static inline u32 jsqz_get_frame_dqp(void __iomem *base)
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{
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return readl(base + REG_84_FRM_AVG_DQP);
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}
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static inline void jsqz_print_all_regs(struct jsqz_dev *jsqz)
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{
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int i;
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void __iomem *base = jsqz->regs;
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dev_dbg(jsqz->dev, "%s: BEGIN\n", __func__);
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for (i = 0; i < 7; i++)
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{
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dev_dbg(jsqz->dev, "%s: 0x%08x : %08x\n", __func__, (i*0x4), readl(base + (i*0x4)));
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}
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for (i = 0; i < 7; i++)
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{
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dev_dbg(jsqz->dev, "%s: 0x%08x : %08x\n", __func__, (REG_39_SW_RESET + (i*0x4)), readl(base + REG_39_SW_RESET + (i*0x4)));
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}
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dev_dbg(jsqz->dev, "%s: 0x%08x : %08x\n", __func__, REG_47_ERROR_FLAG, readl(base + REG_47_ERROR_FLAG));
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for (i = 0; i < 6; i++)
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{
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dev_dbg(jsqz->dev, "%s: 0x%08x : %08x\n", __func__, (REG_80_VELOCITY + (i*0x4)), readl(base + REG_80_VELOCITY + (i*0x4)));
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}
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dev_dbg(jsqz->dev, "%s: END\n", __func__);
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}
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/*
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static inline int get_hw_enc_status(void __iomem *base)
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{
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unsigned int status = 0;
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status = readl(base + MMSQZ_ENC_STAT_REG) & (KBit0 | KBit1);
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return (status != 0 ? -1:0);
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}
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*/
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#endif /* JSQZ_REGS_H_ */
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