kernel_samsung_a53x/arch/x86
Zhang Rui 5a5d98e292 x86/apic: Always explicitly disarm TSC-deadline timer
commit ffd95846c6ec6cf1f93da411ea10d504036cab42 upstream.

New processors have become pickier about the local APIC timer state
before entering low power modes. These low power modes are used (for
example) when you close your laptop lid and suspend. If you put your
laptop in a bag and it is not in this low power mode, it is likely
to get quite toasty while it quickly sucks the battery dry.

The problem boils down to some CPUs' inability to power down until the
CPU recognizes that the local APIC timer is shut down. The current
kernel code works in one-shot and periodic modes but does not work for
deadline mode. Deadline mode has been the supported and preferred mode
on Intel CPUs for over a decade and uses an MSR to drive the timer
instead of an APIC register.

Disable the TSC Deadline timer in lapic_timer_shutdown() by writing to
MSR_IA32_TSC_DEADLINE when in TSC-deadline mode. Also avoid writing
to the initial-count register (APIC_TMICT) which is ignored in
TSC-deadline mode.

Note: The APIC_LVTT|=APIC_LVT_MASKED operation should theoretically be
enough to tell the hardware that the timer will not fire in any of the
timer modes. But mitigating AMD erratum 411[1] also requires clearing
out APIC_TMICT. Solely setting APIC_LVT_MASKED is also ineffective in
practice on Intel Lunar Lake systems, which is the motivation for this
change.

1. 411 Processor May Exit Message-Triggered C1E State Without an Interrupt if Local APIC Timer Reaches Zero - https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/revision-guides/41322_10h_Rev_Gd.pdf

Fixes: 279f1461432c ("x86: apic: Use tsc deadline for oneshot when available")
Suggested-by: Dave Hansen <dave.hansen@intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Tested-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Tested-by: Todd Brandt <todd.e.brandt@intel.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/all/20241015061522.25288-1-rui.zhang%40intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-11-23 23:21:57 +01:00
..
boot x86/boot: Ignore NMIs during very early boot 2024-11-18 12:13:08 +01:00
configs Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
crypto crypto: x86/sha256-avx2 - add missing vzeroupper 2024-11-19 12:26:52 +01:00
entry x86/entry: Have entry_ibpb() invalidate return predictions 2024-11-23 23:21:55 +01:00
events perf/x86/intel/pt: Fix sampling synchronization 2024-11-23 23:21:31 +01:00
hyperv Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
ia32 Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
include x86/cpufeatures: Add a IBPB_NO_RET BUG flag 2024-11-23 23:21:55 +01:00
kernel x86/apic: Always explicitly disarm TSC-deadline timer 2024-11-23 23:21:57 +01:00
kvm KVM: VMX: Split out the non-virtualization part of vmx_interrupt_blocked() 2024-11-23 23:20:13 +01:00
lib x86/retpoline: Move a NOENDBR annotation to the SRSO dummy return thunk 2024-11-19 14:19:45 +01:00
math-emu Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
mm x86/mm: Switch to new Intel CPU model defines 2024-11-23 23:21:29 +01:00
net x86/returnthunk: Allow different return thunks 2024-11-18 22:25:38 +01:00
oprofile Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
pci x86/pci/xen: Fix PCIBIOS_* return code handling 2024-11-23 23:19:56 +01:00
platform x86/platform/iosf_mbi: Convert PCIBIOS_* return codes to errnos 2024-11-23 23:19:56 +01:00
power x86/stackprotector/32: Make the canary into a regular percpu variable 2024-11-19 09:22:37 +01:00
purgatory Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
ras Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
realmode Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
tools x86/boot: Ignore relocations in .notes sections in walk_relocs() too 2024-11-19 12:26:53 +01:00
um Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
video Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
xen xen: use correct end address of kernel for conflict checking 2024-11-23 23:21:22 +01:00
Kbuild Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
Kconfig cpu: Re-enable CPU mitigations by default for !X86 architectures 2024-11-19 11:32:38 +01:00
Kconfig.assembler Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00
Kconfig.cpu x86/Kconfig: Transmeta Crusoe is CPU family 5, not 6 2024-11-18 12:13:31 +01:00
Kconfig.debug x86/kconfig: Select ARCH_WANT_FRAME_POINTERS again when UNWINDER_FRAME_POINTER=y 2024-11-19 12:27:09 +01:00
Makefile x86/stackprotector/32: Make the canary into a regular percpu variable 2024-11-19 09:22:37 +01:00
Makefile.um um: allow not setting extra rpaths in the linux binary 2024-11-18 23:19:35 +01:00
Makefile_32.cpu Import A536BXXU9EXDC 2024-06-15 16:02:09 -03:00