2251 lines
82 KiB
C
Executable file
2251 lines
82 KiB
C
Executable file
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* ALSA SoC - Samsung Abox SoC dependent layer for ABOX 3.1
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*
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* Copyright (c) 2021 Samsung Electronics Co. Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "abox_soc_31.h"
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bool accessible_reg(unsigned int reg)
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{
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switch (reg) {
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case ABOX_IP_INDEX:
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case ABOX_VERSION:
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case ABOX_SYSPOWER_CTRL:
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case ABOX_SYSPOWER_STATUS:
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case ABOX_SYSTEM_CONFIG0:
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case ABOX_SYSTEM_CONFIG1:
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case ABOX_REMAP_MASK:
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case ABOX_REMAP_ADDR:
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case ABOX_DYN_CLOCK_OFF:
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case ABOX_DYN_CLOCK_OFF1:
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case ABOX_DYN_CLOCK_OFF2:
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case ABOX_QCHANNEL_DISABLE:
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case ABOX_TICK_DIV_RATIO:
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case ABOX_TICK_GEN:
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case ABOX_ROUTE_CTRL0:
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case ABOX_ROUTE_CTRL1:
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case ABOX_ROUTE_CTRL2:
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case ABOX_ROUTE_CTRL3:
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case ABOX_ROUTE_CTRL4:
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case ABOX_ROUTE_CTRL5:
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case ABOX_ROUTE_CTRL_CONNECT:
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case ABOX_ROUTE_PDI_CTRL0:
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case ABOX_ROUTE_PDI_CTRL1:
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case ABOX_ROUTE_PDI_CTRL2:
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case ABOX_ROUTE_UDMA_SIFM:
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case ABOX_SPUS_CTRL_FC0:
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case ABOX_SPUS_CTRL_FC1:
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case ABOX_SPUS_CTRL_FC2:
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case ABOX_SPUS_CTRL_FC3:
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case ABOX_SPUS_CTRL_FC4:
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case ABOX_SPUS_CTRL_FC5:
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case ABOX_SPUS_CTRL_SIFS_SEL0:
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case ABOX_SPUS_CTRL_SIFS_SEL1:
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case ABOX_SPUS_CTRL_SIFM_SEL:
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case ABOX_SPUS_CTRL_TUNE_SEL:
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case ABOX_SPUS_CTRL_MIXP_FORMAT:
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case ABOX_SPUS_CTRL_SIFS_CH_CTRL0:
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case ABOX_SPUS_CTRL_SIFS_CH_CTRL1:
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case ABOX_SPUS_CTRL_FLUSH:
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case ABOX_SPUS_CTRL_ASRC_ID0:
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case ABOX_SPUS_CTRL_ASRC_ID1:
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case ABOX_SPUS_CTRL_ASRC_ID2:
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case ABOX_SPUS_CTRL_SIFS_CH_SEL0:
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case ABOX_SPUS_CTRL_SIFS_CH_SEL1:
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case ABOX_SPUS_CTRL_SIFS_CNT0:
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case ABOX_SPUS_CTRL_SIFS_CNT1:
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case ABOX_SPUS_CTRL_SIFS_CNT2:
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case ABOX_SPUS_CTRL_SIFS_CNT3:
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case ABOX_SPUS_CTRL_SIFS_CNT4:
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case ABOX_SPUS_CTRL_SIFS_CNT5:
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case ABOX_SPUS_CTRL_SIFS_CNT6:
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case ABOX_SPUS_LATENCY_CTRL0:
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case ABOX_SPUS_LATENCY_CTRL1:
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case ABOX_SPUS_LATENCY_CTRL2:
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case ABOX_SPUS_LATENCY_CTRL3:
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case ABOX_SPUS_SBANK_RDMA(0):
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case ABOX_SPUS_SBANK_RDMA(1):
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case ABOX_SPUS_SBANK_RDMA(2):
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case ABOX_SPUS_SBANK_RDMA(3):
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case ABOX_SPUS_SBANK_RDMA(4):
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case ABOX_SPUS_SBANK_RDMA(5):
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case ABOX_SPUS_SBANK_RDMA(6):
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case ABOX_SPUS_SBANK_RDMA(7):
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case ABOX_SPUS_SBANK_RDMA(8):
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case ABOX_SPUS_SBANK_RDMA(9):
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case ABOX_SPUS_SBANK_RDMA(10):
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case ABOX_SPUS_SBANK_RDMA(11):
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case ABOX_SPUS_SBANK_ASRC(0):
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case ABOX_SPUS_SBANK_ASRC(1):
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case ABOX_SPUS_SBANK_ASRC(2):
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case ABOX_SPUS_SBANK_ASRC(3):
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case ABOX_SPUS_SBANK_ASRC(4):
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case ABOX_SPUS_SBANK_ASRC(5):
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case ABOX_SPUS_SBANK_ASRC(6):
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case ABOX_SPUS_SBANK_ASRC(7):
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case ABOX_SPUS_SBANK_MIXP:
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case ABOX_SPUS_SBANK_SIDETONE:
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case ABOX_SPUS_SBANK_STMIX:
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case ABOX_SPUS_SBANK_USG(0):
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case ABOX_SPUS_SBANK_USG(1):
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case ABOX_SPUS_SBANK_BQF(0):
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case ABOX_SPUS_SBANK_BQF(1):
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case ABOX_SPUS_SBANK_DRC(0):
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case ABOX_SPUS_SBANK_DRC(1):
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case ABOX_SPUS_SBANK_DSG(0):
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case ABOX_SPUS_SBANK_DSG(1):
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case ABOX_SPUM_CTRL_FC0:
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case ABOX_SPUM_CTRL_FC1:
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case ABOX_SPUM_CTRL_FC2:
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case ABOX_SPUM_CTRL_FC3:
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case ABOX_SPUM_CTRL_SIFS_SEL:
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case ABOX_SPUM_CTRL_TUNE_SEL:
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case ABOX_SPUM_CTRL_FLUSH:
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case ABOX_SPUM_CTRL_SIFM_CH_CTRL0:
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case ABOX_SPUM_CTRL_SIFM_CH_CTRL1:
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case ABOX_SPUM_CTRL_ASRC_ID0:
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case ABOX_SPUM_CTRL_ASRC_ID1:
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case ABOX_SPUM_CTRL_SIFM_CH_SEL0:
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case ABOX_SPUM_CTRL_SIFM_CH_SEL1:
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case ABOX_SPUM_SBANK_NSRC(0):
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case ABOX_SPUM_SBANK_NSRC(1):
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case ABOX_SPUM_SBANK_NSRC(2):
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case ABOX_SPUM_SBANK_NSRC(3):
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case ABOX_SPUM_SBANK_NSRC(4):
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case ABOX_SPUM_SBANK_NSRC(5):
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case ABOX_SPUM_SBANK_NSRC(6):
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case ABOX_SPUM_SBANK_NSRC(7):
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case ABOX_SPUM_SBANK_ASRC(0):
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case ABOX_SPUM_SBANK_ASRC(1):
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case ABOX_SPUM_SBANK_ASRC(2):
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case ABOX_SPUM_SBANK_ASRC(3):
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case ABOX_SPUM_SBANK_USG(0):
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case ABOX_SPUM_SBANK_USG(1):
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case ABOX_SPUM_SBANK_BQF(0):
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case ABOX_SPUM_SBANK_BQF(1):
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case ABOX_SPUM_SBANK_DRC(0):
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case ABOX_SPUM_SBANK_DRC(1):
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case ABOX_SPUM_SBANK_DSG(0):
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case ABOX_SPUM_SBANK_DSG(1):
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case ABOX_AUDEN_FC_MAIN_CTRL0:
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case ABOX_AUDEN_FC_MAIN_CTRL1:
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case ABOX_AUDEN_FC_MAIN_CTRL2:
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case ABOX_AUDEN_FC_ASRC_CTRL0:
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case ABOX_AUDEN_FC_ASRC_CTRL1:
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case ABOX_AUDEN_FC_ASRC_CTRL2:
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case ABOX_AUDEN_FC_MIXP_CTRL0:
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case ABOX_AUDEN_FC_MIXP_CTRL1:
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case ABOX_AUDEN_FC_MIXP_CTRL2:
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case ABOX_AUDEN_FC_WDMA_CTRL0:
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case ABOX_AUDEN_FC_WDMA_CTRL1:
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case ABOX_AUDEN_MIXP_CTRL(0):
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case ABOX_AUDEN_MIXP_CTRL(1):
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case ABOX_AUDEN_MIXP_CTRL(2):
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case ABOX_AUDEN_ASRC_PERF_CON(0):
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case ABOX_AUDEN_ASRC_PERF_CON(1):
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case ABOX_AUDEN_ASRC_PERF_CON(2):
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case ABOX_AUDEN_ASRC_PERF_CON(3):
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case ABOX_AUDEN_ASRC_PERF_CON(4):
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case ABOX_AUDEN_ASRC_PERF_CON(5):
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case ABOX_AUDEN_ASRC_PERF_CON(6):
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case ABOX_AUDEN_ASRC_PERF_CON(7):
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case ABOX_AUDEN_ASRC_PERF_CON(8):
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case ABOX_AUDEN_ASRC_PERF_CON(9):
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case ABOX_AUDEN_ASRC_PERF_CON(10):
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case ABOX_AUDEN_ASRC_PERF_CON(11):
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case ABOX_AUDEN_ASRC_DUMMY_CTRL(0):
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case ABOX_AUDEN_ASRC_DUMMY_CTRL(1):
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case ABOX_AUDEN_ASRC_DUMMY_CTRL(2):
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case ABOX_AUDEN_ASRC_DUMMY_CTRL(3):
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case ABOX_AUDEN_ASRC_DUMMY_CTRL(4):
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case ABOX_AUDEN_ASRC_DUMMY_CTRL(5):
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case ABOX_AUDEN_ASRC_DUMMY_CTRL(6):
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case ABOX_AUDEN_ASRC_DUMMY_CTRL(7):
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case ABOX_AUDEN_ASRC_DUMMY_CTRL(8):
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case ABOX_AUDEN_ASRC_DUMMY_CTRL(9):
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case ABOX_AUDEN_ASRC_DUMMY_CTRL(10):
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case ABOX_AUDEN_ASRC_DUMMY_CTRL(11):
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case ABOX_AUDEN_SBANK_RDMA(0):
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case ABOX_AUDEN_SBANK_RDMA(1):
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case ABOX_AUDEN_SBANK_RDMA(2):
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case ABOX_AUDEN_SBANK_RDMA(3):
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case ABOX_AUDEN_SBANK_RDMA(4):
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case ABOX_AUDEN_SBANK_RDMA(5):
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case ABOX_AUDEN_SBANK_RDMA(6):
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case ABOX_AUDEN_SBANK_RDMA(7):
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case ABOX_AUDEN_SBANK_RDMA(8):
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case ABOX_AUDEN_SBANK_RDMA(9):
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case ABOX_AUDEN_SBANK_RDMA(10):
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case ABOX_AUDEN_SBANK_RDMA(11):
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case ABOX_AUDEN_SBANK_ASRC(0):
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case ABOX_AUDEN_SBANK_ASRC(1):
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case ABOX_AUDEN_SBANK_ASRC(2):
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case ABOX_AUDEN_SBANK_ASRC(3):
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case ABOX_AUDEN_SBANK_ASRC(4):
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case ABOX_AUDEN_SBANK_ASRC(5):
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case ABOX_AUDEN_SBANK_ASRC(6):
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case ABOX_AUDEN_SBANK_ASRC(7):
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case ABOX_AUDEN_SBANK_ASRC(8):
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case ABOX_AUDEN_SBANK_ASRC(9):
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case ABOX_AUDEN_SBANK_ASRC(10):
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case ABOX_AUDEN_SBANK_ASRC(11):
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case ABOX_AUDEN_SBANK_MIXP(0):
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case ABOX_AUDEN_SBANK_MIXP(1):
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case ABOX_AUDEN_SBANK_MIXP(2):
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case ABOX_AUDEN_MIXP_SYNC_CTRL(0):
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case ABOX_AUDEN_MIXP_SYNC_CTRL(1):
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case ABOX_AUDEN_MIXP_SYNC_CTRL(2):
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case ABOX_AUDEN_MIXP_SYNC_EN(0):
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case ABOX_AUDEN_MIXP_SYNC_EN(1):
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case ABOX_AUDEN_MIXP_SYNC_EN(2):
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case ABOX_AUDEN_MIXP_SYNC_RESTART(0):
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case ABOX_AUDEN_MIXP_SYNC_RESTART(1):
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case ABOX_AUDEN_MIXP_SYNC_RESTART(2):
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case ABOX_AUDEN_RDMA_WDMA_BUF_RATIO0:
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case ABOX_AUDEN_RDMA_WDMA_BUF_RATIO1:
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case ABOX_SOUNDWIRE_INFO:
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case ABOX_SOUNDWIRE_DEBUG:
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case ABOX_SW_PDI_CTRL0:
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case ABOX_SW_PDI_CTRL1:
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case ABOX_SW_PDI_CTRL2:
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case ABOX_SW_PDI_CTRL3:
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case ABOX_UAIF_CTRL0(0) ... ABOX_UAIF_STATUS(0):
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case ABOX_UAIF_CTRL0(1) ... ABOX_UAIF_STATUS(1):
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case ABOX_UAIF_CTRL0(2) ... ABOX_UAIF_STATUS(2):
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case ABOX_UAIF_CTRL0(3) ... ABOX_UAIF_STATUS(3):
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case ABOX_UAIF_CTRL0(4) ... ABOX_UAIF_STATUS(4):
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case ABOX_UAIF_CTRL0(5) ... ABOX_UAIF_STATUS(5):
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case ABOX_UAIF_CTRL0(6) ... ABOX_UAIF_STATUS(6):
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case ABOX_DSIF_CTRL:
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case ABOX_DSIF_STATUS:
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case ABOX_RDMA_CTRL(0) ... ABOX_RDMA_DITHER_SEED(0):
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case ABOX_RDMA_STATUS(0):
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case ABOX_RDMA_STATUS_ADD(0):
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case ABOX_RDMA_CTRL(1) ... ABOX_RDMA_DITHER_SEED(1):
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case ABOX_RDMA_STATUS(1):
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case ABOX_RDMA_STATUS_ADD(1):
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case ABOX_RDMA_CTRL(2) ... ABOX_RDMA_DITHER_SEED(2):
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case ABOX_RDMA_STATUS(2):
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case ABOX_RDMA_STATUS_ADD(2):
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case ABOX_RDMA_CTRL(3) ... ABOX_RDMA_DITHER_SEED(3):
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case ABOX_RDMA_STATUS(3):
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case ABOX_RDMA_STATUS_ADD(3):
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case ABOX_RDMA_CTRL(4) ... ABOX_RDMA_DITHER_SEED(4):
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case ABOX_RDMA_STATUS(4):
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case ABOX_RDMA_STATUS_ADD(4):
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case ABOX_RDMA_CTRL(5) ... ABOX_RDMA_DITHER_SEED(5):
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case ABOX_RDMA_STATUS(5):
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case ABOX_RDMA_STATUS_ADD(5):
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case ABOX_RDMA_CTRL(6) ... ABOX_RDMA_DITHER_SEED(6):
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case ABOX_RDMA_STATUS(6):
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case ABOX_RDMA_STATUS_ADD(6):
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case ABOX_RDMA_CTRL(7) ... ABOX_RDMA_DITHER_SEED(7):
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case ABOX_RDMA_STATUS(7):
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case ABOX_RDMA_STATUS_ADD(7):
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case ABOX_RDMA_CTRL(8) ... ABOX_RDMA_DITHER_SEED(8):
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case ABOX_RDMA_STATUS(8):
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case ABOX_RDMA_STATUS_ADD(8):
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case ABOX_RDMA_CTRL(9) ... ABOX_RDMA_DITHER_SEED(9):
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case ABOX_RDMA_STATUS(9):
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case ABOX_RDMA_STATUS_ADD(9):
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case ABOX_RDMA_CTRL(10) ... ABOX_RDMA_DITHER_SEED(10):
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case ABOX_RDMA_STATUS(10):
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case ABOX_RDMA_STATUS_ADD(10):
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case ABOX_RDMA_CTRL(11) ... ABOX_RDMA_DITHER_SEED(11):
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case ABOX_RDMA_STATUS(11):
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case ABOX_RDMA_STATUS_ADD(11):
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case ABOX_SPUS_ASRC_CTRL(0):
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case ABOX_SPUS_ASRC_IS_DEFAULT(0) ... ABOX_SPUS_ASRC_FILTER_CTRL(0):
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case ABOX_SPUS_ASRC_CTRL(1):
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case ABOX_SPUS_ASRC_IS_DEFAULT(1) ... ABOX_SPUS_ASRC_FILTER_CTRL(1):
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case ABOX_SPUS_ASRC_CTRL(2):
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case ABOX_SPUS_ASRC_IS_DEFAULT(2) ... ABOX_SPUS_ASRC_FILTER_CTRL(2):
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case ABOX_SPUS_ASRC_CTRL(3):
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case ABOX_SPUS_ASRC_IS_DEFAULT(3) ... ABOX_SPUS_ASRC_FILTER_CTRL(3):
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case ABOX_SPUS_ASRC_CTRL(4):
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case ABOX_SPUS_ASRC_IS_DEFAULT(4) ... ABOX_SPUS_ASRC_FILTER_CTRL(4):
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case ABOX_SPUS_ASRC_CTRL(5):
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case ABOX_SPUS_ASRC_IS_DEFAULT(5) ... ABOX_SPUS_ASRC_FILTER_CTRL(5):
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case ABOX_SPUS_ASRC_CTRL(6):
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case ABOX_SPUS_ASRC_IS_DEFAULT(6) ... ABOX_SPUS_ASRC_FILTER_CTRL(6):
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case ABOX_SPUS_ASRC_CTRL(7):
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case ABOX_SPUS_ASRC_IS_DEFAULT(7) ... ABOX_SPUS_ASRC_FILTER_CTRL(7):
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case ABOX_WDMA_CTRL(0) ... ABOX_WDMA_DITHER_SEED(0):
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case ABOX_WDMA_STATUS(0):
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case ABOX_WDMA_STATUS_ADD(0):
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case ABOX_WDMA_CTRL(1) ... ABOX_WDMA_DITHER_SEED(1):
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case ABOX_WDMA_STATUS(1):
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case ABOX_WDMA_STATUS_ADD(1):
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case ABOX_WDMA_CTRL(2) ... ABOX_WDMA_DITHER_SEED(2):
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case ABOX_WDMA_STATUS(2):
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case ABOX_WDMA_STATUS_ADD(2):
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case ABOX_WDMA_CTRL(3) ... ABOX_WDMA_DITHER_SEED(3):
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case ABOX_WDMA_STATUS(3):
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case ABOX_WDMA_STATUS_ADD(3):
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case ABOX_WDMA_CTRL(4) ... ABOX_WDMA_DITHER_SEED(4):
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case ABOX_WDMA_STATUS(4):
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case ABOX_WDMA_STATUS_ADD(4):
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case ABOX_WDMA_CTRL(5) ... ABOX_WDMA_DITHER_SEED(5):
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case ABOX_WDMA_STATUS(5):
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case ABOX_WDMA_STATUS_ADD(5):
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case ABOX_WDMA_CTRL(6) ... ABOX_WDMA_DITHER_SEED(6):
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case ABOX_WDMA_STATUS(6):
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case ABOX_WDMA_STATUS_ADD(6):
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case ABOX_WDMA_CTRL(7) ... ABOX_WDMA_DITHER_SEED(7):
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case ABOX_WDMA_STATUS(7):
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case ABOX_WDMA_STATUS_ADD(7):
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case ABOX_WDMA_DUAL_CTRL(0):
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case ABOX_WDMA_DUAL_BUF_STR(0):
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case ABOX_WDMA_DUAL_BUF_END(0):
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case ABOX_WDMA_DUAL_BUF_OFFSET(0):
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case ABOX_WDMA_DUAL_STR_POINT(0):
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case ABOX_WDMA_DUAL_STATUS(0):
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case ABOX_WDMA_DUAL_STATUS_ADD(0):
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case ABOX_WDMA_DUAL_CTRL(1):
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case ABOX_WDMA_DUAL_BUF_STR(1):
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case ABOX_WDMA_DUAL_BUF_END(1):
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case ABOX_WDMA_DUAL_BUF_OFFSET(1):
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case ABOX_WDMA_DUAL_STR_POINT(1):
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case ABOX_WDMA_DUAL_STATUS(1):
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case ABOX_WDMA_DUAL_STATUS_ADD(1):
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case ABOX_WDMA_DUAL_CTRL(2):
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case ABOX_WDMA_DUAL_BUF_STR(2):
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case ABOX_WDMA_DUAL_BUF_END(2):
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case ABOX_WDMA_DUAL_BUF_OFFSET(2):
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case ABOX_WDMA_DUAL_STR_POINT(2):
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case ABOX_WDMA_DUAL_STATUS(2):
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case ABOX_WDMA_DUAL_STATUS_ADD(2):
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case ABOX_WDMA_DUAL_CTRL(3):
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case ABOX_WDMA_DUAL_BUF_STR(3):
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case ABOX_WDMA_DUAL_BUF_END(3):
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case ABOX_WDMA_DUAL_BUF_OFFSET(3):
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case ABOX_WDMA_DUAL_STR_POINT(3):
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case ABOX_WDMA_DUAL_STATUS(3):
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case ABOX_WDMA_DUAL_STATUS_ADD(3):
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case ABOX_WDMA_DUAL_CTRL(4):
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case ABOX_WDMA_DUAL_BUF_STR(4):
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case ABOX_WDMA_DUAL_BUF_END(4):
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case ABOX_WDMA_DUAL_BUF_OFFSET(4):
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case ABOX_WDMA_DUAL_STR_POINT(4):
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case ABOX_WDMA_DUAL_STATUS(4):
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case ABOX_WDMA_DUAL_STATUS_ADD(4):
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case ABOX_WDMA_DUAL_CTRL(5):
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case ABOX_WDMA_DUAL_BUF_STR(5):
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case ABOX_WDMA_DUAL_BUF_END(5):
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case ABOX_WDMA_DUAL_BUF_OFFSET(5):
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case ABOX_WDMA_DUAL_STR_POINT(5):
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case ABOX_WDMA_DUAL_STATUS(5):
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case ABOX_WDMA_DUAL_STATUS_ADD(5):
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case ABOX_WDMA_DUAL_CTRL(6):
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case ABOX_WDMA_DUAL_BUF_STR(6):
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case ABOX_WDMA_DUAL_BUF_END(6):
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case ABOX_WDMA_DUAL_BUF_OFFSET(6):
|
|
case ABOX_WDMA_DUAL_STR_POINT(6):
|
|
case ABOX_WDMA_DUAL_STATUS(6):
|
|
case ABOX_WDMA_DUAL_STATUS_ADD(6):
|
|
case ABOX_WDMA_DUAL_CTRL(7):
|
|
case ABOX_WDMA_DUAL_BUF_STR(7):
|
|
case ABOX_WDMA_DUAL_BUF_END(7):
|
|
case ABOX_WDMA_DUAL_BUF_OFFSET(7):
|
|
case ABOX_WDMA_DUAL_STR_POINT(7):
|
|
case ABOX_WDMA_DUAL_STATUS(7):
|
|
case ABOX_WDMA_DUAL_STATUS_ADD(7):
|
|
case ABOX_WDMA_DEBUG_CTRL(0) ... ABOX_WDMA_DEBUG_SBANK_LIMIT(0):
|
|
case ABOX_WDMA_DEBUG_STATUS(0):
|
|
case ABOX_WDMA_DEBUG_STATUS_ADD(0):
|
|
case ABOX_WDMA_DEBUG_CTRL(1) ... ABOX_WDMA_DEBUG_SBANK_LIMIT(1):
|
|
case ABOX_WDMA_DEBUG_STATUS(1):
|
|
case ABOX_WDMA_DEBUG_STATUS_ADD(1):
|
|
case ABOX_WDMA_DEBUG_CTRL(2) ... ABOX_WDMA_DEBUG_SBANK_LIMIT(2):
|
|
case ABOX_WDMA_DEBUG_STATUS(2):
|
|
case ABOX_WDMA_DEBUG_STATUS_ADD(2):
|
|
case ABOX_WDMA_DEBUG_CTRL(3) ... ABOX_WDMA_DEBUG_SBANK_LIMIT(3):
|
|
case ABOX_WDMA_DEBUG_STATUS(3):
|
|
case ABOX_WDMA_DEBUG_STATUS_ADD(3):
|
|
case ABOX_WDMA_DEBUG_CTRL(4) ... ABOX_WDMA_DEBUG_SBANK_LIMIT(4):
|
|
case ABOX_WDMA_DEBUG_STATUS(4):
|
|
case ABOX_WDMA_DEBUG_STATUS_ADD(4):
|
|
case ABOX_WDMA_DEBUG_CTRL(5) ... ABOX_WDMA_DEBUG_SBANK_LIMIT(5):
|
|
case ABOX_WDMA_DEBUG_STATUS(5):
|
|
case ABOX_WDMA_DEBUG_STATUS_ADD(5):
|
|
case ABOX_SPUM_ASRC_CTRL(0):
|
|
case ABOX_SPUM_ASRC_IS_DEFAULT(0) ... ABOX_SPUM_ASRC_FILTER_CTRL(0):
|
|
case ABOX_SPUM_ASRC_CTRL(1):
|
|
case ABOX_SPUM_ASRC_IS_DEFAULT(1) ... ABOX_SPUM_ASRC_FILTER_CTRL(1):
|
|
case ABOX_SPUM_ASRC_CTRL(2):
|
|
case ABOX_SPUM_ASRC_IS_DEFAULT(2) ... ABOX_SPUM_ASRC_FILTER_CTRL(2):
|
|
case ABOX_SPUM_ASRC_CTRL(3):
|
|
case ABOX_SPUM_ASRC_IS_DEFAULT(3) ... ABOX_SPUM_ASRC_FILTER_CTRL(3):
|
|
case ABOX_CA32_CORE0_R(0) ... ABOX_CA32_CORE0_PC:
|
|
case ABOX_CA32_CORE1_R(0) ... ABOX_CA32_CORE1_PC:
|
|
case ABOX_CA32_STATUS:
|
|
case ABOX_CA32_CNT_CTRL:
|
|
case ABOX_CA32_CNT_CTRL1:
|
|
case ABOX_CA32_CNT_STATUS0:
|
|
case ABOX_CA32_CNT_STATUS1:
|
|
case ABOX_CA32_CNT_STATUS2:
|
|
case ABOX_CA32_CNT_STATUS3:
|
|
case ABOX_COEF_2EVEN0(0) ... ABOX_COEF_8ODD1(0):
|
|
case ABOX_COEF_2EVEN0(1) ... ABOX_COEF_8ODD1(1):
|
|
case ABOX_AUDEN_RDMA_CTRL(0) ... ABOX_AUDEN_RDMA_STATUS(0):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(0):
|
|
case ABOX_AUDEN_RDMA_CTRL(1) ... ABOX_AUDEN_RDMA_STATUS(1):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(1):
|
|
case ABOX_AUDEN_RDMA_CTRL(2) ... ABOX_AUDEN_RDMA_STATUS(2):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(2):
|
|
case ABOX_AUDEN_RDMA_CTRL(3) ... ABOX_AUDEN_RDMA_STATUS(3):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(3):
|
|
case ABOX_AUDEN_RDMA_CTRL(4) ... ABOX_AUDEN_RDMA_STATUS(4):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(4):
|
|
case ABOX_AUDEN_RDMA_CTRL(5) ... ABOX_AUDEN_RDMA_STATUS(5):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(5):
|
|
case ABOX_AUDEN_RDMA_CTRL(6) ... ABOX_AUDEN_RDMA_STATUS(6):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(6):
|
|
case ABOX_AUDEN_RDMA_CTRL(7) ... ABOX_AUDEN_RDMA_STATUS(7):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(7):
|
|
case ABOX_AUDEN_RDMA_CTRL(8) ... ABOX_AUDEN_RDMA_STATUS(8):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(8):
|
|
case ABOX_AUDEN_RDMA_CTRL(9) ... ABOX_AUDEN_RDMA_STATUS(9):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(9):
|
|
case ABOX_AUDEN_RDMA_CTRL(10) ... ABOX_AUDEN_RDMA_STATUS(10):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(10):
|
|
case ABOX_AUDEN_RDMA_CTRL(11) ... ABOX_AUDEN_RDMA_STATUS(11):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(11):
|
|
case ABOX_AUDEN_ASRC_CTRL(0):
|
|
case ABOX_AUDEN_ASRC_IS_DEFAULT(0) ... ABOX_AUDEN_ASRC_FILTER_CTRL(0):
|
|
case ABOX_AUDEN_ASRC_CTRL(1):
|
|
case ABOX_AUDEN_ASRC_IS_DEFAULT(1) ... ABOX_AUDEN_ASRC_FILTER_CTRL(1):
|
|
case ABOX_AUDEN_ASRC_CTRL(2):
|
|
case ABOX_AUDEN_ASRC_IS_DEFAULT(2) ... ABOX_AUDEN_ASRC_FILTER_CTRL(2):
|
|
case ABOX_AUDEN_ASRC_CTRL(3):
|
|
case ABOX_AUDEN_ASRC_IS_DEFAULT(3) ... ABOX_AUDEN_ASRC_FILTER_CTRL(3):
|
|
case ABOX_AUDEN_ASRC_CTRL(4):
|
|
case ABOX_AUDEN_ASRC_IS_DEFAULT(4) ... ABOX_AUDEN_ASRC_FILTER_CTRL(4):
|
|
case ABOX_AUDEN_ASRC_CTRL(5):
|
|
case ABOX_AUDEN_ASRC_IS_DEFAULT(5) ... ABOX_AUDEN_ASRC_FILTER_CTRL(5):
|
|
case ABOX_AUDEN_ASRC_CTRL(6):
|
|
case ABOX_AUDEN_ASRC_IS_DEFAULT(6) ... ABOX_AUDEN_ASRC_FILTER_CTRL(6):
|
|
case ABOX_AUDEN_ASRC_CTRL(7):
|
|
case ABOX_AUDEN_ASRC_IS_DEFAULT(7) ... ABOX_AUDEN_ASRC_FILTER_CTRL(7):
|
|
case ABOX_AUDEN_ASRC_CTRL(8):
|
|
case ABOX_AUDEN_ASRC_IS_DEFAULT(8) ... ABOX_AUDEN_ASRC_FILTER_CTRL(8):
|
|
case ABOX_AUDEN_ASRC_CTRL(9):
|
|
case ABOX_AUDEN_ASRC_IS_DEFAULT(9) ... ABOX_AUDEN_ASRC_FILTER_CTRL(9):
|
|
case ABOX_AUDEN_ASRC_CTRL(10):
|
|
case ABOX_AUDEN_ASRC_IS_DEFAULT(10) ... ABOX_AUDEN_ASRC_FILTER_CTRL(10):
|
|
case ABOX_AUDEN_ASRC_CTRL(11):
|
|
case ABOX_AUDEN_ASRC_IS_DEFAULT(11) ... ABOX_AUDEN_ASRC_FILTER_CTRL(11):
|
|
case ABOX_AUDEN_WDMA_CTRL(0) ... ABOX_AUDEN_WDMA_PRE_INTR_BUF_OFFSET(0):
|
|
case ABOX_AUDEN_WDMA_STATUS(0):
|
|
case ABOX_AUDEN_WDMA_DONE_STATUS(0):
|
|
case ABOX_AUDEN_WDMA_STATUS_ADD(0):
|
|
case ABOX_AUDEN_WDMA_CTRL(1) ... ABOX_AUDEN_WDMA_PRE_INTR_BUF_OFFSET(1):
|
|
case ABOX_AUDEN_WDMA_STATUS(1):
|
|
case ABOX_AUDEN_WDMA_DONE_STATUS(1):
|
|
case ABOX_AUDEN_WDMA_STATUS_ADD(1):
|
|
case ABOX_AUDEN_WDMA_CTRL(2) ... ABOX_AUDEN_WDMA_PRE_INTR_BUF_OFFSET(2):
|
|
case ABOX_AUDEN_WDMA_STATUS(2):
|
|
case ABOX_AUDEN_WDMA_DONE_STATUS(2):
|
|
case ABOX_AUDEN_WDMA_STATUS_ADD(2):
|
|
case ABOX_AUDEN_WDMA_CTRL(3) ... ABOX_AUDEN_WDMA_PRE_INTR_BUF_OFFSET(3):
|
|
case ABOX_AUDEN_WDMA_STATUS(3):
|
|
case ABOX_AUDEN_WDMA_DONE_STATUS(3):
|
|
case ABOX_AUDEN_WDMA_STATUS_ADD(3):
|
|
case ABOX_AUDEN_WDMA_CTRL(4) ... ABOX_AUDEN_WDMA_PRE_INTR_BUF_OFFSET(4):
|
|
case ABOX_AUDEN_WDMA_STATUS(4):
|
|
case ABOX_AUDEN_WDMA_DONE_STATUS(4):
|
|
case ABOX_AUDEN_WDMA_STATUS_ADD(4):
|
|
case ABOX_AUDEN_WDMA_CTRL(5) ... ABOX_AUDEN_WDMA_PRE_INTR_BUF_OFFSET(5):
|
|
case ABOX_AUDEN_WDMA_STATUS(5):
|
|
case ABOX_AUDEN_WDMA_DONE_STATUS(5):
|
|
case ABOX_AUDEN_WDMA_STATUS_ADD(5):
|
|
case ABOX_AUDEN_WDMA_CTRL(6) ... ABOX_AUDEN_WDMA_PRE_INTR_BUF_OFFSET(6):
|
|
case ABOX_AUDEN_WDMA_STATUS(6):
|
|
case ABOX_AUDEN_WDMA_DONE_STATUS(6):
|
|
case ABOX_AUDEN_WDMA_STATUS_ADD(6):
|
|
case ABOX_AUDEN_WDMA_CTRL(7) ... ABOX_AUDEN_WDMA_PRE_INTR_BUF_OFFSET(7):
|
|
case ABOX_AUDEN_WDMA_STATUS(7):
|
|
case ABOX_AUDEN_WDMA_DONE_STATUS(7):
|
|
case ABOX_AUDEN_WDMA_STATUS_ADD(7):
|
|
case ABOX_SIDETONE_CTRL ... ABOX_SIDETONE_HIGHSH_COEF4:
|
|
case ABOX_UDMA_CTRL:
|
|
case ABOX_UDMA_SBANK_RDMA(0) ... ABOX_UDMA_SBANK_RDMA(1):
|
|
case ABOX_UDMA_SBANK_SIFM(0) ... ABOX_UDMA_SBANK_SIFM(1):
|
|
case ABOX_UDMA_TRIGGER_CTRL_RD(0) ... ABOX_UDMA_TRIGGER_OFFSET_RD(0):
|
|
case ABOX_UDMA_TRIGGER_CTRL_RD(1) ... ABOX_UDMA_TRIGGER_OFFSET_RD(1):
|
|
case ABOX_UDMA_TRIGGER_CTRL_WR(0) ... ABOX_UDMA_TRIGGER_OFFSET_WR(0):
|
|
case ABOX_UDMA_TRIGGER_CTRL_WR(1) ... ABOX_UDMA_TRIGGER_OFFSET_WR(1):
|
|
case ABOX_UDMA_RD_CTRL(0) ... ABOX_UDMA_RD_SBANK_LIMIT(0):
|
|
case ABOX_UDMA_RD_STATUS(0):
|
|
case ABOX_UDMA_RD_STATUS_ADD(0):
|
|
case ABOX_UDMA_RD_CTRL(1) ... ABOX_UDMA_RD_SBANK_LIMIT(1):
|
|
case ABOX_UDMA_RD_STATUS(1):
|
|
case ABOX_UDMA_RD_STATUS_ADD(1):
|
|
case ABOX_UDMA_WR_CTRL(0) ... ABOX_UDMA_WR_SBANK_LIMIT(0):
|
|
case ABOX_UDMA_WR_STATUS(0):
|
|
case ABOX_UDMA_WR_STATUS_ADD(0):
|
|
case ABOX_UDMA_WR_CTRL(1) ... ABOX_UDMA_WR_SBANK_LIMIT(1):
|
|
case ABOX_UDMA_WR_STATUS(1):
|
|
case ABOX_UDMA_WR_STATUS_ADD(1):
|
|
case ABOX_UDMA_WR_DUAL_CTRL(0):
|
|
case ABOX_UDMA_WR_DUAL_BUF_STR(0):
|
|
case ABOX_UDMA_WR_DUAL_BUF_END(0):
|
|
case ABOX_UDMA_WR_DUAL_BUF_OFFSET(0):
|
|
case ABOX_UDMA_WR_DUAL_STR_POINT(0):
|
|
case ABOX_UDMA_WR_DUAL_STATUS(0):
|
|
case ABOX_UDMA_WR_DUAL_STATUS_ADD(0):
|
|
case ABOX_UDMA_WR_DUAL_CTRL(1):
|
|
case ABOX_UDMA_WR_DUAL_BUF_STR(1):
|
|
case ABOX_UDMA_WR_DUAL_BUF_END(1):
|
|
case ABOX_UDMA_WR_DUAL_BUF_OFFSET(1):
|
|
case ABOX_UDMA_WR_DUAL_STR_POINT(1):
|
|
case ABOX_UDMA_WR_DUAL_STATUS(1):
|
|
case ABOX_UDMA_WR_DUAL_STATUS_ADD(1):
|
|
case ABOX_UDMA_WR_DEBUG_CTRL(0) ... ABOX_UDMA_WR_DEBUG_SBANK_LIMIT(0):
|
|
case ABOX_UDMA_WR_DEBUG_STATUS(0):
|
|
case ABOX_UDMA_WR_DEBUG_STATUS_ADD(0):
|
|
|
|
/* ATUNE */
|
|
case ATUNE_SPUS_DSGAIN_CTRL(0):
|
|
case ATUNE_SPUS_DSGAIN_VOL_CHANGE_FIN(0):
|
|
case ATUNE_SPUS_DSGAIN_VOL_CHANGE_FOUT(0):
|
|
case ATUNE_SPUS_DSGAIN_GAIN0(0):
|
|
case ATUNE_SPUS_DSGAIN_GAIN1(0):
|
|
case ATUNE_SPUS_DSGAIN_GAIN2(0):
|
|
case ATUNE_SPUS_DSGAIN_GAIN3(0):
|
|
case ATUNE_SPUS_DSGAIN_BIT_CTRL(0):
|
|
|
|
case ATUNE_SPUS_USGAIN_CTRL(0):
|
|
case ATUNE_SPUS_USGAIN_VOL_CHANGE_FIN(0):
|
|
case ATUNE_SPUS_USGAIN_VOL_CHANGE_FOUT(0):
|
|
case ATUNE_SPUS_USGAIN_GAIN0(0):
|
|
case ATUNE_SPUS_USGAIN_GAIN1(0):
|
|
case ATUNE_SPUS_USGAIN_GAIN2(0):
|
|
case ATUNE_SPUS_USGAIN_GAIN3(0):
|
|
|
|
case ATUNE_SPUS_BQF_CTRL(0):
|
|
|
|
case ATUNE_SPUS_BQF_CH0_HEADROOM(0):
|
|
case ATUNE_SPUS_BQF_CH0_POSTAMP(0):
|
|
case ATUNE_SPUS_BQF_CH0_HPF_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH0_HPF_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH0_HPF_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH0_HPF_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH0_HPF_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ0_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ0_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ0_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ0_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ0_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ1_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ1_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ1_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ1_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ1_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ2_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ2_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ2_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ2_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ2_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ3_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ3_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ3_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ3_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ3_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ4_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ4_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ4_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ4_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH0_EQ4_COEF4(0):
|
|
|
|
case ATUNE_SPUS_BQF_CH1_HEADROOM(0):
|
|
case ATUNE_SPUS_BQF_CH1_POSTAMP(0):
|
|
case ATUNE_SPUS_BQF_CH1_HPF_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH1_HPF_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH1_HPF_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH1_HPF_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH1_HPF_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ0_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ0_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ0_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ0_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ0_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ1_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ1_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ1_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ1_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ1_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ2_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ2_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ2_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ2_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ2_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ3_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ3_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ3_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ3_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ3_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ4_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ4_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ4_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ4_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH1_EQ4_COEF4(0):
|
|
|
|
case ATUNE_SPUS_BQF_CH2_HEADROOM(0):
|
|
case ATUNE_SPUS_BQF_CH2_POSTAMP(0):
|
|
case ATUNE_SPUS_BQF_CH2_HPF_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH2_HPF_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH2_HPF_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH2_HPF_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH2_HPF_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ0_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ0_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ0_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ0_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ0_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ1_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ1_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ1_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ1_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ1_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ2_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ2_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ2_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ2_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ2_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ3_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ3_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ3_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ3_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ3_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ4_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ4_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ4_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ4_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH2_EQ4_COEF4(0):
|
|
|
|
case ATUNE_SPUS_BQF_CH3_HEADROOM(0):
|
|
case ATUNE_SPUS_BQF_CH3_POSTAMP(0):
|
|
case ATUNE_SPUS_BQF_CH3_HPF_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH3_HPF_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH3_HPF_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH3_HPF_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH3_HPF_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ0_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ0_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ0_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ0_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ0_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ1_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ1_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ1_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ1_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ1_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ2_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ2_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ2_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ2_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ2_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ3_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ3_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ3_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ3_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ3_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ4_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ4_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ4_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ4_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH3_EQ4_COEF4(0):
|
|
|
|
case ATUNE_SPUS_BQF_CH4_HEADROOM(0):
|
|
case ATUNE_SPUS_BQF_CH4_POSTAMP(0):
|
|
case ATUNE_SPUS_BQF_CH4_HPF_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH4_HPF_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH4_HPF_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH4_HPF_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH4_HPF_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ0_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ0_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ0_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ0_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ0_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ1_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ1_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ1_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ1_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ1_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ2_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ2_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ2_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ2_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ2_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ3_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ3_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ3_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ3_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ3_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ4_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ4_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ4_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ4_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH4_EQ4_COEF4(0):
|
|
|
|
case ATUNE_SPUS_BQF_CH5_HEADROOM(0):
|
|
case ATUNE_SPUS_BQF_CH5_POSTAMP(0):
|
|
case ATUNE_SPUS_BQF_CH5_HPF_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH5_HPF_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH5_HPF_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH5_HPF_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH5_HPF_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ0_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ0_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ0_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ0_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ0_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ1_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ1_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ1_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ1_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ1_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ2_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ2_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ2_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ2_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ2_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ3_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ3_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ3_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ3_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ3_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ4_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ4_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ4_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ4_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH5_EQ4_COEF4(0):
|
|
|
|
case ATUNE_SPUS_BQF_CH6_HEADROOM(0):
|
|
case ATUNE_SPUS_BQF_CH6_POSTAMP(0):
|
|
case ATUNE_SPUS_BQF_CH6_HPF_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH6_HPF_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH6_HPF_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH6_HPF_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH6_HPF_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ0_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ0_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ0_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ0_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ0_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ1_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ1_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ1_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ1_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ1_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ2_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ2_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ2_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ2_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ2_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ3_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ3_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ3_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ3_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ3_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ4_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ4_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ4_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ4_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH6_EQ4_COEF4(0):
|
|
|
|
case ATUNE_SPUS_BQF_CH7_HEADROOM(0):
|
|
case ATUNE_SPUS_BQF_CH7_POSTAMP(0):
|
|
case ATUNE_SPUS_BQF_CH7_HPF_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH7_HPF_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH7_HPF_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH7_HPF_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH7_HPF_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ0_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ0_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ0_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ0_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ0_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ1_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ1_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ1_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ1_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ1_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ2_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ2_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ2_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ2_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ2_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ3_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ3_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ3_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ3_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ3_COEF4(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ4_COEF0(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ4_COEF1(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ4_COEF2(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ4_COEF3(0):
|
|
case ATUNE_SPUS_BQF_CH7_EQ4_COEF4(0):
|
|
|
|
case ATUNE_SPUS_DRC_CTRL(0):
|
|
case ATUNE_SPUS_DRC_COMP_LB0(0):
|
|
case ATUNE_SPUS_DRC_COMP_LB1(0):
|
|
case ATUNE_SPUS_DRC_COMP_LB2(0):
|
|
case ATUNE_SPUS_DRC_COMP_MB0(0):
|
|
case ATUNE_SPUS_DRC_COMP_MB1(0):
|
|
case ATUNE_SPUS_DRC_COMP_MB2(0):
|
|
case ATUNE_SPUS_DRC_COMP_HB0(0):
|
|
case ATUNE_SPUS_DRC_COMP_HB1(0):
|
|
case ATUNE_SPUS_DRC_COMP_HB2(0):
|
|
case ATUNE_SPUS_DRC_LMT_CTRL0(0):
|
|
case ATUNE_SPUS_DRC_LMT_CTRL1(0):
|
|
case ATUNE_SPUS_DRC_xPF0_COEF0(0):
|
|
case ATUNE_SPUS_DRC_xPF0_COEF1(0):
|
|
case ATUNE_SPUS_DRC_xPF0_COEF2(0):
|
|
case ATUNE_SPUS_DRC_xPF0_COEF3(0):
|
|
case ATUNE_SPUS_DRC_xPF1_COEF0(0):
|
|
case ATUNE_SPUS_DRC_xPF1_COEF1(0):
|
|
case ATUNE_SPUS_DRC_xPF1_COEF2(0):
|
|
case ATUNE_SPUS_DRC_xPF1_COEF3(0):
|
|
|
|
case ATUNE_SPUS_DSGAIN_CTRL(1):
|
|
case ATUNE_SPUS_DSGAIN_VOL_CHANGE_FIN(1):
|
|
case ATUNE_SPUS_DSGAIN_VOL_CHANGE_FOUT(1):
|
|
case ATUNE_SPUS_DSGAIN_GAIN0(1):
|
|
case ATUNE_SPUS_DSGAIN_GAIN1(1):
|
|
case ATUNE_SPUS_DSGAIN_GAIN2(1):
|
|
case ATUNE_SPUS_DSGAIN_GAIN3(1):
|
|
case ATUNE_SPUS_DSGAIN_BIT_CTRL(1):
|
|
|
|
case ATUNE_SPUS_USGAIN_CTRL(1):
|
|
case ATUNE_SPUS_USGAIN_VOL_CHANGE_FIN(1):
|
|
case ATUNE_SPUS_USGAIN_VOL_CHANGE_FOUT(1):
|
|
case ATUNE_SPUS_USGAIN_GAIN0(1):
|
|
case ATUNE_SPUS_USGAIN_GAIN1(1):
|
|
case ATUNE_SPUS_USGAIN_GAIN2(1):
|
|
case ATUNE_SPUS_USGAIN_GAIN3(1):
|
|
|
|
case ATUNE_SPUS_BQF_CTRL(1):
|
|
|
|
case ATUNE_SPUS_BQF_CH0_HEADROOM(1):
|
|
case ATUNE_SPUS_BQF_CH0_POSTAMP(1):
|
|
case ATUNE_SPUS_BQF_CH0_HPF_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH0_HPF_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH0_HPF_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH0_HPF_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH0_HPF_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ0_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ0_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ0_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ0_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ0_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ1_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ1_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ1_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ1_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ1_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ2_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ2_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ2_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ2_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ2_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ3_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ3_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ3_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ3_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ3_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ4_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ4_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ4_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ4_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH0_EQ4_COEF4(1):
|
|
|
|
case ATUNE_SPUS_BQF_CH1_HEADROOM(1):
|
|
case ATUNE_SPUS_BQF_CH1_POSTAMP(1):
|
|
case ATUNE_SPUS_BQF_CH1_HPF_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH1_HPF_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH1_HPF_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH1_HPF_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH1_HPF_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ0_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ0_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ0_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ0_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ0_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ1_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ1_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ1_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ1_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ1_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ2_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ2_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ2_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ2_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ2_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ3_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ3_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ3_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ3_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ3_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ4_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ4_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ4_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ4_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH1_EQ4_COEF4(1):
|
|
|
|
case ATUNE_SPUS_BQF_CH2_HEADROOM(1):
|
|
case ATUNE_SPUS_BQF_CH2_POSTAMP(1):
|
|
case ATUNE_SPUS_BQF_CH2_HPF_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH2_HPF_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH2_HPF_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH2_HPF_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH2_HPF_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ0_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ0_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ0_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ0_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ0_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ1_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ1_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ1_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ1_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ1_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ2_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ2_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ2_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ2_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ2_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ3_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ3_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ3_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ3_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ3_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ4_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ4_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ4_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ4_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH2_EQ4_COEF4(1):
|
|
|
|
case ATUNE_SPUS_BQF_CH3_HEADROOM(1):
|
|
case ATUNE_SPUS_BQF_CH3_POSTAMP(1):
|
|
case ATUNE_SPUS_BQF_CH3_HPF_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH3_HPF_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH3_HPF_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH3_HPF_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH3_HPF_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ0_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ0_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ0_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ0_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ0_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ1_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ1_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ1_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ1_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ1_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ2_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ2_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ2_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ2_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ2_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ3_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ3_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ3_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ3_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ3_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ4_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ4_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ4_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ4_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH3_EQ4_COEF4(1):
|
|
|
|
case ATUNE_SPUS_BQF_CH4_HEADROOM(1):
|
|
case ATUNE_SPUS_BQF_CH4_POSTAMP(1):
|
|
case ATUNE_SPUS_BQF_CH4_HPF_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH4_HPF_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH4_HPF_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH4_HPF_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH4_HPF_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ0_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ0_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ0_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ0_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ0_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ1_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ1_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ1_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ1_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ1_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ2_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ2_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ2_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ2_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ2_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ3_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ3_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ3_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ3_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ3_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ4_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ4_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ4_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ4_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH4_EQ4_COEF4(1):
|
|
|
|
case ATUNE_SPUS_BQF_CH5_HEADROOM(1):
|
|
case ATUNE_SPUS_BQF_CH5_POSTAMP(1):
|
|
case ATUNE_SPUS_BQF_CH5_HPF_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH5_HPF_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH5_HPF_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH5_HPF_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH5_HPF_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ0_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ0_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ0_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ0_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ0_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ1_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ1_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ1_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ1_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ1_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ2_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ2_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ2_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ2_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ2_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ3_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ3_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ3_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ3_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ3_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ4_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ4_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ4_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ4_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH5_EQ4_COEF4(1):
|
|
|
|
case ATUNE_SPUS_BQF_CH6_HEADROOM(1):
|
|
case ATUNE_SPUS_BQF_CH6_POSTAMP(1):
|
|
case ATUNE_SPUS_BQF_CH6_HPF_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH6_HPF_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH6_HPF_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH6_HPF_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH6_HPF_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ0_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ0_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ0_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ0_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ0_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ1_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ1_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ1_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ1_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ1_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ2_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ2_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ2_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ2_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ2_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ3_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ3_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ3_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ3_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ3_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ4_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ4_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ4_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ4_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH6_EQ4_COEF4(1):
|
|
|
|
case ATUNE_SPUS_BQF_CH7_HEADROOM(1):
|
|
case ATUNE_SPUS_BQF_CH7_POSTAMP(1):
|
|
case ATUNE_SPUS_BQF_CH7_HPF_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH7_HPF_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH7_HPF_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH7_HPF_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH7_HPF_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ0_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ0_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ0_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ0_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ0_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ1_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ1_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ1_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ1_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ1_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ2_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ2_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ2_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ2_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ2_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ3_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ3_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ3_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ3_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ3_COEF4(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ4_COEF0(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ4_COEF1(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ4_COEF2(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ4_COEF3(1):
|
|
case ATUNE_SPUS_BQF_CH7_EQ4_COEF4(1):
|
|
|
|
case ATUNE_SPUS_DRC_CTRL(1):
|
|
case ATUNE_SPUS_DRC_COMP_LB0(1):
|
|
case ATUNE_SPUS_DRC_COMP_LB1(1):
|
|
case ATUNE_SPUS_DRC_COMP_LB2(1):
|
|
case ATUNE_SPUS_DRC_COMP_MB0(1):
|
|
case ATUNE_SPUS_DRC_COMP_MB1(1):
|
|
case ATUNE_SPUS_DRC_COMP_MB2(1):
|
|
case ATUNE_SPUS_DRC_COMP_HB0(1):
|
|
case ATUNE_SPUS_DRC_COMP_HB1(1):
|
|
case ATUNE_SPUS_DRC_COMP_HB2(1):
|
|
case ATUNE_SPUS_DRC_LMT_CTRL0(1):
|
|
case ATUNE_SPUS_DRC_LMT_CTRL1(1):
|
|
case ATUNE_SPUS_DRC_xPF0_COEF0(1):
|
|
case ATUNE_SPUS_DRC_xPF0_COEF1(1):
|
|
case ATUNE_SPUS_DRC_xPF0_COEF2(1):
|
|
case ATUNE_SPUS_DRC_xPF0_COEF3(1):
|
|
case ATUNE_SPUS_DRC_xPF1_COEF0(1):
|
|
case ATUNE_SPUS_DRC_xPF1_COEF1(1):
|
|
case ATUNE_SPUS_DRC_xPF1_COEF2(1):
|
|
case ATUNE_SPUS_DRC_xPF1_COEF3(1):
|
|
|
|
case ATUNE_SPUM_DSGAIN_CTRL(0):
|
|
case ATUNE_SPUM_DSGAIN_VOL_CHANGE_FIN(0):
|
|
case ATUNE_SPUM_DSGAIN_VOL_CHANGE_FOUT(0):
|
|
case ATUNE_SPUM_DSGAIN_GAIN0(0):
|
|
case ATUNE_SPUM_DSGAIN_GAIN1(0):
|
|
case ATUNE_SPUM_DSGAIN_GAIN2(0):
|
|
case ATUNE_SPUM_DSGAIN_GAIN3(0):
|
|
case ATUNE_SPUM_DSGAIN_BIT_CTRL(0):
|
|
|
|
case ATUNE_SPUM_USGAIN_CTRL(0):
|
|
case ATUNE_SPUM_USGAIN_VOL_CHANGE_FIN(0):
|
|
case ATUNE_SPUM_USGAIN_VOL_CHANGE_FOUT(0):
|
|
case ATUNE_SPUM_USGAIN_GAIN0(0):
|
|
case ATUNE_SPUM_USGAIN_GAIN1(0):
|
|
case ATUNE_SPUM_USGAIN_GAIN2(0):
|
|
case ATUNE_SPUM_USGAIN_GAIN3(0):
|
|
|
|
case ATUNE_SPUM_BQF_CTRL(0):
|
|
|
|
case ATUNE_SPUM_BQF_CH0_HEADROOM(0):
|
|
case ATUNE_SPUM_BQF_CH0_POSTAMP(0):
|
|
case ATUNE_SPUM_BQF_CH0_HPF_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH0_HPF_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH0_HPF_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH0_HPF_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH0_HPF_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ0_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ0_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ0_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ0_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ0_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ1_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ1_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ1_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ1_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ1_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ2_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ2_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ2_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ2_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ2_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ3_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ3_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ3_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ3_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ3_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ4_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ4_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ4_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ4_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH0_EQ4_COEF4(0):
|
|
|
|
case ATUNE_SPUM_BQF_CH1_HEADROOM(0):
|
|
case ATUNE_SPUM_BQF_CH1_POSTAMP(0):
|
|
case ATUNE_SPUM_BQF_CH1_HPF_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH1_HPF_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH1_HPF_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH1_HPF_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH1_HPF_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ0_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ0_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ0_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ0_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ0_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ1_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ1_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ1_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ1_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ1_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ2_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ2_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ2_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ2_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ2_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ3_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ3_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ3_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ3_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ3_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ4_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ4_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ4_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ4_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH1_EQ4_COEF4(0):
|
|
|
|
case ATUNE_SPUM_BQF_CH2_HEADROOM(0):
|
|
case ATUNE_SPUM_BQF_CH2_POSTAMP(0):
|
|
case ATUNE_SPUM_BQF_CH2_HPF_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH2_HPF_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH2_HPF_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH2_HPF_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH2_HPF_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ0_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ0_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ0_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ0_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ0_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ1_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ1_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ1_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ1_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ1_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ2_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ2_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ2_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ2_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ2_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ3_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ3_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ3_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ3_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ3_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ4_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ4_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ4_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ4_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH2_EQ4_COEF4(0):
|
|
|
|
case ATUNE_SPUM_BQF_CH3_HEADROOM(0):
|
|
case ATUNE_SPUM_BQF_CH3_POSTAMP(0):
|
|
case ATUNE_SPUM_BQF_CH3_HPF_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH3_HPF_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH3_HPF_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH3_HPF_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH3_HPF_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ0_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ0_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ0_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ0_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ0_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ1_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ1_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ1_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ1_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ1_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ2_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ2_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ2_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ2_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ2_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ3_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ3_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ3_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ3_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ3_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ4_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ4_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ4_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ4_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH3_EQ4_COEF4(0):
|
|
|
|
case ATUNE_SPUM_BQF_CH4_HEADROOM(0):
|
|
case ATUNE_SPUM_BQF_CH4_POSTAMP(0):
|
|
case ATUNE_SPUM_BQF_CH4_HPF_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH4_HPF_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH4_HPF_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH4_HPF_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH4_HPF_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ0_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ0_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ0_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ0_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ0_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ1_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ1_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ1_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ1_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ1_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ2_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ2_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ2_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ2_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ2_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ3_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ3_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ3_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ3_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ3_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ4_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ4_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ4_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ4_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH4_EQ4_COEF4(0):
|
|
|
|
case ATUNE_SPUM_BQF_CH5_HEADROOM(0):
|
|
case ATUNE_SPUM_BQF_CH5_POSTAMP(0):
|
|
case ATUNE_SPUM_BQF_CH5_HPF_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH5_HPF_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH5_HPF_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH5_HPF_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH5_HPF_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ0_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ0_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ0_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ0_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ0_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ1_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ1_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ1_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ1_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ1_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ2_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ2_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ2_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ2_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ2_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ3_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ3_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ3_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ3_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ3_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ4_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ4_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ4_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ4_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH5_EQ4_COEF4(0):
|
|
|
|
case ATUNE_SPUM_BQF_CH6_HEADROOM(0):
|
|
case ATUNE_SPUM_BQF_CH6_POSTAMP(0):
|
|
case ATUNE_SPUM_BQF_CH6_HPF_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH6_HPF_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH6_HPF_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH6_HPF_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH6_HPF_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ0_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ0_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ0_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ0_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ0_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ1_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ1_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ1_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ1_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ1_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ2_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ2_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ2_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ2_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ2_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ3_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ3_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ3_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ3_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ3_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ4_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ4_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ4_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ4_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH6_EQ4_COEF4(0):
|
|
|
|
case ATUNE_SPUM_BQF_CH7_HEADROOM(0):
|
|
case ATUNE_SPUM_BQF_CH7_POSTAMP(0):
|
|
case ATUNE_SPUM_BQF_CH7_HPF_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH7_HPF_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH7_HPF_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH7_HPF_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH7_HPF_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ0_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ0_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ0_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ0_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ0_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ1_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ1_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ1_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ1_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ1_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ2_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ2_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ2_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ2_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ2_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ3_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ3_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ3_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ3_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ3_COEF4(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ4_COEF0(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ4_COEF1(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ4_COEF2(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ4_COEF3(0):
|
|
case ATUNE_SPUM_BQF_CH7_EQ4_COEF4(0):
|
|
|
|
case ATUNE_SPUM_DRC_CTRL(0):
|
|
case ATUNE_SPUM_DRC_COMP_LB0(0):
|
|
case ATUNE_SPUM_DRC_COMP_LB1(0):
|
|
case ATUNE_SPUM_DRC_COMP_LB2(0):
|
|
case ATUNE_SPUM_DRC_COMP_MB0(0):
|
|
case ATUNE_SPUM_DRC_COMP_MB1(0):
|
|
case ATUNE_SPUM_DRC_COMP_MB2(0):
|
|
case ATUNE_SPUM_DRC_COMP_HB0(0):
|
|
case ATUNE_SPUM_DRC_COMP_HB1(0):
|
|
case ATUNE_SPUM_DRC_COMP_HB2(0):
|
|
case ATUNE_SPUM_DRC_LMT_CTRL0(0):
|
|
case ATUNE_SPUM_DRC_LMT_CTRL1(0):
|
|
case ATUNE_SPUM_DRC_xPF0_COEF0(0):
|
|
case ATUNE_SPUM_DRC_xPF0_COEF1(0):
|
|
case ATUNE_SPUM_DRC_xPF0_COEF2(0):
|
|
case ATUNE_SPUM_DRC_xPF0_COEF3(0):
|
|
case ATUNE_SPUM_DRC_xPF1_COEF0(0):
|
|
case ATUNE_SPUM_DRC_xPF1_COEF1(0):
|
|
case ATUNE_SPUM_DRC_xPF1_COEF2(0):
|
|
case ATUNE_SPUM_DRC_xPF1_COEF3(0):
|
|
|
|
case ATUNE_SPUM_DSGAIN_CTRL(1):
|
|
case ATUNE_SPUM_DSGAIN_VOL_CHANGE_FIN(1):
|
|
case ATUNE_SPUM_DSGAIN_VOL_CHANGE_FOUT(1):
|
|
case ATUNE_SPUM_DSGAIN_GAIN0(1):
|
|
case ATUNE_SPUM_DSGAIN_GAIN1(1):
|
|
case ATUNE_SPUM_DSGAIN_GAIN2(1):
|
|
case ATUNE_SPUM_DSGAIN_GAIN3(1):
|
|
case ATUNE_SPUM_DSGAIN_BIT_CTRL(1):
|
|
|
|
case ATUNE_SPUM_USGAIN_CTRL(1):
|
|
case ATUNE_SPUM_USGAIN_VOL_CHANGE_FIN(1):
|
|
case ATUNE_SPUM_USGAIN_VOL_CHANGE_FOUT(1):
|
|
case ATUNE_SPUM_USGAIN_GAIN0(1):
|
|
case ATUNE_SPUM_USGAIN_GAIN1(1):
|
|
case ATUNE_SPUM_USGAIN_GAIN2(1):
|
|
case ATUNE_SPUM_USGAIN_GAIN3(1):
|
|
|
|
case ATUNE_SPUM_BQF_CTRL(1):
|
|
|
|
case ATUNE_SPUM_BQF_CH0_HEADROOM(1):
|
|
case ATUNE_SPUM_BQF_CH0_POSTAMP(1):
|
|
case ATUNE_SPUM_BQF_CH0_HPF_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH0_HPF_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH0_HPF_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH0_HPF_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH0_HPF_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ0_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ0_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ0_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ0_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ0_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ1_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ1_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ1_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ1_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ1_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ2_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ2_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ2_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ2_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ2_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ3_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ3_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ3_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ3_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ3_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ4_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ4_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ4_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ4_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH0_EQ4_COEF4(1):
|
|
|
|
case ATUNE_SPUM_BQF_CH1_HEADROOM(1):
|
|
case ATUNE_SPUM_BQF_CH1_POSTAMP(1):
|
|
case ATUNE_SPUM_BQF_CH1_HPF_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH1_HPF_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH1_HPF_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH1_HPF_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH1_HPF_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ0_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ0_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ0_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ0_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ0_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ1_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ1_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ1_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ1_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ1_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ2_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ2_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ2_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ2_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ2_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ3_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ3_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ3_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ3_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ3_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ4_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ4_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ4_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ4_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH1_EQ4_COEF4(1):
|
|
|
|
case ATUNE_SPUM_BQF_CH2_HEADROOM(1):
|
|
case ATUNE_SPUM_BQF_CH2_POSTAMP(1):
|
|
case ATUNE_SPUM_BQF_CH2_HPF_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH2_HPF_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH2_HPF_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH2_HPF_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH2_HPF_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ0_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ0_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ0_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ0_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ0_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ1_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ1_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ1_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ1_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ1_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ2_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ2_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ2_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ2_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ2_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ3_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ3_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ3_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ3_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ3_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ4_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ4_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ4_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ4_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH2_EQ4_COEF4(1):
|
|
|
|
case ATUNE_SPUM_BQF_CH3_HEADROOM(1):
|
|
case ATUNE_SPUM_BQF_CH3_POSTAMP(1):
|
|
case ATUNE_SPUM_BQF_CH3_HPF_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH3_HPF_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH3_HPF_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH3_HPF_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH3_HPF_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ0_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ0_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ0_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ0_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ0_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ1_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ1_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ1_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ1_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ1_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ2_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ2_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ2_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ2_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ2_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ3_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ3_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ3_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ3_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ3_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ4_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ4_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ4_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ4_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH3_EQ4_COEF4(1):
|
|
|
|
case ATUNE_SPUM_BQF_CH4_HEADROOM(1):
|
|
case ATUNE_SPUM_BQF_CH4_POSTAMP(1):
|
|
case ATUNE_SPUM_BQF_CH4_HPF_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH4_HPF_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH4_HPF_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH4_HPF_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH4_HPF_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ0_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ0_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ0_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ0_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ0_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ1_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ1_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ1_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ1_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ1_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ2_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ2_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ2_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ2_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ2_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ3_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ3_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ3_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ3_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ3_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ4_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ4_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ4_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ4_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH4_EQ4_COEF4(1):
|
|
|
|
case ATUNE_SPUM_BQF_CH5_HEADROOM(1):
|
|
case ATUNE_SPUM_BQF_CH5_POSTAMP(1):
|
|
case ATUNE_SPUM_BQF_CH5_HPF_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH5_HPF_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH5_HPF_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH5_HPF_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH5_HPF_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ0_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ0_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ0_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ0_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ0_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ1_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ1_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ1_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ1_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ1_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ2_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ2_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ2_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ2_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ2_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ3_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ3_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ3_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ3_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ3_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ4_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ4_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ4_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ4_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH5_EQ4_COEF4(1):
|
|
|
|
case ATUNE_SPUM_BQF_CH6_HEADROOM(1):
|
|
case ATUNE_SPUM_BQF_CH6_POSTAMP(1):
|
|
case ATUNE_SPUM_BQF_CH6_HPF_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH6_HPF_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH6_HPF_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH6_HPF_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH6_HPF_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ0_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ0_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ0_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ0_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ0_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ1_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ1_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ1_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ1_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ1_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ2_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ2_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ2_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ2_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ2_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ3_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ3_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ3_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ3_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ3_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ4_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ4_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ4_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ4_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH6_EQ4_COEF4(1):
|
|
|
|
case ATUNE_SPUM_BQF_CH7_HEADROOM(1):
|
|
case ATUNE_SPUM_BQF_CH7_POSTAMP(1):
|
|
case ATUNE_SPUM_BQF_CH7_HPF_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH7_HPF_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH7_HPF_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH7_HPF_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH7_HPF_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ0_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ0_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ0_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ0_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ0_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ1_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ1_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ1_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ1_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ1_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ2_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ2_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ2_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ2_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ2_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ3_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ3_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ3_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ3_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ3_COEF4(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ4_COEF0(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ4_COEF1(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ4_COEF2(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ4_COEF3(1):
|
|
case ATUNE_SPUM_BQF_CH7_EQ4_COEF4(1):
|
|
|
|
case ATUNE_SPUM_DRC_CTRL(1):
|
|
case ATUNE_SPUM_DRC_COMP_LB0(1):
|
|
case ATUNE_SPUM_DRC_COMP_LB1(1):
|
|
case ATUNE_SPUM_DRC_COMP_LB2(1):
|
|
case ATUNE_SPUM_DRC_COMP_MB0(1):
|
|
case ATUNE_SPUM_DRC_COMP_MB1(1):
|
|
case ATUNE_SPUM_DRC_COMP_MB2(1):
|
|
case ATUNE_SPUM_DRC_COMP_HB0(1):
|
|
case ATUNE_SPUM_DRC_COMP_HB1(1):
|
|
case ATUNE_SPUM_DRC_COMP_HB2(1):
|
|
case ATUNE_SPUM_DRC_LMT_CTRL0(1):
|
|
case ATUNE_SPUM_DRC_LMT_CTRL1(1):
|
|
case ATUNE_SPUM_DRC_xPF0_COEF0(1):
|
|
case ATUNE_SPUM_DRC_xPF0_COEF1(1):
|
|
case ATUNE_SPUM_DRC_xPF0_COEF2(1):
|
|
case ATUNE_SPUM_DRC_xPF0_COEF3(1):
|
|
case ATUNE_SPUM_DRC_xPF1_COEF0(1):
|
|
case ATUNE_SPUM_DRC_xPF1_COEF1(1):
|
|
case ATUNE_SPUM_DRC_xPF1_COEF2(1):
|
|
case ATUNE_SPUM_DRC_xPF1_COEF3(1):
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool readonly_reg(unsigned int reg)
|
|
{
|
|
switch (reg) {
|
|
case ABOX_IP_INDEX:
|
|
case ABOX_VERSION:
|
|
case ABOX_SYSPOWER_STATUS:
|
|
case ABOX_UAIF_STATUS(0):
|
|
case ABOX_UAIF_STATUS(1):
|
|
case ABOX_UAIF_STATUS(2):
|
|
case ABOX_UAIF_STATUS(3):
|
|
case ABOX_UAIF_STATUS(4):
|
|
case ABOX_UAIF_STATUS(5):
|
|
case ABOX_UAIF_STATUS(6):
|
|
case ABOX_DSIF_STATUS:
|
|
case ABOX_RDMA_STATUS(0):
|
|
case ABOX_RDMA_STATUS_ADD(0):
|
|
case ABOX_RDMA_STATUS(1):
|
|
case ABOX_RDMA_STATUS_ADD(1):
|
|
case ABOX_RDMA_STATUS(2):
|
|
case ABOX_RDMA_STATUS_ADD(2):
|
|
case ABOX_RDMA_STATUS(3):
|
|
case ABOX_RDMA_STATUS_ADD(3):
|
|
case ABOX_RDMA_STATUS(4):
|
|
case ABOX_RDMA_STATUS_ADD(4):
|
|
case ABOX_RDMA_STATUS(5):
|
|
case ABOX_RDMA_STATUS_ADD(5):
|
|
case ABOX_RDMA_STATUS(6):
|
|
case ABOX_RDMA_STATUS_ADD(6):
|
|
case ABOX_RDMA_STATUS(7):
|
|
case ABOX_RDMA_STATUS_ADD(7):
|
|
case ABOX_RDMA_STATUS(8):
|
|
case ABOX_RDMA_STATUS_ADD(8):
|
|
case ABOX_RDMA_STATUS(9):
|
|
case ABOX_RDMA_STATUS_ADD(9):
|
|
case ABOX_RDMA_STATUS(10):
|
|
case ABOX_RDMA_STATUS_ADD(10):
|
|
case ABOX_RDMA_STATUS(11):
|
|
case ABOX_RDMA_STATUS_ADD(11):
|
|
case ABOX_WDMA_STATUS(0):
|
|
case ABOX_WDMA_STATUS_ADD(0):
|
|
case ABOX_WDMA_STATUS(1):
|
|
case ABOX_WDMA_STATUS_ADD(1):
|
|
case ABOX_WDMA_STATUS(2):
|
|
case ABOX_WDMA_STATUS_ADD(2):
|
|
case ABOX_WDMA_STATUS(3):
|
|
case ABOX_WDMA_STATUS_ADD(3):
|
|
case ABOX_WDMA_STATUS(4):
|
|
case ABOX_WDMA_STATUS_ADD(4):
|
|
case ABOX_WDMA_STATUS(5):
|
|
case ABOX_WDMA_STATUS_ADD(5):
|
|
case ABOX_WDMA_STATUS(6):
|
|
case ABOX_WDMA_STATUS_ADD(6):
|
|
case ABOX_WDMA_STATUS(7):
|
|
case ABOX_WDMA_STATUS_ADD(7):
|
|
case ABOX_WDMA_DUAL_STATUS(0):
|
|
case ABOX_WDMA_DUAL_STATUS_ADD(0):
|
|
case ABOX_WDMA_DUAL_STATUS(1):
|
|
case ABOX_WDMA_DUAL_STATUS_ADD(1):
|
|
case ABOX_WDMA_DUAL_STATUS(2):
|
|
case ABOX_WDMA_DUAL_STATUS_ADD(2):
|
|
case ABOX_WDMA_DUAL_STATUS(3):
|
|
case ABOX_WDMA_DUAL_STATUS_ADD(3):
|
|
case ABOX_WDMA_DUAL_STATUS(4):
|
|
case ABOX_WDMA_DUAL_STATUS_ADD(4):
|
|
case ABOX_WDMA_DUAL_STATUS(5):
|
|
case ABOX_WDMA_DUAL_STATUS_ADD(5):
|
|
case ABOX_WDMA_DUAL_STATUS(6):
|
|
case ABOX_WDMA_DUAL_STATUS_ADD(6):
|
|
case ABOX_WDMA_DUAL_STATUS(7):
|
|
case ABOX_WDMA_DUAL_STATUS_ADD(7):
|
|
case ABOX_WDMA_DEBUG_STATUS(0):
|
|
case ABOX_WDMA_DEBUG_STATUS_ADD(0):
|
|
case ABOX_WDMA_DEBUG_STATUS(1):
|
|
case ABOX_WDMA_DEBUG_STATUS_ADD(1):
|
|
case ABOX_WDMA_DEBUG_STATUS(2):
|
|
case ABOX_WDMA_DEBUG_STATUS_ADD(2):
|
|
case ABOX_WDMA_DEBUG_STATUS(3):
|
|
case ABOX_WDMA_DEBUG_STATUS_ADD(3):
|
|
case ABOX_WDMA_DEBUG_STATUS(4):
|
|
case ABOX_WDMA_DEBUG_STATUS_ADD(4):
|
|
case ABOX_WDMA_DEBUG_STATUS(5):
|
|
case ABOX_WDMA_DEBUG_STATUS_ADD(5):
|
|
case ABOX_CA32_CORE0_R(0) ... ABOX_CA32_CORE0_PC:
|
|
case ABOX_CA32_CORE1_R(0) ... ABOX_CA32_CORE1_PC:
|
|
case ABOX_CA32_STATUS:
|
|
case ABOX_CA32_CNT_STATUS0:
|
|
case ABOX_CA32_CNT_STATUS1:
|
|
case ABOX_CA32_CNT_STATUS2:
|
|
case ABOX_CA32_CNT_STATUS3:
|
|
case ABOX_AUDEN_RDMA_STATUS(0):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(0):
|
|
case ABOX_AUDEN_RDMA_STATUS(1):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(1):
|
|
case ABOX_AUDEN_RDMA_STATUS(2):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(2):
|
|
case ABOX_AUDEN_RDMA_STATUS(3):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(3):
|
|
case ABOX_AUDEN_RDMA_STATUS(4):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(4):
|
|
case ABOX_AUDEN_RDMA_STATUS(5):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(5):
|
|
case ABOX_AUDEN_RDMA_STATUS(6):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(6):
|
|
case ABOX_AUDEN_RDMA_STATUS(7):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(7):
|
|
case ABOX_AUDEN_RDMA_STATUS(8):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(8):
|
|
case ABOX_AUDEN_RDMA_STATUS(9):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(9):
|
|
case ABOX_AUDEN_RDMA_STATUS(10):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(10):
|
|
case ABOX_AUDEN_RDMA_STATUS(11):
|
|
case ABOX_AUDEN_RDMA_STATUS_ADD(11):
|
|
case ABOX_AUDEN_WDMA_STATUS(0):
|
|
case ABOX_AUDEN_WDMA_DONE_STATUS(0):
|
|
case ABOX_AUDEN_WDMA_STATUS_ADD(0):
|
|
case ABOX_AUDEN_WDMA_STATUS(1):
|
|
case ABOX_AUDEN_WDMA_DONE_STATUS(1):
|
|
case ABOX_AUDEN_WDMA_STATUS_ADD(1):
|
|
case ABOX_AUDEN_WDMA_STATUS(2):
|
|
case ABOX_AUDEN_WDMA_DONE_STATUS(2):
|
|
case ABOX_AUDEN_WDMA_STATUS_ADD(2):
|
|
case ABOX_AUDEN_WDMA_STATUS(3):
|
|
case ABOX_AUDEN_WDMA_DONE_STATUS(3):
|
|
case ABOX_AUDEN_WDMA_STATUS_ADD(3):
|
|
case ABOX_AUDEN_WDMA_STATUS(4):
|
|
case ABOX_AUDEN_WDMA_DONE_STATUS(4):
|
|
case ABOX_AUDEN_WDMA_STATUS_ADD(4):
|
|
case ABOX_AUDEN_WDMA_STATUS(5):
|
|
case ABOX_AUDEN_WDMA_DONE_STATUS(5):
|
|
case ABOX_AUDEN_WDMA_STATUS_ADD(5):
|
|
case ABOX_AUDEN_WDMA_STATUS(6):
|
|
case ABOX_AUDEN_WDMA_DONE_STATUS(6):
|
|
case ABOX_AUDEN_WDMA_STATUS_ADD(6):
|
|
case ABOX_AUDEN_WDMA_STATUS(7):
|
|
case ABOX_AUDEN_WDMA_DONE_STATUS(7):
|
|
case ABOX_AUDEN_WDMA_STATUS_ADD(7):
|
|
case ABOX_UDMA_RD_STATUS(0):
|
|
case ABOX_UDMA_RD_STATUS_ADD(0):
|
|
case ABOX_UDMA_RD_STATUS(1):
|
|
case ABOX_UDMA_RD_STATUS_ADD(1):
|
|
case ABOX_UDMA_WR_STATUS(0):
|
|
case ABOX_UDMA_WR_STATUS_ADD(0):
|
|
case ABOX_UDMA_WR_STATUS(1):
|
|
case ABOX_UDMA_WR_STATUS_ADD(1):
|
|
case ABOX_UDMA_WR_DUAL_STATUS(0):
|
|
case ABOX_UDMA_WR_DUAL_STATUS_ADD(0):
|
|
case ABOX_UDMA_WR_DUAL_STATUS(1):
|
|
case ABOX_UDMA_WR_DUAL_STATUS_ADD(1):
|
|
case ABOX_UDMA_WR_DEBUG_STATUS(0):
|
|
case ABOX_UDMA_WR_DEBUG_STATUS_ADD(0):
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool writeonly_reg(unsigned int reg)
|
|
{
|
|
switch (reg) {
|
|
case ABOX_SPUS_CTRL_FLUSH:
|
|
case ABOX_SPUM_CTRL_FLUSH:
|
|
case ABOX_AUDEN_MIXP_CTRL(0):
|
|
case ABOX_AUDEN_MIXP_CTRL(1):
|
|
case ABOX_AUDEN_MIXP_CTRL(2):
|
|
case ABOX_AUDEN_MIXP_SYNC_RESTART(0):
|
|
case ABOX_AUDEN_MIXP_SYNC_RESTART(1):
|
|
case ABOX_AUDEN_MIXP_SYNC_RESTART(2):
|
|
case ABOX_RDMA_BUF_RESTART(0):
|
|
case ABOX_RDMA_BUF_RESTART(1):
|
|
case ABOX_RDMA_BUF_RESTART(2):
|
|
case ABOX_RDMA_BUF_RESTART(3):
|
|
case ABOX_RDMA_BUF_RESTART(4):
|
|
case ABOX_RDMA_BUF_RESTART(5):
|
|
case ABOX_RDMA_BUF_RESTART(6):
|
|
case ABOX_RDMA_BUF_RESTART(7):
|
|
case ABOX_RDMA_BUF_RESTART(8):
|
|
case ABOX_RDMA_BUF_RESTART(9):
|
|
case ABOX_RDMA_BUF_RESTART(10):
|
|
case ABOX_RDMA_BUF_RESTART(11):
|
|
case ABOX_WDMA_BUF_RESTART(0):
|
|
case ABOX_WDMA_BUF_RESTART(1):
|
|
case ABOX_WDMA_BUF_RESTART(2):
|
|
case ABOX_WDMA_BUF_RESTART(3):
|
|
case ABOX_WDMA_BUF_RESTART(4):
|
|
case ABOX_WDMA_BUF_RESTART(5):
|
|
case ABOX_WDMA_BUF_RESTART(6):
|
|
case ABOX_WDMA_BUF_RESTART(7):
|
|
case ABOX_WDMA_DEBUG_BUF_RESTART(0):
|
|
case ABOX_WDMA_DEBUG_BUF_RESTART(1):
|
|
case ABOX_WDMA_DEBUG_BUF_RESTART(2):
|
|
case ABOX_WDMA_DEBUG_BUF_RESTART(3):
|
|
case ABOX_WDMA_DEBUG_BUF_RESTART(4):
|
|
case ABOX_WDMA_DEBUG_BUF_RESTART(5):
|
|
case ABOX_CA32_CNT_CTRL1:
|
|
case ABOX_AUDEN_RDMA_BUF_RESTART(0):
|
|
case ABOX_AUDEN_RDMA_BUF_RESTART(1):
|
|
case ABOX_AUDEN_RDMA_BUF_RESTART(2):
|
|
case ABOX_AUDEN_RDMA_BUF_RESTART(3):
|
|
case ABOX_AUDEN_RDMA_BUF_RESTART(4):
|
|
case ABOX_AUDEN_RDMA_BUF_RESTART(5):
|
|
case ABOX_AUDEN_RDMA_BUF_RESTART(6):
|
|
case ABOX_AUDEN_RDMA_BUF_RESTART(7):
|
|
case ABOX_AUDEN_RDMA_BUF_RESTART(8):
|
|
case ABOX_AUDEN_RDMA_BUF_RESTART(9):
|
|
case ABOX_AUDEN_RDMA_BUF_RESTART(10):
|
|
case ABOX_AUDEN_RDMA_BUF_RESTART(11):
|
|
case ABOX_AUDEN_WDMA_BUF_RESTART(0):
|
|
case ABOX_AUDEN_WDMA_BUF_RESTART(1):
|
|
case ABOX_AUDEN_WDMA_BUF_RESTART(2):
|
|
case ABOX_AUDEN_WDMA_BUF_RESTART(3):
|
|
case ABOX_AUDEN_WDMA_BUF_RESTART(4):
|
|
case ABOX_AUDEN_WDMA_BUF_RESTART(5):
|
|
case ABOX_AUDEN_WDMA_BUF_RESTART(6):
|
|
case ABOX_AUDEN_WDMA_BUF_RESTART(7):
|
|
case ABOX_UDMA_CTRL:
|
|
case ABOX_UDMA_RD_BUF_RESTART(0):
|
|
case ABOX_UDMA_RD_BUF_RESTART(1):
|
|
case ABOX_UDMA_WR_BUF_RESTART(0):
|
|
case ABOX_UDMA_WR_BUF_RESTART(1):
|
|
case ABOX_UDMA_WR_DEBUG_BUF_RESTART(0):
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool shared_reg(unsigned int reg)
|
|
{
|
|
switch (reg) {
|
|
case ABOX_RDMA_CTRL(0):
|
|
case ABOX_RDMA_CTRL(1):
|
|
case ABOX_RDMA_CTRL(2):
|
|
case ABOX_RDMA_CTRL(3):
|
|
case ABOX_RDMA_CTRL(4):
|
|
case ABOX_RDMA_CTRL(5):
|
|
case ABOX_RDMA_CTRL(6):
|
|
case ABOX_RDMA_CTRL(7):
|
|
case ABOX_RDMA_CTRL(8):
|
|
case ABOX_RDMA_CTRL(9):
|
|
case ABOX_RDMA_CTRL(10):
|
|
case ABOX_RDMA_CTRL(11):
|
|
case ABOX_WDMA_CTRL(0):
|
|
case ABOX_WDMA_CTRL(1):
|
|
case ABOX_WDMA_CTRL(2):
|
|
case ABOX_WDMA_CTRL(3):
|
|
case ABOX_WDMA_CTRL(4):
|
|
case ABOX_WDMA_CTRL(5):
|
|
case ABOX_WDMA_CTRL(6):
|
|
case ABOX_WDMA_CTRL(7):
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static const struct reg_sequence reg_patch[] = {
|
|
{ABOX_REMAP_MASK, 0xffe00000},
|
|
{ABOX_DYN_CLOCK_OFF, 0x6},
|
|
{ABOX_DYN_CLOCK_OFF1, 0x10000000},
|
|
{ABOX_DYN_CLOCK_OFF2, 0x0},
|
|
|
|
/* 0x0000 */
|
|
{ABOX_SPUS_SBANK_RDMA(0), (SZ_512 << 16) | (0 * SZ_512)},
|
|
{ABOX_SPUS_SBANK_RDMA(1), (SZ_512 << 16) | (1 * SZ_512)},
|
|
{ABOX_SPUS_SBANK_RDMA(2), (SZ_512 << 16) | (2 * SZ_512)},
|
|
{ABOX_SPUS_SBANK_RDMA(3), (SZ_512 << 16) | (3 * SZ_512)},
|
|
{ABOX_SPUS_SBANK_RDMA(4), (SZ_512 << 16) | (4 * SZ_512)},
|
|
{ABOX_SPUS_SBANK_RDMA(5), (SZ_512 << 16) | (5 * SZ_512)},
|
|
{ABOX_SPUS_SBANK_RDMA(6), (SZ_512 << 16) | (6 * SZ_512)},
|
|
{ABOX_SPUS_SBANK_RDMA(7), (SZ_512 << 16) | (7 * SZ_512)},
|
|
{ABOX_SPUS_SBANK_RDMA(8), (SZ_512 << 16) | (8 * SZ_512)},
|
|
{ABOX_SPUS_SBANK_RDMA(9), (SZ_512 << 16) | (9 * SZ_512)},
|
|
{ABOX_SPUS_SBANK_RDMA(10), (SZ_512 << 16) | (10 * SZ_512)},
|
|
{ABOX_SPUS_SBANK_RDMA(11), (SZ_512 << 16) | (11 * SZ_512)},
|
|
/* 0x1800 */
|
|
{ABOX_SPUS_SBANK_ASRC(0), (0x340 << 16) | (0x1800 + 0x000)},
|
|
{ABOX_SPUS_SBANK_ASRC(1), (0x220 << 16) | (0x1800 + 0x340)},
|
|
{ABOX_SPUS_SBANK_ASRC(2), (0x220 << 16) | (0x1800 + 0x560)},
|
|
{ABOX_SPUS_SBANK_ASRC(3), (0x190 << 16) | (0x1800 + 0x780)},
|
|
/* 0x2200 */
|
|
{ABOX_SPUS_SBANK_ASRC(4), (0x340 << 16) | (0x2200 + 0x000)},
|
|
{ABOX_SPUS_SBANK_ASRC(5), (0x220 << 16) | (0x2200 + 0x340)},
|
|
{ABOX_SPUS_SBANK_ASRC(6), (0x220 << 16) | (0x2200 + 0x560)},
|
|
{ABOX_SPUS_SBANK_ASRC(7), (0x190 << 16) | (0x2200 + 0x780)},
|
|
/* 0x2c00 */
|
|
{ABOX_SPUS_SBANK_MIXP, (SZ_128 << 16) | (0x2c00 + 0x000)},
|
|
{ABOX_SPUS_SBANK_SIDETONE, (SZ_128 << 16) | (0x2c00 + 0x080)},
|
|
{ABOX_SPUS_SBANK_STMIX, (SZ_128 << 16) | (0x2c00 + 0x100)},
|
|
/* 0x2e00 */
|
|
{ABOX_SPUS_SBANK_USG(0), (SZ_128 << 16) | (0x2e00 + 0x000)},
|
|
{ABOX_SPUS_SBANK_USG(1), (SZ_128 << 16) | (0x2e00 + 0x080)},
|
|
{ABOX_SPUS_SBANK_BQF(0), (SZ_128 << 16) | (0x2e00 + 0x100)},
|
|
{ABOX_SPUS_SBANK_BQF(1), (SZ_128 << 16) | (0x2e00 + 0x180)},
|
|
{ABOX_SPUS_SBANK_DRC(0), (SZ_128 << 16) | (0x2e00 + 0x200)},
|
|
{ABOX_SPUS_SBANK_DRC(1), (SZ_128 << 16) | (0x2e00 + 0x280)},
|
|
{ABOX_SPUS_SBANK_DSG(0), (SZ_128 << 16) | (0x2e00 + 0x300)},
|
|
{ABOX_SPUS_SBANK_DSG(1), (SZ_128 << 16) | (0x2e00 + 0x380)},
|
|
/* LIMIT: 0x3300 */
|
|
|
|
/* 0x0000 */
|
|
{ABOX_SPUM_SBANK_NSRC(0), (SZ_512 << 16) | (0 * SZ_512)},
|
|
{ABOX_SPUM_SBANK_NSRC(1), (SZ_512 << 16) | (1 * SZ_512)},
|
|
{ABOX_SPUM_SBANK_NSRC(2), (SZ_512 << 16) | (2 * SZ_512)},
|
|
{ABOX_SPUM_SBANK_NSRC(3), (SZ_512 << 16) | (3 * SZ_512)},
|
|
{ABOX_SPUM_SBANK_NSRC(4), (SZ_512 << 16) | (4 * SZ_512)},
|
|
{ABOX_SPUM_SBANK_NSRC(5), (SZ_512 << 16) | (5 * SZ_512)},
|
|
{ABOX_SPUM_SBANK_NSRC(6), (SZ_512 << 16) | (6 * SZ_512)},
|
|
{ABOX_SPUM_SBANK_NSRC(7), (SZ_512 << 16) | (7 * SZ_512)},
|
|
/* 0x1000 */
|
|
{ABOX_SPUM_SBANK_ASRC(0), (0x2c0 << 16) | (0x1000 + 0x000)},
|
|
{ABOX_SPUM_SBANK_ASRC(1), (0x220 << 16) | (0x1000 + 0x2c0)},
|
|
{ABOX_SPUM_SBANK_ASRC(2), (0x220 << 16) | (0x1000 + 0x4e0)},
|
|
{ABOX_SPUM_SBANK_ASRC(3), (0x190 << 16) | (0x1000 + 0x700)},
|
|
/* 0x1900 */
|
|
{ABOX_SPUM_SBANK_USG(0), (SZ_128 << 16) | (0x1900 + 0x000)},
|
|
{ABOX_SPUM_SBANK_USG(1), (SZ_128 << 16) | (0x1900 + 0x080)},
|
|
{ABOX_SPUM_SBANK_BQF(0), (SZ_128 << 16) | (0x1900 + 0x100)},
|
|
{ABOX_SPUM_SBANK_BQF(1), (SZ_128 << 16) | (0x1900 + 0x180)},
|
|
{ABOX_SPUM_SBANK_DRC(0), (SZ_128 << 16) | (0x1900 + 0x200)},
|
|
{ABOX_SPUM_SBANK_DRC(1), (SZ_128 << 16) | (0x1900 + 0x280)},
|
|
{ABOX_SPUM_SBANK_DSG(0), (SZ_128 << 16) | (0x1900 + 0x300)},
|
|
{ABOX_SPUM_SBANK_DSG(1), (SZ_128 << 16) | (0x1900 + 0x380)},
|
|
/* LIMIT: 0x1d00 */
|
|
|
|
/* Set default volume to 1.0 */
|
|
{ABOX_RDMA_VOL_FACTOR(0), 0x1 << 23},
|
|
{ABOX_RDMA_VOL_FACTOR(1), 0x1 << 23},
|
|
{ABOX_RDMA_VOL_FACTOR(2), 0x1 << 23},
|
|
{ABOX_RDMA_VOL_FACTOR(3), 0x1 << 23},
|
|
{ABOX_RDMA_VOL_FACTOR(4), 0x1 << 23},
|
|
{ABOX_RDMA_VOL_FACTOR(5), 0x1 << 23},
|
|
{ABOX_RDMA_VOL_FACTOR(6), 0x1 << 23},
|
|
{ABOX_RDMA_VOL_FACTOR(7), 0x1 << 23},
|
|
{ABOX_RDMA_VOL_FACTOR(8), 0x1 << 23},
|
|
{ABOX_RDMA_VOL_FACTOR(9), 0x1 << 23},
|
|
{ABOX_RDMA_VOL_FACTOR(10), 0x1 << 23},
|
|
{ABOX_RDMA_VOL_FACTOR(11), 0x1 << 23},
|
|
|
|
{ABOX_WDMA_VOL_FACTOR(0), 0x1 << 23},
|
|
{ABOX_WDMA_VOL_FACTOR(1), 0x1 << 23},
|
|
{ABOX_WDMA_VOL_FACTOR(2), 0x1 << 23},
|
|
{ABOX_WDMA_VOL_FACTOR(3), 0x1 << 23},
|
|
{ABOX_WDMA_VOL_FACTOR(4), 0x1 << 23},
|
|
{ABOX_WDMA_VOL_FACTOR(5), 0x1 << 23},
|
|
{ABOX_WDMA_VOL_FACTOR(6), 0x1 << 23},
|
|
{ABOX_WDMA_VOL_FACTOR(7), 0x1 << 23},
|
|
|
|
{ABOX_WDMA_DEBUG_VOL_FACTOR(0), 0x1 << 23},
|
|
{ABOX_WDMA_DEBUG_VOL_FACTOR(1), 0x1 << 23},
|
|
{ABOX_WDMA_DEBUG_VOL_FACTOR(2), 0x1 << 23},
|
|
{ABOX_WDMA_DEBUG_VOL_FACTOR(3), 0x1 << 23},
|
|
{ABOX_WDMA_DEBUG_VOL_FACTOR(4), 0x1 << 23},
|
|
{ABOX_WDMA_DEBUG_VOL_FACTOR(5), 0x1 << 23},
|
|
|
|
/* Set default RDMA DST_BIT_WIDTH to 16bit */
|
|
{ABOX_RDMA_BIT_CTRL(0x0), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
{ABOX_RDMA_BIT_CTRL(0x1), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
{ABOX_RDMA_BIT_CTRL(0x2), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
{ABOX_RDMA_BIT_CTRL(0x3), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
{ABOX_RDMA_BIT_CTRL(0x4), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
{ABOX_RDMA_BIT_CTRL(0x5), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
{ABOX_RDMA_BIT_CTRL(0x6), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
{ABOX_RDMA_BIT_CTRL(0x7), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
{ABOX_RDMA_BIT_CTRL(0x8), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
{ABOX_RDMA_BIT_CTRL(0x9), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
{ABOX_RDMA_BIT_CTRL(0xa), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
{ABOX_RDMA_BIT_CTRL(0xb), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
|
|
/* Set default WDMA DST_BIT_WIDTH to 16bit */
|
|
{ABOX_WDMA_BIT_CTRL(0x0), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
{ABOX_WDMA_BIT_CTRL(0x1), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
{ABOX_WDMA_BIT_CTRL(0x2), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
{ABOX_WDMA_BIT_CTRL(0x3), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
{ABOX_WDMA_BIT_CTRL(0x4), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
{ABOX_WDMA_BIT_CTRL(0x5), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
{ABOX_WDMA_BIT_CTRL(0x6), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
{ABOX_WDMA_BIT_CTRL(0x7), 0x1 << ABOX_DMA_DST_BIT_WIDTH_L},
|
|
|
|
/* Set default buffer configuration */
|
|
{ABOX_RDMA_BUF_STR(0x0), IOVA_RDMA_BUFFER(0x0)},
|
|
{ABOX_RDMA_BUF_END(0x0), IOVA_RDMA_BUFFER(0x0) + BUFFER_BYTES_MIN},
|
|
{ABOX_RDMA_BUF_OFFSET(0x0), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_RDMA_STR_POINT(0x0), IOVA_RDMA_BUFFER(0x0)},
|
|
|
|
{ABOX_RDMA_BUF_STR(0x1), IOVA_RDMA_BUFFER(0x1)},
|
|
{ABOX_RDMA_BUF_END(0x1), IOVA_RDMA_BUFFER(0x1) + BUFFER_BYTES_MIN},
|
|
{ABOX_RDMA_BUF_OFFSET(0x1), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_RDMA_STR_POINT(0x1), IOVA_RDMA_BUFFER(0x1)},
|
|
|
|
{ABOX_RDMA_BUF_STR(0x2), IOVA_RDMA_BUFFER(0x2)},
|
|
{ABOX_RDMA_BUF_END(0x2), IOVA_RDMA_BUFFER(0x2) + BUFFER_BYTES_MIN},
|
|
{ABOX_RDMA_BUF_OFFSET(0x2), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_RDMA_STR_POINT(0x2), IOVA_RDMA_BUFFER(0x2)},
|
|
|
|
{ABOX_RDMA_BUF_STR(0x3), IOVA_RDMA_BUFFER(0x3)},
|
|
{ABOX_RDMA_BUF_END(0x3), IOVA_RDMA_BUFFER(0x3) + BUFFER_BYTES_MIN},
|
|
{ABOX_RDMA_BUF_OFFSET(0x3), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_RDMA_STR_POINT(0x3), IOVA_RDMA_BUFFER(0x3)},
|
|
|
|
{ABOX_RDMA_BUF_STR(0x4), IOVA_RDMA_BUFFER(0x4)},
|
|
{ABOX_RDMA_BUF_END(0x4), IOVA_RDMA_BUFFER(0x4) + BUFFER_BYTES_MIN},
|
|
{ABOX_RDMA_BUF_OFFSET(0x4), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_RDMA_STR_POINT(0x4), IOVA_RDMA_BUFFER(0x4)},
|
|
|
|
{ABOX_RDMA_BUF_STR(0x5), IOVA_RDMA_BUFFER(0x5)},
|
|
{ABOX_RDMA_BUF_END(0x5), IOVA_RDMA_BUFFER(0x5) + BUFFER_BYTES_MIN},
|
|
{ABOX_RDMA_BUF_OFFSET(0x5), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_RDMA_STR_POINT(0x5), IOVA_RDMA_BUFFER(0x5)},
|
|
|
|
{ABOX_RDMA_BUF_STR(0x6), IOVA_RDMA_BUFFER(0x6)},
|
|
{ABOX_RDMA_BUF_END(0x6), IOVA_RDMA_BUFFER(0x6) + BUFFER_BYTES_MIN},
|
|
{ABOX_RDMA_BUF_OFFSET(0x6), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_RDMA_STR_POINT(0x6), IOVA_RDMA_BUFFER(0x6)},
|
|
|
|
{ABOX_RDMA_BUF_STR(0x7), IOVA_RDMA_BUFFER(0x7)},
|
|
{ABOX_RDMA_BUF_END(0x7), IOVA_RDMA_BUFFER(0x7) + BUFFER_BYTES_MIN},
|
|
{ABOX_RDMA_BUF_OFFSET(0x7), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_RDMA_STR_POINT(0x7), IOVA_RDMA_BUFFER(0x7)},
|
|
|
|
{ABOX_RDMA_BUF_STR(0x8), IOVA_RDMA_BUFFER(0x8)},
|
|
{ABOX_RDMA_BUF_END(0x8), IOVA_RDMA_BUFFER(0x8) + BUFFER_BYTES_MIN},
|
|
{ABOX_RDMA_BUF_OFFSET(0x8), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_RDMA_STR_POINT(0x8), IOVA_RDMA_BUFFER(0x8)},
|
|
|
|
{ABOX_RDMA_BUF_STR(0x9), IOVA_RDMA_BUFFER(0x9)},
|
|
{ABOX_RDMA_BUF_END(0x9), IOVA_RDMA_BUFFER(0x9) + BUFFER_BYTES_MIN},
|
|
{ABOX_RDMA_BUF_OFFSET(0x9), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_RDMA_STR_POINT(0x9), IOVA_RDMA_BUFFER(0x9)},
|
|
|
|
{ABOX_RDMA_BUF_STR(0xa), IOVA_RDMA_BUFFER(0xa)},
|
|
{ABOX_RDMA_BUF_END(0xa), IOVA_RDMA_BUFFER(0xa) + BUFFER_BYTES_MIN},
|
|
{ABOX_RDMA_BUF_OFFSET(0xa), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_RDMA_STR_POINT(0xa), IOVA_RDMA_BUFFER(0xa)},
|
|
|
|
{ABOX_RDMA_BUF_STR(0xb), IOVA_RDMA_BUFFER(0xb)},
|
|
{ABOX_RDMA_BUF_END(0xb), IOVA_RDMA_BUFFER(0xb) + BUFFER_BYTES_MIN},
|
|
{ABOX_RDMA_BUF_OFFSET(0xb), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_RDMA_STR_POINT(0xb), IOVA_RDMA_BUFFER(0xb)},
|
|
|
|
{ABOX_WDMA_BUF_STR(0x0), IOVA_WDMA_BUFFER(0x0)},
|
|
{ABOX_WDMA_BUF_END(0x0), IOVA_WDMA_BUFFER(0x0) + BUFFER_BYTES_MIN},
|
|
{ABOX_WDMA_BUF_OFFSET(0x0), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_WDMA_STR_POINT(0x0), IOVA_WDMA_BUFFER(0x0)},
|
|
|
|
{ABOX_WDMA_BUF_STR(0x1), IOVA_WDMA_BUFFER(0x1)},
|
|
{ABOX_WDMA_BUF_END(0x1), IOVA_WDMA_BUFFER(0x1) + BUFFER_BYTES_MIN},
|
|
{ABOX_WDMA_BUF_OFFSET(0x1), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_WDMA_STR_POINT(0x1), IOVA_WDMA_BUFFER(0x1)},
|
|
|
|
{ABOX_WDMA_BUF_STR(0x2), IOVA_WDMA_BUFFER(0x2)},
|
|
{ABOX_WDMA_BUF_END(0x2), IOVA_WDMA_BUFFER(0x2) + BUFFER_BYTES_MIN},
|
|
{ABOX_WDMA_BUF_OFFSET(0x2), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_WDMA_STR_POINT(0x2), IOVA_WDMA_BUFFER(0x2)},
|
|
|
|
{ABOX_WDMA_BUF_STR(0x3), IOVA_WDMA_BUFFER(0x3)},
|
|
{ABOX_WDMA_BUF_END(0x3), IOVA_WDMA_BUFFER(0x3) + BUFFER_BYTES_MIN},
|
|
{ABOX_WDMA_BUF_OFFSET(0x3), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_WDMA_STR_POINT(0x3), IOVA_WDMA_BUFFER(0x3)},
|
|
|
|
{ABOX_WDMA_BUF_STR(0x4), IOVA_WDMA_BUFFER(0x4)},
|
|
{ABOX_WDMA_BUF_END(0x4), IOVA_WDMA_BUFFER(0x4) + BUFFER_BYTES_MIN},
|
|
{ABOX_WDMA_BUF_OFFSET(0x4), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_WDMA_STR_POINT(0x4), IOVA_WDMA_BUFFER(0x4)},
|
|
|
|
{ABOX_WDMA_BUF_STR(0x5), IOVA_WDMA_BUFFER(0x5)},
|
|
{ABOX_WDMA_BUF_END(0x5), IOVA_WDMA_BUFFER(0x5) + BUFFER_BYTES_MIN},
|
|
{ABOX_WDMA_BUF_OFFSET(0x5), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_WDMA_STR_POINT(0x5), IOVA_WDMA_BUFFER(0x5)},
|
|
|
|
{ABOX_WDMA_BUF_STR(0x6), IOVA_WDMA_BUFFER(0x6)},
|
|
{ABOX_WDMA_BUF_END(0x6), IOVA_WDMA_BUFFER(0x6) + BUFFER_BYTES_MIN},
|
|
{ABOX_WDMA_BUF_OFFSET(0x6), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_WDMA_STR_POINT(0x6), IOVA_WDMA_BUFFER(0x6)},
|
|
|
|
{ABOX_WDMA_BUF_STR(0x7), IOVA_WDMA_BUFFER(0x7)},
|
|
{ABOX_WDMA_BUF_END(0x7), IOVA_WDMA_BUFFER(0x7) + BUFFER_BYTES_MIN},
|
|
{ABOX_WDMA_BUF_OFFSET(0x7), BUFFER_BYTES_MIN / 2},
|
|
{ABOX_WDMA_STR_POINT(0x7), IOVA_WDMA_BUFFER(0x7)},
|
|
|
|
/* UDMA */
|
|
/* 0x0000 */
|
|
{ABOX_UDMA_SBANK_RDMA(0), (SZ_256 << 16) | (0 * SZ_256)},
|
|
{ABOX_UDMA_SBANK_RDMA(1), (SZ_256 << 16) | (1 * SZ_256)},
|
|
{ABOX_UDMA_SBANK_SIFM(0), (SZ_256 << 16) | (2 * SZ_256)},
|
|
{ABOX_UDMA_SBANK_SIFM(1), (SZ_256 << 16) | (3 * SZ_256)},
|
|
|
|
{ABOX_UDMA_TRIGGER_CNT_RD(0), 0x8 << ABOX_UDMA_TRIGGER_CNT_VAL_L},
|
|
{ABOX_UDMA_TRIGGER_CNT_RD(1), 0x8 << ABOX_UDMA_TRIGGER_CNT_VAL_L},
|
|
{ABOX_UDMA_TRIGGER_CNT_WR(0), 0x8 << ABOX_UDMA_TRIGGER_CNT_VAL_L},
|
|
{ABOX_UDMA_TRIGGER_CNT_WR(1), 0x8 << ABOX_UDMA_TRIGGER_CNT_VAL_L},
|
|
|
|
{ABOX_UDMA_RD_VOL_FACTOR(0), 0x1 << 23},
|
|
{ABOX_UDMA_RD_VOL_FACTOR(1), 0x1 << 23},
|
|
{ABOX_UDMA_WR_VOL_FACTOR(0), 0x1 << 23},
|
|
{ABOX_UDMA_WR_VOL_FACTOR(1), 0x1 << 23},
|
|
|
|
{ABOX_UDMA_WR_DEBUG_CTRL(0), 0x4 << ABOX_DMA_BURST_LEN_L |
|
|
0x20 << ABOX_DMA_DEBUG_SRC_L},
|
|
{ABOX_UDMA_WR_DEBUG_VOL_FACTOR(0), 0x1 << 23},
|
|
|
|
/* ATUNE */
|
|
{ATUNE_SPUS_DSGAIN_CTRL(0), 0x1 << ATUNE_FUNC_L},
|
|
{ATUNE_SPUS_USGAIN_CTRL(0), 0x1 << ATUNE_FUNC_L},
|
|
{ATUNE_SPUS_DSGAIN_CTRL(1), 0x1 << ATUNE_FUNC_L},
|
|
{ATUNE_SPUS_USGAIN_CTRL(1), 0x1 << ATUNE_FUNC_L},
|
|
{ATUNE_SPUM_DSGAIN_CTRL(0), 0x1 << ATUNE_FUNC_L},
|
|
{ATUNE_SPUM_USGAIN_CTRL(0), 0x1 << ATUNE_FUNC_L},
|
|
{ATUNE_SPUM_DSGAIN_CTRL(1), 0x1 << ATUNE_FUNC_L},
|
|
{ATUNE_SPUM_USGAIN_CTRL(1), 0x1 << ATUNE_FUNC_L},
|
|
};
|
|
|
|
int apply_patch(struct regmap *regmap)
|
|
{
|
|
return regmap_multi_reg_write(regmap, reg_patch, ARRAY_SIZE(reg_patch));
|
|
}
|