325 lines
10 KiB
C
Executable file
325 lines
10 KiB
C
Executable file
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* (C) COPYRIGHT 2021 Samsung Electronics Inc. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU licence.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*/
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#include <linux/device.h>
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#include <linux/of.h>
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#include <linux/sysfs.h>
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#include <linux/slab.h>
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#include <gpex_utils.h>
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#include <gpexbe_devicetree.h>
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#define CPU_MAX INT_MAX
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static gpu_dt dt_info;
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static struct _dt_clock_item *clock_table;
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static struct _dt_clqos_item *clqos_table;
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static int gpexbe_devicetree_read_u32(const char *of_string, u32 *of_data)
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{
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int ret = 0;
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if (!of_string || !of_data) {
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GPU_LOG(MALI_EXYNOS_ERROR, "NULL: failed to get item from dt\n");
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return -EINVAL;
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}
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ret = of_property_read_u32(dt_info.dev->of_node, of_string, of_data);
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if (ret) {
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GPU_LOG(MALI_EXYNOS_ERROR,
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"%s: failed to get item from dt. Data will be set to 0.\n", of_string);
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*of_data = 0;
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}
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return ret;
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}
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/* TODO: document in the interface header. Return value same as of_property_read_string */
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static int gpexbe_devicetree_read_string(const char *of_string, const char **of_data)
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{
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int ret = 0;
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if (!of_string || !of_data) {
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GPU_LOG(MALI_EXYNOS_ERROR, "NULL: failed to get item from dt\n");
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return -EINVAL;
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}
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ret = of_property_read_string(dt_info.dev->of_node, of_string, of_data);
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if (ret) {
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GPU_LOG(MALI_EXYNOS_ERROR,
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"%s: failed to get item from dt. Data will be set to NULL.\n", of_string);
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*of_data = NULL;
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}
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return ret;
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}
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static int gpexbe_devicetree_read_u32_array(const char *of_string, int *of_data, int sz)
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{
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int ret = 0;
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if (!of_string || !of_data || sz < 0) {
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GPU_LOG(MALI_EXYNOS_ERROR, "NULL: failed to get item from dt. Invalid params\n");
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return -EINVAL;
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}
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ret = of_property_read_u32_array(dt_info.dev->of_node, of_string, of_data, sz);
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if (ret)
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GPU_LOG(MALI_EXYNOS_ERROR, "%s: failed to get item from dt (u32 array)\n",
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of_string);
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return ret;
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}
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static int read_interactive_info_array(void)
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{
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int interactive_info[3] = { 0, 0, 0 };
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gpexbe_devicetree_read_u32_array("interactive_info", interactive_info, 3);
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/* TODO: change default value to something more sensible */
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dt_info.interactive_info.highspeed_clock =
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interactive_info[0] == 0 ? 500 : (u32)interactive_info[0];
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dt_info.interactive_info.highspeed_load =
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interactive_info[1] == 0 ? 100 : (u32)interactive_info[1];
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dt_info.interactive_info.highspeed_delay =
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interactive_info[2] == 0 ? 0 : (u32)interactive_info[2];
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return 0;
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}
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unsigned int custom_clock[] = {1209000, 1105000, 1001000, 897000, 806000, 702000, 611000, 507000, 403000, 312000, 208000, 104000};
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unsigned int custom_min_threshold[] = {90, 87, 85, 82, 80, 79, 78, 70, 60, 50, 30, 0};
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unsigned int custom_max_threshold[] = {100, 96 ,95, 95, 95, 95, 95, 90, 80, 70, 60, 40};
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unsigned int custom_staycount[] = {5, 5, 5, 5, 5, 5, 5, 3, 3, 2, 2, 1};
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unsigned int custom_mem_freq[] = {2093000, 1794000, 1794000, 1794000, 1539000, 1352000, 1352000, 1014000, 1014000, 845000, 676000, 676000};
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unsigned int custom_lit[] = {1536000, 1440000, 1248000, 1056000, 1056000, 1056000, 1056000, 1056000, 0, 0, 0, 0};
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unsigned int custom_mid = 0;
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unsigned int custom_big = CPU_MAX;
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int custom_array_size = sizeof(custom_clock) / sizeof(custom_clock[0]);
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static int build_clk_table(void)
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{
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int array_size = custom_array_size;
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int i = 0;
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if (array_size <= 0) {
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return -EINVAL;
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}
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clock_table = kcalloc(array_size, sizeof(*clock_table), GFP_KERNEL);
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for (i = 0; i < array_size; i++) {
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clock_table[i].clock = custom_clock[i];
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clock_table[i].min_threshold = custom_min_threshold[i];
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clock_table[i].max_threshold = custom_max_threshold[i];
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clock_table[i].down_staycount = custom_staycount[i];
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clock_table[i].mem_freq = custom_mem_freq[i];
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clock_table[i].cpu_little_min_freq = custom_lit[i];
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if (dt_info.gpu_pmqos_cpu_cluster_num == 3) {
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clock_table[i].cpu_middle_min_freq = custom_mid;
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clock_table[i].cpu_big_max_freq = custom_big;
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GPU_LOG(MALI_EXYNOS_INFO,
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"up [%d] down [%d] staycnt [%d] mif [%d] lit [%d] mid [%d] big [%d]\n",
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clock_table[i].max_threshold, clock_table[i].min_threshold,
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clock_table[i].down_staycount, clock_table[i].mem_freq,
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clock_table[i].cpu_little_min_freq,
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clock_table[i].cpu_middle_min_freq,
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clock_table[i].cpu_big_max_freq);
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} else {
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// Assuming cpu cluster number is 2
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clock_table[i].cpu_big_max_freq = custom_big;
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GPU_LOG(MALI_EXYNOS_INFO,
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"up [%d] down [%d] staycnt [%d] mif [%d] lit [%d] big [%d]\n",
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clock_table[i].max_threshold, clock_table[i].min_threshold,
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clock_table[i].down_staycount, clock_table[i].mem_freq,
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clock_table[i].cpu_little_min_freq,
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clock_table[i].cpu_big_max_freq);
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}
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}
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return 0;
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}
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static int build_cl_pmqos_table(void)
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{
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int array_size = dt_info.gpu_cl_pmqos_table_size.row * dt_info.gpu_cl_pmqos_table_size.col;
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u32 *raw_table;
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int row = 0;
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if (array_size <= 0) {
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int num_rows = dt_info.gpu_dvfs_table_size.row;
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clqos_table = kcalloc(num_rows, sizeof(*clqos_table), GFP_KERNEL);
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for (row = 0; row < num_rows; row++)
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clqos_table[row].clock = clock_table[row].clock;
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dt_info.gpu_cl_pmqos_table_size.row = num_rows;
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dt_info.gpu_cl_pmqos_table_size.col = 1;
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return 0;
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}
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raw_table = kcalloc(array_size, sizeof(*raw_table), GFP_KERNEL);
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if (!raw_table)
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return -ENOMEM;
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gpexbe_devicetree_read_u32_array("gpu_cl_pmqos_table", raw_table, array_size);
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clqos_table =
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kcalloc(dt_info.gpu_cl_pmqos_table_size.row, sizeof(*clqos_table), GFP_KERNEL);
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for (row = 0; row < dt_info.gpu_cl_pmqos_table_size.row; row++) {
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int table_idx = row * dt_info.gpu_cl_pmqos_table_size.col;
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clqos_table[row].clock = raw_table[table_idx];
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clqos_table[row].mif_min = raw_table[table_idx + 1];
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clqos_table[row].little_min = raw_table[table_idx + 2];
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clqos_table[row].middle_min = raw_table[table_idx + 3];
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clqos_table[row].big_max = raw_table[table_idx + 4];
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}
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kfree(raw_table);
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return 0;
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}
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static void read_from_dt(void)
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{
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/* clock backend */
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gpexbe_devicetree_read_u32("g3d_cmu_cal_id", &dt_info.g3d_cmu_cal_id);
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/* PM backend */
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gpexbe_devicetree_read_string("g3d_genpd_name", &dt_info.g3d_genpd_name);
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/* CLOCK */
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dt_info.gpu_max_clock = custom_clock[0];
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dt_info.gpu_min_clock = custom_clock[custom_array_size - 1];
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gpexbe_devicetree_read_u32("gpu_pmqos_cpu_cluster_num", &dt_info.gpu_pmqos_cpu_cluster_num);
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dt_info.gpu_dvfs_table_size.col = 8; // 8 values for each freq
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dt_info.gpu_dvfs_table_size.row = custom_array_size;
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gpexbe_devicetree_read_u32_array("gpu_cl_pmqos_table_size",
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(int *)&dt_info.gpu_cl_pmqos_table_size, 2);
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/* DEBUG_BACKEND */
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gpexbe_devicetree_read_u32("gpu_ess_id_type", &dt_info.gpu_ess_id_type);
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/* LEGACY DVFS */
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gpexbe_devicetree_read_string("governor", &dt_info.governor);
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gpexbe_devicetree_read_u32("gpu_dvfs_bl_config_clock", &dt_info.gpu_dvfs_bl_config_clock);
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gpexbe_devicetree_read_u32("gpu_dvfs_polling_time", &dt_info.gpu_dvfs_polling_time);
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/* IFPO */
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gpexbe_devicetree_read_u32("gpu_inter_frame_pm", &dt_info.gpu_inter_frame_pm);
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/* PM BACKEND */
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gpexbe_devicetree_read_u32("gpu_pmu_status_reg_offset", &dt_info.gpu_pmu_status_reg_offset);
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gpexbe_devicetree_read_u32("gpu_pmu_status_local_pwr_mask",
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&dt_info.gpu_pmu_status_local_pwr_mask);
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/* PM */
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gpexbe_devicetree_read_u32("gpu_runtime_pm_delay_time", &dt_info.gpu_runtime_pm_delay_time);
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/* QOS */
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gpexbe_devicetree_read_u32("gpu_bts_support", &dt_info.gpu_bts_support);
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gpexbe_devicetree_read_u32("gpu_mo_min_clock", &dt_info.gpu_mo_min_clock);
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/* UTILS */
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gpexbe_devicetree_read_u32("gpu_debug_level", &dt_info.gpu_debug_level);
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/* HCM */
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gpexbe_devicetree_read_u32("gpu_heavy_compute_cpu0_min_clock;",
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&dt_info.gpu_heavy_compute_cpu0_min_clock);
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gpexbe_devicetree_read_u32("gpu_heavy_compute_vk_cpu0_min_clock;",
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&dt_info.gpu_heavy_compute_vk_cpu0_min_clock);
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/* TSG */
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gpexbe_devicetree_read_u32("gpu_weight_table_idx_0", &dt_info.gpu_weight_table_idx_0);
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gpexbe_devicetree_read_u32("gpu_weight_table_idx_1", &dt_info.gpu_weight_table_idx_1);
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}
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/******************
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* GETTERS
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* ***************/
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dt_clock_item *gpexbe_devicetree_get_clock_table(void)
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{
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return clock_table;
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}
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/********************************************
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* Helper Functions. (Must remain non static)
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* ******************************************/
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int gpexbe_devicetree_get_int_internal(size_t offset, const char *str)
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{
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//pr_warn("mali: %s %s %d\n", __func__, str, *(int*)((u8*)&dt_info + offset));
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//GPU_LOG(MALI_EXYNOS_INFO, "%s: %s\n", of_string, *of_data);
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return *(int *)((u8 *)&dt_info + offset);
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}
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char *gpexbe_devicetree_get_str_internal(size_t offset, const char *str)
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{
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//pr_warn("mali: %s %s %s\n", __func__, str, *(char**)((u8*)&dt_info + offset));
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//GPU_LOG(MALI_EXYNOS_INFO, "%s: %s\n", of_string, *of_data);
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return *(char **)((u8 *)&dt_info + offset);
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}
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gpu_dt *gpexbe_devicetree_get_gpu_dt(void)
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{
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return &dt_info;
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}
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/************************************************************************
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* INIT and TERM functions
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************************************************************************/
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int gpexbe_devicetree_init(struct device *dev)
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{
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dt_info.dev = dev;
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read_from_dt();
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build_clk_table();
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build_cl_pmqos_table();
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read_interactive_info_array();
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dt_info.gpu_dvfs_table = clock_table;
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dt_info.gpu_cl_pmqos_table = clqos_table;
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dt_info.initialized = 1;
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return 0;
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}
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void gpexbe_devicetree_term(void)
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{
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kfree(clock_table);
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kfree(clqos_table);
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clock_table = NULL;
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clqos_table = NULL;
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memset(&dt_info, 0, sizeof(gpu_dt));
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return;
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}
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