3b301c9f7e
commit b5d1b4b46f856da1473c7ba9a5cdfcb55c9b2478 upstream. The "msg_addr" variable is u64. However, the "aligned_offset" is an unsigned int. This means that when the code does: msg_addr &= ~aligned_offset; it will unintentionally zero out the high 32 bits. Use ALIGN_DOWN() to do the alignment instead. Fixes: 2217fffcd63f ("PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support") Link: https://lore.kernel.org/r/af59c7ad-ab93-40f7-ad4a-7ac0b14d37f5@moroto.mountain Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Niklas Cassel <cassel@kernel.org> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: <stable@vger.kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
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.. | ||
Kconfig | ||
Makefile | ||
pci-dra7xx.c | ||
pci-exynos.c | ||
pci-imx6.c | ||
pci-keystone.c | ||
pci-layerscape-ep.c | ||
pci-layerscape.c | ||
pci-meson.c | ||
pcie-al.c | ||
pcie-armada8k.c | ||
pcie-artpec6.c | ||
pcie-designware-ep.c | ||
pcie-designware-host.c | ||
pcie-designware-plat.c | ||
pcie-designware.c | ||
pcie-designware.h | ||
pcie-exynos-common.h | ||
pcie-exynos-dbg.c | ||
pcie-exynos-dbg.h | ||
pcie-exynos-rc.c | ||
pcie-exynos-rc.h | ||
pcie-exynosS5E9925-rc-cal.c | ||
pcie-exynosS5E9925-rc-cal_s5300.c | ||
pcie-hisi.c | ||
pcie-histb.c | ||
pcie-intel-gw.c | ||
pcie-kirin.c | ||
pcie-qcom.c | ||
pcie-spear13xx.c | ||
pcie-tegra194.c | ||
pcie-uniphier-ep.c | ||
pcie-uniphier.c |