19334 lines
446 KiB
Text
Executable file
19334 lines
446 KiB
Text
Executable file
/dts-v1/;
|
|
|
|
/ {
|
|
compatible = "samsung,armv8\0samsung,s5e9925";
|
|
dtb-hw_rev = <0x00>;
|
|
dtb-hw_rev_end = <0xff>;
|
|
interrupt-parent = <0x01>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
|
|
reserved-memory {
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
phandle = <0x19a>;
|
|
|
|
abox-dbg {
|
|
compatible = "exynos,abox_dbg";
|
|
size = <0x2900000>;
|
|
alloc-ranges = <0x00 0xc0000000 0x20000000>;
|
|
phandle = <0xa8>;
|
|
};
|
|
|
|
abox-slog {
|
|
compatible = "exynos,abox_slog";
|
|
size = <0x2800000>;
|
|
alloc-ranges = <0x00 0xc0000000 0x20000000>;
|
|
phandle = <0xa9>;
|
|
};
|
|
|
|
abox-rmem {
|
|
compatible = "exynos,abox_rmem";
|
|
reg = <0x08 0x8d800000 0x2800000>;
|
|
phandle = <0x9c>;
|
|
};
|
|
|
|
abox-rdma-compr {
|
|
compatible = "exynos,abox_rdma_compr_buffer";
|
|
size = <0x50000>;
|
|
alloc-ranges = <0x00 0xc0000000 0x20000000>;
|
|
phandle = <0x9f>;
|
|
};
|
|
|
|
dpado-rmem {
|
|
compatible = "exynos,dp_ado_rmem";
|
|
size = <0x200000>;
|
|
alloc-ranges = <0x00 0xc0000000 0x20000000>;
|
|
phandle = <0xbd>;
|
|
};
|
|
|
|
sgpu_rmem {
|
|
compatible = "exynos,sgpu_rmem";
|
|
reg = <0x00 0x8ff00000 0xe0000>;
|
|
phandle = <0x98>;
|
|
};
|
|
|
|
el3mon_reserve {
|
|
compatible = "exynos,el3mon";
|
|
reg = <0x00 0xbff80000 0x80000>;
|
|
};
|
|
|
|
ect_binary {
|
|
compatible = "exynos,ect_rmem";
|
|
reg = <0x00 0x90000000 0x3a000>;
|
|
phandle = <0x136>;
|
|
};
|
|
|
|
debug_snapshot {
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
phandle = <0x19b>;
|
|
|
|
header {
|
|
compatible = "header";
|
|
reg = <0x00 0xfd000000 0x10000>;
|
|
no-map;
|
|
phandle = <0xfb>;
|
|
};
|
|
|
|
log_kernel {
|
|
compatible = "log_kernel";
|
|
reg = <0x00 0xfd010000 0x200000>;
|
|
phandle = <0xfc>;
|
|
};
|
|
|
|
log_platform {
|
|
compatible = "log_platform";
|
|
reg = <0x00 0xfd210000 0x400000>;
|
|
phandle = <0x100>;
|
|
};
|
|
|
|
log_s2d {
|
|
compatible = "log_s2d";
|
|
reg = <0x00 0xfd610000 0x1500000>;
|
|
phandle = <0xfd>;
|
|
};
|
|
|
|
log_first {
|
|
compatible = "log_first";
|
|
reg = <0x00 0xfeb10000 0x200000>;
|
|
phandle = <0xfe>;
|
|
};
|
|
|
|
log_kevents {
|
|
compatible = "log_kevents";
|
|
reg = <0x00 0xfed10000 0x500000>;
|
|
phandle = <0x101>;
|
|
};
|
|
|
|
log_kevents_small {
|
|
compatible = "log_kevents";
|
|
reg = <0x00 0xfed10000 0xa6000>;
|
|
status = "no";
|
|
phandle = <0x103>;
|
|
};
|
|
|
|
log_arrdumpreset {
|
|
compatible = "log_arrdumpreset";
|
|
reg = <0x00 0xff210000 0xc30000>;
|
|
phandle = <0xff>;
|
|
};
|
|
};
|
|
|
|
log_itmon {
|
|
reg = <0x00 0xfffe0000 0x20000>;
|
|
no-map;
|
|
phandle = <0x105>;
|
|
};
|
|
|
|
debug_kinfo_reserved@effff000 {
|
|
reg = <0x00 0xfcfff000 0x1000>;
|
|
no-map;
|
|
phandle = <0x104>;
|
|
};
|
|
|
|
log_bcm {
|
|
compatible = "exynos,bcmdbg";
|
|
reg = <0x00 0xfbc00000 0x400000>;
|
|
phandle = <0x196>;
|
|
};
|
|
|
|
log_llc {
|
|
compatible = "exynos,llc";
|
|
reg = <0x00 0xfc000000 0x800000>;
|
|
phandle = <0x198>;
|
|
};
|
|
|
|
log_ppc {
|
|
compatible = "exynos,ppc";
|
|
reg = <0x00 0xfc800000 0x100000>;
|
|
phandle = <0x197>;
|
|
};
|
|
|
|
log_backtrace {
|
|
compatible = "log_backtrace";
|
|
alloc-ranges = <0x00 0x80000000 0x68000000>;
|
|
size = <0x2000>;
|
|
phandle = <0x102>;
|
|
};
|
|
|
|
memlog_region {
|
|
compatible = "shared-dma-pool";
|
|
no-map;
|
|
alloc-ranges = <0x00 0x80000000 0x68000000>;
|
|
size = <0xc00000>;
|
|
phandle = <0x192>;
|
|
};
|
|
|
|
s2mpu_table {
|
|
compatible = "exynos,s2mpu_table";
|
|
reg = <0x00 0xc1800000 0x600000>;
|
|
phandle = <0x137>;
|
|
};
|
|
|
|
seclog_mem {
|
|
compatible = "exynos,seclog";
|
|
reg = <0x00 0xc3000000 0x80000>;
|
|
phandle = <0x138>;
|
|
};
|
|
|
|
gnss_rmem {
|
|
compatible = "samsung,exynos-gnss";
|
|
reg = <0x08 0xa1600000 0x600000>;
|
|
phandle = <0x19c>;
|
|
};
|
|
|
|
teegris_rmem {
|
|
compatible = "exynos,teegris_rmem";
|
|
reg = <0x00 0xed310000 0x2000>;
|
|
phandle = <0x19d>;
|
|
};
|
|
|
|
cp_rmem {
|
|
compatible = "exynos,modem_if";
|
|
reg = <0x08 0x80000000 0xd800000>;
|
|
rmem_index = <0x00>;
|
|
phandle = <0x19e>;
|
|
};
|
|
|
|
cp_rmem1 {
|
|
compatible = "exynos,modem_if";
|
|
reg = <0x08 0x90000000 0x10000000>;
|
|
rmem_index = <0x01>;
|
|
phandle = <0x19f>;
|
|
};
|
|
|
|
mfc_fw_rmem {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x08 0xa2400000 0x800000>;
|
|
alignment = <0x00 0x10000>;
|
|
reusable;
|
|
phandle = <0x15d>;
|
|
};
|
|
|
|
dnc-fw-mem {
|
|
reg = <0x08 0xa1c00000 0x500000>;
|
|
phandle = <0x191>;
|
|
};
|
|
|
|
contexthub_rmem {
|
|
compatible = "samsung,exynos-contexthub";
|
|
size = <0x190000>;
|
|
alloc-ranges = <0x00 0xc0000000 0x40000000>;
|
|
phandle = <0x199>;
|
|
};
|
|
|
|
wifi_msi_rmem {
|
|
compatible = "exynos,pcie_rmem";
|
|
reg = <0x00 0xe7200000 0x1000>;
|
|
phandle = <0x1a0>;
|
|
};
|
|
|
|
sec_rdx_bootdev {
|
|
compatible = "exynos,sec_debug_rdx_bootdev";
|
|
no-ship;
|
|
reg = <0x08 0xb0000000 0xb600000>;
|
|
};
|
|
|
|
crypto {
|
|
compatible = "shared-dma-pool";
|
|
size = <0x1800000>;
|
|
alloc-ranges = <0x08 0xa0000000 0x60000000 0x09 0x00 0x80000000 0x09 0x80000000 0x80000000>;
|
|
alignment = <0x00 0x400000>;
|
|
reusable;
|
|
phandle = <0x0e>;
|
|
};
|
|
|
|
vstream {
|
|
compatible = "shared-dma-pool";
|
|
size = <0x7000000>;
|
|
alloc-ranges = <0x08 0xa0000000 0x60000000 0x09 0x00 0x80000000 0x09 0x80000000 0x80000000>;
|
|
alignment = <0x00 0x400000>;
|
|
reusable;
|
|
phandle = <0x0f>;
|
|
};
|
|
|
|
tui {
|
|
compatible = "shared-dma-pool";
|
|
size = <0x4800000>;
|
|
alloc-ranges = <0x00 0x40000000 0xb0000000>;
|
|
alignment = <0x00 0x400000>;
|
|
reusable;
|
|
phandle = <0x14>;
|
|
};
|
|
|
|
rbin {
|
|
size = "1 \0";
|
|
alloc-ranges = <0x09 0x80000000 0x80000000 0x09 0x00 0x80000000 0x08 0xa0000000 0x60000000>;
|
|
phandle = <0x16>;
|
|
};
|
|
|
|
secure_camera {
|
|
reg = <0x00 0x96000000 0x1ee0000>;
|
|
alignment = <0x00 0x10000>;
|
|
phandle = <0x13>;
|
|
};
|
|
|
|
vframe {
|
|
size = <0x32000000>;
|
|
alignment = <0x00 0x10000>;
|
|
phandle = <0x10>;
|
|
};
|
|
|
|
vscaler {
|
|
size = <0x6c00000>;
|
|
alignment = <0x00 0x10000>;
|
|
phandle = <0x11>;
|
|
};
|
|
|
|
gpu_buffer {
|
|
size = <0x4000000>;
|
|
alignment = <0x00 0x10000>;
|
|
phandle = <0x12>;
|
|
};
|
|
|
|
secure_dsp {
|
|
compatible = "shared-dma-pool";
|
|
size = <0x6c00000>;
|
|
alignment = <0x00 0x400000>;
|
|
reusable;
|
|
phandle = <0x15>;
|
|
};
|
|
};
|
|
|
|
memlog_bl_base {
|
|
samsung,bl-base = <0xfd000000>;
|
|
samsung,bl-offset = <0x290>;
|
|
phandle = <0x193>;
|
|
};
|
|
|
|
sysmmu@0x18D50000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x18d50000 0x9000>;
|
|
interrupts = <0x00 0x4d 0x04 0x00 0x4e 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x18d60000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x00>;
|
|
sysmmu,tlb_property = <0x01 0x00 0x300 0xf0003 0x02 0x00 0x300 0xf0004 0x03 0x00 0x300 0xf0005 0x04 0x00 0x200 0xf0007 0x05 0x00 0x200 0xf0008>;
|
|
port-name = "ABOX (CA32_0), ABOX (UDMA), ...";
|
|
power-domains = <0x02>;
|
|
phandle = <0x9b>;
|
|
};
|
|
|
|
sysmmu@0x17430000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x17430000 0x9000>;
|
|
interrupts = <0x00 0x57 0x04 0x00 0x58 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x17440000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x100 0xf0000 0x02 0x0a 0x100 0xf0008 0x08 0x00 0x100 0xf0001 0x03 0x0a 0x100 0xf0002 0x04 0x0a 0x100 0xf000a 0x05 0x00 0x200 0xf0003 0x06 0x00 0x200 0xf0004 0x07 0x00 0x200 0xf0005>;
|
|
port-name = "BYRP(M0), BYRP(M1), BYRP(M2)...";
|
|
power-domains = <0x03>;
|
|
phandle = <0x165>;
|
|
};
|
|
|
|
sysmmu@0x17530000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x17530000 0x9000>;
|
|
interrupts = <0x00 0x5b 0x04 0x00 0x5c 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x17540000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x07 0x00 0x100 0x70000 0x01 0x0a 0x200 0x70004 0x02 0x0a 0x100 0x70001 0x03 0x0a 0x200 0x70005 0x04 0x0a 0x200 0x70001 0x05 0x0a 0x200 0x70002 0x06 0x00 0x200 0x70003>;
|
|
port-name = "RGBP (M0), RGBP (M0), RGBP (...";
|
|
power-domains = <0x03>;
|
|
phandle = <0x16e>;
|
|
};
|
|
|
|
sysmmu@0x17570000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x17570000 0x9000>;
|
|
interrupts = <0x00 0x5f 0x04 0x00 0x60 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x17580000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x200 0x70000 0x02 0x0a 0x100 0x70001 0x03 0x0a 0x200 0x70001 0x04 0x0a 0x200 0x70005 0x05 0x0a 0x200 0x70002 0x06 0x00 0x200 0x70003>;
|
|
port-name = "RGBP (M1), RGBP (M1), RGBP (...";
|
|
power-domains = <0x03>;
|
|
phandle = <0x16f>;
|
|
};
|
|
|
|
sysmmu@0x17170000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x17170000 0x9000>;
|
|
interrupts = <0x00 0x121 0x04 0x00 0x122 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x17160000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x200 0xf0002 0x02 0x0a 0x200 0xf0004 0x03 0x0a 0x200 0xf0008 0x04 0x0a 0x200 0xf000c 0x05 0x0a 0x200 0xf0001 0x06 0x0a 0x200 0xf0005 0x07 0x0a 0x200 0xf0009 0x08 0x0a 0x200 0xf000d>;
|
|
port-name = "CSISX7_V1.0 (CSIS DMA0), CSI...";
|
|
power-domains = <0x04>;
|
|
phandle = <0x161>;
|
|
};
|
|
|
|
sysmmu@0x171A0000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x171a0000 0x9000>;
|
|
interrupts = <0x00 0x125 0x04 0x00 0x126 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x17190000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x200 0x1f0008 0x02 0x0a 0x200 0x1f0010 0x03 0x0a 0x200 0x1f0018 0x04 0x0a 0x200 0x1f0001 0x05 0x0a 0x200 0x1f0009 0x06 0x0a 0x200 0x1f0011 0x07 0x0a 0x200 0x1f0019 0x08 0x0a 0x200 0x1f0002 0x09 0x0a 0x200 0x1f000a 0x0a 0x0a 0x200 0x1f0012 0x0b 0x0a 0x200 0x1f001a>;
|
|
port-name = "CSISX7_V1.0 (CSIS DMA2), CSI...";
|
|
power-domains = <0x04>;
|
|
phandle = <0x162>;
|
|
};
|
|
|
|
sysmmu@0x171D0000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x171d0000 0x9000>;
|
|
interrupts = <0x00 0x129 0x04 0x00 0x12a 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x171c0000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x100 0x7f0000 0x02 0x0a 0x200 0x7f0020 0x03 0x0a 0x200 0x7f0040 0x04 0x0a 0x200 0x7f0060 0x05 0x00 0x200 0x70001 0x06 0x00 0x200 0x70002 0x07 0x00 0x200 0x70003>;
|
|
port-name = "PDP_TOP_(PDP_STAT_IMG0_AF0),...";
|
|
power-domains = <0x04>;
|
|
phandle = <0x163>;
|
|
};
|
|
|
|
sysmmu@0x18540000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x18540000 0x9000>;
|
|
interrupts = <0x00 0x13f 0x04 0x00 0x140 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x18550000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x200 0x3ff0080 0x02 0x0a 0x200 0x3ff0100 0x03 0x0a 0x200 0x3ff0180 0x04 0x0a 0x100 0x3ff0000 0x05 0x0a 0x200 0x3ff0001 0x06 0x0a 0x200 0x3ff0081 0x07 0x0a 0x200 0x3ff0101 0x08 0x0a 0x200 0x3ff0181 0x09 0x0a 0x100 0x3ff0001 0x0a 0x0a 0x200 0x3ff0002 0x0b 0x0a 0x200 0x3ff0082 0x0c 0x0a 0x200 0x3ff0102 0x0d 0x0a 0x200 0x3ff0182 0x0e 0x0a 0x100 0x3ff0002 0x0f 0x0a 0x200 0x3ff0003 0x10 0x0a 0x200 0x3ff0083 0x11 0x0a 0x200 0x3ff0103 0x12 0x0a 0x200 0x3ff0183 0x13 0x0a 0x100 0x3ff0003 0x14 0x0a 0x200 0x3ff0004 0x15 0x0a 0x200 0x3ff0084 0x16 0x0a 0x200 0x3ff0104 0x17 0x0a 0x200 0x3ff0184 0x3c 0x00 0x100 0x3ff0004 0x18 0x0a 0x200 0x3ff0005 0x19 0x0a 0x200 0x3ff0085 0x1a 0x0a 0x200 0x3ff0105 0x1b 0x0a 0x200 0x3ff0185 0x3d 0x00 0x100 0x3ff0005 0x1c 0x0a 0x200 0x3ff0006 0x1d 0x0a 0x200 0x3ff0086 0x1e 0x0a 0x200 0x3ff0106 0x1f 0x0a 0x200 0x3ff0186 0x3e 0x00 0x100 0x3ff0006 0x20 0x0a 0x200 0x3ff0007 0x21 0x0a 0x200 0x3ff0087 0x22 0x0a 0x200 0x3ff0107 0x23 0x0a 0x200 0x3ff0187 0x3f 0x00 0x100 0x3ff0007 0x24 0x0a 0x200 0x3ff0008 0x25 0x0a 0x200 0x3ff0028 0x26 0x0a 0x200 0x3ff0048 0x27 0x0a 0x200 0x3ff0088 0x28 0x0a 0x200 0x3ff00a8 0x29 0x0a 0x200 0x3ff00c8 0x2a 0x0a 0x200 0x3ff0108 0x2b 0x0a 0x200 0x3ff0128 0x2c 0x0a 0x200 0x3ff0148 0x2d 0x0a 0x200 0x3ff0188 0x2e 0x0a 0x200 0x3ff01a8 0x2f 0x0a 0x200 0x3ff01c8 0x30 0x0a 0x200 0x3ff0009 0x31 0x0a 0x200 0x3ff0029 0x32 0x0a 0x200 0x3ff0049 0x33 0x0a 0x200 0x3ff0089 0x34 0x0a 0x200 0x3ff00a9 0x35 0x0a 0x200 0x3ff00c9 0x36 0x0a 0x200 0x3ff0109 0x37 0x0a 0x200 0x3ff0129 0x38 0x0a 0x200 0x3ff0149 0x39 0x0a 0x200 0x3ff0189 0x3a 0x0a 0x200 0x3ff01a9 0x3b 0x0a 0x200 0x3ff01c9 0x40 0x00 0x200 0x3f000a 0x41 0x00 0x200 0x3f000b 0x42 0x00 0x200 0x3f000c>;
|
|
port-name = "CSTAT_RD0_RGBYHIST, CSTAT_RD...";
|
|
power-domains = <0x05>;
|
|
phandle = <0x164>;
|
|
};
|
|
|
|
sysmmu@0x16040000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x16040000 0x9000>;
|
|
interrupts = <0x00 0x15f 0x04 0x00 0x160 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x16050000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x00>;
|
|
sysmmu,tlb_property = <0x01 0x60 0x300 0x400000>;
|
|
port-name = "IP_SDMA (BUSD0)";
|
|
power-domains = <0x06>;
|
|
phandle = <0x188>;
|
|
};
|
|
|
|
sysmmu@0x16070000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x16070000 0x9000>;
|
|
interrupts = <0x00 0x163 0x04 0x00 0x164 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x16080000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x00>;
|
|
sysmmu,tlb_property = <0x01 0x60 0x300 0x400000>;
|
|
port-name = "IP_SDMA (BUSD0)";
|
|
power-domains = <0x06>;
|
|
phandle = <0x189>;
|
|
};
|
|
|
|
sysmmu@0x160A0000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x160a0000 0x9000>;
|
|
interrupts = <0x00 0x167 0x04 0x00 0x168 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x160b0000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x00>;
|
|
sysmmu,tlb_property = <0x01 0x60 0x300 0x400000>;
|
|
port-name = "IP_SDMA (BUSD0)";
|
|
power-domains = <0x06>;
|
|
phandle = <0x18a>;
|
|
};
|
|
|
|
sysmmu@0x160D0000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x160d0000 0x9000>;
|
|
interrupts = <0x00 0x16b 0x04 0x00 0x16c 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x160e0000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x00>;
|
|
sysmmu,tlb_property = <0x01 0x60 0x300 0x400000>;
|
|
port-name = "IP_SDMA (BUSD0)";
|
|
power-domains = <0x06>;
|
|
phandle = <0x18b>;
|
|
};
|
|
|
|
sysmmu@0x16100000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x16100000 0x9000>;
|
|
interrupts = <0x00 0x15b 0x04 0x00 0x15c 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x16110000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x00>;
|
|
sysmmu,tlb_property = <0x01 0x00 0x100 0xf0002 0x02 0x0a 0x100 0xf000a 0x03 0x0a 0x100 0xf0009 0x04 0x0a 0x100 0x70003 0x05 0x00 0x300 0x70000 0x06 0x00 0x200 0x70004>;
|
|
port-name = "IP_DNC (DRAM)";
|
|
power-domains = <0x06>;
|
|
phandle = <0x187>;
|
|
};
|
|
|
|
sysmmu@0x1AC40000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x1ac40000 0x9000>;
|
|
interrupts = <0x00 0x1b8 0x04 0x00 0x1b9 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x1ac60000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0xaa>;
|
|
sysmmu,tlb_property = <0x02 0x8a 0x100 0x1f0000 0x04 0x2a 0x100 0x1f0002 0x01 0xaa 0x100 0x1f0005 0x05 0x2a 0x100 0x1f0006 0x09 0x0a 0x100 0x1f0007 0x03 0x8a 0x100 0x1f0008 0x06 0x2a 0x100 0x1f000a 0x07 0x2a 0x100 0x1f000c 0x08 0x2a 0x100 0x1f000d 0x0a 0x0a 0x100 0x1f0010 0x0b 0x0a 0x100 0x1f0014 0x0c 0x0a 0x200 0x1f0000 0x0d 0x0a 0x200 0x1f0001>;
|
|
port-name = "DPU_DMA_TOP";
|
|
power-domains = <0x07>;
|
|
phandle = <0xd3>;
|
|
};
|
|
|
|
sysmmu@0x1AC50000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x1ac50000 0x9000>;
|
|
interrupts = <0x00 0x1c0 0x04 0x00 0x1c1 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x1ac70000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x8a>;
|
|
sysmmu,tlb_property = <0x02 0x2a 0x100 0x1f0002 0x03 0x2a 0x100 0x1f0004 0x04 0x2a 0x100 0x1f0005 0x08 0x0a 0x100 0x1f0006 0x09 0x0a 0x100 0x1f0007 0x01 0x8a 0x100 0x1f0008 0x05 0x2a 0x100 0x1f000a 0x06 0x2a 0x100 0x1f000c 0x07 0x2a 0x100 0x1f000d 0x0a 0x0a 0x100 0x1f0010 0x0b 0x00 0x200 0x1f0010 0x0c 0x00 0x200 0x1f0014>;
|
|
port-name = "DPU_DMA_TOP";
|
|
power-domains = <0x07>;
|
|
phandle = <0xd4>;
|
|
};
|
|
|
|
sysmmu@0x1AE40000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x1ae40000 0x9000>;
|
|
interrupts = <0x00 0x1bc 0x04 0x00 0x1bd 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x1ae60000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0xaa>;
|
|
sysmmu,tlb_property = <0x02 0x8a 0x100 0x1f0000 0x04 0x2a 0x100 0x1f0002 0x01 0xaa 0x100 0x1f0005 0x05 0x2a 0x100 0x1f0006 0x09 0x0a 0x100 0x1f0007 0x03 0x8a 0x100 0x1f0008 0x06 0x2a 0x100 0x1f000a 0x07 0x2a 0x100 0x1f000c 0x08 0x2a 0x100 0x1f000d 0x0a 0x0a 0x100 0x1f0010 0x0b 0x0a 0x100 0x1f0014 0x0c 0x0a 0x200 0x1f0000 0x0d 0x0a 0x200 0x1f0001>;
|
|
port-name = "DPU_DMA_TOP";
|
|
power-domains = <0x07>;
|
|
phandle = <0xd5>;
|
|
};
|
|
|
|
sysmmu@0x1AE50000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x1ae50000 0x9000>;
|
|
interrupts = <0x00 0x1c4 0x04 0x00 0x1c5 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x1ae70000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x8a>;
|
|
sysmmu,tlb_property = <0x02 0x2a 0x100 0x1f0002 0x03 0x2a 0x100 0x1f0004 0x04 0x2a 0x100 0x1f0005 0x08 0x0a 0x100 0x1f0006 0x09 0x0a 0x100 0x1f0007 0x01 0x8a 0x100 0x1f0008 0x05 0x2a 0x100 0x1f000a 0x06 0x2a 0x100 0x1f000c 0x07 0x2a 0x100 0x1f000d 0x0a 0x00 0x200 0x1f0010 0x0b 0x00 0x200 0x1f0014>;
|
|
port-name = "DPU_DMA_TOP";
|
|
power-domains = <0x07>;
|
|
phandle = <0xd6>;
|
|
};
|
|
|
|
sysmmu@0x176A0000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x176a0000 0x9000>;
|
|
interrupts = <0x00 0x208 0x04 0x00 0x209 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x176b0000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0xaa>;
|
|
sysmmu,tlb_property = <0x05 0x0a 0x100 0x1f0008 0x02 0x6a 0x200 0x1f0000 0x06 0x0a 0x200 0x1f0008 0x03 0x6a 0x200 0x1f0010 0x07 0x0a 0x200 0x1f0018 0x01 0xaa 0x100 0xf0001 0x08 0x0a 0x100 0xf0009 0x0f 0x00 0x200 0xf0002 0x0d 0x00 0x200 0xf0003 0x0e 0x00 0x100 0xf0004 0x09 0x0a 0x200 0x1f0005 0x0a 0x0a 0x200 0x1f000d 0x04 0x20 0x100 0x1f0005 0x0b 0x0a 0x100 0x1f000d 0x0c 0x0a 0x200 0x1f0015>;
|
|
port-name = "GDC_V10.0 (M0), GDC_V10.0 (M...";
|
|
power-domains = <0x08>;
|
|
phandle = <0x167>;
|
|
};
|
|
|
|
sysmmu@0x18A00000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x18a00000 0x9000>;
|
|
interrupts = <0x00 0x211 0x04 0x00 0x212 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x18a10000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0xaa>;
|
|
sysmmu,tlb_property = <0x0a 0x00 0x100 0x3f000a 0x0b 0x0a 0x200 0x3f0022 0x0c 0x0a 0x200 0x3f0032 0x10 0x00 0x200 0x3f000a 0x01 0x60 0x300 0x70000 0x02 0x60 0x300 0x70001 0x03 0x60 0x300 0x70003 0x07 0x6a 0x100 0x3f0004 0x04 0x4a 0x100 0x3f000c 0x08 0x6a 0x100 0x3f0014 0x05 0x4a 0x100 0x3f001c 0x09 0x6a 0x100 0x3f0024 0x0d 0x0a 0x100 0x3f002c 0x06 0x4a 0x200 0x1f0004 0x11 0x2a 0x200 0x1f000c 0x0e 0x0a 0x200 0x1f0014 0x0f 0x0a 0x200 0x1f001c>;
|
|
port-name = "M2M, JPEG0, JPEG1, JSQZ, FRC...";
|
|
power-domains = <0x09>;
|
|
phandle = <0x15e>;
|
|
};
|
|
|
|
sysmmu@0x15C70000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x15c70000 0x9000>;
|
|
interrupts = <0x00 0x236 0x04 0x00 0x237 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x15c80000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0xaa>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x100 0x20002>;
|
|
port-name = "MCFPV10.1 (M0)";
|
|
power-domains = <0x0a>;
|
|
phandle = <0x169>;
|
|
};
|
|
|
|
sysmmu@0x15CA0000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x15ca0000 0x9000>;
|
|
interrupts = <0x00 0x23a 0x04 0x00 0x23b 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x15cb0000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0xaa>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x100 0x1f0004 0x0a 0x00 0x100 0x1f0001 0x02 0x0a 0x200 0x1f0001 0x03 0x0a 0x200 0x1f0005 0x04 0x0a 0x200 0x1f0009 0x05 0x0a 0x200 0x1f000d 0x06 0x0a 0x200 0x1f0011 0x07 0x0a 0x200 0x1f0002 0x08 0x0a 0x200 0x1f000a 0x09 0x0a 0x200 0x1f0012>;
|
|
port-name = "MCFPV10.1 (M2), MCSCV10.1 (M...";
|
|
power-domains = <0x0a>;
|
|
phandle = <0x16a>;
|
|
};
|
|
|
|
sysmmu@0x15CD0000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x15cd0000 0x9000>;
|
|
interrupts = <0x00 0x23e 0x04 0x00 0x23f 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x15ce0000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0xaa>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x100 0x1f0004 0x02 0x0a 0x200 0x1f0001 0x03 0x0a 0x200 0x1f0009 0x04 0x0a 0x200 0x1f0011 0x05 0x0a 0x200 0x1f0002 0x06 0x0a 0x200 0x1f000a 0x07 0x0a 0x200 0x1f0012>;
|
|
port-name = "MCFPV10.1 (M3), MCSCV10.1 (M...";
|
|
power-domains = <0x0a>;
|
|
phandle = <0x16b>;
|
|
};
|
|
|
|
sysmmu@0x15D00000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x15d00000 0x9000>;
|
|
interrupts = <0x00 0x1ce 0x04 0x00 0x1cf 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x15d10000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x8a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x100 0x70001 0x04 0x00 0x100 0x70002 0x05 0x0a 0x200 0x70000 0x02 0x0a 0x200 0x70001 0x03 0x0a 0x200 0x70005>;
|
|
port-name = "MCFPV10.1 (M4), MCFPV10.1 (M...";
|
|
power-domains = <0x0a>;
|
|
phandle = <0x16c>;
|
|
};
|
|
|
|
sysmmu@0x15D30000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x15d30000 0x9000>;
|
|
interrupts = <0x00 0x1d8 0x04 0x00 0x1ec 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x15d40000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x100 0x3f0001 0x02 0x0a 0x100 0x3f0002 0x03 0x0a 0x100 0x3f0003 0x04 0x0a 0x100 0x3f0004 0x05 0x0a 0x200 0x3f0000 0x06 0x0a 0x200 0x3f0008 0x07 0x0a 0x100 0x3f0005 0x08 0x0a 0x100 0x3f000d 0x09 0x0a 0x200 0x3f0005 0x0a 0x0a 0x200 0x3f000d 0x0b 0x0a 0x200 0x3f0015 0x0c 0x0a 0x200 0x3f001d 0x0d 0x0a 0x200 0x3f0025 0x0e 0x00 0x200 0xf0006 0x0f 0x00 0x200 0xf0007>;
|
|
port-name = "MCFPV10.1 (M6), MCFPV10.1 (M...";
|
|
power-domains = <0x0a>;
|
|
phandle = <0x16d>;
|
|
};
|
|
|
|
sysmmu@0x18670000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x18670000 0x9000>;
|
|
interrupts = <0x00 0x244 0x04 0x00 0x245 0x04>;
|
|
sysmmu,async-fault;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x18680000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x40>;
|
|
port-name = "FIMV_MFCM_V16.0 (M0)";
|
|
power-domains = <0x0b>;
|
|
phandle = <0x158>;
|
|
};
|
|
|
|
sysmmu@0x186A0000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x186a0000 0xa000>;
|
|
interrupts = <0x00 0x248 0x04 0x00 0x249 0x04>;
|
|
sysmmu,async-fault;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x186b0000>;
|
|
qos = <0x0f>;
|
|
vmid_mask = <0x03>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x4a>;
|
|
sysmmu,tlb_property = <0x02 0x00 0x200 0x30001 0x01 0x00 0x300 0x30002>;
|
|
port-name = "FIMV_MFCM_V16.0 (M1), FIMV_M...";
|
|
power-domains = <0x0b>;
|
|
phandle = <0x159>;
|
|
};
|
|
|
|
sysmmu@0x18870000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x18870000 0x9000>;
|
|
interrupts = <0x00 0x24f 0x04 0x00 0x250 0x04>;
|
|
sysmmu,async-fault;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x18880000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x40>;
|
|
port-name = "FIMV_MFCS_V16.0 (M0)";
|
|
power-domains = <0x0c>;
|
|
phandle = <0x15a>;
|
|
};
|
|
|
|
sysmmu@0x188A0000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x188a0000 0x9000>;
|
|
interrupts = <0x00 0x253 0x04 0x00 0x254 0x04>;
|
|
sysmmu,async-fault;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x188b0000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x4a>;
|
|
port-name = "FIMV_MFCS_V16.0 (M1)";
|
|
power-domains = <0x0c>;
|
|
phandle = <0x15b>;
|
|
};
|
|
|
|
sysmmu@0x18070000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x18070000 0x9000>;
|
|
interrupts = <0x00 0x22a 0x04 0x00 0x22b 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x18080000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x200 0x30001 0x06 0x00 0x100 0x30000 0x04 0x00 0x200 0x30000 0x02 0x0a 0x100 0x30002 0x03 0x0a 0x200 0x30002 0x05 0x00 0x200 0x30003>;
|
|
port-name = "YUVP_M1_Y_Y, YUVP_M0_CL_VOTF...";
|
|
power-domains = <0x0d>;
|
|
phandle = <0x175>;
|
|
};
|
|
|
|
sysmmu@0x180A0000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x180a0000 0x9000>;
|
|
interrupts = <0x00 0x22e 0x04 0x00 0x22f 0x04>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x180b0000>;
|
|
qos = <0x0f>;
|
|
#iommu-cells = <0x00>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x100 0x30001 0x02 0x0a 0x100 0x30002 0x03 0x00 0x100 0x30003>;
|
|
port-name = "YUVP_M3_SEG_x, YUVP_M4_DRC0_...";
|
|
power-domains = <0x0d>;
|
|
phandle = <0x176>;
|
|
};
|
|
|
|
dma_heap_exception_area {
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
exception-range = <0x08 0x80000000 0x20000000>;
|
|
};
|
|
|
|
system_dma_heap {
|
|
compatible = "samsung,dma-heap-system";
|
|
dma-heap,name = "system";
|
|
};
|
|
|
|
crypto_dma_heap {
|
|
compatible = "samsung,dma-heap-cma";
|
|
memory-region = <0x0e>;
|
|
dma-heap,name = "crypto";
|
|
dma-heap,alignment = <0x10000>;
|
|
};
|
|
|
|
video_stream_dma_heap {
|
|
compatible = "samsung,dma-heap-cma";
|
|
memory-region = <0x0f>;
|
|
dma-heap,name = "system-secure-vstream";
|
|
dma-heap,secure;
|
|
dma-heap,protection_id = <0x03>;
|
|
dma-heap,alignment = <0x10000>;
|
|
};
|
|
|
|
video_frame_dma_heap {
|
|
compatible = "samsung,dma-heap-carveout";
|
|
memory-region = <0x10>;
|
|
dma-heap,name = "vframe";
|
|
dma-heap,secure;
|
|
dma-heap,protection_id = <0x05>;
|
|
dma-heap,alignment = <0x10000>;
|
|
};
|
|
|
|
video_scaler_dma_heap {
|
|
compatible = "samsung,dma-heap-carveout";
|
|
memory-region = <0x11>;
|
|
dma-heap,name = "vscaler";
|
|
dma-heap,secure;
|
|
dma-heap,protection_id = <0x06>;
|
|
dma-heap,alignment = <0x10000>;
|
|
};
|
|
|
|
gpu_buffer_dma_heap {
|
|
compatible = "samsung,dma-heap-carveout";
|
|
memory-region = <0x12>;
|
|
dma-heap,name = "system-secure-gpu_buffer";
|
|
dma-heap,secure;
|
|
dma-heap,protection_id = <0x09>;
|
|
dma-heap,alignment = <0x10000>;
|
|
};
|
|
|
|
secure_camera_dma_heap {
|
|
compatible = "samsung,dma-heap-carveout";
|
|
memory-region = <0x13>;
|
|
dma-heap,name = "secure_camera";
|
|
dma-heap,untouchable;
|
|
dma-heap,secure;
|
|
dma-heap,protection_id = <0x0b>;
|
|
dma-heap,alignment = <0x10000>;
|
|
};
|
|
|
|
tui_dma_heap {
|
|
compatible = "samsung,dma-heap-cma";
|
|
memory-region = <0x14>;
|
|
dma-heap,name = "tui";
|
|
dma-heap,secure;
|
|
dma-heap,protection_id = <0x14>;
|
|
dma-heap,alignment = <0x10000>;
|
|
};
|
|
|
|
secure_dsp_dma_heap {
|
|
compatible = "samsung,dma-heap-cma";
|
|
memory-region = <0x15>;
|
|
dma-heap,name = "secure_dsp";
|
|
};
|
|
|
|
rbin_dma_heap {
|
|
compatible = "samsung,dma-heap-rbin";
|
|
memory-region = <0x16>;
|
|
dma-heap,name = "camera";
|
|
dma-heap,alignment = <0x10000>;
|
|
};
|
|
|
|
pinctrl@15850000 {
|
|
compatible = "samsung,s5e9925-pinctrl";
|
|
reg = <0x00 0x15850000 0x1000>;
|
|
interrupts = <0x00 0x00 0x04 0x00 0x01 0x04 0x00 0x02 0x04 0x00 0x03 0x04 0x00 0x04 0x04 0x00 0x05 0x04 0x00 0x06 0x04 0x00 0x07 0x04 0x00 0x08 0x04 0x00 0x09 0x04 0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04 0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04 0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x12 0x04 0x00 0x13 0x04 0x00 0x14 0x04 0x00 0x15 0x04 0x00 0x16 0x04 0x00 0x17 0x04 0x00 0x18 0x04 0x00 0x19 0x04 0x00 0x1a 0x04 0x00 0x1b 0x04 0x00 0x1c 0x04 0x00 0x1d 0x04 0x00 0x1e 0x04 0x00 0x1f 0x04 0x00 0x20 0x04 0x00 0x21 0x04>;
|
|
phandle = <0x1a1>;
|
|
|
|
gpa0 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x00 0x04 0x00 0x01 0x04 0x00 0x02 0x04 0x00 0x03 0x04 0x00 0x04 0x04 0x00 0x05 0x04 0x00 0x06 0x04 0x00 0x07 0x04>;
|
|
phandle = <0x1a2>;
|
|
};
|
|
|
|
gpa1 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x08 0x04 0x00 0x09 0x04 0x00 0x0a 0x04 0x00 0x0b 0x04 0x00 0x0c 0x04 0x00 0x0d 0x04 0x00 0x0e 0x04 0x00 0x0f 0x04>;
|
|
phandle = <0x1a3>;
|
|
};
|
|
|
|
gpa2 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x10 0x04 0x00 0x11 0x04 0x00 0x12 0x04 0x00 0x13 0x04 0x00 0x14 0x04 0x00 0x15 0x04 0x00 0x16 0x04 0x00 0x17 0x04>;
|
|
phandle = <0x1a4>;
|
|
};
|
|
|
|
gpa3 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x18 0x04 0x00 0x19 0x04 0x00 0x1a 0x04 0x00 0x1b 0x04 0x00 0x1c 0x04 0x00 0x1d 0x04 0x00 0x1e 0x04 0x00 0x1f 0x04>;
|
|
phandle = <0x1a5>;
|
|
};
|
|
|
|
gpa4 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x20 0x04 0x00 0x21 0x04>;
|
|
phandle = <0x1a6>;
|
|
};
|
|
|
|
gpq0 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
phandle = <0x1a7>;
|
|
};
|
|
|
|
gpq1 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
phandle = <0x1a8>;
|
|
};
|
|
|
|
gpq2 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
phandle = <0x1a9>;
|
|
};
|
|
|
|
uart1-bus {
|
|
samsung,pins = "gpq0-3\0gpq0-2\0gpq0-1\0gpq0-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
phandle = <0x76>;
|
|
};
|
|
|
|
uart1-bus-rts {
|
|
samsung,pins = "gpq0-2";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-val = <0x01>;
|
|
phandle = <0x77>;
|
|
};
|
|
|
|
uart1-bus-tx-dat {
|
|
samsung,pins = "gpq0-1";
|
|
samsung,pin-val = <0x01>;
|
|
phandle = <0x79>;
|
|
};
|
|
|
|
uart1-bus-tx-con {
|
|
samsung,pins = "gpq0-1";
|
|
samsung,pin-function = <0x01>;
|
|
phandle = <0x78>;
|
|
};
|
|
|
|
wakeup-interrupt-controller {
|
|
compatible = "samsung,exynos7-wakeup-eint";
|
|
};
|
|
};
|
|
|
|
pinctrl@14E30000 {
|
|
compatible = "samsung,s5e9925-pinctrl";
|
|
reg = <0x00 0x14e30000 0x1000>;
|
|
interrupts = <0x00 0x80 0x04 0x00 0x81 0x04 0x00 0x82 0x04 0x00 0x83 0x04 0x00 0x84 0x04 0x00 0x85 0x04 0x00 0x86 0x04 0x00 0x87 0x04 0x00 0x88 0x04 0x00 0x89 0x04 0x00 0x8a 0x04 0x00 0x8b 0x04 0x00 0x8c 0x04 0x00 0x8d 0x04 0x00 0x8e 0x04 0x00 0x8f 0x04 0x00 0x90 0x04 0x00 0x91 0x04 0x00 0x92 0x04 0x00 0x93 0x04 0x00 0x94 0x04 0x00 0x95 0x04 0x00 0x96 0x04 0x00 0x97 0x04 0x00 0x98 0x04 0x00 0x99 0x04 0x00 0x9a 0x04 0x00 0x9b 0x04 0x00 0x9c 0x04 0x00 0x9d 0x04 0x00 0x9e 0x04 0x00 0x9f 0x04 0x00 0xa2 0x04 0x00 0xa3 0x04 0x00 0xa4 0x04 0x00 0xa5 0x04 0x00 0xa6 0x04>;
|
|
phandle = <0x1aa>;
|
|
|
|
gpm0 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x80 0x04 0x00 0x81 0x04>;
|
|
phandle = <0x42>;
|
|
};
|
|
|
|
gpm1 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x82 0x04 0x00 0x83 0x04>;
|
|
phandle = <0x44>;
|
|
};
|
|
|
|
gpm2 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x84 0x04 0x00 0x85 0x04>;
|
|
phandle = <0x46>;
|
|
};
|
|
|
|
gpm3 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x86 0x04 0x00 0x87 0x04>;
|
|
phandle = <0x48>;
|
|
};
|
|
|
|
gpm4 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x88 0x04 0x00 0x89 0x04>;
|
|
phandle = <0x4a>;
|
|
};
|
|
|
|
gpm5 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x8a 0x04 0x00 0x8b 0x04>;
|
|
phandle = <0x4c>;
|
|
};
|
|
|
|
gpm6 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x8c 0x04 0x00 0x8d 0x04>;
|
|
phandle = <0x4e>;
|
|
};
|
|
|
|
gpm7 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x8e 0x04 0x00 0x8f 0x04>;
|
|
phandle = <0x50>;
|
|
};
|
|
|
|
gpm8 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x90 0x04 0x00 0x91 0x04>;
|
|
phandle = <0x52>;
|
|
};
|
|
|
|
gpm9 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x92 0x04 0x00 0x93 0x04>;
|
|
phandle = <0x54>;
|
|
};
|
|
|
|
gpm10 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x94 0x04 0x00 0x95 0x04>;
|
|
phandle = <0x56>;
|
|
};
|
|
|
|
gpm11 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x96 0x04 0x00 0x97 0x04>;
|
|
phandle = <0x58>;
|
|
};
|
|
|
|
gpm12 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x98 0x04 0x00 0x99 0x04>;
|
|
phandle = <0x5a>;
|
|
};
|
|
|
|
gpm13 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x9a 0x04 0x00 0x9b 0x04>;
|
|
phandle = <0x5c>;
|
|
};
|
|
|
|
gpm14 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x9c 0x04>;
|
|
phandle = <0x1ab>;
|
|
};
|
|
|
|
gpm15 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x9d 0x04>;
|
|
phandle = <0x1ac>;
|
|
};
|
|
|
|
gpm16 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x9e 0x04>;
|
|
phandle = <0x1ad>;
|
|
};
|
|
|
|
gpm17 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x9f 0x04>;
|
|
phandle = <0x1ae>;
|
|
};
|
|
|
|
gpm20 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0xa2 0x04>;
|
|
phandle = <0x1af>;
|
|
};
|
|
|
|
gpm21 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0xa3 0x04>;
|
|
phandle = <0x1b0>;
|
|
};
|
|
|
|
gpm22 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0xa4 0x04>;
|
|
phandle = <0x1b1>;
|
|
};
|
|
|
|
gpm23 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0xa5 0x04>;
|
|
phandle = <0x5e>;
|
|
};
|
|
|
|
gpm24 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0xa6 0x04>;
|
|
phandle = <0x5f>;
|
|
};
|
|
|
|
hsi2c24-bus {
|
|
samsung,pins = "gpm0-0\0gpm0-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x41>;
|
|
};
|
|
|
|
hsi2c25-bus {
|
|
samsung,pins = "gpm1-0\0gpm1-1";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x43>;
|
|
};
|
|
|
|
hsi2c26-bus {
|
|
samsung,pins = "gpm2-0\0gpm2-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x45>;
|
|
};
|
|
|
|
hsi2c27-bus {
|
|
samsung,pins = "gpm3-0\0gpm3-1";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x47>;
|
|
};
|
|
|
|
hsi2c28-bus {
|
|
samsung,pins = "gpm4-0\0gpm4-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x49>;
|
|
};
|
|
|
|
hsi2c29-bus {
|
|
samsung,pins = "gpm5-0\0gpm5-1";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x4b>;
|
|
};
|
|
|
|
hsi2c30-bus {
|
|
samsung,pins = "gpm6-0\0gpm6-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x4d>;
|
|
};
|
|
|
|
hsi2c31-bus {
|
|
samsung,pins = "gpm7-0\0gpm7-1";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x4f>;
|
|
};
|
|
|
|
hsi2c32-bus {
|
|
samsung,pins = "gpm8-0\0gpm8-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x51>;
|
|
};
|
|
|
|
hsi2c33-bus {
|
|
samsung,pins = "gpm9-0\0gpm9-1";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x53>;
|
|
};
|
|
|
|
hsi2c34-bus {
|
|
samsung,pins = "gpm10-0\0gpm10-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x55>;
|
|
};
|
|
|
|
hsi2c35-bus {
|
|
samsung,pins = "gpm11-0\0gpm11-1";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x57>;
|
|
};
|
|
|
|
hsi2c36-bus {
|
|
samsung,pins = "gpm12-0\0gpm12-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x59>;
|
|
};
|
|
|
|
hsi2c37-bus {
|
|
samsung,pins = "gpm13-0\0gpm13-1";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x5b>;
|
|
};
|
|
|
|
hsi2c38-bus {
|
|
samsung,pins = "gpm23-0\0gpm24-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x5d>;
|
|
};
|
|
|
|
spi12-bus {
|
|
samsung,pins = "gpm0-0\0gpm0-1\0gpm1-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x6e>;
|
|
};
|
|
|
|
spi12-cs {
|
|
samsung,pins = "gpm1-1";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1b2>;
|
|
};
|
|
|
|
spi12-cs-func {
|
|
samsung,pins = "gpm1-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1b3>;
|
|
};
|
|
|
|
spi13-bus {
|
|
samsung,pins = "gpm2-0\0gpm2-1\0gpm3-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x6f>;
|
|
};
|
|
|
|
spi13-cs {
|
|
samsung,pins = "gpm3-1";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1b4>;
|
|
};
|
|
|
|
spi13-cs-func {
|
|
samsung,pins = "gpm3-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1b5>;
|
|
};
|
|
|
|
spi14-bus {
|
|
samsung,pins = "gpm4-0\0gpm4-1\0gpm5-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x70>;
|
|
};
|
|
|
|
spi14-cs {
|
|
samsung,pins = "gpm5-1";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1b6>;
|
|
};
|
|
|
|
spi14-cs-func {
|
|
samsung,pins = "gpm5-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1b7>;
|
|
};
|
|
|
|
spi15-bus {
|
|
samsung,pins = "gpm6-0\0gpm6-1\0gpm7-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x71>;
|
|
};
|
|
|
|
spi15-cs {
|
|
samsung,pins = "gpm7-1";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1b8>;
|
|
};
|
|
|
|
spi15-cs-func {
|
|
samsung,pins = "gpm7-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1b9>;
|
|
};
|
|
|
|
spi16-bus {
|
|
samsung,pins = "gpm8-0\0gpm8-1\0gpm9-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x72>;
|
|
};
|
|
|
|
spi16-cs {
|
|
samsung,pins = "gpm9-1";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1ba>;
|
|
};
|
|
|
|
spi16-cs-func {
|
|
samsung,pins = "gpm9-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1bb>;
|
|
};
|
|
|
|
spi17-bus {
|
|
samsung,pins = "gpm10-0\0gpm10-1\0gpm11-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x73>;
|
|
};
|
|
|
|
spi17-cs {
|
|
samsung,pins = "gpm11-1";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1bc>;
|
|
};
|
|
|
|
spi17-cs-func {
|
|
samsung,pins = "gpm11-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1bd>;
|
|
};
|
|
|
|
spi18-bus {
|
|
samsung,pins = "gpm12-0\0gpm12-1\0gpm13-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x74>;
|
|
};
|
|
|
|
spi18-cs {
|
|
samsung,pins = "gpm13-1";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1be>;
|
|
};
|
|
|
|
spi18-cs-func {
|
|
samsung,pins = "gpm13-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1bf>;
|
|
};
|
|
|
|
uart14-bus {
|
|
samsung,pins = "gpm0-0\0gpm0-1\0gpm2-0\0gpm2-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x86>;
|
|
};
|
|
|
|
uart14-bus-dual {
|
|
samsung,pins = "gpm0-0\0gpm0-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1c0>;
|
|
};
|
|
|
|
uart15-bus {
|
|
samsung,pins = "gpm3-0\0gpm3-1\0gpm4-0\0gpm4-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x87>;
|
|
};
|
|
|
|
uart15-bus-dual {
|
|
samsung,pins = "gpm3-0\0gpm3-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1c1>;
|
|
};
|
|
|
|
uart16-bus {
|
|
samsung,pins = "gpm5-0\0gpm5-1\0gpm6-0\0gpm6-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x88>;
|
|
};
|
|
|
|
uart16-bus-dual {
|
|
samsung,pins = "gpm5-0\0gpm5-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1c2>;
|
|
};
|
|
|
|
uart17-bus {
|
|
samsung,pins = "gpm7-0\0gpm7-1\0gpm8-0\0gpm8-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x89>;
|
|
};
|
|
|
|
uart17-bus-dual {
|
|
samsung,pins = "gpm7-0\0gpm7-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1c3>;
|
|
};
|
|
|
|
uart18-bus {
|
|
samsung,pins = "gpm8-0\0gpm8-1\0gpm9-0\0gpm9-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x8a>;
|
|
};
|
|
|
|
uart18-bus-dual {
|
|
samsung,pins = "gpm8-0\0gpm8-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1c4>;
|
|
};
|
|
|
|
uart19-bus {
|
|
samsung,pins = "gpm10-0\0gpm10-1\0gpm11-0\0gpm11-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x8b>;
|
|
};
|
|
|
|
uart19-bus-dual {
|
|
samsung,pins = "gpm12-0\0gpm12-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1c5>;
|
|
};
|
|
|
|
uart20-bus {
|
|
samsung,pins = "gpm13-0\0gpm13-1\0gpm14-0\0gpm14-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x8c>;
|
|
};
|
|
|
|
uart20-bus-dual {
|
|
samsung,pins = "gpm13-0\0gpm13-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1c6>;
|
|
};
|
|
|
|
wakeup-interrupt-controller {
|
|
compatible = "samsung,exynos-cmgp-wakeup-eint";
|
|
};
|
|
};
|
|
|
|
pinctrl@11240000 {
|
|
compatible = "samsung,s5e9925-pinctrl";
|
|
reg = <0x00 0x11240000 0x1000>;
|
|
interrupts = <0x00 0x1eb 0x04>;
|
|
phandle = <0x1c7>;
|
|
|
|
gpf0 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0xf2>;
|
|
};
|
|
|
|
pcie0_clkreq {
|
|
samsung,pins = "gpf0-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x03>;
|
|
samsung,pin-con-pdn = <0x03>;
|
|
samsung,pin-pud-pdn = <0x03>;
|
|
phandle = <0xf3>;
|
|
};
|
|
|
|
pcie0_perst {
|
|
samsung,pins = "gpf0-1";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-drv = <0x03>;
|
|
samsung,pin-con-pdn = <0x03>;
|
|
phandle = <0xf4>;
|
|
};
|
|
|
|
pcie1_clkreq {
|
|
samsung,pins = "gpf0-2";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x03>;
|
|
samsung,pin-con-pdn = <0x03>;
|
|
samsung,pin-pud-pdn = <0x03>;
|
|
phandle = <0xf6>;
|
|
};
|
|
|
|
pcie1_perst {
|
|
samsung,pins = "gpf0-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-drv = <0x03>;
|
|
samsung,pin-con-pdn = <0x03>;
|
|
phandle = <0xf7>;
|
|
};
|
|
};
|
|
|
|
pinctrl@11040000 {
|
|
compatible = "samsung,s5e9925-pinctrl";
|
|
reg = <0x00 0x11040000 0x1000>;
|
|
interrupts = <0x00 0x224 0x04>;
|
|
phandle = <0x1c8>;
|
|
|
|
gpf1 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1c9>;
|
|
};
|
|
};
|
|
|
|
pinctrl@11060000 {
|
|
compatible = "samsung,s5e9925-pinctrl";
|
|
reg = <0x00 0x11060000 0x1000>;
|
|
interrupts = <0x00 0x223 0x04>;
|
|
phandle = <0x1ca>;
|
|
|
|
gpf2 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1cb>;
|
|
};
|
|
|
|
ufs-rst-n {
|
|
samsung,pins = "gpf2-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x03>;
|
|
samsung,pin-pud-pdn = <0x00>;
|
|
phandle = <0xf8>;
|
|
};
|
|
|
|
ufs-refclk-out {
|
|
samsung,pins = "gpf2-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x03>;
|
|
samsung,pin-drv = <0x02>;
|
|
samsung,pin-pud-pdn = <0x00>;
|
|
phandle = <0xf9>;
|
|
};
|
|
};
|
|
|
|
pinctrl@10430000 {
|
|
compatible = "samsung,s5e9925-pinctrl";
|
|
reg = <0x00 0x10430000 0x1000>;
|
|
interrupts = <0x00 0x29f 0x04>;
|
|
phandle = <0x1cc>;
|
|
|
|
gpb0 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1cd>;
|
|
};
|
|
|
|
gpb1 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1ce>;
|
|
};
|
|
|
|
gpb2 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1cf>;
|
|
};
|
|
|
|
gpb3 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1d0>;
|
|
};
|
|
|
|
gpp4 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x27>;
|
|
};
|
|
|
|
gpc0 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1d1>;
|
|
};
|
|
|
|
gpc1 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1d2>;
|
|
};
|
|
|
|
gpc2 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1d3>;
|
|
};
|
|
|
|
gpg1 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1d4>;
|
|
};
|
|
|
|
gpg2 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0xde>;
|
|
};
|
|
|
|
aud-i2s0-bus {
|
|
samsung,pins = "gpb0-0\0gpb0-1\0gpb0-2\0gpb0-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0xa0>;
|
|
};
|
|
|
|
aud-i2s0-idle {
|
|
samsung,pins = "gpb0-0\0gpb0-1\0gpb0-2\0gpb0-3";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x01>;
|
|
phandle = <0xa1>;
|
|
};
|
|
|
|
aud-i2s1-bus {
|
|
samsung,pins = "gpb1-0\0gpb1-1\0gpb1-2\0gpb1-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0xa2>;
|
|
};
|
|
|
|
aud-i2s1-idle {
|
|
samsung,pins = "gpb1-0\0gpb1-1\0gpb1-2\0gpb1-3";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x01>;
|
|
phandle = <0xa3>;
|
|
};
|
|
|
|
aud-i2s2-bus {
|
|
samsung,pins = "gpb2-0\0gpb2-1\0gpb2-2\0gpb2-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0xa4>;
|
|
};
|
|
|
|
aud-i2s2-idle {
|
|
samsung,pins = "gpb2-0\0gpb2-1\0gpb2-2\0gpb2-3";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x01>;
|
|
phandle = <0xa5>;
|
|
};
|
|
|
|
aud-i2s3-bus {
|
|
samsung,pins = "gpb3-0\0gpb3-1\0gpb3-2\0gpb3-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0xa6>;
|
|
};
|
|
|
|
aud-i2s3-pci {
|
|
samsung,pins = "gpb3-0\0gpb3-1";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0xaa>;
|
|
};
|
|
|
|
aud-i2s3-idle {
|
|
samsung,pins = "gpb3-0\0gpb3-1\0gpb3-2\0gpb3-3";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x01>;
|
|
phandle = <0xa7>;
|
|
};
|
|
|
|
aud-dsd-bus {
|
|
samsung,pins = "gpb1-0\0gpb1-1\0gpb1-2";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1d5>;
|
|
};
|
|
|
|
aud-dsd-idle {
|
|
samsung,pins = "gpb1-0\0gpb1-1\0gpb1-2";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x01>;
|
|
phandle = <0x1d6>;
|
|
};
|
|
|
|
hsi2c8-bus {
|
|
samsung,pins = "gpp4-0\0gpp4-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x26>;
|
|
};
|
|
|
|
hsi2c9-bus {
|
|
samsung,pins = "gpp4-2\0gpp4-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x28>;
|
|
};
|
|
|
|
spi4-bus {
|
|
samsung,pins = "gpp4-2\0gpp4-1\0gpp4-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x66>;
|
|
};
|
|
|
|
spi4-cs {
|
|
samsung,pins = "gpp4-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1d7>;
|
|
};
|
|
|
|
spi4-cs-func {
|
|
samsung,pins = "gpp4-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1d8>;
|
|
};
|
|
|
|
i3c0-bus {
|
|
samsung,pins = "gpc0-0\0gpc0-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x8d>;
|
|
};
|
|
|
|
i3c1-bus {
|
|
samsung,pins = "gpc1-0\0gpc1-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x8e>;
|
|
};
|
|
|
|
i3c2-bus {
|
|
samsung,pins = "gpc2-0\0gpc2-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
samsung,pin-con-pdn = <0x03>;
|
|
samsung,pin-pud-pdn = <0x00>;
|
|
phandle = <0x8f>;
|
|
};
|
|
|
|
uart6-bus {
|
|
samsung,pins = "gpp4-0\0gpp4-1\0gpp4-2\0gpp4-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x7e>;
|
|
};
|
|
|
|
uart6-bus-dual {
|
|
samsung,pins = "gpp4-0\0gpp4-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1d9>;
|
|
};
|
|
|
|
sensor-mclk0-out {
|
|
samsung,pins = "gpg1-0";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1da>;
|
|
};
|
|
|
|
sensor-mclk1-out {
|
|
samsung,pins = "gpg1-1";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1db>;
|
|
};
|
|
|
|
sensor-mclk2-out {
|
|
samsung,pins = "gpg1-2";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1dc>;
|
|
};
|
|
|
|
sensor-mclk3-out {
|
|
samsung,pins = "gpg1-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1dd>;
|
|
};
|
|
|
|
sensor-mclk4-out {
|
|
samsung,pins = "gpg1-4";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1de>;
|
|
};
|
|
|
|
sensor-mclk5-out {
|
|
samsung,pins = "gpg1-5";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1df>;
|
|
};
|
|
|
|
sensor-mclk0-fn {
|
|
samsung,pins = "gpg1-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1e0>;
|
|
};
|
|
|
|
sensor-mclk1-fn {
|
|
samsung,pins = "gpg1-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1e1>;
|
|
};
|
|
|
|
sensor-mclk2-fn {
|
|
samsung,pins = "gpg1-2";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1e2>;
|
|
};
|
|
|
|
sensor-mclk3-fn {
|
|
samsung,pins = "gpg1-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1e3>;
|
|
};
|
|
|
|
sensor-mclk4-fn {
|
|
samsung,pins = "gpg1-4";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1e4>;
|
|
};
|
|
|
|
sensor-mclk5-fn {
|
|
samsung,pins = "gpg1-5";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1e5>;
|
|
};
|
|
|
|
decon_0_te_on {
|
|
samsung,pins = "gpg2-0";
|
|
samsung,pin-function = <0x0f>;
|
|
phandle = <0xdc>;
|
|
};
|
|
|
|
decon_0_te_off {
|
|
samsung,pins = "gpg2-0";
|
|
samsung,pin-function = <0x00>;
|
|
phandle = <0xdd>;
|
|
};
|
|
};
|
|
|
|
pinctrl@10730000 {
|
|
compatible = "samsung,s5e9925-pinctrl";
|
|
reg = <0x00 0x10730000 0x1000>;
|
|
interrupts = <0x00 0x2a3 0x04>;
|
|
phandle = <0x1e6>;
|
|
|
|
gpp7 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x32>;
|
|
};
|
|
|
|
gpp8 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x35>;
|
|
};
|
|
|
|
gpp9 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x38>;
|
|
};
|
|
|
|
gpp10 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x3b>;
|
|
};
|
|
|
|
hsi2c14-bus {
|
|
samsung,pins = "gpp7-0\0gpp7-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x31>;
|
|
};
|
|
|
|
hsi2c15-bus {
|
|
samsung,pins = "gpp7-2\0gpp7-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x33>;
|
|
};
|
|
|
|
hsi2c16-bus {
|
|
samsung,pins = "gpp8-0\0gpp8-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x34>;
|
|
};
|
|
|
|
hsi2c17-bus {
|
|
samsung,pins = "gpp8-2\0gpp8-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x36>;
|
|
};
|
|
|
|
hsi2c18-bus {
|
|
samsung,pins = "gpp9-0\0gpp9-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x37>;
|
|
};
|
|
|
|
hsi2c19-bus {
|
|
samsung,pins = "gpp9-2\0gpp9-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x39>;
|
|
};
|
|
|
|
hsi2c20-bus {
|
|
samsung,pins = "gpp10-0\0gpp10-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x3a>;
|
|
};
|
|
|
|
hsi2c21-bus {
|
|
samsung,pins = "gpp10-2\0gpp10-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x3c>;
|
|
};
|
|
|
|
spi7-bus {
|
|
samsung,pins = "gpp7-2\0gpp7-1\0gpp7-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x69>;
|
|
};
|
|
|
|
spi7-cs {
|
|
samsung,pins = "gpp7-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1e7>;
|
|
};
|
|
|
|
spi7-cs-func {
|
|
samsung,pins = "gpp7-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1e8>;
|
|
};
|
|
|
|
spi8-bus {
|
|
samsung,pins = "gpp8-2\0gpp8-1\0gpp8-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x6a>;
|
|
};
|
|
|
|
spi8-cs {
|
|
samsung,pins = "gpp8-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1e9>;
|
|
};
|
|
|
|
spi8-cs-func {
|
|
samsung,pins = "gpp8-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1ea>;
|
|
};
|
|
|
|
spi9-bus {
|
|
samsung,pins = "gpp9-2\0gpp9-1\0gpp9-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x6b>;
|
|
};
|
|
|
|
spi9-cs {
|
|
samsung,pins = "gpp9-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1eb>;
|
|
};
|
|
|
|
spi9-cs-func {
|
|
samsung,pins = "gpp9-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1ec>;
|
|
};
|
|
|
|
spi10-bus {
|
|
samsung,pins = "gpp10-2\0gpp10-1\0gpp10-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x6c>;
|
|
};
|
|
|
|
spi10-cs {
|
|
samsung,pins = "gpp10-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1ed>;
|
|
};
|
|
|
|
spi10-cs-func {
|
|
samsung,pins = "gpp10-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1ee>;
|
|
};
|
|
|
|
uart9-bus {
|
|
samsung,pins = "gpp7-3\0gpp7-2\0gpp7-1\0gpp7-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x81>;
|
|
};
|
|
|
|
uart9-bus-dual {
|
|
samsung,pins = "gpp7-0\0gpp7-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1ef>;
|
|
};
|
|
|
|
uart10-bus {
|
|
samsung,pins = "gpp8-3\0gpp8-2\0gpp8-1\0gpp8-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x82>;
|
|
};
|
|
|
|
uart10-bus-dual {
|
|
samsung,pins = "gpp8-0\0gpp8-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1f0>;
|
|
};
|
|
|
|
uart11-bus {
|
|
samsung,pins = "gpp9-3\0gpp9-2\0gpp9-1\0gpp9-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x83>;
|
|
};
|
|
|
|
uart11-bus-dual {
|
|
samsung,pins = "gpp9-0\0gpp9-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1f1>;
|
|
};
|
|
|
|
uart12-bus {
|
|
samsung,pins = "gpp10-3\0gpp10-2\0gpp10-1\0gpp10-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x84>;
|
|
};
|
|
|
|
uart12-bus-dual {
|
|
samsung,pins = "gpp10-0\0gpp10-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1f2>;
|
|
};
|
|
};
|
|
|
|
pinctrl@11C30000 {
|
|
compatible = "samsung,s5e9925-pinctrl";
|
|
reg = <0x00 0x11c30000 0x1000>;
|
|
interrupts = <0x00 0x2b0 0x04>;
|
|
phandle = <0x1f3>;
|
|
|
|
gpp0 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1a>;
|
|
};
|
|
|
|
gpp1 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1d>;
|
|
};
|
|
|
|
gpp2 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x20>;
|
|
};
|
|
|
|
gpp3 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x23>;
|
|
};
|
|
|
|
gpp5 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x2b>;
|
|
};
|
|
|
|
gpp6 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x2e>;
|
|
};
|
|
|
|
gpp11 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x3e>;
|
|
};
|
|
|
|
gpc3 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1f4>;
|
|
};
|
|
|
|
gpc4 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1f5>;
|
|
};
|
|
|
|
gpc5 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1f6>;
|
|
};
|
|
|
|
gpc6 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1f7>;
|
|
};
|
|
|
|
gpc7 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1f8>;
|
|
};
|
|
|
|
gpc8 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1f9>;
|
|
};
|
|
|
|
gpc9 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1fa>;
|
|
};
|
|
|
|
gpg0 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1fb>;
|
|
};
|
|
|
|
hsi2c0-bus {
|
|
samsung,pins = "gpp0-0\0gpp0-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x18>;
|
|
};
|
|
|
|
hsi2c1-bus {
|
|
samsung,pins = "gpp0-2\0gpp0-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1b>;
|
|
};
|
|
|
|
hsi2c2-bus {
|
|
samsung,pins = "gpp1-0\0gpp1-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1c>;
|
|
};
|
|
|
|
hsi2c3-bus {
|
|
samsung,pins = "gpp1-2\0gpp1-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1e>;
|
|
};
|
|
|
|
hsi2c4-bus {
|
|
samsung,pins = "gpp2-0\0gpp2-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1f>;
|
|
};
|
|
|
|
hsi2c5-bus {
|
|
samsung,pins = "gpp2-2\0gpp2-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x21>;
|
|
};
|
|
|
|
hsi2c6-bus {
|
|
samsung,pins = "gpp3-0\0gpp3-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x22>;
|
|
};
|
|
|
|
hsi2c7-bus {
|
|
samsung,pins = "gpp3-2\0gpp3-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x24>;
|
|
};
|
|
|
|
hsi2c10-bus {
|
|
samsung,pins = "gpp5-0\0gpp5-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x2a>;
|
|
};
|
|
|
|
hsi2c11-bus {
|
|
samsung,pins = "gpp5-2\0gpp5-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x2c>;
|
|
};
|
|
|
|
hsi2c12-bus {
|
|
samsung,pins = "gpp6-0\0gpp6-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x2d>;
|
|
};
|
|
|
|
hsi2c13-bus {
|
|
samsung,pins = "gpp6-2\0gpp6-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x2f>;
|
|
};
|
|
|
|
hsi2c22-bus {
|
|
samsung,pins = "gpp11-0\0gpp11-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x3d>;
|
|
};
|
|
|
|
hsi2c23-bus {
|
|
samsung,pins = "gpp11-2\0gpp11-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x3f>;
|
|
};
|
|
|
|
spi0-bus {
|
|
samsung,pins = "gpp0-2\0gpp0-1\0gpp0-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x62>;
|
|
};
|
|
|
|
spi0-cs {
|
|
samsung,pins = "gpp0-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1fc>;
|
|
};
|
|
|
|
spi0-cs-func {
|
|
samsung,pins = "gpp0-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1fd>;
|
|
};
|
|
|
|
spi1-bus {
|
|
samsung,pins = "gpp1-2\0gpp1-1\0gpp1-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x63>;
|
|
};
|
|
|
|
spi1-cs {
|
|
samsung,pins = "gpp1-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1fe>;
|
|
};
|
|
|
|
spi1-cs-func {
|
|
samsung,pins = "gpp1-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1ff>;
|
|
};
|
|
|
|
spi2-bus {
|
|
samsung,pins = "gpp2-2\0gpp2-1\0gpp2-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x64>;
|
|
};
|
|
|
|
spi2-cs {
|
|
samsung,pins = "gpp2-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x200>;
|
|
};
|
|
|
|
spi2-cs-func {
|
|
samsung,pins = "gpp2-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x201>;
|
|
};
|
|
|
|
spi3-bus {
|
|
samsung,pins = "gpp3-2\0gpp3-1\0gpp3-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x65>;
|
|
};
|
|
|
|
spi3-cs {
|
|
samsung,pins = "gpp3-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x202>;
|
|
};
|
|
|
|
spi3-cs-func {
|
|
samsung,pins = "gpp3-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x203>;
|
|
};
|
|
|
|
spi5-bus {
|
|
samsung,pins = "gpp5-2\0gpp5-1\0gpp5-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x67>;
|
|
};
|
|
|
|
spi5-cs {
|
|
samsung,pins = "gpp5-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x204>;
|
|
};
|
|
|
|
spi5-cs-func {
|
|
samsung,pins = "gpp5-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x205>;
|
|
};
|
|
|
|
spi6-bus {
|
|
samsung,pins = "gpp6-2\0gpp6-1\0gpp6-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x68>;
|
|
};
|
|
|
|
spi6-cs {
|
|
samsung,pins = "gpp6-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x206>;
|
|
};
|
|
|
|
spi6-cs-func {
|
|
samsung,pins = "gpp6-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x207>;
|
|
};
|
|
|
|
spi11-bus {
|
|
samsung,pins = "gpp11-2\0gpp11-1\0gpp11-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x6d>;
|
|
};
|
|
|
|
spi11-cs {
|
|
samsung,pins = "gpp11-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x208>;
|
|
};
|
|
|
|
spi11-cs-func {
|
|
samsung,pins = "gpp11-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x209>;
|
|
};
|
|
|
|
uart0-bus {
|
|
samsung,pins = "gpg0-2\0gpg0-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x03>;
|
|
phandle = <0x75>;
|
|
};
|
|
|
|
uart2-bus {
|
|
samsung,pins = "gpp0-0\0gpp0-1\0gpp0-2\0gpp0-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x7a>;
|
|
};
|
|
|
|
uart2-bus-dual {
|
|
samsung,pins = "gpp0-0\0gpp0-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x20a>;
|
|
};
|
|
|
|
uart3-bus {
|
|
samsung,pins = "gpp1-0\0gpp1-1\0gpp1-2\0gpp1-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x7b>;
|
|
};
|
|
|
|
uart3-bus-dual {
|
|
samsung,pins = "gpp1-0\0gpp1-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x20b>;
|
|
};
|
|
|
|
uart4-bus {
|
|
samsung,pins = "gpp2-0\0gpp2-1\0gpp2-2\0gpp2-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x7c>;
|
|
};
|
|
|
|
uart4-bus-dual {
|
|
samsung,pins = "gpp2-0\0gpp2-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x20c>;
|
|
};
|
|
|
|
uart5-bus {
|
|
samsung,pins = "gpp3-0\0gpp3-1\0gpp3-2\0gpp3-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x7d>;
|
|
};
|
|
|
|
uart5-bus-dual {
|
|
samsung,pins = "gpp3-0\0gpp3-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x20d>;
|
|
};
|
|
|
|
uart7-bus {
|
|
samsung,pins = "gpp5-0\0gpp5-1\0gpp5-2\0gpp5-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x7f>;
|
|
};
|
|
|
|
uart7-bus-dual {
|
|
samsung,pins = "gpp5-0\0gpp5-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x20e>;
|
|
};
|
|
|
|
uart8-bus {
|
|
samsung,pins = "gpp6-3\0gpp6-2\0gpp6-1\0gpp6-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x80>;
|
|
};
|
|
|
|
uart8-bus-dual {
|
|
samsung,pins = "gpp6-0\0gpp6-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x20f>;
|
|
};
|
|
|
|
uart13-bus {
|
|
samsung,pins = "gpp11-3\0gpp11-2\0gpp11-1\0gpp11-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x85>;
|
|
};
|
|
|
|
uart13-bus-dual {
|
|
samsung,pins = "gpp11-0\0gpp11-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x210>;
|
|
};
|
|
|
|
i3c3-bus {
|
|
samsung,pins = "gpc3-0\0gpc3-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x211>;
|
|
};
|
|
|
|
i3c4-bus {
|
|
samsung,pins = "gpc4-0\0gpc4-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x90>;
|
|
};
|
|
|
|
i3c5-bus {
|
|
samsung,pins = "gpc5-0\0gpc5-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
samsung,pin-con-pdn = <0x03>;
|
|
samsung,pin-pud-pdn = <0x00>;
|
|
phandle = <0x91>;
|
|
};
|
|
|
|
i3c6-bus {
|
|
samsung,pins = "gpc6-0\0gpc6-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x92>;
|
|
};
|
|
|
|
i3c7-bus {
|
|
samsung,pins = "gpc7-0\0gpc7-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x93>;
|
|
};
|
|
|
|
i3c8-bus {
|
|
samsung,pins = "gpc8-0\0gpc8-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x94>;
|
|
};
|
|
|
|
i3c9-bus {
|
|
samsung,pins = "gpc9-0\0gpc9-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
samsung,pin-con-pdn = <0x03>;
|
|
samsung,pin-pud-pdn = <0x00>;
|
|
phandle = <0x95>;
|
|
};
|
|
|
|
i3c10-bus {
|
|
samsung,pins = "gpp2-2\0gpp2-3";
|
|
samsung,pin-function = <0x04>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x96>;
|
|
};
|
|
|
|
i3c11-bus {
|
|
samsung,pins = "gpp3-2\0gpp3-3";
|
|
samsung,pin-function = <0x04>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x97>;
|
|
};
|
|
|
|
ddi-rst {
|
|
samsung,pins = "gpc7-0";
|
|
samsung,pin-con-pdn = <0x03>;
|
|
samsung,pin-pud-pdn = <0x00>;
|
|
phandle = <0x212>;
|
|
};
|
|
};
|
|
|
|
pinctrl@15320000 {
|
|
compatible = "samsung,s5e9925-pinctrl";
|
|
reg = <0x00 0x15320000 0x1000>;
|
|
phandle = <0x213>;
|
|
|
|
gpv0 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x214>;
|
|
};
|
|
|
|
dmic-bus-clk0 {
|
|
samsung,pins = "gpv0-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0xab>;
|
|
};
|
|
|
|
dmic-bus-clk0-idle {
|
|
samsung,pins = "gpv0-0";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0xb4>;
|
|
};
|
|
|
|
dmic-bus-clk1 {
|
|
samsung,pins = "gpv0-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0xad>;
|
|
};
|
|
|
|
dmic-bus-clk1-idle {
|
|
samsung,pins = "gpv0-1";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0xb6>;
|
|
};
|
|
|
|
dmic-bus-clk2 {
|
|
samsung,pins = "gpv0-2";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0xaf>;
|
|
};
|
|
|
|
dmic-bus-clk2-idle {
|
|
samsung,pins = "gpv0-2";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0xb8>;
|
|
};
|
|
|
|
dmic-pdm0-bus {
|
|
samsung,pins = "gpv0-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0xac>;
|
|
};
|
|
|
|
amic-pdm0-bus {
|
|
samsung,pins = "gpv0-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0xb1>;
|
|
};
|
|
|
|
dmic-pdm0-idle {
|
|
samsung,pins = "gpv0-3";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0xb5>;
|
|
};
|
|
|
|
dmic-pdm1-bus {
|
|
samsung,pins = "gpv0-4";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0xae>;
|
|
};
|
|
|
|
amic-pdm1-bus {
|
|
samsung,pins = "gpv0-4";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0xb2>;
|
|
};
|
|
|
|
dmic-pdm1-idle {
|
|
samsung,pins = "gpv0-4";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0xb7>;
|
|
};
|
|
|
|
dmic-pdm2-bus {
|
|
samsung,pins = "gpv0-5";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0xb0>;
|
|
};
|
|
|
|
amic-pdm2-bus {
|
|
samsung,pins = "gpv0-5";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0xb3>;
|
|
};
|
|
|
|
dmic-pdm2-idle {
|
|
samsung,pins = "gpv0-5";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0xb9>;
|
|
};
|
|
};
|
|
|
|
aliases {
|
|
hsi2c0 = "/hsi2c@11D00000";
|
|
hsi2c1 = "/hsi2c@11D10000";
|
|
hsi2c2 = "/hsi2c@11D20000";
|
|
hsi2c3 = "/hsi2c@11D30000";
|
|
hsi2c4 = "/hsi2c@11D40000";
|
|
hsi2c5 = "/hsi2c@11D50000";
|
|
hsi2c6 = "/hsi2c@11D60000";
|
|
hsi2c7 = "/hsi2c@11D70000";
|
|
hsi2c8 = "/hsi2c@10500000";
|
|
hsi2c9 = "/hsi2c@10510000";
|
|
hsi2c10 = "/hsi2c@11DD0000";
|
|
hsi2c11 = "/hsi2c@11D80000";
|
|
hsi2c12 = "/hsi2c@11DE0000";
|
|
hsi2c13 = "/hsi2c@11D90000";
|
|
hsi2c14 = "/hsi2c@10900000";
|
|
hsi2c15 = "/hsi2c@10910000";
|
|
hsi2c16 = "/hsi2c@10920000";
|
|
hsi2c17 = "/hsi2c@10930000";
|
|
hsi2c18 = "/hsi2c@10940000";
|
|
hsi2c19 = "/hsi2c@10950000";
|
|
hsi2c20 = "/hsi2c@10960000";
|
|
hsi2c21 = "/hsi2c@10970000";
|
|
hsi2c22 = "/hsi2c@11DA0000";
|
|
hsi2c23 = "/hsi2c@11DB0000";
|
|
hsi2c24 = "/hsi2c@14F00000";
|
|
hsi2c25 = "/hsi2c@14F10000";
|
|
hsi2c26 = "/hsi2c@14F20000";
|
|
hsi2c27 = "/hsi2c@14F30000";
|
|
hsi2c28 = "/hsi2c@14F40000";
|
|
hsi2c29 = "/hsi2c@14F50000";
|
|
hsi2c30 = "/hsi2c@14F60000";
|
|
hsi2c31 = "/hsi2c@14F70000";
|
|
hsi2c32 = "/hsi2c@14F80000";
|
|
hsi2c33 = "/hsi2c@14F90000";
|
|
hsi2c34 = "/hsi2c@14FA0000";
|
|
hsi2c35 = "/hsi2c@14FB0000";
|
|
hsi2c36 = "/hsi2c@14FC0000";
|
|
hsi2c37 = "/hsi2c@14FD0000";
|
|
hsi2c38 = "/hsi2c@14FE0000";
|
|
spi0 = "/spi@11D00000";
|
|
spi1 = "/spi@11D20000";
|
|
spi2 = "/spi@11D40000";
|
|
spi3 = "/spi@11D60000";
|
|
spi4 = "/spi@10500000";
|
|
spi5 = "/spi@11DD0000";
|
|
spi6 = "/spi@11DE0000";
|
|
spi7 = "/spi@10900000";
|
|
spi8 = "/spi@10920000";
|
|
spi9 = "/spi@10940000";
|
|
spi10 = "/spi@10960000";
|
|
spi11 = "/spi@11DA0000";
|
|
spi12 = "/spi@14F00000";
|
|
spi13 = "/spi@14F20000";
|
|
spi14 = "/spi@14F40000";
|
|
spi15 = "/spi@14F60000";
|
|
spi16 = "/spi@14F80000";
|
|
spi17 = "/spi@14FA0000";
|
|
spi18 = "/spi@14FC0000";
|
|
uart0 = "/uart@11C40000";
|
|
uart1 = "/uart@10840000";
|
|
uart2 = "/uart@11D00000";
|
|
uart3 = "/uart@11D20000";
|
|
uart4 = "/uart@11D40000";
|
|
uart5 = "/uart@11D60000";
|
|
uart6 = "/uart@10500000";
|
|
uart7 = "/uart@11DD0000";
|
|
uart8 = "/uart@11DE0000";
|
|
uart9 = "/uart@10900000";
|
|
uart10 = "/uart@10920000";
|
|
uart11 = "/uart@10940000";
|
|
uart12 = "/uart@10960000";
|
|
uart13 = "/uart@11DA0000";
|
|
uart14 = "/uart@14F00000";
|
|
uart15 = "/uart@14F20000";
|
|
uart16 = "/uart@14F40000";
|
|
uart17 = "/uart@14F60000";
|
|
uart18 = "/uart@14F80000";
|
|
uart19 = "/uart@14FA0000";
|
|
uart20 = "/uart@14FC0000";
|
|
usi0 = "/usi@11C22000";
|
|
usi1 = "/usi@11C22004";
|
|
usi2 = "/usi@11C22008";
|
|
usi3 = "/usi@11C2200C";
|
|
usi4 = "/usi@11C22010";
|
|
usi5 = "/usi@11C22014";
|
|
usi6 = "/usi@10421000";
|
|
usi7 = "/usi@11C2117C";
|
|
usi8 = "/usi@11C21180";
|
|
usi9 = "/usi@10722030";
|
|
usi10 = "/usi@10722034";
|
|
usi11 = "/usi@10722038";
|
|
usi12 = "/usi@1072203c";
|
|
usi13 = "/usi@10722040";
|
|
usi14 = "/usi@10722048";
|
|
usi15 = "/usi@11C211D3";
|
|
usi16 = "/usi@14E22000";
|
|
usi17 = "/usi@14E22070";
|
|
usi18 = "/usi@14E22010";
|
|
usi19 = "/usi@14E22074";
|
|
usi20 = "/usi@14E22020";
|
|
usi21 = "/usi@14E22030";
|
|
usi22 = "/usi@14E22040";
|
|
usi23 = "/usi@14E22050";
|
|
usi24 = "/usi@14E22060";
|
|
i3c0 = "/i3c@10460000";
|
|
i3c1 = "/i3c@10470000";
|
|
i3c2 = "/i3c@10480000";
|
|
i3c3_ois = "/i3c@11DC0000";
|
|
i3c4 = "/i3c@11C80000";
|
|
i3c5 = "/i3c@11C90000";
|
|
i3c6 = "/i3c@11CA0000";
|
|
i3c7 = "/i3c@11CB0000";
|
|
i3c8 = "/i3c@11CC0000";
|
|
i3c9 = "/i3c@11CD0000";
|
|
i3c10 = "/i3c@11CE0000";
|
|
i3c11 = "/i3c@11CF0000";
|
|
dsimfc0 = "/fcmd@0x19CBC000";
|
|
dsimfc1 = "/fcmd@0x19CBD000";
|
|
dsimfc2 = "/fcmd@0x1AEBC000";
|
|
drmdsim0 = "/drmdsim@0x19EC0000";
|
|
drmdp = "/drmdp@0x10A80000";
|
|
smfc0 = "/smfc@18940000";
|
|
smfc1 = "/smfc@18950000";
|
|
scaler0 = "/scaler@18960000";
|
|
iommu-group-module0 = "/is_iommu_group_module";
|
|
iommu-group0 = "/is_iommu_group0";
|
|
iommu-group1 = "/is_iommu_group1";
|
|
iommu-group2 = "/is_iommu_group2";
|
|
iommu-group3 = "/is_iommu_group3";
|
|
wdma-module0 = "/camif-wdma-module@17140000";
|
|
wdma0 = "/camif-wdma@17141000";
|
|
wdma1 = "/camif-wdma@17142000";
|
|
wdma2 = "/camif-wdma@17143000";
|
|
wdma3 = "/camif-wdma@17144000";
|
|
wdma4 = "/camif-wdma@17145000";
|
|
pdp0 = "/sensor-paf-pdp@17100000";
|
|
pdp1 = "/sensor-paf-pdp@17110000";
|
|
pdp2 = "/sensor-paf-pdp@17120000";
|
|
pdp3 = "/sensor-paf-pdp@17130000";
|
|
pinctrl0 = "/pinctrl@15850000";
|
|
pinctrl1 = "/pinctrl@14E30000";
|
|
pinctrl2 = "/pinctrl@11240000";
|
|
pinctrl3 = "/pinctrl@11040000";
|
|
pinctrl4 = "/pinctrl@11060000";
|
|
pinctrl5 = "/pinctrl@10430000";
|
|
pinctrl6 = "/pinctrl@10730000";
|
|
pinctrl7 = "/pinctrl@11C30000";
|
|
pinctrl8 = "/pinctrl@15320000";
|
|
contexthub0 = "/contexthub";
|
|
};
|
|
|
|
syscon@10421000 {
|
|
compatible = "samsung,exynos2100-sysreg-peri\0syscon";
|
|
reg = <0x00 0x10421000 0x100>;
|
|
phandle = <0x25>;
|
|
};
|
|
|
|
syscon@10722000 {
|
|
compatible = "samsung,exynos2100-sysreg-peri\0syscon";
|
|
reg = <0x00 0x10722000 0x100>;
|
|
phandle = <0x30>;
|
|
};
|
|
|
|
syscon@11C21000 {
|
|
compatible = "samsung,exynos2100-sysreg-peri\0syscon";
|
|
reg = <0x00 0x11c21000 0x100>;
|
|
phandle = <0x29>;
|
|
};
|
|
|
|
syscon@11C22000 {
|
|
compatible = "samsung,exynos2100-sysreg-peri\0syscon";
|
|
reg = <0x00 0x11c22000 0x100>;
|
|
phandle = <0x17>;
|
|
};
|
|
|
|
syscon@14E22000 {
|
|
compatible = "samsung,exynos2100-sysreg-cmgp\0syscon";
|
|
reg = <0x00 0x14e22000 0x100>;
|
|
phandle = <0x40>;
|
|
};
|
|
|
|
syscon@1A42102C {
|
|
compatible = "syscon";
|
|
reg = <0x00 0x1a42102c 0x04>;
|
|
phandle = <0x61>;
|
|
};
|
|
|
|
usi@11C22000 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x11c22000 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x215>;
|
|
};
|
|
|
|
usi@11C22004 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x11c22004 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x216>;
|
|
};
|
|
|
|
usi@11C22008 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x11c22008 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x217>;
|
|
};
|
|
|
|
usi@11C2200C {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x11c2200c 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x218>;
|
|
};
|
|
|
|
usi@11C22010 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x11c22010 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x219>;
|
|
};
|
|
|
|
usi@11C22014 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x11c22014 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x21a>;
|
|
};
|
|
|
|
usi@10421000 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x10421000 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x21b>;
|
|
};
|
|
|
|
usi@11C2117C {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x11c2117c 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x21c>;
|
|
};
|
|
|
|
usi@11C21180 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x11c21180 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x21d>;
|
|
};
|
|
|
|
usi@10722030 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x10722030 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x21e>;
|
|
};
|
|
|
|
usi@10722034 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x10723034 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x21f>;
|
|
};
|
|
|
|
usi@10722038 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x10722038 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x220>;
|
|
};
|
|
|
|
usi@1072203c {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x1072203c 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x221>;
|
|
};
|
|
|
|
usi@10722040 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x10722040 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x222>;
|
|
};
|
|
|
|
usi@10722048 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x10722048 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x223>;
|
|
};
|
|
|
|
usi@11C211D3 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x11c211d3 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x224>;
|
|
};
|
|
|
|
usi@14E22000 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x14e22000 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x225>;
|
|
};
|
|
|
|
usi@14E22070 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x14e22070 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x226>;
|
|
};
|
|
|
|
usi@14E22010 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x14e22010 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x227>;
|
|
};
|
|
|
|
usi@14E22074 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x14e22074 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x228>;
|
|
};
|
|
|
|
usi@14E22020 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x14e22020 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x229>;
|
|
};
|
|
|
|
usi@14E22030 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x14e22030 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x22a>;
|
|
};
|
|
|
|
usi@14E22040 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x14e22040 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x22b>;
|
|
};
|
|
|
|
usi@14E22050 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x14e22050 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x22c>;
|
|
};
|
|
|
|
usi@14E22060 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x14e22060 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x22d>;
|
|
};
|
|
|
|
hsi2c@11D00000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2c0 0x04>;
|
|
samsung,usi-phandle = <0x17>;
|
|
samsung,usi-offset = <0x00>;
|
|
reg = <0x00 0x11d00000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x18>;
|
|
clocks = <0x19 0x76f 0x19 0x76c>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x1a 0x00 0x01>;
|
|
gpio_sda = <0x1a 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x22e>;
|
|
};
|
|
|
|
hsi2c@11D10000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2bf 0x04>;
|
|
samsung,usi-phandle = <0x17>;
|
|
samsung,usi-offset = <0x04>;
|
|
reg = <0x00 0x11d10000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x1b>;
|
|
clocks = <0x19 0x777 0x19 0x76c>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x1a 0x02 0x01>;
|
|
gpio_sda = <0x1a 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x22f>;
|
|
};
|
|
|
|
hsi2c@11D20000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2c2 0x04>;
|
|
samsung,usi-phandle = <0x17>;
|
|
samsung,usi-offset = <0x08>;
|
|
reg = <0x00 0x11d20000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x1c>;
|
|
clocks = <0x19 0x770 0x19 0x76c>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x1d 0x00 0x01>;
|
|
gpio_sda = <0x1d 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x230>;
|
|
};
|
|
|
|
hsi2c@11D30000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2c1 0x04>;
|
|
samsung,usi-phandle = <0x17>;
|
|
samsung,usi-offset = <0x0c>;
|
|
reg = <0x00 0x11d30000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x1e>;
|
|
clocks = <0x19 0x778 0x19 0x76c>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x1d 0x02 0x01>;
|
|
gpio_sda = <0x1d 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x231>;
|
|
};
|
|
|
|
hsi2c@11D40000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2c4 0x04>;
|
|
samsung,usi-phandle = <0x17>;
|
|
samsung,usi-offset = <0x10>;
|
|
reg = <0x00 0x11d40000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x1f>;
|
|
clocks = <0x19 0x771 0x19 0x76c>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x20 0x00 0x01>;
|
|
gpio_sda = <0x20 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x232>;
|
|
};
|
|
|
|
hsi2c@11D50000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2c3 0x04>;
|
|
samsung,usi-phandle = <0x17>;
|
|
samsung,usi-offset = <0x14>;
|
|
reg = <0x00 0x11d50000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x21>;
|
|
clocks = <0x19 0x76e 0x19 0x76c>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x20 0x02 0x01>;
|
|
gpio_sda = <0x20 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x233>;
|
|
};
|
|
|
|
hsi2c@11D60000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2c6 0x04>;
|
|
samsung,usi-phandle = <0x17>;
|
|
samsung,usi-offset = <0x18>;
|
|
reg = <0x00 0x11d60000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x22>;
|
|
clocks = <0x19 0x772 0x19 0x76c>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x23 0x00 0x01>;
|
|
gpio_sda = <0x23 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x234>;
|
|
};
|
|
|
|
hsi2c@11D70000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2c5 0x04>;
|
|
samsung,usi-phandle = <0x17>;
|
|
samsung,usi-offset = <0x1c>;
|
|
reg = <0x00 0x11d70000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x24>;
|
|
clocks = <0x19 0x76e 0x19 0x76c>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x23 0x02 0x01>;
|
|
gpio_sda = <0x23 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x235>;
|
|
};
|
|
|
|
hsi2c@10500000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2a1 0x04>;
|
|
samsung,usi-phandle = <0x25>;
|
|
samsung,usi-offset = <0x24>;
|
|
reg = <0x00 0x10500000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x26>;
|
|
clocks = <0x19 0x6a5 0x19 0x6a4>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x27 0x00 0x01>;
|
|
gpio_sda = <0x27 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x236>;
|
|
};
|
|
|
|
hsi2c@10510000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2a0 0x04>;
|
|
samsung,usi-phandle = <0x25>;
|
|
samsung,usi-offset = <0x28>;
|
|
reg = <0x00 0x10510000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x28>;
|
|
clocks = <0x19 0x6a6 0x19 0x6a4>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x27 0x02 0x01>;
|
|
gpio_sda = <0x27 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x237>;
|
|
};
|
|
|
|
hsi2c@11DD0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x21a 0x04>;
|
|
samsung,usi-phandle = <0x29>;
|
|
samsung,usi-offset = <0x17c>;
|
|
reg = <0x00 0x11dd0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x2a>;
|
|
clocks = <0x19 0x773 0x19 0x76c>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x2b 0x00 0x01>;
|
|
gpio_sda = <0x2b 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x238>;
|
|
};
|
|
|
|
hsi2c@11D80000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2c7 0x04>;
|
|
samsung,usi-phandle = <0x29>;
|
|
samsung,usi-offset = <0x2c>;
|
|
reg = <0x00 0x11d80000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x2c>;
|
|
clocks = <0x19 0x76e 0x19 0x76c>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x2b 0x02 0x01>;
|
|
gpio_sda = <0x2b 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x239>;
|
|
};
|
|
|
|
hsi2c@11DE0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x21b 0x04>;
|
|
samsung,usi-phandle = <0x29>;
|
|
samsung,usi-offset = <0x180>;
|
|
reg = <0x00 0x11de0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x2d>;
|
|
clocks = <0x19 0x774 0x19 0x76c>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x2e 0x00 0x01>;
|
|
gpio_sda = <0x2e 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x23a>;
|
|
};
|
|
|
|
hsi2c@11D90000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2c9 0x04>;
|
|
samsung,usi-phandle = <0x29>;
|
|
samsung,usi-offset = <0x04>;
|
|
reg = <0x00 0x11d90000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x2f>;
|
|
clocks = <0x19 0x76e 0x19 0x76c>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x2e 0x02 0x01>;
|
|
gpio_sda = <0x2e 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x23b>;
|
|
};
|
|
|
|
hsi2c@10900000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2a8 0x04>;
|
|
samsung,usi-phandle = <0x30>;
|
|
samsung,usi-offset = <0x30>;
|
|
reg = <0x00 0x10900000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x31>;
|
|
clocks = <0x19 0x70b 0x19 0x708>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x32 0x00 0x01>;
|
|
gpio_sda = <0x32 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x23c>;
|
|
};
|
|
|
|
hsi2c@10910000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2a7 0x04>;
|
|
samsung,usi-phandle = <0x30>;
|
|
samsung,usi-offset = <0x34>;
|
|
reg = <0x00 0x10910000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x33>;
|
|
clocks = <0x19 0x70f 0x19 0x708>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x32 0x02 0x01>;
|
|
gpio_sda = <0x32 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x23d>;
|
|
};
|
|
|
|
hsi2c@10920000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2aa 0x04>;
|
|
samsung,usi-phandle = <0x30>;
|
|
samsung,usi-offset = <0x38>;
|
|
reg = <0x00 0x10920000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x34>;
|
|
clocks = <0x19 0x70c 0x19 0x708>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x35 0x00 0x01>;
|
|
gpio_sda = <0x35 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x23e>;
|
|
};
|
|
|
|
hsi2c@10930000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2a9 0x04>;
|
|
samsung,usi-phandle = <0x30>;
|
|
samsung,usi-offset = <0x3c>;
|
|
reg = <0x00 0x10930000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x36>;
|
|
clocks = <0x19 0x710 0x19 0x708>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x35 0x02 0x01>;
|
|
gpio_sda = <0x35 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x23f>;
|
|
};
|
|
|
|
hsi2c@10940000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2ac 0x04>;
|
|
samsung,usi-phandle = <0x30>;
|
|
samsung,usi-offset = <0x40>;
|
|
reg = <0x00 0x10940000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x37>;
|
|
clocks = <0x19 0x70d 0x19 0x708>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x38 0x00 0x01>;
|
|
gpio_sda = <0x38 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x240>;
|
|
};
|
|
|
|
hsi2c@10950000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2ab 0x04>;
|
|
samsung,usi-phandle = <0x30>;
|
|
samsung,usi-offset = <0x44>;
|
|
reg = <0x00 0x10950000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x39>;
|
|
clocks = <0x19 0x70a 0x19 0x708>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x38 0x02 0x01>;
|
|
gpio_sda = <0x38 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x241>;
|
|
};
|
|
|
|
hsi2c@10960000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2ae 0x04>;
|
|
samsung,usi-phandle = <0x30>;
|
|
samsung,usi-offset = <0x48>;
|
|
reg = <0x00 0x10960000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x3a>;
|
|
clocks = <0x19 0x70e 0x19 0x708>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x3b 0x00 0x01>;
|
|
gpio_sda = <0x3b 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x242>;
|
|
};
|
|
|
|
hsi2c@10970000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2ad 0x04>;
|
|
samsung,usi-phandle = <0x30>;
|
|
samsung,usi-offset = <0x4c>;
|
|
reg = <0x00 0x10970000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x3c>;
|
|
clocks = <0x19 0x70a 0x19 0x708>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x3b 0x02 0x01>;
|
|
gpio_sda = <0x3b 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x243>;
|
|
};
|
|
|
|
hsi2c@11DA0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2cc 0x04>;
|
|
samsung,usi-phandle = <0x29>;
|
|
samsung,usi-offset = <0x58>;
|
|
reg = <0x00 0x11da0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x3d>;
|
|
clocks = <0x19 0x775 0x19 0x76c>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x3e 0x00 0x01>;
|
|
gpio_sda = <0x3e 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x244>;
|
|
};
|
|
|
|
hsi2c@11DB0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x2cb 0x04>;
|
|
samsung,usi-phandle = <0x29>;
|
|
samsung,usi-offset = <0x5c>;
|
|
reg = <0x00 0x11db0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x3f>;
|
|
clocks = <0x19 0x76e 0x19 0x76c>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x3e 0x02 0x01>;
|
|
gpio_sda = <0x3e 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x245>;
|
|
};
|
|
|
|
hsi2c@14F00000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xaf 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x00>;
|
|
reg = <0x00 0x14f00000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x41>;
|
|
clocks = <0x19 0x13d 0x19 0x134>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x42 0x00 0x01>;
|
|
gpio_sda = <0x42 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x246>;
|
|
};
|
|
|
|
hsi2c@14F10000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xad 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x70>;
|
|
reg = <0x00 0x14f10000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x43>;
|
|
clocks = <0x19 0x143 0x19 0x132>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x44 0x00 0x01>;
|
|
gpio_sda = <0x44 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x247>;
|
|
};
|
|
|
|
hsi2c@14F20000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xb0 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x10>;
|
|
reg = <0x00 0x14f20000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x45>;
|
|
clocks = <0x19 0x13c 0x19 0x135>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x46 0x00 0x01>;
|
|
gpio_sda = <0x46 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x248>;
|
|
};
|
|
|
|
hsi2c@14F30000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xae 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x74>;
|
|
reg = <0x00 0x14f30000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x47>;
|
|
clocks = <0x19 0x144 0x19 0x133>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x48 0x00 0x01>;
|
|
gpio_sda = <0x48 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x249>;
|
|
};
|
|
|
|
hsi2c@14F40000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xb1 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x20>;
|
|
reg = <0x00 0x14f40000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x49>;
|
|
clocks = <0x19 0x13e 0x19 0x136>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x4a 0x00 0x01>;
|
|
gpio_sda = <0x4a 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x24a>;
|
|
};
|
|
|
|
hsi2c@14F50000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xa7 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x24>;
|
|
reg = <0x00 0x14f50000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x4b>;
|
|
clocks = <0x19 0x142 0x19 0x12d>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x4c 0x00 0x01>;
|
|
gpio_sda = <0x4c 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x24b>;
|
|
};
|
|
|
|
hsi2c@14F60000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xb2 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x30>;
|
|
reg = <0x00 0x14f60000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x4d>;
|
|
clocks = <0x19 0x13f 0x19 0x137>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x4e 0x00 0x01>;
|
|
gpio_sda = <0x4e 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x24c>;
|
|
};
|
|
|
|
hsi2c@14F70000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xa8 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x34>;
|
|
reg = <0x00 0x14f70000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x4f>;
|
|
clocks = <0x19 0x142 0x19 0x12e>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x50 0x00 0x01>;
|
|
gpio_sda = <0x50 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x24d>;
|
|
};
|
|
|
|
hsi2c@14F80000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xb3 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x40>;
|
|
reg = <0x00 0x14f80000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x51>;
|
|
clocks = <0x19 0x13f 0x19 0x137>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x52 0x00 0x01>;
|
|
gpio_sda = <0x52 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x24e>;
|
|
};
|
|
|
|
hsi2c@14F90000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xa9 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x44>;
|
|
reg = <0x00 0x14f90000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x53>;
|
|
clocks = <0x19 0x142 0x19 0x12f>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x54 0x00 0x01>;
|
|
gpio_sda = <0x54 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x24f>;
|
|
};
|
|
|
|
hsi2c@14FA0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xb4 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x50>;
|
|
reg = <0x00 0x14fa0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x55>;
|
|
clocks = <0x19 0x140 0x19 0x139>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x56 0x00 0x01>;
|
|
gpio_sda = <0x56 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x250>;
|
|
};
|
|
|
|
hsi2c@14FB0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xaa 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x54>;
|
|
reg = <0x00 0x14fb0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x57>;
|
|
clocks = <0x19 0x142 0x19 0x130>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x58 0x00 0x01>;
|
|
gpio_sda = <0x58 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x251>;
|
|
};
|
|
|
|
hsi2c@14FC0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xb5 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x60>;
|
|
reg = <0x00 0x14fc0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x59>;
|
|
clocks = <0x19 0x141 0x19 0x13a>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x5a 0x00 0x01>;
|
|
gpio_sda = <0x5a 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x252>;
|
|
};
|
|
|
|
hsi2c@14FD0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xab 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x64>;
|
|
reg = <0x00 0x14fd0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x5b>;
|
|
clocks = <0x19 0x142 0x19 0x131>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x5c 0x00 0x01>;
|
|
gpio_sda = <0x5c 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x253>;
|
|
};
|
|
|
|
hsi2c@14FE0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x7f 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x80>;
|
|
reg = <0x00 0x14fe0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x5d>;
|
|
clocks = <0x19 0x142 0x19 0x12c>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x5e 0x00 0x01>;
|
|
gpio_sda = <0x5f 0x00 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x254>;
|
|
};
|
|
|
|
spi@11D00000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dmas = <0x60 0x01 0x60 0x00>;
|
|
dma-names = "tx\0rx";
|
|
samsung,dma-phandle = <0x61>;
|
|
samsung,dma-offset-tx = <0x01>;
|
|
samsung,dma-offset-rx = <0x00>;
|
|
samsung,dma-value = <0x01>;
|
|
interrupts = <0x00 0x2c0 0x04>;
|
|
samsung,usi-phandle = <0x17>;
|
|
samsung,usi-offset = <0x00>;
|
|
clocks = <0x19 0x76c 0x19 0x76f>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x62>;
|
|
reg = <0x00 0x11d00000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x255>;
|
|
};
|
|
|
|
spi@11D20000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dmas = <0x60 0x03 0x60 0x02>;
|
|
dma-names = "tx\0rx";
|
|
samsung,dma-phandle = <0x61>;
|
|
samsung,dma-offset-tx = <0x03>;
|
|
samsung,dma-offset-rx = <0x02>;
|
|
samsung,dma-value = <0x01>;
|
|
interrupts = <0x00 0x2c2 0x04>;
|
|
samsung,usi-phandle = <0x17>;
|
|
samsung,usi-offset = <0x08>;
|
|
clocks = <0x19 0x76c 0x19 0x770>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x63>;
|
|
reg = <0x00 0x11d20000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x256>;
|
|
};
|
|
|
|
spi@11D40000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x100>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dmas = <0x60 0x05 0x60 0x04>;
|
|
dma-names = "tx\0rx";
|
|
samsung,dma-phandle = <0x61>;
|
|
samsung,dma-offset-tx = <0x05>;
|
|
samsung,dma-offset-rx = <0x04>;
|
|
samsung,dma-value = <0x01>;
|
|
interrupts = <0x00 0x2c4 0x04>;
|
|
samsung,usi-phandle = <0x17>;
|
|
samsung,usi-offset = <0x10>;
|
|
clocks = <0x19 0x76c 0x19 0x771>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x64>;
|
|
reg = <0x00 0x11d40000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x257>;
|
|
};
|
|
|
|
spi@11D60000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x100>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dmas = <0x60 0x07 0x60 0x06>;
|
|
dma-names = "tx\0rx";
|
|
samsung,dma-phandle = <0x61>;
|
|
samsung,dma-offset-tx = <0x07>;
|
|
samsung,dma-offset-rx = <0x06>;
|
|
samsung,dma-value = <0x01>;
|
|
interrupts = <0x00 0x2c6 0x04>;
|
|
samsung,usi-phandle = <0x17>;
|
|
samsung,usi-offset = <0x18>;
|
|
clocks = <0x19 0x76c 0x19 0x772>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x65>;
|
|
reg = <0x00 0x11d60000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x258>;
|
|
};
|
|
|
|
spi@10500000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dmas = <0x60 0x09 0x60 0x08>;
|
|
dma-names = "tx\0rx";
|
|
samsung,dma-phandle = <0x61>;
|
|
samsung,dma-offset-tx = <0x09>;
|
|
samsung,dma-offset-rx = <0x08>;
|
|
samsung,dma-value = <0x01>;
|
|
interrupts = <0x00 0x2a1 0x04>;
|
|
samsung,usi-phandle = <0x25>;
|
|
samsung,usi-offset = <0x24>;
|
|
clocks = <0x19 0x6a4 0x19 0x6a5>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x66>;
|
|
reg = <0x00 0x10500000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x259>;
|
|
};
|
|
|
|
spi@11DD0000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x100>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dmas = <0x60 0x0b 0x60 0x0a>;
|
|
dma-names = "tx\0rx";
|
|
samsung,dma-phandle = <0x61>;
|
|
samsung,dma-offset-tx = <0x0b>;
|
|
samsung,dma-offset-rx = <0x0a>;
|
|
samsung,dma-value = <0x01>;
|
|
interrupts = <0x00 0x21a 0x04>;
|
|
samsung,usi-phandle = <0x29>;
|
|
samsung,usi-offset = <0x17c>;
|
|
clocks = <0x19 0x76c 0x19 0x773>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x67>;
|
|
reg = <0x00 0x11dd0000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x25a>;
|
|
};
|
|
|
|
spi@11DE0000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dmas = <0x60 0x0d 0x60 0x0c>;
|
|
dma-names = "tx\0rx";
|
|
samsung,dma-phandle = <0x61>;
|
|
samsung,dma-offset-tx = <0x0d>;
|
|
samsung,dma-offset-rx = <0x0c>;
|
|
samsung,dma-value = <0x01>;
|
|
interrupts = <0x00 0x21b 0x04>;
|
|
samsung,usi-phandle = <0x29>;
|
|
samsung,usi-offset = <0x180>;
|
|
clocks = <0x19 0x76c 0x19 0x774>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x68>;
|
|
reg = <0x00 0x11de0000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x25b>;
|
|
};
|
|
|
|
spi@10900000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dmas = <0x60 0x0f 0x60 0x0e>;
|
|
dma-names = "tx\0rx";
|
|
samsung,dma-phandle = <0x61>;
|
|
samsung,dma-offset-tx = <0x0f>;
|
|
samsung,dma-offset-rx = <0x0e>;
|
|
samsung,dma-value = <0x01>;
|
|
interrupts = <0x00 0x2a8 0x04>;
|
|
samsung,usi-phandle = <0x30>;
|
|
samsung,usi-offset = <0x30>;
|
|
clocks = <0x19 0x708 0x19 0x70b>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x69>;
|
|
reg = <0x00 0x10900000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x25c>;
|
|
};
|
|
|
|
spi@10920000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dmas = <0x60 0x11 0x60 0x10>;
|
|
dma-names = "tx\0rx";
|
|
samsung,dma-phandle = <0x61>;
|
|
samsung,dma-offset-tx = <0x11>;
|
|
samsung,dma-offset-rx = <0x10>;
|
|
samsung,dma-value = <0x01>;
|
|
interrupts = <0x00 0x2aa 0x04>;
|
|
samsung,usi-phandle = <0x30>;
|
|
samsung,usi-offset = <0x38>;
|
|
clocks = <0x19 0x708 0x19 0x70c>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x6a>;
|
|
reg = <0x00 0x10920000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x25d>;
|
|
};
|
|
|
|
spi@10940000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dmas = <0x60 0x13 0x60 0x12>;
|
|
dma-names = "tx\0rx";
|
|
samsung,dma-phandle = <0x61>;
|
|
samsung,dma-offset-tx = <0x13>;
|
|
samsung,dma-offset-rx = <0x12>;
|
|
samsung,dma-value = <0x01>;
|
|
interrupts = <0x00 0x2ac 0x04>;
|
|
samsung,usi-phandle = <0x30>;
|
|
samsung,usi-offset = <0x40>;
|
|
clocks = <0x19 0x708 0x19 0x70d>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x6b>;
|
|
reg = <0x00 0x10940000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x25e>;
|
|
};
|
|
|
|
spi@10960000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dmas = <0x60 0x15 0x60 0x14>;
|
|
dma-names = "tx\0rx";
|
|
samsung,dma-phandle = <0x61>;
|
|
samsung,dma-offset-tx = <0x15>;
|
|
samsung,dma-offset-rx = <0x14>;
|
|
samsung,dma-value = <0x01>;
|
|
interrupts = <0x00 0x2ae 0x04>;
|
|
samsung,usi-phandle = <0x30>;
|
|
samsung,usi-offset = <0x48>;
|
|
clocks = <0x19 0x708 0x19 0x70e>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x6c>;
|
|
reg = <0x00 0x10960000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x25f>;
|
|
};
|
|
|
|
spi@11DA0000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dmas = <0x60 0x17 0x60 0x16>;
|
|
dma-names = "tx\0rx";
|
|
samsung,dma-phandle = <0x61>;
|
|
samsung,dma-offset-tx = <0x17>;
|
|
samsung,dma-offset-rx = <0x16>;
|
|
samsung,dma-value = <0x01>;
|
|
interrupts = <0x00 0x2cc 0x04>;
|
|
samsung,usi-phandle = <0x29>;
|
|
samsung,usi-offset = <0x58>;
|
|
clocks = <0x19 0x76c 0x19 0x775>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x6d>;
|
|
reg = <0x00 0x11da0000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x260>;
|
|
};
|
|
|
|
spi@14F00000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xaf 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x00>;
|
|
clocks = <0x19 0x134 0x19 0x13d>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x6e>;
|
|
reg = <0x00 0x14f00000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x261>;
|
|
};
|
|
|
|
spi@14F20000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xb0 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x10>;
|
|
clocks = <0x19 0x135 0x19 0x13c>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x6f>;
|
|
reg = <0x00 0x14f20000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x262>;
|
|
};
|
|
|
|
spi@14F40000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xb1 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x20>;
|
|
clocks = <0x19 0x136 0x19 0x13e>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x70>;
|
|
reg = <0x00 0x14f40000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x263>;
|
|
};
|
|
|
|
spi@14F60000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xb2 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x30>;
|
|
clocks = <0x19 0x137 0x19 0x13f>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x71>;
|
|
reg = <0x00 0x14f60000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x264>;
|
|
};
|
|
|
|
spi@14F80000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xaf 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x40>;
|
|
clocks = <0x19 0x138 0x19 0x13b>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x72>;
|
|
reg = <0x00 0x14f80000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x265>;
|
|
};
|
|
|
|
spi@14FA0000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xb0 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x50>;
|
|
clocks = <0x19 0x139 0x19 0x140>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x73>;
|
|
reg = <0x00 0x14fa0000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x266>;
|
|
};
|
|
|
|
spi@14FC0000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0xb1 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x60>;
|
|
clocks = <0x19 0x13a 0x19 0x141>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x74>;
|
|
reg = <0x00 0x14fc0000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x267>;
|
|
};
|
|
|
|
uart@11C40000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x11c40000 0x100>;
|
|
samsung,fifo-size = <0x100>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0x2af 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x75>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x76c 0x19 0x776>;
|
|
clock-names = "gate_uart_clk0\0ipclk_uart0";
|
|
samsung,dbg-uart-ch;
|
|
samsung,dbg-uart-baud = <0x1c200>;
|
|
samsung,dbg-word-len = <0x08>;
|
|
samsung,source-clock-rate = <0xbebc200>;
|
|
status = "disabled";
|
|
phandle = <0x268>;
|
|
};
|
|
|
|
uart@10840000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x10840000 0x100>;
|
|
samsung,fifo-size = <0x100>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0x2a2 0x04>;
|
|
pinctrl-names = "default\0rts\0tx_dat";
|
|
pinctrl-0 = <0x76>;
|
|
pinctrl-1 = <0x77 0x78>;
|
|
pinctrl-2 = <0x79>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x708 0x19 0x709>;
|
|
clock-names = "gate_uart_clk1\0ipclk_uart1";
|
|
status = "disabled";
|
|
phandle = <0x269>;
|
|
};
|
|
|
|
uart@11D00000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x11d00000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0x2c0 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x7a>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x76c 0x19 0x76f>;
|
|
clock-names = "gate_uart_clk2\0ipclk_uart2";
|
|
samsung,usi-phandle = <0x17>;
|
|
samsung,usi-offset = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0x26a>;
|
|
};
|
|
|
|
uart@11D20000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x11d20000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0x2c2 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x7b>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x76c 0x19 0x770>;
|
|
clock-names = "gate_uart_clk3\0ipclk_uart3";
|
|
samsung,usi-phandle = <0x17>;
|
|
samsung,usi-offset = <0x08>;
|
|
status = "disabled";
|
|
phandle = <0x26b>;
|
|
};
|
|
|
|
uart@11D40000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x11d40000 0x100>;
|
|
samsung,fifo-size = <0x100>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0x2c4 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x7c>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x76c 0x19 0x771>;
|
|
clock-names = "gate_uart_clk4\0ipclk_uart4";
|
|
samsung,usi-phandle = <0x17>;
|
|
samsung,usi-offset = <0x10>;
|
|
status = "disabled";
|
|
phandle = <0x26c>;
|
|
};
|
|
|
|
uart@11D60000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x11d60000 0x100>;
|
|
samsung,fifo-size = <0x100>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0x2c6 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x7d>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x76c 0x19 0x772>;
|
|
clock-names = "gate_uart_clk5\0ipclk_uart5";
|
|
samsung,usi-phandle = <0x17>;
|
|
samsung,usi-offset = <0x18>;
|
|
status = "disabled";
|
|
phandle = <0x26d>;
|
|
};
|
|
|
|
uart@10500000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x10500000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0x2a1 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x7e>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x6a4 0x19 0x6a5>;
|
|
clock-names = "gate_uart_clk6\0ipclk_uart6";
|
|
samsung,usi-phandle = <0x25>;
|
|
samsung,usi-offset = <0x24>;
|
|
status = "disabled";
|
|
phandle = <0x26e>;
|
|
};
|
|
|
|
uart@11DD0000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x11dd0000 0x100>;
|
|
samsung,fifo-size = <0x100>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0x21a 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x7f>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x76c 0x19 0x773>;
|
|
clock-names = "gate_uart_clk7\0ipclk_uart7";
|
|
samsung,usi-phandle = <0x29>;
|
|
samsung,usi-offset = <0x17c>;
|
|
status = "disabled";
|
|
phandle = <0x26f>;
|
|
};
|
|
|
|
uart@11DE0000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x11de0000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0x21b 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x80>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x76c 0x19 0x774>;
|
|
clock-names = "gate_uart_clk8\0ipclk_uart8";
|
|
samsung,usi-phandle = <0x29>;
|
|
samsung,usi-offset = <0x180>;
|
|
status = "disabled";
|
|
phandle = <0x270>;
|
|
};
|
|
|
|
uart@10900000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x10900000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0x2a8 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x81>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x708 0x19 0x70b>;
|
|
clock-names = "gate_uart_clk9\0ipclk_uart9";
|
|
samsung,usi-phandle = <0x30>;
|
|
samsung,usi-offset = <0x30>;
|
|
status = "disabled";
|
|
phandle = <0x271>;
|
|
};
|
|
|
|
uart@10920000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x10920000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0x2aa 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x82>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x708 0x19 0x70c>;
|
|
clock-names = "gate_uart_clk10\0ipclk_uart10";
|
|
samsung,usi-phandle = <0x30>;
|
|
samsung,usi-offset = <0x38>;
|
|
status = "disabled";
|
|
phandle = <0x272>;
|
|
};
|
|
|
|
uart@10940000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x10940000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0x2ac 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x83>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x708 0x19 0x70d>;
|
|
clock-names = "gate_uart_clk11\0ipclk_uart11";
|
|
samsung,usi-phandle = <0x30>;
|
|
samsung,usi-offset = <0x40>;
|
|
status = "disabled";
|
|
phandle = <0x273>;
|
|
};
|
|
|
|
uart@10960000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x10960000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0x2ae 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x84>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x708 0x19 0x70e>;
|
|
clock-names = "gate_uart_clk12\0ipclk_uart12";
|
|
samsung,usi-phandle = <0x30>;
|
|
samsung,usi-offset = <0x48>;
|
|
status = "disabled";
|
|
phandle = <0x274>;
|
|
};
|
|
|
|
uart@11DA0000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x11da0000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0x2cc 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x85>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x76c 0x19 0x775>;
|
|
clock-names = "gate_uart_clk13\0ipclk_uart13";
|
|
samsung,usi-phandle = <0x29>;
|
|
samsung,usi-offset = <0x58>;
|
|
status = "disabled";
|
|
phandle = <0x275>;
|
|
};
|
|
|
|
uart@14F00000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x14f00000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0xaf 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x86>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x134 0x19 0x13d>;
|
|
clock-names = "gate_uart_clk14\0ipclk_uart14";
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0x276>;
|
|
};
|
|
|
|
uart@14F20000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x14f20000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0xb0 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x87>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x135 0x19 0x13c>;
|
|
clock-names = "gate_uart_clk15\0ipclk_uart15";
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x10>;
|
|
status = "disabled";
|
|
phandle = <0x277>;
|
|
};
|
|
|
|
uart@14F40000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x14f40000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0xb1 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x88>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x136 0x19 0x13e>;
|
|
clock-names = "gate_uart_clk16\0ipclk_uart16";
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x20>;
|
|
status = "disabled";
|
|
phandle = <0x278>;
|
|
};
|
|
|
|
uart@14F60000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x14f60000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0xb2 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x89>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x137 0x19 0x13f>;
|
|
clock-names = "gate_uart_clk17\0ipclk_uart17";
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x30>;
|
|
status = "disabled";
|
|
phandle = <0x279>;
|
|
};
|
|
|
|
uart@14F80000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x14f80000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0xaf 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x8a>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x138 0x19 0x13b>;
|
|
clock-names = "gate_uart_clk18\0ipclk_uart18";
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x40>;
|
|
status = "disabled";
|
|
phandle = <0x27a>;
|
|
};
|
|
|
|
uart@14FA0000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x14fa0000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0xb0 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x8b>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x139 0x19 0x140>;
|
|
clock-names = "gate_uart_clk19\0ipclk_uart19";
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x50>;
|
|
status = "disabled";
|
|
phandle = <0x27b>;
|
|
};
|
|
|
|
uart@14FC0000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x14fc0000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0xb1 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x8c>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x19 0x13a 0x19 0x141>;
|
|
clock-names = "gate_uart_clk20\0ipclk_uart20";
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x60>;
|
|
status = "disabled";
|
|
phandle = <0x27c>;
|
|
};
|
|
|
|
i3c@10460000 {
|
|
compatible = "samsung,exynos-i3c-hci";
|
|
reg = <0x00 0x10460000 0x10000>;
|
|
interrupts = <0x00 0x216 0x04>;
|
|
clocks = <0x19 0x708 0x19 0x70a>;
|
|
clock-names = "gate_clk\0ipclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x8d>;
|
|
status = "disabled";
|
|
phandle = <0x27d>;
|
|
};
|
|
|
|
i3c@10470000 {
|
|
compatible = "samsung,exynos-i3c-hci";
|
|
reg = <0x00 0x10470000 0x10000>;
|
|
interrupts = <0x00 0x217 0x04>;
|
|
clocks = <0x19 0x708 0x19 0x70a>;
|
|
clock-names = "gate_clk\0ipclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x8e>;
|
|
status = "disabled";
|
|
phandle = <0x27e>;
|
|
};
|
|
|
|
i3c@10480000 {
|
|
compatible = "samsung,exynos-i3c-hci";
|
|
reg = <0x00 0x10480000 0x10000>;
|
|
interrupts = <0x00 0x218 0x04>;
|
|
clocks = <0x19 0x708 0x19 0x70a>;
|
|
clock-names = "gate_clk\0ipclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x8f>;
|
|
status = "disabled";
|
|
phandle = <0x27f>;
|
|
};
|
|
|
|
i3c@11DC0000 {
|
|
compatible = "samsung,exynos-i3c-hci";
|
|
reg = <0x00 0x11dc0000 0x10000>;
|
|
interrupts = <0x00 0x219 0x04>;
|
|
clocks = <0x19 0x708 0x19 0x70a>;
|
|
clock-names = "gate_clk\0ipclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0xffffffff>;
|
|
status = "disabled";
|
|
phandle = <0x280>;
|
|
};
|
|
|
|
i3c@11C80000 {
|
|
compatible = "samsung,exynos-i3c-hci";
|
|
reg = <0x00 0x11c80000 0x10000>;
|
|
interrupts = <0x00 0x2b2 0x04>;
|
|
clocks = <0x19 0x708 0x19 0x70a>;
|
|
clock-names = "gate_clk\0ipclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x90>;
|
|
status = "disabled";
|
|
phandle = <0x281>;
|
|
};
|
|
|
|
i3c@11C90000 {
|
|
compatible = "samsung,exynos-i3c-hci";
|
|
reg = <0x00 0x11c90000 0x10000>;
|
|
interrupts = <0x00 0x2b3 0x04>;
|
|
clocks = <0x19 0x708 0x19 0x70a>;
|
|
clock-names = "gate_clk\0ipclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x91>;
|
|
status = "disabled";
|
|
phandle = <0x282>;
|
|
};
|
|
|
|
i3c@11CA0000 {
|
|
compatible = "samsung,exynos-i3c-hci";
|
|
reg = <0x00 0x11ca0000 0x10000>;
|
|
interrupts = <0x00 0x2b4 0x04>;
|
|
clocks = <0x19 0x76c 0x19 0x76e>;
|
|
clock-names = "gate_clk\0ipclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x92>;
|
|
status = "disabled";
|
|
phandle = <0x283>;
|
|
};
|
|
|
|
i3c@11CB0000 {
|
|
compatible = "samsung,exynos-i3c-hci";
|
|
reg = <0x00 0x11cb0000 0x10000>;
|
|
interrupts = <0x00 0x2b5 0x04>;
|
|
clocks = <0x19 0x76c 0x19 0x76e>;
|
|
clock-names = "gate_clk\0ipclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x93>;
|
|
status = "disabled";
|
|
phandle = <0x284>;
|
|
};
|
|
|
|
i3c@11CC0000 {
|
|
compatible = "samsung,exynos-i3c-hci";
|
|
reg = <0x00 0x11cc0000 0x10000>;
|
|
interrupts = <0x00 0x2b6 0x04>;
|
|
clocks = <0x19 0x76c 0x19 0x76e>;
|
|
clock-names = "gate_clk\0ipclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x94>;
|
|
status = "disabled";
|
|
phandle = <0x285>;
|
|
};
|
|
|
|
i3c@11CD0000 {
|
|
compatible = "samsung,exynos-i3c-hci";
|
|
reg = <0x00 0x11cd0000 0x10000>;
|
|
interrupts = <0x00 0x2b7 0x04>;
|
|
clocks = <0x19 0x76c 0x19 0x76e>;
|
|
clock-names = "gate_clk\0ipclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x95>;
|
|
status = "disabled";
|
|
phandle = <0x286>;
|
|
};
|
|
|
|
i3c@11CE0000 {
|
|
compatible = "samsung,exynos-i3c-hci";
|
|
reg = <0x00 0x11ce0000 0x10000>;
|
|
interrupts = <0x00 0x2b8 0x04>;
|
|
clocks = <0x19 0x76c 0x19 0x76e>;
|
|
clock-names = "gate_clk\0ipclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x96>;
|
|
status = "disabled";
|
|
phandle = <0x287>;
|
|
};
|
|
|
|
i3c@11CF0000 {
|
|
compatible = "samsung,exynos-i3c-hci";
|
|
reg = <0x00 0x11cf0000 0x10000>;
|
|
interrupts = <0x00 0x2b9 0x04>;
|
|
clocks = <0x19 0x76c 0x19 0x76e>;
|
|
clock-names = "gate_clk\0ipclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x97>;
|
|
status = "disabled";
|
|
phandle = <0x288>;
|
|
};
|
|
|
|
sgpu@16E00000 {
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
#cooling-cells = <0x02>;
|
|
compatible = "samsung-sgpu,samsung-sgpu";
|
|
reg = <0x00 0x16e00000 0x100000 0x00 0x16f00000 0x100000 0x00 0x16dc0000 0x40000 0x00 0x16cd0000 0x10000 0x00 0x16c00000 0x2000>;
|
|
interrupts = <0x00 0x1d3 0x04>;
|
|
interrupt-names = "SGPU";
|
|
memory-region = <0x98>;
|
|
flags = <0x1e>;
|
|
g3d_cmu_cal_id = <0xb04000d>;
|
|
min_freq = <0x49f98>;
|
|
max_freq = <0x13ed90>;
|
|
samsung,imgloader-s2mpu-support;
|
|
dma-coherent;
|
|
power-domains = <0x99>;
|
|
mif_min_lock = "421000 404000:1352000 500000:1716000 807000:2288000 903000:2535000 999000:2730000 1095000:3172000";
|
|
mif_cl_boost_min_lock = "421000 404000:1014000 605000:1352000 807000:1539000 903000:1716000 999000:2028000";
|
|
mo_scenario = "default 404000:g3d_performance";
|
|
llc_ways = "0 605000:16";
|
|
gpu_power_coeff = <0x271>;
|
|
ect-coeff-index = <0x03>;
|
|
gpu_tmu = <0x9a>;
|
|
phandle = <0x11c>;
|
|
|
|
gpu_smntarg {
|
|
reg = <0x00 0x16e00000 0x100000>;
|
|
device_type = "gpu_smntarg";
|
|
};
|
|
|
|
gpu_doorbell {
|
|
reg = <0x00 0x16f00000 0x100000>;
|
|
device_type = "gpu_doorbell";
|
|
};
|
|
|
|
gpu_debug {
|
|
reg = <0x00 0x16dc0000 0x40000>;
|
|
device_type = "gpu_debug";
|
|
};
|
|
|
|
gpu_pm {
|
|
reg = <0x00 0x16cd0000 0x10000>;
|
|
device_type = "gpu_pm";
|
|
};
|
|
|
|
gpu_sysreg {
|
|
reg = <0x00 0x16c00000 0x2000>;
|
|
device_type = "gpu_sysreg";
|
|
};
|
|
};
|
|
|
|
acpm {
|
|
compatible = "samsung,exynos-acpm";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
acpm-ipc-channel = <0x04>;
|
|
use-plugin-library;
|
|
fvmap_offset = <0x44400>;
|
|
reg = <0x00 0x15830000 0x1000>;
|
|
reg-names = "timer_apm";
|
|
peritimer-cnt = <0xffff>;
|
|
};
|
|
|
|
acpm_ipc {
|
|
compatible = "samsung,exynos-acpm-ipc";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
interrupts = <0x00 0x29 0x04>;
|
|
reg = <0x00 0x15900000 0x1000 0x00 0x2060000 0x50000>;
|
|
initdata-base = <0xf800>;
|
|
num-timestamps = <0x20>;
|
|
debug-log-level = <0x00>;
|
|
logging-period = <0x1f4>;
|
|
dump-base = <0x2064000>;
|
|
dump-size = <0x4c000>;
|
|
dram-dump-base = <0x90014000>;
|
|
board-id = <0x10>;
|
|
board-rev = <0x00>;
|
|
interrupt-ch = <0x00>;
|
|
nfc-log-offset = <0x43760>;
|
|
nfc-log-len = <0x10>;
|
|
};
|
|
|
|
acpm_mfd_bus@15960000 {
|
|
compatible = "samsung,exynos-acpm-mfd-bus";
|
|
status = "okay";
|
|
phandle = <0x289>;
|
|
};
|
|
|
|
acpm_mfd_bus@15961000 {
|
|
compatible = "samsung,exynos-acpm-mfd-bus";
|
|
status = "okay";
|
|
phandle = <0x28a>;
|
|
};
|
|
|
|
acpm_mfd_bus@15962000 {
|
|
compatible = "samsung,exynos-acpm-mfd-bus";
|
|
status = "okay";
|
|
phandle = <0x28b>;
|
|
};
|
|
|
|
dmc_plugin {
|
|
compatible = "samsung,exynos-acpm-plg-dbg";
|
|
acpm-ipc-channel = <0x0a>;
|
|
};
|
|
|
|
abox-gic@18cf0000 {
|
|
compatible = "samsung,abox-gic";
|
|
reg = <0x00 0x18cf1000 0x1000 0x00 0x18cf2000 0x1004>;
|
|
reg-names = "gicd\0gicc";
|
|
interrupts = <0x00 0x4a 0x04>;
|
|
phandle = <0x9e>;
|
|
};
|
|
|
|
abox@18c50000 {
|
|
compatible = "samsung,abox";
|
|
reg = <0x00 0x18c50000 0x40000 0x00 0x18c10000 0x10000 0x00 0x2100000 0x40000 0x00 0x18ce0000 0x10000 0x00 0x14c90000 0x1000 0x00 0x1a320000 0x1000>;
|
|
reg-names = "sfr\0sysreg\0sram\0timer\0mailbox_apm\0cmu_top";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
iommus = <0x9b>;
|
|
memory-region = <0x9c>;
|
|
samsung,iommu-group = <0x9d>;
|
|
power-domains = <0x02>;
|
|
clocks = <0x19 0x8ab 0x19 0x8aa 0x19 0x8a0 0x19 0xe2 0x19 0xe3 0x19 0xd3 0x19 0xdb 0x19 0xd2>;
|
|
clock-names = "pll\0pll1\0audif\0bus\0cnt\0sclk\0cp_pcmc\0aud_pcmc";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX";
|
|
samsung,quirks = "try to asrc off\0silent reset";
|
|
samsung,ipc-tx-area = <0x01 0x850000 0x18000>;
|
|
samsung,ipc-rx-area = <0x01 0x868000 0x18000>;
|
|
samsung,shm-area = <0x01 0x8bc000 0x4000>;
|
|
samsung,handshake-area = <0x00 0x292e0 0x20>;
|
|
samsung,abox-slogargs-offset = <0x295f8>;
|
|
samsung,abox-gic = <0x9e>;
|
|
samsung,uaif-max-div = <0x200>;
|
|
samsung,atune-count = <0x01>;
|
|
samsung,pm-qos-int = <0x00 0x00 0x00 0x00 0x00>;
|
|
samsung,pm-qos-aud = <0x127690 0xf3e58 0xc3500 0xaae60 0xa1dd8 0x82208 0x61a80 0x510e0 0x30d40>;
|
|
samsung,pm-qos-stable-min = <0x30d40>;
|
|
samsung,sys_acp_con = <0x404 0x10000>;
|
|
samsung,abox-llc-way = <0x04 0x04 0x00 0x00>;
|
|
phandle = <0x28c>;
|
|
|
|
abox-core@18c55000 {
|
|
compatible = "samsung,abox-core";
|
|
reg = <0x00 0x18c55000 0x80>;
|
|
reg-names = "gpr";
|
|
samsung,id = <0x00>;
|
|
samsung,type = "CA32";
|
|
samsung,pmu_power = <0x36c0 0x01>;
|
|
samsung,sys_standby = <0x400 0x10000000>;
|
|
phandle = <0x28d>;
|
|
|
|
abox-firmware-sram0 {
|
|
samsung,name = "calliope_sram.bin";
|
|
samsung,area = <0x00>;
|
|
samsung,offset = <0x00>;
|
|
samsung,fw-signed;
|
|
samsung,fw-id = <0x00>;
|
|
phandle = <0x28e>;
|
|
};
|
|
|
|
abox-firmware-dram0 {
|
|
samsung,name = "calliope_dram.bin";
|
|
samsung,area = <0x01>;
|
|
samsung,offset = <0x00>;
|
|
phandle = <0x28f>;
|
|
};
|
|
};
|
|
|
|
abox-core@18c55080 {
|
|
compatible = "samsung,abox-core";
|
|
reg = <0x00 0x18c55080 0x80>;
|
|
reg-names = "gpr";
|
|
samsung,id = <0x01>;
|
|
samsung,type = "CA32";
|
|
samsung,pmu_power = <0x3700 0x01>;
|
|
samsung,sys_standby = <0x400 0x20000000>;
|
|
phandle = <0x290>;
|
|
};
|
|
|
|
abox-core@18c55100 {
|
|
compatible = "samsung,abox-core";
|
|
reg = <0x00 0x18c55100 0x80 0x00 0x18c55200 0x04>;
|
|
reg-names = "gpr\0status";
|
|
samsung,id = <0x02>;
|
|
samsung,type = "CA32";
|
|
samsung,pmu_power = <0x3880 0x01>;
|
|
samsung,sys_standby = <0x400 0x40080000>;
|
|
phandle = <0x291>;
|
|
};
|
|
|
|
abox-rdma@18c51000 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51000 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x00>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA0";
|
|
phandle = <0x292>;
|
|
};
|
|
|
|
abox-rdma@18c51100 {
|
|
compatible = "samsung,abox-rdma-compr";
|
|
reg = <0x00 0x18c51100 0x100 0x00 0x2129600 0x70>;
|
|
reg-names = "sfr\0mailbox";
|
|
memory-region = <0x9f>;
|
|
samsung,id = <0x01>;
|
|
samsung,type = "compress";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX ComprTx0";
|
|
phandle = <0x293>;
|
|
};
|
|
|
|
abox-rdma@18c51200 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51200 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x02>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "ion";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA2";
|
|
phandle = <0x294>;
|
|
};
|
|
|
|
abox-rdma@18c51300 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51300 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x03>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
samsung,asrc-id = <0x07>;
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA3";
|
|
phandle = <0x295>;
|
|
};
|
|
|
|
abox-rdma@18c51400 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51400 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x04>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA4";
|
|
phandle = <0x296>;
|
|
};
|
|
|
|
abox-rdma@18c51500 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51500 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x05>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA5";
|
|
phandle = <0x297>;
|
|
};
|
|
|
|
abox-rdma@18c51600 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51600 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x06>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA6";
|
|
phandle = <0x298>;
|
|
};
|
|
|
|
abox-rdma@18c51700 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51700 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x07>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA7";
|
|
phandle = <0x299>;
|
|
};
|
|
|
|
abox-rdma@18c51800 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51800 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x08>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA8";
|
|
phandle = <0x29a>;
|
|
};
|
|
|
|
abox-rdma@18c51900 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51900 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x09>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA9";
|
|
phandle = <0x29b>;
|
|
};
|
|
|
|
abox-rdma@18c51a00 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51a00 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x0a>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA10";
|
|
phandle = <0x29c>;
|
|
};
|
|
|
|
abox-rdma@18c51b00 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51b00 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x0b>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA11";
|
|
phandle = <0x29d>;
|
|
};
|
|
|
|
abox-wdma@18c53000 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53000 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x00>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA0";
|
|
phandle = <0x29e>;
|
|
};
|
|
|
|
abox-wdma@18c53100 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53100 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x01>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "ion";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA1";
|
|
phandle = <0x29f>;
|
|
};
|
|
|
|
abox-wdma@18c53200 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53200 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x02>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA2";
|
|
phandle = <0x2a0>;
|
|
};
|
|
|
|
abox-wdma@18c53300 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53300 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x03>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA3";
|
|
phandle = <0x2a1>;
|
|
};
|
|
|
|
abox-wdma@18c53400 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53400 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x04>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA4";
|
|
phandle = <0x2a2>;
|
|
};
|
|
|
|
abox-wdma@18c53500 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53500 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x05>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA5";
|
|
phandle = <0x2a3>;
|
|
};
|
|
|
|
abox-wdma@18c53600 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53600 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x06>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "ion";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA6";
|
|
phandle = <0x2a4>;
|
|
};
|
|
|
|
abox-wdma@18c53700 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53700 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x07>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA7";
|
|
phandle = <0x2a5>;
|
|
};
|
|
|
|
abox-wdma@18c53800 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53800 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x08>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA8";
|
|
phandle = <0x2a6>;
|
|
};
|
|
|
|
abox-wdma@18c53900 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53900 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x09>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA9";
|
|
phandle = <0x2a7>;
|
|
};
|
|
|
|
abox-wdma@18c53a00 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53a00 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x0a>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA10";
|
|
phandle = <0x2a8>;
|
|
};
|
|
|
|
abox-wdma@18c53b00 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53b00 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x0b>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA11";
|
|
phandle = <0x2a9>;
|
|
};
|
|
|
|
abox-dual@18c53080 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53080 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x00>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA0 DUAL";
|
|
phandle = <0x2aa>;
|
|
};
|
|
|
|
abox-dual@18c53180 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53180 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x01>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA1 DUAL";
|
|
phandle = <0x2ab>;
|
|
};
|
|
|
|
abox-dual@18c53280 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53280 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x02>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA2 DUAL";
|
|
phandle = <0x2ac>;
|
|
};
|
|
|
|
abox-dual@18c53380 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53380 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x03>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA3 DUAL";
|
|
phandle = <0x2ad>;
|
|
};
|
|
|
|
abox-dual@18c53480 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53480 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x04>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA4 DUAL";
|
|
phandle = <0x2ae>;
|
|
};
|
|
|
|
abox-dual@18c53580 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53580 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x05>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA5 DUAL";
|
|
phandle = <0x2af>;
|
|
};
|
|
|
|
abox-dual@18c53680 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53680 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x06>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA6 DUAL";
|
|
phandle = <0x2b0>;
|
|
};
|
|
|
|
abox-dual@18c53780 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53780 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x07>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA7 DUAL";
|
|
phandle = <0x2b1>;
|
|
};
|
|
|
|
abox-dual@18c53880 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53880 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x08>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA8 DUAL";
|
|
phandle = <0x2b2>;
|
|
};
|
|
|
|
abox-dual@18c53980 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53980 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x09>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA9 DUAL";
|
|
phandle = <0x2b3>;
|
|
};
|
|
|
|
abox-dual@18c53a80 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53a80 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x0a>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA10 DUAL";
|
|
phandle = <0x2b4>;
|
|
};
|
|
|
|
abox-dual@18c53b80 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53b80 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x0b>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA11 DUAL";
|
|
phandle = <0x2b5>;
|
|
};
|
|
|
|
abox-ddma@18c56000 {
|
|
compatible = "samsung,abox-ddma";
|
|
reg = <0x00 0x18c56000 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x00>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX DBG0";
|
|
phandle = <0x2b6>;
|
|
};
|
|
|
|
abox-ddma@18c56100 {
|
|
compatible = "samsung,abox-ddma";
|
|
reg = <0x00 0x18c56100 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x01>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX DBG1";
|
|
phandle = <0x2b7>;
|
|
};
|
|
|
|
abox-ddma@18c56200 {
|
|
compatible = "samsung,abox-ddma";
|
|
reg = <0x00 0x18c56200 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x02>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX DBG2";
|
|
phandle = <0x2b8>;
|
|
};
|
|
|
|
abox-ddma@18c56300 {
|
|
compatible = "samsung,abox-ddma";
|
|
reg = <0x00 0x18c56300 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x03>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX DBG3";
|
|
phandle = <0x2b9>;
|
|
};
|
|
|
|
abox-ddma@18c56400 {
|
|
compatible = "samsung,abox-ddma";
|
|
reg = <0x00 0x18c56400 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x04>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX DBG4";
|
|
phandle = <0x2ba>;
|
|
};
|
|
|
|
abox-ddma@18c56500 {
|
|
compatible = "samsung,abox-ddma";
|
|
reg = <0x00 0x18c56500 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x05>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX DBG5";
|
|
phandle = <0x2bb>;
|
|
};
|
|
|
|
abox-uaif@18c50c00 {
|
|
compatible = "samsung,abox-uaif";
|
|
reg = <0x00 0x18c50c00 0x20>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x00>;
|
|
clocks = <0x19 0xde 0x19 0xcb 0x19 0xd5>;
|
|
clock-names = "bclk\0bclk_gate\0mux";
|
|
pinctrl-names = "active\0idle";
|
|
pinctrl-0 = <0xa0>;
|
|
pinctrl-1 = <0xa1>;
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UAIF0";
|
|
phandle = <0x2bc>;
|
|
};
|
|
|
|
abox-uaif@18c50c20 {
|
|
compatible = "samsung,abox-uaif";
|
|
reg = <0x00 0x18c50c20 0x20>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x01>;
|
|
clocks = <0x19 0xdf 0x19 0xcc 0x19 0xd6>;
|
|
clock-names = "bclk\0bclk_gate\0mux";
|
|
pinctrl-names = "active\0idle";
|
|
pinctrl-0 = <0xa2>;
|
|
pinctrl-1 = <0xa3>;
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UAIF1";
|
|
phandle = <0x2bd>;
|
|
};
|
|
|
|
abox-uaif@18c50c40 {
|
|
compatible = "samsung,abox-uaif";
|
|
reg = <0x00 0x18c50c40 0x20>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x02>;
|
|
clocks = <0x19 0xe0 0x19 0xcd 0x19 0xd7>;
|
|
clock-names = "bclk\0bclk_gate\0mux";
|
|
pinctrl-names = "active\0idle";
|
|
pinctrl-0 = <0xa4>;
|
|
pinctrl-1 = <0xa5>;
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UAIF2";
|
|
phandle = <0x2be>;
|
|
};
|
|
|
|
abox-uaif@18c50c60 {
|
|
compatible = "samsung,abox-uaif";
|
|
reg = <0x00 0x18c50c60 0x20>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x03>;
|
|
clocks = <0x19 0xe1 0x19 0xce 0x19 0xd8>;
|
|
clock-names = "bclk\0bclk_gate\0mux";
|
|
pinctrl-names = "active\0idle";
|
|
pinctrl-0 = <0xa6>;
|
|
pinctrl-1 = <0xa7>;
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UAIF3";
|
|
phandle = <0x2bf>;
|
|
};
|
|
|
|
abox-uaif@18c50c80 {
|
|
compatible = "samsung,abox-uaif";
|
|
reg = <0x00 0x18c50c80 0x20>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x04>;
|
|
clocks = <0x19 0xe4 0x19 0xcf 0x19 0xd9>;
|
|
clock-names = "bclk\0bclk_gate\0mux";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UAIF4";
|
|
phandle = <0x2c0>;
|
|
};
|
|
|
|
abox-uaif@18c50ca0 {
|
|
compatible = "samsung,abox-uaif";
|
|
reg = <0x00 0x18c50ca0 0x20>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x05>;
|
|
clocks = <0x19 0xe5 0x19 0xd0 0x19 0xda>;
|
|
clock-names = "bclk\0bclk_gate\0mux";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UAIF5";
|
|
phandle = <0x2c1>;
|
|
};
|
|
|
|
abox-uaif@18c50cc0 {
|
|
compatible = "samsung,abox-uaif";
|
|
reg = <0x00 0x18c50cc0 0x20>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x06>;
|
|
clocks = <0x19 0xe6 0x19 0xd1 0x19 0xd4>;
|
|
clock-names = "bclk\0bclk_gate\0mux";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UAIF6";
|
|
phandle = <0x2c2>;
|
|
};
|
|
|
|
abox-dsif@18c50de0 {
|
|
compatible = "samsung,abox-dsif";
|
|
reg = <0x00 0x18c50de0 0x10>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x07>;
|
|
clocks = <0x19 0xdd 0x19 0xca>;
|
|
clock-names = "bclk\0bclk_gate";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX DSIF";
|
|
phandle = <0x2c3>;
|
|
};
|
|
|
|
abox-udma-rd@18c5c100 {
|
|
compatible = "samsung,abox-udma-rd";
|
|
reg = <0x00 0x18c5c100 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x00>;
|
|
samsung,buffer_type = "ram";
|
|
samsung,buffer-address = <0x03 0x2136000 0x3000>;
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UDMA RD0";
|
|
phandle = <0x2c4>;
|
|
};
|
|
|
|
abox-udma-rd@18c5c200 {
|
|
compatible = "samsung,abox-udma-rd";
|
|
reg = <0x00 0x18c5c200 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x01>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UDMA RD1";
|
|
phandle = <0x2c5>;
|
|
};
|
|
|
|
abox-udma-wr@18c5c700 {
|
|
compatible = "samsung,abox-udma-wr";
|
|
reg = <0x00 0x18c5c700 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x00>;
|
|
samsung,buffer_type = "ram";
|
|
samsung,buffer-address = <0x03 0x212a000 0xc000>;
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UDMA WR0";
|
|
phandle = <0x2c6>;
|
|
};
|
|
|
|
abox-udma-wr@18c5c800 {
|
|
compatible = "samsung,abox-udma-wr";
|
|
reg = <0x00 0x18c5c800 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x01>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UDMA WR1";
|
|
phandle = <0x2c7>;
|
|
};
|
|
|
|
abox-udma-wr-dual@18c5c780 {
|
|
compatible = "samsung,abox-udma-wr-dual";
|
|
reg = <0x00 0x18c5c780 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x00>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UDMA WR0 DUAL";
|
|
phandle = <0x2c8>;
|
|
};
|
|
|
|
abox-udma-wr-dual@18c5c880 {
|
|
compatible = "samsung,abox-udma-wr-dual";
|
|
reg = <0x00 0x18c5c880 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x01>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UDMA WR1 DUAL";
|
|
phandle = <0x2c9>;
|
|
};
|
|
|
|
abox-udma-wr-debug@18c5cd00 {
|
|
compatible = "samsung,abox-udma-wr-debug";
|
|
reg = <0x00 0x18c5cd00 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x00>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UDMA DBG0";
|
|
phandle = <0x2ca>;
|
|
};
|
|
|
|
abox-effect@2139000 {
|
|
compatible = "samsung,abox-effect";
|
|
reg = <0x00 0x2139000 0x1000>;
|
|
reg-names = "reg";
|
|
phandle = <0x2cb>;
|
|
};
|
|
|
|
abox-debug@0 {
|
|
compatible = "samsung,abox-debug";
|
|
memory-region = <0xa8 0xa9>;
|
|
reg = <0x00 0x00 0x00>;
|
|
phandle = <0x2cc>;
|
|
};
|
|
|
|
abox-vss@0 {
|
|
compatible = "samsung,abox-vss";
|
|
samsung,magic-offset = <0x700000>;
|
|
reg = <0x00 0x00 0x00>;
|
|
phandle = <0x2cd>;
|
|
};
|
|
|
|
abox-tplg@0 {
|
|
compatible = "samsung,abox-tplg";
|
|
reg = <0x00 0x00 0x00>;
|
|
sound-name-prefix = "ABOX";
|
|
phandle = <0x2ce>;
|
|
};
|
|
|
|
abox-pci@0 {
|
|
compatible = "samsung,abox-pci";
|
|
status = "disabled";
|
|
memory-region = <0xffffffff>;
|
|
reg = <0x00 0x00 0x00>;
|
|
pinctrl-names = "pci_on\0sleep";
|
|
pinctrl-0 = <0xaa>;
|
|
pinctrl-1 = <0xa7>;
|
|
samsung,mailbox = <0x155a0000>;
|
|
samsung,doorbell_offset = <0x00>;
|
|
phandle = <0x2cf>;
|
|
};
|
|
};
|
|
|
|
mailbox@0x153e0000 {
|
|
compatible = "samsung,mailbox-asoc";
|
|
reg = <0x00 0x153e0000 0x1000>;
|
|
reg-names = "sfr";
|
|
interrupts = <0x00 0x7e 0x04>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x01>;
|
|
phandle = <0xbb>;
|
|
};
|
|
|
|
vts@0x15310000 {
|
|
compatible = "samsung,vts";
|
|
sicd-base = <0x2053400>;
|
|
sicd-size = <0x400>;
|
|
reg = <0x00 0x15310000 0x1020 0x00 0x154f0000 0x10010 0x00 0x15350000 0x08 0x00 0x15360000 0x08 0x00 0x2500000 0x1f4000 0x00 0x15310000 0x50 0x00 0x154c0000 0x08 0x00 0x154d0000 0x08 0x00 0x154b0000 0x08 0x00 0x154e0000 0x08 0x00 0x15340000 0x400>;
|
|
reg-names = "sfr\0baaw\0dmic\0dmic1\0sram\0gpr\0intmem_code\0intmem_data\0intmem_pcm\0intmem_data1\0slif_vts";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
pinctrl-names = "dmic0_default\0dmic1_default\0dmic2_default\0amic0_default\0amic1_default\0amic2_default\0dmic0_idle\0dmic1_idle\0dmic2_idle\0default";
|
|
pinctrl-0 = <0xab 0xac>;
|
|
pinctrl-1 = <0xad 0xae>;
|
|
pinctrl-2 = <0xaf 0xb0>;
|
|
pinctrl-3 = <0xab 0xb1>;
|
|
pinctrl-4 = <0xad 0xb2>;
|
|
pinctrl-5 = <0xaf 0xb3>;
|
|
pinctrl-6 = <0xb4 0xb5>;
|
|
pinctrl-7 = <0xb6 0xb7>;
|
|
pinctrl-8 = <0xb8 0xb9>;
|
|
pinctrl-9;
|
|
power-domains = <0xba>;
|
|
clocks = <0x19 0x0b 0x19 0x8fe 0x19 0x8ff 0x19 0x900 0x19 0x901 0x19 0x903 0x19 0x8fc 0x19 0x8fd 0x19 0x904 0x19 0x902>;
|
|
clock-names = "clk_vts_src\0clk_sys_mux\0clk_dmic_mux\0dmic_if\0dmic_sync\0clk_sys\0clk_slif_src\0clk_slif_src1\0clk_slif_src2\0clk_slif_vts";
|
|
mailbox = <0xbb>;
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "VTS";
|
|
interrupt-parent = <0xbb>;
|
|
interrupts = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0b 0x0f>;
|
|
interrupt-names = "error\0boot_completed\0ipc_received\0voice_triggered\0trigger_period_elapsed\0record_period_elapsed\0debuglog_bufzero\0debuglog_bufone\0audio_dump\0log_dump\0slif_dump\0cp_wakeup";
|
|
samsung,imgloader-vts-support;
|
|
samsung,fw-id = <0x00>;
|
|
phandle = <0xbc>;
|
|
|
|
vts_dma@0 {
|
|
compatible = "samsung,vts-dma";
|
|
vts = <0xbc>;
|
|
id = <0x00>;
|
|
type = "vts-trigger";
|
|
phandle = <0x2d0>;
|
|
};
|
|
|
|
vts_dma@1 {
|
|
compatible = "samsung,vts-dma";
|
|
vts = <0xbc>;
|
|
id = <0x01>;
|
|
type = "vts-record";
|
|
phandle = <0x2d1>;
|
|
};
|
|
};
|
|
|
|
vts_s_lif@0x18f50000 {
|
|
compatible = "samsung,slif";
|
|
status = "okay";
|
|
power-domains = <0x02>;
|
|
samsung,slif-vts = <0xbc>;
|
|
id = <0x00>;
|
|
reg = <0x00 0x18f50000 0x400 0x00 0x18f60000 0x20 0x00 0x18f70000 0x20 0x00 0x18f80000 0x20>;
|
|
reg-names = "sfr\0dmic_aud0\0dmic_aud1\0dmic_aud2";
|
|
clocks = <0x19 0x8fc 0x19 0xc8 0x19 0xc9 0x19 0x8fd 0x19 0x904 0x19 0x905 0x19 0xdc 0x19 0xe7>;
|
|
clock-names = "clk_slif_src\0mux_dmic_aud0\0mux_dmic_aud1\0mux_dmic_aud\0dmic_aud\0dmic_aud_div2\0mux_serial_lif\0serial_lif";
|
|
#sound-dai-cells = <0x01>;
|
|
phandle = <0x2d2>;
|
|
};
|
|
|
|
dp_dma {
|
|
#sound-dai-cells = <0x01>;
|
|
compatible = "samsung,displayport-adma";
|
|
memory-region = <0xbd>;
|
|
phandle = <0x2d3>;
|
|
|
|
dp_dma@0 {
|
|
compatible = "samsung,dp-dma";
|
|
id = <0x00>;
|
|
dmas = <0x60 0x1c>;
|
|
dma-names = "tx";
|
|
fifo_addr = <0x10a85818>;
|
|
sound-name-prefix = "DP AUDIO0";
|
|
#dma-cells = <0x00>;
|
|
phandle = <0x2d4>;
|
|
};
|
|
|
|
dp_dma@1 {
|
|
compatible = "samsung,dp-dma";
|
|
id = <0x01>;
|
|
dmas = <0x60 0x1d>;
|
|
dma-names = "tx";
|
|
fifo_addr = <0x10a86818>;
|
|
sound-name-prefix = "DP AUDIO1";
|
|
#dma-cells = <0x00>;
|
|
phandle = <0x2d5>;
|
|
};
|
|
};
|
|
|
|
arm-pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
interrupts = <0x01 0x07 0xff04>;
|
|
};
|
|
|
|
power-data {
|
|
|
|
cpu {
|
|
|
|
klein-power-data {
|
|
cpus = "0-3";
|
|
capacity-dmips-mhz = <0x10b>;
|
|
dynamic-power-coefficient = <0xbd>;
|
|
static-power-coefficient = <0x3e>;
|
|
cal-id = <0xb040002>;
|
|
ect-param-vt = "DTM_LIT_VOLT_TEMP";
|
|
ect-param-a = "DTM_LIT_ASV";
|
|
tz-name = "LITTLE";
|
|
dhry-to-clang-dp-ratio = <0x334>;
|
|
dhry-to-clang-cap-ratio = <0x21a>;
|
|
power-sharing-dsu;
|
|
|
|
complex {
|
|
cpus = "0-1\02-3";
|
|
};
|
|
};
|
|
|
|
matterhorn-power-data {
|
|
cpus = "4-6";
|
|
capacity-dmips-mhz = <0x17c>;
|
|
dynamic-power-coefficient = <0x230>;
|
|
static-power-coefficient = <0xea>;
|
|
cal-id = <0xb040003>;
|
|
ect-param-vt = "DTM_MID_VOLT_TEMP";
|
|
ect-param-a = "DTM_MID_ASV";
|
|
tz-name = "MID";
|
|
dhry-to-clang-dp-ratio = <0x334>;
|
|
dhry-to-clang-cap-ratio = <0x179>;
|
|
power-sharing-cpus = "7";
|
|
};
|
|
|
|
montblanc-power-data {
|
|
cpus = "7";
|
|
capacity-dmips-mhz = <0x1e8>;
|
|
dynamic-power-coefficient = <0x2fd>;
|
|
static-power-coefficient = <0x219>;
|
|
cal-id = <0xb040004>;
|
|
ect-param-vt = "DTM_BIG_VOLT_TEMP";
|
|
ect-param-a = "DTM_BIG_ASV";
|
|
tz-name = "BIG";
|
|
dhry-to-clang-dp-ratio = <0x334>;
|
|
dhry-to-clang-cap-ratio = <0x181>;
|
|
power-sharing-cpus = "4-6";
|
|
};
|
|
};
|
|
|
|
dsu {
|
|
ect-coeff-idx = <0x05>;
|
|
power-sharing-cpus = "0-3";
|
|
};
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
|
|
cpu-map {
|
|
|
|
cluster0 {
|
|
|
|
core0 {
|
|
cpu = <0xbe>;
|
|
};
|
|
|
|
core1 {
|
|
cpu = <0xbf>;
|
|
};
|
|
|
|
core2 {
|
|
cpu = <0xc0>;
|
|
};
|
|
|
|
core3 {
|
|
cpu = <0xc1>;
|
|
};
|
|
};
|
|
|
|
cluster1 {
|
|
|
|
core0 {
|
|
cpu = <0xc2>;
|
|
};
|
|
|
|
core1 {
|
|
cpu = <0xc3>;
|
|
};
|
|
|
|
core2 {
|
|
cpu = <0xc4>;
|
|
};
|
|
};
|
|
|
|
cluster2 {
|
|
|
|
core0 {
|
|
cpu = <0xc5>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu@0000 {
|
|
device_type = "cpu";
|
|
compatible = "arm,ananke\0arm,armv8";
|
|
reg = <0x00 0x00>;
|
|
capacity-dmips-mhz = <0x10b>;
|
|
dynamic-power-coefficient = <0xbd>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0xc6>;
|
|
phandle = <0xbe>;
|
|
};
|
|
|
|
cpu@0100 {
|
|
device_type = "cpu";
|
|
compatible = "arm,klein\0arm,armv9";
|
|
reg = <0x00 0x100>;
|
|
capacity-dmips-mhz = <0x10b>;
|
|
dynamic-power-coefficient = <0xbd>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0xc6>;
|
|
phandle = <0xbf>;
|
|
};
|
|
|
|
cpu@0200 {
|
|
device_type = "cpu";
|
|
compatible = "arm,klein\0arm,armv9";
|
|
reg = <0x00 0x200>;
|
|
capacity-dmips-mhz = <0x10b>;
|
|
dynamic-power-coefficient = <0xbd>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0xc6>;
|
|
phandle = <0xc0>;
|
|
};
|
|
|
|
cpu@0300 {
|
|
device_type = "cpu";
|
|
compatible = "arm,klein\0arm,armv9";
|
|
reg = <0x00 0x300>;
|
|
capacity-dmips-mhz = <0x10b>;
|
|
dynamic-power-coefficient = <0xbd>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0xc6>;
|
|
phandle = <0xc1>;
|
|
};
|
|
|
|
cpu@0400 {
|
|
device_type = "cpu";
|
|
compatible = "arm,matterhorn\0arm,armv9";
|
|
reg = <0x00 0x400>;
|
|
capacity-dmips-mhz = <0x17c>;
|
|
dynamic-power-coefficient = <0x230>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0xc7>;
|
|
phandle = <0xc2>;
|
|
};
|
|
|
|
cpu@0500 {
|
|
device_type = "cpu";
|
|
compatible = "arm,matterhorn\0arm,armv9";
|
|
reg = <0x00 0x500>;
|
|
capacity-dmips-mhz = <0x17c>;
|
|
dynamic-power-coefficient = <0x230>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0xc7>;
|
|
phandle = <0xc3>;
|
|
};
|
|
|
|
cpu@0600 {
|
|
device_type = "cpu";
|
|
compatible = "arm,matterhorn\0arm,armv9";
|
|
reg = <0x00 0x600>;
|
|
capacity-dmips-mhz = <0x17c>;
|
|
dynamic-power-coefficient = <0x230>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0xc7>;
|
|
phandle = <0xc4>;
|
|
};
|
|
|
|
cpu@0700 {
|
|
device_type = "cpu";
|
|
compatible = "arm,montblanc\0arm,armv9";
|
|
reg = <0x00 0x700>;
|
|
capacity-dmips-mhz = <0x1e8>;
|
|
dynamic-power-coefficient = <0x2fd>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0xc8>;
|
|
phandle = <0xc5>;
|
|
};
|
|
|
|
idle-states {
|
|
entry-method = "arm,psci";
|
|
|
|
klein-cpu-sleep {
|
|
idle-state-name = "c2";
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x10000>;
|
|
entry-latency-us = <0x46>;
|
|
exit-latency-us = <0xa0>;
|
|
min-residency-us = <0x7d0>;
|
|
status = "okay";
|
|
phandle = <0xc6>;
|
|
};
|
|
|
|
matterhorn-cpu-sleep {
|
|
idle-state-name = "c2";
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x10000>;
|
|
entry-latency-us = <0x96>;
|
|
exit-latency-us = <0xbe>;
|
|
min-residency-us = <0x9c4>;
|
|
status = "okay";
|
|
phandle = <0xc7>;
|
|
};
|
|
|
|
montblanc-cpu-sleep {
|
|
idle-state-name = "c2";
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x10000>;
|
|
entry-latency-us = <0xeb>;
|
|
exit-latency-us = <0xdc>;
|
|
min-residency-us = <0xdac>;
|
|
status = "okay";
|
|
phandle = <0xc8>;
|
|
};
|
|
};
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
|
|
exynos-cpuhp {
|
|
compatible = "samsung,exynos-cpuhp";
|
|
status = "okay";
|
|
};
|
|
|
|
exynos-cpupm {
|
|
compatible = "samsung,exynos-cpupm";
|
|
status = "okay";
|
|
cpu-state-spare-addr = <0xbffff054>;
|
|
|
|
cpd_cl0 {
|
|
device_type = "cpupm";
|
|
target-residency = <0x2710>;
|
|
type = <0x00>;
|
|
cal-id = <0x00>;
|
|
siblings = "0-3";
|
|
};
|
|
|
|
cpd_cl1 {
|
|
device_type = "cpupm";
|
|
target-residency = <0x2710>;
|
|
type = <0x00>;
|
|
cal-id = <0x01>;
|
|
siblings = "4-6";
|
|
entry-allowed = "4-6";
|
|
};
|
|
|
|
cpd_cl2 {
|
|
device_type = "cpupm";
|
|
target-residency = <0x2710>;
|
|
type = <0x00>;
|
|
cal-id = <0x02>;
|
|
siblings = "7";
|
|
entry-allowed = "7";
|
|
};
|
|
|
|
dsupd {
|
|
device_type = "cpupm";
|
|
target-residency = <0x2710>;
|
|
type = <0x01>;
|
|
siblings = "0-7";
|
|
entry-allowed = "0-7";
|
|
};
|
|
|
|
sicd {
|
|
device_type = "cpupm";
|
|
target-residency = <0x2710>;
|
|
type = <0x02>;
|
|
siblings = "0-7";
|
|
entry-allowed = "0-7";
|
|
};
|
|
|
|
wakeup-mask {
|
|
|
|
wakeup-masks {
|
|
|
|
wakeup-mask {
|
|
mask-reg-offset = <0x3b44>;
|
|
stat-reg-offset = <0x3b50>;
|
|
mask = <0xff000000>;
|
|
};
|
|
|
|
wakeup-mask2 {
|
|
mask-reg-offset = <0x3b64>;
|
|
stat-reg-offset = <0x3b54>;
|
|
mask = <0x00>;
|
|
};
|
|
};
|
|
|
|
eint-wakeup-masks {
|
|
|
|
eint-wakeup-mask {
|
|
mask-reg-offset = <0x60c>;
|
|
};
|
|
|
|
eint-wakeup-mask2 {
|
|
mask-reg-offset = <0x610>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
exynos-acme {
|
|
compatible = "samsung,exynos-acme";
|
|
status = "okay";
|
|
|
|
domain@0 {
|
|
sibling-cpus = "0-3";
|
|
cal-id = <0xb040002>;
|
|
dm-type = <0x00>;
|
|
dss-type = <0x00>;
|
|
max-freq = <0x1a5e00>;
|
|
min-freq = <0x61a80>;
|
|
fast-switch;
|
|
thread-run-on = "0-5";
|
|
#cooling-cells = <0x02>;
|
|
ect-coeff-index = <0x02>;
|
|
tz-cooling-name = "LITTLE";
|
|
freq-table = <0x61a80 0x8ca00 0xa4100 0xbb800 0xd2f00 0xea600 0x101d00 0x119400 0x130b00 0x148200 0x15f900 0x177000 0x18e700 0x1a5e00>;
|
|
phandle = <0x11a>;
|
|
|
|
dm-constraints {
|
|
list = <0xc9 0xca 0xcb>;
|
|
};
|
|
};
|
|
|
|
domain@1 {
|
|
sibling-cpus = "4-6";
|
|
cal-id = <0xb040003>;
|
|
dm-type = <0x01>;
|
|
dss-type = <0x01>;
|
|
max-freq = <0x266038>;
|
|
min-freq = <0x8ca00>;
|
|
fast-switch;
|
|
thread-run-on = "0-5";
|
|
#cooling-cells = <0x02>;
|
|
ect-coeff-index = <0x01>;
|
|
tz-cooling-name = "MID";
|
|
freq-table = <0x8ca00 0xa4100 0xbb800 0xd2f00 0xea600 0x101d00 0x119400 0x130b00 0x148200 0x15f900 0x177000 0x18e700 0x1a5e00 0x1bd500 0x1d4c00 0x1ec300 0x203a00 0x21b100 0x232800 0x249f00 0x266038>;
|
|
phandle = <0x115>;
|
|
|
|
dm-constraints {
|
|
list = <0xcc 0xcd 0xce>;
|
|
};
|
|
};
|
|
|
|
domain@2 {
|
|
sibling-cpus = "7";
|
|
cal-id = <0xb040004>;
|
|
dm-type = <0x02>;
|
|
dss-type = <0x02>;
|
|
max-freq = <0x2ac538>;
|
|
min-freq = <0x8ca00>;
|
|
fast-switch;
|
|
thread-run-on = "0-5";
|
|
pm_qos-booting = <0x27d738>;
|
|
#cooling-cells = <0x02>;
|
|
ect-coeff-index = <0x00>;
|
|
tz-cooling-name = "BIG";
|
|
freq-table = <0x8ca00 0xa4100 0xbb800 0xd2f00 0xea600 0x101d00 0x119400 0x130b00 0x148200 0x15f900 0x177000 0x18e700 0x1a5e00 0x1bd500 0x1d4c00 0x1ec300 0x203a00 0x21b100 0x232800 0x249f00 0x266038 0x27d738 0x294e38 0x2ac538>;
|
|
phandle = <0x114>;
|
|
|
|
dm-constraints {
|
|
list = <0xcf 0xd0 0xd1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
dm-tables {
|
|
|
|
dm-table@0000 {
|
|
const-type = <0x00>;
|
|
dm-slave = <0x06>;
|
|
master-cal-id = <0xb040002>;
|
|
slave-cal-id = <0xb040006>;
|
|
multi-table;
|
|
table = <0x61a80 0x3a980 0x8ca00 0x5dc00 0xa4100 0x69780 0xbb800 0x80e80 0xd2f00 0x8ca00 0xea600 0x98580 0x101d00 0xafc80 0x119400 0xbb800 0x130b00 0xc7380 0x148200 0xdea80 0x15f900 0xea600 0x177000 0xf6180 0x18e700 0x10d880 0x1a5e00 0x119400>;
|
|
phandle = <0xc9>;
|
|
};
|
|
|
|
dm-table@0010 {
|
|
const-type = <0x00>;
|
|
dm-slave = <0x06>;
|
|
master-cal-id = <0xb040002>;
|
|
slave-cal-id = <0xb040006>;
|
|
multi-table;
|
|
table = <0x61a80 0x30d40 0x8ca00 0x46500 0xa4100 0x52080 0xbb800 0x5dc00 0xd2f00 0x69780 0xea600 0x75300 0x101d00 0x80e80 0x119400 0x8ca00 0x130b00 0x98580 0x148200 0xa4100 0x15f900 0xafc80 0x177000 0xbb800 0x18e700 0x10d880 0x1a5e00 0x119400>;
|
|
phandle = <0xca>;
|
|
};
|
|
|
|
dm-table@0001 {
|
|
const-type = <0x00>;
|
|
dm-slave = <0x06>;
|
|
master-cal-id = <0xb040003>;
|
|
slave-cal-id = <0xb040006>;
|
|
multi-table;
|
|
table = <0x8ca00 0x412f8 0xa4100 0x69780 0xbb800 0x80e80 0xd2f00 0x8ca00 0xea600 0x98580 0x101d00 0xafc80 0x119400 0xbb800 0x130b00 0xc7380 0x148200 0xd2f00 0x15f900 0xea600 0x177000 0xf6180 0x18e700 0x10d880 0x1a5e00 0x119400 0x1bd500 0x124f80 0x1d4c00 0x130b00 0x1ec300 0x148200 0x203a00 0x153d80 0x21b100 0x15f900 0x232800 0x177000 0x249f00 0x182b80 0x266038 0x1a5e00>;
|
|
phandle = <0xcc>;
|
|
};
|
|
|
|
dm-table@0011 {
|
|
const-type = <0x00>;
|
|
dm-slave = <0x06>;
|
|
master-cal-id = <0xb040003>;
|
|
slave-cal-id = <0xb040006>;
|
|
multi-table;
|
|
table = <0x8ca00 0x46500 0xa4100 0x52080 0xbb800 0x5dc00 0xd2f00 0x69780 0xea600 0x75300 0x101d00 0x80e80 0x119400 0x8ca00 0x130b00 0x98580 0x148200 0xa4100 0x15f900 0xafc80 0x177000 0xbb800 0x18e700 0xc7380 0x1a5e00 0xd2f00 0x1bd500 0x124f80 0x1d4c00 0x130b00 0x1ec300 0x148200 0x203a00 0x153d80 0x21b100 0x15f900 0x232800 0x177000 0x249f00 0x182b80 0x266038 0x18e700>;
|
|
phandle = <0xcd>;
|
|
};
|
|
|
|
dm-table@0002 {
|
|
const-type = <0x00>;
|
|
dm-slave = <0x06>;
|
|
master-cal-id = <0xb040004>;
|
|
slave-cal-id = <0xb040006>;
|
|
multi-table;
|
|
table = <0x8ca00 0x412f8 0xa4100 0x69780 0xbb800 0x80e80 0xd2f00 0x8ca00 0xea600 0x98580 0x101d00 0xafc80 0x119400 0xbb800 0x130b00 0xc7380 0x148200 0xdea80 0x15f900 0xea600 0x177000 0xf6180 0x18e700 0x10d880 0x1a5e00 0x119400 0x1bd500 0x124f80 0x1d4c00 0x130b00 0x1ec300 0x148200 0x203a00 0x153d80 0x21b100 0x15f900 0x232800 0x177000 0x249f00 0x182b80 0x266038 0x1a5e00 0x27d738 0x1a5e00 0x294e38 0x1a5e00 0x2ac538 0x1a5e00>;
|
|
phandle = <0xcf>;
|
|
};
|
|
|
|
dm-table@0012 {
|
|
const-type = <0x00>;
|
|
dm-slave = <0x06>;
|
|
master-cal-id = <0xb040004>;
|
|
slave-cal-id = <0xb040006>;
|
|
multi-table;
|
|
table = <0x8ca00 0x46500 0xa4100 0x52080 0xbb800 0x5dc00 0xd2f00 0x69780 0xea600 0x75300 0x101d00 0x80e80 0x119400 0x8ca00 0x130b00 0x98580 0x148200 0xa4100 0x15f900 0xafc80 0x177000 0xbb800 0x18e700 0xc7380 0x1a5e00 0xd2f00 0x1bd500 0x124f80 0x1d4c00 0x130b00 0x1ec300 0x148200 0x203a00 0x153d80 0x21b100 0x15f900 0x232800 0x177000 0x249f00 0x182b80 0x266038 0x18e700 0x27d738 0x18e700 0x294e38 0x18e700 0x2ac538 0x18e700>;
|
|
phandle = <0xd0>;
|
|
};
|
|
|
|
dm-table@0003 {
|
|
const-type = <0x00>;
|
|
dm-slave = <0x03>;
|
|
master-cal-id = <0xb040002>;
|
|
slave-cal-id = <0xb040000>;
|
|
dynamic-disable;
|
|
table = <0x61a80 0x00 0x8ca00 0x00 0xa4100 0x00 0xbb800 0x00 0xd2f00 0x00 0xea600 0x00 0x101d00 0x00 0x119400 0x00 0x130b00 0x00 0x148200 0x00 0x15f900 0x00 0x177000 0x00 0x18e700 0x00 0x1a5e00 0x00>;
|
|
phandle = <0xcb>;
|
|
};
|
|
|
|
dm-table@0004 {
|
|
const-type = <0x00>;
|
|
dm-slave = <0x03>;
|
|
master-cal-id = <0xb040003>;
|
|
slave-cal-id = <0xb040000>;
|
|
dynamic-disable;
|
|
table = <0x8ca00 0x00 0xa4100 0x00 0xbb800 0x00 0xd2f00 0x00 0xea600 0x00 0x101d00 0x00 0x119400 0x00 0x130b00 0x00 0x148200 0x00 0x15f900 0x00 0x177000 0x00 0x18e700 0x00 0x1a5e00 0x00 0x1bd500 0x00 0x1d4c00 0x00 0x1ec300 0x22e980 0x203a00 0x22e980 0x21b100 0x22e980 0x232800 0x26ae58 0x249f00 0x29a810 0x266038 0x3066a0>;
|
|
phandle = <0xce>;
|
|
};
|
|
|
|
dm-table@0005 {
|
|
const-type = <0x00>;
|
|
dm-slave = <0x03>;
|
|
master-cal-id = <0xb040004>;
|
|
slave-cal-id = <0xb040000>;
|
|
dynamic-disable;
|
|
table = <0x8ca00 0x00 0xa4100 0x00 0xbb800 0x00 0xd2f00 0x00 0xea600 0x00 0x101d00 0x00 0x119400 0x00 0x130b00 0x00 0x148200 0x00 0x15f900 0x00 0x177000 0x00 0x18e700 0x00 0x1a5e00 0x00 0x1bd500 0x00 0x1d4c00 0x00 0x1ec300 0x22e980 0x203a00 0x22e980 0x21b100 0x22e980 0x232800 0x26ae58 0x249f00 0x26ae58 0x266038 0x29a810 0x27d738 0x3066a0 0x294e38 0x3066a0 0x2ac538 0x3066a0>;
|
|
phandle = <0xd1>;
|
|
};
|
|
|
|
dm-table@0006 {
|
|
const-type = <0x00>;
|
|
dm-slave = <0x03>;
|
|
ect-name = "DSU_MIF";
|
|
guidance;
|
|
phandle = <0xd2>;
|
|
};
|
|
};
|
|
|
|
exynos-dsufreq {
|
|
compatible = "samsung,exynos-dsufreq";
|
|
status = "okay";
|
|
cal-id = <0xb040006>;
|
|
dm-type = <0x06>;
|
|
dss-type = <0x0b>;
|
|
max-freq = <0x1a5e00>;
|
|
min-freq = <0x17700>;
|
|
init-with-dt = <0x01>;
|
|
table = <0x17700 0x23280 0x2ee00 0x3a980 0x46500 0x52080 0x5dc00 0x69780 0x75300 0x80e80 0x8ca00 0x98580 0xa4100 0xafc80 0xbb800 0xc7380 0xd2f00 0xdea80 0xea600 0xf6180 0x101d00 0x10d880 0x119400 0x124f80 0x130b00 0x13c680 0x148200 0x153d80 0x15f900 0x16b480 0x177000 0x182b80 0x18e700 0x1a5e00>;
|
|
|
|
request_domain0 {
|
|
sibling-cpus = "0-3";
|
|
constraint = <0xc9>;
|
|
};
|
|
|
|
request_domain1 {
|
|
sibling-cpus = "4-6";
|
|
constraint = <0xcc>;
|
|
};
|
|
|
|
request_domain2 {
|
|
sibling-cpus = "7";
|
|
constraint = <0xcf>;
|
|
};
|
|
|
|
hw-constraints {
|
|
list = <0xd2>;
|
|
};
|
|
};
|
|
|
|
exynos-ufcc {
|
|
compatible = "samsung,exynos-ufcc";
|
|
status = "okay";
|
|
|
|
ucc {
|
|
|
|
ucc-config0 {
|
|
index = <0x00>;
|
|
cstate = "4-7";
|
|
};
|
|
|
|
ucc-config1 {
|
|
index = <0x01>;
|
|
cstate = "7";
|
|
};
|
|
|
|
ucc-config2 {
|
|
index = <0x02>;
|
|
};
|
|
};
|
|
|
|
ufc {
|
|
table-col = <0x06>;
|
|
boot-domain-auto-table;
|
|
|
|
domain@0 {
|
|
device_type = "ufc-domain";
|
|
shared-cpus = "0-3";
|
|
table-col-idx = <0x03>;
|
|
};
|
|
|
|
domain@1 {
|
|
device_type = "ufc-domain";
|
|
shared-cpus = "4-6";
|
|
table-col-idx = <0x02>;
|
|
allow-disable-cpus;
|
|
};
|
|
|
|
domain@2 {
|
|
device_type = "ufc-domain";
|
|
shared-cpus = "7";
|
|
table-col-idx = <0x01>;
|
|
allow-disable-cpus;
|
|
};
|
|
|
|
table-info {
|
|
table-order = "vfreq\0big\0mid\0lit\0emstune\0strict";
|
|
};
|
|
|
|
max-limit {
|
|
device_type = "ufc-table";
|
|
ctrl-type = <0x02>;
|
|
table = <0x2ac538 0x2ac538 0x266038 0x1a5e00 0x00 0x00 0x294e38 0x294e38 0x266038 0x1a5e00 0x00 0x00 0x27d738 0x27d738 0x266038 0x177000 0x00 0x00 0x266038 0x266038 0x266038 0x177000 0x00 0x00 0x249f00 0x249f00 0x249f00 0x177000 0x00 0x00 0x232800 0x232800 0x232800 0x177000 0x00 0x00 0x21b100 0x21b100 0x21b100 0x177000 0x00 0x00 0x203a00 0x203a00 0x203a00 0x177000 0x00 0x00 0x1ec300 0x1ec300 0x1ec300 0x177000 0x00 0x00 0x1d4c00 0x1d4c00 0x1d4c00 0x148200 0x00 0x00 0x1bd500 0x1bd500 0x1bd500 0x148200 0x00 0x00 0x1a5e00 0x1a5e00 0x1a5e00 0x148200 0x00 0x00 0x18e700 0x18e700 0x18e700 0x148200 0x00 0x00 0x177000 0x177000 0x177000 0x148200 0x00 0x00 0x15f900 0x15f900 0x15f900 0x148200 0x00 0x00 0x148200 0x148200 0x148200 0x148200 0x00 0x00 0x130b00 0x130b00 0x130b00 0x148200 0x00 0x00 0x119400 0x119400 0x119400 0x148200 0x00 0x00 0x101d00 0x101d00 0x101d00 0x148200 0x00 0x00 0xea600 0xea600 0xea600 0x148200 0x00 0x00 0xd2f00 0xd2f00 0xd2f00 0x148200 0x00 0x00 0xbb800 0xbb800 0xbb800 0x148200 0x00 0x00 0xa4100 0xa4100 0xa4100 0x148200 0x00 0x00 0x8ca00 0x8ca00 0x8ca00 0x148200 0x00 0x00>;
|
|
};
|
|
|
|
min-limit {
|
|
device_type = "ufc-table";
|
|
ctrl-type = <0x00>;
|
|
table = <0x2ac538 0x2ac538 0x266038 0x1a5e00 0x02 0x01 0x294e38 0x294e38 0x266038 0x1a5e00 0x02 0x01 0x27d738 0x27d738 0x266038 0x1a5e00 0x02 0x01 0x266038 0x266038 0x266038 0x1a5e00 0x02 0x01 0x249f00 0x249f00 0x249f00 0x119400 0x02 0x01 0x232800 0x232800 0x232800 0x119400 0x02 0x01 0x21b100 0x21b100 0x21b100 0x119400 0x02 0x01 0x203a00 0x203a00 0x203a00 0x119400 0x02 0x01 0x1ec300 0x1ec300 0x1ec300 0x119400 0x02 0x01 0x1d4c00 0x1d4c00 0x1d4c00 0x119400 0x02 0x01 0x1bd500 0x1bd500 0x1bd500 0x119400 0x01 0x01 0x1a5e00 0x1a5e00 0x1a5e00 0xea600 0x01 0x01 0x18e700 0x18e700 0x18e700 0xea600 0x01 0x01 0x177000 0x177000 0x177000 0xea600 0x01 0x01 0x15f900 0x15f900 0x15f900 0xea600 0x01 0x01 0x148200 0x148200 0x148200 0xea600 0x01 0x01 0x130b00 0x130b00 0x130b00 0xea600 0x01 0x01 0x119400 0x119400 0x119400 0xea600 0x01 0x01 0x101d00 0x101d00 0x101d00 0xea600 0x01 0x01 0xea600 0xea600 0xea600 0xbb800 0x01 0x01 0xd2f00 0xd2f00 0xd2f00 0xbb800 0x01 0x01 0xbb800 0xbb800 0xbb800 0xbb800 0x00 0x01 0xa4100 0xa4100 0xa4100 0xbb800 0x00 0x01 0x8ca00 0x8ca00 0x8ca00 0xbb800 0x00 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
freq-qos-tracer {
|
|
compatible = "samsung,freq-qos-tracer";
|
|
status = "okay";
|
|
};
|
|
|
|
exynos-afm {
|
|
compatible = "samsung,exynos-afm";
|
|
status = "okay";
|
|
waiting-freq-change;
|
|
|
|
domain@0 {
|
|
device_type = "afm-domain";
|
|
compatible = "samsung,exynos-afm";
|
|
interrupts = <0x00 0xd6 0x04>;
|
|
sibling-cpus = "0-3";
|
|
interrupt-src = <0x01>;
|
|
s2mps-afm-offset = <0x74>;
|
|
htu-base-addr = <0x1d080000>;
|
|
down-step = <0x01>;
|
|
max-freq-wo-afm = <0x1e8c50>;
|
|
release-duration = <0x0f>;
|
|
phandle = <0x2d6>;
|
|
};
|
|
|
|
domain@1 {
|
|
device_type = "afm-domain";
|
|
compatible = "samsung,exynos-afm";
|
|
interrupts = <0x00 0xd7 0x04>;
|
|
sibling-cpus = "4-6";
|
|
interrupt-src = <0x01>;
|
|
s2mps-afm-offset = <0x80>;
|
|
htu-base-addr = <0x1d090000>;
|
|
down-step = <0x01>;
|
|
max-freq-wo-afm = <0x1e8c50>;
|
|
release-duration = <0x0f>;
|
|
phandle = <0x2d7>;
|
|
};
|
|
|
|
domain@2 {
|
|
device_type = "afm-domain";
|
|
compatible = "samsung,exynos-afm";
|
|
interrupts = <0x00 0xd8 0x04>;
|
|
sibling-cpus = "7";
|
|
interrupt-src = <0x01>;
|
|
s2mps-afm-offset = <0x80>;
|
|
htu-base-addr = <0x1d0a0000>;
|
|
down-step = <0x01>;
|
|
max-freq-wo-afm = <0x1e8c50>;
|
|
release-duration = <0x0f>;
|
|
phandle = <0x2d8>;
|
|
};
|
|
};
|
|
|
|
dsim_modes {
|
|
phandle = <0xda>;
|
|
|
|
dsim-modes {
|
|
|
|
1440x3200@30 {
|
|
mode-name = "1440x3200@30";
|
|
pmsk = <0x05 0x59 0x00 0xac00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
hs-clk = <0x552>;
|
|
esc-clk = <0x14>;
|
|
cmd_underrun_cnt = <0x2282>;
|
|
};
|
|
|
|
1440x3200@60 {
|
|
mode-name = "1440x3200@60";
|
|
pmsk = <0x05 0x59 0x00 0xac00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
hs-clk = <0x552>;
|
|
esc-clk = <0x14>;
|
|
cmd_underrun_cnt = <0x2282>;
|
|
};
|
|
|
|
1080x2400@30 {
|
|
mode-name = "1080x2400@30";
|
|
pmsk = <0x05 0x59 0x00 0xac00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
hs-clk = <0x552>;
|
|
esc-clk = <0x14>;
|
|
cmd_underrun_cnt = <0x2c61>;
|
|
};
|
|
|
|
1080x2400@60 {
|
|
mode-name = "1080x2400@60";
|
|
pmsk = <0x05 0x59 0x00 0xac00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
hs-clk = <0x552>;
|
|
esc-clk = <0x14>;
|
|
cmd_underrun_cnt = <0x2c61>;
|
|
};
|
|
|
|
1080x2400@120 {
|
|
mode-name = "1080x2400@120";
|
|
pmsk = <0x05 0x59 0x00 0xac00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
hs-clk = <0x552>;
|
|
esc-clk = <0x14>;
|
|
cmd_underrun_cnt = <0xeee>;
|
|
};
|
|
|
|
1080x2340@60 {
|
|
mode-name = "1080x2340@60";
|
|
pmsk = <0x05 0x59 0x00 0xac00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
hs-clk = <0x552>;
|
|
esc-clk = <0x14>;
|
|
cmd_underrun_cnt = <0x2c61>;
|
|
};
|
|
|
|
1080x2340@120 {
|
|
mode-name = "1080x2340@120";
|
|
pmsk = <0x05 0x59 0x00 0xac00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
hs-clk = <0x552>;
|
|
esc-clk = <0x14>;
|
|
cmd_underrun_cnt = <0xeee>;
|
|
};
|
|
|
|
1080x2316@60 {
|
|
mode-name = "1080x2316@60";
|
|
pmsk = <0x05 0x59 0x00 0xac00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
hs-clk = <0x552>;
|
|
esc-clk = <0x14>;
|
|
cmd_underrun_cnt = <0x2c61>;
|
|
};
|
|
|
|
1080x2316@120 {
|
|
mode-name = "1080x2316@120";
|
|
pmsk = <0x05 0x59 0x00 0xac00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
hs-clk = <0x552>;
|
|
esc-clk = <0x14>;
|
|
cmd_underrun_cnt = <0xeee>;
|
|
};
|
|
|
|
720x1600@30 {
|
|
mode-name = "720x1600@30";
|
|
pmsk = <0x05 0x59 0x00 0xac00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
hs-clk = <0x552>;
|
|
esc-clk = <0x14>;
|
|
cmd_underrun_cnt = <0x3370>;
|
|
};
|
|
|
|
720x1600@60 {
|
|
mode-name = "720x1600@60";
|
|
pmsk = <0x05 0x59 0x00 0xac00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
hs-clk = <0x552>;
|
|
esc-clk = <0x14>;
|
|
cmd_underrun_cnt = <0x3370>;
|
|
};
|
|
|
|
720x1600@120 {
|
|
mode-name = "720x1600@120";
|
|
pmsk = <0x05 0x59 0x00 0xac00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
hs-clk = <0x552>;
|
|
esc-clk = <0x14>;
|
|
cmd_underrun_cnt = <0x15fd>;
|
|
};
|
|
|
|
640x480 {
|
|
mode-name = "640x480";
|
|
pmsk = <0x02 0x8a 0x01 0x89d9 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
hs-clk = <0x37e>;
|
|
esc-clk = <0x14>;
|
|
cmd_underrun_cnt = <0x144b>;
|
|
};
|
|
};
|
|
};
|
|
|
|
drmdpp@0x1AD00000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1ad00000 0x1000 0x00 0x1ad30000 0x1000 0x00 0x1ad50000 0x1000 0x00 0x1ad20000 0x500 0x00 0x189e0000 0x10000 0x00 0x1ad40000 0x4000 0x00 0x1ad60000 0x1000 0x00 0x1ad3f000 0x1000 0x00 0x1ad70000 0x1000>;
|
|
reg-names = "dma\0dpp\0sramc\0votf\0votf_mscl\0scl_coef\0hdr_comm\0dpp_debug\0mcd_hdr";
|
|
interrupts = <0x00 0x190 0x04 0x00 0x1a2 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
iommus = <0xd3 0xd4 0xd5 0xd6>;
|
|
samsung,iommu-group = <0xd7>;
|
|
attr = <0x1d0005>;
|
|
port = <0x00>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
dpp,id = <0x00>;
|
|
dpuf,id = <0x00>;
|
|
rsc_sajc = <0x01>;
|
|
rsc_sbwc = <0x02>;
|
|
rsc_rot = <0x01>;
|
|
rsc_scl = <0x02>;
|
|
rsc_itp_csc = <0x04>;
|
|
rsc_sramc = <0x02>;
|
|
rsc_sram_w = <0x400>;
|
|
rsc_sram = <0x2a>;
|
|
phandle = <0xdf>;
|
|
};
|
|
|
|
drmdpp@0x1AD01000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1ad01000 0x1000 0x00 0x1ad31000 0x1000 0x00 0x1ad51000 0x1000 0x00 0x1ad20000 0x500 0x00 0x1ad40000 0x4000 0x00 0x1ad61000 0x1000 0x00 0x1ad71000 0x1000>;
|
|
reg-names = "dma\0dpp\0sramc\0votf\0scl_coef\0hdr_comm\0mcd_hdr";
|
|
interrupts = <0x00 0x191 0x04 0x00 0x1a3 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x1d043d>;
|
|
port = <0x00>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
dpp,id = <0x01>;
|
|
dpuf,id = <0x00>;
|
|
dpp,video;
|
|
phandle = <0xe0>;
|
|
};
|
|
|
|
drmdpp@0x1AD02000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1ad02000 0x1000 0x00 0x1ad32000 0x1000 0x00 0x1ad52000 0x1000 0x00 0x1ad20000 0x500 0x00 0x1ad40000 0x4000 0x00 0x1ad62000 0x1000 0x00 0x1ad72000 0x1000>;
|
|
reg-names = "dma\0dpp\0sramc\0votf\0scl_coef\0hdr_comm\0mcd_hdr";
|
|
interrupts = <0x00 0x192 0x04 0x00 0x1a4 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x1d0005>;
|
|
port = <0x00>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
dpp,id = <0x02>;
|
|
dpuf,id = <0x00>;
|
|
phandle = <0xe1>;
|
|
};
|
|
|
|
drmdpp@0x1AD03000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1ad03000 0x1000 0x00 0x1ad33000 0x1000 0x00 0x1ad53000 0x1000 0x00 0x1ad20000 0x500 0x00 0x1ad40000 0x4000 0x00 0x1ad63000 0x1000 0x00 0x1ad73000 0x1000>;
|
|
reg-names = "dma\0dpp\0sramc\0votf\0scl_coef\0hdr_comm\0mcd_hdr";
|
|
interrupts = <0x00 0x193 0x04 0x00 0x1a5 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x1d043d>;
|
|
port = <0x00>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
dpp,id = <0x03>;
|
|
dpuf,id = <0x00>;
|
|
dpp,video;
|
|
phandle = <0xe2>;
|
|
};
|
|
|
|
drmdpp@0x1AD04000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1ad04000 0x1000 0x00 0x1ad34000 0x1000 0x00 0x1ad54000 0x1000 0x00 0x1ad20000 0x500 0x00 0x1ad40000 0x4000 0x00 0x1ad64000 0x1000 0x00 0x1ad74000 0x1000>;
|
|
reg-names = "dma\0dpp\0sramc\0votf\0scl_coef\0hdr_comm\0mcd_hdr";
|
|
interrupts = <0x00 0x194 0x04 0x00 0x1a6 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x1d0005>;
|
|
port = <0x01>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
dpp,id = <0x04>;
|
|
dpuf,id = <0x00>;
|
|
phandle = <0xe3>;
|
|
};
|
|
|
|
drmdpp@0x1AD05000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1ad05000 0x1000 0x00 0x1ad35000 0x1000 0x00 0x1ad55000 0x1000 0x00 0x1ad20000 0x500 0x00 0x1ad40000 0x4000 0x00 0x1ad65000 0x1000 0x00 0x1ad75000 0x1000>;
|
|
reg-names = "dma\0dpp\0sramc\0votf\0scl_coef\0hdr_comm\0mcd_hdr";
|
|
interrupts = <0x00 0x195 0x04 0x00 0x1a7 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x1d0435>;
|
|
port = <0x01>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
dpp,id = <0x05>;
|
|
dpuf,id = <0x00>;
|
|
dpp,video;
|
|
phandle = <0xe4>;
|
|
};
|
|
|
|
drmdpp@0x1AD06000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1ad06000 0x1000 0x00 0x1ad36000 0x1000 0x00 0x1ad56000 0x1000 0x00 0x1ad20000 0x500 0x00 0x1ad40000 0x4000 0x00 0x1ad66000 0x1000 0x00 0x1ad76000 0x1000>;
|
|
reg-names = "dma\0dpp\0sramc\0votf\0scl_coef\0hdr_comm\0mcd_hdr";
|
|
interrupts = <0x00 0x196 0x04 0x00 0x1a8 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x1d0005>;
|
|
port = <0x01>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
dpp,id = <0x06>;
|
|
dpuf,id = <0x00>;
|
|
phandle = <0xe5>;
|
|
};
|
|
|
|
drmdpp@0x1AD07000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1ad07000 0x1000 0x00 0x1ad37000 0x1000 0x00 0x1ad57000 0x1000 0x00 0x1ad20000 0x500 0x00 0x1ad40000 0x4000 0x00 0x1ad67000 0x1000 0x00 0x1ad77000 0x1000>;
|
|
reg-names = "dma\0dpp\0sramc\0votf\0scl_coef\0hdr_comm\0mcd_hdr";
|
|
interrupts = <0x00 0x197 0x04 0x00 0x1a9 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x1d0435>;
|
|
port = <0x01>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
dpp,id = <0x07>;
|
|
dpuf,id = <0x00>;
|
|
dpp,video;
|
|
phandle = <0xe6>;
|
|
};
|
|
|
|
drmdpp@0x1AF00000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1af00000 0x1000 0x00 0x1af30000 0x1000 0x00 0x1af50000 0x1000 0x00 0x1af20000 0x500 0x00 0x1af40000 0x4000 0x00 0x1af60000 0x1000 0x00 0x1af3f000 0x1000 0x00 0x1af70000 0x1000>;
|
|
reg-names = "dma\0dpp\0sramc\0votf\0scl_coef\0hdr_comm\0dpp_debug\0mcd_hdr";
|
|
interrupts = <0x00 0x198 0x04 0x00 0x1aa 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x1d0005>;
|
|
port = <0x00>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
dpp,id = <0x08>;
|
|
dpuf,id = <0x01>;
|
|
phandle = <0xe7>;
|
|
};
|
|
|
|
drmdpp@0x1AF01000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1af01000 0x1000 0x00 0x1af31000 0x1000 0x00 0x1af51000 0x1000 0x00 0x1af20000 0x500 0x00 0x1af40000 0x4000 0x00 0x1af61000 0x1000 0x00 0x1af71000 0x1000>;
|
|
reg-names = "dma\0dpp\0sramc\0votf\0scl_coef\0hdr_comm\0mcd_hdr";
|
|
interrupts = <0x00 0x199 0x04 0x00 0x1ab 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x1d043d>;
|
|
port = <0x00>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
dpp,id = <0x09>;
|
|
dpuf,id = <0x01>;
|
|
dpp,video;
|
|
phandle = <0xe8>;
|
|
};
|
|
|
|
drmdpp@0x1AF02000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1af02000 0x1000 0x00 0x1af32000 0x1000 0x00 0x1af52000 0x1000 0x00 0x1af20000 0x500 0x00 0x1af40000 0x4000 0x00 0x1af62000 0x1000 0x00 0x1af72000 0x1000>;
|
|
reg-names = "dma\0dpp\0sramc\0votf\0scl_coef\0hdr_comm\0mcd_hdr";
|
|
interrupts = <0x00 0x19a 0x04 0x00 0x1ac 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x1d0005>;
|
|
port = <0x00>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
dpp,id = <0x0a>;
|
|
dpuf,id = <0x01>;
|
|
phandle = <0xe9>;
|
|
};
|
|
|
|
drmdpp@0x1AF03000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1af03000 0x1000 0x00 0x1af33000 0x1000 0x00 0x1af53000 0x1000 0x00 0x1af20000 0x500 0x00 0x1af40000 0x4000 0x00 0x1af63000 0x1000 0x00 0x1af73000 0x1000>;
|
|
reg-names = "dma\0dpp\0sramc\0votf\0scl_coef\0hdr_comm\0mcd_hdr";
|
|
interrupts = <0x00 0x19b 0x04 0x00 0x1ad 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x1d043d>;
|
|
port = <0x00>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
dpp,id = <0x0b>;
|
|
dpuf,id = <0x01>;
|
|
dpp,video;
|
|
phandle = <0xea>;
|
|
};
|
|
|
|
drmdpp@0x1AF04000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1af04000 0x1000 0x00 0x1af34000 0x1000 0x00 0x1af54000 0x1000 0x00 0x1af20000 0x500 0x00 0x1af40000 0x4000 0x00 0x1af64000 0x1000 0x00 0x1af74000 0x1000>;
|
|
reg-names = "dma\0dpp\0sramc\0votf\0scl_coef\0hdr_comm\0mcd_hdr";
|
|
interrupts = <0x00 0x19c 0x04 0x00 0x1ae 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x1d0005>;
|
|
port = <0x01>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
dpp,id = <0x0c>;
|
|
dpuf,id = <0x01>;
|
|
phandle = <0xeb>;
|
|
};
|
|
|
|
drmdpp@0x1AF05000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1af05000 0x1000 0x00 0x1af35000 0x1000 0x00 0x1af55000 0x1000 0x00 0x1af20000 0x500 0x00 0x1af40000 0x4000 0x00 0x1af65000 0x1000 0x00 0x1af75000 0x1000>;
|
|
reg-names = "dma\0dpp\0sramc\0votf\0scl_coef\0hdr_comm\0mcd_hdr";
|
|
interrupts = <0x00 0x19d 0x04 0x00 0x1af 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x1d0435>;
|
|
port = <0x01>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
dpp,id = <0x0d>;
|
|
dpuf,id = <0x01>;
|
|
dpp,video;
|
|
phandle = <0xec>;
|
|
};
|
|
|
|
drmdpp@0x1AF06000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1af06000 0x1000 0x00 0x1af36000 0x1000 0x00 0x1af56000 0x1000 0x00 0x1af20000 0x500 0x00 0x1af40000 0x4000 0x00 0x1af66000 0x1000 0x00 0x1af76000 0x1000>;
|
|
reg-names = "dma\0dpp\0sramc\0votf\0scl_coef\0hdr_comm\0mcd_hdr";
|
|
interrupts = <0x00 0x19e 0x04 0x00 0x1b0 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x1d0005>;
|
|
port = <0x01>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
dpp,id = <0x0e>;
|
|
dpuf,id = <0x01>;
|
|
phandle = <0xed>;
|
|
};
|
|
|
|
drmdpp@0x1AEB8000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1af07000 0x1000 0x00 0x1af37000 0x1000 0x00 0x1af57000 0x1000 0x00 0x1af20000 0x500 0x00 0x1af40000 0x4000 0x00 0x1af67000 0x1000 0x00 0x1af77000 0x1000>;
|
|
reg-names = "dma\0dpp\0sramc\0votf\0scl_coef\0hdr_comm\0mcd_hdr";
|
|
interrupts = <0x00 0x19f 0x04 0x00 0x1b1 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x1d0435>;
|
|
port = <0x01>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
dpp,id = <0x0f>;
|
|
dpuf,id = <0x01>;
|
|
dpp,video;
|
|
phandle = <0xee>;
|
|
};
|
|
|
|
drmdpp@0x1AD08000 {
|
|
compatible = "samsung,exynos-writeback";
|
|
reg = <0x00 0x1ad08000 0x1000 0x00 0x1ad38000 0x1000 0x00 0x1ad20000 0x10000 0x00 0x18700000 0x10000>;
|
|
reg-names = "dma\0dpp\0votf\0votf_mfc";
|
|
interrupts = <0x00 0x1a0 0x04>;
|
|
interrupt-names = "dma";
|
|
iommus = <0xd3 0xd4 0xd5 0xd6>;
|
|
samsung,iommu-group = <0xd7>;
|
|
attr = <0x60010>;
|
|
port = <0x00>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
votf_o,enabled;
|
|
dpp,id = <0x10>;
|
|
dpuf,id = <0x00>;
|
|
phandle = <0x2d9>;
|
|
};
|
|
|
|
drmdpp@0x1AF08000 {
|
|
compatible = "samsung,exynos-writeback";
|
|
reg = <0x00 0x1af08000 0x1000 0x00 0x1af38000 0x1000>;
|
|
reg-names = "dma\0dpp";
|
|
interrupts = <0x00 0x1a1 0x04>;
|
|
interrupt-names = "dma";
|
|
attr = <0x60010>;
|
|
port = <0x00>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
dpp,id = <0x11>;
|
|
dpuf,id = <0x01>;
|
|
phandle = <0x2da>;
|
|
};
|
|
|
|
fcmd@0x19CBC000 {
|
|
compatible = "samsung,exynos-dsimfc";
|
|
reg = <0x00 0x1ad0a000 0x1000>;
|
|
interrupts = <0x00 0x18d 0x04>;
|
|
port = <0x00>;
|
|
phandle = <0x2db>;
|
|
};
|
|
|
|
fcmd@0x19CBD000 {
|
|
compatible = "samsung,exynos-dsimfc";
|
|
reg = <0x00 0x1ad0b000 0x1000>;
|
|
interrupts = <0x00 0x18e 0x04>;
|
|
port = <0x01>;
|
|
phandle = <0x2dc>;
|
|
};
|
|
|
|
fcmd@0x1AEBC000 {
|
|
compatible = "samsung,exynos-dsimfc";
|
|
reg = <0x00 0x1af0a000 0x1000>;
|
|
interrupts = <0x00 0x18f 0x04>;
|
|
port = <0x00>;
|
|
phandle = <0x2dd>;
|
|
};
|
|
|
|
disp_ss@0x19E20000 {
|
|
compatible = "samsung,exynos9-disp_ss";
|
|
reg = <0x00 0x19e21000 0x10>;
|
|
reg-names = "sys";
|
|
phandle = <0x2de>;
|
|
};
|
|
|
|
dphy_m4m4_dsim0@0x15860000 {
|
|
compatible = "samsung,mipi-phy-m4m4-top";
|
|
samsung,pmu-syscon = <0xd8>;
|
|
isolation = <0x714>;
|
|
owner = <0x00>;
|
|
#phy-cells = <0x01>;
|
|
phandle = <0xd9>;
|
|
};
|
|
|
|
drmdsim@0x19EC0000 {
|
|
compatible = "samsung,exynos-dsim";
|
|
reg = <0x00 0x19eb0000 0x300 0x00 0x19ee0100 0x700 0x00 0x19ee0000 0x100 0x00 0x189e0000 0x10000>;
|
|
reg-names = "dsi\0dphy\0dphy-extra\0votf";
|
|
dsim,id = <0x00>;
|
|
interrupts = <0x00 0x17f 0x04>;
|
|
interrupt-names = "dsim";
|
|
iommus = <0xd3 0xd4 0xd5 0xd6>;
|
|
samsung,iommu-group = <0xd7>;
|
|
phys = <0xd9 0x00>;
|
|
phy-names = "dsim_dphy";
|
|
dsim_mode = <0xda>;
|
|
dsi-burst-cmd = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0x2df>;
|
|
};
|
|
|
|
drmdp@0x10A80000 {
|
|
compatible = "samsung,exynos-dp";
|
|
reg = <0x00 0x10a80000 0x6da8 0x00 0x10ad0000 0x250 0x00 0x10ae0000 0xfc>;
|
|
reg-names = "dp_link\0usbdpphy_ctrl\0usbdpphy_tca_ctrl";
|
|
interrupts = <0x00 0x1df 0x04>;
|
|
interrupt-names = "dp";
|
|
power-domains = <0xdb>;
|
|
clock-names = "aclk\0dposc_clk";
|
|
clocks = <0x19 0x258 0x19 0x384>;
|
|
phandle = <0x2e0>;
|
|
};
|
|
|
|
drmdecon@0x19F00000 {
|
|
compatible = "samsung,exynos-decon";
|
|
reg = <0x00 0x19f00000 0xffff 0x00 0x19f10000 0xffff 0x00 0x19f20000 0xffff 0x00 0x19f30000 0xffff 0x00 0x1ad58000 0x1000 0x00 0x1af58000 0x1000 0x00 0x1ad0e000 0x1000 0x00 0x19f70000 0xffff>;
|
|
reg-names = "main\0win\0sub\0wincon\0sramc_d\0sramc1_d\0edma\0dqe";
|
|
decon,id = <0x00>;
|
|
interrupts = <0x00 0x173 0x04 0x00 0x172 0x04 0x00 0x171 0x04 0x00 0x18b 0x04 0x00 0x1b4 0x04>;
|
|
interrupt-names = "frame_start\0frame_done\0extra\0edma\0sramc_d";
|
|
iommus = <0xd3 0xd4 0xd5 0xd6>;
|
|
samsung,iommu-group = <0xd7>;
|
|
samsung,tzmp;
|
|
clock-names = "aclk";
|
|
clocks = <0x19 0x258>;
|
|
pinctrl-names = "hw_te_on\0hw_te_off";
|
|
pinctrl-0 = <0xdc>;
|
|
pinctrl-1 = <0xdd>;
|
|
max_win = <0x10>;
|
|
op_mode = <0x01>;
|
|
trig_mode = <0x00>;
|
|
out_type = <0x01>;
|
|
te_from = <0x00>;
|
|
svsync_time_us = <0xbb8>;
|
|
ppc = <0x02>;
|
|
ppc_rotator = <0x08>;
|
|
ppc_scaler = <0x04>;
|
|
delay_comp = <0x04>;
|
|
delay_scaler = <0x03>;
|
|
inner_width = <0x20>;
|
|
bus_width = <0x20>;
|
|
rot_util = <0x3c>;
|
|
dfs_lv_cnt = <0x09>;
|
|
dfs_lv = <0xc3500 0xa1dd8 0x82208 0x72420 0x61a80 0x510e0 0x30d40 0x20788 0xc350>;
|
|
rd_en = <0x00>;
|
|
rd_hi_thres = <0x800>;
|
|
rd_lo_thres = <0x400>;
|
|
rd_wait_cycle = <0x10>;
|
|
wr_en = <0x00>;
|
|
wr_hi_thres = <0x00>;
|
|
wr_lo_thres = <0x00>;
|
|
dta_en = <0x00>;
|
|
dta_hi_thres = <0x3200>;
|
|
dta_lo_thres = <0x600>;
|
|
dqe_preset_cnt = <0x02>;
|
|
dqe_preset = <0xffff0002 0xffff0003 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff>;
|
|
gpios = <0xde 0x00 0x0f>;
|
|
dpps = <0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee>;
|
|
connector = <0x01 0x02 0x08>;
|
|
hibernation;
|
|
partial-update;
|
|
recovery-max-count = <0x0a>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
phandle = <0x160>;
|
|
|
|
te_eint {
|
|
reg = <0x00 0x10430a24 0x04>;
|
|
};
|
|
};
|
|
|
|
drmdecon@0x19F01000 {
|
|
compatible = "samsung,exynos-decon";
|
|
reg = <0x00 0x19f01000 0xffff 0x00 0x19f10000 0xffff 0x00 0x19f20000 0xffff 0x00 0x19f40000 0xffff 0x00 0x1ad59000 0x1000 0x00 0x1af59000 0x1000>;
|
|
reg-names = "main\0win\0sub\0wincon\0sramc_d\0sramc1_d";
|
|
decon,id = <0x01>;
|
|
interrupts = <0x00 0x178 0x04 0x00 0x177 0x04 0x00 0x176 0x04 0x00 0x1b5 0x04>;
|
|
interrupt-names = "frame_start\0frame_done\0extra\0sramc_d";
|
|
iommus = <0xd3 0xd4 0xd5 0xd6>;
|
|
samsung,iommu-group = <0xd7>;
|
|
samsung,tzmp;
|
|
clock-names = "aclk";
|
|
clocks = <0x19 0x258>;
|
|
max_win = <0x10>;
|
|
op_mode = <0x01>;
|
|
trig_mode = <0x01>;
|
|
out_type = <0x100>;
|
|
te_from = <0x00>;
|
|
ppc = <0x02>;
|
|
ppc_rotator = <0x08>;
|
|
ppc_scaler = <0x04>;
|
|
delay_comp = <0x04>;
|
|
delay_scaler = <0x03>;
|
|
inner_width = <0x20>;
|
|
bus_width = <0x20>;
|
|
rot_util = <0x3c>;
|
|
dfs_lv_cnt = <0x09>;
|
|
dfs_lv = <0xc3500 0xa1dd8 0x82208 0x72420 0x61a80 0x510e0 0x30d40 0x20788 0xc350>;
|
|
dpps = <0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee>;
|
|
connector = <0x08>;
|
|
phandle = <0x2e1>;
|
|
};
|
|
|
|
drmdecon@0x19F02000 {
|
|
compatible = "samsung,exynos-decon";
|
|
reg = <0x00 0x19f02000 0xffff 0x00 0x19f10000 0xffff 0x00 0x19f20000 0xffff 0x00 0x19f50000 0xffff 0x00 0x1ad5a000 0x1000 0x00 0x1af5a000 0x1000>;
|
|
reg-names = "main\0win\0sub\0wincon\0sramc_d\0sramc1_d";
|
|
decon,id = <0x02>;
|
|
interrupts = <0x00 0x17b 0x04 0x00 0x17a 0x04 0x00 0x179 0x04 0x00 0x1b6 0x04>;
|
|
interrupt-names = "frame_start\0frame_done\0extra\0sramc_d";
|
|
iommus = <0xd3 0xd4 0xd5 0xd6>;
|
|
samsung,iommu-group = <0xd7>;
|
|
samsung,tzmp;
|
|
clock-names = "aclk";
|
|
clocks = <0x19 0x258>;
|
|
max_win = <0x10>;
|
|
op_mode = <0x00>;
|
|
trig_mode = <0x00>;
|
|
out_type = <0x10>;
|
|
te_from = <0x00>;
|
|
ppc = <0x02>;
|
|
ppc_rotator = <0x08>;
|
|
ppc_scaler = <0x04>;
|
|
delay_comp = <0x04>;
|
|
delay_scaler = <0x03>;
|
|
inner_width = <0x20>;
|
|
bus_width = <0x20>;
|
|
rot_util = <0x3c>;
|
|
dfs_lv_cnt = <0x09>;
|
|
dfs_lv = <0xc3500 0xa1dd8 0x82208 0x72420 0x61a80 0x510e0 0x30d40 0x20788 0xc350>;
|
|
dpps = <0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee>;
|
|
connector = <0x10>;
|
|
phandle = <0x2e2>;
|
|
};
|
|
|
|
drmdecon@0x19F03000 {
|
|
compatible = "samsung,exynos-decon";
|
|
reg = <0x00 0x19f03000 0xffff 0x00 0x19f10000 0xffff 0x00 0x19f20000 0xffff 0x00 0x19f60000 0xffff 0x00 0x1ad5b000 0x1000 0x00 0x1af5b000 0x1000>;
|
|
reg-names = "main\0win\0sub\0wincon\0sramc_d\0sramc1_d";
|
|
decon,id = <0x03>;
|
|
interrupts = <0x00 0x17e 0x04 0x00 0x17d 0x04 0x00 0x17c 0x04 0x00 0x1b7 0x04>;
|
|
interrupt-names = "frame_start\0frame_done\0extra\0sramc_d";
|
|
iommus = <0xd3 0xd4 0xd5 0xd6>;
|
|
samsung,iommu-group = <0xd7>;
|
|
samsung,tzmp;
|
|
clock-names = "aclk";
|
|
clocks = <0x19 0x258>;
|
|
max_win = <0x10>;
|
|
op_mode = <0x00>;
|
|
trig_mode = <0x00>;
|
|
out_type = <0x10>;
|
|
te_from = <0x00>;
|
|
ppc = <0x02>;
|
|
ppc_rotator = <0x08>;
|
|
ppc_scaler = <0x04>;
|
|
delay_comp = <0x04>;
|
|
delay_scaler = <0x03>;
|
|
inner_width = <0x20>;
|
|
bus_width = <0x20>;
|
|
rot_util = <0x3c>;
|
|
dfs_lv_cnt = <0x09>;
|
|
dfs_lv = <0xc3500 0xa1dd8 0x82208 0x72420 0x61a80 0x510e0 0x30d40 0x20788 0xc350>;
|
|
dpps = <0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee>;
|
|
connector = <0x100>;
|
|
phandle = <0x2e3>;
|
|
};
|
|
|
|
dpu_debug {
|
|
compatible = "samsung,dpu-debug";
|
|
};
|
|
|
|
sysreg_hsi0@10A20000 {
|
|
compatible = "samsung,sysreg-hsi0\0syscon";
|
|
reg = <0x00 0x10a20000 0x10000>;
|
|
phandle = <0xef>;
|
|
};
|
|
|
|
exynos-usb-audio-offloading {
|
|
compatible = "exynos-usb-audio-offloading";
|
|
};
|
|
|
|
usb@10B00000 {
|
|
compatible = "samsung,exynos-dwusb";
|
|
clocks = <0x19 0x387 0x19 0x385>;
|
|
clock-names = "aclk\0sclk";
|
|
reg = <0x00 0x10b00000 0x10000>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
status = "disabled";
|
|
power-domains = <0xdb>;
|
|
samsung,sysreg-hsi0 = <0xef>;
|
|
interrupts = <0x00 0x1e5 0x04>;
|
|
tx-fifo-resize = <0x00>;
|
|
exynos,adj-sof-accuracy = <0x01>;
|
|
exynos,usb_host_device_timeout = <0xc8>;
|
|
exynos,enable_sprs_transfer = <0x01>;
|
|
samsung,no-extra-delay;
|
|
usb_host_device_timeout = <0x7ff>;
|
|
exynos,xhci_l2_support = <0x01>;
|
|
exynos,force_gen1;
|
|
phys = <0xf0 0x00 0xf0 0x01>;
|
|
phy-names = "usb2-phy\0usb3-phy";
|
|
phandle = <0xf1>;
|
|
|
|
dwc3 {
|
|
compatible = "synopsys,dwc3";
|
|
reg = <0x00 0x10b00000 0x10000>;
|
|
interrupts = <0x00 0x1e5 0x04>;
|
|
dr_mode = "peripheral";
|
|
phys = <0xf0 0x00 0xf0 0x01>;
|
|
phy-names = "usb2-phy\0usb3-phy";
|
|
usb_audio_offloading = <0x01>;
|
|
usb-pm-qos-hsi0 = <0x30d40>;
|
|
usb-pm-qos-int = <0x61a80>;
|
|
snps,quirk-frame-length-adjustment = <0x20>;
|
|
snps,has-lpm-erratum;
|
|
snps,lpm-nyet-threshold = <0x00>;
|
|
snps,dis-u2-freeclk-exists-quirk;
|
|
phandle = <0x2e4>;
|
|
};
|
|
};
|
|
|
|
phy@10AA0000 {
|
|
compatible = "samsung,exynos-usbdrd-phy";
|
|
reg = <0x00 0x10aa0000 0x200 0x00 0x10ab0000 0x200 0x00 0x10ac0000 0x200 0x00 0x10ad0000 0x800 0x00 0x10ae0000 0x800 0x00 0x10b00000 0x10000>;
|
|
interrupts = <0x00 0x1e3 0x04 0x00 0x1e1 0x04 0x00 0x1e7 0x04>;
|
|
clocks = <0x19 0x386 0x19 0x387>;
|
|
clock-names = "ext_xtal\0aclk";
|
|
samsung,pmu-syscon = <0xd8>;
|
|
power-domains = <0xdb>;
|
|
pmu_mask = <0x00>;
|
|
pmu_offset = <0x72c>;
|
|
pmu_offset_dp = <0x730>;
|
|
phy_version = <0x301>;
|
|
phyclk_mux = "none";
|
|
phy_refclk = "ext_xtal";
|
|
has_other_phy = <0x00>;
|
|
has_combo_phy = <0x01>;
|
|
sub_phy_version = <0x400>;
|
|
ip_type = <0x00>;
|
|
phy_refsel_clockcore = <0x01>;
|
|
phy_refsel_ext_osc = <0x00>;
|
|
phy_refsel_xtal = <0x00>;
|
|
phy_refsel_diff_pad = <0x00>;
|
|
phy_refsel_diff_internal = <0x00>;
|
|
phy_refsel_diff_single = <0x00>;
|
|
use_io_for_ovc = <0x00>;
|
|
common_block_disable = <0x01>;
|
|
is_not_vbus_pad = <0x01>;
|
|
used_phy_port = <0x00>;
|
|
status = "disabled";
|
|
#phy-cells = <0x01>;
|
|
ranges;
|
|
phandle = <0xf0>;
|
|
};
|
|
|
|
usb_notifier {
|
|
compatible = "samsung,usb-notifier";
|
|
udc = <0xf1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie@113B0000 {
|
|
compatible = "samsung,exynos-pcie-rc";
|
|
gpios = <0xf2 0x01 0x01>;
|
|
reg = <0x00 0x113b0000 0x2000 0x00 0x113c0000 0x5000 0x00 0x113e0000 0x3000 0x00 0x113f0000 0xd000 0x00 0x11220700 0x04 0x00 0x11221050 0x10 0x00 0x11800000 0x381000 0x00 0x113d0000 0x5000 0x00 0x28000000 0x2000 0x00 0x11390000 0x1000>;
|
|
reg-names = "elbi\0soc\0phy\0phyudbg\0sysreg_iocc\0sysreg\0dbi\0pcs\0config\0ia";
|
|
interrupts = <0x00 0x1ee 0x04>;
|
|
#interrupt-cells = <0x01>;
|
|
interrupt-map-mask = <0x00 0x00 0x00 0x00>;
|
|
interrupt-map = <0x00 0x00 0x00 0x00 0x01 0x00 0x1ee 0x04>;
|
|
samsung,syscon-phandle = <0xd8>;
|
|
pinctrl-names = "active\0idle";
|
|
pinctrl-0 = <0xf3 0xf4>;
|
|
pinctrl-1 = <0xf3 0xf4>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x02>;
|
|
device_type = "pci";
|
|
ranges = <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x8000000>;
|
|
ip-ver = <0x992500>;
|
|
ep-ver = <0x4375>;
|
|
num-lanes = <0x01>;
|
|
ch-num = <0x00>;
|
|
pcie-pm-qos-int = <0x412f8>;
|
|
use-cache-coherency = "false";
|
|
use-msi = "false";
|
|
use-sicd = "true";
|
|
use-sysmmu = "false";
|
|
use-ia = "false";
|
|
pmu-offset = <0x71c>;
|
|
pmu-offset1 = <0xab0>;
|
|
pmu-offset2 = <0x3b20>;
|
|
use-nclkoff-en = "false";
|
|
max-link-speed = <0x02>;
|
|
power-domains = <0xf5>;
|
|
status = "disabled";
|
|
phandle = <0x2e5>;
|
|
};
|
|
|
|
pcie@11320000 {
|
|
compatible = "samsung,exynos-pcie-rc";
|
|
gpios = <0xf2 0x03 0x01>;
|
|
reg = <0x00 0x11320000 0x2000 0x00 0x11330000 0x5000 0x00 0x11350000 0x3000 0x00 0x11360000 0xd000 0x00 0x11220700 0x04 0x00 0x11221060 0x10 0x00 0x11400000 0x381000 0x00 0x11340000 0x5000 0x00 0x40ffe000 0x2000 0x00 0x11300000 0x1000>;
|
|
reg-names = "elbi\0soc\0phy\0phyudbg\0sysreg_iocc\0sysreg\0dbi\0pcs\0config\0ia";
|
|
interrupts = <0x00 0x1f4 0x04>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <0x01>;
|
|
samsung,syscon-phandle = <0xd8>;
|
|
pinctrl-names = "active\0idle";
|
|
pinctrl-0 = <0xf6 0xf7>;
|
|
pinctrl-1 = <0xf3 0xf4>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x02>;
|
|
device_type = "pci";
|
|
ranges = <0x82000000 0x00 0x14e00000 0x00 0x40000000 0x00 0xff0000>;
|
|
ip-ver = <0x992500>;
|
|
num-lanes = <0x02>;
|
|
ch-num = <0x01>;
|
|
pcie-pm-qos-int = <0x412f8>;
|
|
use-cache-coherency = "false";
|
|
use-pcieon-sleep = "true";
|
|
use-msi = "false";
|
|
use-sicd = "true";
|
|
use-sysmmu = "false";
|
|
use-ia = "false";
|
|
pmu-offset = <0x720>;
|
|
pmu-offset1 = <0xab4>;
|
|
pmu-offset2 = <0x3b20>;
|
|
max-link-speed = <0x03>;
|
|
power-domains = <0xf5>;
|
|
status = "disabled";
|
|
phandle = <0x2e6>;
|
|
};
|
|
|
|
sysmmu@11280000 {
|
|
compatible = "samsung,pcie-sysmmu";
|
|
reg = <0x00 0x11280000 0x10000>;
|
|
interrupts = <0x00 0x1ff 0x04>;
|
|
qos = <0x0f>;
|
|
port-name = "PCIe";
|
|
#iommu-cells = <0x00>;
|
|
power-domains = <0xf5>;
|
|
phandle = <0x2e7>;
|
|
};
|
|
|
|
sysreg_ufs@11020000 {
|
|
compatible = "samsung,s5e9925-sysreg-ufs\0syscon";
|
|
reg = <0x00 0x11020000 0x1000>;
|
|
phandle = <0xfa>;
|
|
};
|
|
|
|
ufs@0x11100000 {
|
|
compatible = "samsung,exynos-ufs";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
reg = <0x00 0x11100000 0x200 0x00 0x11101100 0x2000 0x00 0x11180000 0x8000 0x00 0x111a0000 0xa014 0x00 0x11104000 0x4000 0x00 0x11108000 0x804>;
|
|
interrupts = <0x00 0x229 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0xf8 0xf9>;
|
|
clocks = <0x19 0x3e8 0x19 0x3e9>;
|
|
clock-names = "GATE_UFS_EMBD\0UFS_EMBD";
|
|
brd-for-cal = [01];
|
|
freq-table-hz = <0x00 0x00 0x00 0x00>;
|
|
ufs,pmd-attr-lane = [02];
|
|
ufs,pmd-attr-gear = [04];
|
|
evt-ver = [01];
|
|
dma-coherent;
|
|
samsung,pmu-phandle = <0xd8>;
|
|
samsung,sysreg-phandle = <0xfa>;
|
|
fixed-prdt-req_list-ocs;
|
|
phandle = <0x2e8>;
|
|
|
|
phy-tcxo-con {
|
|
offset = <0x3e10>;
|
|
mask = <0x08>;
|
|
val = <0x08>;
|
|
};
|
|
|
|
ufs-phy-iso {
|
|
offset = <0x728>;
|
|
mask = <0x01>;
|
|
val = <0x01>;
|
|
};
|
|
|
|
ufs-iocc {
|
|
offset = <0x700>;
|
|
mask = <0x300000>;
|
|
val = <0x300000>;
|
|
};
|
|
|
|
ufs-pm-qos {
|
|
freq-int = <0x510e0>;
|
|
perf-int = "\0\f5";
|
|
perf-mif = <0x3066a0>;
|
|
cpufreq-qos-levels = <0x06 0x06 0x04>;
|
|
};
|
|
|
|
ufs-protector {
|
|
valid-check = [00];
|
|
};
|
|
};
|
|
|
|
dpm {
|
|
phandle = <0x2e9>;
|
|
};
|
|
|
|
dss {
|
|
compatible = "samsung,debug-snapshot";
|
|
panic_to_wdt = <0x00>;
|
|
last_kmsg = <0x01>;
|
|
hold-key = <0x72>;
|
|
trigger-key = <0x74>;
|
|
scratch-offset = <0x810>;
|
|
scratch-bit = <0x06>;
|
|
wa-pre-reading-ecc-sysreg = <0x82000530 0x10000 0x00 0x00>;
|
|
freq_names = "LIT\0MID\0BIG\0INT\0MIF\0CAM\0DISP\0INTCAM\0AUD\0MFC0\0NPU\0DSU\0DNC\0CSIS\0ISP\0MFC1\0DSP\0ALIVE\0CHUB\0VTS\0HSI0\0G3D";
|
|
memory-region = <0xfb 0xfc 0xfd 0xfe 0xff 0x100 0x101 0x102 0x103>;
|
|
phandle = <0x2ea>;
|
|
};
|
|
|
|
dss-qdump {
|
|
compatible = "debug-snapshot,qdump";
|
|
};
|
|
|
|
dss-sfrdump {
|
|
compatible = "debug-snapshot,sfrdump";
|
|
};
|
|
|
|
dss-debug-kinfo {
|
|
compatible = "samsung,debug-snapshot-debug-kinfo";
|
|
memory-region = <0x104>;
|
|
};
|
|
|
|
debug-kinfo {
|
|
compatible = "google,debug-kinfo";
|
|
memory-region = <0x104>;
|
|
};
|
|
|
|
hardlockup-watchdog {
|
|
compatible = "samsung,hardlockup-watchdog";
|
|
};
|
|
|
|
exynos-debug-test {
|
|
compatible = "samsung,exynos-debug-test";
|
|
ps_hold_control_offset = <0x30c>;
|
|
scratch-offset = <0x810>;
|
|
dram-init-bit = <0x04>;
|
|
nr_cpu = <0x08>;
|
|
nr_little_cpu = <0x04>;
|
|
nr_mid_cpu = <0x03>;
|
|
nr_big_cpu = <0x01>;
|
|
little_cpu_start = <0x00>;
|
|
mid_cpu_start = <0x04>;
|
|
big_cpu_start = <0x07>;
|
|
};
|
|
|
|
exynos-ecc-handler {
|
|
compatible = "samsung,exynos-ecc-handler";
|
|
interrupts = <0x00 0xbb 0x04 0x00 0xbf 0x04 0x00 0xc0 0x04 0x00 0xc3 0x04 0x00 0xc4 0x04 0x00 0xc5 0x04 0x00 0xc6 0x04 0x00 0xc7 0x04 0x00 0xc8 0x04 0x00 0xc9 0x04 0x00 0xca 0x04>;
|
|
interrupt-names = "Uncorrectable errors on the L3 data, tag or snoop filter RAMs\0Core0-1 Complex, Uncorrectable errors on the L2 data or tag RAMs\0Core2-3 Complex, Uncorrectable errors on the L2 data or tag RAMs\0Core0, Uncorrectable errors on the L1 data or tag RAMs\0Core1, Uncorrectable errors on the L1 data or tag RAMs\0Core2, Uncorrectable errors on the L1 data or tag RAMs\0Core3, Uncorrectable errors on the L1 data or tag RAMs\0Core4, Uncorrectable errors on the L1 data, tag or L2 data, tag RAMs\0Core5, Uncorrectable errors on the L1 data, tag or L2 data, tag RAMs\0Core6, Uncorrectable errors on the L1 data, tag or L2 data, tag RAMs\0Core7, Uncorrectable errors on the L1 data, tag or L2 data, tag RAMs";
|
|
interrupt-affinity = <0xff 0x03 0x0c 0x01 0x02 0x04 0x08 0x10 0x20 0x40 0x80>;
|
|
};
|
|
|
|
coresight {
|
|
compatible = "samsung,exynos-coresight";
|
|
dbg_base = <0x5010000 0x5110000 0x5210000 0x5310000 0x5410000 0x5510000 0x5610000 0x5710000>;
|
|
cti_base = <0x4010000 0x4020000 0x4030000 0x4040000 0x4050000 0x4060000 0x4070000 0x4080000>;
|
|
pmu_base = <0x5020000 0x5120000 0x5220000 0x5320000 0x5420000 0x5520000 0x5620000 0x5720000>;
|
|
gpr_base = <0x4001000>;
|
|
dbgack-mask = <0xff00000>;
|
|
halt = <0x00>;
|
|
retention = <0x00>;
|
|
};
|
|
|
|
exynos-adv_tracer {
|
|
compatible = "samsung,exynos-adv-tracer";
|
|
reg = <0x00 0x158d0000 0x1000>;
|
|
reg-names = "mailbox";
|
|
interrupts = <0x00 0x30 0x04>;
|
|
status = "ok";
|
|
};
|
|
|
|
exynos_adv_tracer_s2d {
|
|
compatible = "samsung,exynos-adv-tracer-s2d";
|
|
plugin-len = <0x03>;
|
|
plugin-name = "S2D";
|
|
pmu-burnin-ctrl = <0xa08>;
|
|
sel-scanmode-bit = <0x19>;
|
|
dbgsel-sw-bit = <0x04>;
|
|
status = "ok";
|
|
phandle = <0x2eb>;
|
|
};
|
|
|
|
exynos-itmon {
|
|
compatible = "samsung,exynos-itmon";
|
|
memory-region = <0x105>;
|
|
interrupts = <0x00 0x3ab 0x04 0x00 0x205 0x04 0x00 0x20c 0x04>;
|
|
interrupt-affinity = <0xff 0x01 0x01>;
|
|
support-irq-oring;
|
|
no-support-cpu-parsing;
|
|
big-bus-supporting;
|
|
status = "ok";
|
|
phandle = <0x2ec>;
|
|
|
|
dbgc {
|
|
plugin-len = <0x03>;
|
|
plugin-name = "ITM";
|
|
phandle = <0x2ed>;
|
|
};
|
|
};
|
|
|
|
exynos-ehld {
|
|
compatible = "samsung,exynos-ehld";
|
|
reg = <0x00 0x1d0d0000 0x1000 0x00 0x1d0e0000 0x1000 0x00 0x1d0b0000 0x1000 0x00 0x1d0c0000 0x1000>;
|
|
cs_base = <0x5000000>;
|
|
version = <0x03>;
|
|
|
|
cpu0 {
|
|
dbg-offset = <0x00>;
|
|
};
|
|
|
|
cpu1 {
|
|
dbg-offset = <0x100000>;
|
|
};
|
|
|
|
cpu2 {
|
|
dbg-offset = <0x200000>;
|
|
};
|
|
|
|
cpu3 {
|
|
dbg-offset = <0x300000>;
|
|
};
|
|
|
|
cpu4 {
|
|
dbg-offset = <0x400000>;
|
|
};
|
|
|
|
cpu5 {
|
|
dbg-offset = <0x500000>;
|
|
};
|
|
|
|
cpu6 {
|
|
dbg-offset = <0x600000>;
|
|
};
|
|
|
|
cpu7 {
|
|
dbg-offset = <0x700000>;
|
|
};
|
|
|
|
dbgc {
|
|
plugin-len = <0x04>;
|
|
plugin-name = "ELD";
|
|
support = <0x01>;
|
|
interval = <0x64>;
|
|
threshold = <0x5000000>;
|
|
judge = <0x01>;
|
|
phandle = <0x2ee>;
|
|
};
|
|
};
|
|
|
|
etf0@4004000 {
|
|
compatible = "arm,coresight-tmc\0arm,primecell";
|
|
arm,primecell-periphid = <0x1bb961>;
|
|
reg = <0x00 0x4004000 0x1000>;
|
|
clocks = <0x19 0xaf0>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x2ef>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x106>;
|
|
phandle = <0x10c>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x107>;
|
|
phandle = <0x110>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etf1@4005000 {
|
|
compatible = "arm,coresight-tmc\0arm,primecell";
|
|
arm,primecell-periphid = <0x1bb961>;
|
|
reg = <0x00 0x4005000 0x1000>;
|
|
clocks = <0x19 0xaf0>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x2f0>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x108>;
|
|
phandle = <0x10d>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x109>;
|
|
phandle = <0x111>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etr@400a000 {
|
|
compatible = "arm,coresight-tmc\0arm,primecell";
|
|
arm,primecell-periphid = <0x1bb961>;
|
|
reg = <0x00 0x400a000 0x1000>;
|
|
clocks = <0x19 0xaf0>;
|
|
clock-names = "apb_pclk";
|
|
samsung,cs-sfr = <0x400a000 0x100>;
|
|
samsung,q-offset = <0x2c>;
|
|
phandle = <0x2f1>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x10a>;
|
|
phandle = <0x10f>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
stm0@400b000 {
|
|
compatible = "arm,coresight-stm\0arm,primecell";
|
|
arm,primecell-periphid = <0xbb963>;
|
|
reg = <0x00 0x400b000 0x1000 0x00 0x6000000 0x2000000>;
|
|
reg-names = "stm-base\0stm-stimulus-base";
|
|
clocks = <0x19 0xaf0>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x10b>;
|
|
phandle = <0x10e>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel0@4007000 {
|
|
compatible = "arm,coresight-funnel\0arm,primecell";
|
|
arm,primecell-periphid = <0x1bb908>;
|
|
reg = <0x00 0x4007000 0x1000>;
|
|
clocks = <0x19 0xaf0>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x2f2>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x10c>;
|
|
phandle = <0x106>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
};
|
|
};
|
|
|
|
funnel1@4008000 {
|
|
compatible = "arm,coresight-funnel\0arm,primecell";
|
|
arm,primecell-periphid = <0x1bb908>;
|
|
reg = <0x00 0x4008000 0x1000>;
|
|
clocks = <0x19 0xaf0>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x2f3>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x10d>;
|
|
phandle = <0x108>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@7 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x10e>;
|
|
phandle = <0x10b>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnelm@4009000 {
|
|
compatible = "arm,coresight-funnel\0arm,primecell";
|
|
reg = <0x00 0x4009000 0x1000>;
|
|
clocks = <0x19 0xaf0>;
|
|
clock-names = "apb_pclk";
|
|
arm,primecell-periphid = <0x1bb908>;
|
|
phandle = <0x2f4>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x10f>;
|
|
phandle = <0x10a>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x110>;
|
|
phandle = <0x107>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0x111>;
|
|
phandle = <0x109>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
exynos-dm@17000000 {
|
|
compatible = "samsung,exynos-dvfs-manager";
|
|
reg = <0x00 0x17000000 0x00>;
|
|
acpm-ipc-channel = <0x01>;
|
|
phandle = <0x2f5>;
|
|
|
|
dm_domains {
|
|
|
|
cpufreq_cl0 {
|
|
dm-index = <0x00>;
|
|
available = "true";
|
|
cal_id = <0xb040002>;
|
|
dm_type_name = "dm_cpu_cl0";
|
|
fast_switch;
|
|
};
|
|
|
|
cpufreq_cl1 {
|
|
dm-index = <0x01>;
|
|
available = "true";
|
|
cal_id = <0xb040003>;
|
|
dm_type_name = "dm_cpu_cl1";
|
|
fast_switch;
|
|
};
|
|
|
|
cpufreq_cl2 {
|
|
dm-index = <0x02>;
|
|
available = "true";
|
|
cal_id = <0xb040004>;
|
|
dm_type_name = "dm_cpu_cl2";
|
|
fast_switch;
|
|
};
|
|
|
|
devfreq_mif {
|
|
dm-index = <0x03>;
|
|
available = "true";
|
|
policy_use = "true";
|
|
cal_id = <0xb040000>;
|
|
dm_type_name = "dm_mif";
|
|
};
|
|
|
|
devfreq_int {
|
|
dm-index = <0x04>;
|
|
available = "true";
|
|
policy_use = "true";
|
|
cal_id = <0xb040001>;
|
|
dm_type_name = "dm_int";
|
|
};
|
|
|
|
devfreq_npu {
|
|
dm-index = <0x05>;
|
|
available = "true";
|
|
cal_id = <0xb040005>;
|
|
dm_type_name = "dm_npu";
|
|
};
|
|
|
|
devfreq_disp {
|
|
dm-index = <0x07>;
|
|
available = "true";
|
|
cal_id = <0xb040007>;
|
|
dm_type_name = "dm_disp";
|
|
};
|
|
|
|
devfreq_aud {
|
|
dm-index = <0x08>;
|
|
available = "true";
|
|
cal_id = <0xb040008>;
|
|
dm_type_name = "dm_aud";
|
|
};
|
|
|
|
devfreq_GPU {
|
|
dm-index = <0x09>;
|
|
available = "false";
|
|
cal_id = <0xb04000d>;
|
|
dm_type_name = "dm_gpu";
|
|
};
|
|
|
|
devfreq_intcam {
|
|
dm-index = <0x0a>;
|
|
available = "true";
|
|
cal_id = <0xb04000e>;
|
|
dm_type_name = "dm_intcam";
|
|
};
|
|
|
|
devfreq_cam {
|
|
dm-index = <0x0b>;
|
|
available = "true";
|
|
cal_id = <0xb04000f>;
|
|
dm_type_name = "dm_cam";
|
|
};
|
|
|
|
devfreq_dsu {
|
|
dm-index = <0x06>;
|
|
available = "true";
|
|
cal_id = <0xb040006>;
|
|
dm_type_name = "dm_dsu";
|
|
};
|
|
|
|
devfreq_mfc0 {
|
|
dm-index = <0x0e>;
|
|
available = "true";
|
|
cal_id = <0xb040012>;
|
|
dm_type_name = "dm_mfc0";
|
|
};
|
|
|
|
devfreq_csis {
|
|
dm-index = <0x0c>;
|
|
available = "true";
|
|
cal_id = <0xb040010>;
|
|
dm_type_name = "dm_csis";
|
|
};
|
|
|
|
devfreq_isp {
|
|
dm-index = <0x0d>;
|
|
available = "true";
|
|
cal_id = <0xb040011>;
|
|
dm_type_name = "dm_isp";
|
|
};
|
|
|
|
devfreq_mfc1 {
|
|
dm-index = <0x0f>;
|
|
available = "true";
|
|
cal_id = <0xb040013>;
|
|
dm_type_name = "dm_mfc1";
|
|
};
|
|
|
|
devfreq_dsp {
|
|
dm-index = <0x10>;
|
|
available = "true";
|
|
cal_id = <0xb040015>;
|
|
dm_type_name = "dm_dsp";
|
|
};
|
|
|
|
devfreq_dnc {
|
|
dm-index = <0x11>;
|
|
available = "true";
|
|
cal_id = <0xb040016>;
|
|
dm_type_name = "dm_dnc";
|
|
};
|
|
|
|
devfreq_gnss {
|
|
dm-index = <0x12>;
|
|
available = "true";
|
|
cal_id = <0xb040017>;
|
|
dm_type_name = "dm_gnss";
|
|
};
|
|
|
|
devfreq_alive {
|
|
dm-index = <0x13>;
|
|
available = "true";
|
|
cal_id = <0xb040018>;
|
|
dm_type_name = "dm_alive";
|
|
};
|
|
|
|
devfreq_chub {
|
|
dm-index = <0x14>;
|
|
available = "true";
|
|
cal_id = <0xb040019>;
|
|
dm_type_name = "dm_chub";
|
|
};
|
|
|
|
devfreq_vts {
|
|
dm-index = <0x15>;
|
|
available = "true";
|
|
cal_id = <0xb04001a>;
|
|
dm_type_name = "dm_vts";
|
|
};
|
|
|
|
devfreq_hsi0 {
|
|
dm-index = <0x16>;
|
|
available = "true";
|
|
cal_id = <0xb04001b>;
|
|
dm_type_name = "dm_hsi0";
|
|
};
|
|
|
|
devfreq_ufd {
|
|
dm-index = <0x17>;
|
|
available = "true";
|
|
cal_id = <0xb04001c>;
|
|
dm_type_name = "dm_ufd";
|
|
};
|
|
};
|
|
|
|
dm-fast-switch {
|
|
acpm-ipc-channel = <0x0c>;
|
|
};
|
|
};
|
|
|
|
exynos_devfreq {
|
|
compatible = "samsung,exynos-devfreq-root";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
|
|
devfreq_mif@17000010 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000010 0x00>;
|
|
devfreq_type = <0x00>;
|
|
devfreq_domain_name = "MIF";
|
|
pm_qos_class = <0x0e>;
|
|
pm_qos_class_max = <0x0f>;
|
|
ess_flag = <0x04>;
|
|
dm-index = <0x03>;
|
|
clocks = <0x19 0x5dc>;
|
|
clock-names = "DEVFREQ";
|
|
use_delay_time = "false";
|
|
freq_info = <0x3066a0 0x66c88 0x66c88 0x66c88 0x3066a0 0xf78f0>;
|
|
boot_info = <0x28 0x3066a0>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040000>;
|
|
acpm-ipc-channel = <0x01>;
|
|
use_acpm = "true";
|
|
update_fvp = "true";
|
|
use_migov = "true";
|
|
sysbusy = "true";
|
|
use_get_dev = "true";
|
|
um_count = <0x06>;
|
|
um_list = <0x1a100000 0x1a110000 0x1a120000 0x1a130000 0x1a140000 0x1a150000>;
|
|
use_alt_dvfs;
|
|
polling_ms = <0x00>;
|
|
phandle = <0x18f>;
|
|
|
|
alt_mode {
|
|
default_mode = <0x00>;
|
|
|
|
mode_0 {
|
|
mode_id = <0x00>;
|
|
target_load = "60 676000:84 845000:90 1014000:95 1352000:97 2028000:99";
|
|
min_sample_time = <0x32>;
|
|
hold_sample_time = <0x64>;
|
|
hispeed_load = <0x62>;
|
|
hispeed_freq = <0xf78f0>;
|
|
};
|
|
|
|
mode_1 {
|
|
mode_id = <0x01>;
|
|
target_load = "3 3172000:3";
|
|
min_sample_time = <0x32>;
|
|
hold_sample_time = <0x64>;
|
|
hispeed_load = <0x03>;
|
|
hispeed_freq = <0x3066a0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
devfreq_int@17000020 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000020 0x00>;
|
|
devfreq_type = <0x01>;
|
|
devfreq_domain_name = "INT";
|
|
pm_qos_class = <0x0a>;
|
|
pm_qos_class_max = <0x0c>;
|
|
ess_flag = <0x03>;
|
|
dm-index = <0x04>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x61a80 0x13880 0x13880 0x13880 0xc3500 0x61a80>;
|
|
boot_info = <0x28 0x61a80>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040001>;
|
|
acpm-ipc-channel = <0x01>;
|
|
use_acpm = "true";
|
|
phandle = <0x18e>;
|
|
};
|
|
|
|
devfreq_intcam@17000030 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000030 0x00>;
|
|
devfreq_type = <0x02>;
|
|
devfreq_domain_name = "INTCAM";
|
|
pm_qos_class = <0x0b>;
|
|
pm_qos_class_max = <0x0d>;
|
|
ess_flag = <0x07>;
|
|
dm-index = <0x0a>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x39210 0xc350 0xc350 0xc350 0xb5e28 0x39210>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb04000e>;
|
|
phandle = <0x2f6>;
|
|
};
|
|
|
|
devfreq_disp@17000040 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000040 0x00>;
|
|
devfreq_type = <0x03>;
|
|
devfreq_domain_name = "DISP";
|
|
pm_qos_class = <0x10>;
|
|
pm_qos_class_max = <0x11>;
|
|
ess_flag = <0x06>;
|
|
dm-index = <0x07>;
|
|
use_delay_time = "false";
|
|
freq_info = <0xc3500 0xc350 0xc350 0xc350 0xc3500 0xa1dd8>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040007>;
|
|
phandle = <0x2f7>;
|
|
};
|
|
|
|
devfreq_cam@17000050 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000050 0x00>;
|
|
devfreq_type = <0x04>;
|
|
devfreq_domain_name = "CAM";
|
|
pm_qos_class = <0x12>;
|
|
pm_qos_class_max = <0x14>;
|
|
ess_flag = <0x05>;
|
|
dm-index = <0x0b>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x39210 0xc350 0xc350 0xc350 0xb5e28 0x28870>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb04000f>;
|
|
phandle = <0x2f8>;
|
|
};
|
|
|
|
devfreq_npu@17000060 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000060 0x00>;
|
|
devfreq_type = <0x05>;
|
|
devfreq_domain_name = "NPU";
|
|
pm_qos_class = <0x17>;
|
|
pm_qos_class_max = <0x19>;
|
|
ess_flag = <0x0a>;
|
|
dm-index = <0x05>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x27100 0x27100 0x27100 0x27100 0x104410 0x27100>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040005>;
|
|
use_dtm = "true";
|
|
#cooling-cells = <0x02>;
|
|
tz-cooling-name = "NPU";
|
|
phandle = <0x129>;
|
|
|
|
skew {
|
|
|
|
skew_0 {
|
|
master_dm_name = "NPU_INT";
|
|
constraint_dm_type = <0x04>;
|
|
constraint_type = <0x00>;
|
|
};
|
|
|
|
skew_1 {
|
|
master_dm_name = "NPU_MIF";
|
|
constraint_dm_type = <0x03>;
|
|
constraint_type = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
devfreq_aud@17000070 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000070 0x00>;
|
|
devfreq_type = <0x06>;
|
|
devfreq_domain_name = "AUD";
|
|
pm_qos_class = <0x13>;
|
|
pm_qos_class_max = <0x15>;
|
|
ess_flag = <0x08>;
|
|
dm-index = <0x08>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x20b70 0x13880 0x13880 0x13880 0x185290 0x13880>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040008>;
|
|
pd_name = "pd_aud";
|
|
phandle = <0x2f9>;
|
|
|
|
skew {
|
|
|
|
skew_0 {
|
|
master_dm_name = "AUD_INT";
|
|
constraint_dm_type = <0x04>;
|
|
constraint_type = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
devfreq_dnc@17000080 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000080 0x00>;
|
|
devfreq_type = <0x07>;
|
|
devfreq_domain_name = "DNC";
|
|
pm_qos_class = <0x24>;
|
|
pm_qos_class_max = <0x25>;
|
|
ess_flag = <0x0c>;
|
|
dm-index = <0x11>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x27100 0x27100 0x27100 0x27100 0xe4458 0x27100>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040016>;
|
|
phandle = <0x18d>;
|
|
};
|
|
|
|
devfreq_mfc0@17000090 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000090 0x00>;
|
|
devfreq_type = <0x08>;
|
|
devfreq_domain_name = "MFC0";
|
|
pm_qos_class = <0x16>;
|
|
pm_qos_class_max = <0x18>;
|
|
ess_flag = <0x09>;
|
|
dm-index = <0x0e>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x20788 0xc350 0xc350 0xc350 0xc3500 0xc350>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040012>;
|
|
phandle = <0x2fa>;
|
|
};
|
|
|
|
devfreq_csis@170000A0 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x170000a0 0x00>;
|
|
devfreq_type = <0x09>;
|
|
devfreq_domain_name = "CSIS";
|
|
pm_qos_class = <0x1e>;
|
|
pm_qos_class_max = <0x1f>;
|
|
ess_flag = <0x0d>;
|
|
dm-index = <0x0c>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x412f8 0xc350 0xc350 0xc350 0xb5e28 0x28870>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040010>;
|
|
phandle = <0x2fb>;
|
|
};
|
|
|
|
devfreq_isp@170000B0 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x170000b0 0x00>;
|
|
devfreq_type = <0x0a>;
|
|
devfreq_domain_name = "ISP";
|
|
pm_qos_class = <0x20>;
|
|
pm_qos_class_max = <0x21>;
|
|
ess_flag = <0x0e>;
|
|
dm-index = <0x0d>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x39210 0xc350 0xc350 0xc350 0xb5e28 0x28870>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040011>;
|
|
phandle = <0x2fc>;
|
|
};
|
|
|
|
devfreq_mfc1@170000C0 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x170000c0 0x00>;
|
|
devfreq_type = <0x0b>;
|
|
devfreq_domain_name = "MFC1";
|
|
pm_qos_class = <0x22>;
|
|
pm_qos_class_max = <0x23>;
|
|
ess_flag = <0x0f>;
|
|
dm-index = <0x0f>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x20788 0xc350 0xc350 0xc350 0xb5e28 0xc350>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040013>;
|
|
phandle = <0x2fd>;
|
|
};
|
|
|
|
devfreq_dsp@170000D0 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x170000d0 0x00>;
|
|
devfreq_type = <0x0c>;
|
|
devfreq_domain_name = "DSP";
|
|
pm_qos_class = <0x26>;
|
|
pm_qos_class_max = <0x27>;
|
|
ess_flag = <0x10>;
|
|
dm-index = <0x10>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x27100 0x27100 0x27100 0x27100 0x104410 0x27100>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040015>;
|
|
phandle = <0x190>;
|
|
|
|
skew {
|
|
|
|
skew_0 {
|
|
master_dm_name = "DSP_INT";
|
|
constraint_dm_type = <0x04>;
|
|
constraint_type = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
devfreq_alive@170000E0 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x170000e0 0x00>;
|
|
devfreq_type = <0x0d>;
|
|
devfreq_domain_name = "ALIVE";
|
|
pm_qos_class = <0x28>;
|
|
pm_qos_class_max = <0x29>;
|
|
ess_flag = <0x11>;
|
|
dm-index = <0x13>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x61a80 0x186a0 0x186a0 0x61a80 0x61a80 0x61a80>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040018>;
|
|
phandle = <0x2fe>;
|
|
};
|
|
|
|
devfreq_vts@170000F0 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x170000f0 0x00>;
|
|
devfreq_type = <0x0f>;
|
|
devfreq_domain_name = "VTS";
|
|
pm_qos_class = <0x2c>;
|
|
pm_qos_class_max = <0x2d>;
|
|
ess_flag = <0x13>;
|
|
dm-index = <0x15>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x61a80 0x30d40 0x30d40 0x30d40 0x61a80 0x61a80>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb04001a>;
|
|
phandle = <0x2ff>;
|
|
};
|
|
|
|
devfreq_hsi0@17000100 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000100 0x00>;
|
|
devfreq_type = <0x10>;
|
|
devfreq_domain_name = "HSI0";
|
|
pm_qos_class = <0x2e>;
|
|
pm_qos_class_max = <0x2f>;
|
|
ess_flag = <0x14>;
|
|
dm-index = <0x16>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x30d40 0x13880 0x30d40 0x13880 0x30d40 0x30d40>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb04001b>;
|
|
phandle = <0x300>;
|
|
};
|
|
|
|
devfreq_ufd@17000110 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000110 0x00>;
|
|
devfreq_type = <0x11>;
|
|
devfreq_domain_name = "UFD";
|
|
pm_qos_class = <0x30>;
|
|
pm_qos_class_max = <0x31>;
|
|
ess_flag = <0x15>;
|
|
dm-index = <0x17>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x61a80 0x30d40 0x30d40 0x30d40 0x61a80 0x61a80>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb04001c>;
|
|
phandle = <0x301>;
|
|
};
|
|
};
|
|
|
|
BIG@10070000 {
|
|
compatible = "samsung,exynos-tmu-v2";
|
|
reg = <0x00 0x10070000 0x800>;
|
|
interrupts = <0x00 0x3bb 0x04>;
|
|
tmu_name = "BIG";
|
|
id = <0x00>;
|
|
hotplug_enable = <0x01>;
|
|
hotplug_in_threshold = <0x5b>;
|
|
hotplug_out_threshold = <0x60>;
|
|
cpu_domain = "7";
|
|
#thermal-sensor-cells = <0x00>;
|
|
cal_id = <0xb040004>;
|
|
use-pi-thermal;
|
|
use-sync-pi-thermal;
|
|
polling_delay_on = <0x14>;
|
|
polling_delay_off = <0x3e8>;
|
|
k_po = <0x00>;
|
|
k_pu = <0x00>;
|
|
k_i = <0x00>;
|
|
i_max = <0x00>;
|
|
integral_cutoff = <0x00>;
|
|
sustainable_power = <0x00>;
|
|
use-boost;
|
|
emergency_frequency;
|
|
thermal_status_level = <0x157c0 0x16378 0x16f30>;
|
|
phandle = <0x112>;
|
|
};
|
|
|
|
MID@10070000 {
|
|
compatible = "samsung,exynos-tmu-v2";
|
|
reg = <0x00 0x10070000 0x800>;
|
|
interrupts = <0x00 0x3bb 0x04>;
|
|
tmu_name = "MID";
|
|
hotplug_enable = <0x01>;
|
|
hotplug_in_threshold = <0x5b>;
|
|
hotplug_out_threshold = <0x60>;
|
|
cpu_domain = "4-6";
|
|
id = <0x01>;
|
|
#thermal-sensor-cells = <0x00>;
|
|
cal_id = <0xb040003>;
|
|
use-pi-thermal;
|
|
use-sync-pi-thermal;
|
|
polling_delay_on = <0x14>;
|
|
polling_delay_off = <0x3e8>;
|
|
k_po = <0x00>;
|
|
k_pu = <0x00>;
|
|
k_i = <0x00>;
|
|
i_max = <0x00>;
|
|
integral_cutoff = <0x00>;
|
|
sustainable_power = <0x00>;
|
|
use-boost;
|
|
emergency_frequency;
|
|
phandle = <0x116>;
|
|
};
|
|
|
|
LITTLE@10070000 {
|
|
compatible = "samsung,exynos-tmu-v2";
|
|
reg = <0x00 0x10070000 0x800>;
|
|
interrupts = <0x00 0x3bb 0x04>;
|
|
tmu_name = "LITTLE";
|
|
id = <0x02>;
|
|
#thermal-sensor-cells = <0x00>;
|
|
use-pi-thermal;
|
|
polling_delay_on = <0x14>;
|
|
polling_delay_off = <0x3e8>;
|
|
k_po = <0x00>;
|
|
k_pu = <0x00>;
|
|
k_i = <0x00>;
|
|
i_max = <0x00>;
|
|
integral_cutoff = <0x00>;
|
|
sustainable_power = <0x00>;
|
|
use-boost;
|
|
phandle = <0x118>;
|
|
};
|
|
|
|
G3D@10080000 {
|
|
compatible = "samsung,exynos-tmu-v2";
|
|
reg = <0x00 0x10080000 0x800>;
|
|
interrupts = <0x00 0x3bc 0x04>;
|
|
tmu_name = "G3D";
|
|
id = <0x03>;
|
|
#thermal-sensor-cells = <0x00>;
|
|
use-pi-thermal;
|
|
polling_delay_on = <0x14>;
|
|
polling_delay_off = <0x3e8>;
|
|
k_po = <0x00>;
|
|
k_pu = <0x00>;
|
|
k_i = <0x00>;
|
|
i_max = <0x00>;
|
|
integral_cutoff = <0x00>;
|
|
sustainable_power = <0x00>;
|
|
use-boost;
|
|
phandle = <0x9a>;
|
|
};
|
|
|
|
ISP@10080000 {
|
|
compatible = "samsung,exynos-tmu-v2";
|
|
reg = <0x00 0x10080000 0x800>;
|
|
interrupts = <0x00 0x3bc 0x04>;
|
|
tmu_name = "ISP";
|
|
id = <0x04>;
|
|
#thermal-sensor-cells = <0x00>;
|
|
phandle = <0x11d>;
|
|
};
|
|
|
|
NPU@10080000 {
|
|
compatible = "samsung,exynos-tmu-v2";
|
|
reg = <0x00 0x10080000 0x800>;
|
|
interrupts = <0x00 0x3bc 0x04>;
|
|
tmu_name = "NPU";
|
|
id = <0x05>;
|
|
#thermal-sensor-cells = <0x00>;
|
|
phandle = <0x127>;
|
|
};
|
|
|
|
CP@10080000 {
|
|
compatible = "samsung,exynos-tmu-v2";
|
|
reg = <0x00 0x10080000 0x800>;
|
|
interrupts = <0x00 0x3bc 0x04>;
|
|
tmu_name = "CP";
|
|
id = <0x06>;
|
|
#thermal-sensor-cells = <0x00>;
|
|
phandle = <0x131>;
|
|
};
|
|
|
|
acpm_tmu {
|
|
acpm-ipc-channel = <0x07>;
|
|
};
|
|
|
|
exynos_isp_thermal {
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x11f>;
|
|
};
|
|
|
|
thermal-zones {
|
|
|
|
BIG {
|
|
zone_name = "BIG_THERMAL";
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x112>;
|
|
phandle = <0x132>;
|
|
|
|
trips {
|
|
|
|
big-cold {
|
|
temperature = <0x4e20>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x302>;
|
|
};
|
|
|
|
big-switch-on {
|
|
temperature = <0xea60>;
|
|
hysteresis = <0x7d0>;
|
|
type = "active";
|
|
phandle = <0x303>;
|
|
};
|
|
|
|
big-control-temp {
|
|
temperature = <0x11170>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x113>;
|
|
};
|
|
|
|
big-alert0 {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x304>;
|
|
};
|
|
|
|
big-alert1 {
|
|
temperature = <0x186a0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x305>;
|
|
};
|
|
|
|
big-alert2 {
|
|
temperature = <0x19a28>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x306>;
|
|
};
|
|
|
|
big-alert3 {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x307>;
|
|
};
|
|
|
|
big-hot {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "hot";
|
|
phandle = <0x308>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x113>;
|
|
cooling-device = <0x114 0x00 0x00>;
|
|
};
|
|
|
|
map1 {
|
|
trip = <0x113>;
|
|
cooling-device = <0x115 0x00 0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
MID {
|
|
zone_name = "MID_THERMAL";
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x116>;
|
|
phandle = <0x133>;
|
|
|
|
trips {
|
|
|
|
mid-cold {
|
|
temperature = <0x4e20>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x309>;
|
|
};
|
|
|
|
mid-switch-on {
|
|
temperature = <0xea60>;
|
|
hysteresis = <0x7d0>;
|
|
type = "active";
|
|
phandle = <0x30a>;
|
|
};
|
|
|
|
mid-control-temp {
|
|
temperature = <0x11170>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x117>;
|
|
};
|
|
|
|
mid-alert0 {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x30b>;
|
|
};
|
|
|
|
mid-alert1 {
|
|
temperature = <0x186a0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x30c>;
|
|
};
|
|
|
|
mid-alert2 {
|
|
temperature = <0x19a28>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x30d>;
|
|
};
|
|
|
|
mid-alert3 {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x30e>;
|
|
};
|
|
|
|
mid-hot {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "hot";
|
|
phandle = <0x30f>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x117>;
|
|
cooling-device = <0x115 0x00 0x00>;
|
|
};
|
|
|
|
map1 {
|
|
trip = <0x117>;
|
|
cooling-device = <0x114 0x00 0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
LITTLE {
|
|
zone_name = "LITTLE_THERMAL";
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x118>;
|
|
phandle = <0x134>;
|
|
|
|
trips {
|
|
|
|
little-cold {
|
|
temperature = <0x4e20>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x310>;
|
|
};
|
|
|
|
little-switch-on {
|
|
temperature = <0x128e0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x311>;
|
|
};
|
|
|
|
little-control-temp {
|
|
temperature = <0x13c68>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x119>;
|
|
};
|
|
|
|
little-alert0 {
|
|
temperature = <0x14ff0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x312>;
|
|
};
|
|
|
|
little-alert1 {
|
|
temperature = <0x16378>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x313>;
|
|
};
|
|
|
|
little-alert2 {
|
|
temperature = <0x17700>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x314>;
|
|
};
|
|
|
|
little-alert3 {
|
|
temperature = <0x18a88>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x315>;
|
|
};
|
|
|
|
little-hot {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "hot";
|
|
phandle = <0x316>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x119>;
|
|
cooling-device = <0x11a 0x00 0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
G3D {
|
|
zone_name = "G3D_THERMAL";
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x9a>;
|
|
phandle = <0x317>;
|
|
|
|
trips {
|
|
|
|
gpu-cold {
|
|
temperature = <0x4e20>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x318>;
|
|
};
|
|
|
|
gpu-switch-on {
|
|
temperature = <0xfde8>;
|
|
hysteresis = <0x7d0>;
|
|
type = "active";
|
|
phandle = <0x319>;
|
|
};
|
|
|
|
gpu-control-temp {
|
|
temperature = <0x11170>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x11b>;
|
|
};
|
|
|
|
gpu-alert0 {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x31a>;
|
|
};
|
|
|
|
gpu-alert1 {
|
|
temperature = <0x186a0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x31b>;
|
|
};
|
|
|
|
gpu-alert2 {
|
|
temperature = <0x19a28>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x31c>;
|
|
};
|
|
|
|
gpu-alert3 {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x31d>;
|
|
};
|
|
|
|
gpu-hot {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "hot";
|
|
phandle = <0x31e>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x11b>;
|
|
cooling-device = <0x11c 0x00 0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
ISP {
|
|
zone_name = "ISP_THERMAL";
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x11d>;
|
|
phandle = <0x135>;
|
|
|
|
trips {
|
|
|
|
isp-alert0 {
|
|
temperature = <0x4e20>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x11e>;
|
|
};
|
|
|
|
isp-alert1 {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x120>;
|
|
};
|
|
|
|
isp-alert2 {
|
|
temperature = <0x186a0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x121>;
|
|
};
|
|
|
|
isp-alert3 {
|
|
temperature = <0x19a28>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x122>;
|
|
};
|
|
|
|
isp-alert4 {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x123>;
|
|
};
|
|
|
|
isp-alert5 {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x124>;
|
|
};
|
|
|
|
isp-alert6 {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x125>;
|
|
};
|
|
|
|
isp-hot {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "hot";
|
|
phandle = <0x126>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x11e>;
|
|
cooling-device = <0x11f 0x00 0x00>;
|
|
};
|
|
|
|
map1 {
|
|
trip = <0x120>;
|
|
cooling-device = <0x11f 0x00 0x00>;
|
|
};
|
|
|
|
map2 {
|
|
trip = <0x121>;
|
|
cooling-device = <0x11f 0x00 0x00>;
|
|
};
|
|
|
|
map3 {
|
|
trip = <0x122>;
|
|
cooling-device = <0x11f 0x00 0x00>;
|
|
};
|
|
|
|
map4 {
|
|
trip = <0x123>;
|
|
cooling-device = <0x11f 0x00 0x00>;
|
|
};
|
|
|
|
map5 {
|
|
trip = <0x124>;
|
|
cooling-device = <0x11f 0x00 0x00>;
|
|
};
|
|
|
|
map6 {
|
|
trip = <0x125>;
|
|
cooling-device = <0x11f 0x00 0x00>;
|
|
};
|
|
|
|
map7 {
|
|
trip = <0x126>;
|
|
cooling-device = <0x11f 0x00 0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
NPU {
|
|
zone_name = "NPU_THERMAL";
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x127>;
|
|
phandle = <0x31f>;
|
|
|
|
trips {
|
|
|
|
npu-alert0 {
|
|
temperature = <0x4e20>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x128>;
|
|
};
|
|
|
|
npu-alert1 {
|
|
temperature = <0x128e0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x12a>;
|
|
};
|
|
|
|
npu-alert2 {
|
|
temperature = <0x13c68>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x12b>;
|
|
};
|
|
|
|
npu-alert3 {
|
|
temperature = <0x14ff0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x12c>;
|
|
};
|
|
|
|
npu-alert4 {
|
|
temperature = <0x16378>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x12d>;
|
|
};
|
|
|
|
npu-alert5 {
|
|
temperature = <0x17700>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x12e>;
|
|
};
|
|
|
|
npu-alert6 {
|
|
temperature = <0x18a88>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x12f>;
|
|
};
|
|
|
|
npu-hot {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "hot";
|
|
phandle = <0x130>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x128>;
|
|
cooling-device = <0x129 0x00 0x00>;
|
|
};
|
|
|
|
map1 {
|
|
trip = <0x12a>;
|
|
cooling-device = <0x129 0x00 0x00>;
|
|
};
|
|
|
|
map2 {
|
|
trip = <0x12b>;
|
|
cooling-device = <0x129 0x00 0x00>;
|
|
};
|
|
|
|
map3 {
|
|
trip = <0x12c>;
|
|
cooling-device = <0x129 0x00 0x00>;
|
|
};
|
|
|
|
map4 {
|
|
trip = <0x12d>;
|
|
cooling-device = <0x129 0x00 0x00>;
|
|
};
|
|
|
|
map5 {
|
|
trip = <0x12e>;
|
|
cooling-device = <0x129 0x00 0x00>;
|
|
};
|
|
|
|
map6 {
|
|
trip = <0x12f>;
|
|
cooling-device = <0x129 0x00 0x00>;
|
|
};
|
|
|
|
map7 {
|
|
trip = <0x130>;
|
|
cooling-device = <0x129 0x00 0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
CP {
|
|
zone_name = "CP_THERMAL";
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x3e8>;
|
|
thermal-sensors = <0x131>;
|
|
phandle = <0x320>;
|
|
};
|
|
};
|
|
|
|
mcinfo@1c030000 {
|
|
compatible = "samsung,exynos-mcinfo";
|
|
reg = <0x00 0x1c03f04c 0x04 0x00 0x1c13f04c 0x04 0x00 0x1c23f04c 0x04 0x00 0x1c33f04c 0x04>;
|
|
bit_field = <0x18 0x05>;
|
|
basecnt = <0x04>;
|
|
irqcnt = <0x04>;
|
|
reset_cond = <0x0f>;
|
|
interrupts = <0x00 0x25b 0x04 0x00 0x262 0x04 0x00 0x269 0x04 0x00 0x270 0x04>;
|
|
phandle = <0x321>;
|
|
};
|
|
|
|
amb_control {
|
|
compatible = "samsung,exynos-amb-control";
|
|
amb_tz_name = "battery";
|
|
default_sampling_rate = <0x3e8>;
|
|
high_sampling_rate = <0x64>;
|
|
increase_sampling_temp = <0xd6d8>;
|
|
decrease_sampling_temp = <0xc350>;
|
|
mcinfo_threshold = <0xea60>;
|
|
use_mif_throttle;
|
|
mif_down_threshold = <0xea60>;
|
|
mif_up_threshold = <0xd6d8>;
|
|
mif_throttle_freq = <0x1a2f20>;
|
|
use_llc_throttle;
|
|
llc_off_thresohld = <0x14438>;
|
|
llc_on_threshold = <0x13880>;
|
|
|
|
tz_big {
|
|
tz = <0x132>;
|
|
hotplug_cpu_list = "7";
|
|
hotplug_in_threshold = <0xea60>;
|
|
hotplug_out_threshold = <0xfde8>;
|
|
|
|
trip_set {
|
|
|
|
trip_0 {
|
|
trigger_cond = <0x01>;
|
|
trip_point = <0x02>;
|
|
trigger_temp = <0xea60>;
|
|
release_temp = <0xd6d8>;
|
|
throttle_temp = <0x124f8>;
|
|
};
|
|
|
|
trip_1 {
|
|
trigger_cond = <0x01>;
|
|
trip_point = <0x01>;
|
|
trigger_temp = <0xea60>;
|
|
release_temp = <0xd6d8>;
|
|
throttle_temp = <0x11170>;
|
|
};
|
|
|
|
trip_2 {
|
|
trigger_cond = <0x00>;
|
|
trip_point = <0x02>;
|
|
trigger_temp = <0x2710>;
|
|
release_temp = <0x61a8>;
|
|
throttle_temp = <0x14c08>;
|
|
};
|
|
|
|
trip_3 {
|
|
trigger_cond = <0x00>;
|
|
trip_point = <0x01>;
|
|
trigger_temp = <0x2710>;
|
|
release_temp = <0x61a8>;
|
|
throttle_temp = <0x13880>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tz_mid {
|
|
tz = <0x133>;
|
|
hotplug_cpu_list = "5-6";
|
|
hotplug_in_threshold = <0xea60>;
|
|
hotplug_out_threshold = <0xfde8>;
|
|
|
|
trip_set {
|
|
|
|
trip_0 {
|
|
trigger_cond = <0x01>;
|
|
trip_point = <0x02>;
|
|
trigger_temp = <0xea60>;
|
|
release_temp = <0xd6d8>;
|
|
throttle_temp = <0x124f8>;
|
|
};
|
|
|
|
trip_1 {
|
|
trigger_cond = <0x01>;
|
|
trip_point = <0x01>;
|
|
trigger_temp = <0xea60>;
|
|
release_temp = <0xd6d8>;
|
|
throttle_temp = <0x11170>;
|
|
};
|
|
|
|
trip_2 {
|
|
trigger_cond = <0x00>;
|
|
trip_point = <0x02>;
|
|
trigger_temp = <0x2710>;
|
|
release_temp = <0x61a8>;
|
|
throttle_temp = <0x14c08>;
|
|
};
|
|
|
|
trip_3 {
|
|
trigger_cond = <0x00>;
|
|
trip_point = <0x01>;
|
|
trigger_temp = <0x2710>;
|
|
release_temp = <0x61a8>;
|
|
throttle_temp = <0x13880>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tz_lit {
|
|
tz = <0x134>;
|
|
hotplug_cpu_list = "2-3";
|
|
hotplug_in_threshold = <0x11170>;
|
|
hotplug_out_threshold = <0x124f8>;
|
|
|
|
trip_set {
|
|
|
|
trip_0 {
|
|
trigger_cond = <0x00>;
|
|
trip_point = <0x02>;
|
|
trigger_temp = <0x2710>;
|
|
release_temp = <0x61a8>;
|
|
throttle_temp = <0x14c08>;
|
|
};
|
|
|
|
trip_1 {
|
|
trigger_cond = <0x00>;
|
|
trip_point = <0x01>;
|
|
trigger_temp = <0x2710>;
|
|
release_temp = <0x61a8>;
|
|
throttle_temp = <0x13880>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tz_isp {
|
|
tz = <0x135>;
|
|
|
|
trip_set {
|
|
|
|
trip_0 {
|
|
trigger_cond = <0x00>;
|
|
trip_point = <0x01>;
|
|
trigger_temp = <0xea60>;
|
|
release_temp = <0xd6d8>;
|
|
throttle_temp = <0x17318>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
exynos-ect {
|
|
compatible = "samsung,exynos-ect";
|
|
memory-region = <0x136>;
|
|
};
|
|
|
|
acpm_dvfs {
|
|
compatible = "samsung,exynos-acpm-dvfs";
|
|
acpm-ipc-channel = <0x05>;
|
|
};
|
|
|
|
exynos-wow {
|
|
compatible = "samsung,exynos-wow";
|
|
reg = <0x00 0x1a100000 0x1000 0x00 0x1a120000 0x1000 0x00 0x1a130000 0x1000 0x00 0x1a170000 0x1000>;
|
|
polling_delay = <0xea60>;
|
|
|
|
wow-ip {
|
|
|
|
CPUCL0 {
|
|
bus_width = <0x20>;
|
|
nr_ppc = <0x02>;
|
|
nr_base = <0x01>;
|
|
reg_index = <0x00>;
|
|
use_latency;
|
|
};
|
|
|
|
G3D {
|
|
bus_width = <0x10>;
|
|
nr_ppc = <0x04>;
|
|
nr_base = <0x01>;
|
|
reg_index = <0x01>;
|
|
};
|
|
|
|
IRPS {
|
|
bus_width = <0x20>;
|
|
nr_ppc = <0x04>;
|
|
nr_base = <0x01>;
|
|
reg_index = <0x02>;
|
|
};
|
|
|
|
MIF {
|
|
bus_width = <0x10>;
|
|
nr_ppc = <0x04>;
|
|
nr_base = <0x01>;
|
|
reg_index = <0x03>;
|
|
monitor_only;
|
|
};
|
|
};
|
|
};
|
|
|
|
s2mpu {
|
|
compatible = "samsung,exynos-s2mpu";
|
|
memory_region = <0x137>;
|
|
subsystem-num = <0x11>;
|
|
subsystem-names = "MFC0\0MFC1\0ABOX\0VTS\0DNC\0CHUB\0GNSS\0G3D_TMR\0PCIE_GEN2_WIFI\0PCIE_GEN3\0MODEM_PP\0DIT\0APM\0G3D_NORMAL\0DPU\0CAMERA\0DEFAULT";
|
|
instance-num = <0x32>;
|
|
instance-names = "DPUF0_D0\0DPUF0_D1\0DPUF1_D0\0DPUF1_D1\0CSIS_D0\0CSIS_D1\0CSIS_D2\0BRP_D0\0BRP_D1\0BRP_D2\0CSTAT\0SDMA0\0SDMA1\0SDMA2\0SDMA3\0IPDNC\0LME\0M2M\0MCSC_D0\0MCSC_D1\0MCSC_D2\0MCSC_D3\0MCSC_D4\0MFC0_D0\0MFC0_D1\0MFC1_D0\0MFC1_D1\0YUVP_D0\0YUVP_D1\0AUD\0HSI0\0HSI1\0UFD\0UFS\0MODEM\0APM\0DIT\0TT\0G3D\0EMPTY\0EMPTY\0EMPTY\0EMPTY\0EMPTY\0EMPTY\0EMPTY\0EMPTY\0EMPTY\0EMPTY\0EMPTY";
|
|
irqcnt = <0x32>;
|
|
interrupts = <0x00 0x1ba 0x04 0x00 0x1c2 0x04 0x00 0x1be 0x04 0x00 0x1c6 0x04 0x00 0x123 0x04 0x00 0x127 0x04 0x00 0x12b 0x04 0x00 0x59 0x04 0x00 0x5d 0x04 0x00 0x61 0x04 0x00 0x141 0x04 0x00 0x161 0x04 0x00 0x165 0x04 0x00 0x169 0x04 0x00 0x16d 0x04 0x00 0x15d 0x04 0x00 0x20a 0x04 0x00 0x213 0x04 0x00 0x238 0x04 0x00 0x23c 0x04 0x00 0x240 0x04 0x00 0x1d0 0x04 0x00 0x1ed 0x04 0x00 0x246 0x04 0x00 0x24a 0x04 0x00 0x251 0x04 0x00 0x255 0x04 0x00 0x22c 0x04 0x00 0x230 0x04 0x00 0x4f 0x04 0x00 0x1e9 0x04 0x00 0x201 0x04 0x00 0x221 0x04 0x00 0x227 0x04 0x00 0x283 0x04 0x00 0x27d 0x04 0x00 0x299 0x04 0x00 0x29d 0x04 0x00 0x27f 0x04 0x00 0xe3 0x04 0x00 0xe3 0x04 0x00 0xe3 0x04 0x00 0xe3 0x04 0x00 0xe3 0x04 0x00 0xe3 0x04 0x00 0xe3 0x04 0x00 0xe3 0x04 0x00 0xe3 0x04 0x00 0xe3 0x04 0x00 0xe3 0x04>;
|
|
};
|
|
|
|
exynos-el2 {
|
|
compatible = "samsung,exynos-el2";
|
|
interrupts = <0x00 0xe2 0x04>;
|
|
};
|
|
|
|
tee {
|
|
compatible = "samsung,exynos-tee";
|
|
interrupts = <0x00 0xdf 0x01>;
|
|
};
|
|
|
|
tee-tui {
|
|
compatible = "samsung,exynos-tui";
|
|
samsung,tzmp;
|
|
};
|
|
|
|
seclog {
|
|
compatible = "samsung,exynos-seclog";
|
|
interrupts = <0x00 0xe0 0x04>;
|
|
memory-region = <0x138>;
|
|
};
|
|
|
|
tzasc {
|
|
compatible = "samsung,exynos-tzasc";
|
|
channel = <0x04>;
|
|
tzc_ver = <0x190>;
|
|
irqcnt = <0x04>;
|
|
interrupts = <0x00 0x25c 0x04 0x00 0x263 0x04 0x00 0x26a 0x04 0x00 0x271 0x04>;
|
|
};
|
|
|
|
ppmpu {
|
|
compatible = "samsung,exynos-ppmpu";
|
|
channel = <0x04>;
|
|
tzc_ver = <0x190>;
|
|
irqcnt = <0x04>;
|
|
interrupts = <0x00 0x259 0x04 0x00 0x260 0x04 0x00 0x267 0x04 0x00 0x26e 0x04>;
|
|
};
|
|
|
|
hdcp {
|
|
compatible = "samsung,exynos-hdcp";
|
|
interrupts = <0x00 0xde 0x04>;
|
|
};
|
|
|
|
secmem {
|
|
compatible = "samsung,exynos-secmem";
|
|
power-domains = <0xdb>;
|
|
memory-region = <0x0e 0x0f>;
|
|
};
|
|
|
|
ufs-srpmb {
|
|
compatible = "samsung,ufs-srpmb";
|
|
interrupts = <0x00 0xe1 0x04>;
|
|
};
|
|
|
|
fmp {
|
|
compatible = "samsung,exynos-fmp";
|
|
dun-swap = [00];
|
|
};
|
|
|
|
fmp-simulator {
|
|
compatible = "samsung,exynos-fmp-simulator";
|
|
};
|
|
|
|
ssp {
|
|
compatible = "samsung,exynos-ssp";
|
|
power-domains = <0x139>;
|
|
phandle = <0x322>;
|
|
};
|
|
|
|
cryptomanager {
|
|
compatible = "samsung,exynos-cm";
|
|
sysreg_addr = <0x18221018>;
|
|
ap_addr = <0x18340000>;
|
|
cp_addr = <0x18330000>;
|
|
};
|
|
|
|
exynos-bts {
|
|
compatible = "samsung,exynos-bts";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
list-scen = "default\0cp_throughput\0mfc_uhd\0mfc_uhd_10bit\0mfc_8k_dec30\0gdc_8k_8b_30\0gdc_8k_8b_60\0g3d_heavy\0g3d_performance\0dp_default\0camera_default\0npu_normal\0mfc_uhd_enc60\0camera_heavy\0npu_performance";
|
|
bw_params = <0x04 0x10 0x20 0x41 0x46>;
|
|
|
|
nocl0_irps0 {
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
reg = <0x00 0x1a904000 0x400>;
|
|
status = "okay";
|
|
bts-type = <0x02>;
|
|
};
|
|
|
|
nocl0_irps1 {
|
|
reg = <0x00 0x1a914000 0x400>;
|
|
status = "okay";
|
|
bts-type = <0x02>;
|
|
};
|
|
|
|
nocl0_irps2 {
|
|
reg = <0x00 0x1a924000 0x400>;
|
|
status = "okay";
|
|
bts-type = <0x02>;
|
|
};
|
|
|
|
nocl0_irps3 {
|
|
reg = <0x00 0x1a934000 0x400>;
|
|
status = "okay";
|
|
bts-type = <0x02>;
|
|
};
|
|
|
|
snode_dp {
|
|
reg = <0x00 0x1a942000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x05>;
|
|
};
|
|
|
|
snode_irps0 {
|
|
reg = <0x00 0x1a902000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x05>;
|
|
};
|
|
|
|
snode_irps1 {
|
|
reg = <0x00 0x1a912000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x05>;
|
|
};
|
|
|
|
snode_irps2 {
|
|
reg = <0x00 0x1a922000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x05>;
|
|
};
|
|
|
|
snode_irps3 {
|
|
reg = <0x00 0x1a932000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x05>;
|
|
};
|
|
|
|
sci_node {
|
|
reg = <0x00 0x1a000100 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x03>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
rmo = <0x00>;
|
|
wmo = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
};
|
|
};
|
|
|
|
bts_dpuf0 {
|
|
reg = <0x00 0x1b2a0000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_dpuf1 {
|
|
reg = <0x00 0x1b2b0000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_d0modem {
|
|
reg = <0x00 0x1a890000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x0d>;
|
|
awqos = <0x0d>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
qurgent_th_w = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_aud {
|
|
reg = <0x00 0x1a8c0000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x09>;
|
|
awqos = <0x09>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
qurgent_th_w = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_csis0 {
|
|
reg = <0x00 0x1b400000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
cal-pdid = <0xb1380002>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x0c>;
|
|
awqos = <0x0c>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
qurgent_th_w = <0x0d>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_csis1 {
|
|
reg = <0x00 0x1b410000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
cal-pdid = <0xb1380002>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x0c>;
|
|
awqos = <0x0c>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
qurgent_th_w = <0x0d>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_csis2 {
|
|
reg = <0x00 0x1b420000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
cal-pdid = <0xb1380002>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x0c>;
|
|
awqos = <0x0c>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
qurgent_th_w = <0x0d>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_cstat {
|
|
reg = <0x00 0x1b430000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
cal-pdid = <0xb1380002>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x0c>;
|
|
awqos = <0x0c>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
qurgent_th_w = <0x0d>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_lme {
|
|
reg = <0x00 0x1b250000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
gdc_8k_8b_30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x3c>;
|
|
wmo = <0x14>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
gdc_8k_8b_60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x84>;
|
|
wmo = <0x28>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x28>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x28>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x28>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mcsc0 {
|
|
reg = <0x00 0x1b470000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
cal-pdid = <0xb1380002>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mcsc1 {
|
|
reg = <0x00 0x1b480000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
cal-pdid = <0xb1380002>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mcsc2 {
|
|
reg = <0x00 0x1b490000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
cal-pdid = <0xb1380002>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mcsc3 {
|
|
reg = <0x00 0x1b4a0000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
cal-pdid = <0xb1380002>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mcsc4 {
|
|
reg = <0x00 0x1b4b0000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
cal-pdid = <0xb1380002>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_brp0 {
|
|
reg = <0x00 0x1b440000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
cal-pdid = <0xb1380002>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_brp1 {
|
|
reg = <0x00 0x1b450000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
cal-pdid = <0xb1380002>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_brp2 {
|
|
reg = <0x00 0x1b460000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
cal-pdid = <0xb1380002>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_yuvp0 {
|
|
reg = <0x00 0x1b4c0000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
cal-pdid = <0xb1380002>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_yuvp1 {
|
|
reg = <0x00 0x1b4d0000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
cal-pdid = <0xb1380002>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mfc00 {
|
|
reg = <0x00 0x1b260000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x40>;
|
|
wmo = <0x40>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mfc10 {
|
|
reg = <0x00 0x1b280000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x40>;
|
|
wmo = <0x40>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mfc01 {
|
|
reg = <0x00 0x1b270000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x40>;
|
|
wmo = <0x40>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mfc11 {
|
|
reg = <0x00 0x1b290000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x40>;
|
|
wmo = <0x40>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_hsi0 {
|
|
reg = <0x00 0x1b000000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
};
|
|
|
|
bts_dit {
|
|
reg = <0x00 0x1b030000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
};
|
|
|
|
bts_ufs {
|
|
reg = <0x00 0x1b010000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
};
|
|
|
|
bts_hsi1 {
|
|
reg = <0x00 0x1b240000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
};
|
|
|
|
bts_m2m {
|
|
reg = <0x00 0x1b2c0000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x18>;
|
|
wmo = <0x18>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x08>;
|
|
qmax0_limit_w = <0x08>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mmug3d {
|
|
reg = <0x00 0x1a870000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_g3d0 {
|
|
reg = <0x00 0x1a000010 0x20 0x00 0x1a021220 0x10>;
|
|
status = "okay";
|
|
bts-type = <0x09>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x40>;
|
|
wmo = <0x40>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x40>;
|
|
wmo = <0x40>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
};
|
|
};
|
|
|
|
bts_g3d1 {
|
|
reg = <0x00 0x1a000038 0x20 0x00 0x1a021230 0x10>;
|
|
status = "okay";
|
|
bts-type = <0x09>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x40>;
|
|
wmo = <0x40>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x40>;
|
|
wmo = <0x40>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
};
|
|
};
|
|
|
|
bts_g3d2 {
|
|
reg = <0x00 0x1a000060 0x20 0x00 0x1a021240 0x10>;
|
|
status = "okay";
|
|
bts-type = <0x09>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x40>;
|
|
wmo = <0x40>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x40>;
|
|
wmo = <0x40>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
};
|
|
};
|
|
|
|
bts_g3d3 {
|
|
reg = <0x00 0x1a000088 0x20 0x00 0x1a021250 0x10>;
|
|
status = "okay";
|
|
bts-type = <0x09>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x40>;
|
|
wmo = <0x40>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x40>;
|
|
wmo = <0x40>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
};
|
|
};
|
|
|
|
bts_ssp {
|
|
reg = <0x00 0x1a8e0000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_ufd {
|
|
reg = <0x00 0x1a8f0000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_cssys {
|
|
reg = <0x00 0x1a880000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_d1modem {
|
|
reg = <0x00 0x1a8a0000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x01>;
|
|
rmo = <0x14>;
|
|
wmo = <0x14>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_d2modem {
|
|
reg = <0x00 0x1a8b0000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x14>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_dnc0 {
|
|
reg = <0x00 0x1be00000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
cal-pdid = <0xb1380015>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x30>;
|
|
wmo = <0x30>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x30>;
|
|
wmo = <0x30>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x30>;
|
|
wmo = <0x30>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0xffff>;
|
|
wmo = <0xffff>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_dnc1 {
|
|
reg = <0x00 0x1be10000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
cal-pdid = <0xb1380015>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x30>;
|
|
wmo = <0x30>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x30>;
|
|
wmo = <0x30>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x30>;
|
|
wmo = <0x30>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0xffff>;
|
|
wmo = <0xffff>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_dnc2 {
|
|
reg = <0x00 0x1be20000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
cal-pdid = <0xb1380015>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x30>;
|
|
wmo = <0x30>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x30>;
|
|
wmo = <0x30>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x30>;
|
|
wmo = <0x30>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0xffff>;
|
|
wmo = <0xffff>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_dnc3 {
|
|
reg = <0x00 0x1be30000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
cal-pdid = <0xb1380015>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x30>;
|
|
wmo = <0x30>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x30>;
|
|
wmo = <0x30>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x30>;
|
|
wmo = <0x30>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0xffff>;
|
|
wmo = <0xffff>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_dnc4 {
|
|
reg = <0x00 0x1be40000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
cal-pdid = <0xb1380015>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x30>;
|
|
wmo = <0x30>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x30>;
|
|
wmo = <0x30>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x30>;
|
|
wmo = <0x30>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0xffff>;
|
|
wmo = <0xffff>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pd_aud@15861880 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15861880 0x20>;
|
|
cal_id = <0xb1380000>;
|
|
need_smc = <0x18d10204>;
|
|
cmu_id = <0x18c00000>;
|
|
status = "okay";
|
|
power-down-ok = <0x01>;
|
|
#power-domain-cells = <0x00>;
|
|
skip-idle-ip;
|
|
phandle = <0x02>;
|
|
};
|
|
|
|
pd_nocl1c@15861a80 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15861a80 0x20>;
|
|
cal_id = <0xb1380002>;
|
|
need_smc = <0x1a610204>;
|
|
cmu_id = <0x1a600000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x13a>;
|
|
};
|
|
|
|
pd_brp@15861900 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15861900 0x20>;
|
|
cal_id = <0xb1380001>;
|
|
need_smc = <0x17410204>;
|
|
cmu_id = <0x17400000>;
|
|
status = "okay";
|
|
parent = <0x13a>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x03>;
|
|
};
|
|
|
|
pd_csis@15861f00 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15861f00 0x20>;
|
|
cal_id = <0xb1380004>;
|
|
cmu_id = <0x17000000>;
|
|
status = "okay";
|
|
parent = <0x13a>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x13b>;
|
|
};
|
|
|
|
pd_cstat@15861f80 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15861f80 0x20>;
|
|
cal_id = <0xb1380005>;
|
|
need_smc = <0x18410204>;
|
|
cmu_id = <0x18400000>;
|
|
status = "okay";
|
|
parent = <0x13a>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x05>;
|
|
};
|
|
|
|
pd_allcsis@15862000 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15862000 0x20>;
|
|
cal_id = <0xb1380006>;
|
|
need_smc = <0x17010204>;
|
|
cmu_id = <0x170e0000>;
|
|
status = "okay";
|
|
parent = <0x13b>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x04>;
|
|
};
|
|
|
|
pd_dpub@15862080 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15862080 0x20>;
|
|
cal_id = <0xb1380007>;
|
|
need_smc = <0x19e10204>;
|
|
cmu_id = <0x19e00000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x13c>;
|
|
};
|
|
|
|
pd_dpuf@15862100 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15862100 0x20>;
|
|
cal_id = <0xb1380008>;
|
|
need_smc = <0x1ac10204>;
|
|
cmu_id = <0x1ac00000>;
|
|
status = "okay";
|
|
pd-boot-on;
|
|
parent = <0x13c>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x07>;
|
|
};
|
|
|
|
pd_g3dcore@15862280 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15862280 0x20>;
|
|
cal_id = <0xb138000a>;
|
|
need_smc = <0x16c10204>;
|
|
cmu_id = <0x16c30000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x99>;
|
|
};
|
|
|
|
pd_strong@15862300 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15862300 0x20>;
|
|
cal_id = <0xb138000b>;
|
|
cmu_id = <0x18300000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x139>;
|
|
};
|
|
|
|
pd_dnc@15862e80 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15862e80 0x20>;
|
|
cal_id = <0xb1380015>;
|
|
need_smc = <0x16010204>;
|
|
cmu_id = <0x16000000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x06>;
|
|
};
|
|
|
|
pd_hsi0@15862500 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15862500 0x20>;
|
|
cal_id = <0xb138000e>;
|
|
need_smc = <0x10a10204>;
|
|
cmu_id = <0x10a00000>;
|
|
status = "okay";
|
|
power-down-ok = <0x03>;
|
|
#power-domain-cells = <0x00>;
|
|
skip-idle-ip;
|
|
phandle = <0xdb>;
|
|
};
|
|
|
|
pd_hsi1@15862580 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15862580 0x20>;
|
|
cal_id = <0xb138000f>;
|
|
need_smc = <0x11210204>;
|
|
cmu_id = <0x11200000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
skip-idle-ip;
|
|
phandle = <0xf5>;
|
|
};
|
|
|
|
pd_lme@15862600 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15862600 0x20>;
|
|
cal_id = <0xb1380010>;
|
|
need_smc = <0x17610204>;
|
|
cmu_id = <0x17600000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x08>;
|
|
};
|
|
|
|
pd_m2m@15862680 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15862680 0x20>;
|
|
cal_id = <0xb1380011>;
|
|
need_smc = <0x18910204>;
|
|
cmu_id = <0x18900000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x09>;
|
|
};
|
|
|
|
pd_mcsc@15862780 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15862780 0x20>;
|
|
cal_id = <0xb1380012>;
|
|
need_smc = <0x15c10204>;
|
|
cmu_id = <0x15c00000>;
|
|
status = "okay";
|
|
parent = <0x13a>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x0a>;
|
|
};
|
|
|
|
pd_mfc0@15862800 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15862800 0x20>;
|
|
cal_id = <0xb1380013>;
|
|
need_smc = <0x18610204>;
|
|
cmu_id = <0x18600000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x0b>;
|
|
};
|
|
|
|
pd_mfc1@15862880 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15862880 0x20>;
|
|
cal_id = <0xb1380014>;
|
|
need_smc = <0x18810204>;
|
|
cmu_id = <0x18800000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x0c>;
|
|
};
|
|
|
|
pd_vts@15863080 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15863080 0x20>;
|
|
cal_id = <0xb1380017>;
|
|
need_smc = <0x15322000>;
|
|
cmu_id = <0x15300000>;
|
|
status = "okay";
|
|
power-down-ok = <0x02>;
|
|
#power-domain-cells = <0x00>;
|
|
skip-idle-ip;
|
|
phandle = <0xba>;
|
|
};
|
|
|
|
pd_yuvp@15863100 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15863100 0x20>;
|
|
cal_id = <0xb1380018>;
|
|
need_smc = <0x18010204>;
|
|
cmu_id = <0x18000000>;
|
|
status = "okay";
|
|
parent = <0x13a>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x0d>;
|
|
};
|
|
|
|
pd_sdma@15863180 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15863180 0x20>;
|
|
cal_id = <0xb1380019>;
|
|
need_smc = <0x16b10204>;
|
|
cmu_id = <0x16b00000>;
|
|
status = "okay";
|
|
parent = <0x06>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x13d>;
|
|
};
|
|
|
|
pd_ufd@15863300 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15863300 0x20>;
|
|
cal_id = <0xb138001a>;
|
|
need_smc = <0x15010204>;
|
|
cmu_id = <0x15000000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x141>;
|
|
};
|
|
|
|
pd_gnpu0@15862380 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15862380 0x20>;
|
|
cal_id = <0xb138000c>;
|
|
need_smc = <0x19810204>;
|
|
cmu_id = <0x19800000>;
|
|
status = "okay";
|
|
parent = <0x13d>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x13e>;
|
|
};
|
|
|
|
pd_gnpu1@15862400 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15862400 0x20>;
|
|
cal_id = <0xb138000d>;
|
|
need_smc = <0x19910204>;
|
|
cmu_id = <0x19900000>;
|
|
status = "okay";
|
|
parent = <0x13e>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x13f>;
|
|
};
|
|
|
|
pd_dsp0@15862f00 {
|
|
compatible = "samsung,exynos-pd";
|
|
reg = <0x00 0x15862f00 0x20>;
|
|
cal_id = <0xb1380016>;
|
|
need_smc = <0x16810204>;
|
|
cmu_id = <0x16800000>;
|
|
status = "okay";
|
|
parent = <0x13d>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x140>;
|
|
};
|
|
|
|
dbgdev-pd-aud {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x02>;
|
|
};
|
|
|
|
dbgdev-pd-nocl1c {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x13a>;
|
|
};
|
|
|
|
dbgdev-pd-brp {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x03>;
|
|
};
|
|
|
|
dbgdev-pd-cstat {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x05>;
|
|
};
|
|
|
|
dbgdev-pd-allcsis {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x04>;
|
|
};
|
|
|
|
dbgdev-pd-dpub {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x13c>;
|
|
};
|
|
|
|
dbgdev-pd-dpuf {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x07>;
|
|
};
|
|
|
|
dbgdev-pd-g3dcore {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x99>;
|
|
};
|
|
|
|
dbgdev-pd-strong {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x139>;
|
|
};
|
|
|
|
dbgdev-pd-dnc {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x06>;
|
|
};
|
|
|
|
dbgdev-pd-gnpu0 {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x13e>;
|
|
};
|
|
|
|
dbgdev-pd-gnpu1 {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x13f>;
|
|
};
|
|
|
|
dbgdev-pd-hsi0 {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xdb>;
|
|
};
|
|
|
|
dbgdev-pd-hsi1 {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xf5>;
|
|
};
|
|
|
|
dbgdev-pd-lme {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x08>;
|
|
};
|
|
|
|
dbgdev-pd-m2m {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x09>;
|
|
};
|
|
|
|
dbgdev-pd-mcsc {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x0a>;
|
|
};
|
|
|
|
dbgdev-pd-mfc0 {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x0b>;
|
|
};
|
|
|
|
dbgdev-pd-mfc1 {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x0c>;
|
|
};
|
|
|
|
dbgdev-pd-dsp0 {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x140>;
|
|
};
|
|
|
|
dbgdev-pd-vts {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xba>;
|
|
};
|
|
|
|
dbgdev-pd-yuvp {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x0d>;
|
|
};
|
|
|
|
dbgdev-pd-sdma {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x13d>;
|
|
};
|
|
|
|
dbgdev-pd-ufd {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x141>;
|
|
};
|
|
|
|
boot_set {
|
|
phandle = <0x142>;
|
|
|
|
sched_policy {
|
|
root = <0x05>;
|
|
foreground = <0x05>;
|
|
background = <0x05>;
|
|
top-app = <0x05>;
|
|
rt = <0x05>;
|
|
system = <0x05>;
|
|
system-background = <0x05>;
|
|
nnapi-hal = <0x05>;
|
|
camera-daemon = <0x05>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x41 0x64 0x64>;
|
|
foreground = <0x41 0x64 0x64>;
|
|
background = <0x41 0x64 0x64>;
|
|
top-app = <0x41 0x64 0x64>;
|
|
rt = <0x41 0x64 0x64>;
|
|
system = <0x41 0x64 0x64>;
|
|
system-background = <0x41 0x64 0x64>;
|
|
nnapi-hal = <0x41 0x64 0x64>;
|
|
camera-daemon = <0x41 0x64 0x64>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0x82 0xc8 0xc8>;
|
|
foreground = <0x82 0xc8 0xc8>;
|
|
background = <0x82 0xc8 0xc8>;
|
|
top-app = <0x82 0xc8 0xc8>;
|
|
rt = <0x82 0xc8 0xc8>;
|
|
system = <0x82 0xc8 0xc8>;
|
|
system-background = <0x82 0xc8 0xc8>;
|
|
nnapi-hal = <0x82 0xc8 0xc8>;
|
|
camera-daemon = <0x82 0xc8 0xc8>;
|
|
};
|
|
|
|
freqboost {
|
|
top-app = <0x05 0x05 0x05>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
|
|
ontime {
|
|
foreground = <0x01>;
|
|
top-app = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x15>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x08>;
|
|
upper-boundary = <0x4b>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x31>;
|
|
upper-boundary = <0x64>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
};
|
|
|
|
tex {
|
|
top-app = <0x01>;
|
|
prio = <0x6e>;
|
|
pinning-mask = "4-7";
|
|
qjump = <0x00>;
|
|
};
|
|
|
|
prefer_cpu {
|
|
};
|
|
|
|
stt {
|
|
boost-step = <0x14>;
|
|
htask-cnt = <0x02>;
|
|
top-app = <0x01>;
|
|
foreground = <0x01>;
|
|
};
|
|
|
|
fclamp {
|
|
|
|
monitor-group {
|
|
top-app = <0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
set@0000 {
|
|
phandle = <0x143>;
|
|
|
|
freqboost {
|
|
top-app = <0x0f 0x0f 0x0f>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x64 0x64>;
|
|
};
|
|
|
|
ontime {
|
|
top-app = <0x01>;
|
|
foreground = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x1f>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x08>;
|
|
upper-boundary = <0x42>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x2b>;
|
|
upper-boundary = <0x64>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
|
|
domain0 {
|
|
busy-threshold-ratio = <0x32>;
|
|
};
|
|
|
|
domain1 {
|
|
busy-threshold-ratio = <0x32>;
|
|
};
|
|
};
|
|
|
|
prefer_cpu {
|
|
top-app = "4-7";
|
|
};
|
|
|
|
stt {
|
|
boost-step = <0x14>;
|
|
htask-cnt = <0x02>;
|
|
top-app = <0x01>;
|
|
foreground = <0x01>;
|
|
};
|
|
|
|
fclamp {
|
|
max-freq = <0x119400 0x00 0x00>;
|
|
max-target-period = <0x04 0x00 0x00>;
|
|
max-target-ratio = <0x50 0x00 0x00>;
|
|
|
|
monitor-group {
|
|
top-app = <0x01>;
|
|
foreground = <0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
set@0001 {
|
|
phandle = <0x144>;
|
|
|
|
sched_policy {
|
|
foreground = <0x05>;
|
|
top-app = <0x05>;
|
|
};
|
|
|
|
freqboost {
|
|
top-app = <0x00 0x00 0x00>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
|
|
ontime {
|
|
foreground = <0x01>;
|
|
top-app = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x15>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x08>;
|
|
upper-boundary = <0x42>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x2b>;
|
|
upper-boundary = <0x64>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
};
|
|
};
|
|
|
|
set@0002 {
|
|
phandle = <0x145>;
|
|
|
|
sched_policy {
|
|
foreground = <0x05>;
|
|
top-app = <0x05>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
|
|
ontime {
|
|
foreground = <0x01>;
|
|
top-app = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x15>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x08>;
|
|
upper-boundary = <0x42>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x2b>;
|
|
upper-boundary = <0x64>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
};
|
|
|
|
tex {
|
|
top-app = <0x01>;
|
|
prio = <0x6e>;
|
|
pinning-mask = "4-7";
|
|
qjump = <0x00>;
|
|
};
|
|
|
|
ntu {
|
|
root = <0x00>;
|
|
foreground = <0x00>;
|
|
background = <0x00>;
|
|
top-app = <0x00>;
|
|
rt = <0x00>;
|
|
system = <0x00>;
|
|
system-background = <0x00>;
|
|
nnapi-hal = <0x00>;
|
|
camera-daemon = <0x00>;
|
|
};
|
|
|
|
prefer_cpu {
|
|
top-app = "4-7";
|
|
foreground = "4-7";
|
|
};
|
|
};
|
|
|
|
set@0100 {
|
|
phandle = <0x146>;
|
|
|
|
active_weight {
|
|
root = <0x500 0xc8 0x19>;
|
|
foreground = <0x500 0xc8 0x19>;
|
|
background = <0x500 0xc8 0x19>;
|
|
top-app = <0x500 0xc8 0x19>;
|
|
rt = <0x500 0xc8 0x19>;
|
|
system = <0x500 0xc8 0x19>;
|
|
system-background = <0x500 0xc8 0x19>;
|
|
nnapi-hal = <0x500 0xc8 0x19>;
|
|
camera-daemon = <0x500 0xc8 0x19>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0xa00 0x190 0x32>;
|
|
foreground = <0xa00 0x190 0x32>;
|
|
background = <0xa00 0x190 0x32>;
|
|
top-app = <0xa00 0x190 0x32>;
|
|
rt = <0xa00 0x190 0x32>;
|
|
system = <0xa00 0x190 0x32>;
|
|
system-background = <0xa00 0x190 0x32>;
|
|
nnapi-hal = <0xa00 0x190 0x32>;
|
|
camera-daemon = <0xa00 0x190 0x32>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x5a 0x64 0x64>;
|
|
};
|
|
|
|
ontime {
|
|
foreground = <0x01>;
|
|
top-app = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x19>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-7";
|
|
lower-boundary = <0x0d>;
|
|
upper-boundary = <0x64>;
|
|
};
|
|
};
|
|
|
|
stt {
|
|
boost-step = <0x00>;
|
|
htask-cnt = <0x04>;
|
|
top-app = <0x01>;
|
|
};
|
|
|
|
fclamp {
|
|
|
|
monitor-group {
|
|
top-app = <0x01>;
|
|
};
|
|
};
|
|
|
|
cpufreq_gov {
|
|
up-rate-limit-ms = <0x10 0x10 0x10>;
|
|
up-rate-limit-freq = <0x119400 0x232800 0x203a00>;
|
|
pelt-margin = <0x06 0x06 0x06>;
|
|
pelt-margin-freq = <0x119400 0x232800 0x203a00>;
|
|
dis-buck-share = <0x01 0x01 0x01>;
|
|
};
|
|
};
|
|
|
|
set@0101 {
|
|
phandle = <0x147>;
|
|
|
|
sched_policy {
|
|
root = <0x01>;
|
|
foreground = <0x01>;
|
|
background = <0x00>;
|
|
top-app = <0x01>;
|
|
rt = <0x01>;
|
|
system = <0x01>;
|
|
system-background = <0x01>;
|
|
nnapi-hal = <0x01>;
|
|
camera-daemon = <0x01>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x500 0xc8 0x19>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x500 0xc8 0x19>;
|
|
top-app = <0x64 0x64 0x64>;
|
|
rt = <0x500 0xc8 0x19>;
|
|
system = <0x500 0xc8 0x19>;
|
|
system-background = <0x500 0xc8 0x19>;
|
|
nnapi-hal = <0x500 0xc8 0x19>;
|
|
camera-daemon = <0x500 0xc8 0x19>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0xa00 0x190 0x32>;
|
|
foreground = <0xfa 0x3e8 0x3e8>;
|
|
background = <0xa00 0x190 0x32>;
|
|
top-app = <0xfa 0x3e8 0x3e8>;
|
|
rt = <0xa00 0x190 0x32>;
|
|
system = <0xa00 0x190 0x32>;
|
|
system-background = <0xa00 0x190 0x32>;
|
|
nnapi-hal = <0xa00 0x190 0x32>;
|
|
camera-daemon = <0xa00 0x190 0x32>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
};
|
|
|
|
set@0102 {
|
|
phandle = <0x148>;
|
|
|
|
sched_policy {
|
|
root = <0x01>;
|
|
foreground = <0x05>;
|
|
background = <0x01>;
|
|
top-app = <0x05>;
|
|
rt = <0x01>;
|
|
system = <0x01>;
|
|
system-background = <0x01>;
|
|
nnapi-hal = <0x01>;
|
|
camera-daemon = <0x01>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x64 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0xc8 0xc8 0xc8>;
|
|
foreground = <0xc8 0xc8 0xc8>;
|
|
background = <0xc8 0xc8 0xc8>;
|
|
top-app = <0xc8 0xc8 0xc8>;
|
|
rt = <0xc8 0xc8 0xc8>;
|
|
system = <0xc8 0xc8 0xc8>;
|
|
system-background = <0xc8 0xc8 0xc8>;
|
|
nnapi-hal = <0xc8 0xc8 0xc8>;
|
|
camera-daemon = <0xc8 0xc8 0xc8>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
|
|
tex {
|
|
top-app = <0x01>;
|
|
prio = <0x6e>;
|
|
pinning-mask = "4-7";
|
|
qjump = <0x00>;
|
|
};
|
|
};
|
|
|
|
set@0200 {
|
|
phandle = <0x149>;
|
|
|
|
sched_policy {
|
|
root = <0x01>;
|
|
foreground = <0x01>;
|
|
background = <0x01>;
|
|
top-app = <0x01>;
|
|
rt = <0x01>;
|
|
system = <0x01>;
|
|
system-background = <0x01>;
|
|
nnapi-hal = <0x01>;
|
|
camera-daemon = <0x01>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x96 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0xc8 0xc8 0xc8>;
|
|
foreground = <0xc8 0xc8 0xc8>;
|
|
background = <0xc8 0xc8 0xc8>;
|
|
top-app = <0xc8 0x12c 0xc8>;
|
|
rt = <0xc8 0xc8 0xc8>;
|
|
system = <0xc8 0xc8 0xc8>;
|
|
system-background = <0xc8 0xc8 0xc8>;
|
|
nnapi-hal = <0xc8 0xc8 0xc8>;
|
|
camera-daemon = <0xc8 0xc8 0xc8>;
|
|
};
|
|
|
|
freqboost {
|
|
top-app = <0x00 0x00 0x00>;
|
|
};
|
|
|
|
wakeboost {
|
|
top-app = <0x4b 0x4b 0x4b>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x64 0x64>;
|
|
};
|
|
|
|
ontime {
|
|
foreground = <0x01>;
|
|
top-app = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x05>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x01>;
|
|
upper-boundary = <0x3f>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x27>;
|
|
upper-boundary = <0x64>;
|
|
};
|
|
};
|
|
|
|
prefer_cpu {
|
|
top-app = "4-7";
|
|
};
|
|
|
|
stt {
|
|
boost-step = <0x19>;
|
|
htask-cnt = <0x02>;
|
|
top-app = <0x01>;
|
|
foreground = <0x01>;
|
|
};
|
|
|
|
fclamp {
|
|
max-freq = <0x148200 0x00 0x00>;
|
|
max-target-period = <0x04 0x00 0x00>;
|
|
max-target-ratio = <0x50 0x00 0x00>;
|
|
|
|
monitor-group {
|
|
top-app = <0x01>;
|
|
foreground = <0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
set@0201 {
|
|
phandle = <0x14a>;
|
|
|
|
active_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x96 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0xc8 0xc8 0xc8>;
|
|
foreground = <0xfa 0x3e8 0x3e8>;
|
|
background = <0xc8 0xc8 0xc8>;
|
|
top-app = <0xfa 0x3e8 0x3e8>;
|
|
rt = <0xc8 0xc8 0xc8>;
|
|
system = <0xc8 0xc8 0xc8>;
|
|
system-background = <0xc8 0xc8 0xc8>;
|
|
nnapi-hal = <0xc8 0xc8 0xc8>;
|
|
camera-daemon = <0xc8 0xc8 0xc8>;
|
|
};
|
|
|
|
wakeboost {
|
|
top-app = <0x28 0x28 0x28>;
|
|
};
|
|
};
|
|
|
|
set@0202 {
|
|
phandle = <0x14b>;
|
|
|
|
sched_policy {
|
|
root = <0x01>;
|
|
foreground = <0x05>;
|
|
background = <0x01>;
|
|
top-app = <0x05>;
|
|
rt = <0x01>;
|
|
system = <0x01>;
|
|
system-background = <0x01>;
|
|
nnapi-hal = <0x01>;
|
|
camera-daemon = <0x01>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x96 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0xc8 0xc8 0xc8>;
|
|
foreground = <0xc8 0xc8 0xc8>;
|
|
background = <0xc8 0xc8 0xc8>;
|
|
top-app = <0xc8 0x12c 0xc8>;
|
|
rt = <0xc8 0xc8 0xc8>;
|
|
system = <0xc8 0xc8 0xc8>;
|
|
system-background = <0xc8 0xc8 0xc8>;
|
|
nnapi-hal = <0xc8 0xc8 0xc8>;
|
|
camera-daemon = <0xc8 0xc8 0xc8>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
|
|
tex {
|
|
top-app = <0x01>;
|
|
prio = <0x6e>;
|
|
pinning-mask = "4-7";
|
|
qjump = <0x00>;
|
|
};
|
|
};
|
|
|
|
set@0300 {
|
|
phandle = <0x14c>;
|
|
|
|
frt {
|
|
active-ratio = <0x32 0x64 0x64>;
|
|
};
|
|
|
|
ontime {
|
|
foreground = <0x01>;
|
|
top-app = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x12>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-7";
|
|
lower-boundary = <0x06>;
|
|
upper-boundary = <0x64>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
|
|
domain0 {
|
|
busy-threshold-ratio = <0x00>;
|
|
};
|
|
|
|
domain1 {
|
|
busy-threshold-ratio = <0x5f>;
|
|
};
|
|
};
|
|
|
|
cpus_binding {
|
|
target-sched-class = <0x08>;
|
|
background = "0-3";
|
|
};
|
|
|
|
stt {
|
|
boost-step = <0x0a>;
|
|
htask-cnt = <0x04>;
|
|
top-app = <0x01>;
|
|
};
|
|
|
|
fclamp {
|
|
|
|
monitor-group {
|
|
top-app = <0x01>;
|
|
};
|
|
};
|
|
|
|
cpufreq_gov {
|
|
up-rate-limit-ms = <0x10 0x10 0x10>;
|
|
up-rate-limit-freq = <0x119400 0x232800 0x203a00>;
|
|
pelt-margin = <0x06 0x06 0x06>;
|
|
pelt-margin-freq = <0x119400 0x232800 0x203a00>;
|
|
};
|
|
};
|
|
|
|
set@0301 {
|
|
phandle = <0x14d>;
|
|
};
|
|
|
|
set@0302 {
|
|
phandle = <0x14e>;
|
|
|
|
sched_policy {
|
|
root = <0x01>;
|
|
foreground = <0x05>;
|
|
background = <0x01>;
|
|
top-app = <0x05>;
|
|
rt = <0x01>;
|
|
system = <0x01>;
|
|
system-background = <0x01>;
|
|
nnapi-hal = <0x01>;
|
|
camera-daemon = <0x01>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0xc8 0xc8 0xc8>;
|
|
foreground = <0xc8 0xc8 0xc8>;
|
|
background = <0xc8 0xc8 0xc8>;
|
|
top-app = <0xc8 0xc8 0xc8>;
|
|
rt = <0xc8 0xc8 0xc8>;
|
|
system = <0xc8 0xc8 0xc8>;
|
|
system-background = <0xc8 0xc8 0xc8>;
|
|
nnapi-hal = <0xc8 0xc8 0xc8>;
|
|
camera-daemon = <0xc8 0xc8 0xc8>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
|
|
tex {
|
|
top-app = <0x01>;
|
|
prio = <0x6e>;
|
|
pinning-mask = "4-7";
|
|
qjump = <0x00>;
|
|
};
|
|
};
|
|
|
|
set@0400 {
|
|
phandle = <0x14f>;
|
|
|
|
freqboost {
|
|
top-app = <0x00 0x00 0x00>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x64 0x64>;
|
|
};
|
|
|
|
ontime {
|
|
top-app = <0x01>;
|
|
foreground = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x1f>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x08>;
|
|
upper-boundary = <0x42>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x2b>;
|
|
upper-boundary = <0x64>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
|
|
domain0 {
|
|
busy-threshold-ratio = <0x32>;
|
|
};
|
|
|
|
domain1 {
|
|
busy-threshold-ratio = <0x32>;
|
|
};
|
|
};
|
|
|
|
prefer_cpu {
|
|
top-app = "4-7";
|
|
};
|
|
|
|
stt {
|
|
boost-step = <0x00>;
|
|
htask-cnt = <0x02>;
|
|
top-app = <0x01>;
|
|
foreground = <0x01>;
|
|
};
|
|
|
|
fclamp {
|
|
max-freq = <0x119400 0x00 0x266038>;
|
|
max-target-period = <0x04 0x00 0x04>;
|
|
max-target-ratio = <0x50 0x00 0x50>;
|
|
|
|
monitor-group {
|
|
top-app = <0x01>;
|
|
foreground = <0x01>;
|
|
};
|
|
};
|
|
|
|
cpufreq_gov {
|
|
up-rate-limit-ms = <0x10 0x10 0x10>;
|
|
up-rate-limit-freq = <0x119400 0x232800 0x203a00>;
|
|
pelt-margin = <0x06 0x06 0x06>;
|
|
pelt-margin-freq = <0x119400 0x232800 0x203a00>;
|
|
dis-buck-share = <0x01 0x01 0x01>;
|
|
};
|
|
};
|
|
|
|
set@0401 {
|
|
phandle = <0x150>;
|
|
|
|
sched_policy {
|
|
foreground = <0x05>;
|
|
top-app = <0x05>;
|
|
};
|
|
|
|
freqboost {
|
|
top-app = <0x00 0x00 0x00>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
|
|
ontime {
|
|
foreground = <0x01>;
|
|
top-app = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x15>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x08>;
|
|
upper-boundary = <0x42>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x2b>;
|
|
upper-boundary = <0x64>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
};
|
|
};
|
|
|
|
set@0402 {
|
|
phandle = <0x151>;
|
|
|
|
sched_policy {
|
|
foreground = <0x05>;
|
|
top-app = <0x05>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
|
|
ontime {
|
|
foreground = <0x01>;
|
|
top-app = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x15>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x08>;
|
|
upper-boundary = <0x42>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x2b>;
|
|
upper-boundary = <0x64>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
};
|
|
|
|
tex {
|
|
top-app = <0x01>;
|
|
prio = <0x6e>;
|
|
pinning-mask = "4-7";
|
|
qjump = <0x00>;
|
|
};
|
|
|
|
ntu {
|
|
root = <0x00>;
|
|
foreground = <0x00>;
|
|
background = <0x00>;
|
|
top-app = <0x00>;
|
|
rt = <0x00>;
|
|
system = <0x00>;
|
|
system-background = <0x00>;
|
|
nnapi-hal = <0x00>;
|
|
camera-daemon = <0x00>;
|
|
};
|
|
|
|
prefer_cpu {
|
|
top-app = "4-7";
|
|
foreground = "4-7";
|
|
};
|
|
};
|
|
|
|
set@0500 {
|
|
phandle = <0x152>;
|
|
|
|
sched_policy {
|
|
root = <0x00>;
|
|
foreground = <0x00>;
|
|
background = <0x00>;
|
|
top-app = <0x00>;
|
|
rt = <0x00>;
|
|
system = <0x00>;
|
|
system-background = <0x00>;
|
|
nnapi-hal = <0x00>;
|
|
camera-daemon = <0x00>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x64 0x12c 0x190>;
|
|
foreground = <0x64 0x12c 0x190>;
|
|
background = <0x64 0x12c 0x190>;
|
|
top-app = <0x64 0x12c 0x190>;
|
|
rt = <0x64 0x12c 0x190>;
|
|
system = <0x64 0x12c 0x190>;
|
|
system-background = <0x64 0x12c 0x190>;
|
|
nnapi-hal = <0x64 0x12c 0x190>;
|
|
camera-daemon = <0x64 0x12c 0x190>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x64 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
freqboost {
|
|
top-app = <0x05 0x05 0x05>;
|
|
};
|
|
|
|
wakeboost {
|
|
top-app = <0x00 0x00 0x00>;
|
|
};
|
|
|
|
esg {
|
|
step = <0x04 0x06 0x08>;
|
|
pelt-margin = <0x19 0x19 0x19>;
|
|
up-rate-limit-ms = <0x04>;
|
|
down-rate-limit-ms = <0x08>;
|
|
rapid-scale-up = <0x01>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x64 0x64>;
|
|
};
|
|
|
|
ontime {
|
|
top-app = <0x01>;
|
|
foreground = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x15>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x08>;
|
|
upper-boundary = <0x4b>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x31>;
|
|
upper-boundary = <0x64>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
|
|
domain0 {
|
|
busy-threshold-ratio = <0x32>;
|
|
};
|
|
|
|
domain1 {
|
|
busy-threshold-ratio = <0x05>;
|
|
};
|
|
};
|
|
|
|
prefer_cpu {
|
|
top-app = "4-7";
|
|
};
|
|
|
|
stt {
|
|
boost-step = <0x14>;
|
|
htask-cnt = <0x02>;
|
|
top-app = <0x01>;
|
|
foreground = <0x01>;
|
|
};
|
|
|
|
cpufreq_gov {
|
|
pelt-margin = <0x05 0x19 0x19>;
|
|
};
|
|
};
|
|
|
|
set@0501 {
|
|
phandle = <0x153>;
|
|
|
|
sched_policy {
|
|
root = <0x00>;
|
|
foreground = <0x00>;
|
|
background = <0x00>;
|
|
top-app = <0x05>;
|
|
rt = <0x00>;
|
|
system = <0x00>;
|
|
system-background = <0x00>;
|
|
nnapi-hal = <0x00>;
|
|
camera-daemon = <0x00>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x64 0x12c 0x12c>;
|
|
foreground = <0x64 0x12c 0x12c>;
|
|
background = <0x64 0x12c 0x12c>;
|
|
top-app = <0x64 0x12c 0x12c>;
|
|
rt = <0x64 0x12c 0x12c>;
|
|
system = <0x64 0x12c 0x12c>;
|
|
system-background = <0x64 0x12c 0x12c>;
|
|
nnapi-hal = <0x64 0x12c 0x12c>;
|
|
camera-daemon = <0x64 0x12c 0x12c>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x64 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
freqboost {
|
|
top-app = <0x1e 0x1e 0x1e>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
|
|
ontime {
|
|
foreground = <0x01>;
|
|
top-app = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x15>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x08>;
|
|
upper-boundary = <0x4b>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x31>;
|
|
upper-boundary = <0x64>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
};
|
|
};
|
|
|
|
set@0502 {
|
|
phandle = <0x154>;
|
|
|
|
sched_policy {
|
|
root = <0x01>;
|
|
foreground = <0x05>;
|
|
background = <0x01>;
|
|
top-app = <0x05>;
|
|
rt = <0x01>;
|
|
system = <0x01>;
|
|
system-background = <0x01>;
|
|
nnapi-hal = <0x01>;
|
|
camera-daemon = <0x01>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x41 0x12c 0x12c>;
|
|
foreground = <0x41 0x12c 0x12c>;
|
|
background = <0x41 0x12c 0x12c>;
|
|
top-app = <0x41 0x12c 0x12c>;
|
|
rt = <0x41 0x12c 0x12c>;
|
|
system = <0x41 0x12c 0x12c>;
|
|
system-background = <0x41 0x12c 0x12c>;
|
|
nnapi-hal = <0x41 0x12c 0x12c>;
|
|
camera-daemon = <0x41 0x12c 0x12c>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0x82 0xc8 0xc8>;
|
|
foreground = <0x82 0xc8 0xc8>;
|
|
background = <0x82 0xc8 0xc8>;
|
|
top-app = <0x82 0xc8 0xc8>;
|
|
rt = <0x82 0xc8 0xc8>;
|
|
system = <0x82 0xc8 0xc8>;
|
|
system-background = <0x82 0xc8 0xc8>;
|
|
nnapi-hal = <0x82 0xc8 0xc8>;
|
|
camera-daemon = <0x82 0xc8 0xc8>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
|
|
ontime {
|
|
foreground = <0x01>;
|
|
top-app = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x15>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x08>;
|
|
upper-boundary = <0x4b>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x31>;
|
|
upper-boundary = <0x64>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
};
|
|
|
|
tex {
|
|
top-app = <0x01>;
|
|
prio = <0x6e>;
|
|
pinning-mask = "4-7";
|
|
qjump = <0x00>;
|
|
};
|
|
|
|
prefer_cpu {
|
|
};
|
|
};
|
|
|
|
set@0600 {
|
|
phandle = <0x155>;
|
|
|
|
freqboost {
|
|
top-app = <0x00 0x00 0x00>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x64 0x64>;
|
|
};
|
|
|
|
ontime {
|
|
top-app = <0x01>;
|
|
foreground = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x1f>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x08>;
|
|
upper-boundary = <0x42>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x2b>;
|
|
upper-boundary = <0x64>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
|
|
domain0 {
|
|
busy-threshold-ratio = <0x32>;
|
|
};
|
|
|
|
domain1 {
|
|
busy-threshold-ratio = <0x32>;
|
|
};
|
|
};
|
|
|
|
prefer_cpu {
|
|
top-app = "4-7";
|
|
};
|
|
|
|
stt {
|
|
boost-step = <0x05>;
|
|
htask-cnt = <0x02>;
|
|
top-app = <0x01>;
|
|
foreground = <0x01>;
|
|
};
|
|
|
|
fclamp {
|
|
max-freq = <0x119400 0x00 0x00>;
|
|
max-target-period = <0x04 0x00 0x00>;
|
|
max-target-ratio = <0x50 0x00 0x00>;
|
|
|
|
monitor-group {
|
|
top-app = <0x01>;
|
|
foreground = <0x01>;
|
|
};
|
|
};
|
|
|
|
cpufreq_gov {
|
|
up-rate-limit-ms = <0x10 0x10 0x10>;
|
|
up-rate-limit-freq = <0x119400 0x232800 0x203a00>;
|
|
pelt-margin = <0x06 0x06 0x06>;
|
|
pelt-margin-freq = <0x119400 0x232800 0x203a00>;
|
|
dis-buck-share = <0x01 0x01 0x01>;
|
|
};
|
|
};
|
|
|
|
set@0601 {
|
|
phandle = <0x156>;
|
|
|
|
sched_policy {
|
|
foreground = <0x05>;
|
|
top-app = <0x05>;
|
|
};
|
|
|
|
freqboost {
|
|
top-app = <0x00 0x00 0x00>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
|
|
ontime {
|
|
foreground = <0x01>;
|
|
top-app = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x15>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x08>;
|
|
upper-boundary = <0x42>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x2b>;
|
|
upper-boundary = <0x64>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
};
|
|
};
|
|
|
|
set@0602 {
|
|
phandle = <0x157>;
|
|
|
|
sched_policy {
|
|
foreground = <0x05>;
|
|
top-app = <0x05>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
|
|
ontime {
|
|
foreground = <0x01>;
|
|
top-app = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x15>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x08>;
|
|
upper-boundary = <0x42>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x2b>;
|
|
upper-boundary = <0x64>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
};
|
|
|
|
tex {
|
|
top-app = <0x01>;
|
|
prio = <0x6e>;
|
|
pinning-mask = "4-7";
|
|
qjump = <0x00>;
|
|
};
|
|
|
|
ntu {
|
|
root = <0x00>;
|
|
foreground = <0x00>;
|
|
background = <0x00>;
|
|
top-app = <0x00>;
|
|
rt = <0x00>;
|
|
system = <0x00>;
|
|
system-background = <0x00>;
|
|
nnapi-hal = <0x00>;
|
|
camera-daemon = <0x00>;
|
|
};
|
|
|
|
prefer_cpu {
|
|
top-app = "4-7";
|
|
foreground = "4-7";
|
|
};
|
|
};
|
|
|
|
ems {
|
|
compatible = "samsung,ems";
|
|
status = "okay";
|
|
|
|
cpu-selection-domain {
|
|
|
|
klein-complex0 {
|
|
cpus = "0-1";
|
|
};
|
|
|
|
klein-complex1 {
|
|
cpus = "2-3";
|
|
};
|
|
|
|
matterhorn {
|
|
cpus = "4-6";
|
|
};
|
|
|
|
montblanc {
|
|
cpus = "7";
|
|
};
|
|
};
|
|
|
|
esg {
|
|
thread-run-on = "0-6";
|
|
|
|
domain@0 {
|
|
shared-cpus = "0-3";
|
|
};
|
|
|
|
domain@1 {
|
|
shared-cpus = "4-6";
|
|
};
|
|
|
|
domain@2 {
|
|
shared-cpus = "7";
|
|
};
|
|
};
|
|
|
|
ego {
|
|
thread-run-on = "0-6";
|
|
|
|
domain@0 {
|
|
cpus = "0-3";
|
|
ratio = <0x3e8>;
|
|
};
|
|
|
|
domain@1 {
|
|
cpus = "4-6";
|
|
ratio = <0x3e8>;
|
|
somac_wall = <0x2bf200>;
|
|
};
|
|
|
|
domain@2 {
|
|
cpus = "7";
|
|
ratio = <0x3e8>;
|
|
somac_wall = <0x2bf200>;
|
|
};
|
|
};
|
|
|
|
stt {
|
|
|
|
domain@0 {
|
|
cpus = "0-3";
|
|
};
|
|
|
|
domain@1 {
|
|
cpus = "4-6";
|
|
};
|
|
|
|
domain@2 {
|
|
cpus = "7";
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
|
|
stage0 {
|
|
cpus = "0-1";
|
|
};
|
|
|
|
stage1 {
|
|
cpus = "0-3";
|
|
};
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-7";
|
|
|
|
stage0 {
|
|
cpus = "4-5";
|
|
};
|
|
|
|
stage1 {
|
|
cpus = "4-6";
|
|
};
|
|
|
|
stage2 {
|
|
cpus = "4-7";
|
|
};
|
|
};
|
|
};
|
|
|
|
emstune {
|
|
boost-level = <0x02>;
|
|
boot-set = <0x142>;
|
|
|
|
mode0 {
|
|
desc = "high";
|
|
|
|
level0 {
|
|
base = <0x143>;
|
|
set = <0x143>;
|
|
};
|
|
|
|
level1 {
|
|
base = <0x143>;
|
|
set = <0x144>;
|
|
};
|
|
|
|
level2 {
|
|
base = <0x143>;
|
|
set = <0x145>;
|
|
};
|
|
};
|
|
|
|
mode1 {
|
|
desc = "power-scenario";
|
|
|
|
level0 {
|
|
base = <0x146>;
|
|
set = <0x146>;
|
|
};
|
|
|
|
level1 {
|
|
base = <0x146>;
|
|
set = <0x147>;
|
|
};
|
|
|
|
level2 {
|
|
base = <0x146>;
|
|
set = <0x148>;
|
|
};
|
|
};
|
|
|
|
mode2 {
|
|
desc = "performance";
|
|
|
|
level0 {
|
|
base = <0x149>;
|
|
set = <0x149>;
|
|
};
|
|
|
|
level1 {
|
|
base = <0x149>;
|
|
set = <0x14a>;
|
|
};
|
|
|
|
level2 {
|
|
base = <0x149>;
|
|
set = <0x14b>;
|
|
};
|
|
};
|
|
|
|
mode3 {
|
|
desc = "game";
|
|
|
|
level0 {
|
|
base = <0x14c>;
|
|
set = <0x14c>;
|
|
};
|
|
|
|
level1 {
|
|
base = <0x14c>;
|
|
set = <0x14d>;
|
|
};
|
|
|
|
level2 {
|
|
base = <0x14c>;
|
|
set = <0x14e>;
|
|
};
|
|
};
|
|
|
|
mode4 {
|
|
desc = "balance";
|
|
|
|
level0 {
|
|
base = <0x14f>;
|
|
set = <0x14f>;
|
|
};
|
|
|
|
level1 {
|
|
base = <0x14f>;
|
|
set = <0x150>;
|
|
};
|
|
|
|
level2 {
|
|
base = <0x14f>;
|
|
set = <0x151>;
|
|
};
|
|
};
|
|
|
|
mode5 {
|
|
desc = "camera";
|
|
|
|
level0 {
|
|
base = <0x152>;
|
|
set = <0x152>;
|
|
};
|
|
|
|
level1 {
|
|
base = <0x152>;
|
|
set = <0x153>;
|
|
};
|
|
|
|
level2 {
|
|
base = <0x152>;
|
|
set = <0x154>;
|
|
};
|
|
};
|
|
|
|
mode6 {
|
|
desc = "normal";
|
|
|
|
level0 {
|
|
base = <0x155>;
|
|
set = <0x155>;
|
|
};
|
|
|
|
level1 {
|
|
base = <0x155>;
|
|
set = <0x156>;
|
|
};
|
|
|
|
level2 {
|
|
base = <0x155>;
|
|
set = <0x157>;
|
|
};
|
|
};
|
|
};
|
|
|
|
sysbusy {
|
|
somac-ready-run = <0x01>;
|
|
somac-ready-cpus = "0-3";
|
|
};
|
|
|
|
gsc {
|
|
enabled = <0x01>;
|
|
up_threshold = <0xb9>;
|
|
down_threshold = <0x9b>;
|
|
min_interval_us = <0xbb80>;
|
|
min_retain_us = <0x1d4c0>;
|
|
min_admit_ns = <0x5f5e100>;
|
|
};
|
|
};
|
|
|
|
mfc {
|
|
compatible = "samsung,exynos-mfc";
|
|
iommus = <0x158 0x159 0x15a 0x15b>;
|
|
samsung,iommu-group = <0x15c>;
|
|
samsung,iommu-reserved-map = <0x00 0x00 0x10000000 0x00 0x10000000 0x100000 0x00 0x10100000 0x100000>;
|
|
samsung,iommu-identity-map = <0x00 0x1771f000 0x10000 0x00 0x1ad2f000 0x10000>;
|
|
samsung,tzmp;
|
|
memory-region = <0x15d>;
|
|
ip_ver = <0x1600010c>;
|
|
debug_mode = <0x00>;
|
|
nal_q_entry_size = <0x300>;
|
|
nal_q_dump_size = <0x178>;
|
|
nal_q = <0x01 0x00>;
|
|
skype = <0x01 0x00>;
|
|
black_bar = <0x01 0x00>;
|
|
color_aspect_dec = <0x01 0x00>;
|
|
static_info_dec = <0x01 0x00>;
|
|
color_aspect_enc = <0x01 0x00>;
|
|
static_info_enc = <0x01 0x180314>;
|
|
hdr10_plus = <0x01 0x180709>;
|
|
vp9_stride_align = <0x01 0x00>;
|
|
sbwc_uncomp = <0x01 0x190702>;
|
|
mem_clear = <0x01 0x00>;
|
|
wait_fw_status = <0x01 0x190122>;
|
|
wait_nalq_status = <0x01 0x191107>;
|
|
drm_switch_predict = <0x01 0x00>;
|
|
sbwc_enc_src_ctrl = <0x01 0x200110>;
|
|
metadata_interface = <0x01 0x200910>;
|
|
hdr10_plus_full = <0x01 0x200910>;
|
|
average_qp = <0x01 0x201030>;
|
|
mv_search_mode = <0x01 0x201118>;
|
|
hdr10_plus_stat_info = <0x01 0x210402>;
|
|
enc_idr_flag = <0x01 0x210611>;
|
|
min_quality_mode = <0x01 0x210705>;
|
|
enc_ts_delta = <0x01 0x211027>;
|
|
wfd_rc_mode = <0x01 0x211229>;
|
|
support_av1_dec = <0x01>;
|
|
av1_film_grain = <0x01 0x200717>;
|
|
P010_decoding = <0x01>;
|
|
dithering_enable = <0x00>;
|
|
stride_align = <0x100>;
|
|
stride_type = <0x01>;
|
|
support_10bit = <0x01>;
|
|
support_422 = <0x00>;
|
|
support_rgb = <0x01>;
|
|
support_sbwc = <0x01>;
|
|
support_sbwcl = <0x01>;
|
|
support_sbwcl40 = <0x01>;
|
|
sbwc_dec_max_width = <0xf00>;
|
|
sbwc_dec_max_height = <0x870>;
|
|
sbwc_dec_max_inst_num = <0x01>;
|
|
sbwc_dec_max_framerate = <0x3c>;
|
|
sbwc_dec_hdr10_off = <0x00>;
|
|
max_hdr_win = <0x01>;
|
|
hdr10_plus_profile = <0x03>;
|
|
display_err_type = <0x02>;
|
|
security_ctrl = <0x01>;
|
|
display_framerate = <0x00>;
|
|
enc_param_num = <0x19>;
|
|
enc_param_addr = <0xf7b4 0xf7b8 0xf7b0 0xf798 0xfa2c 0xf790 0xfa34 0xfa38 0xfa3c 0xf7c0 0xf7c8 0xf7cc 0xfa60 0xfdd4 0xfddc 0xfb54 0xfb58 0xfba8 0xfd90 0xfd94 0xfd40 0xfd48 0xfd4c 0xfd50 0xfd80>;
|
|
enc_param_val = <0x80 0x80 0x00 0x4000 0x3fd00 0x00 0x00 0x2710 0x3e8 0x00 0x00 0x00 0x00 0x8050d211 0x00 0x3011 0x00 0x00 0x2d 0xa00 0x1d 0xf4240 0x33003300 0x02 0x01>;
|
|
bw_enc_h264 = <0xb190 0xdb30 0x2ba2>;
|
|
bw_enc_hevc = <0xb6a4 0xce1e 0x2623>;
|
|
bw_enc_hevc_10bit = <0xd269 0xfcf1 0x310c>;
|
|
bw_enc_vp8 = <0xfa00 0x106f6 0x57f6>;
|
|
bw_enc_vp9 = <0x11a86 0xe94e 0x4092>;
|
|
bw_enc_vp9_10bit = <0x2465d 0x1c0f0 0x7abb>;
|
|
bw_enc_mpeg4 = <0xae67 0xd81c 0x253b>;
|
|
bw_dec_h264 = <0x7f5d 0x864d 0x530f>;
|
|
bw_dec_hevc = <0x7515 0x70b3 0x4482>;
|
|
bw_dec_hevc_10bit = <0xce7b 0xb4a5 0x7a77>;
|
|
bw_dec_vp8 = <0x7000 0x7704 0x5734>;
|
|
bw_dec_vp9 = <0x47af 0x4a03 0x41ed>;
|
|
bw_dec_vp9_10bit = <0xa590 0x8694 0x7c16>;
|
|
bw_dec_av1 = <0x5ceb 0x4c72 0x3df0>;
|
|
bw_dec_av1_10bit = <0xa1bf 0x8aa2 0x7403>;
|
|
bw_dec_mpeg4 = <0x7b34 0x6318 0x3d9a>;
|
|
sbwc_bw_enc_h264 = <0x7b86 0x7db7 0x1b99>;
|
|
sbwc_bw_enc_hevc = <0x5dec 0x6b86 0x1700>;
|
|
sbwc_bw_enc_hevc_10bit = <0x7f9a 0x92da 0x2289>;
|
|
sbwc_bw_enc_vp8 = <0x7f9a 0x92da 0x2289>;
|
|
sbwc_bw_enc_vp9 = <0x5aec 0x6904 0x21fe>;
|
|
sbwc_bw_enc_vp9_10bit = <0xa53e 0xa09c 0x36e4>;
|
|
sbwc_bw_enc_mpeg4 = <0x7f9a 0x92da 0x2289>;
|
|
sbwc_bw_dec_h264 = <0x5ccd 0x48ab 0x3534>;
|
|
sbwc_bw_dec_hevc = <0x3bcd 0x3c1b 0x2827>;
|
|
sbwc_bw_dec_hevc_10bit = <0x5148 0x507a 0x3a14>;
|
|
sbwc_bw_dec_vp8 = <0x4333 0x4769 0x3452>;
|
|
sbwc_bw_dec_vp9 = <0x2b71 0x25db 0x2327>;
|
|
sbwc_bw_dec_vp9_10bit = <0x457b 0x3cde 0x384d>;
|
|
sbwc_bw_dec_mpeg4 = <0x49ec 0x3b75 0x24f6>;
|
|
num_mfc_freq = <0x07>;
|
|
mfc_freqs = <0x20788 0x412f8 0x510e0 0x61a80 0x82208 0xa1dd8 0xc3500>;
|
|
max_Kbps = <0x3c000 0x14000>;
|
|
dynamic_weight = <0x01>;
|
|
qos_weight_h264_hevc = <0x64>;
|
|
qos_weight_vp8_vp9 = <0x64>;
|
|
qos_weight_av1 = <0x46>;
|
|
qos_weight_other_codec = <0x19>;
|
|
qos_weight_3plane = <0x50>;
|
|
qos_weight_10bit = <0x4b>;
|
|
qos_weight_422 = <0x46>;
|
|
qos_weight_bframe = <0x32>;
|
|
qos_weight_num_of_ref = <0x3c>;
|
|
qos_weight_gpb = <0x32>;
|
|
qos_weight_num_of_tile = <0x4b>;
|
|
qos_weight_super64_bframe = <0x3c>;
|
|
qos_weight_mbaff = <0x3c>;
|
|
core_balance = <0x36>;
|
|
iova_threshold = <0x6a4>;
|
|
idle_clk_ctrl = <0x01>;
|
|
qos_ctrl_level = <0x01>;
|
|
int_freq_fw_verify = <0x61a80>;
|
|
enc_timing_dis = <0x01>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
phandle = <0x323>;
|
|
|
|
MFC-0 {
|
|
compatible = "samsung,exynos-mfc-core";
|
|
id = <0x00>;
|
|
reg = <0x00 0x186d0000 0x10000>;
|
|
interrupts = <0x00 0x242 0x04>;
|
|
clock-names = "aclk_mfc";
|
|
clocks = <0x19 0x9c4>;
|
|
iommus = <0x158 0x159>;
|
|
samsung,iommu-group = <0x15c>;
|
|
samsung,iommu-reserved-map = <0x00 0x10000000 0x100000>;
|
|
samsung,iommu-identity-map = <0x00 0x1771f000 0x10000 0x00 0x1ad2f000 0x10000>;
|
|
samsung,tzmp;
|
|
samsung,imgloader-s2mpu-support;
|
|
ip_ver = <0x1600010c>;
|
|
share_sysmmu = <0x00>;
|
|
axid_mask = <0x07>;
|
|
mfc_fault_num = <0x00>;
|
|
trans_info_offset = <0x1004>;
|
|
tsmux_axid = <0x01>;
|
|
llc = <0x01>;
|
|
need_llc_flush = <0x00>;
|
|
mfc_votf_base = <0x18700000>;
|
|
gdc_votf_base = <0x1771f000>;
|
|
dpu_votf_base = <0x1ad2f000>;
|
|
num_default_qos_steps = <0x0a>;
|
|
num_encoder_qos_steps = <0x07>;
|
|
max_mb = <0x4db795>;
|
|
max_hw_mb = <0x3b5380>;
|
|
mfc_freq_control = <0x01>;
|
|
mo_control = <0x01>;
|
|
bw_control = <0x01>;
|
|
memlog_size = <0x80000>;
|
|
memlog_sfr_size = <0x1000>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
phandle = <0x324>;
|
|
|
|
iommu {
|
|
reg = <0x00 0x18670000 0x9000 0x00 0x186a0000 0x9000>;
|
|
};
|
|
|
|
votf {
|
|
reg = <0x00 0x18700000 0x1000>;
|
|
};
|
|
|
|
mfc_default_qos_table {
|
|
|
|
mfc_d_qos_variant_0 {
|
|
thrd_mb = <0x00>;
|
|
freq_mfc = <0x20788>;
|
|
freq_int = <0x20788>;
|
|
freq_mif = <0x66c88>;
|
|
bts_scen = "default";
|
|
time_fw = <0x4d6>;
|
|
};
|
|
|
|
mfc_d_qos_variant_1 {
|
|
thrd_mb = <0x85727>;
|
|
freq_mfc = <0x412f8>;
|
|
freq_int = <0x20788>;
|
|
freq_mif = <0x854d0>;
|
|
bts_scen = "default";
|
|
time_fw = <0x34a>;
|
|
};
|
|
|
|
mfc_d_qos_variant_2 {
|
|
thrd_mb = <0x11cf37>;
|
|
freq_mfc = <0x510e0>;
|
|
freq_int = <0x30d40>;
|
|
freq_mif = <0xa50a0>;
|
|
bts_scen = "default";
|
|
time_fw = <0x29b>;
|
|
};
|
|
|
|
mfc_d_qos_variant_3 {
|
|
thrd_mb = <0x1c5f35>;
|
|
freq_mfc = <0x510e0>;
|
|
freq_int = <0x30d40>;
|
|
freq_mif = <0xce4c8>;
|
|
bts_scen = "default";
|
|
time_fw = <0x242>;
|
|
};
|
|
|
|
mfc_d_qos_variant_4 {
|
|
thrd_mb = <0x1fb6e1>;
|
|
freq_mfc = <0x72420>;
|
|
freq_int = <0x30d40>;
|
|
freq_mif = <0xf78f0>;
|
|
bts_scen = "default";
|
|
time_fw = <0x1e3>;
|
|
};
|
|
|
|
mfc_d_qos_variant_5 {
|
|
thrd_mb = <0x271c0a>;
|
|
freq_mfc = <0x82208>;
|
|
freq_int = <0x510e0>;
|
|
freq_mif = <0x14a140>;
|
|
bts_scen = "default";
|
|
time_fw = <0x16a>;
|
|
};
|
|
|
|
mfc_d_qos_variant_6 {
|
|
thrd_mb = <0x306d8d>;
|
|
freq_mfc = <0xa1dd8>;
|
|
freq_int = <0x61a80>;
|
|
freq_mif = <0x14a140>;
|
|
bts_scen = "default";
|
|
time_fw = <0x132>;
|
|
};
|
|
|
|
mfc_d_qos_variant_7 {
|
|
thrd_mb = <0x38b5b1>;
|
|
freq_mfc = <0xb5e28>;
|
|
freq_int = <0x82208>;
|
|
freq_mif = <0x177bb8>;
|
|
bts_scen = "default";
|
|
time_fw = <0x10b>;
|
|
};
|
|
|
|
mfc_d_qos_variant_8 {
|
|
thrd_mb = <0x41570e>;
|
|
freq_mfc = <0xb5e28>;
|
|
freq_int = <0xa1dd8>;
|
|
freq_mif = <0x1ef1e0>;
|
|
bts_scen = "default";
|
|
time_fw = <0xeb>;
|
|
};
|
|
|
|
mfc_d_qos_variant_9 {
|
|
thrd_mb = <0x4a180a>;
|
|
freq_mfc = "\0\f5";
|
|
freq_int = "\0\f5";
|
|
freq_mif = <0x3066a0>;
|
|
bts_scen = "mfc_uhd_10bit";
|
|
time_fw = <0xaf>;
|
|
};
|
|
};
|
|
|
|
mfc_encoder_qos_table {
|
|
|
|
mfc_e_qos_variant_0 {
|
|
thrd_mb = <0x00>;
|
|
freq_mfc = <0x20788>;
|
|
freq_int = <0x20788>;
|
|
freq_mif = <0x66c88>;
|
|
bts_scen = "default";
|
|
time_fw = <0x4d6>;
|
|
};
|
|
|
|
mfc_e_qos_variant_1 {
|
|
thrd_mb = <0x85727>;
|
|
freq_mfc = <0x412f8>;
|
|
freq_int = <0x20788>;
|
|
freq_mif = <0x854d0>;
|
|
bts_scen = "default";
|
|
time_fw = <0x34a>;
|
|
};
|
|
|
|
mfc_e_qos_variant_2 {
|
|
thrd_mb = <0x11cf37>;
|
|
freq_mfc = <0x510e0>;
|
|
freq_int = <0x30d40>;
|
|
freq_mif = <0xa50a0>;
|
|
bts_scen = "default";
|
|
time_fw = <0x29b>;
|
|
};
|
|
|
|
mfc_e_qos_variant_3 {
|
|
thrd_mb = <0x1c5f35>;
|
|
freq_mfc = <0x510e0>;
|
|
freq_int = <0x30d40>;
|
|
freq_mif = <0xce4c8>;
|
|
bts_scen = "default";
|
|
time_fw = <0x242>;
|
|
};
|
|
|
|
mfc_e_qos_variant_4 {
|
|
thrd_mb = <0x1fb6e1>;
|
|
freq_mfc = <0x82208>;
|
|
freq_int = <0x61a80>;
|
|
freq_mif = <0xce4c8>;
|
|
bts_scen = "default";
|
|
time_fw = <0x1d7>;
|
|
};
|
|
|
|
mfc_e_qos_variant_5 {
|
|
thrd_mb = <0x26f671>;
|
|
freq_mfc = <0x72420>;
|
|
freq_int = <0x510e0>;
|
|
freq_mif = <0x177bb8>;
|
|
bts_scen = "mfc_uhd";
|
|
time_fw = <0x167>;
|
|
};
|
|
|
|
mfc_e_qos_variant_6 {
|
|
thrd_mb = <0x3075be>;
|
|
freq_mfc = <0xa1dd8>;
|
|
freq_int = <0xa1dd8>;
|
|
freq_mif = <0x1a2f20>;
|
|
bts_scen = "default";
|
|
time_fw = <0x11f>;
|
|
};
|
|
};
|
|
|
|
mfc_perf_boost_table {
|
|
num_cluster = <0x03>;
|
|
freq_cluster = <0x1a94b0 0x1cf610 0x163780>;
|
|
freq_mfc = <0xa2990>;
|
|
freq_int = <0x825f0>;
|
|
freq_mif = <0x29a810>;
|
|
bts_scen = "mfc_uhd_10bit";
|
|
};
|
|
};
|
|
|
|
MFC-1 {
|
|
compatible = "samsung,exynos-mfc-core";
|
|
id = <0x01>;
|
|
reg = <0x00 0x188d0000 0x10000>;
|
|
interrupts = <0x00 0x24d 0x04>;
|
|
clock-names = "aclk_mfc";
|
|
clocks = <0x19 0xa28>;
|
|
iommus = <0x15a 0x15b>;
|
|
samsung,iommu-group = <0x15c>;
|
|
samsung,iommu-reserved-map = <0x00 0x10100000 0x100000>;
|
|
samsung,tzmp;
|
|
samsung,imgloader-s2mpu-support;
|
|
ip_ver = <0x1600010d>;
|
|
share_sysmmu = <0x00>;
|
|
axid_mask = <0xffff>;
|
|
mfc_fault_num = <0x00>;
|
|
trans_info_offset = <0x1004>;
|
|
llc = <0x01>;
|
|
need_llc_flush = <0x00>;
|
|
num_default_qos_steps = <0x0a>;
|
|
num_encoder_qos_steps = <0x07>;
|
|
max_mb = <0x511b61>;
|
|
max_hw_mb = <0x3b5380>;
|
|
mfc_freq_control = <0x01>;
|
|
mo_control = <0x01>;
|
|
bw_control = <0x01>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
phandle = <0x325>;
|
|
|
|
iommu {
|
|
reg = <0x00 0x18870000 0x9000 0x00 0x188a0000 0x9000>;
|
|
};
|
|
|
|
mfc_default_qos_table {
|
|
|
|
mfc_d_qos_variant_0 {
|
|
thrd_mb = <0x00>;
|
|
freq_mfc = <0x20788>;
|
|
freq_int = <0x20788>;
|
|
freq_mif = <0x66c88>;
|
|
bts_scen = "default";
|
|
time_fw = <0x4d6>;
|
|
};
|
|
|
|
mfc_d_qos_variant_1 {
|
|
thrd_mb = <0x85727>;
|
|
freq_mfc = <0x39210>;
|
|
freq_int = <0x20788>;
|
|
freq_mif = <0x854d0>;
|
|
bts_scen = "default";
|
|
time_fw = <0x34a>;
|
|
};
|
|
|
|
mfc_d_qos_variant_2 {
|
|
thrd_mb = <0x11cf37>;
|
|
freq_mfc = <0x510e0>;
|
|
freq_int = <0x30d40>;
|
|
freq_mif = <0xa50a0>;
|
|
bts_scen = "default";
|
|
time_fw = <0x29b>;
|
|
};
|
|
|
|
mfc_d_qos_variant_3 {
|
|
thrd_mb = <0x1c5f35>;
|
|
freq_mfc = <0x510e0>;
|
|
freq_int = <0x30d40>;
|
|
freq_mif = <0xce4c8>;
|
|
bts_scen = "default";
|
|
time_fw = <0x242>;
|
|
};
|
|
|
|
mfc_d_qos_variant_4 {
|
|
thrd_mb = <0x1fb6e1>;
|
|
freq_mfc = <0x72420>;
|
|
freq_int = <0x30d40>;
|
|
freq_mif = <0xf78f0>;
|
|
bts_scen = "default";
|
|
time_fw = <0x1e3>;
|
|
};
|
|
|
|
mfc_d_qos_variant_5 {
|
|
thrd_mb = <0x271c0a>;
|
|
freq_mfc = <0x82208>;
|
|
freq_int = <0x510e0>;
|
|
freq_mif = <0x14a140>;
|
|
bts_scen = "default";
|
|
time_fw = <0x16a>;
|
|
};
|
|
|
|
mfc_d_qos_variant_6 {
|
|
thrd_mb = <0x306d8d>;
|
|
freq_mfc = <0xa1dd8>;
|
|
freq_int = <0x61a80>;
|
|
freq_mif = <0x14a140>;
|
|
bts_scen = "default";
|
|
time_fw = <0x132>;
|
|
};
|
|
|
|
mfc_d_qos_variant_7 {
|
|
thrd_mb = <0x38b5b1>;
|
|
freq_mfc = <0xb5e28>;
|
|
freq_int = <0x82208>;
|
|
freq_mif = <0x177bb8>;
|
|
bts_scen = "default";
|
|
time_fw = <0x10b>;
|
|
};
|
|
|
|
mfc_d_qos_variant_8 {
|
|
thrd_mb = <0x41570e>;
|
|
freq_mfc = <0xb5e28>;
|
|
freq_int = <0xa1dd8>;
|
|
freq_mif = <0x1ef1e0>;
|
|
bts_scen = "default";
|
|
time_fw = <0xeb>;
|
|
};
|
|
|
|
mfc_d_qos_variant_9 {
|
|
thrd_mb = <0x4a180a>;
|
|
freq_mfc = "\0\f5";
|
|
freq_int = "\0\f5";
|
|
freq_mif = <0x3066a0>;
|
|
bts_scen = "mfc_8k_dec30";
|
|
time_fw = <0xaf>;
|
|
};
|
|
};
|
|
|
|
mfc_encoder_qos_table {
|
|
|
|
mfc_e_qos_variant_0 {
|
|
thrd_mb = <0x00>;
|
|
freq_mfc = <0x20788>;
|
|
freq_int = <0x20788>;
|
|
freq_mif = <0x66c88>;
|
|
bts_scen = "default";
|
|
time_fw = <0x4d6>;
|
|
};
|
|
|
|
mfc_e_qos_variant_1 {
|
|
thrd_mb = <0x85727>;
|
|
freq_mfc = <0x412f8>;
|
|
freq_int = <0x20788>;
|
|
freq_mif = <0x854d0>;
|
|
bts_scen = "default";
|
|
time_fw = <0x34a>;
|
|
};
|
|
|
|
mfc_e_qos_variant_2 {
|
|
thrd_mb = <0x11cf37>;
|
|
freq_mfc = <0x510e0>;
|
|
freq_int = <0x30d40>;
|
|
freq_mif = <0xa50a0>;
|
|
bts_scen = "default";
|
|
time_fw = <0x29b>;
|
|
};
|
|
|
|
mfc_e_qos_variant_3 {
|
|
thrd_mb = <0x1c5f35>;
|
|
freq_mfc = <0x510e0>;
|
|
freq_int = <0x30d40>;
|
|
freq_mif = <0xce4c8>;
|
|
bts_scen = "default";
|
|
time_fw = <0x242>;
|
|
};
|
|
|
|
mfc_e_qos_variant_4 {
|
|
thrd_mb = <0x1fb6e1>;
|
|
freq_mfc = <0x82208>;
|
|
freq_int = <0x61a80>;
|
|
freq_mif = <0xce4c8>;
|
|
bts_scen = "default";
|
|
time_fw = <0x1d7>;
|
|
};
|
|
|
|
mfc_e_qos_variant_5 {
|
|
thrd_mb = <0x26f671>;
|
|
freq_mfc = <0x72420>;
|
|
freq_int = <0x510e0>;
|
|
freq_mif = <0x177bb8>;
|
|
bts_scen = "mfc_uhd";
|
|
time_fw = <0x167>;
|
|
};
|
|
|
|
mfc_e_qos_variant_6 {
|
|
thrd_mb = <0x3075be>;
|
|
freq_mfc = <0xa1dd8>;
|
|
freq_int = <0xa1dd8>;
|
|
freq_mif = <0x1a2f20>;
|
|
bts_scen = "default";
|
|
time_fw = <0x11f>;
|
|
};
|
|
};
|
|
|
|
mfc_perf_boost_table {
|
|
num_cluster = <0x03>;
|
|
freq_cluster = <0x1a94b0 0x1cf610 0x163780>;
|
|
freq_mfc = <0xa2990>;
|
|
freq_int = <0x825f0>;
|
|
freq_mif = <0x29a810>;
|
|
bts_scen = "mfc_uhd_10bit";
|
|
};
|
|
};
|
|
};
|
|
|
|
smfc@18940000 {
|
|
compatible = "samsung,exynos8890-jpeg";
|
|
dma-coherent;
|
|
reg = <0x00 0x18940000 0x1000>;
|
|
interrupts = <0x00 0x20d 0x04>;
|
|
iommus = <0x15e>;
|
|
samsung,iommu-group = <0x15f>;
|
|
smfc,int_qos_minlock = "\0\f5";
|
|
phandle = <0x326>;
|
|
};
|
|
|
|
smfc@18950000 {
|
|
compatible = "samsung,exynos8890-jpeg";
|
|
dma-coherent;
|
|
reg = <0x00 0x18950000 0x1000>;
|
|
interrupts = <0x00 0x20e 0x04>;
|
|
iommus = <0x15e>;
|
|
samsung,iommu-group = <0x15f>;
|
|
smfc,int_qos_minlock = "\0\f5";
|
|
phandle = <0x327>;
|
|
};
|
|
|
|
scaler@18960000 {
|
|
compatible = "samsung,exynos5-scaler";
|
|
reg = <0x00 0x18960000 0x3000>;
|
|
interrupts = <0x00 0x210 0x04>;
|
|
clocks = <0x19 0x514>;
|
|
clock-names = "gate";
|
|
itmon,master = "MSCL";
|
|
itmon,dest = "M2M";
|
|
dma-coherent;
|
|
iommus = <0x15e>;
|
|
samsung,iommu-group = <0x15f>;
|
|
samsung,tzmp;
|
|
#dma-address-cells = <0x01>;
|
|
#dma-size-cells = <0x01>;
|
|
dma-window = <0x00 0xe0000000>;
|
|
mscl_qos_table = <0x00 0xc3500 0xc3500 0x00 0xa1dd8 0xa1dd8 0x00 0x82208 0x87028 0x00 0x61a80 0x61a80 0x00 0x55730 0x55730 0x00 0x30d40 0x30d40 0x00 0x27100 0x27100>;
|
|
mscl_ppc_table = <0x0c 0x1f0 0x1d6 0x10 0x176 0x156 0x18 0x12f 0x120 0x20 0xbd 0xbc 0x64 0x1df 0x1b4>;
|
|
mscl_mif_ref = <0x854d0>;
|
|
mscl_bw_ref = <0x2e593c>;
|
|
#mscl-votf-address-cells = <0x01>;
|
|
#mscl-votf-size-cells = <0x01>;
|
|
mscl_votf_reg = <0x189e0000 0x10000>;
|
|
samsung,mscl-votf_targets = <0x160 0x1ad00000 0x10000 0x1ad20000 0x10000 0x160 0x1af00000 0x10000 0x1af20000 0x10000>;
|
|
phandle = <0x328>;
|
|
};
|
|
|
|
jsqz@18980000 {
|
|
compatible = "samsung,exynos-jsqz";
|
|
reg = <0x00 0x18980000 0x200>;
|
|
interrupts = <0x00 0x20f 0x04>;
|
|
iommus = <0x15e>;
|
|
samsung,iommu-group = <0x15f>;
|
|
jsqz,int_qos_minlock = <0x82208>;
|
|
phandle = <0x329>;
|
|
};
|
|
|
|
mcfrc@0x18A50000 {
|
|
compatible = "samsung,exynos-mcfrc";
|
|
reg = <0x00 0x18a50000 0x1000>;
|
|
interrupts = <0x00 0x1cb 0x04 0x00 0x1ca 0x04>;
|
|
iommus = <0x15e>;
|
|
samsung,iommu-group = <0x15f>;
|
|
mcfrc,int_qos_minlock = <0xa1dd8>;
|
|
phandle = <0x32a>;
|
|
};
|
|
|
|
tsmux@186E0000 {
|
|
compatible = "samsung,exynos-tsmux";
|
|
reg = <0x00 0x186e0000 0x1000>;
|
|
interrupts = <0x00 0x24c 0x04>;
|
|
iommus = <0x159>;
|
|
samsung,iommu-group = <0x15c>;
|
|
power-domains = <0x0b>;
|
|
phandle = <0x32b>;
|
|
};
|
|
|
|
repeater@0 {
|
|
compatible = "samsung,exynos-repeater";
|
|
power-domains = <0x0b>;
|
|
phandle = <0x32c>;
|
|
};
|
|
|
|
xperf {
|
|
compatible = "samsung,exynos-perf";
|
|
status = "ok";
|
|
cal-id-mif = <0xb040000>;
|
|
cal-id-g3d = <0xb04000d>;
|
|
cal-id-cpucl0 = <0xb040002>;
|
|
cal-id-cpucl1 = <0xb040003>;
|
|
cal-id-cpucl2 = <0xb040004>;
|
|
power-coeff = <0x178 0x26c 0x3b8>;
|
|
|
|
pago {
|
|
gov-ms = <0xc8>;
|
|
gov-run = <0x00>;
|
|
power-limit = <0x1f40 0x1f40 0x1f40 0x1f40>;
|
|
multi-volt = <0x7d0 0x41a 0x41a>;
|
|
batt-tz-names = "battery";
|
|
batt-temp-thd = <0x4e20>;
|
|
};
|
|
|
|
gmc {
|
|
bind-cpu = <0x00>;
|
|
polling-ms = <0x3e8>;
|
|
cpu-tz-names = "LITTLE\0MID\0BIG";
|
|
gpu-tz-names = "G3D";
|
|
|
|
type0 {
|
|
set-timer = <0x00 0x03>;
|
|
throttle = <0x01>;
|
|
|
|
trigger {
|
|
gpu-fps = <0x50>;
|
|
gpu-freq = <0xdbba0>;
|
|
gpu-temp = <0x11170>;
|
|
cpu-temp = <0x11170 0x11170 0x11170>;
|
|
};
|
|
|
|
release {
|
|
gpu-fps = <0x14>;
|
|
gpu-temp = <0xd6d8>;
|
|
cpu-temp = <0xd6d8 0xd6d8 0xd6d8>;
|
|
};
|
|
};
|
|
|
|
type1 {
|
|
boost-cnt = <0x00>;
|
|
boost-step = <0x00>;
|
|
cpu-maxlock = <0x119400 0x177000 0x177000>;
|
|
fps-drop = <0x0a>;
|
|
|
|
trigger {
|
|
gpu-fps = <0x1e>;
|
|
gpu-freq = <0xdbba0>;
|
|
gpu-temp = <0xea60>;
|
|
cpu-temp = <0xea60 0xea60 0xea60>;
|
|
};
|
|
|
|
release {
|
|
gpu-fps = <0x0a>;
|
|
gpu-temp = <0xd6d8>;
|
|
cpu-temp = <0xd6d8 0xd6d8 0xd6d8>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
exynos_is@18440000 {
|
|
compatible = "samsung,exynos-is";
|
|
reg = <0x00 0x17140000 0x10000 0x00 0x17100000 0x10000 0x00 0x17110000 0x10000 0x00 0x17120000 0x10000 0x00 0x17130000 0x10000 0x00 0x18440000 0x10000 0x00 0x18450000 0x10000 0x00 0x18460000 0x10000 0x00 0x18470000 0x10000 0x00 0x17140000 0x10000 0x00 0x17630000 0x10000 0x00 0x17480000 0x10000 0x00 0x175b0000 0x10000 0x00 0x15e00000 0x10000 0x00 0x18040000 0x10000 0x00 0x15c40000 0x10000>;
|
|
interrupts = <0x00 0x136 0x04 0x00 0x137 0x04 0x00 0x138 0x04 0x00 0x139 0x04 0x00 0x13a 0x04 0x00 0x13b 0x04 0x00 0x13c 0x04 0x00 0x13d 0x04 0x00 0x206 0x04 0x00 0x52 0x04 0x00 0x53 0x04 0x00 0x55 0x04 0x00 0x56 0x04 0x00 0x1cc 0x04 0x00 0x1cd 0x04 0x00 0x301 0x04 0x00 0x302 0x04 0x00 0x233 0x04 0x00 0x234 0x04>;
|
|
pinctrl-names = "default\0release";
|
|
pinctrl-0;
|
|
pinctrl-1;
|
|
clocks = <0x19 0x898 0x19 0x899 0x19 0x89a 0x19 0x89b 0x19 0x89c 0x19 0x89d 0x19 0x89e 0x19 0x89f 0x19 0x8a2 0x19 0x8a3 0x19 0x8a4 0x19 0x8a5 0x19 0x8a6 0x19 0x8a7 0x19 0x8a8 0x19 0x8a9 0x19 0x64 0x19 0x190 0x19 0x191 0x19 0x192 0x19 0x193 0x19 0x194 0x19 0x195 0x19 0x196 0x19 0x65 0x19 0x66 0x19 0x67 0x19 0x68 0x19 0x69 0x19 0x4b0 0x19 0x578 0x19 0x960 0x19 0x579>;
|
|
clock-names = "GATE_DFTMUX_CMU_QCH_CIS_CLK0\0GATE_DFTMUX_CMU_QCH_CIS_CLK1\0GATE_DFTMUX_CMU_QCH_CIS_CLK2\0GATE_DFTMUX_CMU_QCH_CIS_CLK3\0GATE_DFTMUX_CMU_QCH_CIS_CLK4\0GATE_DFTMUX_CMU_QCH_CIS_CLK5\0GATE_DFTMUX_CMU_QCH_CIS_CLK6\0GATE_DFTMUX_CMU_QCH_CIS_CLK7\0DOUT_DIV_CLKCMU_CIS_CLK0\0DOUT_DIV_CLKCMU_CIS_CLK1\0DOUT_DIV_CLKCMU_CIS_CLK2\0DOUT_DIV_CLKCMU_CIS_CLK3\0DOUT_DIV_CLKCMU_CIS_CLK4\0DOUT_DIV_CLKCMU_CIS_CLK5\0DOUT_DIV_CLKCMU_CIS_CLK6\0DOUT_DIV_CLKCMU_CIS_CLK7\0GATE_CSIS_PDP_QCH_DMA\0GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS0\0GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS1\0GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS2\0GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS3\0GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS4\0GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS5\0GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS6\0GATE_CSIS_PDP_QCH_PDP\0GATE_LH_AST_SI_OTF0_CSISCSTAT_QCH\0GATE_LH_AST_SI_OTF1_CSISCSTAT_QCH\0GATE_LH_AST_SI_OTF2_CSISCSTAT_QCH\0GATE_LH_AST_SI_OTF3_CSISCSTAT_QCH\0GATE_LME_QCH_0\0GATE_MCFP_QCH\0GATE_YUVP_QCH\0GATE_MCSC_QCH";
|
|
status = "ok";
|
|
iommus = <0x161 0x162 0x163 0x164 0x165>;
|
|
samsung,iommu-group = <0x166>;
|
|
#cooling-cells = <0x02>;
|
|
ewf-index = <0x39>;
|
|
list-scen-bts = "camera_default\0camera_heavy";
|
|
num_of_3aa = <0x04>;
|
|
num_of_lme = <0x01>;
|
|
num_of_isp = <0x00>;
|
|
num_of_byrp = <0x01>;
|
|
num_of_rgbp = <0x01>;
|
|
num_of_mcsc = <0x01>;
|
|
num_of_vra = <0x00>;
|
|
num_of_clh = <0x00>;
|
|
num_of_ypp = <0x01>;
|
|
num_of_mcfp = <0x01>;
|
|
memory-region = <0xffffffff>;
|
|
samsung,tzmp;
|
|
phy_ldos = "AVDD_CSI_0P85\0AVDD_CSI_1P2";
|
|
phandle = <0x32d>;
|
|
|
|
is_qos {
|
|
|
|
CSIS {
|
|
typ = <0x00>;
|
|
lev = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08>;
|
|
frq = <0x2e9 0x297 0x215 0x1d4 0x190 0x14c 0x10b 0xa6 0x32>;
|
|
qos = <0xb5e28 0xa1dd8 0x82208 0x72420 0x61a80 0x510e0 0x412f8 0x28870 0xc350>;
|
|
otf;
|
|
};
|
|
|
|
CAM {
|
|
typ = <0x01>;
|
|
lev = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08>;
|
|
frq = <0x2e9 0x297 0x215 0x1d4 0x190 0x14c 0xea 0xa6 0x32>;
|
|
qos = <0xb5e28 0xa1dd8 0x82208 0x72420 0x61a80 0x510e0 0x39210 0x28870 0xc350>;
|
|
};
|
|
|
|
ISP {
|
|
typ = <0x02>;
|
|
lev = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08>;
|
|
frq = <0x2e9 0x297 0x215 0x1d4 0x190 0x14c 0xea 0xa6 0x32>;
|
|
qos = <0xb5e28 0xa1dd8 0x82208 0x72420 0x61a80 0x510e0 0x39210 0x28870 0xc350>;
|
|
};
|
|
|
|
INT_CAM {
|
|
typ = <0x03>;
|
|
lev = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08>;
|
|
frq = <0x2e9 0x297 0x215 0x1d4 0x190 0x14c 0xea 0xa6 0x32>;
|
|
qos = <0xb5e28 0xa1dd8 0x82208 0x72420 0x61a80 0x510e0 0x39210 0x28870 0xc350>;
|
|
};
|
|
|
|
MIF {
|
|
typ = <0x05>;
|
|
lev = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c>;
|
|
frq = <0xc64 0xaaa 0x9e7 0x8f0 0x7ec 0x6b3 0x603 0x548 0x3f6 0x34d 0x2a4 0x222 0x1a5>;
|
|
qos = <0x3066a0 0x29a810 0x26ae58 0x22e980 0x1ef1e0 0x1a2d2c 0x177bb8 0x14a140 0xf78f0 0xce4c8 0xa50a0 0x854d0 0x66c88>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gdc@17700000 {
|
|
compatible = "samsung,exynos-is-gdc";
|
|
reg = <0x00 0x17700000 0x10000>;
|
|
interrupts = <0x00 0x1c8 0x04 0x00 0x1c9 0x04>;
|
|
pinctrl-names = "default\0release";
|
|
pinctrl-0;
|
|
pinctrl-1;
|
|
clocks = <0x19 0x4b0>;
|
|
clock-names = "gate";
|
|
status = "okay";
|
|
iommus = <0x167>;
|
|
samsung,iommu-group = <0x168>;
|
|
#cooling-cells = <0x02>;
|
|
dma-coherent;
|
|
phandle = <0x32e>;
|
|
|
|
votf_axi {
|
|
votf_src_dest = <0x17710000 0x18700000>;
|
|
};
|
|
};
|
|
|
|
votf0 {
|
|
compatible = "samsung,exynos-camerapp-votf";
|
|
id = <0x00>;
|
|
iommus = <0x169 0x16a 0x16b 0x16c 0x16d 0x16e 0x16f>;
|
|
samsung,iommu-group = <0x170>;
|
|
status = "okay";
|
|
use_axi;
|
|
phandle = <0x32f>;
|
|
|
|
table0 {
|
|
|
|
byrp_wdma {
|
|
info = <0x174a0000 0x174a 0x01 0x00 0x00 0x03>;
|
|
};
|
|
|
|
byrp_rdma {
|
|
info = <0x174c0000 0x174c 0x02 0x00 0x01 0x03>;
|
|
};
|
|
|
|
rgbp_rdma {
|
|
info = <0x175c0000 0x175c 0x01 0x00 0x00 0x03>;
|
|
};
|
|
|
|
rgbp_wdma {
|
|
info = <0x175d0000 0x175d 0x03 0x00 0x00 0x03>;
|
|
};
|
|
|
|
mcsc_rdma {
|
|
info = <0x15c60000 0x15c6 0x01 0x00 0x01 0x03>;
|
|
};
|
|
|
|
mcsc_wdma {
|
|
info = <0x15c50000 0x15c5 0x10 0x00 0x00 0x03>;
|
|
};
|
|
};
|
|
|
|
service {
|
|
|
|
m0s4 {
|
|
info = <0x00 0x00 0x100 0x1c 0x2c>;
|
|
};
|
|
|
|
m2s2 {
|
|
info = <0x01 0x100 0x200 0x1c 0x2c>;
|
|
};
|
|
|
|
m3s1 {
|
|
info = <0x02 0x100 0x200 0x1c 0x2c>;
|
|
};
|
|
|
|
m16s16 {
|
|
info = <0x03 0x100 0x300 0x1c 0x2c>;
|
|
};
|
|
};
|
|
};
|
|
|
|
votf1 {
|
|
compatible = "samsung,exynos-camerapp-votf";
|
|
id = <0x01>;
|
|
iommus = <0x161 0x162 0x163 0x164 0x165>;
|
|
samsung,iommu-group = <0x166>;
|
|
status = "okay";
|
|
use_axi;
|
|
phandle = <0x330>;
|
|
|
|
table0 {
|
|
|
|
csis_wdma0 {
|
|
info = <0x17380000 0x1738 0x10 0x00 0x00 0x03>;
|
|
};
|
|
|
|
csis_wdma1 {
|
|
info = <0x17390000 0x1739 0x04 0x00 0x00 0x03>;
|
|
};
|
|
|
|
pdp_rdma {
|
|
info = <0x173a0000 0x173a 0x01 0x00 0x01 0x03>;
|
|
};
|
|
|
|
byrp_rdma {
|
|
info = <0x174c0000 0x174c 0x02 0x00 0x01 0x03>;
|
|
};
|
|
|
|
cstat_wdma {
|
|
info = <0x18510000 0x1851 0x0c 0x00 0x00 0x03>;
|
|
};
|
|
|
|
cstat_rdma {
|
|
info = <0x18500000 0x1850 0x04 0x00 0x01 0x03>;
|
|
};
|
|
};
|
|
|
|
service {
|
|
|
|
m0s4 {
|
|
info = <0x00 0x00 0x100 0x1c 0x2c>;
|
|
};
|
|
|
|
m2s2 {
|
|
info = <0x01 0x100 0x200 0x1c 0x2c>;
|
|
};
|
|
|
|
m3s1 {
|
|
info = <0x02 0x100 0x200 0x1c 0x2c>;
|
|
};
|
|
|
|
m16s16 {
|
|
info = <0x03 0x100 0x300 0x1c 0x2c>;
|
|
};
|
|
};
|
|
};
|
|
|
|
votf2 {
|
|
compatible = "samsung,exynos-camerapp-votf";
|
|
id = <0x02>;
|
|
iommus = <0x167>;
|
|
samsung,iommu-group = <0x168>;
|
|
status = "okay";
|
|
use_axi;
|
|
phandle = <0x331>;
|
|
|
|
table0 {
|
|
|
|
gdc_wdma {
|
|
info = <0x17710000 0x1771 0x02 0x00 0x00 0x03>;
|
|
};
|
|
};
|
|
|
|
service {
|
|
|
|
m0s4 {
|
|
info = <0x00 0x00 0x100 0x1c 0x2c>;
|
|
};
|
|
|
|
m2s2 {
|
|
info = <0x01 0x100 0x200 0x1c 0x2c>;
|
|
};
|
|
|
|
m3s1 {
|
|
info = <0x02 0x100 0x200 0x1c 0x2c>;
|
|
};
|
|
|
|
m16s16 {
|
|
info = <0x03 0x100 0x300 0x1c 0x2c>;
|
|
};
|
|
};
|
|
};
|
|
|
|
is_iommu_group_module {
|
|
compatible = "samsung,exynos-is-iommu-group-module";
|
|
groups = <0x171 0x172 0x173 0x174>;
|
|
phandle = <0x332>;
|
|
};
|
|
|
|
is_iommu_group0 {
|
|
compatible = "samsung,exynos-is-iommu-group";
|
|
iommus = <0x161 0x162 0x163 0x164 0x165>;
|
|
samsung,iommu-group = <0x166>;
|
|
phandle = <0x171>;
|
|
};
|
|
|
|
is_iommu_group1 {
|
|
compatible = "samsung,exynos-is-iommu-group";
|
|
iommus = <0x167>;
|
|
samsung,iommu-group = <0x168>;
|
|
phandle = <0x172>;
|
|
};
|
|
|
|
is_iommu_group2 {
|
|
compatible = "samsung,exynos-is-iommu-group";
|
|
iommus = <0x169 0x16a 0x16b 0x16c 0x16d 0x16e 0x16f>;
|
|
samsung,iommu-group = <0x170>;
|
|
phandle = <0x173>;
|
|
};
|
|
|
|
is_iommu_group3 {
|
|
compatible = "samsung,exynos-is-iommu-group";
|
|
iommus = <0x175 0x176>;
|
|
samsung,iommu-group = <0x177>;
|
|
phandle = <0x174>;
|
|
};
|
|
|
|
camif-wdma-module@17140000 {
|
|
compatible = "samsung,camif-wdma-module";
|
|
reg = <0x00 0x17140000 0x300>;
|
|
reg-names = "ctl";
|
|
channels = <0x178 0x179 0x17a 0x17b 0x17c>;
|
|
samsung,quirks = "has test pattern gen";
|
|
phandle = <0x17d>;
|
|
};
|
|
|
|
camif-wdma@17141000 {
|
|
compatible = "samsung,camif-wdma";
|
|
reg = <0x00 0x17020520 0x04 0x00 0x17141400 0x100 0x00 0x17141000 0x100 0x00 0x17141100 0x100 0x00 0x17141200 0x100 0x00 0x17141300 0x100>;
|
|
reg-names = "mux\0ctl\0vc0\0vc1\0vc2\0vc3";
|
|
interrupts = <0x00 0x111 0x04>;
|
|
interrupt-names = "dma";
|
|
module = <0x17d>;
|
|
phandle = <0x178>;
|
|
};
|
|
|
|
camif-wdma@17142000 {
|
|
compatible = "samsung,camif-wdma";
|
|
reg = <0x00 0x17020524 0x04 0x00 0x17142400 0x100 0x00 0x17142000 0x100 0x00 0x17142100 0x100 0x00 0x17142200 0x100 0x00 0x17142300 0x100>;
|
|
reg-names = "mux\0ctl\0vc0\0vc1\0vc2\0vc3";
|
|
interrupts = <0x00 0x112 0x04>;
|
|
interrupt-names = "dma";
|
|
module = <0x17d>;
|
|
phandle = <0x179>;
|
|
};
|
|
|
|
camif-wdma@17143000 {
|
|
compatible = "samsung,camif-wdma";
|
|
reg = <0x00 0x17020528 0x04 0x00 0x17143400 0x100 0x00 0x17143000 0x100 0x00 0x17143100 0x100 0x00 0x17143200 0x100 0x00 0x17143300 0x100>;
|
|
reg-names = "mux\0ctl\0vc0\0vc1\0vc2\0vc3";
|
|
interrupts = <0x00 0x113 0x04>;
|
|
interrupt-names = "dma";
|
|
module = <0x17d>;
|
|
phandle = <0x17a>;
|
|
};
|
|
|
|
camif-wdma@17144000 {
|
|
compatible = "samsung,camif-wdma";
|
|
reg = <0x00 0x1702052c 0x04 0x00 0x17144400 0x100 0x00 0x17144000 0x100 0x00 0x17144100 0x100 0x00 0x17144200 0x100 0x00 0x17144300 0x100>;
|
|
reg-names = "mux\0ctl\0vc0\0vc1\0vc2\0vc3";
|
|
interrupts = <0x00 0x114 0x04>;
|
|
interrupt-names = "dma";
|
|
module = <0x17d>;
|
|
phandle = <0x17b>;
|
|
};
|
|
|
|
camif-wdma@17145000 {
|
|
compatible = "samsung,camif-wdma";
|
|
reg = <0x00 0x17020490 0x04 0x00 0x17145400 0x100 0x00 0x17145000 0x100 0x00 0x17145100 0x100 0x00 0x17145200 0x100 0x00 0x17145300 0x100>;
|
|
reg-names = "mux\0ctl\0vc0\0vc1\0vc2\0vc3";
|
|
interrupts = <0x00 0x115 0x04>;
|
|
interrupt-names = "dma";
|
|
module = <0x17d>;
|
|
phandle = <0x17c>;
|
|
};
|
|
|
|
camif-mcb@17151000 {
|
|
compatible = "samsung,camif-mcb";
|
|
reg = <0x00 0x17151000 0x1000>;
|
|
phandle = <0x333>;
|
|
};
|
|
|
|
camif-ebuf@17152000 {
|
|
compatible = "samsung,camif-ebuf";
|
|
reg = <0x00 0x17152000 0x1000>;
|
|
interrupts = <0x00 0x184 0x04>;
|
|
num_of_ebuf = <0x04>;
|
|
status = "disabled";
|
|
phandle = <0x334>;
|
|
};
|
|
|
|
camif-bns@17153000 {
|
|
compatible = "samsung,camif-bns";
|
|
reg = <0x00 0x17153000 0x100 0x00 0x17020494 0x04>;
|
|
reg-names = "ctl\0mux";
|
|
mux = <0x00 0x01 0x02 0x03>;
|
|
dma_mux = <0x24>;
|
|
phandle = <0x335>;
|
|
};
|
|
|
|
system-controller@17020500 {
|
|
compatible = "samsung,exynos9925-csis\0syscon";
|
|
reg = <0x00 0x17020500 0x04>;
|
|
phandle = <0x17e>;
|
|
};
|
|
|
|
dcphy_m0s4s4s4s4s4s4_s22_csi0@170F1300 {
|
|
compatible = "samsung,mipi-phy-m0s4s4s4s4s4s4_s22";
|
|
samsung,pmu-syscon = <0xd8>;
|
|
power-gating = <0xa88>;
|
|
samsung,reset-sysreg = <0x17e>;
|
|
reset = <0x00>;
|
|
reg = <0x00 0x170f1300 0x500>;
|
|
owner = <0x01>;
|
|
#phy-cells = <0x01>;
|
|
phandle = <0x17f>;
|
|
};
|
|
|
|
dcphy_m0s4s4s4s4s4s4_s22_csi1@170F1B00 {
|
|
compatible = "samsung,mipi-phy-m0s4s4s4s4s4s4_s22";
|
|
samsung,pmu-syscon = <0xd8>;
|
|
power-gating = <0xa8c>;
|
|
samsung,reset-sysreg = <0x17e>;
|
|
reset = <0x01>;
|
|
reg = <0x00 0x170f1b00 0x500>;
|
|
owner = <0x01>;
|
|
#phy-cells = <0x01>;
|
|
phandle = <0x181>;
|
|
};
|
|
|
|
dcphy_m0s4s4s4s4s4s4_s22_csi2@170F2300 {
|
|
compatible = "samsung,mipi-phy-m0s4s4s4s4s4s4_s22";
|
|
samsung,pmu-syscon = <0xd8>;
|
|
power-gating = <0xa90>;
|
|
samsung,reset-sysreg = <0x17e>;
|
|
reset = <0x02>;
|
|
reg = <0x00 0x170f2300 0x500>;
|
|
owner = <0x01>;
|
|
#phy-cells = <0x01>;
|
|
phandle = <0x182>;
|
|
};
|
|
|
|
dcphy_m0s4s4s4s4s4s4_s22_csi3@170F2B00 {
|
|
compatible = "samsung,mipi-phy-m0s4s4s4s4s4s4_s22";
|
|
samsung,pmu-syscon = <0xd8>;
|
|
power-gating = <0xa94>;
|
|
samsung,reset-sysreg = <0x17e>;
|
|
reset = <0x03>;
|
|
reg = <0x00 0x170f2b00 0x500>;
|
|
owner = <0x01>;
|
|
#phy-cells = <0x01>;
|
|
phandle = <0x183>;
|
|
};
|
|
|
|
dphy_m0s4s4s4s4s4s4_s22_csi4@170F3300 {
|
|
compatible = "samsung,mipi-phy-m0s4s4s4s4s4s4_s22";
|
|
samsung,pmu-syscon = <0xd8>;
|
|
power-gating = <0xa98>;
|
|
samsung,reset-sysreg = <0x17e>;
|
|
reset = <0x07>;
|
|
reg = <0x00 0x170f3300 0x500>;
|
|
owner = <0x01>;
|
|
#phy-cells = <0x01>;
|
|
phandle = <0x184>;
|
|
};
|
|
|
|
dphy_m0s4s4s4s4s4s4_s22_csi5@170F3B00 {
|
|
compatible = "samsung,mipi-phy-m0s4s4s4s4s4s4_s22";
|
|
samsung,pmu-syscon = <0xd8>;
|
|
power-gating = <0xa9c>;
|
|
samsung,reset-sysreg = <0x17e>;
|
|
reset = <0x04>;
|
|
reg = <0x00 0x170f3b00 0x500>;
|
|
owner = <0x01>;
|
|
#phy-cells = <0x01>;
|
|
phandle = <0x185>;
|
|
};
|
|
|
|
dphy_m0s4s4s4s4s4s4_s22_csi5@170F3A00 {
|
|
compatible = "samsung,mipi-phy-m0s4s4s4s4s4s4_s22";
|
|
samsung,pmu-syscon = <0xd8>;
|
|
power-gating = <0xaa0>;
|
|
samsung,reset-sysreg = <0x17e>;
|
|
reset = <0x05>;
|
|
reg = <0x00 0x170f3a00 0x100>;
|
|
owner = <0x01>;
|
|
#phy-cells = <0x01>;
|
|
phandle = <0x336>;
|
|
};
|
|
|
|
is_sensor0@17030000 {
|
|
compatible = "samsung,exynos-is-sensor";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
reg = <0x00 0x17030000 0x1000 0x00 0x170f0000 0x10000 0x00 0x17150050 0x10>;
|
|
reg-names = "csi\0phy\0fro";
|
|
interrupts = <0x00 0x10a 0x04>;
|
|
interrupt-names = "csi";
|
|
phys = <0x17f 0x00>;
|
|
phy-names = "csis_dphy";
|
|
phy_setfile = <0x180>;
|
|
iommus = <0x161 0x162>;
|
|
samsung,iommu-group = <0x166>;
|
|
phandle = <0x337>;
|
|
};
|
|
|
|
is_sensor1@17040000 {
|
|
compatible = "samsung,exynos-is-sensor";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
reg = <0x00 0x17040000 0x1000 0x00 0x170f0000 0x10000 0x00 0x17150050 0x10>;
|
|
reg-names = "csi\0phy\0fro";
|
|
interrupts = <0x00 0x10b 0x04>;
|
|
interrupt-names = "csi";
|
|
phys = <0x181 0x00>;
|
|
phy-names = "csis_dphy";
|
|
phy_setfile = <0x180>;
|
|
iommus = <0x161 0x162>;
|
|
samsung,iommu-group = <0x166>;
|
|
samsung,tzmp;
|
|
phandle = <0x338>;
|
|
};
|
|
|
|
is_sensor2@17050000 {
|
|
compatible = "samsung,exynos-is-sensor";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
reg = <0x00 0x17050000 0x1000 0x00 0x170f0000 0x10000 0x00 0x17150050 0x10>;
|
|
reg-names = "csi\0phy\0fro";
|
|
interrupts = <0x00 0x10c 0x04>;
|
|
interrupt-names = "csi";
|
|
phys = <0x182 0x00>;
|
|
phy-names = "csis_dphy";
|
|
phy_setfile = <0x180>;
|
|
iommus = <0x161 0x162>;
|
|
samsung,iommu-group = <0x166>;
|
|
phandle = <0x339>;
|
|
};
|
|
|
|
is_sensor3@17060000 {
|
|
compatible = "samsung,exynos-is-sensor";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
reg = <0x00 0x17060000 0x1000 0x00 0x170f0000 0x10000 0x00 0x17150050 0x10>;
|
|
reg-names = "csi\0phy\0fro";
|
|
interrupts = <0x00 0x10d 0x04>;
|
|
interrupt-names = "csi";
|
|
phys = <0x183 0x00>;
|
|
phy-names = "csis_dphy";
|
|
phy_setfile = <0x180>;
|
|
iommus = <0x161 0x162>;
|
|
samsung,iommu-group = <0x166>;
|
|
phandle = <0x33a>;
|
|
};
|
|
|
|
is_sensor4@17070000 {
|
|
compatible = "samsung,exynos-is-sensor";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
reg = <0x00 0x17070000 0x1000 0x00 0x170f0000 0x10000 0x00 0x17150050 0x10>;
|
|
reg-names = "csi\0phy\0fro";
|
|
interrupts = <0x00 0x10e 0x04>;
|
|
interrupt-names = "csi";
|
|
phys = <0x184 0x00>;
|
|
phy-names = "csis_dphy";
|
|
phy_setfile = <0x180>;
|
|
iommus = <0x161 0x162>;
|
|
samsung,iommu-group = <0x166>;
|
|
phandle = <0x33b>;
|
|
};
|
|
|
|
is_sensor5@17080000 {
|
|
compatible = "samsung,exynos-is-sensor";
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x01>;
|
|
reg = <0x00 0x17080000 0x1000 0x00 0x170f0000 0x10000 0x00 0x17150050 0x10>;
|
|
reg-names = "csi\0phy\0fro";
|
|
interrupts = <0x00 0x10f 0x04>;
|
|
interrupt-names = "csi";
|
|
phys = <0x185 0x00>;
|
|
phy-names = "csis_dphy";
|
|
phy_setfile = <0x180>;
|
|
iommus = <0x161 0x162>;
|
|
samsung,iommu-group = <0x166>;
|
|
phandle = <0x33c>;
|
|
};
|
|
|
|
lic-lut-origin {
|
|
lic_mode_default = <0x00>;
|
|
lic_14bit = <0x00>;
|
|
lic_dma_only = <0x00>;
|
|
phandle = <0x186>;
|
|
|
|
lic_scen0 {
|
|
mode = <0x00>;
|
|
param0 = <0x00>;
|
|
param1 = <0x00>;
|
|
param2 = <0x00>;
|
|
};
|
|
};
|
|
|
|
sensor-paf-pdp@17100000 {
|
|
compatible = "samsung,sensor-paf-pdp";
|
|
reg = <0x00 0x17100000 0x10000 0x00 0x17100000 0x10000 0x00 0x17020510 0x04 0x00 0x17020430 0x04 0x00 0x17020530 0x04>;
|
|
reg-names = "core\0common\0mux\0vc_mux\0en";
|
|
interrupts = <0x00 0x118 0x04 0x00 0x119 0x04>;
|
|
mux = <0x00 0x01 0x02 0x03 0x04 0x05 0x06>;
|
|
vc_mux = <0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x10003 0x10003 0x10003 0x10003 0x10003 0x10003 0x10003>;
|
|
en = <0x00 0x01 0x02 0x03 0x04 0x05 0x06>;
|
|
leader;
|
|
lic_lut = <0x186>;
|
|
phandle = <0x33d>;
|
|
};
|
|
|
|
sensor-paf-pdp@17110000 {
|
|
compatible = "samsung,sensor-paf-pdp";
|
|
reg = <0x00 0x17110000 0x10000 0x00 0x17100000 0x10000 0x00 0x17020514 0x04 0x00 0x17020434 0x04 0x00 0x17020534 0x04>;
|
|
reg-names = "core\0common\0mux\0vc_mux\0en";
|
|
interrupts = <0x00 0x11a 0x04 0x00 0x11b 0x04>;
|
|
mux = <0x00 0x01 0x02 0x03 0x04 0x05 0x06>;
|
|
vc_mux = <0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x10003 0x10003 0x10003 0x10003 0x10003 0x10003 0x10003>;
|
|
en = <0x00 0x01 0x02 0x03 0x04 0x05 0x06>;
|
|
leader;
|
|
lic_lut = <0x186>;
|
|
phandle = <0x33e>;
|
|
};
|
|
|
|
sensor-paf-pdp@17120000 {
|
|
compatible = "samsung,sensor-paf-pdp";
|
|
reg = <0x00 0x17120000 0x10000 0x00 0x17100000 0x10000 0x00 0x17020518 0x04 0x00 0x17020438 0x04 0x00 0x17020538 0x04>;
|
|
reg-names = "core\0common\0mux\0vc_mux\0en";
|
|
interrupts = <0x00 0x11c 0x04 0x00 0x11d 0x04>;
|
|
mux = <0x00 0x01 0x02 0x03 0x04 0x05 0x06>;
|
|
vc_mux = <0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x10003 0x10003 0x10003 0x10003 0x10003 0x10003 0x10003>;
|
|
en = <0x00 0x01 0x02 0x03 0x04 0x05 0x06>;
|
|
leader;
|
|
lic_lut = <0x186>;
|
|
phandle = <0x33f>;
|
|
};
|
|
|
|
sensor-paf-pdp@17130000 {
|
|
compatible = "samsung,sensor-paf-pdp";
|
|
reg = <0x00 0x17130000 0x10000 0x00 0x17100000 0x10000 0x00 0x1702051c 0x04 0x00 0x1702043c 0x04 0x00 0x1702053c 0x04>;
|
|
reg-names = "core\0common\0mux\0vc_mux\0en";
|
|
interrupts = <0x00 0x11e 0x04 0x00 0x11f 0x04>;
|
|
mux = <0x00 0x01 0x02 0x03 0x04 0x05 0x06>;
|
|
vc_mux = <0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x10003 0x10003 0x10003 0x10003 0x10003 0x10003 0x10003>;
|
|
en = <0x00 0x01 0x02 0x03 0x04 0x05 0x06>;
|
|
leader;
|
|
lic_lut = <0x186>;
|
|
phandle = <0x340>;
|
|
};
|
|
|
|
dphy-setfile@00 {
|
|
phandle = <0x180>;
|
|
|
|
comm {
|
|
0 = <0x1000 0x00 0x20 0x10 0x05 0x00>;
|
|
1 = <0x1004 0x00 0x20 0x110 0x05 0x00>;
|
|
2 = <0x1008 0x00 0x20 0x3223 0x05 0x00>;
|
|
3 = <0x1010 0x00 0x20 0x200 0x05 0x00>;
|
|
4 = <0x1114 0x00 0x20 0x500 0x05 0x00>;
|
|
5 = <0x1118 0x00 0x20 0x8e 0x05 0x00>;
|
|
6 = <0x111c 0x00 0x20 0x3d40 0x05 0x00>;
|
|
7 = <0x1120 0x00 0x20 0x1e00 0x05 0x00>;
|
|
8 = <0x1124 0x00 0x20 0x1300 0x05 0x00>;
|
|
9 = <0x04 0x00 0x20 0x3d40 0x00 0x00>;
|
|
10 = <0x08 0x00 0x20 0x04 0x00 0x00>;
|
|
11 = <0x0c 0x00 0x20 0xa0f0 0x00 0x00>;
|
|
12 = <0x10 0x00 0x20 0x02 0x00 0x00>;
|
|
13 = <0x14 0x00 0x20 0x8600 0x00 0x00>;
|
|
14 = <0x18 0x00 0x20 0x4000 0x00 0x00>;
|
|
15 = <0x30 0x00 0x20 0x309 0x00 0x00>;
|
|
16 = <0x40 0x00 0x20 0x01 0x00 0x00>;
|
|
17 = <0x00 0x00 0x20 0x01 0x00 0x00>;
|
|
};
|
|
|
|
lane {
|
|
0 = <0x04 0x00 0x20 0x3d40 0x00 0x04>;
|
|
1 = <0x08 0x00 0x20 0x04 0x00 0x04>;
|
|
2 = <0x0c 0x00 0x20 0xa0f0 0x00 0x04>;
|
|
3 = <0x10 0x00 0x20 0x02 0x00 0x04>;
|
|
4 = <0x10 0x08 0x02 0x00 0x04 0x04>;
|
|
5 = <0x14 0x00 0x20 0x8600 0x00 0x04>;
|
|
6 = <0x18 0x00 0x20 0x2000 0x00 0x04>;
|
|
7 = <0x18 0x00 0x20 0x4000 0x00 0x03>;
|
|
8 = <0x30 0x00 0x08 0x00 0x01 0x04>;
|
|
9 = <0x30 0x08 0x01 0x00 0x02 0x04>;
|
|
10 = <0x34 0x00 0x20 0x03 0x00 0x04>;
|
|
11 = <0x40 0x00 0x01 0x00 0x03 0x04>;
|
|
12 = <0x50 0x00 0x20 0x81a 0x00 0x04>;
|
|
13 = <0x00 0x00 0x20 0x01 0x00 0x04>;
|
|
};
|
|
};
|
|
|
|
cphy-setfile@00 {
|
|
phandle = <0x341>;
|
|
|
|
comm {
|
|
0 = <0x1000 0x00 0x20 0x10 0x05 0x00>;
|
|
1 = <0x1004 0x00 0x20 0x110 0x05 0x00>;
|
|
2 = <0x1008 0x00 0x20 0x3223 0x05 0x00>;
|
|
3 = <0x1010 0x00 0x20 0x240 0x05 0x00>;
|
|
4 = <0x1114 0x00 0x20 0x500 0x05 0x00>;
|
|
5 = <0x1118 0x00 0x20 0x10 0x05 0x00>;
|
|
6 = <0x111c 0x00 0x20 0x3d40 0x05 0x00>;
|
|
7 = <0x1120 0x00 0x20 0x1e00 0x05 0x00>;
|
|
8 = <0x1124 0x00 0x20 0x1300 0x05 0x00>;
|
|
};
|
|
|
|
lane {
|
|
0 = <0x04 0x00 0x20 0x3d40 0x00 0x03>;
|
|
1 = <0x08 0x00 0x20 0xf7 0x00 0x03>;
|
|
2 = <0x0c 0x00 0x20 0xff29 0x00 0x03>;
|
|
3 = <0x10 0x00 0x20 0x05 0x00 0x03>;
|
|
4 = <0x14 0x00 0x20 0x8600 0x00 0x03>;
|
|
5 = <0x18 0x00 0x20 0x4040 0x00 0x03>;
|
|
6 = <0x1c 0x00 0x20 0x2200 0x00 0x03>;
|
|
7 = <0x20 0x00 0x20 0xe08 0x00 0x03>;
|
|
8 = <0x24 0x00 0x20 0x40 0x00 0x03>;
|
|
9 = <0x30 0x00 0x08 0x00 0x01 0x03>;
|
|
10 = <0x30 0x08 0x01 0x00 0x02 0x03>;
|
|
11 = <0x34 0x00 0x20 0x34 0x00 0x03>;
|
|
12 = <0x5c 0x00 0x20 0x1000 0x00 0x03>;
|
|
13 = <0x64 0x00 0x20 0x1501 0x00 0x03>;
|
|
14 = <0x68 0x00 0x20 0x23 0x00 0x03>;
|
|
15 = <0x9c 0x00 0x20 0x80 0x00 0x03>;
|
|
16 = <0x00 0x00 0x20 0x01 0x00 0x03>;
|
|
};
|
|
};
|
|
|
|
cphy-univ-2la-setfile@00 {
|
|
phandle = <0x342>;
|
|
|
|
comm {
|
|
0 = <0x1000 0x00 0x20 0x10 0x05 0x00>;
|
|
1 = <0x1004 0x00 0x20 0x110 0x05 0x00>;
|
|
2 = <0x1008 0x00 0x20 0x3223 0x05 0x00>;
|
|
3 = <0x1010 0x00 0x20 0x240 0x05 0x00>;
|
|
4 = <0x1114 0x00 0x20 0x500 0x05 0x00>;
|
|
5 = <0x1118 0x00 0x20 0x10 0x05 0x00>;
|
|
6 = <0x111c 0x00 0x20 0x3d40 0x05 0x00>;
|
|
7 = <0x1120 0x00 0x20 0x1e00 0x05 0x00>;
|
|
8 = <0x1124 0x00 0x20 0x1300 0x05 0x00>;
|
|
};
|
|
|
|
lane {
|
|
0 = <0x04 0x00 0x20 0x3d40 0x00 0x03>;
|
|
1 = <0x08 0x00 0x20 0xf7 0x00 0x03>;
|
|
2 = <0x0c 0x00 0x20 0xff29 0x00 0x03>;
|
|
3 = <0x10 0x00 0x20 0x05 0x00 0x03>;
|
|
4 = <0x14 0x00 0x20 0x8600 0x00 0x03>;
|
|
5 = <0x18 0x00 0x20 0x4040 0x00 0x03>;
|
|
6 = <0x1c 0x00 0x20 0x2200 0x00 0x03>;
|
|
7 = <0x20 0x00 0x20 0xe08 0x00 0x03>;
|
|
8 = <0x24 0x00 0x20 0x40 0x00 0x03>;
|
|
9 = <0x30 0x00 0x08 0x00 0x01 0x03>;
|
|
10 = <0x30 0x08 0x01 0x00 0x02 0x03>;
|
|
11 = <0x34 0x00 0x20 0x34 0x00 0x03>;
|
|
12 = <0x5c 0x00 0x20 0x1000 0x00 0x03>;
|
|
13 = <0x64 0x00 0x20 0x1501 0x00 0x03>;
|
|
14 = <0x68 0x00 0x20 0x23 0x00 0x03>;
|
|
15 = <0x9c 0x00 0x20 0x80 0x00 0x03>;
|
|
16 = <0x00 0x00 0x20 0x01 0x00 0x03>;
|
|
};
|
|
};
|
|
|
|
npu_exynos {
|
|
compatible = "samsung,exynos-npu";
|
|
iommus = <0x187 0x188 0x189 0x18a 0x18b>;
|
|
samsung,iommu-group = <0x18c>;
|
|
interrupts = <0x00 0x14c 0x04 0x00 0x14d 0x04 0x00 0x14e 0x04 0x00 0x149 0x04>;
|
|
samsung,npusys-corenum = <0x03>;
|
|
samsung,npumem-address = <0x00 0x1a730000 0x10000 0x00 0x16000000 0x100000 0x00 0x16200000 0x400000 0x00 0x16300000 0x100000 0x00 0x16400000 0x100000 0x00 0x16500000 0x100000 0x00 0x16800000 0x100000 0x00 0x16b00000 0x100000 0x00 0x17c00000 0x100000 0x00 0x19000000 0x100000 0x00 0x19100000 0x100000 0x00 0x19200000 0x100000 0x00 0x19300000 0x100000 0x00 0x19800000 0x100000 0x00 0x19900000 0x100000 0x00 0x19a00000 0x100000 0x00 0x19b00000 0x100000 0x00 0x17f10000 0x10000 0x00 0x400d000 0x1000 0x00 0x400b000 0x1000 0x00 0x400c000 0x1000 0x50640000 0x10040100 0x1000 0x00 0x106f0000 0x1000 0x00 0x16220860 0x100 0x00 0x16220824 0x100 0x00 0x158637e0 0x10 0x00 0x19400000 0x300000 0x00 0x17dd0000 0x10000 0x00 0x31000000 0x200000 0x00 0x32000000 0x500000 0x00 0x33000000 0x500000 0x02 0x34000000 0x1000000 0x00 0x35800000 0x100000 0x00 0x36000000 0x200000 0x00 0x36500000 0x1000 0x00 0x36501000 0x7000 0x00 0x36508000 0x100000 0x00 0x40000000 0x40000000>;
|
|
samsung,npumem-names = "sfrcmutop\0SFR\0sfrdncclk\0SFR\0sfrdnc\0SFR\0sfrsdma\0SFR\0sfrgnpu0\0SFR\0sfrgnpu1\0SFR\0sfrdsp0\0SFR\0sfrsdmac\0SFR\0sfrnpus\0SFR\0sfrnpuc0\0SFR\0sfrnpuc1\0SFR\0sfrnpuc2\0SFR\0sfrnpuc3\0SFR\0sfrnpu0\0SFR\0sfrnpu1\0SFR\0sfrnpu2\0SFR\0sfrnpu3\0SFR\0sfrsnpus\0SFR\0sfrcoresight\0SFR\0sfrstm\0SFR\0sfrstm1\0SFR\0sfrmctg\0SFR\0sfrpwm\0SFR\0sfrmbox0\0SFR\0sfrmbox1\0SFR\0sfrpmu\0SFR\0idpsram\0SFR\0htunpus\0SFR\0fwmbox\0fwmbox\0fwunittest\0fwunittest\0ivp_pm\0dsp_ivp_pm.bin\0llc\0llc\0dl_out\0dl_out\0dsp_mem\0dsp_mem\0dhcp\0dhcp\0ivp_dm\0dsp_ivp_dm.bin\0fwlog\0fwlog\0CHUNK_IMB\0IMB";
|
|
samsung,npucmd-hwacgendnc-sfr = "sfrdnc\0sfrsdma\0sfrsdma\0sfrdncclk\0sfrdncclk\0sfrdncclk\0sfrdncclk\0sfrdncclk\0sfrdncclk\0sfrsdmac\0sfrsdma";
|
|
samsung,npucmd-hwacgendnc-data = <0x01 0x20008 0x00 0x01 0x00 0x01 0x08 0x00 0x01 0x00 0x01 0x80000 0x00 0x01 0x00 0x01 0x2040c 0xffffffff 0xffffffff 0x00 0x01 0x20410 0xffffffff 0xffffffff 0x00 0x01 0x20414 0xffffffff 0xffffffff 0x00 0x01 0x20418 0xffffffff 0xffffffff 0x00 0x01 0x2041c 0xffffffff 0xffffffff 0x00 0x01 0x20420 0xffffffff 0xffffffff 0x00 0x01 0x20104 0xffffffff 0xffffffff 0x00 0x01 0x08 0x80000000 0x80000000 0x00>;
|
|
samsung,npucmd-hwacgennpu-sfr = "sfrgnpu0\0sfrgnpu1\0sfrnpu0\0sfrnpu0\0sfrnpu1\0sfrnpu1";
|
|
samsung,npucmd-hwacgennpu-data = <0x01 0xf0608 0x00 0x03 0x00 0x01 0xf0608 0x00 0x03 0x00 0x01 0x20400 0xffffffff 0xffffffff 0x00 0x01 0x20404 0xffffffff 0xffffffff 0x00 0x01 0x20400 0xffffffff 0xffffffff 0x00 0x01 0x20404 0xffffffff 0xffffffff 0x00>;
|
|
samsung,npucmd-hwacgendsp-sfr = "sfrdsp0\0sfrdsp0";
|
|
samsung,npucmd-hwacgendsp-data = <0x01 0x20104 0xffffffff 0xffffffff 0x00 0x01 0x20420 0xffffffff 0xffffffff 0x00>;
|
|
samsung,npucmd-hwacgdisdnc-sfr = "sfrdnc\0sfrsdma\0sfrsdma\0sfrdncclk\0sfrdncclk\0sfrdncclk\0sfrdncclk\0sfrdncclk\0sfrdncclk\0sfrsdmac\0sfrsdma";
|
|
samsung,npucmd-hwacgdisdnc-data = <0x01 0x20008 0x01 0x01 0x00 0x01 0x08 0x01 0x01 0x00 0x01 0x80000 0x01 0x01 0x00 0x01 0x2040c 0x00 0xffffffff 0x00 0x01 0x20410 0x00 0xffffffff 0x00 0x01 0x20414 0x00 0xffffffff 0x00 0x01 0x20418 0x00 0xffffffff 0x00 0x01 0x2041c 0x00 0xffffffff 0x00 0x01 0x20420 0x00 0xffffffff 0x00 0x01 0x20104 0x00 0xffffffff 0x00 0x01 0x08 0x00 0x80000000 0x00>;
|
|
samsung,npucmd-hwacgdisnpu-sfr = "sfrgnpu0\0sfrgnpu1\0sfrnpu0\0sfrnpu0\0sfrnpu1\0sfrnpu1";
|
|
samsung,npucmd-hwacgdisnpu-data = <0x01 0xf0608 0x03 0x03 0x00 0x01 0xf0608 0x03 0x03 0x00 0x01 0x20400 0x00 0xffffffff 0x00 0x01 0x20404 0x00 0xffffffff 0x00 0x01 0x20400 0x00 0xffffffff 0x00 0x01 0x20404 0x00 0xffffffff 0x00>;
|
|
samsung,npucmd-hwacgdisdsp-sfr = "sfrdsp0\0sfrdsp0";
|
|
samsung,npucmd-hwacgdisdsp-data = <0x01 0x20104 0x00 0xffffffff 0x00 0x01 0x20420 0x00 0xffffffff 0x00>;
|
|
samsung,npucmd-cpuon-sfr = "sfrdnc\0sfrdnc\0sfrdnc\0sfrdnc\0sfrdnc\0sfrdnc";
|
|
samsung,npucmd-cpuon-data = <0x01 0xe011c 0x00 0xffffffff 0x00 0x01 0xe0000 0x01 0xffffffff 0x00 0x03 0xe0004 0x01 0xffffffff 0x00 0x01 0xe0008 0x30000000 0xffffffff 0x00 0x03 0xe000c 0x30000000 0xffffffff 0x00 0x03 0xe0040 0x03 0xffffffff 0x00>;
|
|
samsung,npucmd-cpuoff-sfr = "sfrdnc";
|
|
samsung,npucmd-cpuoff-data = <0x03 0xe0040 0x00 0xffffffff 0x00>;
|
|
samsung,npucmd-cpupc-sfr = "sfrdnc\0sfrdnc";
|
|
samsung,npucmd-cpupc-data = <0x00 0xe00cc 0x00 0xffffffff 0x00 0x00 0xe00d0 0x00 0xffffffff 0x00>;
|
|
samsung,npucmd-enablestm-sfr = "sfrdnc\0sfrsdma\0sfrgnpu0\0sfrgnpu1\0sfrcoresight\0sfrcoresight";
|
|
samsung,npucmd-enablestm-data = <0x01 0x20018 0x01 0x01 0x00 0x01 0xf800 0x80000000 0x80000000 0x00 0x01 0xf0514 0x01 0x01 0x00 0x01 0xf0514 0x01 0x01 0x00 0x01 0x34 0x01 0x01 0x00 0x01 0x2c 0x01 0x01 0x00>;
|
|
samsung,npucmd-disablestm-sfr = "sfrcoresight\0sfrcoresight\0sfrgnpu0\0sfrgnpu1\0sfrsdma\0sfrdnc";
|
|
samsung,npucmd-disablestm-data = <0x01 0x2c 0x00 0x01 0x00 0x01 0x34 0x00 0x01 0x00 0x01 0xf0514 0x00 0x01 0x00 0x01 0xf0514 0x00 0x01 0x00 0x01 0xf800 0x00 0x80000000 0x00 0x01 0x20018 0x00 0x01 0x00>;
|
|
samsung,npucmd-enstmdsp-sfr = "sfrdnc\0sfrsdma\0sfrcoresight\0sfrcoresight";
|
|
samsung,npucmd-enstmdsp-data = <0x01 0x20018 0x01 0x01 0x00 0x01 0xf800 0x80000000 0x80000000 0x00 0x01 0x34 0x01 0x01 0x00 0x01 0x2c 0x01 0x01 0x00>;
|
|
samsung,npucmd-disstmdnc-sfr = "sfrcoresight\0sfrcoresight\0sfrsdma\0sfrdnc";
|
|
samsung,npucmd-disstmdnc-data = <0x01 0x2c 0x00 0x01 0x00 0x01 0x34 0x00 0x01 0x00 0x01 0xf800 0x00 0x80000000 0x00 0x01 0x20018 0x00 0x01 0x00>;
|
|
samsung,npucmd-enstmnpu-sfr = "sfrdnc\0sfrsdma\0sfrgnpu0\0sfrgnpu1\0sfrcoresight\0sfrcoresight";
|
|
samsung,npucmd-enstmnpu-data = <0x01 0x20018 0x01 0x01 0x00 0x01 0xf800 0x80000000 0x80000000 0x00 0x01 0xf0514 0x01 0x01 0x00 0x01 0xf0514 0x01 0x01 0x00 0x01 0x34 0x01 0x01 0x00 0x01 0x2c 0x01 0x01 0x00>;
|
|
samsung,npucmd-disstmnpu-sfr = "sfrgnpu0\0sfrgnpu1";
|
|
samsung,npucmd-disstmnpu-data = <0x01 0xf0514 0x00 0x01 0x00 0x01 0xf0514 0x00 0x01 0x00>;
|
|
samsung,npucmd-allow64stm-sfr = "sfrstm\0sfrstm\0sfrstm\0sfrstm\0sfrstm\0sfrstm\0sfrstm";
|
|
samsung,npucmd-allow64stm-data = <0x01 0xd64 0x00 0xffffffff 0x00 0x01 0xd60 0x00 0x01 0x00 0x01 0xd20 0xffffffff 0xffffffff 0x00 0x01 0xd00 0xffffffff 0xffffffff 0x00 0x01 0xd60 0x01 0x01 0x00 0x01 0xd20 0xffffffff 0xffffffff 0x00 0x01 0xd00 0xffffffff 0xffffffff 0x00>;
|
|
samsung,npucmd-sync-sfr = "sfrgnpu0\0sfrgnpu1";
|
|
samsung,npucmd-sync-data = <0x01 0x101b0 0x80000000 0xffffffff 0x00 0x01 0x101b0 0x80000000 0xffffffff 0x00>;
|
|
samsung,npucmd-fwpwm-sfr = "sfrdnc";
|
|
samsung,npucmd-fwpwm-data = <0x00 0x5002c 0x00 0xffffffff 0x00>;
|
|
samsung,imgloader-s2mpu-support = "true";
|
|
samsung,npusched-tpf-others = <0x5dc>;
|
|
samsung,npusched-afmlimit = "\0\f5";
|
|
samsung,npusched-min-active-cores = <0x01>;
|
|
samsung,npusched-dvfs = <0x129 0x104410 0x1e 0x78 0x4b 0x55 0x4b 0x1e 0x00 0x64 0x64 0x104410 0x104410 0x00 0x00 0x104410 0x104410 0x18d 0xe4458 0x1e 0x78 0x4b 0x55 0x1e 0x1e 0x00 0x64 0x64 0xe4458 0xe4458 0x00 0x00 0xe4458 0xe4458 0x18e 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x18f 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x190 0x104410 0x1e 0x78 0x4b 0x55 0x4b 0x1e 0x00 0x64 0x64 0x104410 0x104410 0x00 0x00 0x104410 0x104410>;
|
|
samsung,npusched-names = "NPU\0exynos-interactive\0DNC\0exynos-interactive\0INT\0\0MIF\0\0DSP\0exynos-interactive";
|
|
samsung,npudvfs-normal-dvfs = "DNC\0DNC\0NPU\0NPU\0DSP\0DSP\0INT\0MIF";
|
|
samsung,npudvfs-normal-clock = <0x00 0x00 0x01 0xe4458 0x00 0x00 0x01 0x104410 0x00 0x00 0x01 0x104410 0x00 0x00 0x00 0x00>;
|
|
samsung,npudvfs-boost-dvfs = "DNC\0NPU\0NPU\0DSP\0DSP\0INT\0MIF";
|
|
samsung,npudvfs-boost-clock = <0x00 0xe4458 0x01 0x104410 0x00 0x104410 0x01 0x104410 0x00 0x104410 0x00 0xc3500 0x00 0x3066a0>;
|
|
samsung,npudvfs-boostdlv3-dvfs = "DNC\0NPU\0NPU\0DSP\0DSP";
|
|
samsung,npudvfs-boostdlv3-clock = <0x00 0xe4458 0x01 0x104410 0x00 0x104410 0x01 0x104410 0x00 0x104410>;
|
|
samsung,npudvfs-boostblocking-dvfs = "DNC\0NPU\0NPU\0DSP\0DSP\0INT\0MIF";
|
|
samsung,npudvfs-boostblocking-clock = <0x00 0xe4458 0x01 0x104410 0x00 0x104410 0x01 0x104410 0x00 0x104410 0x00 0xc3500 0x00 0x3066a0>;
|
|
samsung,npuinter-isr-cpu-affinity = <0x05>;
|
|
samsung,npuproto-task-priority = <0x01>;
|
|
samsung,npuproto-task-cpu-affinity = <0x05>;
|
|
status = "ok";
|
|
vertex_name = "npu";
|
|
configs = <0x10 0x03 0x20 0x10 0x0a 0x400 0x400 0x400000 0x00 0x14 0x1000 0x8000 0x80000 0x12c 0x2ee0 0x00 0x00 0x50e00000 0x17eb0000 0x17ec0000 0x15010000 0x10000 0x00 0x01 0x02 0x03 0x80000000 0x2000000 0xf4240 0x00 0x3e8 0xbb8 0x08 0x00 0x00 0x80000 0x40000000>;
|
|
phandle = <0x343>;
|
|
|
|
samsung,npurmem-address {
|
|
|
|
fwmem {
|
|
memory-region = <0x191>;
|
|
iova = <0x30000000>;
|
|
size = <0x500000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
hwdev_dnc {
|
|
compatible = "samsung,exynos-npu-hwdev";
|
|
samsung,npuhwdev-name = "DNC";
|
|
samsung,npuhwdev-id = <0x01>;
|
|
clocks = <0x19 0x1f4>;
|
|
clock-names = "dnc_noc";
|
|
samsung,npuhwdev-type = <0x03>;
|
|
iommus = <0x187 0x188 0x189 0x18a 0x18b>;
|
|
samsung,iommu-group = <0x18c>;
|
|
#dma-address-cells = <0x01>;
|
|
#dma-size-cells = <0x01>;
|
|
dma-window = <0x80000000 0x80000000>;
|
|
dma-coherent;
|
|
status = "ok";
|
|
phandle = <0x344>;
|
|
};
|
|
|
|
hwdev_npu {
|
|
compatible = "samsung,exynos-npu-hwdev";
|
|
samsung,npuhwdev-name = "NPU";
|
|
samsung,npuhwdev-id = <0x02>;
|
|
samsung,npuhwdev-parent = "DNC";
|
|
power-domains = <0x13f>;
|
|
samsung,npuhwdev-type = <0x07>;
|
|
status = "ok";
|
|
phandle = <0x345>;
|
|
};
|
|
|
|
hwdev_dsp {
|
|
compatible = "samsung,exynos-npu-hwdev";
|
|
samsung,npuhwdev-name = "DSP";
|
|
samsung,npuhwdev-id = <0x04>;
|
|
samsung,npuhwdev-parent = "DNC";
|
|
power-domains = <0x140>;
|
|
samsung,npuhwdev-type = <0x07>;
|
|
status = "ok";
|
|
phandle = <0x346>;
|
|
};
|
|
|
|
hwdev_cl1 {
|
|
compatible = "samsung,exynos-npu-hwdev";
|
|
samsung,npuhwdev-name = "CL1";
|
|
samsung,npuhwdev-id = <0x40>;
|
|
samsung,npuhwdev-type = <0x04>;
|
|
status = "ok";
|
|
phandle = <0x347>;
|
|
};
|
|
|
|
hwdev_mif {
|
|
compatible = "samsung,exynos-npu-hwdev";
|
|
samsung,npuhwdev-name = "MIF";
|
|
samsung,npuhwdev-id = <0x08>;
|
|
samsung,npuhwdev-type = <0x08>;
|
|
status = "ok";
|
|
phandle = <0x348>;
|
|
};
|
|
|
|
hwdev_int {
|
|
compatible = "samsung,exynos-npu-hwdev";
|
|
samsung,npuhwdev-name = "INT";
|
|
samsung,npuhwdev-id = <0x10>;
|
|
samsung,npuhwdev-type = <0x08>;
|
|
status = "ok";
|
|
phandle = <0x349>;
|
|
};
|
|
|
|
pmucal_dbg {
|
|
latency_base = <0x20a4090>;
|
|
latency_size = <0x70>;
|
|
profile_en_offset = <0x3c0c>;
|
|
profile_en_bit = <0x02>;
|
|
profile_en = <0x00>;
|
|
|
|
pmucal_dbg_cpu {
|
|
|
|
core0 {
|
|
device_type = "pmucal_dbg_cpu";
|
|
id = <0x00>;
|
|
emul_offset = <0x100c>;
|
|
emul_bit = <0x00>;
|
|
emul_en = <0x00>;
|
|
latency_offset = <0x00>;
|
|
};
|
|
|
|
core1 {
|
|
device_type = "pmucal_dbg_cpu";
|
|
id = <0x01>;
|
|
emul_offset = <0x108c>;
|
|
emul_bit = <0x00>;
|
|
emul_en = <0x00>;
|
|
latency_offset = <0x08>;
|
|
};
|
|
|
|
core2 {
|
|
device_type = "pmucal_dbg_cpu";
|
|
id = <0x02>;
|
|
emul_offset = <0x110c>;
|
|
emul_bit = <0x00>;
|
|
emul_en = <0x00>;
|
|
latency_offset = <0x10>;
|
|
};
|
|
|
|
core3 {
|
|
device_type = "pmucal_dbg_cpu";
|
|
id = <0x03>;
|
|
emul_offset = <0x118c>;
|
|
emul_bit = <0x00>;
|
|
emul_en = <0x00>;
|
|
latency_offset = <0x18>;
|
|
};
|
|
|
|
core4 {
|
|
device_type = "pmucal_dbg_cpu";
|
|
id = <0x04>;
|
|
emul_offset = <0x130c>;
|
|
emul_bit = <0x00>;
|
|
emul_en = <0x00>;
|
|
latency_offset = <0x20>;
|
|
};
|
|
|
|
core5 {
|
|
device_type = "pmucal_dbg_cpu";
|
|
id = <0x05>;
|
|
emul_offset = <0x138c>;
|
|
emul_bit = <0x00>;
|
|
emul_en = <0x00>;
|
|
latency_offset = <0x28>;
|
|
};
|
|
|
|
core6 {
|
|
device_type = "pmucal_dbg_cpu";
|
|
id = <0x06>;
|
|
emul_offset = <0x150c>;
|
|
emul_bit = <0x00>;
|
|
emul_en = <0x00>;
|
|
latency_offset = <0x30>;
|
|
};
|
|
|
|
core7 {
|
|
device_type = "pmucal_dbg_cpu";
|
|
id = <0x07>;
|
|
emul_offset = <0x158c>;
|
|
emul_bit = <0x00>;
|
|
emul_en = <0x00>;
|
|
latency_offset = <0x38>;
|
|
};
|
|
};
|
|
|
|
pmucal_dbg_cluster {
|
|
|
|
cluster1 {
|
|
device_type = "pmucal_dbg_cluster";
|
|
id = <0x01>;
|
|
emul_offset = <0x1c8c>;
|
|
emul_bit = <0x00>;
|
|
emul_en = <0x00>;
|
|
latency_offset = <0x40>;
|
|
};
|
|
|
|
cluster2 {
|
|
device_type = "pmucal_dbg_cluster";
|
|
id = <0x02>;
|
|
emul_offset = <0x1d0c>;
|
|
emul_bit = <0x00>;
|
|
emul_en = <0x00>;
|
|
latency_offset = <0x48>;
|
|
};
|
|
};
|
|
|
|
pmucal_dbg_system {
|
|
|
|
sys-sicd {
|
|
device_type = "pmucal_dbg_system";
|
|
id = <0x00>;
|
|
emul_offset = <0x3a0c>;
|
|
emul_bit = <0x00>;
|
|
emul_en = <0x00>;
|
|
latency_offset = <0x50>;
|
|
};
|
|
|
|
sys-sleep {
|
|
device_type = "pmucal_dbg_system";
|
|
id = <0x08>;
|
|
emul_offset = <0x3a0c>;
|
|
emul_bit = <0x01>;
|
|
emul_en = <0x00>;
|
|
latency_offset = <0x60>;
|
|
};
|
|
};
|
|
};
|
|
|
|
fixed-rate-clocks {
|
|
|
|
oscclk {
|
|
compatible = "samsung,s5e9925-oscclk";
|
|
clock-frequency = <0x493e000>;
|
|
};
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "clocksource=arch_sys_counter clk_ignore_unused firmware_class.path=/vendor/firmware rcupdate.rcu_expedited=1 printk.devkmsg=on allow_mismatched_32bit_el0 s3c2410_wdt.tmr_atboot=1 cpif.cp_btl=on swiotlb=noforce cgroup.memory=nokmem coherent_pool=8M kasan=off loop.max_part=7 kfence.sample_interval=0";
|
|
linux,initrd-start = <0x84000000>;
|
|
linux,initrd-end = <0x84ffffff>;
|
|
phandle = <0x34a>;
|
|
};
|
|
|
|
interrupt-controller@10200000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <0x03>;
|
|
interrupt-controller;
|
|
reg = <0x00 0x10200000 0x10000 0x00 0x10240000 0x200000>;
|
|
interrupts = <0x01 0x09 0x04>;
|
|
phandle = <0x01>;
|
|
};
|
|
|
|
gic_vh {
|
|
compatible = "arm,gic-v3-vh";
|
|
class0-cpus = "0-3";
|
|
class1-cpus = "4-7";
|
|
phandle = <0x34b>;
|
|
};
|
|
|
|
clock-controller@0x1A320000 {
|
|
compatible = "samsung,s5e9925-clock";
|
|
reg = <0x00 0x1a320000 0x8000>;
|
|
#clock-cells = <0x01>;
|
|
phandle = <0x19>;
|
|
};
|
|
|
|
chipid@10000000 {
|
|
compatible = "samsung,s5e9925-chipid";
|
|
reg = <0x00 0x10000000 0x10000>;
|
|
has_additional_info = <0x01>;
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <0x01 0x0d 0xff08 0x01 0x0e 0xff08 0x01 0x0b 0xff08 0x01 0x0a 0xff08>;
|
|
clock-frequency = <0x186a000>;
|
|
use-clocksource-only;
|
|
};
|
|
|
|
samsung,memlogger {
|
|
compatible = "samsung,memlogger";
|
|
memory-region = <0x192>;
|
|
samsung,bl-node = <0x193>;
|
|
phandle = <0x34c>;
|
|
};
|
|
|
|
samsung,memlog_policy {
|
|
samsung,log-level = <0x04>;
|
|
samsung,file-default-status = <0x01>;
|
|
samsung,mem-constraint = <0x00>;
|
|
samsung,mem-to-file-allow = <0x01>;
|
|
phandle = <0x34d>;
|
|
};
|
|
|
|
ext_26m {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0x00>;
|
|
clock-frequency = <0x18cba80>;
|
|
clock-output-names = "ext-26m";
|
|
phandle = <0x34e>;
|
|
};
|
|
|
|
ext_200m {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0x00>;
|
|
clock-frequency = <0xbebc200>;
|
|
clock-output-names = "ext-200m";
|
|
phandle = <0x34f>;
|
|
};
|
|
|
|
exynos-pmu {
|
|
compatible = "samsung,exynos-pmu";
|
|
samsung,syscon-phandle = <0xd8>;
|
|
reg = <0x00 0x15860000 0x10000>;
|
|
reg-names = "pmu_alive";
|
|
cpu_offset = <0x00 0x80 0x100 0x180 0x300 0x380 0x400 0x600>;
|
|
};
|
|
|
|
system-controller@15860000 {
|
|
compatible = "samsung,exynos991-pmu\0syscon";
|
|
reg = <0x00 0x15860000 0x10000>;
|
|
phandle = <0xd8>;
|
|
};
|
|
|
|
system-controller@15960000 {
|
|
compatible = "samsung,spmi\0syscon";
|
|
reg = <0x00 0x15960000 0x1000>;
|
|
phandle = <0x194>;
|
|
};
|
|
|
|
exynos-pm {
|
|
compatible = "samsung,exynos-pm";
|
|
reg = <0x00 0x15850000 0x1000 0x00 0x10200200 0x100 0x00 0x159a0000 0x1000>;
|
|
reg-names = "gpio_alive_base\0gicd_ispendrn_base\0sysreg_vgpio2pmu";
|
|
num-eint = <0x22>;
|
|
num-gic = <0x1f>;
|
|
suspend_mode_idx = <0x08>;
|
|
wakeup_stat_offset = <0x3b50 0x3b54>;
|
|
wakeup_int_en_offset = <0x3b44 0x3b64>;
|
|
wakeup_int_en = <0xfff6f 0x180c>;
|
|
usbl2_wakeup_int_en = <0x00 0x0c>;
|
|
eint_wakeup_mask_offset = <0x60c 0x610>;
|
|
wakeup-stat-eint = <0x0d>;
|
|
wakeup-stat-rtc = <0x00>;
|
|
vgpio_wakeup_inten = <0xfc0>;
|
|
vgpio_wakeup_inten_offset = <0x288>;
|
|
wake_lock = <0x00>;
|
|
pcieon_suspend_available = <0x01>;
|
|
pcieon_suspend_mode_idx = <0x0d>;
|
|
|
|
wakeup_stats {
|
|
|
|
wakeup_stat {
|
|
ws-name = "RTC_ALARM\0RTC_TICK\0TRTC_ALARM\0TRTC_TICK\0SPARE\0CMGP2PMU_AP_EINT0\0CMGP2PMU_AP_EINT1\0MAILBOX_APM2AP\0MAILBOX_CP2AP\0MAILBOX_VTS2AP\0S_MAILBOX_CP2AP\0VTS_WDT\0CHUB_WDT\0EINT\0MAILBOX_GNSS2AP\0MAILBOX_CHUB2AP\0RESETREQ_CP\0RESETREQ_GNSS\0USB_REWA\0RSVD1_19\0UFD2AP";
|
|
};
|
|
|
|
wakeup2_stat {
|
|
ws-name = "AUD_ABOX_GIC400\0GNSS_ACTIVE\0USB20_PHY_FS_VMINUS\0USB20_PHY_FS_VPLUS\0UART_BT_CTSn\0UART_BT_RXD\0AUD_WDT\0PCIE_GEN3\0GNSS2AP_WAKEUP_INT\0CHUB2PMU_AP_EINT0\0CHUB2PMU_AP_EINT1\0RSVD2_11\0vGPIO2PMU_EINT1";
|
|
};
|
|
};
|
|
};
|
|
|
|
exynos_flexpmu_dbg {
|
|
compatible = "samsung,exynos-flexpmu-dbg";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
data-base = <0x20a3b00>;
|
|
data-size = <0x600>;
|
|
};
|
|
|
|
cmu_ewf {
|
|
compatible = "samsung,exynos-cmuewf";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
reg = <0x00 0x1a320000 0x1000>;
|
|
};
|
|
|
|
cal_if {
|
|
compatible = "samsung,exynos_cal_if";
|
|
reg = <0x00 0x1a320000 0x8000 0x00 0x18c00000 0x1000 0x00 0x1a030000 0x1000 0x00 0x1d040000 0x1000 0x00 0x1d050000 0x1000 0x00 0x1d060000 0x1000 0x00 0x1d030000 0x1000 0x00 0x10020000 0x1000>;
|
|
acpm-ipc-channel = <0x00>;
|
|
};
|
|
|
|
exynos-reboot {
|
|
compatible = "samsung,exynos-reboot";
|
|
samsung,syscon-phandle = <0xd8>;
|
|
samsung,spmi-syscon-phandle = <0x194>;
|
|
shutdown-offset = <0x30c>;
|
|
shutdown-trigger = <0x100>;
|
|
reboot-offset = <0x3c00>;
|
|
reboot-trigger = <0x02>;
|
|
reboot-cmd-offset = <0x810>;
|
|
status = "okay";
|
|
};
|
|
|
|
mct_alive@15890000 {
|
|
compatible = "samsung,s5e9925-mct";
|
|
reg = <0x00 0x15890000 0x800>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x01>;
|
|
interrupt-parent = <0x195>;
|
|
interrupts = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b>;
|
|
clocks = <0x19 0x01 0x19 0x0a>;
|
|
clock-names = "fin_pll\0mct";
|
|
use-clockevent-only;
|
|
|
|
mct-alive-map {
|
|
#interrupt-cells = <0x01>;
|
|
#address-cells = <0x00>;
|
|
#size-cells = <0x00>;
|
|
interrupt-map = <0x00 0x01 0x00 0x32 0x04 0x01 0x01 0x00 0x33 0x04 0x02 0x01 0x00 0x34 0x04 0x03 0x01 0x00 0x35 0x04 0x04 0x01 0x00 0x36 0x04 0x05 0x01 0x00 0x37 0x04 0x06 0x01 0x00 0x38 0x04 0x07 0x01 0x00 0x39 0x04 0x08 0x01 0x00 0x3a 0x04 0x09 0x01 0x00 0x3b 0x04 0x0a 0x01 0x00 0x3c 0x04 0x0b 0x01 0x00 0x3d 0x04>;
|
|
phandle = <0x195>;
|
|
};
|
|
};
|
|
|
|
iommu_group_dpu {
|
|
compatible = "samsung,sysmmu-group";
|
|
phandle = <0xd7>;
|
|
};
|
|
|
|
iommu_group_mfc {
|
|
compatible = "samsung,sysmmu-group";
|
|
phandle = <0x15c>;
|
|
};
|
|
|
|
iommu_group_is {
|
|
compatible = "samsung,sysmmu-group";
|
|
phandle = <0x166>;
|
|
};
|
|
|
|
iommu_group_is_1 {
|
|
compatible = "samsung,sysmmu-group";
|
|
phandle = <0x168>;
|
|
};
|
|
|
|
iommu_group_is_2 {
|
|
compatible = "samsung,sysmmu-group";
|
|
phandle = <0x170>;
|
|
};
|
|
|
|
iommu_group_is_3 {
|
|
compatible = "samsung,sysmmu-group";
|
|
phandle = <0x177>;
|
|
};
|
|
|
|
iommu_group_mscl_smfc {
|
|
compatible = "samsung,sysmmu-group";
|
|
phandle = <0x15f>;
|
|
};
|
|
|
|
iommu_group_aud {
|
|
compatible = "samsung,sysmmu-group";
|
|
phandle = <0x9d>;
|
|
};
|
|
|
|
iommu_group_npu {
|
|
compatible = "samsung,sysmmu-group";
|
|
phandle = <0x18c>;
|
|
};
|
|
|
|
iommu_group_vpc {
|
|
compatible = "samsung,sysmmu-group";
|
|
phandle = <0x350>;
|
|
};
|
|
|
|
iommu_group_camerapp_gdc {
|
|
compatible = "samsung,sysmmu-group";
|
|
phandle = <0x351>;
|
|
};
|
|
|
|
amba {
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
compatible = "arm,amba-bus";
|
|
interrupt-parent = <0x01>;
|
|
ranges;
|
|
|
|
pdma0@1A4E0000 {
|
|
compatible = "arm,pl330\0arm,primecell";
|
|
reg = <0x00 0x1a4e0000 0x1000>;
|
|
interrupts = <0x00 0x296 0x04>;
|
|
clocks = <0x19 0x640>;
|
|
clock-names = "apb_pclk";
|
|
#dma-cells = <0x01>;
|
|
#dma-channels = <0x08>;
|
|
#dma-requests = <0x20>;
|
|
#dma-multi-irq = <0x01>;
|
|
dma-arwrapper = <0x1a4e4400 0x1a4e4420 0x1a4e4440 0x1a4e4460 0x1a4e4480 0x1a4e44a0 0x1a4e44c0 0x1a4e44e0>;
|
|
dma-awwrapper = <0x1a4e4404 0x1a4e4424 0x1a4e4444 0x1a4e4464 0x1a4e4484 0x1a4e44a4 0x1a4e44c4 0x1a4e44e4>;
|
|
dma-instwrapper = <0x1a4e4500>;
|
|
dma-mask-bit = <0x24>;
|
|
coherent-mask-bit = <0x24>;
|
|
phandle = <0x60>;
|
|
};
|
|
};
|
|
|
|
exynos-bcmdbg {
|
|
compatible = "samsung,exynos-bcm_dbg";
|
|
memory-region = <0x196>;
|
|
pd-name = "pd_trex\0pd_aud\0pd_brp\0pd_allcsis\0pd_cstat\0pd_dnc\0pd_dpuf\0pd_g3dcore\0pd_strong\0pd_gnpu0\0pd_gnpu1\0pd_hsi0\0pd_hsi1\0pd_lme\0pd_m2m\0pd_mcsc\0pd_mfc0\0pd_mfc1\0pd_dsp0\0pd_vts\0pd_yuvp\0pd_sdma\0pd_ufd\0pd_nocl1c";
|
|
max_define_event = <0x08>;
|
|
define_events = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x04 0x02 0x26 0x24 0x05 0x03 0x27 0x25 0x02 0x04 0x00 0x24 0x24 0x05 0x01 0x25 0x25 0x03 0x04 0x02 0x04 0x26 0x05 0x03 0x05 0x27 0x04 0x02 0x10 0x10 0x26 0x03 0x11 0x11 0x27 0x05 0x04 0x12 0x12 0x06 0x05 0x13 0x13 0x14 0x06 0x02 0x15 0x18 0x1b 0x03 0x16 0x19 0x1c 0x07 0x04 0x05 0x26 0x24 0x00 0x01 0x27 0x25>;
|
|
default_define_event = <0x01>;
|
|
define_filter_id = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x00 0x00 0x03 0x00 0x00 0x04 0x00 0x00 0x05 0x00 0x00 0x06 0x00 0x00 0x07 0x00 0x00>;
|
|
define_filter_id_active = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x04 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
define_filter_other_0 = <0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x04 0x00 0x00 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x07 0x00 0x00 0x00>;
|
|
define_filter_other_1 = <0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x04 0x00 0x00 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x07 0x00 0x00 0x00>;
|
|
define_filter_other_active = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x04 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
define_sample_id = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x00 0x00 0x03 0x00 0x00 0x04 0x00 0x00 0x05 0x00 0x00 0x06 0x00 0x00 0x07 0x00 0x00>;
|
|
define_sample_id_enable = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x01 0x00 0x00 0x00 0x01 0x00 0x02 0x00 0x00 0x01 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01 0x04 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01 0x05 0x00 0x00 0x01 0x00 0x00 0x00 0x01 0x00 0x06 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
bcm_cnt_nr = <0x08>;
|
|
bcm_ip_nr = <0x40>;
|
|
bcm_ip_print_nr = <0x0a>;
|
|
initial_run_bcm_ip = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f>;
|
|
initial_bcm_run = <0x00>;
|
|
initial_period = <0x01>;
|
|
initial_bcm_mode = <0x00>;
|
|
available_stop_owner = <0x00 0x01 0x02 0x03>;
|
|
buff_size = <0x200000>;
|
|
glb_auto_en = <0x00>;
|
|
bcm_calc_num_ip = <0x04>;
|
|
bcm_calc_ip_idx = <0x01 0x03 0x32 0x3d>;
|
|
bcm_calc_ip_name = "CPUCL0_0\0G3D0\0IRPS0\0MIF0";
|
|
bcm_calc_ip_cnt = <0x02 0x04 0x04 0x04>;
|
|
bcm_calc_bus_width = <0x20 0x10 0x20 0x10>;
|
|
bcm_calc_sample_time = <0x32>;
|
|
perf_define_event = <0x07>;
|
|
|
|
ipc_bcm_event {
|
|
plugin-len = <0x05>;
|
|
plugin-name = "BCM";
|
|
};
|
|
};
|
|
|
|
exynos-sci_dbg {
|
|
compatible = "samsung,exynos-sci_dbg";
|
|
memory-region = <0x197>;
|
|
};
|
|
|
|
exynos-sci {
|
|
compatible = "samsung,exynos-sci";
|
|
memory-region = <0x198>;
|
|
interrupts = <0x00 0xcb 0x04 0x00 0xcc 0x04>;
|
|
nr_irq = <0x02>;
|
|
acpm-ipc-channel = <0x09>;
|
|
use_init_llc_region = <0x01>;
|
|
initial_llc_region = <0x01>;
|
|
ret_enable = <0x00>;
|
|
llc_enable = <0x01>;
|
|
hfreq_rate = <0x1e>;
|
|
freq_th = <0x1ef1e0>;
|
|
on_time_th = <0xbebc200>;
|
|
off_time_th = "SrN";
|
|
llc_gov_en = <0x01>;
|
|
region_name = "LLC_REGION_DISABLE\0LLC_REGION_CPU\0LLC_REGION_CALL\0LLC_REGION_OFFLOAD\0LLC_REGION_CPD2\0LLC_REGION_CPCPU\0LLC_REGION_DPU\0LLC_REGION_MFC0_INT\0LLC_REGION_MFC1_INT\0LLC_REGION_MFC0_DPB\0LLC_REGION_MFC1_DPB\0LLC_REGION_GDC\0LLC_REGION_MIGOV\0LLC_REGION_GPU\0LLC_REGION_NPU0\0LLC_REGION_NPU1\0LLC_REGION_NPU2\0LLC_REGION_DSP0\0LLC_REGION_DSP1\0LLC_REGION_CAM_MCFP\0LLC_REGION_CAM_CSIS\0LLC_REGION_CP_MAX_TP";
|
|
region_priority = <0x00 0x01 0x02 0x03 0x04 0x0c 0x05 0x0f 0x10 0x0d 0x0e 0x06 0x07 0x08 0x09 0x0a 0x0b 0x11 0x12 0x13 0x14 0x15>;
|
|
qpd_onoff = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x00 0x00 0x00>;
|
|
cpu_min_region = <0x00>;
|
|
devfreq = <0x18f>;
|
|
vch_pd_calid = <0xb1380015 0xb1380006>;
|
|
};
|
|
|
|
pwm@11C50000 {
|
|
compatible = "samsung,s3c6400-pwm";
|
|
reg = <0x00 0x11c50000 0x1000>;
|
|
samsung,pwm-outputs = <0x00 0x01 0x02 0x03 0x04>;
|
|
#pwm-cells = <0x03>;
|
|
clocks = <0x19 0x76d 0x19 0x01>;
|
|
clock-names = "pwm_pclk\0pwm_sclk";
|
|
status = "okay";
|
|
phandle = <0x352>;
|
|
};
|
|
|
|
watchdog_cl0@10050000 {
|
|
compatible = "samsung,s5e9925-v1-wdt";
|
|
reg = <0x00 0x10050000 0x100>;
|
|
interrupts = <0x00 0x3ad 0x04>;
|
|
clocks = <0x19 0x02 0x19 0x7d2>;
|
|
clock-names = "rate_watchdog\0gate_watchdog";
|
|
timeout-sec = <0x3c>;
|
|
shutdown_wdt_timeout = <0x1e>;
|
|
samsung,syscon-phandle = <0xd8>;
|
|
index = <0x00>;
|
|
status = "okay";
|
|
};
|
|
|
|
watchdog_cl1@10060000 {
|
|
compatible = "samsung,s5e9925-v2-wdt";
|
|
reg = <0x00 0x10060000 0x100>;
|
|
interrupts = <0x00 0x3ae 0x04>;
|
|
clocks = <0x19 0x02 0x19 0x7d3>;
|
|
clock-names = "rate_watchdog\0gate_watchdog";
|
|
timeout-sec = <0x3c>;
|
|
shutdown_wdt_timeout = <0x1e>;
|
|
samsung,syscon-phandle = <0xd8>;
|
|
index = <0x01>;
|
|
use_multistage_wdt;
|
|
status = "okay";
|
|
};
|
|
|
|
watchdog_builtin_wdt {
|
|
compatible = "samsung,s3c2410-builtin-wdt";
|
|
reg = <0x00 0x10050000 0x20>;
|
|
status = "okay";
|
|
};
|
|
|
|
exynos-migov {
|
|
compatible = "samsung,exynos-migov";
|
|
status = "okay";
|
|
window-period = <0x64>;
|
|
window-number = <0x1e>;
|
|
active-pct-thr = <0x32>;
|
|
valid-freq-delta-pct = <0x32>;
|
|
min-sensitivity = <0x0a>;
|
|
cpu-bottleneck-thr = <0x10e>;
|
|
gpu-bottleneck-thr = <0x320>;
|
|
gpu-ar-bottleneck-thr = <0x2ee>;
|
|
mif-bottleneck-thr = <0x12c0>;
|
|
hp-minlock-fps-delta-pct-thr = <0x177>;
|
|
hp-minlock-power-upper-thr = <0xbb8>;
|
|
hp-minlock-power-lower-thr = <0x9c4>;
|
|
dyn-mo-control = <0x00>;
|
|
mo-id = <0x27 0x28 0x29 0x2a>;
|
|
frame-src = <0x00>;
|
|
max-fps = <0x258>;
|
|
dt-ctrl-en = <0x01>;
|
|
dt-over-thr = <0x0a>;
|
|
dt-under-thr = <0x64>;
|
|
dt-up-step = <0x0a>;
|
|
dt-down-step = <0x0a>;
|
|
dpat-upper-thr = <0x895440>;
|
|
dpat-lower-thr = <0x00>;
|
|
dpat-lower-cnt-thr = <0x01>;
|
|
dpat-up-step = <0x0a>;
|
|
dpat-down-step = <0x0a>;
|
|
inc-perf-temp-thr = <0x41>;
|
|
inc-perf-power-thr = <0x00>;
|
|
inc-perf-thr = <0x00>;
|
|
dec-perf-thr = <0xfffffc18>;
|
|
fragutil-thr = <0x32>;
|
|
gpu-freq-thr = <0x62638>;
|
|
heavy-gpu-ms-thr = <0x32>;
|
|
runtime-thr-0 = <0xffffff38>;
|
|
runtime-thr-1 = <0xfffffe3e>;
|
|
runtime-thr-2 = <0xffffffce>;
|
|
runtime-thr-3 = <0xffffffce>;
|
|
runtime-thr-4 = <0xffffff06>;
|
|
runtime-thr-5 = <0xfffffff6>;
|
|
|
|
cl0 {
|
|
max = <0xc8>;
|
|
min = <0xffffff9c>;
|
|
up-step = <0x02>;
|
|
down-step = <0x05>;
|
|
default-step = <0x0a>;
|
|
pm-qos-cpu = <0x00>;
|
|
pm-qos-min-freq = <0x00>;
|
|
pm-qos-max-freq = <0x148200>;
|
|
hp-minlock-low-limit = <0x1e8c50>;
|
|
lp-minlock-low-limit = <0x00>;
|
|
};
|
|
|
|
cl1 {
|
|
max = <0xc8>;
|
|
min = <0xffffff9c>;
|
|
up-step = <0x02>;
|
|
down-step = <0x05>;
|
|
default-step = <0x0a>;
|
|
pm-qos-cpu = <0x04>;
|
|
pm-qos-max-freq = "\0#(";
|
|
hp-minlock-low-limit = <0x1e26c0>;
|
|
lp-minlock-low-limit = <0x00>;
|
|
};
|
|
|
|
cl2 {
|
|
max = <0xc8>;
|
|
min = <0xffffff9c>;
|
|
up-step = <0x02>;
|
|
down-step = <0x05>;
|
|
default-step = <0x0a>;
|
|
pm-qos-cpu = <0x07>;
|
|
pm-qos-max-freq = "\0#(";
|
|
hp-minlock-low-limit = <0x1e26c0>;
|
|
lp-minlock-low-limit = <0x00>;
|
|
};
|
|
|
|
gpu {
|
|
max = <0x64>;
|
|
min = <0xffffff9c>;
|
|
up-step = <0x02>;
|
|
down-step = <0x05>;
|
|
default-step = <0x02>;
|
|
pm-qos-max-class = <0x1b>;
|
|
pm-qos-min-class = <0x1a>;
|
|
pm-qos-max-freq = <0xe7b08>;
|
|
pm-qos-min-freq = <0x00>;
|
|
q0-empty-pct-thr = <0x00>;
|
|
q1-empty-pct-thr = <0x00>;
|
|
active-pct-thr = <0x64>;
|
|
};
|
|
|
|
mif {
|
|
max = <0xc8>;
|
|
min = <0x00>;
|
|
up-step = <0x02>;
|
|
down-step = <0x05>;
|
|
default-step = <0x0a>;
|
|
pm-qos-min-class = <0x0e>;
|
|
pm-qos-max-class = <0x0f>;
|
|
freq-stats0-mode-min-freq = <0x1a2f20>;
|
|
pm-qos-max-freq = <0x3066a0>;
|
|
pm-qos-min-freq = <0xce4c8>;
|
|
freq-stats0-thr = <0x1194>;
|
|
freq-stats0-updown-delta-pct-thr = <0xc8>;
|
|
hp-minlock-low-limit = <0x29a810>;
|
|
};
|
|
};
|
|
|
|
exynos-cpu-profiler {
|
|
compatible = "samsung,exynos-cpu-profiler";
|
|
status = "okay";
|
|
|
|
domain@0 {
|
|
sibling-cpus = "0-3";
|
|
cal-id = <0xb040002>;
|
|
migov-id = <0x00>;
|
|
power-coefficient = <0xd9>;
|
|
static-power-coefficient = <0x06>;
|
|
phandle = <0x353>;
|
|
};
|
|
|
|
domain@1 {
|
|
sibling-cpus = "4-6";
|
|
cal-id = <0xb040003>;
|
|
migov-id = <0x01>;
|
|
power-coefficient = <0x21c>;
|
|
static-power-coefficient = <0x96>;
|
|
tz-name = "MID";
|
|
phandle = <0x354>;
|
|
};
|
|
|
|
domain@2 {
|
|
sibling-cpus = "7";
|
|
cal-id = <0xb040004>;
|
|
migov-id = <0x02>;
|
|
power-coefficient = <0x35b>;
|
|
static-power-coefficient = <0x257>;
|
|
tz-name = "BIG";
|
|
phandle = <0x355>;
|
|
};
|
|
};
|
|
|
|
exynos-gpu-profiler {
|
|
compatible = "samsung,exynos-gpu-profiler";
|
|
status = "okay";
|
|
cal-id = <0xb04000d>;
|
|
migov-id = <0x03>;
|
|
power-coefficient = <0x201c>;
|
|
static-power-coefficient = <0x00>;
|
|
tz-name = "G3D";
|
|
};
|
|
|
|
exynos-mif-profiler {
|
|
compatible = "samsung,exynos-mif-profiler";
|
|
status = "okay";
|
|
cal-id = <0xb040000>;
|
|
migov-id = <0x04>;
|
|
devfreq-type = <0x00>;
|
|
power-coefficient = <0x5abdfb0>;
|
|
static-power-coefficient = <0x217>;
|
|
};
|
|
|
|
contexthub {
|
|
compatible = "samsung,exynos-nanohub";
|
|
memory-region = <0x199>;
|
|
interrupts = <0x00 0x2a 0x04 0x00 0x130 0x04>;
|
|
reg = <0x00 0x14cc0000 0x200 0x00 0x2800000 0x180000 0x00 0x148f0000 0x100 0x00 0x15530000 0xc0 0x00 0x15540000 0xc0 0x00 0x15560000 0x200 0x00 0x15861b20 0x10 0x00 0x14860000 0x50>;
|
|
reg-names = "mailbox\0sram\0dumpgpr\0baaw_c_chub\0baaw_ld_chub\0upmu\0chub_out\0chub_dump_pwm";
|
|
baaw,names = "baaw_c_chub\0baaw_ld_chub";
|
|
baaw,sizes = <0x04 0x01>;
|
|
baaw,values = <0x00 0x60000 0x100000 0x60000 0x00 0x70 0x14e00 0x15200 0x14e00 0x80000003 0x90 0x50000 0x50001 0x50000 0x80000003 0xa0 0x40a60 0x40a70 0x15560 0x80000003 0x80 0x50000 0x50001 0x10000 0x80000003>;
|
|
smc-required = "true";
|
|
multi-os = "disabled";
|
|
one-binary = "enabled";
|
|
chub-dfs-gov = "disabled";
|
|
use_alive_mct;
|
|
chub_mct_alive_base = <0x15890000>;
|
|
chub_mct_frc_offset = <0x110>;
|
|
clocks = <0x19 0x0b 0x19 0x0c>;
|
|
clock-names = "chub_bus\0chub_peri";
|
|
phandle = <0x356>;
|
|
};
|
|
|
|
teegris {
|
|
compatible = "samsung,teegris";
|
|
interrupts = <0x00 0x364 0x04 0x00 0x365 0x04>;
|
|
};
|
|
|
|
__symbols__ {
|
|
reserved_memory = "/reserved-memory";
|
|
abox_dbg = "/reserved-memory/abox-dbg";
|
|
abox_slog = "/reserved-memory/abox-slog";
|
|
abox_rmem = "/reserved-memory/abox-rmem";
|
|
abox_rdma_compr = "/reserved-memory/abox-rdma-compr";
|
|
dp_ado_rmem = "/reserved-memory/dpado-rmem";
|
|
sgpu_rmem = "/reserved-memory/sgpu_rmem";
|
|
ect_binary = "/reserved-memory/ect_binary";
|
|
dss_rmem = "/reserved-memory/debug_snapshot";
|
|
header = "/reserved-memory/debug_snapshot/header";
|
|
log_kernel = "/reserved-memory/debug_snapshot/log_kernel";
|
|
log_platform = "/reserved-memory/debug_snapshot/log_platform";
|
|
log_s2d = "/reserved-memory/debug_snapshot/log_s2d";
|
|
log_first = "/reserved-memory/debug_snapshot/log_first";
|
|
log_kevents = "/reserved-memory/debug_snapshot/log_kevents";
|
|
log_kevents_small = "/reserved-memory/debug_snapshot/log_kevents_small";
|
|
log_arrdumpreset = "/reserved-memory/debug_snapshot/log_arrdumpreset";
|
|
log_itmon = "/reserved-memory/log_itmon";
|
|
debug_kinfo_reserved = "/reserved-memory/debug_kinfo_reserved@effff000";
|
|
log_bcm = "/reserved-memory/log_bcm";
|
|
log_llc = "/reserved-memory/log_llc";
|
|
log_ppc = "/reserved-memory/log_ppc";
|
|
log_backtrace = "/reserved-memory/log_backtrace";
|
|
memlog_mem = "/reserved-memory/memlog_region";
|
|
s2mpu_table = "/reserved-memory/s2mpu_table";
|
|
seclog_mem = "/reserved-memory/seclog_mem";
|
|
gnss_rmem = "/reserved-memory/gnss_rmem";
|
|
teegris_rmem = "/reserved-memory/teegris_rmem";
|
|
cp_rmem = "/reserved-memory/cp_rmem";
|
|
cp_rmem1 = "/reserved-memory/cp_rmem1";
|
|
mfc_fw_rmem = "/reserved-memory/mfc_fw_rmem";
|
|
dnc_fw_mem = "/reserved-memory/dnc-fw-mem";
|
|
contexthub_rmem = "/reserved-memory/contexthub_rmem";
|
|
wifi_msi_rmem = "/reserved-memory/wifi_msi_rmem";
|
|
crypto = "/reserved-memory/crypto";
|
|
vstream = "/reserved-memory/vstream";
|
|
tui = "/reserved-memory/tui";
|
|
rbin = "/reserved-memory/rbin";
|
|
secure_camera = "/reserved-memory/secure_camera";
|
|
vframe = "/reserved-memory/vframe";
|
|
vscaler = "/reserved-memory/vscaler";
|
|
gpu_buffer = "/reserved-memory/gpu_buffer";
|
|
secure_dsp = "/reserved-memory/secure_dsp";
|
|
memlog_bl_base = "/memlog_bl_base";
|
|
sysmmu_d_aud = "/sysmmu@0x18D50000";
|
|
sysmmu_d0_brp = "/sysmmu@0x17430000";
|
|
sysmmu_d1_brp = "/sysmmu@0x17530000";
|
|
sysmmu_d2_brp = "/sysmmu@0x17570000";
|
|
sysmmu_d0_csis = "/sysmmu@0x17170000";
|
|
sysmmu_d1_csis = "/sysmmu@0x171A0000";
|
|
sysmmu_d2_csis = "/sysmmu@0x171D0000";
|
|
sysmmu_d_cstat = "/sysmmu@0x18540000";
|
|
sysmmu_sdma0 = "/sysmmu@0x16040000";
|
|
sysmmu_sdma1 = "/sysmmu@0x16070000";
|
|
sysmmu_sdma2 = "/sysmmu@0x160A0000";
|
|
sysmmu_sdma3 = "/sysmmu@0x160D0000";
|
|
sysmmu_ipdnc = "/sysmmu@0x16100000";
|
|
sysmmu_d0_dpuf0 = "/sysmmu@0x1AC40000";
|
|
sysmmu_d1_dpuf0 = "/sysmmu@0x1AC50000";
|
|
sysmmu_d0_dpuf1 = "/sysmmu@0x1AE40000";
|
|
sysmmu_d1_dpuf1 = "/sysmmu@0x1AE50000";
|
|
sysmmu_d_lme = "/sysmmu@0x176A0000";
|
|
sysmmu_d_m2m = "/sysmmu@0x18A00000";
|
|
sysmmu_d0_mcsc = "/sysmmu@0x15C70000";
|
|
sysmmu_d1_mcsc = "/sysmmu@0x15CA0000";
|
|
sysmmu_d2_mcsc = "/sysmmu@0x15CD0000";
|
|
sysmmu_d3_mcsc = "/sysmmu@0x15D00000";
|
|
sysmmu_d4_mcsc = "/sysmmu@0x15D30000";
|
|
sysmmu_d0_mfc0 = "/sysmmu@0x18670000";
|
|
sysmmu_d1_mfc0 = "/sysmmu@0x186A0000";
|
|
sysmmu_d0_mfc1 = "/sysmmu@0x18870000";
|
|
sysmmu_d1_mfc1 = "/sysmmu@0x188A0000";
|
|
sysmmu_d0_yuvp = "/sysmmu@0x18070000";
|
|
sysmmu_d1_yuvp = "/sysmmu@0x180A0000";
|
|
pinctrl_0 = "/pinctrl@15850000";
|
|
gpa0 = "/pinctrl@15850000/gpa0";
|
|
gpa1 = "/pinctrl@15850000/gpa1";
|
|
gpa2 = "/pinctrl@15850000/gpa2";
|
|
gpa3 = "/pinctrl@15850000/gpa3";
|
|
gpa4 = "/pinctrl@15850000/gpa4";
|
|
gpq0 = "/pinctrl@15850000/gpq0";
|
|
gpq1 = "/pinctrl@15850000/gpq1";
|
|
gpq2 = "/pinctrl@15850000/gpq2";
|
|
uart1_bus_single = "/pinctrl@15850000/uart1-bus";
|
|
uart1_bus_rts = "/pinctrl@15850000/uart1-bus-rts";
|
|
uart1_bus_tx_dat = "/pinctrl@15850000/uart1-bus-tx-dat";
|
|
uart1_bus_tx_con = "/pinctrl@15850000/uart1-bus-tx-con";
|
|
pinctrl_1 = "/pinctrl@14E30000";
|
|
gpm0 = "/pinctrl@14E30000/gpm0";
|
|
gpm1 = "/pinctrl@14E30000/gpm1";
|
|
gpm2 = "/pinctrl@14E30000/gpm2";
|
|
gpm3 = "/pinctrl@14E30000/gpm3";
|
|
gpm4 = "/pinctrl@14E30000/gpm4";
|
|
gpm5 = "/pinctrl@14E30000/gpm5";
|
|
gpm6 = "/pinctrl@14E30000/gpm6";
|
|
gpm7 = "/pinctrl@14E30000/gpm7";
|
|
gpm8 = "/pinctrl@14E30000/gpm8";
|
|
gpm9 = "/pinctrl@14E30000/gpm9";
|
|
gpm10 = "/pinctrl@14E30000/gpm10";
|
|
gpm11 = "/pinctrl@14E30000/gpm11";
|
|
gpm12 = "/pinctrl@14E30000/gpm12";
|
|
gpm13 = "/pinctrl@14E30000/gpm13";
|
|
gpm14 = "/pinctrl@14E30000/gpm14";
|
|
gpm15 = "/pinctrl@14E30000/gpm15";
|
|
gpm16 = "/pinctrl@14E30000/gpm16";
|
|
gpm17 = "/pinctrl@14E30000/gpm17";
|
|
gpm20 = "/pinctrl@14E30000/gpm20";
|
|
gpm21 = "/pinctrl@14E30000/gpm21";
|
|
gpm22 = "/pinctrl@14E30000/gpm22";
|
|
gpm23 = "/pinctrl@14E30000/gpm23";
|
|
gpm24 = "/pinctrl@14E30000/gpm24";
|
|
hsi2c24_bus = "/pinctrl@14E30000/hsi2c24-bus";
|
|
hsi2c25_bus = "/pinctrl@14E30000/hsi2c25-bus";
|
|
hsi2c26_bus = "/pinctrl@14E30000/hsi2c26-bus";
|
|
hsi2c27_bus = "/pinctrl@14E30000/hsi2c27-bus";
|
|
hsi2c28_bus = "/pinctrl@14E30000/hsi2c28-bus";
|
|
hsi2c29_bus = "/pinctrl@14E30000/hsi2c29-bus";
|
|
hsi2c30_bus = "/pinctrl@14E30000/hsi2c30-bus";
|
|
hsi2c31_bus = "/pinctrl@14E30000/hsi2c31-bus";
|
|
hsi2c32_bus = "/pinctrl@14E30000/hsi2c32-bus";
|
|
hsi2c33_bus = "/pinctrl@14E30000/hsi2c33-bus";
|
|
hsi2c34_bus = "/pinctrl@14E30000/hsi2c34-bus";
|
|
hsi2c35_bus = "/pinctrl@14E30000/hsi2c35-bus";
|
|
hsi2c36_bus = "/pinctrl@14E30000/hsi2c36-bus";
|
|
hsi2c37_bus = "/pinctrl@14E30000/hsi2c37-bus";
|
|
hsi2c38_bus = "/pinctrl@14E30000/hsi2c38-bus";
|
|
spi12_bus = "/pinctrl@14E30000/spi12-bus";
|
|
spi12_cs = "/pinctrl@14E30000/spi12-cs";
|
|
spi12_cs_func = "/pinctrl@14E30000/spi12-cs-func";
|
|
spi13_bus = "/pinctrl@14E30000/spi13-bus";
|
|
spi13_cs = "/pinctrl@14E30000/spi13-cs";
|
|
spi13_cs_func = "/pinctrl@14E30000/spi13-cs-func";
|
|
spi14_bus = "/pinctrl@14E30000/spi14-bus";
|
|
spi14_cs = "/pinctrl@14E30000/spi14-cs";
|
|
spi14_cs_func = "/pinctrl@14E30000/spi14-cs-func";
|
|
spi15_bus = "/pinctrl@14E30000/spi15-bus";
|
|
spi15_cs = "/pinctrl@14E30000/spi15-cs";
|
|
spi15_cs_func = "/pinctrl@14E30000/spi15-cs-func";
|
|
spi16_bus = "/pinctrl@14E30000/spi16-bus";
|
|
spi16_cs = "/pinctrl@14E30000/spi16-cs";
|
|
spi16_cs_func = "/pinctrl@14E30000/spi16-cs-func";
|
|
spi17_bus = "/pinctrl@14E30000/spi17-bus";
|
|
spi17_cs = "/pinctrl@14E30000/spi17-cs";
|
|
spi17_cs_func = "/pinctrl@14E30000/spi17-cs-func";
|
|
spi18_bus = "/pinctrl@14E30000/spi18-bus";
|
|
spi18_cs = "/pinctrl@14E30000/spi18-cs";
|
|
spi18_cs_func = "/pinctrl@14E30000/spi18-cs-func";
|
|
uart14_bus_single = "/pinctrl@14E30000/uart14-bus";
|
|
uart14_bus_dual = "/pinctrl@14E30000/uart14-bus-dual";
|
|
uart15_bus_single = "/pinctrl@14E30000/uart15-bus";
|
|
uart15_bus_dual = "/pinctrl@14E30000/uart15-bus-dual";
|
|
uart16_bus_single = "/pinctrl@14E30000/uart16-bus";
|
|
uart16_bus_dual = "/pinctrl@14E30000/uart16-bus-dual";
|
|
uart17_bus_single = "/pinctrl@14E30000/uart17-bus";
|
|
uart17_bus_dual = "/pinctrl@14E30000/uart17-bus-dual";
|
|
uart18_bus_single = "/pinctrl@14E30000/uart18-bus";
|
|
uart18_bus_dual = "/pinctrl@14E30000/uart18-bus-dual";
|
|
uart19_bus_single = "/pinctrl@14E30000/uart19-bus";
|
|
uart19_bus_dual = "/pinctrl@14E30000/uart19-bus-dual";
|
|
uart20_bus_single = "/pinctrl@14E30000/uart20-bus";
|
|
uart20_bus_dual = "/pinctrl@14E30000/uart20-bus-dual";
|
|
pinctrl_2 = "/pinctrl@11240000";
|
|
gpf0 = "/pinctrl@11240000/gpf0";
|
|
pcie0_clkreq = "/pinctrl@11240000/pcie0_clkreq";
|
|
pcie0_perst = "/pinctrl@11240000/pcie0_perst";
|
|
pcie1_clkreq = "/pinctrl@11240000/pcie1_clkreq";
|
|
pcie1_perst = "/pinctrl@11240000/pcie1_perst";
|
|
pinctrl_3 = "/pinctrl@11040000";
|
|
gpf1 = "/pinctrl@11040000/gpf1";
|
|
pinctrl_4 = "/pinctrl@11060000";
|
|
gpf2 = "/pinctrl@11060000/gpf2";
|
|
ufs_rst_n = "/pinctrl@11060000/ufs-rst-n";
|
|
ufs_refclk_out = "/pinctrl@11060000/ufs-refclk-out";
|
|
pinctrl_5 = "/pinctrl@10430000";
|
|
gpb0 = "/pinctrl@10430000/gpb0";
|
|
gpb1 = "/pinctrl@10430000/gpb1";
|
|
gpb2 = "/pinctrl@10430000/gpb2";
|
|
gpb3 = "/pinctrl@10430000/gpb3";
|
|
gpp4 = "/pinctrl@10430000/gpp4";
|
|
gpc0 = "/pinctrl@10430000/gpc0";
|
|
gpc1 = "/pinctrl@10430000/gpc1";
|
|
gpc2 = "/pinctrl@10430000/gpc2";
|
|
gpg1 = "/pinctrl@10430000/gpg1";
|
|
gpg2 = "/pinctrl@10430000/gpg2";
|
|
aud_i2s0_bus = "/pinctrl@10430000/aud-i2s0-bus";
|
|
aud_i2s0_idle = "/pinctrl@10430000/aud-i2s0-idle";
|
|
aud_i2s1_bus = "/pinctrl@10430000/aud-i2s1-bus";
|
|
aud_i2s1_idle = "/pinctrl@10430000/aud-i2s1-idle";
|
|
aud_i2s2_bus = "/pinctrl@10430000/aud-i2s2-bus";
|
|
aud_i2s2_idle = "/pinctrl@10430000/aud-i2s2-idle";
|
|
aud_i2s3_bus = "/pinctrl@10430000/aud-i2s3-bus";
|
|
aud_i2s3_pci = "/pinctrl@10430000/aud-i2s3-pci";
|
|
aud_i2s3_idle = "/pinctrl@10430000/aud-i2s3-idle";
|
|
aud_dsd_bus = "/pinctrl@10430000/aud-dsd-bus";
|
|
aud_dsd_idle = "/pinctrl@10430000/aud-dsd-idle";
|
|
hsi2c8_bus = "/pinctrl@10430000/hsi2c8-bus";
|
|
hsi2c9_bus = "/pinctrl@10430000/hsi2c9-bus";
|
|
spi4_bus = "/pinctrl@10430000/spi4-bus";
|
|
spi4_cs = "/pinctrl@10430000/spi4-cs";
|
|
spi4_cs_func = "/pinctrl@10430000/spi4-cs-func";
|
|
i3c0_bus = "/pinctrl@10430000/i3c0-bus";
|
|
i3c1_bus = "/pinctrl@10430000/i3c1-bus";
|
|
i3c2_bus = "/pinctrl@10430000/i3c2-bus";
|
|
uart6_bus_single = "/pinctrl@10430000/uart6-bus";
|
|
uart6_bus_dual = "/pinctrl@10430000/uart6-bus-dual";
|
|
sensor_mclk0_out = "/pinctrl@10430000/sensor-mclk0-out";
|
|
sensor_mclk1_out = "/pinctrl@10430000/sensor-mclk1-out";
|
|
sensor_mclk2_out = "/pinctrl@10430000/sensor-mclk2-out";
|
|
sensor_mclk3_out = "/pinctrl@10430000/sensor-mclk3-out";
|
|
sensor_mclk4_out = "/pinctrl@10430000/sensor-mclk4-out";
|
|
sensor_mclk5_out = "/pinctrl@10430000/sensor-mclk5-out";
|
|
sensor_mclk0_fn = "/pinctrl@10430000/sensor-mclk0-fn";
|
|
sensor_mclk1_fn = "/pinctrl@10430000/sensor-mclk1-fn";
|
|
sensor_mclk2_fn = "/pinctrl@10430000/sensor-mclk2-fn";
|
|
sensor_mclk3_fn = "/pinctrl@10430000/sensor-mclk3-fn";
|
|
sensor_mclk4_fn = "/pinctrl@10430000/sensor-mclk4-fn";
|
|
sensor_mclk5_fn = "/pinctrl@10430000/sensor-mclk5-fn";
|
|
decon_0_te_on = "/pinctrl@10430000/decon_0_te_on";
|
|
decon_0_te_off = "/pinctrl@10430000/decon_0_te_off";
|
|
pinctrl_6 = "/pinctrl@10730000";
|
|
gpp7 = "/pinctrl@10730000/gpp7";
|
|
gpp8 = "/pinctrl@10730000/gpp8";
|
|
gpp9 = "/pinctrl@10730000/gpp9";
|
|
gpp10 = "/pinctrl@10730000/gpp10";
|
|
hsi2c14_bus = "/pinctrl@10730000/hsi2c14-bus";
|
|
hsi2c15_bus = "/pinctrl@10730000/hsi2c15-bus";
|
|
hsi2c16_bus = "/pinctrl@10730000/hsi2c16-bus";
|
|
hsi2c17_bus = "/pinctrl@10730000/hsi2c17-bus";
|
|
hsi2c18_bus = "/pinctrl@10730000/hsi2c18-bus";
|
|
hsi2c19_bus = "/pinctrl@10730000/hsi2c19-bus";
|
|
hsi2c20_bus = "/pinctrl@10730000/hsi2c20-bus";
|
|
hsi2c21_bus = "/pinctrl@10730000/hsi2c21-bus";
|
|
spi7_bus = "/pinctrl@10730000/spi7-bus";
|
|
spi7_cs = "/pinctrl@10730000/spi7-cs";
|
|
spi7_cs_func = "/pinctrl@10730000/spi7-cs-func";
|
|
spi8_bus = "/pinctrl@10730000/spi8-bus";
|
|
spi8_cs = "/pinctrl@10730000/spi8-cs";
|
|
spi8_cs_func = "/pinctrl@10730000/spi8-cs-func";
|
|
spi9_bus = "/pinctrl@10730000/spi9-bus";
|
|
spi9_cs = "/pinctrl@10730000/spi9-cs";
|
|
spi9_cs_func = "/pinctrl@10730000/spi9-cs-func";
|
|
spi10_bus = "/pinctrl@10730000/spi10-bus";
|
|
spi10_cs = "/pinctrl@10730000/spi10-cs";
|
|
spi10_cs_func = "/pinctrl@10730000/spi10-cs-func";
|
|
uart9_bus_single = "/pinctrl@10730000/uart9-bus";
|
|
uart9_bus_dual = "/pinctrl@10730000/uart9-bus-dual";
|
|
uart10_bus_single = "/pinctrl@10730000/uart10-bus";
|
|
uart10_bus_dual = "/pinctrl@10730000/uart10-bus-dual";
|
|
uart11_bus_single = "/pinctrl@10730000/uart11-bus";
|
|
uart11_bus_dual = "/pinctrl@10730000/uart11-bus-dual";
|
|
uart12_bus_single = "/pinctrl@10730000/uart12-bus";
|
|
uart12_bus_dual = "/pinctrl@10730000/uart12-bus-dual";
|
|
pinctrl_7 = "/pinctrl@11C30000";
|
|
gpp0 = "/pinctrl@11C30000/gpp0";
|
|
gpp1 = "/pinctrl@11C30000/gpp1";
|
|
gpp2 = "/pinctrl@11C30000/gpp2";
|
|
gpp3 = "/pinctrl@11C30000/gpp3";
|
|
gpp5 = "/pinctrl@11C30000/gpp5";
|
|
gpp6 = "/pinctrl@11C30000/gpp6";
|
|
gpp11 = "/pinctrl@11C30000/gpp11";
|
|
gpc3 = "/pinctrl@11C30000/gpc3";
|
|
gpc4 = "/pinctrl@11C30000/gpc4";
|
|
gpc5 = "/pinctrl@11C30000/gpc5";
|
|
gpc6 = "/pinctrl@11C30000/gpc6";
|
|
gpc7 = "/pinctrl@11C30000/gpc7";
|
|
gpc8 = "/pinctrl@11C30000/gpc8";
|
|
gpc9 = "/pinctrl@11C30000/gpc9";
|
|
gpg0 = "/pinctrl@11C30000/gpg0";
|
|
hsi2c0_bus = "/pinctrl@11C30000/hsi2c0-bus";
|
|
hsi2c1_bus = "/pinctrl@11C30000/hsi2c1-bus";
|
|
hsi2c2_bus = "/pinctrl@11C30000/hsi2c2-bus";
|
|
hsi2c3_bus = "/pinctrl@11C30000/hsi2c3-bus";
|
|
hsi2c4_bus = "/pinctrl@11C30000/hsi2c4-bus";
|
|
hsi2c5_bus = "/pinctrl@11C30000/hsi2c5-bus";
|
|
hsi2c6_bus = "/pinctrl@11C30000/hsi2c6-bus";
|
|
hsi2c7_bus = "/pinctrl@11C30000/hsi2c7-bus";
|
|
hsi2c10_bus = "/pinctrl@11C30000/hsi2c10-bus";
|
|
hsi2c11_bus = "/pinctrl@11C30000/hsi2c11-bus";
|
|
hsi2c12_bus = "/pinctrl@11C30000/hsi2c12-bus";
|
|
hsi2c13_bus = "/pinctrl@11C30000/hsi2c13-bus";
|
|
hsi2c22_bus = "/pinctrl@11C30000/hsi2c22-bus";
|
|
hsi2c23_bus = "/pinctrl@11C30000/hsi2c23-bus";
|
|
spi0_bus = "/pinctrl@11C30000/spi0-bus";
|
|
spi0_cs = "/pinctrl@11C30000/spi0-cs";
|
|
spi0_cs_func = "/pinctrl@11C30000/spi0-cs-func";
|
|
spi1_bus = "/pinctrl@11C30000/spi1-bus";
|
|
spi1_cs = "/pinctrl@11C30000/spi1-cs";
|
|
spi1_cs_func = "/pinctrl@11C30000/spi1-cs-func";
|
|
spi2_bus = "/pinctrl@11C30000/spi2-bus";
|
|
spi2_cs = "/pinctrl@11C30000/spi2-cs";
|
|
spi2_cs_func = "/pinctrl@11C30000/spi2-cs-func";
|
|
spi3_bus = "/pinctrl@11C30000/spi3-bus";
|
|
spi3_cs = "/pinctrl@11C30000/spi3-cs";
|
|
spi3_cs_func = "/pinctrl@11C30000/spi3-cs-func";
|
|
spi5_bus = "/pinctrl@11C30000/spi5-bus";
|
|
spi5_cs = "/pinctrl@11C30000/spi5-cs";
|
|
spi5_cs_func = "/pinctrl@11C30000/spi5-cs-func";
|
|
spi6_bus = "/pinctrl@11C30000/spi6-bus";
|
|
spi6_cs = "/pinctrl@11C30000/spi6-cs";
|
|
spi6_cs_func = "/pinctrl@11C30000/spi6-cs-func";
|
|
spi11_bus = "/pinctrl@11C30000/spi11-bus";
|
|
spi11_cs = "/pinctrl@11C30000/spi11-cs";
|
|
spi11_cs_func = "/pinctrl@11C30000/spi11-cs-func";
|
|
uart0_bus = "/pinctrl@11C30000/uart0-bus";
|
|
uart2_bus_single = "/pinctrl@11C30000/uart2-bus";
|
|
uart2_bus_dual = "/pinctrl@11C30000/uart2-bus-dual";
|
|
uart3_bus_single = "/pinctrl@11C30000/uart3-bus";
|
|
uart3_bus_dual = "/pinctrl@11C30000/uart3-bus-dual";
|
|
uart4_bus_single = "/pinctrl@11C30000/uart4-bus";
|
|
uart4_bus_dual = "/pinctrl@11C30000/uart4-bus-dual";
|
|
uart5_bus_single = "/pinctrl@11C30000/uart5-bus";
|
|
uart5_bus_dual = "/pinctrl@11C30000/uart5-bus-dual";
|
|
uart7_bus_single = "/pinctrl@11C30000/uart7-bus";
|
|
uart7_bus_dual = "/pinctrl@11C30000/uart7-bus-dual";
|
|
uart8_bus_single = "/pinctrl@11C30000/uart8-bus";
|
|
uart8_bus_dual = "/pinctrl@11C30000/uart8-bus-dual";
|
|
uart13_bus_single = "/pinctrl@11C30000/uart13-bus";
|
|
uart13_bus_dual = "/pinctrl@11C30000/uart13-bus-dual";
|
|
i3c3_bus = "/pinctrl@11C30000/i3c3-bus";
|
|
i3c4_bus = "/pinctrl@11C30000/i3c4-bus";
|
|
i3c5_bus = "/pinctrl@11C30000/i3c5-bus";
|
|
i3c6_bus = "/pinctrl@11C30000/i3c6-bus";
|
|
i3c7_bus = "/pinctrl@11C30000/i3c7-bus";
|
|
i3c8_bus = "/pinctrl@11C30000/i3c8-bus";
|
|
i3c9_bus = "/pinctrl@11C30000/i3c9-bus";
|
|
i3c10_bus = "/pinctrl@11C30000/i3c10-bus";
|
|
i3c11_bus = "/pinctrl@11C30000/i3c11-bus";
|
|
ddi_rst = "/pinctrl@11C30000/ddi-rst";
|
|
pinctrl_8 = "/pinctrl@15320000";
|
|
gpv0 = "/pinctrl@15320000/gpv0";
|
|
dmic_bus_clk0 = "/pinctrl@15320000/dmic-bus-clk0";
|
|
dmic_bus_clk0_idle = "/pinctrl@15320000/dmic-bus-clk0-idle";
|
|
dmic_bus_clk1 = "/pinctrl@15320000/dmic-bus-clk1";
|
|
dmic_bus_clk1_idle = "/pinctrl@15320000/dmic-bus-clk1-idle";
|
|
dmic_bus_clk2 = "/pinctrl@15320000/dmic-bus-clk2";
|
|
dmic_bus_clk2_idle = "/pinctrl@15320000/dmic-bus-clk2-idle";
|
|
dmic_pdm0_bus = "/pinctrl@15320000/dmic-pdm0-bus";
|
|
amic_pdm0_bus = "/pinctrl@15320000/amic-pdm0-bus";
|
|
dmic_pdm0_idle = "/pinctrl@15320000/dmic-pdm0-idle";
|
|
dmic_pdm1_bus = "/pinctrl@15320000/dmic-pdm1-bus";
|
|
amic_pdm1_bus = "/pinctrl@15320000/amic-pdm1-bus";
|
|
dmic_pdm1_idle = "/pinctrl@15320000/dmic-pdm1-idle";
|
|
dmic_pdm2_bus = "/pinctrl@15320000/dmic-pdm2-bus";
|
|
amic_pdm2_bus = "/pinctrl@15320000/amic-pdm2-bus";
|
|
dmic_pdm2_idle = "/pinctrl@15320000/dmic-pdm2-idle";
|
|
sysreg_peric0_usi = "/syscon@10421000";
|
|
sysreg_peric1_usi = "/syscon@10722000";
|
|
sysreg_peric2_1_usi = "/syscon@11C21000";
|
|
sysreg_peric2_2_usi = "/syscon@11C22000";
|
|
sysreg_cmgp_usi = "/syscon@14E22000";
|
|
sysreg_pdma_peri_sel = "/syscon@1A42102C";
|
|
usi_0 = "/usi@11C22000";
|
|
usi_0_spi_i2c = "/usi@11C22004";
|
|
usi_1 = "/usi@11C22008";
|
|
usi_1_spi_i2c = "/usi@11C2200C";
|
|
usi_2 = "/usi@11C22010";
|
|
usi_3 = "/usi@11C22014";
|
|
usi_4 = "/usi@10421000";
|
|
usi_5 = "/usi@11C2117C";
|
|
usi_6 = "/usi@11C21180";
|
|
usi_7 = "/usi@10722030";
|
|
usi_7_spi_i2c = "/usi@10722034";
|
|
usi_8 = "/usi@10722038";
|
|
usi_8_spi_i2c = "/usi@1072203c";
|
|
usi_9 = "/usi@10722040";
|
|
usi_10 = "/usi@10722048";
|
|
usi_11 = "/usi@11C211D3";
|
|
usi_00_cmgp = "/usi@14E22000";
|
|
usi_00_cmgp_spi_i2c = "/usi@14E22070";
|
|
usi_01_cmgp = "/usi@14E22010";
|
|
usi_01_cmgp_spi_i2c = "/usi@14E22074";
|
|
usi_02_cmgp = "/usi@14E22020";
|
|
usi_03_cmgp = "/usi@14E22030";
|
|
usi_04_cmgp = "/usi@14E22040";
|
|
usi_05_cmgp = "/usi@14E22050";
|
|
usi_06_cmgp = "/usi@14E22060";
|
|
hsi2c_0 = "/hsi2c@11D00000";
|
|
hsi2c_1 = "/hsi2c@11D10000";
|
|
hsi2c_2 = "/hsi2c@11D20000";
|
|
hsi2c_3 = "/hsi2c@11D30000";
|
|
hsi2c_4 = "/hsi2c@11D40000";
|
|
hsi2c_5 = "/hsi2c@11D50000";
|
|
hsi2c_6 = "/hsi2c@11D60000";
|
|
hsi2c_7 = "/hsi2c@11D70000";
|
|
hsi2c_8 = "/hsi2c@10500000";
|
|
hsi2c_9 = "/hsi2c@10510000";
|
|
hsi2c_10 = "/hsi2c@11DD0000";
|
|
hsi2c_11 = "/hsi2c@11D80000";
|
|
hsi2c_12 = "/hsi2c@11DE0000";
|
|
hsi2c_13 = "/hsi2c@11D90000";
|
|
hsi2c_14 = "/hsi2c@10900000";
|
|
hsi2c_15 = "/hsi2c@10910000";
|
|
hsi2c_16 = "/hsi2c@10920000";
|
|
hsi2c_17 = "/hsi2c@10930000";
|
|
hsi2c_18 = "/hsi2c@10940000";
|
|
hsi2c_19 = "/hsi2c@10950000";
|
|
hsi2c_20 = "/hsi2c@10960000";
|
|
hsi2c_21 = "/hsi2c@10970000";
|
|
hsi2c_22 = "/hsi2c@11DA0000";
|
|
hsi2c_23 = "/hsi2c@11DB0000";
|
|
hsi2c_24 = "/hsi2c@14F00000";
|
|
hsi2c_25 = "/hsi2c@14F10000";
|
|
hsi2c_26 = "/hsi2c@14F20000";
|
|
hsi2c_27 = "/hsi2c@14F30000";
|
|
hsi2c_28 = "/hsi2c@14F40000";
|
|
hsi2c_29 = "/hsi2c@14F50000";
|
|
hsi2c_30 = "/hsi2c@14F60000";
|
|
hsi2c_31 = "/hsi2c@14F70000";
|
|
hsi2c_32 = "/hsi2c@14F80000";
|
|
hsi2c_33 = "/hsi2c@14F90000";
|
|
hsi2c_34 = "/hsi2c@14FA0000";
|
|
hsi2c_35 = "/hsi2c@14FB0000";
|
|
hsi2c_36 = "/hsi2c@14FC0000";
|
|
hsi2c_37 = "/hsi2c@14FD0000";
|
|
hsi2c_38 = "/hsi2c@14FE0000";
|
|
spi_0 = "/spi@11D00000";
|
|
spi_1 = "/spi@11D20000";
|
|
spi_2 = "/spi@11D40000";
|
|
spi_3 = "/spi@11D60000";
|
|
spi_4 = "/spi@10500000";
|
|
spi_5 = "/spi@11DD0000";
|
|
spi_6 = "/spi@11DE0000";
|
|
spi_7 = "/spi@10900000";
|
|
spi_8 = "/spi@10920000";
|
|
spi_9 = "/spi@10940000";
|
|
spi_10 = "/spi@10960000";
|
|
spi_11 = "/spi@11DA0000";
|
|
spi_12 = "/spi@14F00000";
|
|
spi_13 = "/spi@14F20000";
|
|
spi_14 = "/spi@14F40000";
|
|
spi_15 = "/spi@14F60000";
|
|
spi_16 = "/spi@14F80000";
|
|
spi_17 = "/spi@14FA0000";
|
|
spi_18 = "/spi@14FC0000";
|
|
serial_0 = "/uart@11C40000";
|
|
serial_1 = "/uart@10840000";
|
|
serial_2 = "/uart@11D00000";
|
|
serial_3 = "/uart@11D20000";
|
|
serial_4 = "/uart@11D40000";
|
|
serial_5 = "/uart@11D60000";
|
|
serial_6 = "/uart@10500000";
|
|
serial_7 = "/uart@11DD0000";
|
|
serial_8 = "/uart@11DE0000";
|
|
serial_9 = "/uart@10900000";
|
|
serial_10 = "/uart@10920000";
|
|
serial_11 = "/uart@10940000";
|
|
serial_12 = "/uart@10960000";
|
|
serial_13 = "/uart@11DA0000";
|
|
serial_14 = "/uart@14F00000";
|
|
serial_15 = "/uart@14F20000";
|
|
serial_16 = "/uart@14F40000";
|
|
serial_17 = "/uart@14F60000";
|
|
serial_18 = "/uart@14F80000";
|
|
serial_19 = "/uart@14FA0000";
|
|
serial_20 = "/uart@14FC0000";
|
|
i3c_0 = "/i3c@10460000";
|
|
i3c_1 = "/i3c@10470000";
|
|
i3c_2 = "/i3c@10480000";
|
|
i3c_ois = "/i3c@11DC0000";
|
|
i3c_4 = "/i3c@11C80000";
|
|
i3c_5 = "/i3c@11C90000";
|
|
i3c_6 = "/i3c@11CA0000";
|
|
i3c_7 = "/i3c@11CB0000";
|
|
i3c_8 = "/i3c@11CC0000";
|
|
i3c_9 = "/i3c@11CD0000";
|
|
i3c_10 = "/i3c@11CE0000";
|
|
i3c_11 = "/i3c@11CF0000";
|
|
sgpu = "/sgpu@16E00000";
|
|
acpm_mfd_bus0 = "/acpm_mfd_bus@15960000";
|
|
acpm_mfd_bus1 = "/acpm_mfd_bus@15961000";
|
|
acpm_mfd_bus2 = "/acpm_mfd_bus@15962000";
|
|
abox_gic = "/abox-gic@18cf0000";
|
|
abox = "/abox@18c50000";
|
|
abox_core0 = "/abox@18c50000/abox-core@18c55000";
|
|
abox_firmware_sram0 = "/abox@18c50000/abox-core@18c55000/abox-firmware-sram0";
|
|
abox_firmware_dram0 = "/abox@18c50000/abox-core@18c55000/abox-firmware-dram0";
|
|
abox_core1 = "/abox@18c50000/abox-core@18c55080";
|
|
abox_core2 = "/abox@18c50000/abox-core@18c55100";
|
|
abox_rdma_0 = "/abox@18c50000/abox-rdma@18c51000";
|
|
abox_rdma_1 = "/abox@18c50000/abox-rdma@18c51100";
|
|
abox_rdma_2 = "/abox@18c50000/abox-rdma@18c51200";
|
|
abox_rdma_3 = "/abox@18c50000/abox-rdma@18c51300";
|
|
abox_rdma_4 = "/abox@18c50000/abox-rdma@18c51400";
|
|
abox_rdma_5 = "/abox@18c50000/abox-rdma@18c51500";
|
|
abox_rdma_6 = "/abox@18c50000/abox-rdma@18c51600";
|
|
abox_rdma_7 = "/abox@18c50000/abox-rdma@18c51700";
|
|
abox_rdma_8 = "/abox@18c50000/abox-rdma@18c51800";
|
|
abox_rdma_9 = "/abox@18c50000/abox-rdma@18c51900";
|
|
abox_rdma_10 = "/abox@18c50000/abox-rdma@18c51a00";
|
|
abox_rdma_11 = "/abox@18c50000/abox-rdma@18c51b00";
|
|
abox_wdma_0 = "/abox@18c50000/abox-wdma@18c53000";
|
|
abox_wdma_1 = "/abox@18c50000/abox-wdma@18c53100";
|
|
abox_wdma_2 = "/abox@18c50000/abox-wdma@18c53200";
|
|
abox_wdma_3 = "/abox@18c50000/abox-wdma@18c53300";
|
|
abox_wdma_4 = "/abox@18c50000/abox-wdma@18c53400";
|
|
abox_wdma_5 = "/abox@18c50000/abox-wdma@18c53500";
|
|
abox_wdma_6 = "/abox@18c50000/abox-wdma@18c53600";
|
|
abox_wdma_7 = "/abox@18c50000/abox-wdma@18c53700";
|
|
abox_wdma_8 = "/abox@18c50000/abox-wdma@18c53800";
|
|
abox_wdma_9 = "/abox@18c50000/abox-wdma@18c53900";
|
|
abox_wdma_10 = "/abox@18c50000/abox-wdma@18c53a00";
|
|
abox_wdma_11 = "/abox@18c50000/abox-wdma@18c53b00";
|
|
abox_dual_0 = "/abox@18c50000/abox-dual@18c53080";
|
|
abox_dual_1 = "/abox@18c50000/abox-dual@18c53180";
|
|
abox_dual_2 = "/abox@18c50000/abox-dual@18c53280";
|
|
abox_dual_3 = "/abox@18c50000/abox-dual@18c53380";
|
|
abox_dual_4 = "/abox@18c50000/abox-dual@18c53480";
|
|
abox_dual_5 = "/abox@18c50000/abox-dual@18c53580";
|
|
abox_dual_6 = "/abox@18c50000/abox-dual@18c53680";
|
|
abox_dual_7 = "/abox@18c50000/abox-dual@18c53780";
|
|
abox_dual_8 = "/abox@18c50000/abox-dual@18c53880";
|
|
abox_dual_9 = "/abox@18c50000/abox-dual@18c53980";
|
|
abox_dual_10 = "/abox@18c50000/abox-dual@18c53a80";
|
|
abox_dual_11 = "/abox@18c50000/abox-dual@18c53b80";
|
|
abox_ddma_0 = "/abox@18c50000/abox-ddma@18c56000";
|
|
abox_ddma_1 = "/abox@18c50000/abox-ddma@18c56100";
|
|
abox_ddma_2 = "/abox@18c50000/abox-ddma@18c56200";
|
|
abox_ddma_3 = "/abox@18c50000/abox-ddma@18c56300";
|
|
abox_ddma_4 = "/abox@18c50000/abox-ddma@18c56400";
|
|
abox_ddma_5 = "/abox@18c50000/abox-ddma@18c56500";
|
|
abox_uaif_0 = "/abox@18c50000/abox-uaif@18c50c00";
|
|
abox_uaif_1 = "/abox@18c50000/abox-uaif@18c50c20";
|
|
abox_uaif_2 = "/abox@18c50000/abox-uaif@18c50c40";
|
|
abox_uaif_3 = "/abox@18c50000/abox-uaif@18c50c60";
|
|
abox_uaif_4 = "/abox@18c50000/abox-uaif@18c50c80";
|
|
abox_uaif_5 = "/abox@18c50000/abox-uaif@18c50ca0";
|
|
abox_uaif_6 = "/abox@18c50000/abox-uaif@18c50cc0";
|
|
abox_dsif = "/abox@18c50000/abox-dsif@18c50de0";
|
|
abox_udma_rd_0 = "/abox@18c50000/abox-udma-rd@18c5c100";
|
|
abox_udma_rd_1 = "/abox@18c50000/abox-udma-rd@18c5c200";
|
|
abox_udma_wr_0 = "/abox@18c50000/abox-udma-wr@18c5c700";
|
|
abox_udma_wr_1 = "/abox@18c50000/abox-udma-wr@18c5c800";
|
|
abox_udma_wr_dual_0 = "/abox@18c50000/abox-udma-wr-dual@18c5c780";
|
|
abox_udma_wr_dual_1 = "/abox@18c50000/abox-udma-wr-dual@18c5c880";
|
|
abox_udma_wr_debug_0 = "/abox@18c50000/abox-udma-wr-debug@18c5cd00";
|
|
abox_effect = "/abox@18c50000/abox-effect@2139000";
|
|
abox_debug = "/abox@18c50000/abox-debug@0";
|
|
abox_vss = "/abox@18c50000/abox-vss@0";
|
|
abox_tplg = "/abox@18c50000/abox-tplg@0";
|
|
abox_pci = "/abox@18c50000/abox-pci@0";
|
|
mailbox_vts = "/mailbox@0x153e0000";
|
|
vts = "/vts@0x15310000";
|
|
vts_dma0 = "/vts@0x15310000/vts_dma@0";
|
|
vts_dma1 = "/vts@0x15310000/vts_dma@1";
|
|
vts_s_lif = "/vts_s_lif@0x18f50000";
|
|
displayport_adma = "/dp_dma";
|
|
dp_dma0 = "/dp_dma/dp_dma@0";
|
|
dp_dma1 = "/dp_dma/dp_dma@1";
|
|
cpu0 = "/cpus/cpu@0000";
|
|
cpu1 = "/cpus/cpu@0100";
|
|
cpu2 = "/cpus/cpu@0200";
|
|
cpu3 = "/cpus/cpu@0300";
|
|
cpu4 = "/cpus/cpu@0400";
|
|
cpu5 = "/cpus/cpu@0500";
|
|
cpu6 = "/cpus/cpu@0600";
|
|
cpu7 = "/cpus/cpu@0700";
|
|
KLEIN_CPU_SLEEP = "/cpus/idle-states/klein-cpu-sleep";
|
|
MATTERHORN_CPU_SLEEP = "/cpus/idle-states/matterhorn-cpu-sleep";
|
|
MONTBLANC_CPU_SLEEP = "/cpus/idle-states/montblanc-cpu-sleep";
|
|
cpufreq_domain0 = "/exynos-acme/domain@0";
|
|
cpufreq_domain1 = "/exynos-acme/domain@1";
|
|
cpufreq_domain2 = "/exynos-acme/domain@2";
|
|
lit_dsu_perf = "/dm-tables/dm-table@0000";
|
|
lit_dsu_perf_game = "/dm-tables/dm-table@0010";
|
|
med_dsu_perf = "/dm-tables/dm-table@0001";
|
|
med_dsu_perf_game = "/dm-tables/dm-table@0011";
|
|
big_dsu_perf = "/dm-tables/dm-table@0002";
|
|
big_dsu_perf_game = "/dm-tables/dm-table@0012";
|
|
lit_mif_perf = "/dm-tables/dm-table@0003";
|
|
med_mif_perf = "/dm-tables/dm-table@0004";
|
|
big_mif_perf = "/dm-tables/dm-table@0005";
|
|
dsu_mif_skew = "/dm-tables/dm-table@0006";
|
|
afm_domain0 = "/exynos-afm/domain@0";
|
|
afm_domain1 = "/exynos-afm/domain@1";
|
|
afm_domain2 = "/exynos-afm/domain@2";
|
|
dsim_modes = "/dsim_modes";
|
|
drmdpp0 = "/drmdpp@0x1AD00000";
|
|
drmdpp1 = "/drmdpp@0x1AD01000";
|
|
drmdpp2 = "/drmdpp@0x1AD02000";
|
|
drmdpp3 = "/drmdpp@0x1AD03000";
|
|
drmdpp4 = "/drmdpp@0x1AD04000";
|
|
drmdpp5 = "/drmdpp@0x1AD05000";
|
|
drmdpp6 = "/drmdpp@0x1AD06000";
|
|
drmdpp7 = "/drmdpp@0x1AD07000";
|
|
drmdpp8 = "/drmdpp@0x1AF00000";
|
|
drmdpp9 = "/drmdpp@0x1AF01000";
|
|
drmdpp10 = "/drmdpp@0x1AF02000";
|
|
drmdpp11 = "/drmdpp@0x1AF03000";
|
|
drmdpp12 = "/drmdpp@0x1AF04000";
|
|
drmdpp13 = "/drmdpp@0x1AF05000";
|
|
drmdpp14 = "/drmdpp@0x1AF06000";
|
|
drmdpp15 = "/drmdpp@0x1AEB8000";
|
|
drmdpp16 = "/drmdpp@0x1AD08000";
|
|
drmdpp17 = "/drmdpp@0x1AF08000";
|
|
dma_dsimfc_0 = "/fcmd@0x19CBC000";
|
|
dma_dsimfc_1 = "/fcmd@0x19CBD000";
|
|
dma_dsimfc_2 = "/fcmd@0x1AEBC000";
|
|
disp_ss = "/disp_ss@0x19E20000";
|
|
mipi_phy_dsim0_m4m4 = "/dphy_m4m4_dsim0@0x15860000";
|
|
drmdsim_0 = "/drmdsim@0x19EC0000";
|
|
drmdp = "/drmdp@0x10A80000";
|
|
drmdecon0 = "/drmdecon@0x19F00000";
|
|
drmdecon1 = "/drmdecon@0x19F01000";
|
|
drmdecon2 = "/drmdecon@0x19F02000";
|
|
drmdecon3 = "/drmdecon@0x19F03000";
|
|
sysreg_hsi0 = "/sysreg_hsi0@10A20000";
|
|
udc = "/usb@10B00000";
|
|
usbdrd_dwc3 = "/usb@10B00000/dwc3";
|
|
usbdrd_phy0 = "/phy@10AA0000";
|
|
pcie_0 = "/pcie@113B0000";
|
|
pcie_1 = "/pcie@11320000";
|
|
sysmmu_pcie = "/sysmmu@11280000";
|
|
sysreg_ufs = "/sysreg_ufs@11020000";
|
|
ufs = "/ufs@0x11100000";
|
|
dpm = "/dpm";
|
|
dss = "/dss";
|
|
s2d = "/exynos_adv_tracer_s2d";
|
|
itmon = "/exynos-itmon";
|
|
itmon_dbgc = "/exynos-itmon/dbgc";
|
|
ehld_dbgc = "/exynos-ehld/dbgc";
|
|
etf0 = "/etf0@4004000";
|
|
etf0_in = "/etf0@4004000/in-ports/port/endpoint";
|
|
etf0_out = "/etf0@4004000/out-ports/port/endpoint";
|
|
etf1 = "/etf1@4005000";
|
|
etf1_in = "/etf1@4005000/in-ports/port/endpoint";
|
|
etf1_out = "/etf1@4005000/out-ports/port/endpoint";
|
|
etr = "/etr@400a000";
|
|
etr_in = "/etr@400a000/in-ports/port/endpoint";
|
|
stm0_out = "/stm0@400b000/out-ports/port/endpoint";
|
|
funnel0 = "/funnel0@4007000";
|
|
funnel0_out0 = "/funnel0@4007000/out-ports/port/endpoint";
|
|
funnel1 = "/funnel1@4008000";
|
|
funnel1_out0 = "/funnel1@4008000/out-ports/port/endpoint";
|
|
funnel1_in7 = "/funnel1@4008000/in-ports/port@7/endpoint";
|
|
funnelm = "/funnelm@4009000";
|
|
funnelm_out0 = "/funnelm@4009000/out-ports/port/endpoint";
|
|
funnelm_in0 = "/funnelm@4009000/in-ports/port@0/endpoint";
|
|
funnelm_in1 = "/funnelm@4009000/in-ports/port@1/endpoint";
|
|
exynos_dm = "/exynos-dm@17000000";
|
|
devfreq_0 = "/exynos_devfreq/devfreq_mif@17000010";
|
|
devfreq_1 = "/exynos_devfreq/devfreq_int@17000020";
|
|
devfreq_2 = "/exynos_devfreq/devfreq_intcam@17000030";
|
|
devfreq_3 = "/exynos_devfreq/devfreq_disp@17000040";
|
|
devfreq_4 = "/exynos_devfreq/devfreq_cam@17000050";
|
|
devfreq_5 = "/exynos_devfreq/devfreq_npu@17000060";
|
|
devfreq_6 = "/exynos_devfreq/devfreq_aud@17000070";
|
|
devfreq_7 = "/exynos_devfreq/devfreq_dnc@17000080";
|
|
devfreq_8 = "/exynos_devfreq/devfreq_mfc0@17000090";
|
|
devfreq_9 = "/exynos_devfreq/devfreq_csis@170000A0";
|
|
devfreq_10 = "/exynos_devfreq/devfreq_isp@170000B0";
|
|
devfreq_11 = "/exynos_devfreq/devfreq_mfc1@170000C0";
|
|
devfreq_12 = "/exynos_devfreq/devfreq_dsp@170000D0";
|
|
devfreq_13 = "/exynos_devfreq/devfreq_alive@170000E0";
|
|
devfreq_14 = "/exynos_devfreq/devfreq_vts@170000F0";
|
|
devfreq_15 = "/exynos_devfreq/devfreq_hsi0@17000100";
|
|
devfreq_16 = "/exynos_devfreq/devfreq_ufd@17000110";
|
|
tmuctrl_0 = "/BIG@10070000";
|
|
tmuctrl_1 = "/MID@10070000";
|
|
tmuctrl_2 = "/LITTLE@10070000";
|
|
tmuctrl_3 = "/G3D@10080000";
|
|
tmuctrl_4 = "/ISP@10080000";
|
|
tmuctrl_5 = "/NPU@10080000";
|
|
tmuctrl_6 = "/CP@10080000";
|
|
exynos_isp_thermal = "/exynos_isp_thermal";
|
|
big_thermal = "/thermal-zones/BIG";
|
|
big_cold = "/thermal-zones/BIG/trips/big-cold";
|
|
big_switch_on = "/thermal-zones/BIG/trips/big-switch-on";
|
|
big_control_temp = "/thermal-zones/BIG/trips/big-control-temp";
|
|
big_alert0 = "/thermal-zones/BIG/trips/big-alert0";
|
|
big_alert1 = "/thermal-zones/BIG/trips/big-alert1";
|
|
big_alert2 = "/thermal-zones/BIG/trips/big-alert2";
|
|
big_alert3 = "/thermal-zones/BIG/trips/big-alert3";
|
|
big_hot = "/thermal-zones/BIG/trips/big-hot";
|
|
mid_thermal = "/thermal-zones/MID";
|
|
mid_cold = "/thermal-zones/MID/trips/mid-cold";
|
|
mid_switch_on = "/thermal-zones/MID/trips/mid-switch-on";
|
|
mid_control_temp = "/thermal-zones/MID/trips/mid-control-temp";
|
|
mid_alert0 = "/thermal-zones/MID/trips/mid-alert0";
|
|
mid_alert1 = "/thermal-zones/MID/trips/mid-alert1";
|
|
mid_alert2 = "/thermal-zones/MID/trips/mid-alert2";
|
|
mid_alert3 = "/thermal-zones/MID/trips/mid-alert3";
|
|
mid_hot = "/thermal-zones/MID/trips/mid-hot";
|
|
little_thermal = "/thermal-zones/LITTLE";
|
|
little_cold = "/thermal-zones/LITTLE/trips/little-cold";
|
|
little_switch_on = "/thermal-zones/LITTLE/trips/little-switch-on";
|
|
little_control_temp = "/thermal-zones/LITTLE/trips/little-control-temp";
|
|
little_alert0 = "/thermal-zones/LITTLE/trips/little-alert0";
|
|
little_alert1 = "/thermal-zones/LITTLE/trips/little-alert1";
|
|
little_alert2 = "/thermal-zones/LITTLE/trips/little-alert2";
|
|
little_alert3 = "/thermal-zones/LITTLE/trips/little-alert3";
|
|
little_hot = "/thermal-zones/LITTLE/trips/little-hot";
|
|
gpu_thermal = "/thermal-zones/G3D";
|
|
gpu_cold = "/thermal-zones/G3D/trips/gpu-cold";
|
|
gpu_switch_on = "/thermal-zones/G3D/trips/gpu-switch-on";
|
|
gpu_control_temp = "/thermal-zones/G3D/trips/gpu-control-temp";
|
|
gpu_alert0 = "/thermal-zones/G3D/trips/gpu-alert0";
|
|
gpu_alert1 = "/thermal-zones/G3D/trips/gpu-alert1";
|
|
gpu_alert2 = "/thermal-zones/G3D/trips/gpu-alert2";
|
|
gpu_alert3 = "/thermal-zones/G3D/trips/gpu-alert3";
|
|
gpu_hot = "/thermal-zones/G3D/trips/gpu-hot";
|
|
isp_thermal = "/thermal-zones/ISP";
|
|
isp_alert0 = "/thermal-zones/ISP/trips/isp-alert0";
|
|
isp_alert1 = "/thermal-zones/ISP/trips/isp-alert1";
|
|
isp_alert2 = "/thermal-zones/ISP/trips/isp-alert2";
|
|
isp_alert3 = "/thermal-zones/ISP/trips/isp-alert3";
|
|
isp_alert4 = "/thermal-zones/ISP/trips/isp-alert4";
|
|
isp_alert5 = "/thermal-zones/ISP/trips/isp-alert5";
|
|
isp_alert6 = "/thermal-zones/ISP/trips/isp-alert6";
|
|
isp_hot = "/thermal-zones/ISP/trips/isp-hot";
|
|
npu_thermal = "/thermal-zones/NPU";
|
|
npu_alert0 = "/thermal-zones/NPU/trips/npu-alert0";
|
|
npu_alert1 = "/thermal-zones/NPU/trips/npu-alert1";
|
|
npu_alert2 = "/thermal-zones/NPU/trips/npu-alert2";
|
|
npu_alert3 = "/thermal-zones/NPU/trips/npu-alert3";
|
|
npu_alert4 = "/thermal-zones/NPU/trips/npu-alert4";
|
|
npu_alert5 = "/thermal-zones/NPU/trips/npu-alert5";
|
|
npu_alert6 = "/thermal-zones/NPU/trips/npu-alert6";
|
|
npu_hot = "/thermal-zones/NPU/trips/npu-hot";
|
|
cp_thermal = "/thermal-zones/CP";
|
|
smc_info = "/mcinfo@1c030000";
|
|
ssp = "/ssp";
|
|
pd_aud = "/pd_aud@15861880";
|
|
pd_nocl1c = "/pd_nocl1c@15861a80";
|
|
pd_brp = "/pd_brp@15861900";
|
|
pd_csis = "/pd_csis@15861f00";
|
|
pd_cstat = "/pd_cstat@15861f80";
|
|
pd_allcsis = "/pd_allcsis@15862000";
|
|
pd_dpub = "/pd_dpub@15862080";
|
|
pd_dpuf = "/pd_dpuf@15862100";
|
|
pd_g3dcore = "/pd_g3dcore@15862280";
|
|
pd_strong = "/pd_strong@15862300";
|
|
pd_dnc = "/pd_dnc@15862e80";
|
|
pd_hsi0 = "/pd_hsi0@15862500";
|
|
pd_hsi1 = "/pd_hsi1@15862580";
|
|
pd_lme = "/pd_lme@15862600";
|
|
pd_m2m = "/pd_m2m@15862680";
|
|
pd_mcsc = "/pd_mcsc@15862780";
|
|
pd_mfc0 = "/pd_mfc0@15862800";
|
|
pd_mfc1 = "/pd_mfc1@15862880";
|
|
pd_vts = "/pd_vts@15863080";
|
|
pd_yuvp = "/pd_yuvp@15863100";
|
|
pd_sdma = "/pd_sdma@15863180";
|
|
pd_ufd = "/pd_ufd@15863300";
|
|
pd_gnpu0 = "/pd_gnpu0@15862380";
|
|
pd_gnpu1 = "/pd_gnpu1@15862400";
|
|
pd_dsp0 = "/pd_dsp0@15862f00";
|
|
boot_set = "/boot_set";
|
|
set0 = "/set@0000";
|
|
set0_1 = "/set@0001";
|
|
set0_2 = "/set@0002";
|
|
set1 = "/set@0100";
|
|
set1_1 = "/set@0101";
|
|
set1_2 = "/set@0102";
|
|
set2 = "/set@0200";
|
|
set2_1 = "/set@0201";
|
|
set2_2 = "/set@0202";
|
|
set3 = "/set@0300";
|
|
set3_1 = "/set@0301";
|
|
set3_2 = "/set@0302";
|
|
set4 = "/set@0400";
|
|
set4_1 = "/set@0401";
|
|
set4_2 = "/set@0402";
|
|
set5 = "/set@0500";
|
|
set5_1 = "/set@0501";
|
|
set5_2 = "/set@0502";
|
|
set6 = "/set@0600";
|
|
set6_1 = "/set@0601";
|
|
set6_2 = "/set@0602";
|
|
mfc = "/mfc";
|
|
mfc_core0 = "/mfc/MFC-0";
|
|
mfc_core1 = "/mfc/MFC-1";
|
|
smfc_0 = "/smfc@18940000";
|
|
smfc_1 = "/smfc@18950000";
|
|
scaler_0 = "/scaler@18960000";
|
|
jsqz = "/jsqz@18980000";
|
|
mcfrc = "/mcfrc@0x18A50000";
|
|
tsmux = "/tsmux@186E0000";
|
|
repeater = "/repeater@0";
|
|
exynos_is = "/exynos_is@18440000";
|
|
camerapp_gdc = "/gdc@17700000";
|
|
camerapp_votf0 = "/votf0";
|
|
camerapp_votf1 = "/votf1";
|
|
camerapp_votf2 = "/votf2";
|
|
is_iommu_group_module = "/is_iommu_group_module";
|
|
is_iommu_group0 = "/is_iommu_group0";
|
|
is_iommu_group1 = "/is_iommu_group1";
|
|
is_iommu_group2 = "/is_iommu_group2";
|
|
is_iommu_group3 = "/is_iommu_group3";
|
|
camif_wdma0 = "/camif-wdma-module@17140000";
|
|
camif_wdma0_0 = "/camif-wdma@17141000";
|
|
camif_wdma0_1 = "/camif-wdma@17142000";
|
|
camif_wdma0_2 = "/camif-wdma@17143000";
|
|
camif_wdma0_3 = "/camif-wdma@17144000";
|
|
camif_wdma0_4 = "/camif-wdma@17145000";
|
|
camif_mcb = "/camif-mcb@17151000";
|
|
camif_ebuf = "/camif-ebuf@17152000";
|
|
camif_bns = "/camif-bns@17153000";
|
|
sysreg_csis_reset = "/system-controller@17020500";
|
|
mipi_phy_csis0_m0s4s4s4s4s4s4_s22 = "/dcphy_m0s4s4s4s4s4s4_s22_csi0@170F1300";
|
|
mipi_phy_csis1_m0s4s4s4s4s4s4_s22 = "/dcphy_m0s4s4s4s4s4s4_s22_csi1@170F1B00";
|
|
mipi_phy_csis2_m0s4s4s4s4s4s4_s22 = "/dcphy_m0s4s4s4s4s4s4_s22_csi2@170F2300";
|
|
mipi_phy_csis3_m0s4s4s4s4s4s4_s22 = "/dcphy_m0s4s4s4s4s4s4_s22_csi3@170F2B00";
|
|
mipi_phy_csis4_m0s4s4s4s4s4s4_s22 = "/dphy_m0s4s4s4s4s4s4_s22_csi4@170F3300";
|
|
mipi_phy_csis5_m0s4s4s4s4s4s4_s22 = "/dphy_m0s4s4s4s4s4s4_s22_csi5@170F3B00";
|
|
mipi_phy_csis6_m0s4s4s4s4s4s4_s22 = "/dphy_m0s4s4s4s4s4s4_s22_csi5@170F3A00";
|
|
is_sensor0 = "/is_sensor0@17030000";
|
|
is_sensor1 = "/is_sensor1@17040000";
|
|
is_sensor2 = "/is_sensor2@17050000";
|
|
is_sensor3 = "/is_sensor3@17060000";
|
|
is_sensor4 = "/is_sensor4@17070000";
|
|
is_sensor5 = "/is_sensor5@17080000";
|
|
lic_lut_origin = "/lic-lut-origin";
|
|
sensor_paf_pdp_0 = "/sensor-paf-pdp@17100000";
|
|
sensor_paf_pdp_1 = "/sensor-paf-pdp@17110000";
|
|
sensor_paf_pdp_2 = "/sensor-paf-pdp@17120000";
|
|
sensor_paf_pdp_3 = "/sensor-paf-pdp@17130000";
|
|
dphy_setfile = "/dphy-setfile@00";
|
|
cphy_setfile = "/cphy-setfile@00";
|
|
cphy_univ_2la_setfile = "/cphy-univ-2la-setfile@00";
|
|
npu = "/npu_exynos";
|
|
hwdevdnc = "/hwdev_dnc";
|
|
hwdevnpu = "/hwdev_npu";
|
|
hwdevdsp = "/hwdev_dsp";
|
|
hwdevcl1 = "/hwdev_cl1";
|
|
hwdevmif = "/hwdev_mif";
|
|
hwdevint = "/hwdev_int";
|
|
chosen = "/chosen";
|
|
gic = "/interrupt-controller@10200000";
|
|
gic_vh = "/gic_vh";
|
|
clock = "/clock-controller@0x1A320000";
|
|
memlogger = "/samsung,memlogger";
|
|
memlogger_policy = "/samsung,memlog_policy";
|
|
ext_26m = "/ext_26m";
|
|
ext_200m = "/ext_200m";
|
|
pmu_system_controller = "/system-controller@15860000";
|
|
spmi_controller = "/system-controller@15960000";
|
|
mct_alive_map = "/mct_alive@15890000/mct-alive-map";
|
|
iommu_group_dpu = "/iommu_group_dpu";
|
|
iommu_group_mfc = "/iommu_group_mfc";
|
|
iommu_group_is = "/iommu_group_is";
|
|
iommu_group_is_1 = "/iommu_group_is_1";
|
|
iommu_group_is_2 = "/iommu_group_is_2";
|
|
iommu_group_is_3 = "/iommu_group_is_3";
|
|
iommu_group_mscl_smfc = "/iommu_group_mscl_smfc";
|
|
iommu_group_aud = "/iommu_group_aud";
|
|
iommu_group_npu = "/iommu_group_npu";
|
|
iommu_group_vpc = "/iommu_group_vpc";
|
|
iommu_group_camerapp_gdc = "/iommu_group_camerapp_gdc";
|
|
pdma0 = "/amba/pdma0@1A4E0000";
|
|
sec_pwm = "/pwm@11C50000";
|
|
cpu_domain0 = "/exynos-cpu-profiler/domain@0";
|
|
cpu_domain1 = "/exynos-cpu-profiler/domain@1";
|
|
cpu_domain2 = "/exynos-cpu-profiler/domain@2";
|
|
contexthub_0 = "/contexthub";
|
|
};
|
|
|
|
__fixups__ {
|
|
i3c3_ois_bus = "/i3c@11DC0000:pinctrl-0:0";
|
|
abox_pci_rmem = "/abox@18c50000/abox-pci@0:memory-region:0";
|
|
camera_bin = "/exynos_is@18440000:memory-region:0";
|
|
};
|
|
|
|
__local_fixups__ {
|
|
interrupt-parent = <0x00>;
|
|
|
|
sysmmu@0x18D50000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x17430000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x17530000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x17570000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x17170000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x171A0000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x171D0000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x18540000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x16040000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x16070000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x160A0000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x160D0000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x16100000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x1AC40000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x1AC50000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x1AE40000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x1AE50000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x176A0000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x18A00000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x15C70000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x15CA0000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x15CD0000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x15D00000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x15D30000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x18670000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x186A0000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x18870000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x188A0000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x18070000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@0x180A0000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
crypto_dma_heap {
|
|
memory-region = <0x00>;
|
|
};
|
|
|
|
video_stream_dma_heap {
|
|
memory-region = <0x00>;
|
|
};
|
|
|
|
video_frame_dma_heap {
|
|
memory-region = <0x00>;
|
|
};
|
|
|
|
video_scaler_dma_heap {
|
|
memory-region = <0x00>;
|
|
};
|
|
|
|
gpu_buffer_dma_heap {
|
|
memory-region = <0x00>;
|
|
};
|
|
|
|
secure_camera_dma_heap {
|
|
memory-region = <0x00>;
|
|
};
|
|
|
|
tui_dma_heap {
|
|
memory-region = <0x00>;
|
|
};
|
|
|
|
secure_dsp_dma_heap {
|
|
memory-region = <0x00>;
|
|
};
|
|
|
|
rbin_dma_heap {
|
|
memory-region = <0x00>;
|
|
};
|
|
|
|
pinctrl@15850000 {
|
|
|
|
gpa0 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpa1 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpa2 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpa3 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpa4 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
};
|
|
|
|
pinctrl@14E30000 {
|
|
|
|
gpm0 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm1 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm2 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm3 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm4 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm5 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm6 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm7 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm8 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm9 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm10 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm11 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm12 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm13 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm14 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm15 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm16 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm17 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm20 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm21 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm22 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm23 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
|
|
gpm24 {
|
|
interrupt-parent = <0x00>;
|
|
};
|
|
};
|
|
|
|
hsi2c@11D00000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@11D10000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@11D20000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@11D30000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@11D40000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@11D50000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@11D60000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@11D70000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@10500000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@10510000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@11DD0000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@11D80000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@11DE0000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@11D90000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@10900000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@10910000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@10920000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@10930000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@10940000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@10950000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@10960000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@10970000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@11DA0000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@11DB0000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@14F00000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@14F10000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@14F20000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@14F30000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@14F40000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@14F50000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@14F60000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@14F70000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@14F80000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@14F90000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@14FA0000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@14FB0000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@14FC0000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@14FD0000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
hsi2c@14FE0000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
gpio_scl = <0x00>;
|
|
gpio_sda = <0x00>;
|
|
};
|
|
|
|
spi@11D00000 {
|
|
dmas = <0x00 0x08>;
|
|
samsung,dma-phandle = <0x00>;
|
|
samsung,usi-phandle = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
spi@11D20000 {
|
|
dmas = <0x00 0x08>;
|
|
samsung,dma-phandle = <0x00>;
|
|
samsung,usi-phandle = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
spi@11D40000 {
|
|
dmas = <0x00 0x08>;
|
|
samsung,dma-phandle = <0x00>;
|
|
samsung,usi-phandle = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
spi@11D60000 {
|
|
dmas = <0x00 0x08>;
|
|
samsung,dma-phandle = <0x00>;
|
|
samsung,usi-phandle = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
spi@10500000 {
|
|
dmas = <0x00 0x08>;
|
|
samsung,dma-phandle = <0x00>;
|
|
samsung,usi-phandle = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
spi@11DD0000 {
|
|
dmas = <0x00 0x08>;
|
|
samsung,dma-phandle = <0x00>;
|
|
samsung,usi-phandle = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
spi@11DE0000 {
|
|
dmas = <0x00 0x08>;
|
|
samsung,dma-phandle = <0x00>;
|
|
samsung,usi-phandle = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
spi@10900000 {
|
|
dmas = <0x00 0x08>;
|
|
samsung,dma-phandle = <0x00>;
|
|
samsung,usi-phandle = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
spi@10920000 {
|
|
dmas = <0x00 0x08>;
|
|
samsung,dma-phandle = <0x00>;
|
|
samsung,usi-phandle = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
spi@10940000 {
|
|
dmas = <0x00 0x08>;
|
|
samsung,dma-phandle = <0x00>;
|
|
samsung,usi-phandle = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
spi@10960000 {
|
|
dmas = <0x00 0x08>;
|
|
samsung,dma-phandle = <0x00>;
|
|
samsung,usi-phandle = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
spi@11DA0000 {
|
|
dmas = <0x00 0x08>;
|
|
samsung,dma-phandle = <0x00>;
|
|
samsung,usi-phandle = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
spi@14F00000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
spi@14F20000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
spi@14F40000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
spi@14F60000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
spi@14F80000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
spi@14FA0000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
spi@14FC0000 {
|
|
samsung,usi-phandle = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
uart@11C40000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
};
|
|
|
|
uart@10840000 {
|
|
pinctrl-0 = <0x00>;
|
|
pinctrl-1 = <0x00 0x04>;
|
|
pinctrl-2 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
};
|
|
|
|
uart@11D00000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,usi-phandle = <0x00>;
|
|
};
|
|
|
|
uart@11D20000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,usi-phandle = <0x00>;
|
|
};
|
|
|
|
uart@11D40000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,usi-phandle = <0x00>;
|
|
};
|
|
|
|
uart@11D60000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,usi-phandle = <0x00>;
|
|
};
|
|
|
|
uart@10500000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,usi-phandle = <0x00>;
|
|
};
|
|
|
|
uart@11DD0000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,usi-phandle = <0x00>;
|
|
};
|
|
|
|
uart@11DE0000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,usi-phandle = <0x00>;
|
|
};
|
|
|
|
uart@10900000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,usi-phandle = <0x00>;
|
|
};
|
|
|
|
uart@10920000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,usi-phandle = <0x00>;
|
|
};
|
|
|
|
uart@10940000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,usi-phandle = <0x00>;
|
|
};
|
|
|
|
uart@10960000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,usi-phandle = <0x00>;
|
|
};
|
|
|
|
uart@11DA0000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,usi-phandle = <0x00>;
|
|
};
|
|
|
|
uart@14F00000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,usi-phandle = <0x00>;
|
|
};
|
|
|
|
uart@14F20000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,usi-phandle = <0x00>;
|
|
};
|
|
|
|
uart@14F40000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,usi-phandle = <0x00>;
|
|
};
|
|
|
|
uart@14F60000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,usi-phandle = <0x00>;
|
|
};
|
|
|
|
uart@14F80000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,usi-phandle = <0x00>;
|
|
};
|
|
|
|
uart@14FA0000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,usi-phandle = <0x00>;
|
|
};
|
|
|
|
uart@14FC0000 {
|
|
pinctrl-0 = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,usi-phandle = <0x00>;
|
|
};
|
|
|
|
i3c@10460000 {
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
i3c@10470000 {
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
i3c@10480000 {
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
i3c@11DC0000 {
|
|
clocks = <0x00 0x08>;
|
|
};
|
|
|
|
i3c@11C80000 {
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
i3c@11C90000 {
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
i3c@11CA0000 {
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
i3c@11CB0000 {
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
i3c@11CC0000 {
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
i3c@11CD0000 {
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
i3c@11CE0000 {
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
i3c@11CF0000 {
|
|
clocks = <0x00 0x08>;
|
|
pinctrl-0 = <0x00>;
|
|
};
|
|
|
|
sgpu@16E00000 {
|
|
memory-region = <0x00>;
|
|
power-domains = <0x00>;
|
|
gpu_tmu = <0x00>;
|
|
};
|
|
|
|
abox@18c50000 {
|
|
iommus = <0x00>;
|
|
memory-region = <0x00>;
|
|
samsung,iommu-group = <0x00>;
|
|
power-domains = <0x00>;
|
|
clocks = <0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38>;
|
|
samsung,abox-gic = <0x00>;
|
|
|
|
abox-rdma@18c51100 {
|
|
memory-region = <0x00>;
|
|
};
|
|
|
|
abox-uaif@18c50c00 {
|
|
clocks = <0x00 0x08 0x10>;
|
|
pinctrl-0 = <0x00>;
|
|
pinctrl-1 = <0x00>;
|
|
};
|
|
|
|
abox-uaif@18c50c20 {
|
|
clocks = <0x00 0x08 0x10>;
|
|
pinctrl-0 = <0x00>;
|
|
pinctrl-1 = <0x00>;
|
|
};
|
|
|
|
abox-uaif@18c50c40 {
|
|
clocks = <0x00 0x08 0x10>;
|
|
pinctrl-0 = <0x00>;
|
|
pinctrl-1 = <0x00>;
|
|
};
|
|
|
|
abox-uaif@18c50c60 {
|
|
clocks = <0x00 0x08 0x10>;
|
|
pinctrl-0 = <0x00>;
|
|
pinctrl-1 = <0x00>;
|
|
};
|
|
|
|
abox-uaif@18c50c80 {
|
|
clocks = <0x00 0x08 0x10>;
|
|
};
|
|
|
|
abox-uaif@18c50ca0 {
|
|
clocks = <0x00 0x08 0x10>;
|
|
};
|
|
|
|
abox-uaif@18c50cc0 {
|
|
clocks = <0x00 0x08 0x10>;
|
|
};
|
|
|
|
abox-dsif@18c50de0 {
|
|
clocks = <0x00 0x08>;
|
|
};
|
|
|
|
abox-debug@0 {
|
|
memory-region = <0x00 0x04>;
|
|
};
|
|
|
|
abox-pci@0 {
|
|
pinctrl-0 = <0x00>;
|
|
pinctrl-1 = <0x00>;
|
|
};
|
|
};
|
|
|
|
vts@0x15310000 {
|
|
pinctrl-0 = <0x00 0x04>;
|
|
pinctrl-1 = <0x00 0x04>;
|
|
pinctrl-2 = <0x00 0x04>;
|
|
pinctrl-3 = <0x00 0x04>;
|
|
pinctrl-4 = <0x00 0x04>;
|
|
pinctrl-5 = <0x00 0x04>;
|
|
pinctrl-6 = <0x00 0x04>;
|
|
pinctrl-7 = <0x00 0x04>;
|
|
pinctrl-8 = <0x00 0x04>;
|
|
power-domains = <0x00>;
|
|
clocks = <0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48>;
|
|
mailbox = <0x00>;
|
|
interrupt-parent = <0x00>;
|
|
|
|
vts_dma@0 {
|
|
vts = <0x00>;
|
|
};
|
|
|
|
vts_dma@1 {
|
|
vts = <0x00>;
|
|
};
|
|
};
|
|
|
|
vts_s_lif@0x18f50000 {
|
|
power-domains = <0x00>;
|
|
samsung,slif-vts = <0x00>;
|
|
clocks = <0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38>;
|
|
};
|
|
|
|
dp_dma {
|
|
memory-region = <0x00>;
|
|
|
|
dp_dma@0 {
|
|
dmas = <0x00>;
|
|
};
|
|
|
|
dp_dma@1 {
|
|
dmas = <0x00>;
|
|
};
|
|
};
|
|
|
|
cpus {
|
|
|
|
cpu-map {
|
|
|
|
cluster0 {
|
|
|
|
core0 {
|
|
cpu = <0x00>;
|
|
};
|
|
|
|
core1 {
|
|
cpu = <0x00>;
|
|
};
|
|
|
|
core2 {
|
|
cpu = <0x00>;
|
|
};
|
|
|
|
core3 {
|
|
cpu = <0x00>;
|
|
};
|
|
};
|
|
|
|
cluster1 {
|
|
|
|
core0 {
|
|
cpu = <0x00>;
|
|
};
|
|
|
|
core1 {
|
|
cpu = <0x00>;
|
|
};
|
|
|
|
core2 {
|
|
cpu = <0x00>;
|
|
};
|
|
};
|
|
|
|
cluster2 {
|
|
|
|
core0 {
|
|
cpu = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu@0000 {
|
|
cpu-idle-states = <0x00>;
|
|
};
|
|
|
|
cpu@0100 {
|
|
cpu-idle-states = <0x00>;
|
|
};
|
|
|
|
cpu@0200 {
|
|
cpu-idle-states = <0x00>;
|
|
};
|
|
|
|
cpu@0300 {
|
|
cpu-idle-states = <0x00>;
|
|
};
|
|
|
|
cpu@0400 {
|
|
cpu-idle-states = <0x00>;
|
|
};
|
|
|
|
cpu@0500 {
|
|
cpu-idle-states = <0x00>;
|
|
};
|
|
|
|
cpu@0600 {
|
|
cpu-idle-states = <0x00>;
|
|
};
|
|
|
|
cpu@0700 {
|
|
cpu-idle-states = <0x00>;
|
|
};
|
|
};
|
|
|
|
exynos-acme {
|
|
|
|
domain@0 {
|
|
|
|
dm-constraints {
|
|
list = <0x00 0x04 0x08>;
|
|
};
|
|
};
|
|
|
|
domain@1 {
|
|
|
|
dm-constraints {
|
|
list = <0x00 0x04 0x08>;
|
|
};
|
|
};
|
|
|
|
domain@2 {
|
|
|
|
dm-constraints {
|
|
list = <0x00 0x04 0x08>;
|
|
};
|
|
};
|
|
};
|
|
|
|
exynos-dsufreq {
|
|
|
|
request_domain0 {
|
|
constraint = <0x00>;
|
|
};
|
|
|
|
request_domain1 {
|
|
constraint = <0x00>;
|
|
};
|
|
|
|
request_domain2 {
|
|
constraint = <0x00>;
|
|
};
|
|
|
|
hw-constraints {
|
|
list = <0x00>;
|
|
};
|
|
};
|
|
|
|
drmdpp@0x1AD00000 {
|
|
iommus = <0x00 0x04 0x08 0x0c>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
drmdpp@0x1AD08000 {
|
|
iommus = <0x00 0x04 0x08 0x0c>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
dphy_m4m4_dsim0@0x15860000 {
|
|
samsung,pmu-syscon = <0x00>;
|
|
};
|
|
|
|
drmdsim@0x19EC0000 {
|
|
iommus = <0x00 0x04 0x08 0x0c>;
|
|
samsung,iommu-group = <0x00>;
|
|
phys = <0x00>;
|
|
dsim_mode = <0x00>;
|
|
};
|
|
|
|
drmdp@0x10A80000 {
|
|
power-domains = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
};
|
|
|
|
drmdecon@0x19F00000 {
|
|
iommus = <0x00 0x04 0x08 0x0c>;
|
|
samsung,iommu-group = <0x00>;
|
|
clocks = <0x00>;
|
|
pinctrl-0 = <0x00>;
|
|
pinctrl-1 = <0x00>;
|
|
gpios = <0x00>;
|
|
dpps = <0x00 0x04 0x08 0x0c 0x10 0x14 0x18 0x1c 0x20 0x24 0x28 0x2c 0x30 0x34 0x38 0x3c>;
|
|
};
|
|
|
|
drmdecon@0x19F01000 {
|
|
iommus = <0x00 0x04 0x08 0x0c>;
|
|
samsung,iommu-group = <0x00>;
|
|
clocks = <0x00>;
|
|
dpps = <0x00 0x04 0x08 0x0c 0x10 0x14 0x18 0x1c 0x20 0x24 0x28 0x2c 0x30 0x34 0x38 0x3c>;
|
|
};
|
|
|
|
drmdecon@0x19F02000 {
|
|
iommus = <0x00 0x04 0x08 0x0c>;
|
|
samsung,iommu-group = <0x00>;
|
|
clocks = <0x00>;
|
|
dpps = <0x00 0x04 0x08 0x0c 0x10 0x14 0x18 0x1c 0x20 0x24 0x28 0x2c 0x30 0x34 0x38 0x3c>;
|
|
};
|
|
|
|
drmdecon@0x19F03000 {
|
|
iommus = <0x00 0x04 0x08 0x0c>;
|
|
samsung,iommu-group = <0x00>;
|
|
clocks = <0x00>;
|
|
dpps = <0x00 0x04 0x08 0x0c 0x10 0x14 0x18 0x1c 0x20 0x24 0x28 0x2c 0x30 0x34 0x38 0x3c>;
|
|
};
|
|
|
|
usb@10B00000 {
|
|
clocks = <0x00 0x08>;
|
|
power-domains = <0x00>;
|
|
samsung,sysreg-hsi0 = <0x00>;
|
|
phys = <0x00 0x08>;
|
|
|
|
dwc3 {
|
|
phys = <0x00 0x08>;
|
|
};
|
|
};
|
|
|
|
phy@10AA0000 {
|
|
clocks = <0x00 0x08>;
|
|
samsung,pmu-syscon = <0x00>;
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
usb_notifier {
|
|
udc = <0x00>;
|
|
};
|
|
|
|
pcie@113B0000 {
|
|
gpios = <0x00>;
|
|
interrupt-map = <0x10>;
|
|
samsung,syscon-phandle = <0x00>;
|
|
pinctrl-0 = <0x00 0x04>;
|
|
pinctrl-1 = <0x00 0x04>;
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
pcie@11320000 {
|
|
gpios = <0x00>;
|
|
samsung,syscon-phandle = <0x00>;
|
|
pinctrl-0 = <0x00 0x04>;
|
|
pinctrl-1 = <0x00 0x04>;
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
sysmmu@11280000 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
ufs@0x11100000 {
|
|
pinctrl-0 = <0x00 0x04>;
|
|
clocks = <0x00 0x08>;
|
|
samsung,pmu-phandle = <0x00>;
|
|
samsung,sysreg-phandle = <0x00>;
|
|
};
|
|
|
|
dss {
|
|
memory-region = <0x00 0x04 0x08 0x0c 0x10 0x14 0x18 0x1c 0x20>;
|
|
};
|
|
|
|
dss-debug-kinfo {
|
|
memory-region = <0x00>;
|
|
};
|
|
|
|
debug-kinfo {
|
|
memory-region = <0x00>;
|
|
};
|
|
|
|
exynos-itmon {
|
|
memory-region = <0x00>;
|
|
};
|
|
|
|
etf0@4004000 {
|
|
clocks = <0x00>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etf1@4005000 {
|
|
clocks = <0x00>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etr@400a000 {
|
|
clocks = <0x00>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
stm0@400b000 {
|
|
clocks = <0x00>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel0@4007000 {
|
|
clocks = <0x00>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel1@4008000 {
|
|
clocks = <0x00>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
|
|
port@7 {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnelm@4009000 {
|
|
clocks = <0x00>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
|
|
port@0 {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x00>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
exynos_devfreq {
|
|
|
|
devfreq_mif@17000010 {
|
|
clocks = <0x00>;
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
|
|
BIG {
|
|
thermal-sensors = <0x00>;
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
|
|
map1 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
MID {
|
|
thermal-sensors = <0x00>;
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
|
|
map1 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
LITTLE {
|
|
thermal-sensors = <0x00>;
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
G3D {
|
|
thermal-sensors = <0x00>;
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
ISP {
|
|
thermal-sensors = <0x00>;
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
|
|
map1 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
|
|
map2 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
|
|
map3 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
|
|
map4 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
|
|
map5 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
|
|
map6 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
|
|
map7 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
NPU {
|
|
thermal-sensors = <0x00>;
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
|
|
map1 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
|
|
map2 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
|
|
map3 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
|
|
map4 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
|
|
map5 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
|
|
map6 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
|
|
map7 {
|
|
trip = <0x00>;
|
|
cooling-device = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
CP {
|
|
thermal-sensors = <0x00>;
|
|
};
|
|
};
|
|
|
|
amb_control {
|
|
|
|
tz_big {
|
|
tz = <0x00>;
|
|
};
|
|
|
|
tz_mid {
|
|
tz = <0x00>;
|
|
};
|
|
|
|
tz_lit {
|
|
tz = <0x00>;
|
|
};
|
|
|
|
tz_isp {
|
|
tz = <0x00>;
|
|
};
|
|
};
|
|
|
|
exynos-ect {
|
|
memory-region = <0x00>;
|
|
};
|
|
|
|
s2mpu {
|
|
memory_region = <0x00>;
|
|
};
|
|
|
|
seclog {
|
|
memory-region = <0x00>;
|
|
};
|
|
|
|
secmem {
|
|
power-domains = <0x00>;
|
|
memory-region = <0x00 0x04>;
|
|
};
|
|
|
|
ssp {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
pd_brp@15861900 {
|
|
parent = <0x00>;
|
|
};
|
|
|
|
pd_csis@15861f00 {
|
|
parent = <0x00>;
|
|
};
|
|
|
|
pd_cstat@15861f80 {
|
|
parent = <0x00>;
|
|
};
|
|
|
|
pd_allcsis@15862000 {
|
|
parent = <0x00>;
|
|
};
|
|
|
|
pd_dpuf@15862100 {
|
|
parent = <0x00>;
|
|
};
|
|
|
|
pd_mcsc@15862780 {
|
|
parent = <0x00>;
|
|
};
|
|
|
|
pd_yuvp@15863100 {
|
|
parent = <0x00>;
|
|
};
|
|
|
|
pd_sdma@15863180 {
|
|
parent = <0x00>;
|
|
};
|
|
|
|
pd_gnpu0@15862380 {
|
|
parent = <0x00>;
|
|
};
|
|
|
|
pd_gnpu1@15862400 {
|
|
parent = <0x00>;
|
|
};
|
|
|
|
pd_dsp0@15862f00 {
|
|
parent = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-aud {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-nocl1c {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-brp {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-cstat {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-allcsis {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-dpub {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-dpuf {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-g3dcore {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-strong {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-dnc {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-gnpu0 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-gnpu1 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-hsi0 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-hsi1 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-lme {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-m2m {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-mcsc {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-mfc0 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-mfc1 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-dsp0 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-vts {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-yuvp {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-sdma {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
dbgdev-pd-ufd {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
ems {
|
|
|
|
emstune {
|
|
boot-set = <0x00>;
|
|
|
|
mode0 {
|
|
|
|
level0 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
|
|
level1 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
|
|
level2 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
};
|
|
|
|
mode1 {
|
|
|
|
level0 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
|
|
level1 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
|
|
level2 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
};
|
|
|
|
mode2 {
|
|
|
|
level0 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
|
|
level1 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
|
|
level2 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
};
|
|
|
|
mode3 {
|
|
|
|
level0 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
|
|
level1 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
|
|
level2 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
};
|
|
|
|
mode4 {
|
|
|
|
level0 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
|
|
level1 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
|
|
level2 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
};
|
|
|
|
mode5 {
|
|
|
|
level0 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
|
|
level1 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
|
|
level2 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
};
|
|
|
|
mode6 {
|
|
|
|
level0 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
|
|
level1 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
|
|
level2 {
|
|
base = <0x00>;
|
|
set = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
mfc {
|
|
iommus = <0x00 0x04 0x08 0x0c>;
|
|
samsung,iommu-group = <0x00>;
|
|
memory-region = <0x00>;
|
|
|
|
MFC-0 {
|
|
clocks = <0x00>;
|
|
iommus = <0x00 0x04>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
MFC-1 {
|
|
clocks = <0x00>;
|
|
iommus = <0x00 0x04>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
};
|
|
|
|
smfc@18940000 {
|
|
iommus = <0x00>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
smfc@18950000 {
|
|
iommus = <0x00>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
scaler@18960000 {
|
|
clocks = <0x00>;
|
|
iommus = <0x00>;
|
|
samsung,iommu-group = <0x00>;
|
|
samsung,mscl-votf_targets = <0x00 0x14>;
|
|
};
|
|
|
|
jsqz@18980000 {
|
|
iommus = <0x00>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
mcfrc@0x18A50000 {
|
|
iommus = <0x00>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
tsmux@186E0000 {
|
|
iommus = <0x00>;
|
|
samsung,iommu-group = <0x00>;
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
repeater@0 {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
exynos_is@18440000 {
|
|
clocks = <0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 0x98 0xa0 0xa8 0xb0 0xb8 0xc0 0xc8 0xd0 0xd8 0xe0 0xe8 0xf0 0xf8 0x100>;
|
|
iommus = <0x00 0x04 0x08 0x0c 0x10>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
gdc@17700000 {
|
|
clocks = <0x00>;
|
|
iommus = <0x00>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
votf0 {
|
|
iommus = <0x00 0x04 0x08 0x0c 0x10 0x14 0x18>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
votf1 {
|
|
iommus = <0x00 0x04 0x08 0x0c 0x10>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
votf2 {
|
|
iommus = <0x00>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
is_iommu_group_module {
|
|
groups = <0x00 0x04 0x08 0x0c>;
|
|
};
|
|
|
|
is_iommu_group0 {
|
|
iommus = <0x00 0x04 0x08 0x0c 0x10>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
is_iommu_group1 {
|
|
iommus = <0x00>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
is_iommu_group2 {
|
|
iommus = <0x00 0x04 0x08 0x0c 0x10 0x14 0x18>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
is_iommu_group3 {
|
|
iommus = <0x00 0x04>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
camif-wdma-module@17140000 {
|
|
channels = <0x00 0x04 0x08 0x0c 0x10>;
|
|
};
|
|
|
|
camif-wdma@17141000 {
|
|
module = <0x00>;
|
|
};
|
|
|
|
camif-wdma@17142000 {
|
|
module = <0x00>;
|
|
};
|
|
|
|
camif-wdma@17143000 {
|
|
module = <0x00>;
|
|
};
|
|
|
|
camif-wdma@17144000 {
|
|
module = <0x00>;
|
|
};
|
|
|
|
camif-wdma@17145000 {
|
|
module = <0x00>;
|
|
};
|
|
|
|
dcphy_m0s4s4s4s4s4s4_s22_csi0@170F1300 {
|
|
samsung,pmu-syscon = <0x00>;
|
|
samsung,reset-sysreg = <0x00>;
|
|
};
|
|
|
|
dcphy_m0s4s4s4s4s4s4_s22_csi1@170F1B00 {
|
|
samsung,pmu-syscon = <0x00>;
|
|
samsung,reset-sysreg = <0x00>;
|
|
};
|
|
|
|
dcphy_m0s4s4s4s4s4s4_s22_csi2@170F2300 {
|
|
samsung,pmu-syscon = <0x00>;
|
|
samsung,reset-sysreg = <0x00>;
|
|
};
|
|
|
|
dcphy_m0s4s4s4s4s4s4_s22_csi3@170F2B00 {
|
|
samsung,pmu-syscon = <0x00>;
|
|
samsung,reset-sysreg = <0x00>;
|
|
};
|
|
|
|
dphy_m0s4s4s4s4s4s4_s22_csi4@170F3300 {
|
|
samsung,pmu-syscon = <0x00>;
|
|
samsung,reset-sysreg = <0x00>;
|
|
};
|
|
|
|
dphy_m0s4s4s4s4s4s4_s22_csi5@170F3B00 {
|
|
samsung,pmu-syscon = <0x00>;
|
|
samsung,reset-sysreg = <0x00>;
|
|
};
|
|
|
|
dphy_m0s4s4s4s4s4s4_s22_csi5@170F3A00 {
|
|
samsung,pmu-syscon = <0x00>;
|
|
samsung,reset-sysreg = <0x00>;
|
|
};
|
|
|
|
is_sensor0@17030000 {
|
|
phys = <0x00>;
|
|
phy_setfile = <0x00>;
|
|
iommus = <0x00 0x04>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
is_sensor1@17040000 {
|
|
phys = <0x00>;
|
|
phy_setfile = <0x00>;
|
|
iommus = <0x00 0x04>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
is_sensor2@17050000 {
|
|
phys = <0x00>;
|
|
phy_setfile = <0x00>;
|
|
iommus = <0x00 0x04>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
is_sensor3@17060000 {
|
|
phys = <0x00>;
|
|
phy_setfile = <0x00>;
|
|
iommus = <0x00 0x04>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
is_sensor4@17070000 {
|
|
phys = <0x00>;
|
|
phy_setfile = <0x00>;
|
|
iommus = <0x00 0x04>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
is_sensor5@17080000 {
|
|
phys = <0x00>;
|
|
phy_setfile = <0x00>;
|
|
iommus = <0x00 0x04>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
sensor-paf-pdp@17100000 {
|
|
lic_lut = <0x00>;
|
|
};
|
|
|
|
sensor-paf-pdp@17110000 {
|
|
lic_lut = <0x00>;
|
|
};
|
|
|
|
sensor-paf-pdp@17120000 {
|
|
lic_lut = <0x00>;
|
|
};
|
|
|
|
sensor-paf-pdp@17130000 {
|
|
lic_lut = <0x00>;
|
|
};
|
|
|
|
npu_exynos {
|
|
iommus = <0x00 0x04 0x08 0x0c 0x10>;
|
|
samsung,iommu-group = <0x00>;
|
|
samsung,npusched-dvfs = <0x00 0x44 0x88 0xcc 0x110>;
|
|
|
|
samsung,npurmem-address {
|
|
|
|
fwmem {
|
|
memory-region = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
hwdev_dnc {
|
|
clocks = <0x00>;
|
|
iommus = <0x00 0x04 0x08 0x0c 0x10>;
|
|
samsung,iommu-group = <0x00>;
|
|
};
|
|
|
|
hwdev_npu {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
hwdev_dsp {
|
|
power-domains = <0x00>;
|
|
};
|
|
|
|
samsung,memlogger {
|
|
memory-region = <0x00>;
|
|
samsung,bl-node = <0x00>;
|
|
};
|
|
|
|
exynos-pmu {
|
|
samsung,syscon-phandle = <0x00>;
|
|
};
|
|
|
|
exynos-reboot {
|
|
samsung,syscon-phandle = <0x00>;
|
|
samsung,spmi-syscon-phandle = <0x00>;
|
|
};
|
|
|
|
mct_alive@15890000 {
|
|
interrupt-parent = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
|
|
mct-alive-map {
|
|
interrupt-map = <0x04 0x18 0x2c 0x40 0x54 0x68 0x7c 0x90 0xa4 0xb8 0xcc 0xe0>;
|
|
};
|
|
};
|
|
|
|
amba {
|
|
interrupt-parent = <0x00>;
|
|
|
|
pdma0@1A4E0000 {
|
|
clocks = <0x00>;
|
|
};
|
|
};
|
|
|
|
exynos-bcmdbg {
|
|
memory-region = <0x00>;
|
|
};
|
|
|
|
exynos-sci_dbg {
|
|
memory-region = <0x00>;
|
|
};
|
|
|
|
exynos-sci {
|
|
memory-region = <0x00>;
|
|
devfreq = <0x00>;
|
|
};
|
|
|
|
pwm@11C50000 {
|
|
clocks = <0x00 0x08>;
|
|
};
|
|
|
|
watchdog_cl0@10050000 {
|
|
clocks = <0x00 0x08>;
|
|
samsung,syscon-phandle = <0x00>;
|
|
};
|
|
|
|
watchdog_cl1@10060000 {
|
|
clocks = <0x00 0x08>;
|
|
samsung,syscon-phandle = <0x00>;
|
|
};
|
|
|
|
contexthub {
|
|
memory-region = <0x00>;
|
|
clocks = <0x00 0x08>;
|
|
};
|
|
};
|
|
};
|