18492 lines
424 KiB
Text
Executable file
18492 lines
424 KiB
Text
Executable file
/dts-v1/;
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/ {
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compatible = "samsung,armv8\0samsung,exynos2100";
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interrupt-parent = <0x01>;
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#address-cells = <0x02>;
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#size-cells = <0x01>;
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reserved-memory {
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#address-cells = <0x02>;
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#size-cells = <0x01>;
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ranges;
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phandle = <0x177>;
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ect_binary {
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compatible = "exynos,ect_rmem";
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reg = <0x00 0x90000000 0x3a000>;
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phandle = <0x136>;
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};
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el3mon_reserve {
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compatible = "exynos,el3mon";
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reg = <0x00 0xbff80000 0x80000>;
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};
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debug_snapshot {
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#address-cells = <0x02>;
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#size-cells = <0x01>;
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phandle = <0x178>;
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header {
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reg = <0x00 0xf0000000 0x10000>;
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no-map;
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phandle = <0xda>;
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};
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log_kernel {
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reg = <0x00 0xf0010000 0x200000>;
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phandle = <0xdb>;
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};
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log_platform {
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reg = <0x00 0xf0210000 0x400000>;
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phandle = <0xe0>;
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};
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log_s2d {
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reg = <0x00 0xf0610000 0x1200000>;
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phandle = <0xdc>;
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};
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log_first {
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reg = <0x00 0xf1810000 0x200000>;
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phandle = <0xdd>;
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};
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log_arrdumpreset {
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reg = <0x00 0xf1a10000 0xb00000>;
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phandle = <0xde>;
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};
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log_arrdumppanic {
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reg = <0x00 0xf2510000 0x600000>;
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phandle = <0xdf>;
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};
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log_kevents {
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reg = <0x00 0xf2b10000 0x600000>;
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phandle = <0xe1>;
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};
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log_last {
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reg = <0x00 0xf3110000 0x200000>;
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phandle = <0xe2>;
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};
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};
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log_bcm {
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compatible = "exynos,bcmdbg";
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reg = <0x00 0xff000000 0x400000>;
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phandle = <0x174>;
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};
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log_llc {
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compatible = "exynos,llc";
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reg = <0x00 0xff400000 0x800000>;
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phandle = <0x172>;
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};
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log_ppc {
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compatible = "exynos,ppc";
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reg = <0x00 0xffc00000 0x100000>;
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phandle = <0x171>;
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};
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seclog_mem {
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compatible = "exynos,seclog";
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reg = <0x00 0xc3000000 0x80000>;
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phandle = <0x141>;
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};
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s2mpu_table {
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compatible = "exynos,s2mpu_table";
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reg = <0x00 0xc1800000 0x800000>;
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phandle = <0x140>;
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};
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cp_rmem {
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compatible = "exynos,modem_if";
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reg = <0x08 0x80000000 0xd800000>;
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rmem_index = <0x00>;
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phandle = <0x179>;
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};
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cp_rmem1 {
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compatible = "exynos,modem_if";
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reg = <0x08 0x90000000 0xa000000>;
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rmem_index = <0x01>;
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phandle = <0x17a>;
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};
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dummy_heap {
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compatible = "shared-dma-pool";
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reg = <0x08 0x9f000000 0x1000000>;
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alignment = <0x00 0x400000>;
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reusable;
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phandle = <0x17b>;
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};
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abox-dbg {
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compatible = "exynos,abox_dbg";
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size = <0x2900000>;
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alloc-ranges = <0x00 0xc0000000 0x20000000>;
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phandle = <0x15c>;
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};
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abox-slog {
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compatible = "exynos,abox_slog";
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reg = <0x08 0x9b800000 0x2800000>;
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phandle = <0x15d>;
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};
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abox-rmem {
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compatible = "exynos,abox_rmem";
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reg = <0x08 0x8d800000 0x2800000>;
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phandle = <0x14c>;
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};
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abox-rdma-compr {
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compatible = "exynos,abox_rdma_compr_buffer";
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size = <0x50000>;
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alloc-ranges = <0x00 0xc0000000 0x20000000>;
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phandle = <0x14f>;
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};
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dpado-rmem {
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compatible = "exynos,dp_ado_rmem";
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size = <0x200000>;
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alloc-ranges = <0x00 0xc0000000 0x20000000>;
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phandle = <0x16d>;
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};
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memlog_region {
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compatible = "shared-dma-pool";
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no-map;
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reg = <0x08 0x9a000000 0x1800000>;
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phandle = <0x175>;
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};
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default_cma {
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compatible = "shared-dma-pool";
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reg = <0x08 0x9e000000 0x1000000>;
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alignment = <0x00 0x400000>;
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reusable;
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linux,cma-default;
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};
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dsp-shmem {
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compatible = "exynos,dsp_shmem";
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size = <0x1000>;
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alloc-ranges = <0x00 0xc0000000 0x40000000>;
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phandle = <0x17c>;
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};
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dsp-master-rmem {
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compatible = "exynos,dsp_master_rmem";
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size = <0x110000>;
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alloc-ranges = <0x00 0xc0000000 0x40000000>;
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phandle = <0x17d>;
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};
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mfc_fw_rmem {
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compatible = "samsung,exynos-mfc";
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size = <0x400000>;
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alignment = <0x00 0x10000>;
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phandle = <0x147>;
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};
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crypto {
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compatible = "shared-dma-pool";
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size = <0x1800000>;
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alloc-ranges = <0x0a 0x00 0x10000000 0x00 0x40000000 0xb0000000>;
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alignment = <0x00 0x400000>;
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reusable;
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phandle = <0x100>;
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};
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vstream {
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compatible = "shared-dma-pool";
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size = <0x4800000>;
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alloc-ranges = <0x00 0x40000000 0xb0000000>;
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alignment = <0x00 0x400000>;
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reusable;
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phandle = <0x101>;
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};
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vframe {
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compatible = "shared-dma-pool";
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size = <0x20000000>;
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alignment = <0x00 0x400000>;
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reusable;
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phandle = <0x102>;
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};
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vscaler {
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compatible = "shared-dma-pool";
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size = <0x3400000>;
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alignment = <0x00 0x400000>;
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reusable;
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phandle = <0x103>;
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};
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gpu_buffer {
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compatible = "shared-dma-pool";
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size = <0x4000000>;
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alignment = <0x00 0x400000>;
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reusable;
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phandle = <0x104>;
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};
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};
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memlog_bl_base {
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samsung,bl-base = <0xf0000000>;
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samsung,bl-offset = <0x290>;
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phandle = <0x176>;
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};
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pinctrl@15850000 {
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compatible = "samsung,exynos2100-pinctrl";
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reg = <0x00 0x15850000 0x1000>;
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interrupts = <0x00 0x05 0x04>;
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phandle = <0x17e>;
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gpq0 {
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gpio-controller;
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#gpio-cells = <0x02>;
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phandle = <0x17f>;
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};
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gpq1 {
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gpio-controller;
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#gpio-cells = <0x02>;
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phandle = <0x180>;
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};
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gpq2 {
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gpio-controller;
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#gpio-cells = <0x02>;
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phandle = <0x181>;
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};
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gpb5 {
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gpio-controller;
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#gpio-cells = <0x02>;
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phandle = <0x182>;
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};
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uart1-bus {
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samsung,pins = "gpq0-3\0gpq0-2\0gpq0-1\0gpq0-0";
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samsung,pin-function = <0x02>;
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samsung,pin-pud = <0x03>;
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phandle = <0x69>;
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};
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uart1-bus-rts {
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samsung,pins = "gpq0-2";
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samsung,pin-function = <0x01>;
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samsung,pin-pud = <0x00>;
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samsung,pin-val = <0x01>;
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phandle = <0x6a>;
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};
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uart1-bus-tx-dat {
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samsung,pins = "gpq0-1";
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samsung,pin-val = <0x01>;
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phandle = <0x6c>;
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};
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uart1-bus-tx-con {
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samsung,pins = "gpq0-1";
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samsung,pin-function = <0x01>;
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phandle = <0x6b>;
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};
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aud-i2s5-bus {
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samsung,pins = "gpb5-0\0gpb5-1\0gpb5-2\0gpb5-3";
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samsung,pin-function = <0x03>;
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samsung,pin-pud = <0x00>;
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phandle = <0x15a>;
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};
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aud-i2s5-idle {
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samsung,pins = "gpb5-0\0gpb5-1\0gpb5-2\0gpb5-3";
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samsung,pin-function = <0x00>;
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samsung,pin-pud = <0x01>;
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phandle = <0x15b>;
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};
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};
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pinctrl@14E30000 {
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compatible = "samsung,exynos2100-pinctrl";
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reg = <0x00 0x14e30000 0x1000>;
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interrupts = <0x00 0x55 0x04 0x00 0x56 0x04 0x00 0x57 0x04 0x00 0x58 0x04 0x00 0x59 0x04 0x00 0x5a 0x04 0x00 0x5b 0x04 0x00 0x5c 0x04 0x00 0x5d 0x04 0x00 0x5e 0x04 0x00 0x5f 0x04 0x00 0x60 0x04 0x00 0x61 0x04 0x00 0x62 0x04 0x00 0x63 0x04 0x00 0x64 0x04 0x00 0x65 0x04 0x00 0x66 0x04 0x00 0x67 0x04 0x00 0x68 0x04 0x00 0x69 0x04 0x00 0x6a 0x04 0x00 0x6b 0x04 0x00 0x6c 0x04 0x00 0x6d 0x04 0x00 0x6e 0x04 0x00 0x6f 0x04 0x00 0x70 0x04 0x00 0x71 0x04 0x00 0x72 0x04 0x00 0x73 0x04 0x00 0x74 0x04 0x00 0x75 0x04 0x00 0x76 0x04>;
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phandle = <0x183>;
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gpm0 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x55 0x04 0x00 0x56 0x04>;
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phandle = <0x42>;
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};
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gpm1 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x57 0x04 0x00 0x58 0x04>;
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phandle = <0x44>;
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};
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gpm2 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x59 0x04 0x00 0x5a 0x04>;
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phandle = <0x46>;
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};
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gpm3 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x5b 0x04 0x00 0x5c 0x04>;
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phandle = <0x48>;
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};
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gpm4 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x5d 0x04 0x00 0x5e 0x04>;
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phandle = <0x4a>;
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};
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gpm5 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x5f 0x04 0x00 0x60 0x04>;
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phandle = <0x4c>;
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};
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gpm6 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x61 0x04 0x00 0x62 0x04>;
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phandle = <0x4e>;
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};
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gpm7 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x63 0x04 0x00 0x64 0x04>;
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phandle = <0x50>;
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};
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gpm8 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x65 0x04>;
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phandle = <0x184>;
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};
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gpm9 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x66 0x04>;
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phandle = <0x185>;
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};
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gpm10 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x67 0x04>;
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phandle = <0x186>;
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};
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gpm11 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x68 0x04>;
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phandle = <0x187>;
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};
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gpm12 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x69 0x04>;
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phandle = <0x188>;
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};
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gpm13 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x6a 0x04>;
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phandle = <0x189>;
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};
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gpm14 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x6b 0x04>;
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phandle = <0x18a>;
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};
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gpm15 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x6c 0x04>;
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phandle = <0x18b>;
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};
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gpm16 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x6d 0x04>;
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phandle = <0x18c>;
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};
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gpm17 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x6e 0x04>;
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phandle = <0x18d>;
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};
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gpm18 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x6f 0x04>;
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phandle = <0x18e>;
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};
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gpm19 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
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interrupt-parent = <0x01>;
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interrupts = <0x00 0x70 0x04>;
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phandle = <0x18f>;
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};
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gpm20 {
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gpio-controller;
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#gpio-cells = <0x02>;
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interrupt-controller;
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#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x71 0x04>;
|
|
phandle = <0x190>;
|
|
};
|
|
|
|
gpm21 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x72 0x04>;
|
|
phandle = <0x191>;
|
|
};
|
|
|
|
gpm22 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x73 0x04>;
|
|
phandle = <0x192>;
|
|
};
|
|
|
|
gpm23 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x74 0x04>;
|
|
phandle = <0x193>;
|
|
};
|
|
|
|
gpm24 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x75 0x04>;
|
|
phandle = <0x194>;
|
|
};
|
|
|
|
gpm25 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x76 0x04>;
|
|
phandle = <0x195>;
|
|
};
|
|
|
|
hsi2c38-bus {
|
|
samsung,pins = "gpm0-0\0gpm0-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x41>;
|
|
};
|
|
|
|
hsi2c39-bus {
|
|
samsung,pins = "gpm1-0\0gpm1-1";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x43>;
|
|
};
|
|
|
|
hsi2c40-bus {
|
|
samsung,pins = "gpm2-0\0gpm2-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x45>;
|
|
};
|
|
|
|
hsi2c41-bus {
|
|
samsung,pins = "gpm3-0\0gpm3-1";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x47>;
|
|
};
|
|
|
|
hsi2c42-bus {
|
|
samsung,pins = "gpm4-0\0gpm4-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x49>;
|
|
};
|
|
|
|
hsi2c43-bus {
|
|
samsung,pins = "gpm5-0\0gpm5-1";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x4b>;
|
|
};
|
|
|
|
hsi2c44-bus {
|
|
samsung,pins = "gpm6-0\0gpm6-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x4d>;
|
|
};
|
|
|
|
hsi2c45-bus {
|
|
samsung,pins = "gpm7-0\0gpm7-1";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x4f>;
|
|
};
|
|
|
|
spi19-bus {
|
|
samsung,pins = "gpm0-0\0gpm0-1\0gpm1-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x64>;
|
|
};
|
|
|
|
spi19-cs {
|
|
samsung,pins = "gpm1-1";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x196>;
|
|
};
|
|
|
|
spi19-cs-func {
|
|
samsung,pins = "gpm1-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x197>;
|
|
};
|
|
|
|
spi20-bus {
|
|
samsung,pins = "gpm2-0\0gpm2-1\0gpm3-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x65>;
|
|
};
|
|
|
|
spi20-cs {
|
|
samsung,pins = "gpm3-1";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x198>;
|
|
};
|
|
|
|
spi20-cs-func {
|
|
samsung,pins = "gpm3-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x199>;
|
|
};
|
|
|
|
spi21-bus {
|
|
samsung,pins = "gpm4-0\0gpm4-1\0gpm5-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x66>;
|
|
};
|
|
|
|
spi21-cs {
|
|
samsung,pins = "gpm5-1";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x19a>;
|
|
};
|
|
|
|
spi21-cs-func {
|
|
samsung,pins = "gpm5-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x19b>;
|
|
};
|
|
|
|
spi22-bus {
|
|
samsung,pins = "gpm6-0\0gpm6-1\0gpm7-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x67>;
|
|
};
|
|
|
|
spi22-cs {
|
|
samsung,pins = "gpm7-1";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x19c>;
|
|
};
|
|
|
|
spi22-cs-func {
|
|
samsung,pins = "gpm7-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x19d>;
|
|
};
|
|
|
|
uart21-bus {
|
|
samsung,pins = "gpm0-0\0gpm0-1\0gpm2-0\0gpm2-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x80>;
|
|
};
|
|
|
|
uart21-bus-dual {
|
|
samsung,pins = "gpm0-0\0gpm0-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x19e>;
|
|
};
|
|
|
|
uart22-bus {
|
|
samsung,pins = "gpm3-0\0gpm3-1\0gpm4-0\0gpm4-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x81>;
|
|
};
|
|
|
|
uart22-bus-dual {
|
|
samsung,pins = "gpm3-0\0gpm3-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x19f>;
|
|
};
|
|
|
|
uart23-bus {
|
|
samsung,pins = "gpm5-0\0gpm5-1\0gpm6-0\0gpm6-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x82>;
|
|
};
|
|
|
|
uart23-bus-dual {
|
|
samsung,pins = "gpm5-0\0gpm5-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1a0>;
|
|
};
|
|
|
|
uart24-bus {
|
|
samsung,pins = "gpm7-0\0gpm7-1\0gpm8-0\0gpm8-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x83>;
|
|
};
|
|
|
|
uart24-bus-dual {
|
|
samsung,pins = "gpm7-0\0gpm7-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1a1>;
|
|
};
|
|
|
|
wakeup-interrupt-controller {
|
|
compatible = "samsung,exynos-cmgp-wakeup-eint";
|
|
};
|
|
};
|
|
|
|
pinctrl@14EC0000 {
|
|
compatible = "samsung,exynos2100-pinctrl";
|
|
reg = <0x00 0x14ec0000 0x1000>;
|
|
interrupts = <0x00 0x31 0x04 0x00 0x32 0x04 0x00 0x33 0x04 0x00 0x34 0x04 0x00 0x35 0x04 0x00 0x36 0x04 0x00 0x37 0x04 0x00 0x38 0x04 0x00 0x39 0x04 0x00 0x3a 0x04 0x00 0x3b 0x04 0x00 0x3c 0x04 0x00 0x3d 0x04 0x00 0x3e 0x04 0x00 0x3f 0x04 0x00 0x40 0x04 0x00 0x41 0x04 0x00 0x42 0x04 0x00 0x43 0x04 0x00 0x44 0x04 0x00 0x45 0x04 0x00 0x46 0x04 0x00 0x47 0x04 0x00 0x48 0x04 0x00 0x49 0x04 0x00 0x4a 0x04 0x00 0x4b 0x04 0x00 0x4c 0x04 0x00 0x4d 0x04 0x00 0x4e 0x04 0x00 0x4f 0x04 0x00 0x50 0x04 0x00 0x51 0x04 0x00 0x52 0x04>;
|
|
phandle = <0x1a2>;
|
|
|
|
gpa0 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x03>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x31 0x04 0x00 0x32 0x04 0x00 0x33 0x04 0x00 0x34 0x04 0x00 0x35 0x04 0x00 0x36 0x04 0x00 0x37 0x04 0x00 0x38 0x04>;
|
|
phandle = <0x1a3>;
|
|
};
|
|
|
|
gpa1 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x03>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x39 0x04 0x00 0x3a 0x04 0x00 0x3b 0x04 0x00 0x3c 0x04 0x00 0x3d 0x04 0x00 0x3e 0x04 0x00 0x3f 0x04 0x00 0x40 0x04>;
|
|
phandle = <0x1a4>;
|
|
};
|
|
|
|
gpa2 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x03>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x41 0x04 0x00 0x42 0x04 0x00 0x43 0x04 0x00 0x44 0x04 0x00 0x45 0x04 0x00 0x46 0x04 0x00 0x47 0x04 0x00 0x48 0x04>;
|
|
phandle = <0x1a5>;
|
|
};
|
|
|
|
gpa3 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x03>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x49 0x04 0x00 0x4a 0x04 0x00 0x4b 0x04 0x00 0x4c 0x04 0x00 0x4d 0x04 0x00 0x4e 0x04 0x00 0x4f 0x04 0x00 0x50 0x04>;
|
|
phandle = <0x1a6>;
|
|
};
|
|
|
|
gpa4 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x03>;
|
|
interrupt-parent = <0x01>;
|
|
interrupts = <0x00 0x51 0x04 0x00 0x52 0x04>;
|
|
phandle = <0x1a7>;
|
|
};
|
|
|
|
wakeup-interrupt-controller {
|
|
compatible = "samsung,exynos7-wakeup-eint";
|
|
};
|
|
};
|
|
|
|
pinctrl@11040000 {
|
|
compatible = "samsung,exynos2100-pinctrl";
|
|
reg = <0x00 0x11040000 0x1000>;
|
|
interrupts = <0x00 0x164 0x04>;
|
|
phandle = <0x1a8>;
|
|
|
|
gpf0 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x109>;
|
|
};
|
|
|
|
gpf1 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1a9>;
|
|
};
|
|
|
|
gpf2 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1aa>;
|
|
};
|
|
|
|
pcie0_clkreq {
|
|
samsung,pins = "gpf0-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x03>;
|
|
samsung,pin-con-pdn = <0x03>;
|
|
samsung,pin-pud-pdn = <0x03>;
|
|
phandle = <0x10a>;
|
|
};
|
|
|
|
pcie0_perst {
|
|
samsung,pins = "gpf0-1";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-drv = <0x03>;
|
|
samsung,pin-con-pdn = <0x03>;
|
|
phandle = <0x10b>;
|
|
};
|
|
|
|
pcie1_clkreq {
|
|
samsung,pins = "gpf0-2";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x03>;
|
|
samsung,pin-con-pdn = <0x03>;
|
|
samsung,pin-pud-pdn = <0x03>;
|
|
phandle = <0x10c>;
|
|
};
|
|
|
|
pcie1_perst {
|
|
samsung,pins = "gpf0-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-drv = <0x03>;
|
|
samsung,pin-con-pdn = <0x03>;
|
|
phandle = <0x10d>;
|
|
};
|
|
|
|
ufs-rst-n {
|
|
samsung,pins = "gpf2-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x03>;
|
|
samsung,pin-pud-pdn = <0x00>;
|
|
phandle = <0xb4>;
|
|
};
|
|
|
|
ufs-refclk-out {
|
|
samsung,pins = "gpf2-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x03>;
|
|
samsung,pin-drv = <0x01>;
|
|
samsung,pin-pud-pdn = <0x00>;
|
|
phandle = <0xb5>;
|
|
};
|
|
|
|
sd2-clk {
|
|
samsung,pins = "gpf1-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x02>;
|
|
phandle = <0x1ab>;
|
|
};
|
|
|
|
sd2-cmd {
|
|
samsung,pins = "gpf1-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x02>;
|
|
phandle = <0x1ac>;
|
|
};
|
|
|
|
sd2-bus-width1 {
|
|
samsung,pins = "gpf1-2";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x02>;
|
|
phandle = <0x1ad>;
|
|
};
|
|
|
|
sd2-bus-width4 {
|
|
samsung,pins = "gpf1-3\0gpf1-4\0gpf1-5";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x03>;
|
|
samsung,pin-drv = <0x02>;
|
|
phandle = <0x1ae>;
|
|
};
|
|
|
|
sd2-clk_fast_slew_rate_1x {
|
|
samsung,pins = "gpf1-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1af>;
|
|
};
|
|
|
|
sd2-clk_fast_slew_rate_1_5x {
|
|
samsung,pins = "gpf1-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x01>;
|
|
phandle = <0x1b0>;
|
|
};
|
|
|
|
sd2-clk_fast_slew_rate_2x {
|
|
samsung,pins = "gpf1-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x02>;
|
|
phandle = <0x1b1>;
|
|
};
|
|
|
|
sd2-clk_fast_slew_rate_2_5x {
|
|
samsung,pins = "gpf1-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x03>;
|
|
phandle = <0x1b2>;
|
|
};
|
|
|
|
sd2-clk_fast_slew_rate_3x {
|
|
samsung,pins = "gpf1-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x04>;
|
|
phandle = <0x1b3>;
|
|
};
|
|
|
|
sd2-clk_fast_slew_rate_4x {
|
|
samsung,pins = "gpf1-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x05>;
|
|
phandle = <0x1b4>;
|
|
};
|
|
|
|
sd2-pins-as-pdn {
|
|
samsung,pins = "gpf1-0\0gpf1-1\0gpf1-2\0gpf1-3\0gpf1-4\0gpf1-5";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x02>;
|
|
phandle = <0x1b5>;
|
|
};
|
|
};
|
|
|
|
pinctrl@10430000 {
|
|
compatible = "samsung,exynos2100-pinctrl";
|
|
reg = <0x00 0x10430000 0x1000>;
|
|
interrupts = <0x00 0x1fd 0x04>;
|
|
phandle = <0x1b6>;
|
|
|
|
gpp0 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x05>;
|
|
};
|
|
|
|
gpp1 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x08>;
|
|
};
|
|
|
|
gpp2 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x0b>;
|
|
};
|
|
|
|
gpp3 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x0e>;
|
|
};
|
|
|
|
gpp4 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x11>;
|
|
};
|
|
|
|
gpp5 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x14>;
|
|
};
|
|
|
|
gpp13 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x2f>;
|
|
};
|
|
|
|
gpp14 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x32>;
|
|
};
|
|
|
|
gpp15 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x35>;
|
|
};
|
|
|
|
gpg0 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1b7>;
|
|
};
|
|
|
|
uart0-bus {
|
|
samsung,pins = "gpg0-2\0gpg0-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x03>;
|
|
phandle = <0x68>;
|
|
};
|
|
|
|
hsi2c0-bus {
|
|
samsung,pins = "gpp0-0\0gpp0-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x03>;
|
|
};
|
|
|
|
hsi2c1-bus {
|
|
samsung,pins = "gpp0-2\0gpp0-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x06>;
|
|
};
|
|
|
|
hsi2c2-bus {
|
|
samsung,pins = "gpp1-0\0gpp1-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x07>;
|
|
};
|
|
|
|
hsi2c3-bus {
|
|
samsung,pins = "gpp1-2\0gpp1-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x09>;
|
|
};
|
|
|
|
hsi2c4-bus {
|
|
samsung,pins = "gpp2-0\0gpp2-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x0a>;
|
|
};
|
|
|
|
hsi2c5-bus {
|
|
samsung,pins = "gpp2-2\0gpp2-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x0c>;
|
|
};
|
|
|
|
hsi2c6-bus {
|
|
samsung,pins = "gpp3-0\0gpp3-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x0d>;
|
|
};
|
|
|
|
hsi2c7-bus {
|
|
samsung,pins = "gpp3-2\0gpp3-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x0f>;
|
|
};
|
|
|
|
hsi2c8-bus {
|
|
samsung,pins = "gpp4-0\0gpp4-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x10>;
|
|
};
|
|
|
|
hsi2c9-bus {
|
|
samsung,pins = "gpp4-2\0gpp4-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x12>;
|
|
};
|
|
|
|
hsi2c10-bus {
|
|
samsung,pins = "gpp5-0\0gpp5-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x13>;
|
|
};
|
|
|
|
hsi2c11-bus {
|
|
samsung,pins = "gpp5-2\0gpp5-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x15>;
|
|
};
|
|
|
|
hsi2c26-bus {
|
|
samsung,pins = "gpp13-0\0gpp13-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x2e>;
|
|
};
|
|
|
|
hsi2c27-bus {
|
|
samsung,pins = "gpp13-2\0gpp13-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x30>;
|
|
};
|
|
|
|
hsi2c28-bus {
|
|
samsung,pins = "gpp14-0\0gpp14-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x31>;
|
|
};
|
|
|
|
hsi2c29-bus {
|
|
samsung,pins = "gpp14-2\0gpp14-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x33>;
|
|
};
|
|
|
|
hsi2c30-bus {
|
|
samsung,pins = "gpp15-0\0gpp15-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x34>;
|
|
};
|
|
|
|
hsi2c31-bus {
|
|
samsung,pins = "gpp15-2\0gpp15-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x36>;
|
|
};
|
|
|
|
spi0-bus {
|
|
samsung,pins = "gpp0-2\0gpp0-1\0gpp0-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x51>;
|
|
};
|
|
|
|
spi0-cs {
|
|
samsung,pins = "gpp0-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1b8>;
|
|
};
|
|
|
|
spi0-cs-func {
|
|
samsung,pins = "gpp0-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1b9>;
|
|
};
|
|
|
|
spi1-bus {
|
|
samsung,pins = "gpp1-2\0gpp1-1\0gpp1-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x52>;
|
|
};
|
|
|
|
spi1-cs {
|
|
samsung,pins = "gpp1-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1ba>;
|
|
};
|
|
|
|
spi1-cs-func {
|
|
samsung,pins = "gpp1-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1bb>;
|
|
};
|
|
|
|
spi2-bus {
|
|
samsung,pins = "gpp2-2\0gpp2-1\0gpp2-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x53>;
|
|
};
|
|
|
|
spi2-cs {
|
|
samsung,pins = "gpp2-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1bc>;
|
|
};
|
|
|
|
spi2-cs-func {
|
|
samsung,pins = "gpp2-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1bd>;
|
|
};
|
|
|
|
spi3-bus {
|
|
samsung,pins = "gpp3-2\0gpp3-1\0gpp3-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x54>;
|
|
};
|
|
|
|
spi3-cs {
|
|
samsung,pins = "gpp3-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1be>;
|
|
};
|
|
|
|
spi3-cs-func {
|
|
samsung,pins = "gpp3-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1bf>;
|
|
};
|
|
|
|
spi4-bus {
|
|
samsung,pins = "gpp4-2\0gpp4-1\0gpp4-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x55>;
|
|
};
|
|
|
|
spi4-cs {
|
|
samsung,pins = "gpp4-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1c0>;
|
|
};
|
|
|
|
spi4-cs-func {
|
|
samsung,pins = "gpp4-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1c1>;
|
|
};
|
|
|
|
spi5-bus {
|
|
samsung,pins = "gpp5-2\0gpp5-1\0gpp5-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x56>;
|
|
};
|
|
|
|
spi5-cs {
|
|
samsung,pins = "gpp5-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1c2>;
|
|
};
|
|
|
|
spi5-cs-func {
|
|
samsung,pins = "gpp5-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1c3>;
|
|
};
|
|
|
|
spi13-bus {
|
|
samsung,pins = "gpp13-2\0gpp13-1\0gpp13-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x5e>;
|
|
};
|
|
|
|
spi13-cs {
|
|
samsung,pins = "gpp13-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1c4>;
|
|
};
|
|
|
|
spi13-cs-func {
|
|
samsung,pins = "gpp13-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1c5>;
|
|
};
|
|
|
|
spi14-bus {
|
|
samsung,pins = "gpp14-2\0gpp14-1\0gpp14-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x5f>;
|
|
};
|
|
|
|
spi14-cs {
|
|
samsung,pins = "gpp14-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1c6>;
|
|
};
|
|
|
|
spi14-cs-func {
|
|
samsung,pins = "gpp14-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1c7>;
|
|
};
|
|
|
|
spi15-bus {
|
|
samsung,pins = "gpp15-2\0gpp15-1\0gpp15-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x60>;
|
|
};
|
|
|
|
spi15-cs {
|
|
samsung,pins = "gpp15-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1c8>;
|
|
};
|
|
|
|
spi15-cs-func {
|
|
samsung,pins = "gpp15-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1c9>;
|
|
};
|
|
|
|
uart2-bus {
|
|
samsung,pins = "gpp0-0\0gpp0-1\0gpp0-2\0gpp0-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x6d>;
|
|
};
|
|
|
|
uart2-bus-dual {
|
|
samsung,pins = "gpp0-0\0gpp0-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1ca>;
|
|
};
|
|
|
|
uart3-bus {
|
|
samsung,pins = "gpp1-0\0gpp1-1\0gpp1-2\0gpp1-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x6e>;
|
|
};
|
|
|
|
uart3-bus-dual {
|
|
samsung,pins = "gpp1-0\0gpp1-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1cb>;
|
|
};
|
|
|
|
uart4-bus {
|
|
samsung,pins = "gpp2-0\0gpp2-1\0gpp2-2\0gpp2-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x6f>;
|
|
};
|
|
|
|
uart4-bus-dual {
|
|
samsung,pins = "gpp2-0\0gpp2-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1cc>;
|
|
};
|
|
|
|
uart5-bus {
|
|
samsung,pins = "gpp3-0\0gpp3-1\0gpp3-2\0gpp3-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x70>;
|
|
};
|
|
|
|
uart5-bus-dual {
|
|
samsung,pins = "gpp3-0\0gpp3-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1cd>;
|
|
};
|
|
|
|
uart6-bus {
|
|
samsung,pins = "gpp4-0\0gpp4-1\0gpp4-2\0gpp4-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x71>;
|
|
};
|
|
|
|
uart6-bus-dual {
|
|
samsung,pins = "gpp4-0\0gpp4-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1ce>;
|
|
};
|
|
|
|
uart7-bus {
|
|
samsung,pins = "gpp5-0\0gpp5-1\0gpp5-2\0gpp5-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x72>;
|
|
};
|
|
|
|
uart7-bus-dual {
|
|
samsung,pins = "gpp5-0\0gpp5-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1cf>;
|
|
};
|
|
|
|
uart15-bus {
|
|
samsung,pins = "gpp13-0\0gpp13-1\0gpp13-2\0gpp13-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x7a>;
|
|
};
|
|
|
|
uart15-bus-dual {
|
|
samsung,pins = "gpp13-0\0gpp13-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1d0>;
|
|
};
|
|
|
|
uart16-bus {
|
|
samsung,pins = "gpp14-0\0gpp14-1\0gpp14-2\0gpp14-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x7b>;
|
|
};
|
|
|
|
uart16-bus-dual {
|
|
samsung,pins = "gpp14-0\0gpp14-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1d1>;
|
|
};
|
|
|
|
uart17-bus {
|
|
samsung,pins = "gpp15-0\0gpp15-1\0gpp15-2\0gpp15-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x7c>;
|
|
};
|
|
|
|
uart17-bus-dual {
|
|
samsung,pins = "gpp15-0\0gpp15-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1d2>;
|
|
};
|
|
};
|
|
|
|
pinctrl@10730000 {
|
|
compatible = "samsung,exynos2100-pinctrl";
|
|
reg = <0x00 0x10730000 0x1000>;
|
|
interrupts = <0x00 0x216 0x04>;
|
|
phandle = <0x1d3>;
|
|
|
|
gpb3 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1d4>;
|
|
};
|
|
|
|
gpb4 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1d5>;
|
|
};
|
|
|
|
gpp11 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x28>;
|
|
};
|
|
|
|
gpp12 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x2c>;
|
|
};
|
|
|
|
gpp16 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x38>;
|
|
};
|
|
|
|
gpp17 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x3b>;
|
|
};
|
|
|
|
gpp18 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x3e>;
|
|
};
|
|
|
|
gpg1 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0xc8>;
|
|
};
|
|
|
|
gpg2 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0xb9>;
|
|
};
|
|
|
|
gpb0 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1d6>;
|
|
};
|
|
|
|
gpb1 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1d7>;
|
|
};
|
|
|
|
gpb2 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1d8>;
|
|
};
|
|
|
|
hsi2c22-bus {
|
|
samsung,pins = "gpp11-0\0gpp11-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x27>;
|
|
};
|
|
|
|
hsi2c23-bus {
|
|
samsung,pins = "gpp11-2\0gpp11-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x29>;
|
|
};
|
|
|
|
hsi2c24-bus {
|
|
samsung,pins = "gpp12-0\0gpp12-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x2b>;
|
|
};
|
|
|
|
hsi2c25-bus {
|
|
samsung,pins = "gpp12-2\0gpp12-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x2d>;
|
|
};
|
|
|
|
hsi2c32-bus {
|
|
samsung,pins = "gpp16-0\0gpp16-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x37>;
|
|
};
|
|
|
|
hsi2c33-bus {
|
|
samsung,pins = "gpp16-2\0gpp16-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x39>;
|
|
};
|
|
|
|
hsi2c34-bus {
|
|
samsung,pins = "gpp17-0\0gpp17-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x3a>;
|
|
};
|
|
|
|
hsi2c35-bus {
|
|
samsung,pins = "gpp17-2\0gpp17-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x3c>;
|
|
};
|
|
|
|
hsi2c36-bus {
|
|
samsung,pins = "gpp18-0\0gpp18-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x3d>;
|
|
};
|
|
|
|
hsi2c37-bus {
|
|
samsung,pins = "gpp18-2\0gpp18-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x3f>;
|
|
};
|
|
|
|
spi11-bus {
|
|
samsung,pins = "gpp11-2\0gpp11-1\0gpp11-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x5c>;
|
|
};
|
|
|
|
spi11-cs {
|
|
samsung,pins = "gpp11-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1d9>;
|
|
};
|
|
|
|
spi11-cs-func {
|
|
samsung,pins = "gpp11-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1da>;
|
|
};
|
|
|
|
spi12-bus {
|
|
samsung,pins = "gpp12-2\0gpp12-1\0gpp12-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x5d>;
|
|
};
|
|
|
|
spi12-cs {
|
|
samsung,pins = "gpp12-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1db>;
|
|
};
|
|
|
|
spi12-cs-func {
|
|
samsung,pins = "gpp12-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1dc>;
|
|
};
|
|
|
|
spi16-bus {
|
|
samsung,pins = "gpp16-2\0gpp16-1\0gpp16-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x61>;
|
|
};
|
|
|
|
spi16-cs {
|
|
samsung,pins = "gpp16-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1dd>;
|
|
};
|
|
|
|
spi16-cs-func {
|
|
samsung,pins = "gpp16-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1de>;
|
|
};
|
|
|
|
spi17-bus {
|
|
samsung,pins = "gpp17-2\0gpp17-1\0gpp17-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x62>;
|
|
};
|
|
|
|
spi17-cs {
|
|
samsung,pins = "gpp17-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1df>;
|
|
};
|
|
|
|
spi17-cs-func {
|
|
samsung,pins = "gpp17-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1e0>;
|
|
};
|
|
|
|
spi18-bus {
|
|
samsung,pins = "gpp18-2\0gpp18-1\0gpp18-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x63>;
|
|
};
|
|
|
|
spi18-cs {
|
|
samsung,pins = "gpp18-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1e1>;
|
|
};
|
|
|
|
spi18-cs-func {
|
|
samsung,pins = "gpp18-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1e2>;
|
|
};
|
|
|
|
uart13-bus {
|
|
samsung,pins = "gpp11-3\0gpp11-2\0gpp11-1\0gpp11-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x78>;
|
|
};
|
|
|
|
uart13-bus-dual {
|
|
samsung,pins = "gpp11-0\0gpp11-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1e3>;
|
|
};
|
|
|
|
uart14-bus {
|
|
samsung,pins = "gpp12-3\0gpp12-2\0gpp12-1\0gpp12-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x79>;
|
|
};
|
|
|
|
uart14-bus-dual {
|
|
samsung,pins = "gpp12-0\0gpp12-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1e4>;
|
|
};
|
|
|
|
uart18-bus {
|
|
samsung,pins = "gpp16-3\0gpp16-2\0gpp16-1\0gpp16-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x7d>;
|
|
};
|
|
|
|
uart18-bus-dual {
|
|
samsung,pins = "gpp16-0\0gpp16-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1e5>;
|
|
};
|
|
|
|
uart19-bus {
|
|
samsung,pins = "gpp17-3\0gpp17-2\0gpp17-1\0gpp17-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x7e>;
|
|
};
|
|
|
|
uart19-bus-dual {
|
|
samsung,pins = "gpp17-0\0gpp17-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1e6>;
|
|
};
|
|
|
|
uart20-bus {
|
|
samsung,pins = "gpp18-3\0gpp18-2\0gpp18-1\0gpp18-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x7f>;
|
|
};
|
|
|
|
uart20-bus-dual {
|
|
samsung,pins = "gpp18-0\0gpp18-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1e7>;
|
|
};
|
|
|
|
aud-i2s0-bus {
|
|
samsung,pins = "gpb0-0\0gpb0-1\0gpb0-2\0gpb0-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x150>;
|
|
};
|
|
|
|
aud-i2s0-idle {
|
|
samsung,pins = "gpb0-0\0gpb0-1\0gpb0-2\0gpb0-3";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x01>;
|
|
phandle = <0x151>;
|
|
};
|
|
|
|
aud-i2s1-bus {
|
|
samsung,pins = "gpb1-0\0gpb1-1\0gpb1-2\0gpb1-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x152>;
|
|
};
|
|
|
|
aud-i2s1-idle {
|
|
samsung,pins = "gpb1-0\0gpb1-1\0gpb1-2\0gpb1-3";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x01>;
|
|
phandle = <0x153>;
|
|
};
|
|
|
|
aud-i2s2-bus {
|
|
samsung,pins = "gpb2-0\0gpb2-1\0gpb2-2\0gpb2-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x154>;
|
|
};
|
|
|
|
aud-i2s2-idle {
|
|
samsung,pins = "gpb2-0\0gpb2-1\0gpb2-2\0gpb2-3";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x01>;
|
|
phandle = <0x155>;
|
|
};
|
|
|
|
aud-i2s3-bus {
|
|
samsung,pins = "gpb3-0\0gpb3-1\0gpb3-2\0gpb3-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x156>;
|
|
};
|
|
|
|
aud-i2s3-idle {
|
|
samsung,pins = "gpb3-0\0gpb3-1\0gpb3-2\0gpb3-3";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x01>;
|
|
phandle = <0x157>;
|
|
};
|
|
|
|
aud-i2s4-bus {
|
|
samsung,pins = "gpb4-0\0gpb4-1\0gpb4-2\0gpb4-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x158>;
|
|
};
|
|
|
|
aud-i2s4-idle {
|
|
samsung,pins = "gpb4-0\0gpb4-1\0gpb4-2\0gpb4-3";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x01>;
|
|
phandle = <0x159>;
|
|
};
|
|
|
|
aud-dsd-bus {
|
|
samsung,pins = "gpb1-0\0gpb1-1\0gpb1-2";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x1e8>;
|
|
};
|
|
|
|
aud-dsd-idle {
|
|
samsung,pins = "gpb1-0\0gpb1-1\0gpb1-2";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x01>;
|
|
phandle = <0x1e9>;
|
|
};
|
|
|
|
decon_0_te_on {
|
|
samsung,pins = "gpg1-4";
|
|
samsung,pin-function = <0x0f>;
|
|
phandle = <0xc6>;
|
|
};
|
|
|
|
decon_0_te_off {
|
|
samsung,pins = "gpg1-4";
|
|
samsung,pin-function = <0x00>;
|
|
phandle = <0xc7>;
|
|
};
|
|
|
|
sensor-mclk0-out {
|
|
samsung,pins = "gpg1-0";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1ea>;
|
|
};
|
|
|
|
sensor-mclk1-out {
|
|
samsung,pins = "gpg1-1";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1eb>;
|
|
};
|
|
|
|
sensor-mclk2-out {
|
|
samsung,pins = "gpg1-2";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1ec>;
|
|
};
|
|
|
|
sensor-mclk3-out {
|
|
samsung,pins = "gpg1-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1ed>;
|
|
};
|
|
|
|
sensor-mclk4-out {
|
|
samsung,pins = "gpg2-1";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1ee>;
|
|
};
|
|
|
|
sensor-mclk5-out {
|
|
samsung,pins = "gpg2-2";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1ef>;
|
|
};
|
|
|
|
sensor-mclk0-fn {
|
|
samsung,pins = "gpg1-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1f0>;
|
|
};
|
|
|
|
sensor-mclk1-fn {
|
|
samsung,pins = "gpg1-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1f1>;
|
|
};
|
|
|
|
sensor-mclk2-fn {
|
|
samsung,pins = "gpg1-2";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1f2>;
|
|
};
|
|
|
|
sensor-mclk3-fn {
|
|
samsung,pins = "gpg1-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1f3>;
|
|
};
|
|
|
|
sensor-mclk4-fn {
|
|
samsung,pins = "gpg2-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1f4>;
|
|
};
|
|
|
|
sensor-mclk5-fn {
|
|
samsung,pins = "gpg2-2";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1f5>;
|
|
};
|
|
|
|
ufs-boot-ldo {
|
|
samsung,pins = "gpg2-0";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x03>;
|
|
samsung,pin-pud-pdn = <0x00>;
|
|
phandle = <0xb6>;
|
|
};
|
|
};
|
|
|
|
pinctrl@11D30000 {
|
|
compatible = "samsung,exynos2100-pinctrl";
|
|
reg = <0x00 0x11d30000 0x1000>;
|
|
interrupts = <0x00 0x227 0x04>;
|
|
phandle = <0x1f6>;
|
|
|
|
gpp6 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x18>;
|
|
};
|
|
|
|
gpp7 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1b>;
|
|
};
|
|
|
|
gpp8 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x1e>;
|
|
};
|
|
|
|
gpp9 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x21>;
|
|
};
|
|
|
|
gpp10 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x24>;
|
|
};
|
|
|
|
hsi2c12-bus {
|
|
samsung,pins = "gpp6-0\0gpp6-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x17>;
|
|
};
|
|
|
|
hsi2c13-bus {
|
|
samsung,pins = "gpp6-2\0gpp6-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x19>;
|
|
};
|
|
|
|
hsi2c14-bus {
|
|
samsung,pins = "gpp7-0\0gpp7-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1a>;
|
|
};
|
|
|
|
hsi2c15-bus {
|
|
samsung,pins = "gpp7-2\0gpp7-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1c>;
|
|
};
|
|
|
|
hsi2c16-bus {
|
|
samsung,pins = "gpp8-0\0gpp8-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1d>;
|
|
};
|
|
|
|
hsi2c17-bus {
|
|
samsung,pins = "gpp8-2\0gpp8-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1f>;
|
|
};
|
|
|
|
hsi2c18-bus {
|
|
samsung,pins = "gpp9-0\0gpp9-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x20>;
|
|
};
|
|
|
|
hsi2c19-bus {
|
|
samsung,pins = "gpp9-2\0gpp9-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x22>;
|
|
};
|
|
|
|
hsi2c20-bus {
|
|
samsung,pins = "gpp10-0\0gpp10-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x23>;
|
|
};
|
|
|
|
hsi2c21-bus {
|
|
samsung,pins = "gpp10-2\0gpp10-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x25>;
|
|
};
|
|
|
|
spi6-bus {
|
|
samsung,pins = "gpp6-2\0gpp6-1\0gpp6-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x57>;
|
|
};
|
|
|
|
spi6-cs {
|
|
samsung,pins = "gpp6-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1f7>;
|
|
};
|
|
|
|
spi6-cs-func {
|
|
samsung,pins = "gpp6-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1f8>;
|
|
};
|
|
|
|
spi7-bus {
|
|
samsung,pins = "gpp7-2\0gpp7-1\0gpp7-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x58>;
|
|
};
|
|
|
|
spi7-cs {
|
|
samsung,pins = "gpp7-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1f9>;
|
|
};
|
|
|
|
spi7-cs-func {
|
|
samsung,pins = "gpp7-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1fa>;
|
|
};
|
|
|
|
spi8-bus {
|
|
samsung,pins = "gpp8-2\0gpp8-1\0gpp8-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x59>;
|
|
};
|
|
|
|
spi8-cs {
|
|
samsung,pins = "gpp8-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1fb>;
|
|
};
|
|
|
|
spi8-cs-func {
|
|
samsung,pins = "gpp8-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1fc>;
|
|
};
|
|
|
|
spi9-bus {
|
|
samsung,pins = "gpp9-2\0gpp9-1\0gpp9-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x5a>;
|
|
};
|
|
|
|
spi9-cs {
|
|
samsung,pins = "gpp9-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1fd>;
|
|
};
|
|
|
|
spi9-cs-func {
|
|
samsung,pins = "gpp9-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1fe>;
|
|
};
|
|
|
|
spi10-bus {
|
|
samsung,pins = "gpp10-2\0gpp10-1\0gpp10-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x5b>;
|
|
};
|
|
|
|
spi10-cs {
|
|
samsung,pins = "gpp10-3";
|
|
samsung,pin-function = <0x01>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x1ff>;
|
|
};
|
|
|
|
spi10-cs-func {
|
|
samsung,pins = "gpp10-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-drv = <0x00>;
|
|
phandle = <0x200>;
|
|
};
|
|
|
|
uart8-bus {
|
|
samsung,pins = "gpp6-3\0gpp6-2\0gpp6-1\0gpp6-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x73>;
|
|
};
|
|
|
|
uart8-bus-dual {
|
|
samsung,pins = "gpp6-0\0gpp6-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x201>;
|
|
};
|
|
|
|
uart9-bus {
|
|
samsung,pins = "gpp7-3\0gpp7-2\0gpp7-1\0gpp7-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x74>;
|
|
};
|
|
|
|
uart9-bus-dual {
|
|
samsung,pins = "gpp7-0\0gpp7-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x202>;
|
|
};
|
|
|
|
uart10-bus {
|
|
samsung,pins = "gpp8-3\0gpp8-2\0gpp8-1\0gpp8-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x75>;
|
|
};
|
|
|
|
uart10-bus-dual {
|
|
samsung,pins = "gpp8-0\0gpp8-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x203>;
|
|
};
|
|
|
|
uart11-bus {
|
|
samsung,pins = "gpp9-3\0gpp9-2\0gpp9-1\0gpp9-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x76>;
|
|
};
|
|
|
|
uart11-bus-dual {
|
|
samsung,pins = "gpp9-0\0gpp9-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x204>;
|
|
};
|
|
|
|
uart12-bus {
|
|
samsung,pins = "gpp10-3\0gpp10-2\0gpp10-1\0gpp10-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x77>;
|
|
};
|
|
|
|
uart12-bus-dual {
|
|
samsung,pins = "gpp10-0\0gpp10-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x00>;
|
|
phandle = <0x205>;
|
|
};
|
|
};
|
|
|
|
pinctrl@15580000 {
|
|
compatible = "samsung,exynos2100-pinctrl";
|
|
reg = <0x00 0x15580000 0x1000>;
|
|
phandle = <0x206>;
|
|
|
|
gpv0 {
|
|
gpio-controller;
|
|
#gpio-cells = <0x02>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x02>;
|
|
phandle = <0x207>;
|
|
};
|
|
|
|
dmic-bus-clk {
|
|
samsung,pins = "gpv0-0";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0x15e>;
|
|
};
|
|
|
|
dmic-bus-clk-idle {
|
|
samsung,pins = "gpv0-0";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0x163>;
|
|
};
|
|
|
|
dmic-bus-clk1 {
|
|
samsung,pins = "gpv0-1";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0x160>;
|
|
};
|
|
|
|
dmic-bus-clk1-idle {
|
|
samsung,pins = "gpv0-1";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0x165>;
|
|
};
|
|
|
|
dmic-bus-clk2 {
|
|
samsung,pins = "gpv0-2";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0x167>;
|
|
};
|
|
|
|
dmic-bus-clk2-idle {
|
|
samsung,pins = "gpv0-2";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0x169>;
|
|
};
|
|
|
|
dmic-pdm {
|
|
samsung,pins = "gpv0-3";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0x15f>;
|
|
};
|
|
|
|
amic-pdm {
|
|
samsung,pins = "gpv0-3";
|
|
samsung,pin-function = <0x03>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0x161>;
|
|
};
|
|
|
|
dmic-pdm-idle {
|
|
samsung,pins = "gpv0-3";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0x164>;
|
|
};
|
|
|
|
dmic-pdm1-bus {
|
|
samsung,pins = "gpv0-4";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0x162>;
|
|
};
|
|
|
|
dmic-pdm1-idle {
|
|
samsung,pins = "gpv0-4";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0x166>;
|
|
};
|
|
|
|
dmic-pdm2-bus {
|
|
samsung,pins = "gpv0-5";
|
|
samsung,pin-function = <0x02>;
|
|
samsung,pin-pud = <0x01>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0x168>;
|
|
};
|
|
|
|
dmic-pdm2-idle {
|
|
samsung,pins = "gpv0-5";
|
|
samsung,pin-function = <0x00>;
|
|
samsung,pin-pud = <0x00>;
|
|
samsung,pin-con-pdn = <0x02>;
|
|
phandle = <0x16a>;
|
|
};
|
|
};
|
|
|
|
aliases {
|
|
hsi2c0 = "/hsi2c@10550000";
|
|
hsi2c1 = "/hsi2c@10560000";
|
|
hsi2c2 = "/hsi2c@10570000";
|
|
hsi2c3 = "/hsi2c@10580000";
|
|
hsi2c4 = "/hsi2c@10590000";
|
|
hsi2c5 = "/hsi2c@105A0000";
|
|
hsi2c6 = "/hsi2c@105B0000";
|
|
hsi2c7 = "/hsi2c@105C0000";
|
|
hsi2c8 = "/hsi2c@105D0000";
|
|
hsi2c9 = "/hsi2c@105E0000";
|
|
hsi2c10 = "/hsi2c@105F0000";
|
|
hsi2c11 = "/hsi2c@10600000";
|
|
hsi2c12 = "/hsi2c@11EA0000";
|
|
hsi2c13 = "/hsi2c@11EB0000";
|
|
hsi2c14 = "/hsi2c@11EC0000";
|
|
hsi2c15 = "/hsi2c@11ED0000";
|
|
hsi2c16 = "/hsi2c@11EE0000";
|
|
hsi2c17 = "/hsi2c@11EF0000";
|
|
hsi2c18 = "/hsi2c@11f00000";
|
|
hsi2c19 = "/hsi2c@11f10000";
|
|
hsi2c20 = "/hsi2c@11f20000";
|
|
hsi2c21 = "/hsi2c@11f30000";
|
|
hsi2c22 = "/hsi2c@10940000";
|
|
hsi2c23 = "/hsi2c@10950000";
|
|
hsi2c24 = "/hsi2c@109C0000";
|
|
hsi2c25 = "/hsi2c@109D0000";
|
|
hsi2c26 = "/hsi2c@10630000";
|
|
hsi2c27 = "/hsi2c@10640000";
|
|
hsi2c28 = "/hsi2c@10650000";
|
|
hsi2c29 = "/hsi2c@10660000";
|
|
hsi2c30 = "/hsi2c@10670000";
|
|
hsi2c31 = "/hsi2c@10680000";
|
|
hsi2c32 = "/hsi2c@10960000";
|
|
hsi2c33 = "/hsi2c@10970000";
|
|
hsi2c34 = "/hsi2c@10990000";
|
|
hsi2c35 = "/hsi2c@109A0000";
|
|
hsi2c36 = "/hsi2c@109E0000";
|
|
hsi2c37 = "/hsi2c@109F0000";
|
|
hsi2c38 = "/hsi2c@14F00000";
|
|
hsi2c39 = "/hsi2c@14F10000";
|
|
hsi2c40 = "/hsi2c@14F20000";
|
|
hsi2c41 = "/hsi2c@14F30000";
|
|
hsi2c42 = "/hsi2c@14F40000";
|
|
hsi2c43 = "/hsi2c@14F50000";
|
|
hsi2c44 = "/hsi2c@14F60000";
|
|
hsi2c45 = "/hsi2c@14F70000";
|
|
spi0 = "/spi@10550000";
|
|
spi1 = "/spi@10570000";
|
|
spi2 = "/spi@10590000";
|
|
spi3 = "/spi@105B0000";
|
|
spi4 = "/spi@105D0000";
|
|
spi5 = "/spi@105F0000";
|
|
spi6 = "/spi@11EA0000";
|
|
spi7 = "/spi@11EC0000";
|
|
spi8 = "/spi@11EE0000";
|
|
spi9 = "/spi@11f00000";
|
|
spi10 = "/spi@11f20000";
|
|
spi11 = "/spi@10940000";
|
|
spi12 = "/spi@109C0000";
|
|
spi13 = "/spi@10630000";
|
|
spi14 = "/spi@10650000";
|
|
spi15 = "/spi@10670000";
|
|
spi16 = "/spi@10960000";
|
|
spi17 = "/spi@10990000";
|
|
spi18 = "/spi@109E0000";
|
|
spi19 = "/spi@14F00000";
|
|
spi20 = "/spi@14F20000";
|
|
spi21 = "/spi@14F40000";
|
|
spi22 = "/spi@14F60000";
|
|
uart0 = "/uart@10540000";
|
|
uart1 = "/uart@10840000";
|
|
uart2 = "/uart@10550000";
|
|
uart3 = "/uart@10570000";
|
|
uart4 = "/uart@10590000";
|
|
uart5 = "/uart@105B0000";
|
|
uart6 = "/uart@105D0000";
|
|
uart7 = "/uart@105F0000";
|
|
uart8 = "/uart@11EA0000";
|
|
uart9 = "/uart@11EC0000";
|
|
uart10 = "/uart@11EE0000";
|
|
uart11 = "/uart@11f00000";
|
|
uart12 = "/uart@11f20000";
|
|
uart13 = "/uart@10940000";
|
|
uart14 = "/uart@109C0000";
|
|
uart15 = "/uart@10630000";
|
|
uart16 = "/uart@10650000";
|
|
uart17 = "/uart@10670000";
|
|
uart18 = "/uart@10960000";
|
|
uart19 = "/uart@10990000";
|
|
uart20 = "/uart@109E0000";
|
|
uart21 = "/uart@14F00000";
|
|
uart22 = "/uart@14F20000";
|
|
uart23 = "/uart@14F40000";
|
|
uart24 = "/uart@14F60000";
|
|
usi18 = "/usi@10722008";
|
|
panel0 = "/panel_0";
|
|
dpp0 = "/dpp@0x19CB0000";
|
|
dpp1 = "/dpp@0x19CB1000";
|
|
dpp2 = "/dpp@0x19CB2000";
|
|
dpp3 = "/dpp@0x19CB3000";
|
|
dpp4 = "/dpp@0x19CB4000";
|
|
dpp5 = "/dpp@0x19CB5000";
|
|
dpp6 = "/dpp@0x19CB6000";
|
|
dpp7 = "/dpp@0x19CB7000";
|
|
dpp8 = "/dpp@0x1AEB1000";
|
|
dpp9 = "/dpp@0x1AEB2000";
|
|
dpp10 = "/dpp@0x1AEB3000";
|
|
dpp11 = "/dpp@0x1AEB4000";
|
|
dpp12 = "/dpp@0x1AEB5000";
|
|
dpp13 = "/dpp@0x1AEB6000";
|
|
dpp14 = "/dpp@0x1AEB7000";
|
|
dpp15 = "/dpp@0x1AEB8000";
|
|
dpp16 = "/dpp@0x19CBC000";
|
|
fcmd0 = "/fcmd@0x19CBC000";
|
|
fcmd1 = "/fcmd@0x19CBD000";
|
|
fcmd2 = "/fcmd@0x1AEBC000";
|
|
dsim0 = "/dsim@0x19EC0000";
|
|
displayport = "/displayport@0x10AB0000";
|
|
decon0 = "/decon_0@0x19F00000";
|
|
decon1 = "/decon_1@0x19F01000";
|
|
decon2 = "/decon_2@0x19F02000";
|
|
decon3 = "/decon_3@0x19F03000";
|
|
smfc0 = "/smfc@18940000";
|
|
smfc1 = "/smfc@18950000";
|
|
scaler0 = "/scaler@18960000";
|
|
pinctrl0 = "/pinctrl@15850000";
|
|
pinctrl1 = "/pinctrl@14E30000";
|
|
pinctrl2 = "/pinctrl@14EC0000";
|
|
pinctrl3 = "/pinctrl@11040000";
|
|
pinctrl4 = "/pinctrl@10430000";
|
|
pinctrl5 = "/pinctrl@10730000";
|
|
pinctrl6 = "/pinctrl@11D30000";
|
|
pinctrl7 = "/pinctrl@15580000";
|
|
};
|
|
|
|
syscon@10421000 {
|
|
compatible = "samsung,exynos2100-sysreg-peri\0syscon";
|
|
reg = <0x00 0x10421000 0x100>;
|
|
phandle = <0x02>;
|
|
};
|
|
|
|
syscon@10721000 {
|
|
compatible = "samsung,exynos2100-sysreg-peri\0syscon";
|
|
reg = <0x00 0x10721000 0x100>;
|
|
phandle = <0x26>;
|
|
};
|
|
|
|
syscon@10722000 {
|
|
compatible = "samsung,exynos2100-sysreg-peri\0syscon";
|
|
reg = <0x00 0x10722000 0x100>;
|
|
phandle = <0x2a>;
|
|
};
|
|
|
|
syscon@11D21000 {
|
|
compatible = "samsung,exynos2100-sysreg-peri\0syscon";
|
|
reg = <0x00 0x11d21000 0x100>;
|
|
phandle = <0x16>;
|
|
};
|
|
|
|
syscon@14E22000 {
|
|
compatible = "samsung,exynos2100-sysreg-cmgp\0syscon";
|
|
reg = <0x00 0x14e22000 0x100>;
|
|
phandle = <0x40>;
|
|
};
|
|
|
|
usi@10722008 {
|
|
compatible = "samsung,exynos-usi-v2";
|
|
reg = <0x00 0x10722008 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x208>;
|
|
};
|
|
|
|
hsi2c@10550000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x204 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x04>;
|
|
reg = <0x00 0x10550000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x03>;
|
|
clocks = <0x04 0x6ef 0x04 0x6db>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x05 0x00 0x01>;
|
|
gpio_sda = <0x05 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x209>;
|
|
};
|
|
|
|
hsi2c@10560000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x203 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x08>;
|
|
reg = <0x00 0x10560000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x06>;
|
|
clocks = <0x04 0x6f5 0x04 0x6dc>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x05 0x02 0x01>;
|
|
gpio_sda = <0x05 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x20a>;
|
|
};
|
|
|
|
hsi2c@10570000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x206 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x0c>;
|
|
reg = <0x00 0x10570000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x07>;
|
|
clocks = <0x04 0x6f0 0x04 0x6dd>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x08 0x00 0x01>;
|
|
gpio_sda = <0x08 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x20b>;
|
|
};
|
|
|
|
hsi2c@10580000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x205 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x10>;
|
|
reg = <0x00 0x10580000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x09>;
|
|
clocks = <0x04 0x6f5 0x04 0x6de>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x08 0x02 0x01>;
|
|
gpio_sda = <0x08 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x20c>;
|
|
};
|
|
|
|
hsi2c@10590000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x208 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x14>;
|
|
reg = <0x00 0x10590000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x0a>;
|
|
clocks = <0x04 0x6f1 0x04 0x6df>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x0b 0x00 0x01>;
|
|
gpio_sda = <0x0b 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x20d>;
|
|
};
|
|
|
|
hsi2c@105A0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x207 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x18>;
|
|
reg = <0x00 0x105a0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x0c>;
|
|
clocks = <0x04 0x6f5 0x04 0x6e0>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x0b 0x02 0x01>;
|
|
gpio_sda = <0x0b 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x20e>;
|
|
};
|
|
|
|
hsi2c@105B0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x20a 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x1c>;
|
|
reg = <0x00 0x105b0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x0d>;
|
|
clocks = <0x04 0x6f2 0x04 0x6e1>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x0e 0x00 0x01>;
|
|
gpio_sda = <0x0e 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x20f>;
|
|
};
|
|
|
|
hsi2c@105C0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x209 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x20>;
|
|
reg = <0x00 0x105c0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x0f>;
|
|
clocks = <0x04 0x6f5 0x04 0x6e2>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x0e 0x02 0x01>;
|
|
gpio_sda = <0x0e 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x210>;
|
|
};
|
|
|
|
hsi2c@105D0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x20c 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x24>;
|
|
reg = <0x00 0x105d0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x10>;
|
|
clocks = <0x04 0x6f3 0x04 0x6e3>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x11 0x00 0x01>;
|
|
gpio_sda = <0x11 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x211>;
|
|
};
|
|
|
|
hsi2c@105E0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x20b 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x28>;
|
|
reg = <0x00 0x105e0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x12>;
|
|
clocks = <0x04 0x6f5 0x04 0x6e4>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x11 0x02 0x01>;
|
|
gpio_sda = <0x11 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x212>;
|
|
};
|
|
|
|
hsi2c@105F0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x20e 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x2c>;
|
|
reg = <0x00 0x105f0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x13>;
|
|
clocks = <0x04 0x6f4 0x04 0x6e5>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x14 0x00 0x01>;
|
|
gpio_sda = <0x14 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x213>;
|
|
};
|
|
|
|
hsi2c@10600000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x20d 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x30>;
|
|
reg = <0x00 0x10600000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x15>;
|
|
clocks = <0x04 0x6f5 0x04 0x6e6>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x14 0x02 0x01>;
|
|
gpio_sda = <0x14 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x214>;
|
|
};
|
|
|
|
hsi2c@11EA0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x229 0x04>;
|
|
samsung,usi-phandle = <0x16>;
|
|
samsung,usi-offset = <0x00>;
|
|
reg = <0x00 0x11ea0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x17>;
|
|
clocks = <0x04 0x7ab 0x04 0x7a2>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x18 0x00 0x01>;
|
|
gpio_sda = <0x18 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x215>;
|
|
};
|
|
|
|
hsi2c@11EB0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x228 0x04>;
|
|
samsung,usi-phandle = <0x16>;
|
|
samsung,usi-offset = <0x04>;
|
|
reg = <0x00 0x11eb0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x19>;
|
|
clocks = <0x04 0x7aa 0x04 0x7a6>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x18 0x02 0x01>;
|
|
gpio_sda = <0x18 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x216>;
|
|
};
|
|
|
|
hsi2c@11EC0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x22b 0x04>;
|
|
samsung,usi-phandle = <0x16>;
|
|
samsung,usi-offset = <0x08>;
|
|
reg = <0x00 0x11ec0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x1a>;
|
|
clocks = <0x04 0x7ac 0x04 0x7a3>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x1b 0x00 0x01>;
|
|
gpio_sda = <0x1b 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x217>;
|
|
};
|
|
|
|
hsi2c@11ED0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x22a 0x04>;
|
|
samsung,usi-phandle = <0x16>;
|
|
samsung,usi-offset = <0x0c>;
|
|
reg = <0x00 0x11ed0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x1c>;
|
|
clocks = <0x04 0x7aa 0x04 0x7a7>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x1b 0x02 0x01>;
|
|
gpio_sda = <0x1b 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x218>;
|
|
};
|
|
|
|
hsi2c@11EE0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x22d 0x04>;
|
|
samsung,usi-phandle = <0x16>;
|
|
samsung,usi-offset = <0x10>;
|
|
reg = <0x00 0x11ee0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x1d>;
|
|
clocks = <0x04 0x7a9 0x04 0x7a4>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x1e 0x00 0x01>;
|
|
gpio_sda = <0x1e 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x219>;
|
|
};
|
|
|
|
hsi2c@11EF0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x22c 0x04>;
|
|
samsung,usi-phandle = <0x16>;
|
|
samsung,usi-offset = <0x14>;
|
|
reg = <0x00 0x11ef0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x1f>;
|
|
clocks = <0x04 0x7aa 0x04 0x7a5>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x1e 0x02 0x01>;
|
|
gpio_sda = <0x1e 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x21a>;
|
|
};
|
|
|
|
hsi2c@11f00000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x115 0x04>;
|
|
samsung,usi-phandle = <0x16>;
|
|
samsung,usi-offset = <0x18>;
|
|
reg = <0x00 0x11f00000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x20>;
|
|
clocks = <0x04 0x7b1 0x04 0x7ad>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x21 0x00 0x01>;
|
|
gpio_sda = <0x21 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x21b>;
|
|
};
|
|
|
|
hsi2c@11f10000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x114 0x04>;
|
|
samsung,usi-phandle = <0x16>;
|
|
samsung,usi-offset = <0x1c>;
|
|
reg = <0x00 0x11f10000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x22>;
|
|
clocks = <0x04 0x7aa 0x04 0x7ae>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x21 0x02 0x01>;
|
|
gpio_sda = <0x21 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x21c>;
|
|
};
|
|
|
|
hsi2c@11f20000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x117 0x04>;
|
|
samsung,usi-phandle = <0x16>;
|
|
samsung,usi-offset = <0x20>;
|
|
reg = <0x00 0x11f20000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x23>;
|
|
clocks = <0x04 0x7b2 0x04 0x7af>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x24 0x00 0x01>;
|
|
gpio_sda = <0x24 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x21d>;
|
|
};
|
|
|
|
hsi2c@11f30000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x116 0x04>;
|
|
samsung,usi-phandle = <0x16>;
|
|
samsung,usi-offset = <0x24>;
|
|
reg = <0x00 0x11f30000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x25>;
|
|
clocks = <0x04 0x7aa 0x04 0x7b0>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x24 0x02 0x01>;
|
|
gpio_sda = <0x24 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x21e>;
|
|
};
|
|
|
|
hsi2c@10940000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x21c 0x04>;
|
|
samsung,usi-phandle = <0x26>;
|
|
samsung,usi-offset = <0x28>;
|
|
reg = <0x00 0x10940000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x27>;
|
|
clocks = <0x04 0x758 0x04 0x743>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x28 0x00 0x01>;
|
|
gpio_sda = <0x28 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x21f>;
|
|
};
|
|
|
|
hsi2c@10950000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x21b 0x04>;
|
|
samsung,usi-phandle = <0x26>;
|
|
samsung,usi-offset = <0x2c>;
|
|
reg = <0x00 0x10950000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x29>;
|
|
clocks = <0x04 0x753 0x04 0x744>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x28 0x02 0x01>;
|
|
gpio_sda = <0x28 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x220>;
|
|
};
|
|
|
|
hsi2c@109C0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x21e 0x04>;
|
|
samsung,usi-phandle = <0x2a>;
|
|
samsung,usi-offset = <0x00>;
|
|
reg = <0x00 0x109c0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x2b>;
|
|
clocks = <0x04 0x755 0x04 0x749>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x2c 0x00 0x01>;
|
|
gpio_sda = <0x2c 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x221>;
|
|
};
|
|
|
|
hsi2c@109D0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x21d 0x04>;
|
|
samsung,usi-phandle = <0x2a>;
|
|
samsung,usi-offset = <0x04>;
|
|
reg = <0x00 0x109d0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x2d>;
|
|
clocks = <0x04 0x753 0x04 0x74a>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x2c 0x02 0x01>;
|
|
gpio_sda = <0x2c 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x222>;
|
|
};
|
|
|
|
hsi2c@10630000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x210 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x3c>;
|
|
reg = <0x00 0x10630000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x2e>;
|
|
clocks = <0x04 0x6f7 0x04 0x6e7>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x2f 0x00 0x01>;
|
|
gpio_sda = <0x2f 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x223>;
|
|
};
|
|
|
|
hsi2c@10640000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x20f 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x40>;
|
|
reg = <0x00 0x10640000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x30>;
|
|
clocks = <0x04 0x6f5 0x04 0x6e8>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x2f 0x02 0x01>;
|
|
gpio_sda = <0x2f 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x224>;
|
|
};
|
|
|
|
hsi2c@10650000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x212 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x44>;
|
|
reg = <0x00 0x10650000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x31>;
|
|
clocks = <0x04 0x6f8 0x04 0x6e9>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x32 0x00 0x01>;
|
|
gpio_sda = <0x32 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x225>;
|
|
};
|
|
|
|
hsi2c@10660000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x211 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x48>;
|
|
reg = <0x00 0x10660000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x33>;
|
|
clocks = <0x04 0x6f5 0x04 0x6ea>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x32 0x02 0x01>;
|
|
gpio_sda = <0x32 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x226>;
|
|
};
|
|
|
|
hsi2c@10670000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x214 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x4c>;
|
|
reg = <0x00 0x10670000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x34>;
|
|
clocks = <0x04 0x6f9 0x04 0x6eb>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x35 0x00 0x01>;
|
|
gpio_sda = <0x35 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x227>;
|
|
};
|
|
|
|
hsi2c@10680000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x213 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x50>;
|
|
reg = <0x00 0x10680000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x36>;
|
|
clocks = <0x04 0x6f5 0x04 0x6ec>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x35 0x02 0x01>;
|
|
gpio_sda = <0x35 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x228>;
|
|
};
|
|
|
|
hsi2c@10960000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x221 0x04>;
|
|
samsung,usi-phandle = <0x26>;
|
|
samsung,usi-offset = <0x30>;
|
|
reg = <0x00 0x10960000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x37>;
|
|
clocks = <0x04 0x759 0x04 0x745>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x38 0x00 0x01>;
|
|
gpio_sda = <0x38 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x229>;
|
|
};
|
|
|
|
hsi2c@10970000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x21f 0x04>;
|
|
samsung,usi-phandle = <0x26>;
|
|
samsung,usi-offset = <0x34>;
|
|
reg = <0x00 0x10970000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x39>;
|
|
clocks = <0x04 0x753 0x04 0x746>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x38 0x02 0x01>;
|
|
gpio_sda = <0x38 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x22a>;
|
|
};
|
|
|
|
hsi2c@10990000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x224 0x04>;
|
|
samsung,usi-phandle = <0x26>;
|
|
samsung,usi-offset = <0x38>;
|
|
reg = <0x00 0x10990000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x3a>;
|
|
clocks = <0x04 0x75a 0x04 0x747>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x3b 0x00 0x01>;
|
|
gpio_sda = <0x3b 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x22b>;
|
|
};
|
|
|
|
hsi2c@109A0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x222 0x04>;
|
|
samsung,usi-phandle = <0x26>;
|
|
samsung,usi-offset = <0x3c>;
|
|
reg = <0x00 0x109a0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x3c>;
|
|
clocks = <0x04 0x753 0x04 0x748>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x3b 0x02 0x01>;
|
|
gpio_sda = <0x3b 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x22c>;
|
|
};
|
|
|
|
hsi2c@109E0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x226 0x04>;
|
|
samsung,usi-phandle = <0x2a>;
|
|
samsung,usi-offset = <0x08>;
|
|
reg = <0x00 0x109e0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x3d>;
|
|
clocks = <0x04 0x754 0x04 0x74b>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x3e 0x00 0x01>;
|
|
gpio_sda = <0x3e 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x22d>;
|
|
};
|
|
|
|
hsi2c@109F0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x225 0x04>;
|
|
samsung,usi-phandle = <0x2a>;
|
|
samsung,usi-offset = <0x0c>;
|
|
reg = <0x00 0x109f0000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x3f>;
|
|
clocks = <0x04 0x753 0x04 0x74c>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x3e 0x02 0x01>;
|
|
gpio_sda = <0x3e 0x03 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x22e>;
|
|
};
|
|
|
|
hsi2c@14F00000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x7c 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x00>;
|
|
reg = <0x00 0x14f00000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x41>;
|
|
clocks = <0x04 0x178 0x04 0x172>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x42 0x00 0x01>;
|
|
gpio_sda = <0x42 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x22f>;
|
|
};
|
|
|
|
hsi2c@14F10000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x77 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x04>;
|
|
reg = <0x00 0x14f10000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x43>;
|
|
clocks = <0x04 0x176 0x04 0x168>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x44 0x00 0x01>;
|
|
gpio_sda = <0x44 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x230>;
|
|
};
|
|
|
|
hsi2c@14F20000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x7d 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x10>;
|
|
reg = <0x00 0x14f20000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x45>;
|
|
clocks = <0x04 0x177 0x04 0x173>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x46 0x00 0x01>;
|
|
gpio_sda = <0x46 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x231>;
|
|
};
|
|
|
|
hsi2c@14F30000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x78 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x14>;
|
|
reg = <0x00 0x14f30000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x47>;
|
|
clocks = <0x04 0x17b 0x04 0x169>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x48 0x00 0x01>;
|
|
gpio_sda = <0x48 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x232>;
|
|
};
|
|
|
|
hsi2c@14F40000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x7e 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x20>;
|
|
reg = <0x00 0x14f40000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x49>;
|
|
clocks = <0x04 0x179 0x04 0x174>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x4a 0x00 0x01>;
|
|
gpio_sda = <0x4a 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x233>;
|
|
};
|
|
|
|
hsi2c@14F50000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x79 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x24>;
|
|
reg = <0x00 0x14f50000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x4b>;
|
|
clocks = <0x04 0x17c 0x04 0x16a>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x4c 0x00 0x01>;
|
|
gpio_sda = <0x4c 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x234>;
|
|
};
|
|
|
|
hsi2c@14F60000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x7f 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x30>;
|
|
reg = <0x00 0x14f60000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x4d>;
|
|
clocks = <0x04 0x17a 0x04 0x175>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x4e 0x00 0x01>;
|
|
gpio_sda = <0x4e 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x235>;
|
|
};
|
|
|
|
hsi2c@14F70000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
default-clk = <0xbebc200>;
|
|
samsung,scl-clk-stretching;
|
|
samsung,reset-before-trans;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x7a 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x34>;
|
|
reg = <0x00 0x14f70000 0x1000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x4f>;
|
|
clocks = <0x04 0x17d 0x04 0x16b>;
|
|
clock-names = "ipclk_hsi2c\0gate_hsi2c_clk";
|
|
gpio_scl = <0x50 0x00 0x01>;
|
|
gpio_sda = <0x50 0x01 0x01>;
|
|
status = "disabled";
|
|
phandle = <0x236>;
|
|
};
|
|
|
|
spi@10550000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dma-names = "tx\0rx";
|
|
interrupts = <0x00 0x204 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
clocks = <0x04 0x6db 0x04 0x6ef>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x51>;
|
|
samsung,usi-offset = <0x04>;
|
|
reg = <0x00 0x10550000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x237>;
|
|
};
|
|
|
|
spi@10570000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dma-names = "tx\0rx";
|
|
interrupts = <0x00 0x206 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
clocks = <0x04 0x6dd 0x04 0x6f0>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x52>;
|
|
samsung,usi-offset = <0x0c>;
|
|
reg = <0x00 0x10570000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x238>;
|
|
};
|
|
|
|
spi@10590000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dma-names = "tx\0rx";
|
|
interrupts = <0x00 0x208 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
clocks = <0x04 0x6df 0x04 0x6f1>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x53>;
|
|
samsung,usi-offset = <0x14>;
|
|
reg = <0x00 0x10590000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x239>;
|
|
};
|
|
|
|
spi@105B0000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dma-names = "tx\0rx";
|
|
interrupts = <0x00 0x20a 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
clocks = <0x04 0x6e1 0x04 0x6f2>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x54>;
|
|
samsung,usi-offset = <0x1c>;
|
|
reg = <0x00 0x105b0000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x23a>;
|
|
};
|
|
|
|
spi@105D0000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dma-names = "tx\0rx";
|
|
interrupts = <0x00 0x20c 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
clocks = <0x04 0x6e3 0x04 0x6f3>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x55>;
|
|
samsung,usi-offset = <0x24>;
|
|
reg = <0x00 0x105d0000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x23b>;
|
|
};
|
|
|
|
spi@105F0000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dma-names = "tx\0rx";
|
|
interrupts = <0x00 0x20e 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
clocks = <0x04 0x6e5 0x04 0x6f4>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x56>;
|
|
samsung,usi-offset = <0x2c>;
|
|
reg = <0x00 0x105f0000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x23c>;
|
|
};
|
|
|
|
spi@11EA0000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dma-names = "tx\0rx";
|
|
interrupts = <0x00 0x229 0x04>;
|
|
samsung,usi-phandle = <0x16>;
|
|
clocks = <0x04 0x7a2 0x04 0x7ab>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x57>;
|
|
samsung,usi-offset = <0x00>;
|
|
reg = <0x00 0x11ea0000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x23d>;
|
|
};
|
|
|
|
spi@11EC0000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dma-names = "tx\0rx";
|
|
interrupts = <0x00 0x22b 0x04>;
|
|
samsung,usi-phandle = <0x16>;
|
|
clocks = <0x04 0x7a3 0x04 0x7ac>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x58>;
|
|
samsung,usi-offset = <0x08>;
|
|
reg = <0x00 0x11ec0000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x23e>;
|
|
};
|
|
|
|
spi@11EE0000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x100>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dma-names = "tx\0rx";
|
|
interrupts = <0x00 0x22d 0x04>;
|
|
samsung,usi-phandle = <0x16>;
|
|
clocks = <0x04 0x7a4 0x04 0x7a9>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x59>;
|
|
samsung,usi-offset = <0x10>;
|
|
reg = <0x00 0x11ee0000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x23f>;
|
|
};
|
|
|
|
spi@11f00000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x100>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dma-names = "tx\0rx";
|
|
interrupts = <0x00 0x115 0x04>;
|
|
samsung,usi-phandle = <0x16>;
|
|
clocks = <0x04 0x7ad 0x04 0x7b1>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x5a>;
|
|
samsung,usi-offset = <0x18>;
|
|
reg = <0x00 0x11f00000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x240>;
|
|
};
|
|
|
|
spi@11f20000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x100>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dma-names = "tx\0rx";
|
|
interrupts = <0x00 0x117 0x04>;
|
|
samsung,usi-phandle = <0x16>;
|
|
clocks = <0x04 0x7af 0x04 0x7b2>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x5b>;
|
|
samsung,usi-offset = <0x20>;
|
|
reg = <0x00 0x11f20000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x241>;
|
|
};
|
|
|
|
spi@10940000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dma-names = "tx\0rx";
|
|
interrupts = <0x00 0x21c 0x04>;
|
|
samsung,usi-phandle = <0x26>;
|
|
clocks = <0x04 0x743 0x04 0x758>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x5c>;
|
|
samsung,usi-offset = <0x28>;
|
|
reg = <0x00 0x10940000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x242>;
|
|
};
|
|
|
|
spi@109C0000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dma-names = "tx\0rx";
|
|
interrupts = <0x00 0x21e 0x04>;
|
|
samsung,usi-phandle = <0x2a>;
|
|
clocks = <0x04 0x749 0x04 0x755>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x5d>;
|
|
samsung,usi-offset = <0x00>;
|
|
reg = <0x00 0x109c0000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x243>;
|
|
};
|
|
|
|
spi@10630000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x210 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
clocks = <0x04 0x6e7 0x04 0x6f7>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x5e>;
|
|
samsung,usi-offset = <0x3c>;
|
|
reg = <0x00 0x10630000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x244>;
|
|
};
|
|
|
|
spi@10650000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x212 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
clocks = <0x04 0x6e9 0x04 0x6f8>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x5f>;
|
|
samsung,usi-offset = <0x44>;
|
|
reg = <0x00 0x10650000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x245>;
|
|
};
|
|
|
|
spi@10670000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x214 0x04>;
|
|
samsung,usi-phandle = <0x02>;
|
|
clocks = <0x04 0x6eb 0x04 0x6f9>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x60>;
|
|
samsung,usi-offset = <0x4c>;
|
|
reg = <0x00 0x10670000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x246>;
|
|
};
|
|
|
|
spi@10960000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dma-names = "tx\0rx";
|
|
interrupts = <0x00 0x221 0x04>;
|
|
samsung,usi-phandle = <0x26>;
|
|
clocks = <0x04 0x745 0x04 0x759>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x61>;
|
|
samsung,usi-offset = <0x30>;
|
|
reg = <0x00 0x10960000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x247>;
|
|
};
|
|
|
|
spi@10990000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dma-names = "tx\0rx";
|
|
interrupts = <0x00 0x224 0x04>;
|
|
samsung,usi-phandle = <0x26>;
|
|
clocks = <0x04 0x747 0x04 0x75a>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x62>;
|
|
samsung,usi-offset = <0x38>;
|
|
reg = <0x00 0x10990000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x248>;
|
|
};
|
|
|
|
spi@109E0000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
dma-names = "tx\0rx";
|
|
interrupts = <0x00 0x226 0x04>;
|
|
samsung,usi-phandle = <0x2a>;
|
|
clocks = <0x04 0x74b 0x04 0x754>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x63>;
|
|
samsung,usi-offset = <0x08>;
|
|
reg = <0x00 0x109e0000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x249>;
|
|
};
|
|
|
|
spi@14F00000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x7c 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
clocks = <0x04 0x172 0x04 0x178>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x64>;
|
|
samsung,usi-offset = <0x00>;
|
|
reg = <0x00 0x14f00000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x24a>;
|
|
};
|
|
|
|
spi@14F20000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x7d 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
clocks = <0x04 0x173 0x04 0x177>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x65>;
|
|
samsung,usi-offset = <0x10>;
|
|
reg = <0x00 0x14f20000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x24b>;
|
|
};
|
|
|
|
spi@14F40000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x7e 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
clocks = <0x04 0x174 0x04 0x179>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x66>;
|
|
samsung,usi-offset = <0x20>;
|
|
reg = <0x00 0x14f40000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x24c>;
|
|
};
|
|
|
|
spi@14F60000 {
|
|
compatible = "samsung,exynos-spi";
|
|
samsung,spi-fifosize = <0x40>;
|
|
swap-mode = <0x01>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
interrupts = <0x00 0x7f 0x04>;
|
|
samsung,usi-phandle = <0x40>;
|
|
clocks = <0x04 0x175 0x04 0x17a>;
|
|
clock-names = "gate_spi_clk\0ipclk_spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x67>;
|
|
samsung,usi-offset = <0x30>;
|
|
reg = <0x00 0x14f60000 0x1000>;
|
|
status = "disabled";
|
|
phandle = <0x24d>;
|
|
};
|
|
|
|
uart@10540000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x10540000 0x100>;
|
|
samsung,fifo-size = <0x100>;
|
|
reg-io-width = <0x04>;
|
|
interrupts = <0x00 0x1fc 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x68>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x6da 0x04 0x6f6>;
|
|
clock-names = "gate_uart_clk0\0ipclk_uart0";
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x00>;
|
|
samsung,dbg-uart-ch;
|
|
samsung,dbg-uart-baud = <0x1c200>;
|
|
samsung,dbg-word-len = <0x08>;
|
|
samsung,source-clock-rate = <0x7f28155>;
|
|
status = "disabled";
|
|
phandle = <0x24e>;
|
|
};
|
|
|
|
uart@10840000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x10840000 0x100>;
|
|
samsung,fifo-size = <0x100>;
|
|
interrupts = <0x00 0x215 0x04>;
|
|
pinctrl-names = "default\0rts\0tx_dat";
|
|
pinctrl-0 = <0x69>;
|
|
pinctrl-1 = <0x6a 0x6b>;
|
|
pinctrl-2 = <0x6c>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x73e 0x04 0x752>;
|
|
clock-names = "gate_uart_clk1\0ipclk_uart1";
|
|
samsung,usi-phandle = <0x26>;
|
|
samsung,usi-offset = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0x24f>;
|
|
};
|
|
|
|
uart@10550000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x10550000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x204 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x6d>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x6db 0x04 0x6ef>;
|
|
clock-names = "gate_uart_clk2\0ipclk_uart2";
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x04>;
|
|
status = "disabled";
|
|
phandle = <0x250>;
|
|
};
|
|
|
|
uart@10570000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x10570000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x206 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x6e>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x6dd 0x04 0x6f0>;
|
|
clock-names = "gate_uart_clk3\0ipclk_uart3";
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x0c>;
|
|
status = "disabled";
|
|
phandle = <0x251>;
|
|
};
|
|
|
|
uart@10590000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x10590000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x208 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x6f>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x6df 0x04 0x6f1>;
|
|
clock-names = "gate_uart_clk4\0ipclk_uart4";
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x14>;
|
|
status = "disabled";
|
|
phandle = <0x252>;
|
|
};
|
|
|
|
uart@105B0000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x105b0000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x20a 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x70>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x6e1 0x04 0x6f2>;
|
|
clock-names = "gate_uart_clk5\0ipclk_uart5";
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x1c>;
|
|
status = "disabled";
|
|
phandle = <0x253>;
|
|
};
|
|
|
|
uart@105D0000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x105d0000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x20c 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x71>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x6e3 0x04 0x6f3>;
|
|
clock-names = "gate_uart_clk6\0ipclk_uart6";
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x24>;
|
|
status = "disabled";
|
|
phandle = <0x254>;
|
|
};
|
|
|
|
uart@105F0000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x105f0000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x20e 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x72>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x6e5 0x04 0x6f4>;
|
|
clock-names = "gate_uart_clk7\0ipclk_uart7";
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x2c>;
|
|
status = "disabled";
|
|
phandle = <0x255>;
|
|
};
|
|
|
|
uart@11EA0000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x11ea0000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x229 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x73>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x7a2 0x04 0x7ab>;
|
|
clock-names = "gate_uart_clk8\0ipclk_uart8";
|
|
samsung,usi-phandle = <0x16>;
|
|
samsung,usi-offset = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0x256>;
|
|
};
|
|
|
|
uart@11EC0000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x11ec0000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x22b 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x74>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x7a3 0x04 0x7ac>;
|
|
clock-names = "gate_uart_clk9\0ipclk_uart9";
|
|
samsung,usi-phandle = <0x16>;
|
|
samsung,usi-offset = <0x08>;
|
|
status = "disabled";
|
|
phandle = <0x257>;
|
|
};
|
|
|
|
uart@11EE0000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x11ee0000 0x100>;
|
|
samsung,fifo-size = <0x100>;
|
|
interrupts = <0x00 0x22d 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x75>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x7a4 0x04 0x7a9>;
|
|
clock-names = "gate_uart_clk10\0ipclk_uart10";
|
|
samsung,usi-phandle = <0x16>;
|
|
samsung,usi-offset = <0x10>;
|
|
status = "disabled";
|
|
phandle = <0x258>;
|
|
};
|
|
|
|
uart@11f00000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x11f00000 0x100>;
|
|
samsung,fifo-size = <0x100>;
|
|
interrupts = <0x00 0x115 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x76>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x7ad 0x04 0x7b1>;
|
|
clock-names = "gate_uart_clk11\0ipclk_uart11";
|
|
samsung,usi-phandle = <0x16>;
|
|
samsung,usi-offset = <0x18>;
|
|
status = "disabled";
|
|
phandle = <0x259>;
|
|
};
|
|
|
|
uart@11f20000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x11f20000 0x100>;
|
|
samsung,fifo-size = <0x100>;
|
|
interrupts = <0x00 0x117 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x77>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x7af 0x04 0x7b2>;
|
|
clock-names = "gate_uart_clk12\0ipclk_uart12";
|
|
samsung,usi-phandle = <0x16>;
|
|
samsung,usi-offset = <0x20>;
|
|
status = "disabled";
|
|
phandle = <0x25a>;
|
|
};
|
|
|
|
uart@10940000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x10940000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x21c 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x78>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x743 0x04 0x758>;
|
|
clock-names = "gate_uart_clk13\0ipclk_uart13";
|
|
samsung,usi-phandle = <0x26>;
|
|
samsung,usi-offset = <0x28>;
|
|
status = "disabled";
|
|
phandle = <0x25b>;
|
|
};
|
|
|
|
uart@109C0000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x109c0000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x21e 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x79>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x749 0x04 0x755>;
|
|
clock-names = "gate_uart_clk14\0ipclk_uart14";
|
|
samsung,usi-phandle = <0x2a>;
|
|
samsung,usi-offset = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0x25c>;
|
|
};
|
|
|
|
uart@10630000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x10630000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x210 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x7a>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x6e7 0x04 0x6f7>;
|
|
clock-names = "gate_uart_clk15\0ipclk_uart15";
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x3c>;
|
|
status = "disabled";
|
|
phandle = <0x25d>;
|
|
};
|
|
|
|
uart@10650000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x10650000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x212 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x7b>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x6e9 0x04 0x6f8>;
|
|
clock-names = "gate_uart_clk16\0ipclk_uart16";
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x44>;
|
|
status = "disabled";
|
|
phandle = <0x25e>;
|
|
};
|
|
|
|
uart@10670000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x10670000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x214 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x7c>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x6eb 0x04 0x6f9>;
|
|
clock-names = "gate_uart_clk17\0ipclk_uart17";
|
|
samsung,usi-phandle = <0x02>;
|
|
samsung,usi-offset = <0x4c>;
|
|
status = "disabled";
|
|
phandle = <0x25f>;
|
|
};
|
|
|
|
uart@10960000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x10960000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x221 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x7d>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x745 0x04 0x759>;
|
|
clock-names = "gate_uart_clk18\0ipclk_uart18";
|
|
samsung,usi-phandle = <0x26>;
|
|
samsung,usi-offset = <0x30>;
|
|
status = "disabled";
|
|
phandle = <0x260>;
|
|
};
|
|
|
|
uart@10990000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x10990000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x224 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x7e>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x747 0x04 0x75a>;
|
|
clock-names = "gate_uart_clk19\0ipclk_uart19";
|
|
samsung,usi-phandle = <0x26>;
|
|
samsung,usi-offset = <0x38>;
|
|
status = "disabled";
|
|
phandle = <0x261>;
|
|
};
|
|
|
|
uart@109E0000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x109e0000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x226 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x7f>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x74b 0x04 0x754>;
|
|
clock-names = "gate_uart_clk20\0ipclk_uart20";
|
|
samsung,usi-phandle = <0x2a>;
|
|
samsung,usi-offset = <0x08>;
|
|
status = "disabled";
|
|
phandle = <0x262>;
|
|
};
|
|
|
|
uart@14F00000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x14f00000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x7c 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x80>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x172 0x04 0x178>;
|
|
clock-names = "gate_uart_clk21\0ipclk_uart21";
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x00>;
|
|
status = "disabled";
|
|
phandle = <0x263>;
|
|
};
|
|
|
|
uart@14F20000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x14f20000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x7d 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x81>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x173 0x04 0x177>;
|
|
clock-names = "gate_uart_clk22\0ipclk_uart22";
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x10>;
|
|
status = "disabled";
|
|
phandle = <0x264>;
|
|
};
|
|
|
|
uart@14F40000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x14f40000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x7e 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x82>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x174 0x04 0x179>;
|
|
clock-names = "gate_uart_clk23\0ipclk_uart23";
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x20>;
|
|
status = "disabled";
|
|
phandle = <0x265>;
|
|
};
|
|
|
|
uart@14F60000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x00 0x14f60000 0x100>;
|
|
samsung,fifo-size = <0x40>;
|
|
interrupts = <0x00 0x7f 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0x83>;
|
|
samsung,usi-serial-v2;
|
|
clocks = <0x04 0x175 0x04 0x17a>;
|
|
clock-names = "gate_uart_clk24\0ipclk_uart24";
|
|
samsung,usi-phandle = <0x40>;
|
|
samsung,usi-offset = <0x30>;
|
|
status = "disabled";
|
|
phandle = <0x266>;
|
|
};
|
|
|
|
set@0000 {
|
|
phandle = <0x84>;
|
|
|
|
sched_policy {
|
|
root = <0x00>;
|
|
foreground = <0x00>;
|
|
background = <0x00>;
|
|
top-app = <0x00>;
|
|
rt = <0x00>;
|
|
system = <0x00>;
|
|
system-background = <0x00>;
|
|
nnapi-hal = <0x00>;
|
|
camera-daemon = <0x00>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x64 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x64 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
freqboost {
|
|
top-app = <0x05 0x05 0x05>;
|
|
};
|
|
|
|
wakeboost {
|
|
top-app = <0x00 0x00 0x00>;
|
|
};
|
|
|
|
esg {
|
|
step = <0x04 0x06 0x08>;
|
|
pelt-margin = <0x19 0x19 0x19>;
|
|
up-rate-limit-ms = <0x04>;
|
|
down-rate-limit-ms = <0x08>;
|
|
rapid-scale-up = <0x01>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x64 0x64>;
|
|
};
|
|
|
|
ontime {
|
|
top-app = <0x01>;
|
|
foreground = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x5a>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x3c>;
|
|
upper-boundary = <0x258>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x1f4>;
|
|
upper-boundary = <0x400>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
|
|
domain0 {
|
|
busy-threshold-ratio = <0x64>;
|
|
};
|
|
};
|
|
|
|
prefer_cpu {
|
|
top-app = "4-7";
|
|
};
|
|
};
|
|
|
|
set@0001 {
|
|
phandle = <0x85>;
|
|
|
|
sched_policy {
|
|
root = <0x00>;
|
|
foreground = <0x00>;
|
|
background = <0x00>;
|
|
top-app = <0x05>;
|
|
rt = <0x00>;
|
|
system = <0x00>;
|
|
system-background = <0x00>;
|
|
nnapi-hal = <0x00>;
|
|
camera-daemon = <0x00>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x64 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x64 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
freqboost {
|
|
top-app = <0x1e 0x1e 0x1e>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
|
|
ontime {
|
|
foreground = <0x01>;
|
|
top-app = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x5a>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x3c>;
|
|
upper-boundary = <0x258>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x1f4>;
|
|
upper-boundary = <0x400>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
};
|
|
};
|
|
|
|
set@0002 {
|
|
phandle = <0x86>;
|
|
|
|
sched_policy {
|
|
root = <0x01>;
|
|
foreground = <0x05>;
|
|
background = <0x01>;
|
|
top-app = <0x05>;
|
|
rt = <0x01>;
|
|
system = <0x01>;
|
|
system-background = <0x01>;
|
|
nnapi-hal = <0x01>;
|
|
camera-daemon = <0x01>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x41 0x64 0x64>;
|
|
foreground = <0x41 0x64 0x64>;
|
|
background = <0x41 0x64 0x64>;
|
|
top-app = <0x41 0x64 0x64>;
|
|
rt = <0x41 0x64 0x64>;
|
|
system = <0x41 0x64 0x64>;
|
|
system-background = <0x41 0x64 0x64>;
|
|
nnapi-hal = <0x41 0x64 0x64>;
|
|
camera-daemon = <0x41 0x64 0x64>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0x82 0xc8 0xc8>;
|
|
foreground = <0x82 0xc8 0xc8>;
|
|
background = <0x82 0xc8 0xc8>;
|
|
top-app = <0x82 0xc8 0xc8>;
|
|
rt = <0x82 0xc8 0xc8>;
|
|
system = <0x82 0xc8 0xc8>;
|
|
system-background = <0x82 0xc8 0xc8>;
|
|
nnapi-hal = <0x82 0xc8 0xc8>;
|
|
camera-daemon = <0x82 0xc8 0xc8>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
|
|
ontime {
|
|
foreground = <0x01>;
|
|
top-app = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x5a>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x3c>;
|
|
upper-boundary = <0x258>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x1f4>;
|
|
upper-boundary = <0x400>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
};
|
|
|
|
prio_pinning {
|
|
top-app = <0x01>;
|
|
mask = "4-7";
|
|
prio = <0x6e>;
|
|
};
|
|
|
|
prefer_cpu {
|
|
};
|
|
};
|
|
|
|
set@0100 {
|
|
phandle = <0x87>;
|
|
|
|
sched_policy {
|
|
root = <0x00>;
|
|
foreground = <0x00>;
|
|
background = <0x00>;
|
|
top-app = <0x00>;
|
|
rt = <0x00>;
|
|
system = <0x00>;
|
|
system-background = <0x00>;
|
|
nnapi-hal = <0x00>;
|
|
camera-daemon = <0x00>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x500 0xc8 0x19>;
|
|
foreground = <0x500 0xc8 0x19>;
|
|
background = <0x500 0xc8 0x19>;
|
|
top-app = <0x500 0xc8 0x19>;
|
|
rt = <0x500 0xc8 0x19>;
|
|
system = <0x500 0xc8 0x19>;
|
|
system-background = <0x500 0xc8 0x19>;
|
|
nnapi-hal = <0x500 0xc8 0x19>;
|
|
camera-daemon = <0x500 0xc8 0x19>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0xa00 0x190 0x32>;
|
|
foreground = <0xa00 0x190 0x32>;
|
|
background = <0xa00 0x190 0x32>;
|
|
top-app = <0xa00 0x190 0x32>;
|
|
rt = <0xa00 0x190 0x32>;
|
|
system = <0xa00 0x190 0x32>;
|
|
system-background = <0xa00 0x190 0x32>;
|
|
nnapi-hal = <0xa00 0x190 0x32>;
|
|
camera-daemon = <0xa00 0x190 0x32>;
|
|
};
|
|
|
|
esg {
|
|
step = <0x0a 0x08 0x0a>;
|
|
patient-mode = <0x01 0x01 0x01>;
|
|
pelt-margin = <0x19 0x19 0x19>;
|
|
up-rate-limit-ms = <0x04>;
|
|
down-rate-limit-ms = <0x04>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x5a 0x64 0x64>;
|
|
};
|
|
|
|
ontime {
|
|
foreground = <0x01>;
|
|
top-app = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x69>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-7";
|
|
lower-boundary = <0x6a>;
|
|
upper-boundary = <0x400>;
|
|
};
|
|
};
|
|
};
|
|
|
|
set@0101 {
|
|
phandle = <0x88>;
|
|
|
|
sched_policy {
|
|
root = <0x01>;
|
|
foreground = <0x01>;
|
|
background = <0x00>;
|
|
top-app = <0x01>;
|
|
rt = <0x01>;
|
|
system = <0x01>;
|
|
system-background = <0x01>;
|
|
nnapi-hal = <0x01>;
|
|
camera-daemon = <0x01>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x500 0xc8 0x19>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x500 0xc8 0x19>;
|
|
top-app = <0x64 0x64 0x64>;
|
|
rt = <0x500 0xc8 0x19>;
|
|
system = <0x500 0xc8 0x19>;
|
|
system-background = <0x500 0xc8 0x19>;
|
|
nnapi-hal = <0x500 0xc8 0x19>;
|
|
camera-daemon = <0x500 0xc8 0x19>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0xa00 0x190 0x32>;
|
|
foreground = <0xfa 0x3e8 0x3e8>;
|
|
background = <0xa00 0x190 0x32>;
|
|
top-app = <0xfa 0x3e8 0x3e8>;
|
|
rt = <0xa00 0x190 0x32>;
|
|
system = <0xa00 0x190 0x32>;
|
|
system-background = <0xa00 0x190 0x32>;
|
|
nnapi-hal = <0xa00 0x190 0x32>;
|
|
camera-daemon = <0xa00 0x190 0x32>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
};
|
|
|
|
set@0102 {
|
|
phandle = <0x89>;
|
|
|
|
sched_policy {
|
|
root = <0x01>;
|
|
foreground = <0x05>;
|
|
background = <0x01>;
|
|
top-app = <0x05>;
|
|
rt = <0x01>;
|
|
system = <0x01>;
|
|
system-background = <0x01>;
|
|
nnapi-hal = <0x01>;
|
|
camera-daemon = <0x01>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x64 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0xc8 0xc8 0xc8>;
|
|
foreground = <0xc8 0xc8 0xc8>;
|
|
background = <0xc8 0xc8 0xc8>;
|
|
top-app = <0xc8 0xc8 0xc8>;
|
|
rt = <0xc8 0xc8 0xc8>;
|
|
system = <0xc8 0xc8 0xc8>;
|
|
system-background = <0xc8 0xc8 0xc8>;
|
|
nnapi-hal = <0xc8 0xc8 0xc8>;
|
|
camera-daemon = <0xc8 0xc8 0xc8>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
|
|
prio_pinning {
|
|
top-app = <0x01>;
|
|
mask = "4-7";
|
|
prio = <0x6e>;
|
|
};
|
|
};
|
|
|
|
set@0200 {
|
|
phandle = <0x8a>;
|
|
|
|
sched_policy {
|
|
root = <0x01>;
|
|
foreground = <0x01>;
|
|
background = <0x01>;
|
|
top-app = <0x01>;
|
|
rt = <0x01>;
|
|
system = <0x01>;
|
|
system-background = <0x01>;
|
|
nnapi-hal = <0x01>;
|
|
camera-daemon = <0x01>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x96 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0xc8 0xc8 0xc8>;
|
|
foreground = <0xc8 0xc8 0xc8>;
|
|
background = <0xc8 0xc8 0xc8>;
|
|
top-app = <0xc8 0x12c 0xc8>;
|
|
rt = <0xc8 0xc8 0xc8>;
|
|
system = <0xc8 0xc8 0xc8>;
|
|
system-background = <0xc8 0xc8 0xc8>;
|
|
nnapi-hal = <0xc8 0xc8 0xc8>;
|
|
camera-daemon = <0xc8 0xc8 0xc8>;
|
|
};
|
|
|
|
freqboost {
|
|
top-app = <0x05 0x05 0x05>;
|
|
};
|
|
|
|
wakeboost {
|
|
top-app = <0x4b 0x4b 0x4b>;
|
|
};
|
|
|
|
esg {
|
|
step = <0x04 0x06 0x08>;
|
|
pelt-margin = <0x190 0x190 0x19>;
|
|
up-rate-limit-ms = <0x04>;
|
|
down-rate-limit-ms = <0x08>;
|
|
rapid-scale-up = <0x01>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x64 0x64>;
|
|
};
|
|
|
|
ontime {
|
|
foreground = <0x01>;
|
|
top-app = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x14>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x0a>;
|
|
upper-boundary = <0x1f4>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x190>;
|
|
upper-boundary = <0x400>;
|
|
};
|
|
};
|
|
|
|
prefer_cpu {
|
|
top-app = "4-7";
|
|
};
|
|
};
|
|
|
|
set@0201 {
|
|
phandle = <0x8b>;
|
|
|
|
active_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x96 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0xc8 0xc8 0xc8>;
|
|
foreground = <0xfa 0x3e8 0x3e8>;
|
|
background = <0xc8 0xc8 0xc8>;
|
|
top-app = <0xfa 0x3e8 0x3e8>;
|
|
rt = <0xc8 0xc8 0xc8>;
|
|
system = <0xc8 0xc8 0xc8>;
|
|
system-background = <0xc8 0xc8 0xc8>;
|
|
nnapi-hal = <0xc8 0xc8 0xc8>;
|
|
camera-daemon = <0xc8 0xc8 0xc8>;
|
|
};
|
|
|
|
wakeboost {
|
|
top-app = <0x28 0x28 0x28>;
|
|
};
|
|
|
|
esg {
|
|
step = <0x04 0x06 0x08>;
|
|
patient-mode = <0x00 0x00 0x00>;
|
|
pelt-margin = <0x19 0x19 0x19>;
|
|
up-rate-limit-ms = <0x04>;
|
|
down-rate-limit-ms = <0x08>;
|
|
rapid-scale-up = <0x01>;
|
|
};
|
|
};
|
|
|
|
set@0202 {
|
|
phandle = <0x8c>;
|
|
|
|
sched_policy {
|
|
root = <0x01>;
|
|
foreground = <0x05>;
|
|
background = <0x01>;
|
|
top-app = <0x05>;
|
|
rt = <0x01>;
|
|
system = <0x01>;
|
|
system-background = <0x01>;
|
|
nnapi-hal = <0x01>;
|
|
camera-daemon = <0x01>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x96 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0xc8 0xc8 0xc8>;
|
|
foreground = <0xc8 0xc8 0xc8>;
|
|
background = <0xc8 0xc8 0xc8>;
|
|
top-app = <0xc8 0x12c 0xc8>;
|
|
rt = <0xc8 0xc8 0xc8>;
|
|
system = <0xc8 0xc8 0xc8>;
|
|
system-background = <0xc8 0xc8 0xc8>;
|
|
nnapi-hal = <0xc8 0xc8 0xc8>;
|
|
camera-daemon = <0xc8 0xc8 0xc8>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
|
|
prio_pinning {
|
|
top-app = <0x01>;
|
|
mask = "4-7";
|
|
prio = <0x6e>;
|
|
};
|
|
};
|
|
|
|
set@0300 {
|
|
phandle = <0x8d>;
|
|
|
|
sched_policy {
|
|
root = <0x00>;
|
|
foreground = <0x00>;
|
|
background = <0x00>;
|
|
top-app = <0x00>;
|
|
rt = <0x00>;
|
|
system = <0x00>;
|
|
system-background = <0x00>;
|
|
nnapi-hal = <0x00>;
|
|
camera-daemon = <0x00>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x64 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x64 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
esg {
|
|
step = <0x04 0x04 0x04>;
|
|
patient-mode = <0x01 0x01 0x01>;
|
|
up-rate-limit-ms = <0x04>;
|
|
down-rate-limit-ms = <0x04>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x32 0x64 0x64>;
|
|
};
|
|
|
|
ontime {
|
|
foreground = <0x01>;
|
|
top-app = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x4b>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-7";
|
|
lower-boundary = <0x32>;
|
|
upper-boundary = <0x400>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
|
|
domain0 {
|
|
busy-threshold-ratio = <0x64>;
|
|
};
|
|
};
|
|
|
|
cpus_binding {
|
|
target-sched-class = <0x08>;
|
|
background = "0-3";
|
|
};
|
|
};
|
|
|
|
set@0301 {
|
|
phandle = <0x8e>;
|
|
};
|
|
|
|
set@0302 {
|
|
phandle = <0x8f>;
|
|
|
|
sched_policy {
|
|
root = <0x01>;
|
|
foreground = <0x05>;
|
|
background = <0x01>;
|
|
top-app = <0x05>;
|
|
rt = <0x01>;
|
|
system = <0x01>;
|
|
system-background = <0x01>;
|
|
nnapi-hal = <0x01>;
|
|
camera-daemon = <0x01>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x64 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0xc8 0xc8 0xc8>;
|
|
foreground = <0xc8 0xc8 0xc8>;
|
|
background = <0xc8 0xc8 0xc8>;
|
|
top-app = <0xc8 0xc8 0xc8>;
|
|
rt = <0xc8 0xc8 0xc8>;
|
|
system = <0xc8 0xc8 0xc8>;
|
|
system-background = <0xc8 0xc8 0xc8>;
|
|
nnapi-hal = <0xc8 0xc8 0xc8>;
|
|
camera-daemon = <0xc8 0xc8 0xc8>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
|
|
prio_pinning {
|
|
top-app = <0x01>;
|
|
mask = "4-7";
|
|
prio = <0x6e>;
|
|
};
|
|
};
|
|
|
|
set@0400 {
|
|
phandle = <0x90>;
|
|
|
|
sched_policy {
|
|
root = <0x00>;
|
|
foreground = <0x00>;
|
|
background = <0x00>;
|
|
top-app = <0x00>;
|
|
rt = <0x00>;
|
|
system = <0x00>;
|
|
system-background = <0x00>;
|
|
nnapi-hal = <0x00>;
|
|
camera-daemon = <0x00>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x64 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x64 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
freqboost {
|
|
top-app = <0x05 0x05 0x05>;
|
|
};
|
|
|
|
wakeboost {
|
|
top-app = <0x00 0x00 0x00>;
|
|
};
|
|
|
|
esg {
|
|
step = <0x04 0x06 0x08>;
|
|
pelt-margin = <0x19 0x19 0x19>;
|
|
up-rate-limit-ms = <0x04>;
|
|
down-rate-limit-ms = <0x08>;
|
|
rapid-scale-up = <0x01>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x64 0x64>;
|
|
};
|
|
|
|
ontime {
|
|
top-app = <0x01>;
|
|
foreground = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x5a>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x3c>;
|
|
upper-boundary = <0x258>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x1f4>;
|
|
upper-boundary = <0x400>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
|
|
domain0 {
|
|
busy-threshold-ratio = <0x64>;
|
|
};
|
|
};
|
|
|
|
prefer_cpu {
|
|
top-app = "4-7";
|
|
};
|
|
};
|
|
|
|
set@0401 {
|
|
phandle = <0x91>;
|
|
|
|
sched_policy {
|
|
root = <0x00>;
|
|
foreground = <0x00>;
|
|
background = <0x00>;
|
|
top-app = <0x05>;
|
|
rt = <0x00>;
|
|
system = <0x00>;
|
|
system-background = <0x00>;
|
|
nnapi-hal = <0x00>;
|
|
camera-daemon = <0x00>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x64 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x64 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
freqboost {
|
|
top-app = <0x1e 0x1e 0x1e>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
|
|
ontime {
|
|
foreground = <0x01>;
|
|
top-app = <0x01>;
|
|
|
|
domain0 {
|
|
cpus = "0-3";
|
|
lower-boundary = <0x00>;
|
|
upper-boundary = <0x5a>;
|
|
};
|
|
|
|
domain1 {
|
|
cpus = "4-6";
|
|
lower-boundary = <0x3c>;
|
|
upper-boundary = <0x258>;
|
|
};
|
|
|
|
domain2 {
|
|
cpus = "7";
|
|
lower-boundary = <0x1f4>;
|
|
upper-boundary = <0x400>;
|
|
};
|
|
};
|
|
|
|
ecs {
|
|
};
|
|
};
|
|
|
|
set@0402 {
|
|
phandle = <0x92>;
|
|
|
|
sched_policy {
|
|
root = <0x01>;
|
|
foreground = <0x05>;
|
|
background = <0x01>;
|
|
top-app = <0x05>;
|
|
rt = <0x01>;
|
|
system = <0x01>;
|
|
system-background = <0x01>;
|
|
nnapi-hal = <0x01>;
|
|
camera-daemon = <0x01>;
|
|
};
|
|
|
|
active_weight {
|
|
root = <0x64 0x64 0x64>;
|
|
foreground = <0x64 0x64 0x64>;
|
|
background = <0x64 0x64 0x64>;
|
|
top-app = <0x64 0x64 0x64>;
|
|
rt = <0x64 0x64 0x64>;
|
|
system = <0x64 0x64 0x64>;
|
|
system-background = <0x64 0x64 0x64>;
|
|
nnapi-hal = <0x64 0x64 0x64>;
|
|
camera-daemon = <0x64 0x64 0x64>;
|
|
};
|
|
|
|
idle_weight {
|
|
root = <0xc8 0xc8 0xc8>;
|
|
foreground = <0xc8 0xc8 0xc8>;
|
|
background = <0xc8 0xc8 0xc8>;
|
|
top-app = <0xc8 0xc8 0xc8>;
|
|
rt = <0xc8 0xc8 0xc8>;
|
|
system = <0xc8 0xc8 0xc8>;
|
|
system-background = <0xc8 0xc8 0xc8>;
|
|
nnapi-hal = <0xc8 0xc8 0xc8>;
|
|
camera-daemon = <0xc8 0xc8 0xc8>;
|
|
};
|
|
|
|
frt {
|
|
active-ratio = <0x19 0x03 0x05>;
|
|
};
|
|
|
|
prio_pinning {
|
|
top-app = <0x01>;
|
|
mask = "4-7";
|
|
prio = <0x6e>;
|
|
};
|
|
};
|
|
|
|
ems {
|
|
compatible = "samsung,ems";
|
|
status = "okay";
|
|
|
|
esg {
|
|
thread-run-on = "0-6";
|
|
|
|
domain@0 {
|
|
shared-cpus = "0-3";
|
|
};
|
|
|
|
domain@1 {
|
|
shared-cpus = "4-6";
|
|
};
|
|
|
|
domain@2 {
|
|
shared-cpus = "7";
|
|
};
|
|
};
|
|
|
|
emstune {
|
|
boost-level = <0x02>;
|
|
|
|
mode0 {
|
|
desc = "normal";
|
|
|
|
level0 {
|
|
base = <0x84>;
|
|
set = <0x84>;
|
|
};
|
|
|
|
level1 {
|
|
base = <0x84>;
|
|
set = <0x85>;
|
|
};
|
|
|
|
level2 {
|
|
base = <0x84>;
|
|
set = <0x86>;
|
|
};
|
|
};
|
|
|
|
mode1 {
|
|
desc = "power-scenario";
|
|
|
|
level0 {
|
|
base = <0x87>;
|
|
set = <0x87>;
|
|
};
|
|
|
|
level1 {
|
|
base = <0x87>;
|
|
set = <0x88>;
|
|
};
|
|
|
|
level2 {
|
|
base = <0x87>;
|
|
set = <0x89>;
|
|
};
|
|
};
|
|
|
|
mode2 {
|
|
desc = "performance";
|
|
|
|
level0 {
|
|
base = <0x8a>;
|
|
set = <0x8a>;
|
|
};
|
|
|
|
level1 {
|
|
base = <0x8a>;
|
|
set = <0x8b>;
|
|
};
|
|
|
|
level2 {
|
|
base = <0x8a>;
|
|
set = <0x8c>;
|
|
};
|
|
};
|
|
|
|
mode3 {
|
|
desc = "game";
|
|
|
|
level0 {
|
|
base = <0x8d>;
|
|
set = <0x8d>;
|
|
};
|
|
|
|
level1 {
|
|
base = <0x8d>;
|
|
set = <0x8e>;
|
|
};
|
|
|
|
level2 {
|
|
base = <0x8d>;
|
|
set = <0x8f>;
|
|
};
|
|
};
|
|
|
|
mode4 {
|
|
desc = "balance";
|
|
|
|
level0 {
|
|
base = <0x90>;
|
|
set = <0x90>;
|
|
};
|
|
|
|
level1 {
|
|
base = <0x90>;
|
|
set = <0x91>;
|
|
};
|
|
|
|
level2 {
|
|
base = <0x90>;
|
|
set = <0x92>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x00>;
|
|
|
|
cpu-map {
|
|
|
|
cluster0 {
|
|
|
|
core0 {
|
|
cpu = <0x93>;
|
|
};
|
|
|
|
core1 {
|
|
cpu = <0x94>;
|
|
};
|
|
|
|
core2 {
|
|
cpu = <0x95>;
|
|
};
|
|
|
|
core3 {
|
|
cpu = <0x96>;
|
|
};
|
|
};
|
|
|
|
cluster1 {
|
|
|
|
core0 {
|
|
cpu = <0x97>;
|
|
};
|
|
|
|
core1 {
|
|
cpu = <0x98>;
|
|
};
|
|
|
|
core2 {
|
|
cpu = <0x99>;
|
|
};
|
|
};
|
|
|
|
cluster2 {
|
|
|
|
core0 {
|
|
cpu = <0x9a>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu@0000 {
|
|
device_type = "cpu";
|
|
compatible = "arm,ananke\0arm,armv8";
|
|
reg = <0x00 0x00>;
|
|
capacity-dmips-mhz = <0x104>;
|
|
dynamic-power-coefficient = <0x59>;
|
|
static-power-coefficient = <0x57>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x9b>;
|
|
phandle = <0x93>;
|
|
};
|
|
|
|
cpu@0100 {
|
|
device_type = "cpu";
|
|
compatible = "arm,ananke\0arm,armv8";
|
|
reg = <0x00 0x100>;
|
|
capacity-dmips-mhz = <0x104>;
|
|
dynamic-power-coefficient = <0x59>;
|
|
static-power-coefficient = <0x57>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x9b>;
|
|
phandle = <0x94>;
|
|
};
|
|
|
|
cpu@0200 {
|
|
device_type = "cpu";
|
|
compatible = "arm,ananke\0arm,armv8";
|
|
reg = <0x00 0x200>;
|
|
capacity-dmips-mhz = <0x104>;
|
|
dynamic-power-coefficient = <0x59>;
|
|
static-power-coefficient = <0x57>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x9b>;
|
|
phandle = <0x95>;
|
|
};
|
|
|
|
cpu@0300 {
|
|
device_type = "cpu";
|
|
compatible = "arm,ananke\0arm,armv8";
|
|
reg = <0x00 0x300>;
|
|
capacity-dmips-mhz = <0x104>;
|
|
dynamic-power-coefficient = <0x59>;
|
|
static-power-coefficient = <0x57>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x9b>;
|
|
phandle = <0x96>;
|
|
};
|
|
|
|
cpu@0400 {
|
|
device_type = "cpu";
|
|
compatible = "arm,hercules\0arm,armv8";
|
|
reg = <0x00 0x400>;
|
|
capacity-dmips-mhz = <0x370>;
|
|
dynamic-power-coefficient = <0x201>;
|
|
static-power-coefficient = <0xfd>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x9c>;
|
|
phandle = <0x97>;
|
|
};
|
|
|
|
cpu@0500 {
|
|
device_type = "cpu";
|
|
compatible = "arm,hercules\0arm,armv8";
|
|
reg = <0x00 0x500>;
|
|
capacity-dmips-mhz = <0x370>;
|
|
dynamic-power-coefficient = <0x201>;
|
|
static-power-coefficient = <0xfd>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x9c>;
|
|
phandle = <0x98>;
|
|
};
|
|
|
|
cpu@0600 {
|
|
device_type = "cpu";
|
|
compatible = "arm,hercules\0arm,armv8";
|
|
reg = <0x00 0x600>;
|
|
capacity-dmips-mhz = <0x370>;
|
|
dynamic-power-coefficient = <0x201>;
|
|
static-power-coefficient = <0xfd>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x9c>;
|
|
phandle = <0x99>;
|
|
};
|
|
|
|
cpu@0700 {
|
|
device_type = "cpu";
|
|
compatible = "arm,hera\0arm,armv8";
|
|
reg = <0x00 0x700>;
|
|
capacity-dmips-mhz = <0x3e5>;
|
|
dynamic-power-coefficient = <0x2f5>;
|
|
static-power-coefficient = <0xfd>;
|
|
enable-method = "psci";
|
|
cpu-idle-states = <0x9d>;
|
|
phandle = <0x9a>;
|
|
};
|
|
|
|
idle-states {
|
|
entry-method = "arm,psci";
|
|
|
|
ananke-cpu-sleep {
|
|
idle-state-name = "c2";
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x10000>;
|
|
entry-latency-us = <0x46>;
|
|
exit-latency-us = <0xa0>;
|
|
min-residency-us = <0x7d0>;
|
|
status = "okay";
|
|
phandle = <0x9b>;
|
|
};
|
|
|
|
hercules-cpu-sleep {
|
|
idle-state-name = "c2";
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x10000>;
|
|
entry-latency-us = <0x96>;
|
|
exit-latency-us = <0xbe>;
|
|
min-residency-us = <0x9c4>;
|
|
status = "okay";
|
|
phandle = <0x9c>;
|
|
};
|
|
|
|
hera-cpu-sleep {
|
|
idle-state-name = "c2";
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x10000>;
|
|
entry-latency-us = <0xeb>;
|
|
exit-latency-us = <0xdc>;
|
|
min-residency-us = <0xdac>;
|
|
status = "okay";
|
|
phandle = <0x9d>;
|
|
};
|
|
};
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
|
|
exynos-cpuhp {
|
|
compatible = "samsung,exynos-cpuhp";
|
|
status = "okay";
|
|
};
|
|
|
|
exynos-cpupm {
|
|
compatible = "samsung,exynos-cpupm";
|
|
status = "okay";
|
|
|
|
cpd_cl0 {
|
|
device_type = "cpupm";
|
|
target-residency = <0x2710>;
|
|
type = <0x00>;
|
|
cal-id = <0x00>;
|
|
siblings = "0-3";
|
|
};
|
|
|
|
cpd_cl1 {
|
|
device_type = "cpupm";
|
|
target-residency = <0x2710>;
|
|
type = <0x00>;
|
|
cal-id = <0x01>;
|
|
siblings = "4-6";
|
|
entry-allowed = "4-6";
|
|
};
|
|
|
|
cpd_cl2 {
|
|
device_type = "cpupm";
|
|
target-residency = <0x2710>;
|
|
type = <0x00>;
|
|
cal-id = <0x02>;
|
|
siblings = "7";
|
|
entry-allowed = "7";
|
|
};
|
|
|
|
dsupd {
|
|
device_type = "cpupm";
|
|
target-residency = <0x2710>;
|
|
type = <0x01>;
|
|
siblings = "0-7";
|
|
entry-allowed = "0-7";
|
|
};
|
|
|
|
sicd {
|
|
device_type = "cpupm";
|
|
target-residency = <0x2710>;
|
|
type = <0x02>;
|
|
siblings = "0-7";
|
|
entry-allowed = "0-7";
|
|
};
|
|
|
|
wakeup-mask {
|
|
|
|
wakeup-masks {
|
|
|
|
wakeup-mask {
|
|
mask-reg-offset = <0x3b44>;
|
|
stat-reg-offset = <0x3b50>;
|
|
mask = <0xff000000>;
|
|
};
|
|
|
|
wakeup-mask2 {
|
|
mask-reg-offset = <0x3b64>;
|
|
stat-reg-offset = <0x3b54>;
|
|
mask = <0x00>;
|
|
};
|
|
};
|
|
|
|
eint-wakeup-masks {
|
|
|
|
eint-wakeup-mask {
|
|
mask-reg-offset = <0x60c>;
|
|
};
|
|
|
|
eint-wakeup-mask2 {
|
|
mask-reg-offset = <0x610>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
exynos-acme {
|
|
compatible = "samsung,exynos-acme";
|
|
status = "okay";
|
|
|
|
domain@0 {
|
|
sibling-cpus = "0-3";
|
|
cal-id = <0xb040002>;
|
|
dm-type = <0x00>;
|
|
max-freq = <0x21b8d0>;
|
|
min-freq = <0x61a80>;
|
|
#cooling-cells = <0x02>;
|
|
ect-coeff-index = <0x02>;
|
|
tz-cooling-name = "LITTLE";
|
|
freq-table = <0x2b368 0x40f10 0x61a80 0x82208 0x9eb10 0xb8150 0xd1790 0xeadd0 0x104410 0x11da50 0x137090 0x1506d0 0x169d10 0x183350 0x19c990 0x1b5fd0 0x1cf610 0x1e8c50 0x202290 0x21b8d0 0x234f10 0x247fc0>;
|
|
phandle = <0x116>;
|
|
|
|
dm-constraints {
|
|
list = <0x9e 0x9f>;
|
|
};
|
|
};
|
|
|
|
domain@1 {
|
|
sibling-cpus = "4-6";
|
|
cal-id = <0xb040003>;
|
|
dm-type = <0x01>;
|
|
max-freq = <0x2ad8c0>;
|
|
min-freq = <0x82208>;
|
|
#cooling-cells = <0x02>;
|
|
ect-coeff-index = <0x01>;
|
|
tz-cooling-name = "MID";
|
|
freq-table = <0x2b368 0x40f10 0x61a80 0x82208 0x98580 0xb1bc0 0xcb200 0xe4840 0xfde80 0x1174c0 0x130b00 0x14a140 0x163780 0x17cdc0 0x196400 0x1afa40 0x1c9080 0x1e26c0 0x1fbd00 0x215340 0x22e980 0x247fc0 0x261600 0x27ac40 0x294280 0x2ad8c0 0x2c6f00 0x2d9fb0>;
|
|
phandle = <0x113>;
|
|
|
|
dm-constraints {
|
|
list = <0xa0 0xa1>;
|
|
};
|
|
};
|
|
|
|
domain@2 {
|
|
sibling-cpus = "7";
|
|
cal-id = <0xb040004>;
|
|
dm-type = <0x02>;
|
|
max-freq = "\0,o";
|
|
min-freq = <0x82208>;
|
|
#cooling-cells = <0x02>;
|
|
ect-coeff-index = <0x00>;
|
|
tz-cooling-name = "BIG";
|
|
freq-table = <0x2b368 0x40f10 0x61a80 0x82208 0x98580 0xb1bc0 0xcb200 0xe4840 0xfde80 0x1174c0 0x130b00 0x14a140 0x163780 0x17cdc0 0x196400 0x1afa40 0x1c9080 0x1e26c0 0x1fbd00 0x215340 0x22e980 0x247fc0 0x261600 0x27ac40 0x294280 0x2ad8c0 0x2c6f00 0x2d9fb0>;
|
|
phandle = <0x110>;
|
|
|
|
dm-constraints {
|
|
list = <0xa2 0xa3>;
|
|
};
|
|
};
|
|
};
|
|
|
|
dm-tables {
|
|
|
|
dm-table@0000 {
|
|
const-type = <0x00>;
|
|
dm-slave = <0x06>;
|
|
master-cal-id = <0xb040002>;
|
|
slave-cal-id = <0xb040006>;
|
|
table = <0x2b368 0x2b368 0x40f10 0x2b368 0x61a80 0x40f10 0x82208 0x40f10 0x9eb10 0x61a80 0xb8150 0x82208 0xd1790 0x82208 0xeadd0 0x9eb10 0x104410 0x9eb10 0x11da50 0xb8150 0x137090 0xd1790 0x1506d0 0xeadd0 0x169d10 0xeadd0 0x183350 0x104410 0x19c990 0x11da50 0x1b5fd0 0x11da50 0x1cf610 0x137090 0x1e8c50 0x1506d0 0x202290 0x1506d0 0x21b8d0 0x169d10 0x234f10 0x183350 0x247fc0 0x19c990>;
|
|
phandle = <0x9e>;
|
|
};
|
|
|
|
dm-table@0001 {
|
|
const-type = <0x00>;
|
|
dm-slave = <0x06>;
|
|
master-cal-id = <0xb040003>;
|
|
slave-cal-id = <0xb040006>;
|
|
table = <0x2b368 0x2b368 0x40f10 0x2b368 0x61a80 0x40f10 0x82208 0x40f10 0x98580 0x61a80 0xb1bc0 0x61a80 0xcb200 0x82208 0xe4840 0x9eb10 0xfde80 0x9eb10 0x1174c0 0xb8150 0x130b00 0xd1790 0x14a140 0xd1790 0x163780 0xeadd0 0x17cdc0 0x104410 0x196400 0x11da50 0x1afa40 0x11da50 0x1c9080 0x137090 0x1e26c0 0x1506d0 0x1fbd00 0x1506d0 0x215340 0x169d10 0x22e980 0x183350 0x247fc0 0x183350 0x261600 0x19c990 0x27ac40 0x1b5fd0 0x294280 0x1b5fd0 0x2ad8c0 0x1cf610 0x2c6f00 0x1e8c50 0x2d9fb0 0x1e8c50>;
|
|
phandle = <0xa0>;
|
|
};
|
|
|
|
dm-table@0002 {
|
|
const-type = <0x00>;
|
|
dm-slave = <0x06>;
|
|
master-cal-id = <0xb040004>;
|
|
slave-cal-id = <0xb040006>;
|
|
table = <0x2b368 0x2b368 0x40f10 0x2b368 0x61a80 0x40f10 0x82208 0x40f10 0x98580 0x61a80 0xb1bc0 0x61a80 0xcb200 0x82208 0xe4840 0x9eb10 0xfde80 0x9eb10 0x1174c0 0xb8150 0x130b00 0xd1790 0x14a140 0xd1790 0x163780 0xeadd0 0x17cdc0 0x104410 0x196400 0x11da50 0x1afa40 0x11da50 0x1c9080 0x137090 0x1e26c0 0x1506d0 0x1fbd00 0x1506d0 0x215340 0x169d10 0x22e980 0x183350 0x247fc0 0x183350 0x261600 0x19c990 0x27ac40 0x1b5fd0 0x294280 0x1b5fd0 0x2ad8c0 0x1cf610 0x2c6f00 0x1e8c50 0x2d9fb0 0x1e8c50>;
|
|
phandle = <0xa2>;
|
|
};
|
|
|
|
dm-table@0003 {
|
|
const-type = <0x00>;
|
|
dm-slave = <0x03>;
|
|
master-cal-id = <0xb040002>;
|
|
slave-cal-id = <0xb040000>;
|
|
dynamic-disable;
|
|
table = <0x2b368 0x00 0x40f10 0x00 0x61a80 0x00 0x82208 0x00 0x9eb10 0x00 0xb8150 0x00 0xd1790 0x00 0xeadd0 0x00 0x104410 0x00 0x11da50 0x00 0x137090 0x00 0x1506d0 0x00 0x169d10 0x00 0x183350 0x00 0x19c990 0x00 0x1b5fd0 0x00 0x1cf610 0x00 0x1e8c50 0x00 0x202290 0x00 0x21b8d0 0x00 0x234f10 0x00 0x247fc0 0x00>;
|
|
phandle = <0x9f>;
|
|
};
|
|
|
|
dm-table@0004 {
|
|
const-type = <0x00>;
|
|
dm-slave = <0x03>;
|
|
master-cal-id = <0xb040003>;
|
|
slave-cal-id = <0xb040000>;
|
|
dynamic-disable;
|
|
table = <0x2b368 0x00 0x40f10 0x00 0x61a80 0x00 0x82208 0x00 0x98580 0x00 0xb1bc0 0x00 0xcb200 0x00 0xe4840 0x00 0xfde80 0x00 0x1174c0 0x00 0x130b00 0x00 0x14a140 0x00 0x163780 0x00 0x17cdc0 0x00 0x196400 0x00 0x1afa40 0x00 0x1c9080 0x00 0x1e26c0 0x00 0x1fbd00 0x22e980 0x215340 0x22e980 0x22e980 0x26ae58 0x247fc0 0x26ae58 0x261600 0x29a810 0x27ac40 0x29a810 0x294280 0x3066a0 0x2ad8c0 0x3066a0 0x2c6f00 0x3066a0 0x2d9fb0 0x3066a0>;
|
|
phandle = <0xa1>;
|
|
};
|
|
|
|
dm-table@0005 {
|
|
const-type = <0x00>;
|
|
dm-slave = <0x03>;
|
|
master-cal-id = <0xb040004>;
|
|
slave-cal-id = <0xb040000>;
|
|
dynamic-disable;
|
|
table = <0x2b368 0x00 0x40f10 0x00 0x61a80 0x00 0x82208 0x00 0x98580 0x00 0xb1bc0 0x00 0xcb200 0x00 0xe4840 0x00 0xfde80 0x00 0x1174c0 0x00 0x130b00 0x00 0x14a140 0x00 0x163780 0x00 0x17cdc0 0x00 0x196400 0x00 0x1afa40 0x00 0x1c9080 0x00 0x1e26c0 0x00 0x1fbd00 0x22e980 0x215340 0x22e980 0x22e980 0x26ae58 0x247fc0 0x26ae58 0x261600 0x29a810 0x27ac40 0x29a810 0x294280 0x3066a0 0x2ad8c0 0x3066a0 0x2c6f00 0x3066a0 0x2d9fb0 0x3066a0>;
|
|
phandle = <0xa3>;
|
|
};
|
|
};
|
|
|
|
exynos-dsufreq {
|
|
compatible = "samsung,exynos-dsufreq";
|
|
status = "okay";
|
|
cal-id = <0xb040006>;
|
|
dm-type = <0x06>;
|
|
dss-type = <0x0e>;
|
|
init-with-dt = <0x01>;
|
|
|
|
request_domain0 {
|
|
sibling-cpus = "0-3";
|
|
constraint = <0x9e>;
|
|
};
|
|
|
|
request_domain1 {
|
|
sibling-cpus = "4-6";
|
|
constraint = <0xa0>;
|
|
};
|
|
|
|
request_domain2 {
|
|
sibling-cpus = "7";
|
|
constraint = <0xa2>;
|
|
};
|
|
};
|
|
|
|
exynos-ufcc {
|
|
compatible = "samsung,exynos-ufcc";
|
|
status = "okay";
|
|
|
|
ucc {
|
|
|
|
ucc-config0 {
|
|
index = <0x00>;
|
|
cstate = "4-7";
|
|
};
|
|
|
|
ucc-config1 {
|
|
index = <0x01>;
|
|
cstate = "7";
|
|
};
|
|
|
|
ucc-config2 {
|
|
index = <0x03>;
|
|
};
|
|
};
|
|
|
|
ufc {
|
|
table-col = <0x06>;
|
|
boot-domain-auto-table;
|
|
|
|
domain@0 {
|
|
device_type = "ufc-domain";
|
|
shared-cpus = "0-3";
|
|
table-col-idx = <0x03>;
|
|
};
|
|
|
|
domain@1 {
|
|
device_type = "ufc-domain";
|
|
shared-cpus = "4-6";
|
|
table-col-idx = <0x02>;
|
|
allow-disable-cpus;
|
|
};
|
|
|
|
domain@2 {
|
|
device_type = "ufc-domain";
|
|
shared-cpus = "7";
|
|
table-col-idx = <0x01>;
|
|
allow-disable-cpus;
|
|
};
|
|
|
|
max-limit {
|
|
device_type = "ufc-table";
|
|
ctrl-type = <0x02>;
|
|
table = <0x2c6f00 0x2c6f00 0x2c6f00 0x21b8d0 0x00 0x00 0x2ad8c0 0x2ad8c0 0x2ad8c0 0x21b8d0 0x00 0x00 0x294280 0x294280 0x294280 0x21b8d0 0x00 0x00 0x27ac40 0x27ac40 0x27ac40 0x21b8d0 0x00 0x00 0x261600 0x261600 0x261600 0x21b8d0 0x00 0x00 0x247fc0 0x247fc0 0x247fc0 0x21b8d0 0x00 0x00 0x22e980 0x22e980 0x22e980 0x21b8d0 0x00 0x00 0x215340 0x215340 0x215340 0x21b8d0 0x00 0x00 0x1fbd00 0x1fbd00 0x1fbd00 0x21b8d0 0x00 0x00 0x1e26c0 0x1e26c0 0x1e26c0 0x21b8d0 0x00 0x00 0x1c9080 0x1c9080 0x1c9080 0x21b8d0 0x00 0x00 0x1afa40 0x1afa40 0x1afa40 0x21b8d0 0x00 0x00 0x196400 0x196400 0x196400 0x21b8d0 0x00 0x00 0x17cdc0 0x17cdc0 0x17cdc0 0x202290 0x00 0x00 0x163780 0x163780 0x163780 0x202290 0x00 0x00 0x14a140 0x14a140 0x14a140 0x1e8c50 0x00 0x00 0x130b00 0x130b00 0x130b00 0x1e8c50 0x00 0x00 0x1174c0 0x1174c0 0x1174c0 0x1cf610 0x00 0x00 0xfde80 0xfde80 0xfde80 0x1b5fd0 0x00 0x00 0xe4840 0xe4840 0xe4840 0x19c990 0x00 0x00 0xcb200 0xcb200 0xcb200 0x19c990 0x00 0x00 0xb1bc0 0xb1bc0 0xb1bc0 0x183350 0x00 0x00 0x98580 0x98580 0x98580 0x169d10 0x00 0x00 0x82208 0x82208 0x82208 0x1506d0 0x00 0x00>;
|
|
};
|
|
|
|
min-limit {
|
|
device_type = "ufc-table";
|
|
ctrl-type = <0x00>;
|
|
table = <0x2c6f00 0x2c6f00 0x2c6f00 0x21b8d0 0x02 0x01 0x2ad8c0 0x2ad8c0 0x2ad8c0 0x21b8d0 0x02 0x01 0x294280 0x294280 0x294280 0x21b8d0 0x02 0x01 0x27ac40 0x27ac40 0x27ac40 0x21b8d0 0x02 0x01 0x261600 0x261600 0x261600 0x21b8d0 0x02 0x01 0x247fc0 0x247fc0 0x247fc0 0x21b8d0 0x02 0x01 0x22e980 0x22e980 0x22e980 0xd1790 0x01 0x01 0x215340 0x215340 0x215340 0xd1790 0x01 0x01 0x1fbd00 0x1fbd00 0x1fbd00 0xd1790 0x01 0x01 0x1e26c0 0x1e26c0 0x1e26c0 0xd1790 0x01 0x01 0x1c9080 0x1c9080 0x1c9080 0xd1790 0x01 0x01 0x1afa40 0x1afa40 0x1afa40 0xd1790 0x01 0x01 0x196400 0x196400 0x196400 0xd1790 0x01 0x01 0x17cdc0 0x17cdc0 0x17cdc0 0xd1790 0x01 0x01 0x163780 0x163780 0x163780 0xd1790 0x00 0x01 0x14a140 0x14a140 0x14a140 0xd1790 0x00 0x01 0x130b00 0x130b00 0x130b00 0xd1790 0x00 0x01 0x1174c0 0x1174c0 0x1174c0 0xd1790 0x00 0x01 0xfde80 0xfde80 0xfde80 0xd1790 0x00 0x01 0xe4840 0xe4840 0xe4840 0xd1790 0x00 0x01 0xcb200 0xcb200 0xcb200 0xd1790 0x00 0x01 0xb1bc0 0xb1bc0 0xb1bc0 0xd1790 0x00 0x01 0x98580 0x98580 0x98580 0xd1790 0x00 0x01 0x82208 0x82208 0x82208 0xd1790 0x00 0x01>;
|
|
};
|
|
};
|
|
};
|
|
|
|
exynos-afm {
|
|
compatible = "samsung,exynos-afm";
|
|
status = "okay";
|
|
|
|
domain@1 {
|
|
device_type = "afm-domain";
|
|
compatible = "samsung,exynos-afm";
|
|
interrupts = <0x00 0xa4 0x04>;
|
|
sibling-cpus = "4-6";
|
|
cluster = <0x01>;
|
|
down-step = <0x01>;
|
|
max-freq-wo-afm = <0x1fbd00>;
|
|
release-duration = <0x0f>;
|
|
phandle = <0x267>;
|
|
};
|
|
|
|
domain@2 {
|
|
device_type = "afm-domain";
|
|
compatible = "samsung,exynos-afm";
|
|
interrupts = <0x00 0xa5 0x04>;
|
|
sibling-cpus = "7";
|
|
cluster = <0x02>;
|
|
down-step = <0x01>;
|
|
max-freq-wo-afm = <0x1fbd00>;
|
|
release-duration = <0x0f>;
|
|
phandle = <0x268>;
|
|
};
|
|
};
|
|
|
|
freq-qos-tracer {
|
|
compatible = "samsung,freq-qos-tracer";
|
|
status = "okay";
|
|
};
|
|
|
|
sysmmu@19D00000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x19d00000 0x9000>;
|
|
interrupts = <0x00 0x12d 0x04 0x00 0x12e 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x19d30000>;
|
|
sysmmu,default_tlb = <0xca>;
|
|
sysmmu,tlb_property = <0x01 0xca 0x100 0xf0005 0x02 0x8a 0x100 0xf0008 0x03 0x0a 0x100 0xf0006 0x04 0x0a 0x100 0xf000a 0x05 0x0a 0x100 0xf000c 0x06 0x0a 0x100 0x1f001e 0x07 0x0a 0x100 0xf0000 0x08 0x0a 0x100 0xf0007 0x09 0x0a 0x100 0xf000d 0x0a 0x0a 0x100 0x1f000e 0x0b 0x0a 0x100 0x1f000f>;
|
|
port-name = "DPUF0 D0";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x2fc>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xa4>;
|
|
phandle = <0xba>;
|
|
};
|
|
|
|
sysmmu@19D10000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x19d10000 0x9000>;
|
|
interrupts = <0x00 0x130 0x04 0x00 0x131 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x19d40000>;
|
|
sysmmu,default_tlb = <0x8a>;
|
|
sysmmu,tlb_property = <0x01 0x8a 0x100 0xf000c 0x02 0x0a 0x100 0xf000d 0x03 0x0a 0x100 0xf0002 0x04 0x0a 0x100 0xf0004 0x05 0x0a 0x100 0x1f000e 0x06 0x0a 0x100 0x1f001e 0x07 0x0a 0x100 0xf0005 0x08 0x0a 0x100 0xf0008 0x09 0x0a 0x100 0x1f000f 0x0a 0x0a 0x200 0xf0000 0x0b 0x0a 0x200 0xf0001 0x0c 0x00 0x200 0xf0008>;
|
|
port-name = "DPUF0 D1";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x2fe>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xa4>;
|
|
phandle = <0xbb>;
|
|
};
|
|
|
|
sysmmu@1AF00000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x1af00000 0x9000>;
|
|
interrupts = <0x00 0x145 0x04 0x00 0x146 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x1af30000>;
|
|
sysmmu,default_tlb = <0xca>;
|
|
sysmmu,tlb_property = <0x01 0xca 0x100 0xf0005 0x02 0x8a 0x100 0xf0008 0x03 0x0a 0x100 0xf0006 0x04 0x0a 0x100 0xf000a 0x05 0x0a 0x100 0xf000c 0x06 0x0a 0x100 0x1f001e 0x07 0x0a 0x100 0xf0000 0x08 0x0a 0x100 0xf0007 0x09 0x0a 0x100 0xf000d 0x0a 0x0a 0x100 0x1f000e 0x0b 0x0a 0x100 0x1f000f>;
|
|
port-name = "DPUF1 D0";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x328>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xa5>;
|
|
phandle = <0xbc>;
|
|
};
|
|
|
|
sysmmu@1AF10000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x1af10000 0x9000>;
|
|
interrupts = <0x00 0x148 0x04 0x00 0x149 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x1af40000>;
|
|
sysmmu,default_tlb = <0x8a>;
|
|
sysmmu,tlb_property = <0x01 0x8a 0x100 0xf000c 0x03 0x0a 0x100 0xf0002 0x04 0x0a 0x100 0xf0004 0x05 0x0a 0x100 0x1f000e 0x06 0x0a 0x100 0xf0005 0x07 0x0a 0x100 0xf0008 0x08 0x0a 0x100 0xf000d 0x09 0x0a 0x100 0x1f000f>;
|
|
port-name = "DPUF1 D1";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x32a>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xa5>;
|
|
phandle = <0xbd>;
|
|
};
|
|
|
|
sysmmu@17110000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x17110000 0x9000>;
|
|
interrupts = <0x00 0xd7 0x04 0x00 0xd8 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x17100000>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x200 0xf0002 0x02 0x0a 0x200 0xf0004 0x03 0x0a 0x200 0xf0006 0x04 0x0a 0x200 0xf0008 0x05 0x0a 0x200 0xf000a 0x06 0x0a 0x200 0xf000c 0x07 0x0a 0x200 0xf000e 0x08 0x0a 0x200 0xf0001 0x09 0x0a 0x200 0xf0005 0x0a 0x0a 0x200 0xf0009 0x0b 0x0a 0x200 0xf000d>;
|
|
port-name = "CSIS DMA0,1";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0xd8>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xa6>;
|
|
phandle = <0x269>;
|
|
};
|
|
|
|
sysmmu@17140000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x17140000 0x9000>;
|
|
interrupts = <0x00 0xda 0x04 0x00 0xdb 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x17130000>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x200 0xf0004 0x02 0x0a 0x200 0xf0008 0x03 0x0a 0x200 0xf000c 0x04 0x0a 0x200 0xf0001 0x05 0x0a 0x200 0xf0005 0x06 0x0a 0x200 0xf0009 0x07 0x0a 0x200 0xf000d>;
|
|
port-name = "CSIS DMA2,3";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0xdb>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xa6>;
|
|
phandle = <0x26a>;
|
|
};
|
|
|
|
sysmmu@17170000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x17170000 0x9000>;
|
|
interrupts = <0x00 0xdd 0x04 0x00 0xe2 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x17160000>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x200 0x70004 0x02 0x0a 0x200 0x70001 0x03 0x0a 0x200 0x70002 0x04 0x0a 0x200 0x70003>;
|
|
port-name = "CSIS ZSL0";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0xe2>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xa6>;
|
|
phandle = <0x26b>;
|
|
};
|
|
|
|
sysmmu@171A0000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x171a0000 0x9000>;
|
|
interrupts = <0x00 0xe4 0x04 0x00 0xe5 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x17190000>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x200 0x7f0040 0x02 0x0a 0x200 0x7f0008 0x03 0x0a 0x200 0x7f0010 0x04 0x0a 0x200 0x7f0018 0x05 0x0a 0x200 0xf0001 0x06 0x0a 0x100 0xf0001 0x07 0x0a 0x100 0xf0009 0x08 0x0a 0x200 0xf0002 0x09 0x0a 0x100 0xf0002 0x0a 0x0a 0x200 0xf0003 0x0b 0x0a 0x100 0xf0003 0x0c 0x0a 0x200 0xf0004 0x0d 0x0a 0x100 0xf0004 0x0e 0x0a 0x100 0xf0005 0x0f 0x0a 0x100 0xf0006 0x10 0x0a 0x200 0x7f0020 0x11 0x00 0x200 0x7f0028 0x12 0x00 0x200 0xf0007>;
|
|
port-name = "CSIS STRP,PDP";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0xe5>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xa6>;
|
|
phandle = <0x26c>;
|
|
};
|
|
|
|
sysmmu@17770000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x17770000 0x9000>;
|
|
interrupts = <0x00 0x179 0x04 0x00 0x17a 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x17780000>;
|
|
sysmmu,default_tlb = <0x20>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x200 0x70000 0x02 0x0a 0x200 0x70002 0x03 0x00 0x200 0x70003>;
|
|
port-name = "LME";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x4b6>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xa7>;
|
|
phandle = <0x26d>;
|
|
};
|
|
|
|
sysmmu@16E40000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x16e40000 0x9000>;
|
|
interrupts = <0x00 0x247 0x04 0x00 0x248 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x16e30000>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x200 0x1ff0080 0x02 0x0a 0x200 0x1ff0100 0x03 0x0a 0x200 0x1ff0180 0x04 0x0a 0x200 0x1ff0001 0x05 0x0a 0x200 0x1ff0081 0x06 0x0a 0x200 0x1ff0101 0x07 0x0a 0x200 0x1ff0181 0x08 0x0a 0x200 0x1ff0002 0x09 0x0a 0x200 0x1ff0022 0x0a 0x0a 0x200 0x1ff0042 0x0b 0x0a 0x200 0x1ff0082 0x0c 0x0a 0x200 0x1ff00a2 0x0d 0x0a 0x200 0x1ff00c2 0x0e 0x0a 0x200 0x1ff0102 0x0f 0x0a 0x200 0x1ff0122 0x10 0x0a 0x200 0x1ff0142 0x11 0x0a 0x200 0x1ff0182 0x12 0x0a 0x200 0x1ff01a2 0x13 0x0a 0x200 0x1ff01c2 0x14 0x0a 0x200 0x1ff0003 0x15 0x0a 0x200 0x1ff0084 0x16 0x0a 0x200 0x1ff0105 0x17 0x0a 0x200 0x1ff0186 0x18 0x0a 0x200 0x1ff0007 0x19 0x0a 0x200 0x1ff0087 0x1a 0x0a 0x200 0x1ff0107 0x1b 0x0a 0x200 0x1ff0187 0x1c 0x0a 0x200 0x1ff0008 0x1d 0x0a 0x200 0x1ff0088 0x1e 0x0a 0x200 0x1ff0108 0x1f 0x0a 0x200 0x1ff0188 0x20 0x0a 0x200 0x1ff0009 0x21 0x0a 0x200 0x1ff0089 0x22 0x0a 0x200 0x1ff0109 0x23 0x0a 0x200 0x1ff0189 0x24 0x0a 0x200 0x1ff000a 0x25 0x0a 0x200 0x1ff008a 0x26 0x0a 0x200 0x1ff010a 0x27 0x0a 0x200 0x1ff018a 0x28 0x00 0x200 0x1f000b 0x29 0x00 0x200 0x1f000c>;
|
|
port-name = "TAA";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x870>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xa8>;
|
|
phandle = <0x26e>;
|
|
};
|
|
|
|
sysmmu@18080000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x18080000 0x9000>;
|
|
interrupts = <0x00 0x274 0x04 0x00 0x275 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x18090000>;
|
|
sysmmu,default_tlb = <0x40>;
|
|
sysmmu,tlb_property = <0x01 0x40 0x200 0x30000 0x02 0x0a 0x100 0x70001 0x03 0x0a 0x100 0x70005 0x04 0x0a 0x100 0x70002 0x05 0x0a 0x100 0x70006 0x06 0x00 0x200 0x70003>;
|
|
port-name = "YUVPP";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x96d>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xa9>;
|
|
phandle = <0x26f>;
|
|
};
|
|
|
|
sysmmu@17540000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x17540000 0x9000>;
|
|
interrupts = <0x00 0xf0 0x04 0x00 0xf1 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x17550000>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x200 0xf0000 0x02 0x0a 0x100 0xf0001 0x03 0x0a 0x200 0xf0001 0x04 0x0a 0x100 0xf0002 0x05 0x0a 0x200 0xf0002 0x06 0x0a 0x200 0xf000a 0x07 0x0a 0x100 0xf0003 0x08 0x0a 0x200 0xf0003 0x09 0x0a 0x100 0xf0004 0x0a 0x0a 0x200 0xf0004 0x0b 0x0a 0x100 0xf0005 0x0c 0x0a 0x200 0xf0005 0x0d 0x0a 0x200 0xf000d 0x0e 0x0a 0x100 0xf0006 0x0f 0x0a 0x200 0xf0006 0x10 0x0a 0x100 0xf0007 0x11 0x0a 0x200 0xf0007>;
|
|
port-name = "DNS M0-M7";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x293>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xaa>;
|
|
phandle = <0x270>;
|
|
};
|
|
|
|
sysmmu@17580000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x17580000 0x9000>;
|
|
interrupts = <0x00 0xf3 0x04 0x00 0xf4 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x17590000>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x200 0xf0000 0x02 0x0a 0x200 0xf0004 0x03 0x0a 0x100 0xf0001 0x04 0x0a 0x200 0xf0001 0x05 0x0a 0x100 0xf0002 0x06 0x0a 0x200 0xf0002 0x07 0x0a 0x200 0xf0003 0x08 0x0a 0x200 0xe0004>;
|
|
port-name = "DNS M8-M10";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x295>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xaa>;
|
|
phandle = <0x271>;
|
|
};
|
|
|
|
sysmmu@15CA0000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x15ca0000 0x9000>;
|
|
interrupts = <0x00 0x1a3 0x04 0x00 0x1a4 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x15cb0000>;
|
|
sysmmu,default_tlb = <0xaa>;
|
|
sysmmu,tlb_property = <0x01 0xaa 0x100 0x70001 0x02 0x8a 0x200 0xf0000 0x03 0x8a 0x200 0xf0008 0x04 0x0a 0x200 0xf0004 0x05 0x0a 0x200 0xf000c 0x06 0x00 0x200 0x70002 0x07 0x00 0x200 0x70003>;
|
|
port-name = "GDC0 M0, M3";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x58c>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xab>;
|
|
phandle = <0x272>;
|
|
};
|
|
|
|
sysmmu@15CD0000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x15cd0000 0x9000>;
|
|
interrupts = <0x00 0x1a6 0x04 0x00 0x1a7 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x15ce0000>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x200 0x1f0000 0x02 0x0a 0x200 0x1f0008 0x03 0x0a 0x200 0x1f0010 0x04 0x0a 0x200 0x1f0001 0x05 0x0a 0x200 0x1f0009 0x06 0x0a 0x200 0x1f0011 0x07 0x0a 0x100 0x7f0002 0x08 0x0a 0x100 0x7f0006 0x09 0x0a 0x100 0x7f000a 0x0a 0x0a 0x100 0x7f000e 0x0b 0x0a 0x100 0x7f0012 0x0c 0x0a 0x100 0x7f0016 0x0d 0x0a 0x100 0x7f001a 0x0e 0x0a 0x100 0x7f005a 0x0f 0x0a 0x100 0x7f001e>;
|
|
port-name = "GDC1 M0, MCSC M4";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x58e>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xab>;
|
|
phandle = <0x273>;
|
|
};
|
|
|
|
sysmmu@15D00000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x15d00000 0x9000>;
|
|
interrupts = <0x00 0x1a9 0x04 0x00 0x1aa 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x15d10000>;
|
|
sysmmu,tlb_property = <0x02 0x0a 0x200 0x3f0000 0x03 0x0a 0x200 0x3f0008 0x04 0x0a 0x200 0x3f0010 0x05 0x0a 0x200 0x3f0018 0x06 0x0a 0x200 0x3f0020 0x07 0x0a 0x200 0x3f0001 0x08 0x0a 0x200 0x3f0009 0x09 0x0a 0x200 0x3f0011 0x0a 0x0a 0x200 0x3f0019 0x0b 0x0a 0x200 0x3f0021 0x0c 0x0a 0x200 0x3f0002 0x0d 0x0a 0x200 0x3f0012 0x0e 0x0a 0x200 0x3f0022 0x0f 0x00 0x200 0xf0003 0x10 0x00 0x200 0xf0004>;
|
|
port-name = "MCSC M0-M2";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x590>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xab>;
|
|
phandle = <0x274>;
|
|
};
|
|
|
|
sysmmu@178A0000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x178a0000 0x9000>;
|
|
interrupts = <0x00 0x185 0x04 0x00 0x186 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x178b0000>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x100 0x70001 0x02 0x0a 0x100 0x70002 0x03 0x0a 0x100 0x70004 0x04 0x0a 0x200 0x70000 0x05 0x0a 0x200 0x70004 0x06 0x8a 0x100 0x70003>;
|
|
port-name = "MCFP0 M0-M3";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x51f>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xac>;
|
|
phandle = <0x275>;
|
|
};
|
|
|
|
sysmmu@178D0000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x178d0000 0x9000>;
|
|
interrupts = <0x00 0x188 0x04 0x00 0x189 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x178e0000>;
|
|
sysmmu,default_tlb = <0xaa>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x100 0x10001 0x02 0x0a 0x200 0x10000>;
|
|
port-name = "MCFP0 M4";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x521>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xac>;
|
|
phandle = <0x276>;
|
|
};
|
|
|
|
sysmmu@17900000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x17900000 0x9000>;
|
|
interrupts = <0x00 0x18b 0x04 0x00 0x18c 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x17910000>;
|
|
sysmmu,default_tlb = <0xaa>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x100 0x10001>;
|
|
port-name = "MCFP0 M5";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x523>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xad>;
|
|
phandle = <0x277>;
|
|
};
|
|
|
|
sysmmu@17930000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x17930000 0x9000>;
|
|
interrupts = <0x00 0x18e 0x04 0x00 0x18f 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x17940000>;
|
|
sysmmu,default_tlb = <0xaa>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x100 0x10001>;
|
|
port-name = "MCFP0 M6";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x525>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xad>;
|
|
phandle = <0x278>;
|
|
};
|
|
|
|
sysmmu@17A70000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x17a70000 0x9000>;
|
|
interrupts = <0x00 0x193 0x04 0x00 0x194 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x17a80000>;
|
|
sysmmu,default_tlb = <0x8a>;
|
|
sysmmu,tlb_property = <0x01 0x8a 0x100 0xf0005 0x02 0x8a 0x100 0xf0006 0x03 0x4a 0x100 0xf0000 0x04 0x4a 0x100 0xf0004 0x05 0x40 0x200 0xf0000 0x06 0x40 0x200 0xf0004 0x07 0x0a 0x200 0xf0001 0x08 0x0a 0x200 0xf0005 0x09 0x00 0x200 0xf0003 0x0a 0x00 0x200 0xf0007>;
|
|
port-name = "ORBMCH M0-M2";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x551>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xac>;
|
|
phandle = <0x279>;
|
|
};
|
|
|
|
sysmmu@18670000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x18670000 0x9000>;
|
|
interrupts = <0x00 0x1ad 0x04 0x00 0x1ae 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x18680000>;
|
|
sysmmu,default_tlb = <0x60>;
|
|
port-name = "MFC0 D0";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x5eb>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xae>;
|
|
phandle = <0x142>;
|
|
};
|
|
|
|
sysmmu@186A0000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x186a0000 0x9000>;
|
|
interrupts = <0x00 0x1b0 0x04 0x00 0x1b1 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x186b0000>;
|
|
sysmmu,default_tlb = <0x60>;
|
|
sysmmu,tlb_property = <0x01 0x20 0x300 0x70001 0x02 0x00 0x300 0x70002>;
|
|
port-name = "MFC0 D1";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x5ed>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xae>;
|
|
phandle = <0x143>;
|
|
};
|
|
|
|
sysmmu@18870000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x18870000 0x9000>;
|
|
interrupts = <0x00 0x1b5 0x04 0x00 0x1b6 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x18880000>;
|
|
sysmmu,default_tlb = <0x60>;
|
|
port-name = "MFC1 D0";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x616>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xaf>;
|
|
phandle = <0x144>;
|
|
};
|
|
|
|
sysmmu@188A0000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x188a0000 0x9000>;
|
|
interrupts = <0x00 0x1b8 0x04 0x00 0x1b9 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x188b0000>;
|
|
sysmmu,default_tlb = <0x60>;
|
|
port-name = "MFC1 D1";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x618>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xaf>;
|
|
phandle = <0x145>;
|
|
};
|
|
|
|
sysmmu@18A00000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x18a00000 0x9000>;
|
|
interrupts = <0x00 0x181 0x04 0x00 0x182 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x18a10000>;
|
|
sysmmu,default_tlb = <0xa0>;
|
|
sysmmu,tlb_property = <0x01 0x60 0x300 0x70000 0x02 0x60 0x300 0x70001 0x03 0x00 0x300 0x70004 0x04 0x00 0x300 0x70003 0x05 0x00 0x200 0xf000a>;
|
|
port-name = "MSCL, SMFC";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x4f0>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xb0>;
|
|
phandle = <0x148>;
|
|
};
|
|
|
|
sysmmu@18D50000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x18d50000 0x9000>;
|
|
interrupts = <0x00 0x1b 0x04 0x00 0x1c 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x18d60000>;
|
|
sysmmu,no-suspend;
|
|
sysmmu,default_tlb = <0x00>;
|
|
sysmmu,tlb_property = <0x01 0x00 0x300 0xf0001 0x02 0x00 0x300 0xf0009 0x03 0x00 0x300 0x70005 0x04 0x00 0x300 0x70003 0x05 0x00 0x300 0x70004 0x06 0x00 0x300 0xf0007 0x07 0x00 0x300 0xf000f>;
|
|
port-name = "AUD";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x7f>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xb1>;
|
|
phandle = <0x14b>;
|
|
};
|
|
|
|
sysmmu@17C50000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x17c50000 0x9000>;
|
|
interrupts = <0x00 0x1e3 0x04 0x00 0x1e4 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x17c60000>;
|
|
sysmmu,default_tlb = <0x8a>;
|
|
sysmmu,tlb_property = <0x01 0x8a 0x100 0x70000 0x02 0x8a 0x100 0x70004 0x03 0x8a 0x200 0x30001 0x04 0x8a 0x100 0x70001 0x05 0x8a 0x100 0x70005 0x06 0x0a 0x200 0x30002 0x07 0x0a 0x100 0x70002 0x08 0x0a 0x100 0x70006 0x09 0x0a 0x200 0x30003 0x0a 0x0a 0x100 0x70003 0x0b 0x0a 0x100 0x70007>;
|
|
port-name = "IP NPUS M13";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x6b5>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xb2>;
|
|
phandle = <0x27a>;
|
|
};
|
|
|
|
sysmmu@17C80000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x17c80000 0x9000>;
|
|
interrupts = <0x00 0x1e6 0x04 0x00 0x1e7 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x17c90000>;
|
|
sysmmu,default_tlb = <0x8a>;
|
|
sysmmu,tlb_property = <0x01 0x8a 0x100 0x70000 0x02 0x8a 0x100 0x70004 0x03 0x0a 0x200 0x30002 0x04 0x0a 0x100 0x70002 0x05 0x0a 0x100 0x70006>;
|
|
port-name = "IP NPUS M14";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x6b7>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xb2>;
|
|
phandle = <0x27b>;
|
|
};
|
|
|
|
sysmmu@17CB0000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x17cb0000 0x9000>;
|
|
interrupts = <0x00 0x1e9 0x04 0x00 0x1ea 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x17cc0000>;
|
|
sysmmu,default_tlb = <0x0a>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x100 0xf0003 0x02 0x0a 0x100 0xf0005 0x03 0x0a 0x100 0xf0007 0x04 0x0a 0x300 0x370006 0x05 0x8a 0x300 0x370002 0x06 0x8a 0x300 0x370012 0x07 0x8a 0x300 0x370022 0x08 0x8a 0x300 0x370032 0x09 0x00 0x300 0x70004 0x0a 0x00 0x200 0xd0009>;
|
|
port-name = "IP NPUS M15";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x6b9>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xb2>;
|
|
phandle = <0x27c>;
|
|
};
|
|
|
|
sysmmu@16650000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x16650000 0x9000>;
|
|
interrupts = <0x00 0x267 0x04 0x00 0x268 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x16660000>;
|
|
sysmmu,default_tlb = <0x60>;
|
|
port-name = "VPC M0";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x8a2>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xb3>;
|
|
phandle = <0x27d>;
|
|
};
|
|
|
|
sysmmu@16680000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x16680000 0x9000>;
|
|
interrupts = <0x00 0x26a 0x04 0x00 0x26b 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x16690000>;
|
|
sysmmu,default_tlb = <0x60>;
|
|
port-name = "VPC M1";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x8a4>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xb3>;
|
|
phandle = <0x27e>;
|
|
};
|
|
|
|
sysmmu@166B0000 {
|
|
compatible = "samsung,sysmmu-v8";
|
|
reg = <0x00 0x166b0000 0x9000>;
|
|
interrupts = <0x00 0x26d 0x04 0x00 0x26e 0x04>;
|
|
qos = <0x0f>;
|
|
sysmmu,secure-irq;
|
|
sysmmu,secure_base = <0x166c0000>;
|
|
sysmmu,default_tlb = <0x00>;
|
|
sysmmu,tlb_property = <0x01 0x0a 0x100 0x370000 0x02 0x0a 0x100 0x370001 0x03 0x0a 0x100 0x370002 0x04 0x0a 0x300 0x370010 0x05 0x0a 0x300 0x370011 0x06 0x0a 0x300 0x370012 0x07 0x0a 0x200 0x200020>;
|
|
port-name = "VPC M2";
|
|
#iommu-cells = <0x00>;
|
|
clocks = <0x04 0x8a6>;
|
|
clock-names = "aclk";
|
|
power-domains = <0xb3>;
|
|
phandle = <0x27f>;
|
|
};
|
|
|
|
sysreg_hsi1_ufs@11020000 {
|
|
compatible = "samsung,exynos991-sysreg-hsi1-ufs\0syscon";
|
|
reg = <0x00 0x11020000 0x1000>;
|
|
phandle = <0xb8>;
|
|
};
|
|
|
|
ufs@0x13100000 {
|
|
compatible = "samsung,exynos-ufs";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
reg = <0x00 0x13100000 0x200 0x00 0x13101100 0x200 0x00 0x13180000 0x8000 0x00 0x132a0000 0x100 0x00 0x13104000 0x4000 0x00 0x13108000 0x804>;
|
|
interrupts = <0x00 0x10e 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <0xb4 0xb5 0xb6>;
|
|
clocks = <0x04 0x436 0x04 0x438>;
|
|
clock-names = "GATE_UFS_EMBD\0UFS_EMBD";
|
|
brd-for-cal = [10];
|
|
freq-table-hz = <0x00 0x00 0x00 0x00>;
|
|
vcc-supply = <0xb7>;
|
|
vcc-fixed-regulator;
|
|
ufs,pmd-attr-lane = [02];
|
|
ufs,pmd-attr-gear = [04];
|
|
evt-ver = [01];
|
|
dma-coherent;
|
|
samsung,sysreg-phandle = <0xb8>;
|
|
phandle = <0x280>;
|
|
|
|
phy-tcxo-con {
|
|
offset = <0x3e10>;
|
|
mask = <0x08>;
|
|
val = <0x08>;
|
|
};
|
|
|
|
ufs-phy-iso {
|
|
offset = <0x728>;
|
|
mask = <0x01>;
|
|
val = <0x01>;
|
|
};
|
|
|
|
ufs-iocc {
|
|
offset = <0x700>;
|
|
mask = <0x300000>;
|
|
val = <0x300000>;
|
|
};
|
|
|
|
ufs-pm-qos {
|
|
freq-int = <0x412f8>;
|
|
};
|
|
};
|
|
|
|
fixedregulator@0 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "ufs-vcc";
|
|
gpio = <0xb9 0x00 0x00>;
|
|
enable-active-high;
|
|
phandle = <0xb7>;
|
|
};
|
|
|
|
fragment@lcd {
|
|
target-path = "/";
|
|
|
|
__overlay__ {
|
|
|
|
emul_display {
|
|
id = <0xffffff>;
|
|
mode = <0x00>;
|
|
resolution = <0x280 0x1e0>;
|
|
size = <0x50 0x78>;
|
|
timing,refresh = <0x3c>;
|
|
timing,h-porch = <0x14 0x14 0x14>;
|
|
timing,v-porch = <0x14 0x14 0x14>;
|
|
timing,dsi-hs-clk = <0x258>;
|
|
timing,pmsk = <0x01 0x60 0x02 0x00>;
|
|
timing,dsi-escape-clk = <0x14>;
|
|
underrun_lp_ref = <0x133>;
|
|
mic_en = <0x00>;
|
|
mic_ratio = <0x00>;
|
|
mic_ver = <0x02>;
|
|
type_of_ddi = <0x00>;
|
|
dsc_en = <0x00>;
|
|
dsc_cnt = <0x00>;
|
|
dsc_slice_num = <0x00>;
|
|
data_lane = <0x04>;
|
|
cmd_underrun_lp_ref = <0x4b3>;
|
|
vt_compensation = <0x29eb>;
|
|
hdr_num = <0x00>;
|
|
hdr_type = <0x00 0x00 0x00 0x00>;
|
|
hdr_max_luma = <0x00>;
|
|
hdr_max_avg_luma = <0x00>;
|
|
hdr_min_luma = <0x00>;
|
|
phandle = <0x281>;
|
|
};
|
|
|
|
s6e3hf4_wqhd {
|
|
mode = <0x02>;
|
|
resolution = <0x5a0 0xa00>;
|
|
size = <0x44 0x7a>;
|
|
timing,refresh = <0x3c>;
|
|
timing,h-porch = <0x02 0x02 0x02>;
|
|
timing,v-porch = <0x0f 0x03 0x01>;
|
|
timing,dsi-hs-clk = <0x44c>;
|
|
timing,pmsk = <0x03 0xfe 0x02 0x00>;
|
|
timing,dsi-escape-clk = <0x14>;
|
|
mic_en = <0x00>;
|
|
mic_ratio = <0x02>;
|
|
mic_ver = <0x02>;
|
|
type_of_ddi = <0x00>;
|
|
dsc_en = <0x01>;
|
|
dsc_cnt = <0x02>;
|
|
dsc_slice_num = <0x04>;
|
|
dsc_slice_h = <0x40>;
|
|
data_lane = <0x04>;
|
|
cmd_underrun_lp_ref = <0x15fd>;
|
|
mres_en = <0x00>;
|
|
mres_number = <0x01>;
|
|
mres_width = <0x5a0 0x00 0x00>;
|
|
mres_height = <0xa00 0x00 0x00>;
|
|
mres_dsc_width = <0x168 0x00 0x00>;
|
|
mres_dsc_height = <0x40 0x00 0x00>;
|
|
mres_dsc_en = <0x01 0x00 0x00>;
|
|
hdr_num = <0x01>;
|
|
hdr_type = <0x02 0x00 0x00 0x00>;
|
|
hdr_max_luma = <0x5265c0>;
|
|
hdr_max_avg_luma = <0x124f80>;
|
|
hdr_min_luma = <0x05>;
|
|
phandle = <0x282>;
|
|
};
|
|
|
|
s6e3ha2k_wqhd {
|
|
mode = <0x02>;
|
|
resolution = <0x5a0 0xa00>;
|
|
size = <0x50 0x78>;
|
|
timing,refresh = <0x3c>;
|
|
timing,h-porch = <0x02 0x02 0x02>;
|
|
timing,v-porch = <0x13 0x03 0x01>;
|
|
timing,dsi-hs-clk = <0x44c>;
|
|
timing,pmsk = <0x03 0x7f 0x00 0x00>;
|
|
timing,dsi-escape-clk = <0x14>;
|
|
mic_en = <0x01>;
|
|
mic_ratio = <0x00>;
|
|
mic_ver = <0x02>;
|
|
type_of_ddi = <0x00>;
|
|
dsc_en = <0x00>;
|
|
dsc_cnt = <0x00>;
|
|
dsc_slice_num = <0x00>;
|
|
dsc_slice_h = <0x00>;
|
|
data_lane = <0x04>;
|
|
cmd_underrun_lp_ref = <0x4b3>;
|
|
mres_en = <0x00>;
|
|
mres_number = <0x01>;
|
|
mres_width = <0x5a0 0x00 0x00>;
|
|
mres_height = <0xa00 0x00 0x00>;
|
|
mres_dsc_width = <0x00 0x00 0x00>;
|
|
mres_dsc_height = <0x00 0x00 0x00>;
|
|
mres_dsc_en = <0x00 0x00 0x00>;
|
|
hdr_num = <0x01>;
|
|
hdr_type = <0x02 0x00 0x00 0x00>;
|
|
hdr_max_luma = <0x5265c0>;
|
|
hdr_max_avg_luma = <0x124f80>;
|
|
hdr_min_luma = <0x05>;
|
|
phandle = <0x283>;
|
|
};
|
|
|
|
s6e3ha3_wqhd {
|
|
mode = <0x02>;
|
|
resolution = <0x5a0 0xa00>;
|
|
size = <0x46 0x79>;
|
|
timing,refresh = <0x3c>;
|
|
timing,h-porch = <0x02 0x02 0x02>;
|
|
timing,v-porch = <0x13 0x03 0x01>;
|
|
timing,dsi-hs-clk = <0x44c>;
|
|
timing,pmsk = <0x03 0x7f 0x00 0x00>;
|
|
timing,dsi-escape-clk = <0x14>;
|
|
mic_en = <0x00>;
|
|
mic_ratio = <0x02>;
|
|
mic_ver = <0x02>;
|
|
type_of_ddi = <0x00>;
|
|
dsc_en = <0x01>;
|
|
dsc_cnt = <0x01>;
|
|
dsc_slice_num = <0x01>;
|
|
dsc_slice_h = <0x20>;
|
|
data_lane = <0x04>;
|
|
cmd_underrun_lp_ref = <0x4b3>;
|
|
mres_en = <0x00>;
|
|
mres_number = <0x01>;
|
|
mres_width = <0x5a0 0x00 0x00>;
|
|
mres_height = <0xa00 0x00 0x00>;
|
|
mres_dsc_width = <0x5a0 0x00 0x00>;
|
|
mres_dsc_height = <0x20 0x00 0x00>;
|
|
mres_dsc_en = <0x01 0x00 0x00>;
|
|
hdr_num = <0x01>;
|
|
hdr_type = <0x02 0x00 0x00 0x00>;
|
|
hdr_max_luma = <0x5265c0>;
|
|
hdr_max_avg_luma = <0x124f80>;
|
|
hdr_min_luma = <0x05>;
|
|
phandle = <0x284>;
|
|
};
|
|
|
|
s6e3ha6_ddi {
|
|
mode = <0x02>;
|
|
resolution = <0x5a0 0xb90>;
|
|
size = <0x45 0x8e>;
|
|
timing,refresh = <0x3c>;
|
|
timing,h-porch = <0x02 0x02 0x02>;
|
|
timing,v-porch = <0x0f 0x03 0x01>;
|
|
timing,dsi-hs-clk = <0x382>;
|
|
timing,pmsk = <0x02 0x114 0x02 0x4ec5 0x0d 0x06 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
timing,dsi-escape-clk = <0x14>;
|
|
mic_en = <0x00>;
|
|
mic_ratio = <0x02>;
|
|
mic_ver = <0x02>;
|
|
type_of_ddi = <0x00>;
|
|
dsc_en = <0x01>;
|
|
dsc_cnt = <0x02>;
|
|
dsc_slice_num = <0x02>;
|
|
dsc_slice_h = <0x28>;
|
|
data_lane = <0x04>;
|
|
cmd_underrun_lp_ref = <0xea0 0x14ef 0x110f>;
|
|
mres_en = <0x01>;
|
|
mres_number = <0x03>;
|
|
mres_width = <0x5a0 0x438 0x2d0>;
|
|
mres_height = <0xb90 0x8ac 0x5c8>;
|
|
mres_dsc_width = <0x2d0 0x21c 0x168>;
|
|
mres_dsc_height = <0x28 0x1e 0x4a>;
|
|
mres_dsc_en = <0x01 0x01 0x00>;
|
|
hdr_num = <0x01>;
|
|
hdr_type = <0x02 0x00 0x00 0x00>;
|
|
hdr_max_luma = <0x5265c0>;
|
|
hdr_max_avg_luma = <0x124f80>;
|
|
hdr_min_luma = <0x05>;
|
|
phandle = <0x285>;
|
|
};
|
|
|
|
s6e3ha8_ddi {
|
|
id = <0x460091 0x430491 0x870091>;
|
|
mode = <0x02>;
|
|
resolution = <0x5a0 0xb90>;
|
|
size = <0x45 0x8e>;
|
|
timing,refresh = <0x3c>;
|
|
timing,h-porch = <0x02 0x02 0x02>;
|
|
timing,v-porch = <0x0f 0x08 0x01>;
|
|
timing,v-blank-t = <0x78>;
|
|
timing,dsi-hs-clk = <0x382>;
|
|
timing,pmsk = <0x02 0x8a 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
timing,dsi-escape-clk = <0x14>;
|
|
mic_en = <0x00>;
|
|
mic_ratio = <0x02>;
|
|
mic_ver = <0x02>;
|
|
type_of_ddi = <0x00>;
|
|
dsc_en = <0x01>;
|
|
dsc_cnt = <0x02>;
|
|
dsc_slice_num = <0x02>;
|
|
dsc_slice_h = <0x28>;
|
|
data_lane = <0x04>;
|
|
mres_en = <0x01>;
|
|
mres_number = <0x03>;
|
|
mres_width = <0x5a0 0x438 0x2d0>;
|
|
mres_height = <0xb90 0x8ac 0x5c8>;
|
|
mres_dsc_width = <0x2d0 0x21c 0x168>;
|
|
mres_dsc_height = <0x28 0x1e 0x4a>;
|
|
mres_dsc_en = <0x01 0x01 0x01>;
|
|
default_mode = <0x00>;
|
|
display_mode = <0x5a0 0xb90 0x3c 0xbce 0x01 0x2d0 0x28 0x438 0x8ac 0x3c 0x14ef 0x01 0x21c 0x1e 0x2d0 0x5c8 0x3c 0x1b77 0x01 0x168 0x4a>;
|
|
hdr_num = <0x01>;
|
|
hdr_type = <0x02 0x00 0x00 0x00>;
|
|
hdr_max_luma = <0x5265c0>;
|
|
hdr_max_avg_luma = <0x124f80>;
|
|
hdr_min_luma = <0x05>;
|
|
phandle = <0xc5>;
|
|
};
|
|
|
|
s6e3ha9_ddi {
|
|
id = <0x1090 0x1310a1 0x1330a1 0x1300a1>;
|
|
mode = <0x02>;
|
|
resolution = <0x5a0 0xbe0>;
|
|
size = <0x45 0x8e>;
|
|
timing,refresh = <0x3c>;
|
|
timing,h-porch = <0x02 0x02 0x02>;
|
|
timing,v-porch = <0x0f 0x08 0x01>;
|
|
timing,v-blank-t = <0x78>;
|
|
timing,dsi-hs-clk = <0x382>;
|
|
timing,pmsk = <0x02 0x8a 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
timing,dsi-escape-clk = <0x14>;
|
|
mic_en = <0x00>;
|
|
mic_ratio = <0x02>;
|
|
mic_ver = <0x02>;
|
|
type_of_ddi = <0x00>;
|
|
dsc_en = <0x01>;
|
|
dsc_cnt = <0x02>;
|
|
dsc_slice_num = <0x02>;
|
|
dsc_slice_h = <0x28>;
|
|
data_lane = <0x04>;
|
|
mres_en = <0x00>;
|
|
mres_number = <0x03>;
|
|
mres_width = <0x5a0 0x438 0x2d0>;
|
|
mres_height = <0xbe0 0x8e8 0x5f0>;
|
|
mres_dsc_width = <0x2d0 0x21c 0x168>;
|
|
mres_dsc_height = <0x28 0x1e 0x4a>;
|
|
mres_dsc_en = <0x01 0x01 0x01>;
|
|
default_mode = <0x00>;
|
|
display_mode = <0x5a0 0xbe0 0x3c 0xb3d 0x01 0x2d0 0x28>;
|
|
hdr_num = <0x01>;
|
|
hdr_type = <0x02 0x00 0x00 0x00>;
|
|
hdr_max_luma = <0x5265c0>;
|
|
hdr_max_avg_luma = <0x124f80>;
|
|
hdr_min_luma = <0x05>;
|
|
phandle = <0xc4>;
|
|
};
|
|
|
|
s6e3hab_ddi {
|
|
id = <0x1080 0x411080 0x421081 0x31181>;
|
|
mode = <0x02>;
|
|
resolution = <0x5a0 0xc80>;
|
|
size = <0x45 0x9a>;
|
|
timing,refresh = <0x3c>;
|
|
timing,h-porch = <0x02 0x02 0x02>;
|
|
timing,v-porch = <0x0f 0x08 0x01>;
|
|
timing,v-blank-t = <0x78>;
|
|
timing,dsi-hs-clk = <0x382>;
|
|
timing,pmsk = <0x02 0x8a 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
timing,dsi-escape-clk = <0x14>;
|
|
mic_en = <0x00>;
|
|
mic_ratio = <0x02>;
|
|
mic_ver = <0x02>;
|
|
type_of_ddi = <0x00>;
|
|
dsc_en = <0x01>;
|
|
dsc_cnt = <0x02>;
|
|
dsc_slice_num = <0x02>;
|
|
dsc_slice_h = <0x28>;
|
|
data_lane = <0x04>;
|
|
mres_en = <0x01>;
|
|
mres_number = <0x03>;
|
|
mres_width = <0x5a0 0x438 0x2d0>;
|
|
mres_height = <0xc80 0x960 0x640>;
|
|
mres_dsc_width = <0x2d0 0x21c 0x168>;
|
|
mres_dsc_height = <0x28 0x28 0x50>;
|
|
mres_dsc_en = <0x01 0x01 0x01>;
|
|
default_mode = <0x00>;
|
|
display_mode = <0x5a0 0xc80 0x3c 0xbce 0x01 0x2d0 0x28 0x438 0x960 0x3c 0x13fb 0x01 0x21c 0x28 0x438 0x960 0x78 0x294 0x01 0x21c 0x28 0x2d0 0x640 0x3c 0x1b0a 0x01 0x168 0x50 0x2d0 0x640 0x78 0x9a3 0x01 0x168 0x50>;
|
|
hdr_num = <0x01>;
|
|
hdr_type = <0x02 0x00 0x00 0x00>;
|
|
hdr_max_luma = <0x5265c0>;
|
|
hdr_max_avg_luma = <0x124f80>;
|
|
hdr_min_luma = <0x05>;
|
|
phandle = <0xc1>;
|
|
};
|
|
|
|
s6e3fa0_fhd {
|
|
id = <0x244040>;
|
|
mode = <0x02>;
|
|
resolution = <0x438 0x780>;
|
|
size = <0x46 0x79>;
|
|
timing,refresh = <0x3c>;
|
|
timing,h-porch = <0x02 0x02 0x02>;
|
|
timing,v-porch = <0x0a 0x03 0x01>;
|
|
timing,dsi-hs-clk = <0x44c>;
|
|
timing,pmsk = <0x03 0xfe 0x02 0x00>;
|
|
timing,dsi-escape-clk = <0x14>;
|
|
mic_en = <0x00>;
|
|
mic_ratio = <0x02>;
|
|
mic_ver = <0x00>;
|
|
type_of_ddi = <0x00>;
|
|
dsc_en = <0x00>;
|
|
dsc_cnt = <0x00>;
|
|
dsc_slice_num = <0x00>;
|
|
dsc_slice_h = <0x28>;
|
|
data_lane = <0x04>;
|
|
mres_en = <0x00>;
|
|
mres_number = <0x01>;
|
|
mres_width = <0x438 0x00 0x00>;
|
|
mres_height = <0x780 0x00 0x00>;
|
|
mres_dsc_width = <0x00 0x00 0x00>;
|
|
mres_dsc_height = <0x00 0x00 0x00>;
|
|
mres_dsc_en = <0x00 0x00 0x00>;
|
|
default_mode = <0x00>;
|
|
display_mode = <0x438 0x780 0x3c 0x9a3 0x00 0x00 0x00>;
|
|
hdr_num = <0x01>;
|
|
hdr_type = <0x02 0x00 0x00 0x00>;
|
|
hdr_max_luma = <0x5265c0>;
|
|
hdr_max_avg_luma = <0x124f80>;
|
|
hdr_min_luma = <0x05>;
|
|
phandle = <0x286>;
|
|
};
|
|
|
|
s6e3fa0_fhd_vid {
|
|
id = <0x244040>;
|
|
mode = <0x00>;
|
|
resolution = <0x438 0x780>;
|
|
size = <0x50 0x78>;
|
|
timing,refresh = <0x3c>;
|
|
timing,h-porch = <0x14 0x14 0x14>;
|
|
timing,v-porch = <0x02 0x14 0x02>;
|
|
timing,dsi-hs-clk = <0x44c>;
|
|
timing,pmsk = <0x04 0x2a5 0x02 0x00>;
|
|
timing,dsi-escape-clk = <0x14>;
|
|
mic_en = <0x00>;
|
|
mic_ratio = <0x00>;
|
|
mic_ver = <0x00>;
|
|
type_of_ddi = <0x00>;
|
|
dsc_en = <0x00>;
|
|
dsc_cnt = <0x00>;
|
|
dsc_slice_num = <0x00>;
|
|
data_lane = <0x04>;
|
|
cmd_underrun_cnt = <0x134e>;
|
|
vt_compensation = <0x27>;
|
|
mres_en = <0x00>;
|
|
mres_number = <0x03>;
|
|
mres_width = <0x5a0 0x438 0x2d0>;
|
|
mres_height = <0xb90 0x8ac 0x5c8>;
|
|
mres_dsc_width = <0x2d0 0x21c 0x168>;
|
|
mres_dsc_height = <0x28 0x1e 0x4a>;
|
|
mres_dsc_en = <0x01 0x01 0x00>;
|
|
hdr_num = <0x01>;
|
|
hdr_type = <0x02 0x00 0x00 0x00>;
|
|
hdr_max_luma = <0x5265c0>;
|
|
hdr_max_avg_luma = <0x124f80>;
|
|
hdr_min_luma = <0x05>;
|
|
phandle = <0x287>;
|
|
};
|
|
|
|
s6e3fab_ddi {
|
|
id = <0x1581 0x315a0 0x115a0 0x115a1>;
|
|
mode = <0x02>;
|
|
resolution = <0x438 0x960>;
|
|
size = <0x46 0x9b>;
|
|
timing,refresh = <0x3c>;
|
|
timing,h-porch = <0x01 0x01 0x01>;
|
|
timing,v-porch = <0x01 0x0f 0x01>;
|
|
timing,v-blank-t = <0x78>;
|
|
timing,dsi-hs-clk = <0x552>;
|
|
timing,pmsk = <0x02 0x69 0x00 0xc4ec 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
timing,dsi-escape-clk = <0x14>;
|
|
mic_en = <0x00>;
|
|
mic_ratio = <0x02>;
|
|
mic_ver = <0x02>;
|
|
type_of_ddi = <0x00>;
|
|
dsc_en = <0x01>;
|
|
dsc_cnt = <0x02>;
|
|
dsc_slice_num = <0x02>;
|
|
dsc_slice_h = <0x78>;
|
|
data_lane = <0x04>;
|
|
mres_en = <0x01>;
|
|
mres_number = <0x03>;
|
|
mres_width = <0x5a0 0x438 0x2d0>;
|
|
mres_height = <0xc80 0x960 0x640>;
|
|
mres_dsc_width = <0x2d0 0x21c 0x168>;
|
|
mres_dsc_height = <0x28 0x28 0x50>;
|
|
mres_dsc_en = <0x01 0x01 0x01>;
|
|
default_mode = <0x00>;
|
|
display_mode = <0x438 0x960 0x3c 0x2879 0x01 0x21c 0x78 0x438 0x960 0x78 0xd09 0x01 0x21c 0x78>;
|
|
hdr_num = <0x01>;
|
|
hdr_type = <0x02 0x00 0x00 0x00>;
|
|
hdr_max_luma = <0x5265c0>;
|
|
hdr_max_avg_luma = <0x124f80>;
|
|
hdr_min_luma = <0x05>;
|
|
phandle = <0xc2>;
|
|
};
|
|
|
|
s6e3had_ddi {
|
|
id = <0xe12680 0xe22690 0xe32690 0xe32691>;
|
|
mode = <0x02>;
|
|
resolution = <0x5a0 0xc80>;
|
|
size = <0x46 0x79>;
|
|
timing,refresh = <0x3c>;
|
|
timing,h-porch = <0x01 0x01 0x01>;
|
|
timing,v-porch = <0x0f 0x01 0x01>;
|
|
timing,v-blank-t = <0x78>;
|
|
timing,dsi-hs-clk = <0x552>;
|
|
timing,pmsk = <0x02 0x69 0x00 0xc4ec 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
timing,dsi-escape-clk = <0x14>;
|
|
mic_en = <0x00>;
|
|
mic_ratio = <0x02>;
|
|
mic_ver = <0x02>;
|
|
type_of_ddi = <0x00>;
|
|
dsc_en = <0x01>;
|
|
dsc_cnt = <0x02>;
|
|
dsc_slice_num = <0x02>;
|
|
dsc_slice_h = <0x28>;
|
|
data_lane = <0x04>;
|
|
mres_en = <0x01>;
|
|
mres_number = <0x03>;
|
|
mres_width = <0x5a0 0x438 0x2d0>;
|
|
mres_height = <0xc80 0x960 0x640>;
|
|
mres_dsc_width = <0x2d0 0x21c 0x168>;
|
|
mres_dsc_height = <0x28 0x28 0x50>;
|
|
mres_dsc_en = <0x01 0x01 0x01>;
|
|
default_mode = <0x00>;
|
|
display_mode = <0x5a0 0xc80 0x3c 0x1e9a 0x01 0x2d0 0x28 0x5a0 0xc80 0x78 0x32a 0x01 0x2d0 0x28 0x438 0x960 0x3c 0x2879 0x01 0x21c 0x28 0x438 0x960 0x78 0xd09 0x01 0x21c 0x28 0x2d0 0x640 0x3c 0x2f88 0x01 0x168 0x50 0x2d0 0x640 0x78 0x1418 0x01 0x168 0x50>;
|
|
hdr_num = <0x01>;
|
|
hdr_type = <0x02 0x00 0x00 0x00>;
|
|
hdr_max_luma = <0x5265c0>;
|
|
hdr_max_avg_luma = <0x124f80>;
|
|
hdr_min_luma = <0x05>;
|
|
phandle = <0xc3>;
|
|
};
|
|
};
|
|
};
|
|
|
|
dpp@0x19CB0000 {
|
|
compatible = "samsung,exynos9-dpp";
|
|
#pb-id-cells = <0x03>;
|
|
reg = <0x00 0x19cb0000 0x1000 0x00 0x19cd0000 0x1000 0x00 0x19cb0000 0x110 0x00 0x19ca0000 0x500>;
|
|
interrupts = <0x00 0x11c 0x04 0x00 0x125 0x04>;
|
|
attr = <0x50004>;
|
|
port = <0x00>;
|
|
src_f_w = <0x20 0xfffe 0x01>;
|
|
src_f_h = <0x10 0x1ffe 0x01>;
|
|
src_w = <0x20 0x1000 0x01>;
|
|
src_h = <0x10 0x10e0 0x01>;
|
|
src_xy_align = <0x01 0x01>;
|
|
dst_f_w = <0x20 0x1ffe 0x01>;
|
|
dst_f_h = <0x10 0x1ffe 0x01>;
|
|
dst_w = <0x20 0x1000 0x01>;
|
|
dst_h = <0x10 0x10e0 0x01>;
|
|
dst_xy_align = <0x01 0x01>;
|
|
blk_w = <0x04 0x1000 0x01>;
|
|
blk_h = <0x01 0x10e0 0x01>;
|
|
blk_xy_align = <0x01 0x01>;
|
|
src_w_rot_max = <0x2000>;
|
|
src_h_rot_max = <0x874>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
fmt_cnt = <0x06>;
|
|
fmt = <0x0d 0x0e 0x0f 0x10 0x11 0x12>;
|
|
phandle = <0x288>;
|
|
};
|
|
|
|
dpp@0x19CB1000 {
|
|
compatible = "samsung,exynos9-dpp";
|
|
#pb-id-cells = <0x03>;
|
|
reg = <0x00 0x19cb1000 0x1000 0x00 0x19cd1000 0x1000>;
|
|
interrupts = <0x00 0x11d 0x04 0x00 0x126 0x04>;
|
|
attr = <0x5043d>;
|
|
port = <0x00>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
fmt_cnt = <0x23>;
|
|
fmt = <0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x16 0x17 0x18 0x19 0x1e 0x1f 0x20 0x21 0x24 0x25 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38>;
|
|
phandle = <0x289>;
|
|
};
|
|
|
|
dpp@0x19CB2000 {
|
|
compatible = "samsung,exynos9-dpp";
|
|
#pb-id-cells = <0x03>;
|
|
reg = <0x00 0x19cb2000 0x1000 0x00 0x19cd2000 0x1000>;
|
|
interrupts = <0x00 0x11e 0x04 0x00 0x127 0x04>;
|
|
attr = <0x50005>;
|
|
port = <0x00>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
fmt_cnt = <0x06>;
|
|
fmt = <0x0d 0x0e 0x0f 0x10 0x11 0x12>;
|
|
phandle = <0x28a>;
|
|
};
|
|
|
|
dpp@0x19CB3000 {
|
|
compatible = "samsung,exynos9-dpp";
|
|
#pb-id-cells = <0x03>;
|
|
reg = <0x00 0x19cb3000 0x1000 0x00 0x19cd3000 0x1000>;
|
|
interrupts = <0x00 0x11f 0x04 0x00 0x128 0x04>;
|
|
attr = <0x50434>;
|
|
port = <0x00>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
fmt_cnt = <0x23>;
|
|
fmt = <0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x16 0x17 0x18 0x19 0x1e 0x1f 0x20 0x21 0x24 0x25 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38>;
|
|
lib_reserved;
|
|
phandle = <0x28b>;
|
|
};
|
|
|
|
dpp@0x19CB4000 {
|
|
compatible = "samsung,exynos9-dpp";
|
|
#pb-id-cells = <0x03>;
|
|
reg = <0x00 0x19cb4000 0x1000 0x00 0x19cd4000 0x1000>;
|
|
interrupts = <0x00 0x120 0x04 0x00 0x129 0x04>;
|
|
attr = <0x50005>;
|
|
port = <0x01>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
fmt_cnt = <0x06>;
|
|
fmt = <0x0d 0x0e 0x0f 0x10 0x11 0x12>;
|
|
phandle = <0x28c>;
|
|
};
|
|
|
|
dpp@0x19CB5000 {
|
|
compatible = "samsung,exynos9-dpp";
|
|
#pb-id-cells = <0x03>;
|
|
reg = <0x00 0x19cb5000 0x1000 0x00 0x19cd5000 0x1000>;
|
|
interrupts = <0x00 0x121 0x04 0x00 0x12a 0x04>;
|
|
attr = <0x50014>;
|
|
port = <0x01>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
fmt_cnt = <0x13>;
|
|
fmt = <0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x16 0x17 0x18 0x19 0x1e 0x1f 0x20 0x21 0x24 0x25 0x28>;
|
|
phandle = <0x28d>;
|
|
};
|
|
|
|
dpp@0x19CB6000 {
|
|
compatible = "samsung,exynos9-dpp";
|
|
#pb-id-cells = <0x03>;
|
|
reg = <0x00 0x19cb6000 0x1000 0x00 0x19cd6000 0x1000>;
|
|
interrupts = <0x00 0x122 0x04 0x00 0x12b 0x04>;
|
|
attr = <0x50004>;
|
|
port = <0x01>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
fmt_cnt = <0x06>;
|
|
fmt = <0x0d 0x0e 0x0f 0x10 0x11 0x12>;
|
|
phandle = <0x28e>;
|
|
};
|
|
|
|
dpp@0x19CB7000 {
|
|
compatible = "samsung,exynos9-dpp";
|
|
#pb-id-cells = <0x03>;
|
|
reg = <0x00 0x19cb7000 0x1000 0x00 0x19cd7000 0x1000>;
|
|
interrupts = <0x00 0x123 0x04 0x00 0x12c 0x04>;
|
|
attr = <0x50435>;
|
|
port = <0x01>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
fmt_cnt = <0x23>;
|
|
fmt = <0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x16 0x17 0x18 0x19 0x1e 0x1f 0x20 0x21 0x24 0x25 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38>;
|
|
phandle = <0x28f>;
|
|
};
|
|
|
|
dpp@0x1AEB1000 {
|
|
compatible = "samsung,exynos9-dpp";
|
|
#pb-id-cells = <0x03>;
|
|
reg = <0x00 0x1aeb0000 0x1000 0x00 0x1aed0000 0x1000 0x00 0x1aea0000 0x500>;
|
|
interrupts = <0x00 0x134 0x04 0x00 0x13d 0x04>;
|
|
attr = <0x50004>;
|
|
port = <0x02>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
fmt_cnt = <0x06>;
|
|
fmt = <0x0d 0x0e 0x0f 0x10 0x11 0x12>;
|
|
phandle = <0x290>;
|
|
};
|
|
|
|
dpp@0x1AEB2000 {
|
|
compatible = "samsung,exynos9-dpp";
|
|
#pb-id-cells = <0x03>;
|
|
reg = <0x00 0x1aeb1000 0x1000 0x00 0x1aed1000 0x1000>;
|
|
interrupts = <0x00 0x135 0x04 0x00 0x13e 0x04>;
|
|
attr = <0x5043d>;
|
|
port = <0x02>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
fmt_cnt = <0x23>;
|
|
fmt = <0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x16 0x17 0x18 0x19 0x1e 0x1f 0x20 0x21 0x24 0x25 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38>;
|
|
phandle = <0x291>;
|
|
};
|
|
|
|
dpp@0x1AEB3000 {
|
|
compatible = "samsung,exynos9-dpp";
|
|
#pb-id-cells = <0x03>;
|
|
reg = <0x00 0x1aeb2000 0x1000 0x00 0x1aed2000 0x1000>;
|
|
interrupts = <0x00 0x136 0x04 0x00 0x13f 0x04>;
|
|
attr = <0x50005>;
|
|
port = <0x02>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
fmt_cnt = <0x06>;
|
|
fmt = <0x0d 0x0e 0x0f 0x10 0x11 0x12>;
|
|
phandle = <0x292>;
|
|
};
|
|
|
|
dpp@0x1AEB4000 {
|
|
compatible = "samsung,exynos9-dpp";
|
|
#pb-id-cells = <0x03>;
|
|
reg = <0x00 0x1aeb3000 0x1000 0x00 0x1aed3000 0x1000>;
|
|
interrupts = <0x00 0x137 0x04 0x00 0x140 0x04>;
|
|
attr = <0x50434>;
|
|
port = <0x02>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
fmt_cnt = <0x23>;
|
|
fmt = <0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x16 0x17 0x18 0x19 0x1e 0x1f 0x20 0x21 0x24 0x25 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38>;
|
|
lib_reserved;
|
|
phandle = <0x293>;
|
|
};
|
|
|
|
dpp@0x1AEB5000 {
|
|
compatible = "samsung,exynos9-dpp";
|
|
#pb-id-cells = <0x03>;
|
|
reg = <0x00 0x1aeb4000 0x1000 0x00 0x1aed4000 0x1000>;
|
|
interrupts = <0x00 0x138 0x04 0x00 0x141 0x04>;
|
|
attr = <0x50005>;
|
|
port = <0x03>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
fmt_cnt = <0x06>;
|
|
fmt = <0x0d 0x0e 0x0f 0x10 0x11 0x12>;
|
|
phandle = <0x294>;
|
|
};
|
|
|
|
dpp@0x1AEB6000 {
|
|
compatible = "samsung,exynos9-dpp";
|
|
#pb-id-cells = <0x03>;
|
|
reg = <0x00 0x1aeb5000 0x1000 0x00 0x1aed5000 0x1000>;
|
|
interrupts = <0x00 0x139 0x04 0x00 0x142 0x04>;
|
|
attr = <0x50014>;
|
|
port = <0x03>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
fmt_cnt = <0x13>;
|
|
fmt = <0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x16 0x17 0x18 0x19 0x1e 0x1f 0x20 0x21 0x24 0x25 0x28>;
|
|
phandle = <0x295>;
|
|
};
|
|
|
|
dpp@0x1AEB7000 {
|
|
compatible = "samsung,exynos9-dpp";
|
|
#pb-id-cells = <0x03>;
|
|
reg = <0x00 0x1aeb6000 0x1000 0x00 0x1aed6000 0x1000>;
|
|
interrupts = <0x00 0x13a 0x04 0x00 0x143 0x04>;
|
|
attr = <0x50004>;
|
|
port = <0x03>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
fmt_cnt = <0x06>;
|
|
fmt = <0x0d 0x0e 0x0f 0x10 0x11 0x12>;
|
|
phandle = <0x296>;
|
|
};
|
|
|
|
dpp@0x1AEB8000 {
|
|
compatible = "samsung,exynos9-dpp";
|
|
#pb-id-cells = <0x03>;
|
|
reg = <0x00 0x1aeb7000 0x1000 0x00 0x1aed7000 0x1000>;
|
|
interrupts = <0x00 0x13b 0x04 0x00 0x144 0x04>;
|
|
attr = <0x50435>;
|
|
port = <0x03>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
fmt_cnt = <0x23>;
|
|
fmt = <0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x16 0x17 0x18 0x19 0x1e 0x1f 0x20 0x21 0x24 0x25 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38>;
|
|
phandle = <0x297>;
|
|
};
|
|
|
|
dpp@0x19CBC000 {
|
|
compatible = "samsung,exynos9-dpp";
|
|
#pb-id-cells = <0x03>;
|
|
reg = <0x00 0x19cba000 0x1000 0x00 0x19cda000 0x1000>;
|
|
interrupts = <0x00 0x124 0x04>;
|
|
attr = <0xe0010>;
|
|
port = <0x01>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
fmt_cnt = <0x11>;
|
|
fmt = <0x0f 0x10 0x11 0x12 0x13 0x14 0x16 0x17 0x18 0x19 0x1e 0x1f 0x20 0x21 0x24 0x25 0x28>;
|
|
iommus = <0xba 0xbb 0xbc 0xbd>;
|
|
samsung,iommu-group = <0xbe>;
|
|
samsung,tzmp;
|
|
clock-names = "aclk";
|
|
clocks = <0x04 0x2bd>;
|
|
phandle = <0x298>;
|
|
};
|
|
|
|
fcmd@0x19CBC000 {
|
|
compatible = "samsung,exynos9-fcmd";
|
|
reg = <0x00 0x19cbc000 0x1000>;
|
|
interrupts = <0x00 0x109 0x04>;
|
|
port = <0x00>;
|
|
phandle = <0x299>;
|
|
};
|
|
|
|
fcmd@0x19CBD000 {
|
|
compatible = "samsung,exynos9-fcmd";
|
|
reg = <0x00 0x19cbd000 0x1000>;
|
|
interrupts = <0x00 0x10a 0x04>;
|
|
port = <0x01>;
|
|
phandle = <0x29a>;
|
|
};
|
|
|
|
fcmd@0x1AEBC000 {
|
|
compatible = "samsung,exynos9-fcmd";
|
|
reg = <0x00 0x1aebc000 0x1000>;
|
|
interrupts = <0x00 0x10b 0x04>;
|
|
port = <0x02>;
|
|
phandle = <0x29b>;
|
|
};
|
|
|
|
disp_ss@0x19E20000 {
|
|
compatible = "samsung,exynos9-disp_ss";
|
|
reg = <0x00 0x19e21000 0x10>;
|
|
reg-names = "sys";
|
|
phandle = <0x29c>;
|
|
};
|
|
|
|
dphy_m4m4_dsim0@0x15860000 {
|
|
compatible = "samsung,mipi-phy-m4m4-top";
|
|
samsung,pmu-syscon = <0xbf>;
|
|
isolation = <0x714>;
|
|
owner = <0x00>;
|
|
#phy-cells = <0x01>;
|
|
phandle = <0xc0>;
|
|
};
|
|
|
|
dsim@0x19EC0000 {
|
|
compatible = "samsung,exynos9-dsim";
|
|
reg = <0x00 0x19ec0000 0x300 0x00 0x19ee0100 0x700 0x00 0x19ee0000 0x100 0x00 0x189e0000 0x10000>;
|
|
interrupts = <0x00 0x101 0x04>;
|
|
iommus = <0xba 0xbb 0xbc 0xbd>;
|
|
samsung,iommu-group = <0xbe>;
|
|
samsung,tzmp;
|
|
clock-names = "aclk";
|
|
clocks = <0x04 0x2bd>;
|
|
phys = <0xc0 0x00>;
|
|
phy-names = "dsim_dphy";
|
|
phandle = <0x14a>;
|
|
};
|
|
|
|
panel_0 {
|
|
compatible = "samsung,exynos-panel";
|
|
ddi_id = <0x01>;
|
|
lcd_info = <0xc1 0xc2 0xc3 0xc4 0xc5>;
|
|
phandle = <0x29d>;
|
|
};
|
|
|
|
displayport@0x10AB0000 {
|
|
compatible = "samsung,exynos-displayport";
|
|
reg = <0x00 0x10ab0000 0x6da8 0x00 0x10ae0000 0x263c>;
|
|
interrupts = <0x00 0x159 0x04>;
|
|
iommus = <0xba 0xbb 0xbc 0xbd>;
|
|
samsung,iommu-group = <0xbe>;
|
|
samsung,tzmp;
|
|
clock-names = "aclk";
|
|
clocks = <0x04 0x2bd>;
|
|
phandle = <0x29e>;
|
|
};
|
|
|
|
decon_0@0x19F00000 {
|
|
compatible = "samsung,exynos9-decon";
|
|
#pb-id-cells = <0x04>;
|
|
reg = <0x00 0x19f00000 0xffff 0x00 0x19f10000 0xffff 0x00 0x19f20000 0xffff 0x00 0x19f30000 0xffff 0x00 0x19f70000 0xffff>;
|
|
interrupts = <0x00 0xfa 0x04 0x00 0xf9 0x04 0x00 0xf8 0x04 0x00 0x216 0x04>;
|
|
pinctrl-names = "hw_te_on\0hw_te_off";
|
|
pinctrl-0 = <0xc6>;
|
|
pinctrl-1 = <0xc7>;
|
|
max_win = <0x10>;
|
|
default_win = <0x0d>;
|
|
default_ch = <0x01>;
|
|
psr_mode = <0x02>;
|
|
trig_mode = <0x00>;
|
|
dsi_mode = <0x00>;
|
|
out_type = <0x00>;
|
|
out_idx = <0x00>;
|
|
ppc = <0x02>;
|
|
ppc_rotator = <0x08>;
|
|
ppc_scaler = <0x04>;
|
|
delay_comp = <0x04>;
|
|
delay_scaler = <0x03>;
|
|
inner_width = <0x10>;
|
|
bus_width = <0x20>;
|
|
bus_util = <0x46>;
|
|
rot_util = <0x3c>;
|
|
bw_weight = <0x64>;
|
|
dfs_lv_cnt = <0x08>;
|
|
dfs_lv = <0xa1dd8 0x82208 0x72420 0x61a80 0x510e0 0x412f8 0x1c908 0xc350>;
|
|
chip_ver = <0x834>;
|
|
dpp_cnt = <0x11>;
|
|
dsim_cnt = <0x01>;
|
|
decon_cnt = <0x04>;
|
|
cursor_margin = <0x05>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
gpios = <0xc8 0x04 0x0f>;
|
|
phandle = <0x29f>;
|
|
|
|
te_eint {
|
|
reg = <0x00 0x10730a1c 0x04>;
|
|
};
|
|
};
|
|
|
|
decon_1@0x19F01000 {
|
|
compatible = "samsung,exynos9-decon";
|
|
#pb-id-cells = <0x04>;
|
|
reg = <0x00 0x19f01000 0xffff 0x00 0x19f10000 0xffff 0x00 0x19f20000 0xffff 0x00 0x19f40000 0xffff>;
|
|
interrupts = <0x00 0xfd 0x04 0x00 0xfc 0x04 0x00 0xfb 0x04>;
|
|
max_win = <0x10>;
|
|
default_win = <0x03>;
|
|
default_ch = <0x00>;
|
|
psr_mode = <0x00>;
|
|
trig_mode = <0x00>;
|
|
dsi_mode = <0x00>;
|
|
out_type = <0x03>;
|
|
out_idx = <0x00>;
|
|
ppc = <0x02>;
|
|
ppc_rotator = <0x08>;
|
|
ppc_scaler = <0x04>;
|
|
delay_comp = <0x04>;
|
|
delay_scaler = <0x03>;
|
|
inner_width = <0x10>;
|
|
bus_width = <0x20>;
|
|
bus_util = <0x46>;
|
|
rot_util = <0x3c>;
|
|
bw_weight = <0x64>;
|
|
dfs_lv_cnt = <0x08>;
|
|
dfs_lv = <0xa1dd8 0x82208 0x72420 0x61a80 0x510e0 0x412f8 0x1c908 0xc350>;
|
|
chip_ver = <0x834>;
|
|
dpp_cnt = <0x11>;
|
|
dsim_cnt = <0x01>;
|
|
decon_cnt = <0x04>;
|
|
cursor_margin = <0x28>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
phandle = <0x2a0>;
|
|
};
|
|
|
|
decon_2@0x19F02000 {
|
|
compatible = "samsung,exynos9-decon";
|
|
#pb-id-cells = <0x04>;
|
|
reg = <0x00 0x19f02000 0xffff 0x00 0x19f10000 0xffff 0x00 0x19f20000 0xffff 0x00 0x19f50000 0xffff>;
|
|
interrupts = <0x00 0x100 0x04 0x00 0xff 0x04 0x00 0xfe 0x04>;
|
|
max_win = <0x10>;
|
|
default_win = <0x04>;
|
|
default_ch = <0x02>;
|
|
psr_mode = <0x00>;
|
|
trig_mode = <0x00>;
|
|
dsi_mode = <0x00>;
|
|
out_type = <0x03>;
|
|
out_idx = <0x00>;
|
|
ppc = <0x02>;
|
|
ppc_rotator = <0x08>;
|
|
ppc_scaler = <0x04>;
|
|
delay_comp = <0x04>;
|
|
delay_scaler = <0x03>;
|
|
inner_width = <0x10>;
|
|
bus_width = <0x20>;
|
|
bus_util = <0x46>;
|
|
rot_util = <0x3c>;
|
|
bw_weight = <0x64>;
|
|
dfs_lv_cnt = <0x08>;
|
|
dfs_lv = <0xa1dd8 0x82208 0x72420 0x61a80 0x510e0 0x412f8 0x1c908 0xc350>;
|
|
chip_ver = <0x834>;
|
|
dpp_cnt = <0x11>;
|
|
dsim_cnt = <0x01>;
|
|
decon_cnt = <0x04>;
|
|
cursor_margin = <0x28>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
phandle = <0x2a1>;
|
|
};
|
|
|
|
decon_3@0x19F03000 {
|
|
compatible = "samsung,exynos9-decon";
|
|
#pb-id-cells = <0x04>;
|
|
reg = <0x00 0x19f03000 0xffff 0x00 0x19f10000 0xffff 0x00 0x19f20000 0xffff 0x00 0x19f60000 0xffff>;
|
|
interrupts = <0x00 0x107 0x04 0x00 0x106 0x04 0x00 0x105 0x04>;
|
|
max_win = <0x10>;
|
|
default_win = <0x05>;
|
|
default_ch = <0x03>;
|
|
psr_mode = <0x00>;
|
|
trig_mode = <0x00>;
|
|
dsi_mode = <0x00>;
|
|
out_type = <0x03>;
|
|
out_idx = <0x00>;
|
|
ppc = <0x02>;
|
|
ppc_rotator = <0x08>;
|
|
ppc_scaler = <0x04>;
|
|
delay_comp = <0x04>;
|
|
delay_scaler = <0x03>;
|
|
inner_width = <0x10>;
|
|
bus_width = <0x20>;
|
|
bus_util = <0x46>;
|
|
rot_util = <0x3c>;
|
|
bw_weight = <0x64>;
|
|
dfs_lv_cnt = <0x08>;
|
|
dfs_lv = <0xa1dd8 0x82208 0x72420 0x61a80 0x510e0 0x412f8 0x1c908 0xc350>;
|
|
chip_ver = <0x834>;
|
|
dpp_cnt = <0x11>;
|
|
dsim_cnt = <0x01>;
|
|
decon_cnt = <0x04>;
|
|
cursor_margin = <0x28>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
phandle = <0x2a2>;
|
|
};
|
|
|
|
dsim_modes {
|
|
phandle = <0xc9>;
|
|
|
|
dsim-modes {
|
|
|
|
1440x3200@60 {
|
|
mode-name = "1440x3200";
|
|
pmsk = <0x02 0x8a 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
hs-clk = <0x382>;
|
|
esc-clk = <0x14>;
|
|
cmd_underrun_cnt = <0xbce>;
|
|
};
|
|
|
|
1080x2400@60 {
|
|
mode-name = "1080x2400";
|
|
pmsk = <0x02 0x8a 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
hs-clk = <0x382>;
|
|
esc-clk = <0x14>;
|
|
cmd_underrun_cnt = <0x13fb>;
|
|
};
|
|
|
|
1080x2400@120 {
|
|
mode-name = "1080x2400";
|
|
pmsk = <0x02 0x8a 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
hs-clk = <0x382>;
|
|
esc-clk = <0x14>;
|
|
cmd_underrun_cnt = <0x294>;
|
|
};
|
|
|
|
720x1600@60 {
|
|
mode-name = "720x1600";
|
|
pmsk = <0x02 0x8a 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
hs-clk = <0x382>;
|
|
esc-clk = <0x14>;
|
|
cmd_underrun_cnt = <0x1b0a>;
|
|
};
|
|
|
|
720x1600@120 {
|
|
mode-name = "720x1600";
|
|
pmsk = <0x02 0x8a 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
hs-clk = <0x382>;
|
|
esc-clk = <0x14>;
|
|
cmd_underrun_cnt = <0x9a3>;
|
|
};
|
|
};
|
|
};
|
|
|
|
drmdpp@0x19CB0000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x19cb0000 0x1000 0x00 0x19cd0000 0x1000 0x00 0x19ca0000 0x500>;
|
|
reg-names = "dma\0dpp\0votf";
|
|
interrupts = <0x00 0x11c 0x04 0x00 0x125 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x50004>;
|
|
port = <0x00>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
dpp,id = <0x00>;
|
|
phandle = <0xca>;
|
|
};
|
|
|
|
drmdpp@0x19CB1000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x19cb1000 0x1000 0x00 0x19cd1000 0x1000>;
|
|
reg-names = "dma\0dpp";
|
|
interrupts = <0x00 0x11d 0x04 0x00 0x126 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x5043d>;
|
|
port = <0x00>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
dpp,id = <0x01>;
|
|
dpp,video;
|
|
phandle = <0xcb>;
|
|
};
|
|
|
|
drmdpp@0x19CB2000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x19cb2000 0x1000 0x00 0x19cd2000 0x1000>;
|
|
reg-names = "dma\0dpp";
|
|
interrupts = <0x00 0x11e 0x04 0x00 0x127 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x50005>;
|
|
port = <0x00>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
dpp,id = <0x02>;
|
|
phandle = <0xcc>;
|
|
};
|
|
|
|
drmdpp@0x19CB3000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x19cb3000 0x1000 0x00 0x19cd3000 0x1000>;
|
|
reg-names = "dma\0dpp";
|
|
interrupts = <0x00 0x11f 0x04 0x00 0x128 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x50434>;
|
|
port = <0x00>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
dpp,id = <0x03>;
|
|
dpp,video;
|
|
phandle = <0xcd>;
|
|
};
|
|
|
|
drmdpp@0x19CB4000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x19cb4000 0x1000 0x00 0x19cd4000 0x1000>;
|
|
reg-names = "dma\0dpp";
|
|
interrupts = <0x00 0x120 0x04 0x00 0x129 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x50005>;
|
|
port = <0x01>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
dpp,id = <0x04>;
|
|
phandle = <0xce>;
|
|
};
|
|
|
|
drmdpp@0x19CB5000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x19cb5000 0x1000 0x00 0x19cd5000 0x1000>;
|
|
reg-names = "dma\0dpp";
|
|
interrupts = <0x00 0x121 0x04 0x00 0x12a 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x50014>;
|
|
port = <0x01>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
dpp,id = <0x05>;
|
|
dpp,video;
|
|
phandle = <0xcf>;
|
|
};
|
|
|
|
drmdpp@0x19CB6000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x19cb6000 0x1000 0x00 0x19cd6000 0x1000>;
|
|
reg-names = "dma\0dpp";
|
|
interrupts = <0x00 0x122 0x04 0x00 0x12b 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x50004>;
|
|
port = <0x01>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
dpp,id = <0x06>;
|
|
phandle = <0xd0>;
|
|
};
|
|
|
|
drmdpp@0x19CB7000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x19cb7000 0x1000 0x00 0x19cd7000 0x1000>;
|
|
reg-names = "dma\0dpp";
|
|
interrupts = <0x00 0x123 0x04 0x00 0x12c 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x50435>;
|
|
port = <0x01>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
dpp,id = <0x07>;
|
|
dpp,video;
|
|
phandle = <0xd1>;
|
|
};
|
|
|
|
drmdpp@0x1AEB1000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1aeb0000 0x1000 0x00 0x1aed0000 0x1000 0x00 0x1aea0000 0x500>;
|
|
reg-names = "dma\0dpp\0votf";
|
|
interrupts = <0x00 0x134 0x04 0x00 0x13d 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x50004>;
|
|
port = <0x02>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
dpp,id = <0x08>;
|
|
phandle = <0xd2>;
|
|
};
|
|
|
|
drmdpp@0x1AEB2000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1aeb1000 0x1000 0x00 0x1aed1000 0x1000>;
|
|
reg-names = "dma\0dpp";
|
|
interrupts = <0x00 0x135 0x04 0x00 0x13e 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x5043d>;
|
|
port = <0x02>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
dpp,id = <0x09>;
|
|
dpp,video;
|
|
phandle = <0xd3>;
|
|
};
|
|
|
|
drmdpp@0x1AEB3000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1aeb2000 0x1000 0x00 0x1aed2000 0x1000>;
|
|
reg-names = "dma\0dpp";
|
|
interrupts = <0x00 0x136 0x04 0x00 0x13f 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x50005>;
|
|
port = <0x02>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
dpp,id = <0x0a>;
|
|
phandle = <0xd4>;
|
|
};
|
|
|
|
drmdpp@0x1AEB4000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1aeb3000 0x1000 0x00 0x1aed3000 0x1000>;
|
|
reg-names = "dma\0dpp";
|
|
interrupts = <0x00 0x137 0x04 0x00 0x140 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x50434>;
|
|
port = <0x02>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
dpp,id = <0x0b>;
|
|
dpp,video;
|
|
phandle = <0xd5>;
|
|
};
|
|
|
|
drmdpp@0x1AEB5000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1aeb4000 0x1000 0x00 0x1aed4000 0x1000>;
|
|
reg-names = "dma\0dpp";
|
|
interrupts = <0x00 0x138 0x04 0x00 0x141 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x50005>;
|
|
port = <0x03>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
dpp,id = <0x0c>;
|
|
phandle = <0xd6>;
|
|
};
|
|
|
|
drmdpp@0x1AEB6000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1aeb5000 0x1000 0x00 0x1aed5000 0x1000>;
|
|
reg-names = "dma\0dpp";
|
|
interrupts = <0x00 0x139 0x04 0x00 0x142 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x50014>;
|
|
port = <0x03>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
dpp,id = <0x0d>;
|
|
dpp,video;
|
|
phandle = <0xd7>;
|
|
};
|
|
|
|
drmdpp@0x1AEB7000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1aeb6000 0x1000 0x00 0x1aed6000 0x1000>;
|
|
reg-names = "dma\0dpp";
|
|
interrupts = <0x00 0x13a 0x04 0x00 0x143 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x50004>;
|
|
port = <0x03>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
dpp,id = <0x0e>;
|
|
phandle = <0xd8>;
|
|
};
|
|
|
|
drmdpp@0x1AEB8000 {
|
|
compatible = "samsung,exynos-dpp";
|
|
reg = <0x00 0x1aeb7000 0x1000 0x00 0x1aed7000 0x1000>;
|
|
reg-names = "dma\0dpp";
|
|
interrupts = <0x00 0x13b 0x04 0x00 0x144 0x04>;
|
|
interrupt-names = "dma\0dpp";
|
|
attr = <0x50435>;
|
|
port = <0x03>;
|
|
scale_down = <0x04>;
|
|
scale_up = <0x08>;
|
|
dpp,id = <0x0f>;
|
|
dpp,video;
|
|
phandle = <0xd9>;
|
|
};
|
|
|
|
drmdpp@0x19CBC000 {
|
|
compatible = "samsung,exynos-writeback";
|
|
reg = <0x00 0x19cba000 0x1000 0x00 0x19cda000 0x1000>;
|
|
reg-names = "dma\0dpp";
|
|
interrupts = <0x00 0x124 0x04>;
|
|
interrupt-names = "dma";
|
|
attr = <0x60010>;
|
|
port = <0x01>;
|
|
scale_down = <0x01>;
|
|
scale_up = <0x01>;
|
|
hwfc,enabled;
|
|
dpp,id = <0x10>;
|
|
phandle = <0x2a3>;
|
|
};
|
|
|
|
drmdsim@0x19EC0000 {
|
|
compatible = "samsung,exynos-dsim";
|
|
reg = <0x00 0x19ec0000 0x300 0x00 0x19ee0100 0x700 0x00 0x19ee0000 0x100 0x00 0x189e0000 0x10000>;
|
|
reg-names = "dsi\0dphy\0dphy-extra\0votf";
|
|
dsim,id = <0x00>;
|
|
interrupts = <0x00 0x101 0x04>;
|
|
interrupt-names = "dsim";
|
|
phys = <0xc0 0x00>;
|
|
phy-names = "dsim_dphy";
|
|
dsim_mode = <0xc9>;
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
phandle = <0x2a4>;
|
|
|
|
drmpanel {
|
|
compatible = "samsung,s6e3hab";
|
|
reg = <0x00>;
|
|
phandle = <0x2a5>;
|
|
};
|
|
};
|
|
|
|
drmdp@0x10AB0000 {
|
|
compatible = "samsung,exynos-dp";
|
|
reg = <0x00 0x10ab0000 0x6da8 0x00 0x10ae0000 0x263c>;
|
|
interrupts = <0x00 0x159 0x04>;
|
|
iommus = <0xba 0xbb 0xbc 0xbd>;
|
|
samsung,iommu-group = <0xbe>;
|
|
samsung,tzmp;
|
|
clock-names = "aclk";
|
|
clocks = <0x04 0x2bd>;
|
|
phandle = <0x2a6>;
|
|
};
|
|
|
|
drmdecon@0x19F00000 {
|
|
compatible = "samsung,exynos-decon";
|
|
reg = <0x00 0x19f00000 0xffff 0x00 0x19f10000 0xffff 0x00 0x19f20000 0xffff 0x00 0x19f30000 0xffff 0x00 0x19f70000 0xffff>;
|
|
reg-names = "main\0win\0sub\0wincon\0dqe";
|
|
decon,id = <0x00>;
|
|
interrupts = <0x00 0xfa 0x04 0x00 0xf9 0x04 0x00 0xf8 0x04>;
|
|
interrupt-names = "frame_start\0frame_done\0extra";
|
|
iommus = <0xba 0xbb 0xbc 0xbd>;
|
|
samsung,iommu-group = <0xbe>;
|
|
samsung,tzmp;
|
|
clock-names = "aclk";
|
|
clocks = <0x04 0x2bd>;
|
|
pinctrl-names = "hw_te_on\0hw_te_off";
|
|
pinctrl-0 = <0xc6>;
|
|
pinctrl-1 = <0xc7>;
|
|
max_win = <0x10>;
|
|
op_mode = <0x01>;
|
|
trig_mode = <0x00>;
|
|
out_type = <0x01>;
|
|
te_from = <0x00>;
|
|
ppc = <0x02>;
|
|
line_mem_cnt = <0x04>;
|
|
cycle_per_line = <0x08>;
|
|
rd_en = <0x00>;
|
|
rd_hi_thres = <0x800>;
|
|
rd_lo_thres = <0x400>;
|
|
rd_wait_cycle = <0x10>;
|
|
wr_en = <0x00>;
|
|
wr_hi_thres = <0x00>;
|
|
wr_lo_thres = <0x00>;
|
|
dta_en = <0x00>;
|
|
dta_hi_thres = <0x3200>;
|
|
dta_lo_thres = <0x600>;
|
|
gpios = <0xc8 0x04 0x0f>;
|
|
dpps = <0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9>;
|
|
connector = <0x01 0x02 0x08>;
|
|
hibernation;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
phandle = <0x2a7>;
|
|
|
|
te_eint {
|
|
reg = <0x00 0x10730a1c 0x04>;
|
|
};
|
|
};
|
|
|
|
drmdecon@0x19F01000 {
|
|
compatible = "samsung,exynos-decon";
|
|
reg = <0x00 0x19f01000 0xffff 0x00 0x19f10000 0xffff 0x00 0x19f20000 0xffff 0x00 0x19f40000 0xffff>;
|
|
reg-names = "main\0win\0sub\0wincon";
|
|
decon,id = <0x01>;
|
|
interrupts = <0x00 0xfd 0x04 0x00 0xfc 0x04 0x00 0xfb 0x04>;
|
|
interrupt-names = "frame_start\0frame_done\0extra";
|
|
iommus = <0xba 0xbb 0xbc 0xbd>;
|
|
samsung,iommu-group = <0xbe>;
|
|
samsung,tzmp;
|
|
clock-names = "aclk";
|
|
clocks = <0x04 0x2bd>;
|
|
max_win = <0x10>;
|
|
op_mode = <0x01>;
|
|
trig_mode = <0x01>;
|
|
out_type = <0x100>;
|
|
te_from = <0x00>;
|
|
ppc = <0x02>;
|
|
line_mem_cnt = <0x04>;
|
|
cycle_per_line = <0x08>;
|
|
dpps = <0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9>;
|
|
connector = <0x08>;
|
|
phandle = <0x2a8>;
|
|
};
|
|
|
|
drmdecon@0x19F02000 {
|
|
compatible = "samsung,exynos-decon";
|
|
reg = <0x00 0x19f02000 0xffff 0x00 0x19f10000 0xffff 0x00 0x19f20000 0xffff 0x00 0x19f50000 0xffff>;
|
|
reg-names = "main\0win\0sub\0wincon";
|
|
decon,id = <0x02>;
|
|
interrupts = <0x00 0x100 0x04 0x00 0xff 0x04 0x00 0xfe 0x04>;
|
|
interrupt-names = "frame_start\0frame_done\0extra";
|
|
iommus = <0xba 0xbb 0xbc 0xbd>;
|
|
samsung,iommu-group = <0xbe>;
|
|
samsung,tzmp;
|
|
clock-names = "aclk";
|
|
clocks = <0x04 0x2bd>;
|
|
max_win = <0x10>;
|
|
op_mode = <0x00>;
|
|
trig_mode = <0x00>;
|
|
out_type = <0x10>;
|
|
te_from = <0x00>;
|
|
ppc = <0x02>;
|
|
line_mem_cnt = <0x04>;
|
|
cycle_per_line = <0x08>;
|
|
dpps = <0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9>;
|
|
connector = <0x10>;
|
|
phandle = <0x2a9>;
|
|
};
|
|
|
|
drmdecon@0x19F03000 {
|
|
compatible = "samsung,exynos-decon";
|
|
reg = <0x00 0x19f03000 0xffff 0x00 0x19f10000 0xffff 0x00 0x19f20000 0xffff 0x00 0x19f60000 0xffff>;
|
|
reg-names = "main\0win\0sub\0wincon";
|
|
decon,id = <0x03>;
|
|
interrupts = <0x00 0x107 0x04 0x00 0x106 0x04 0x00 0x105 0x04>;
|
|
interrupt-names = "frame_start\0frame_done\0extra";
|
|
iommus = <0xba 0xbb 0xbc 0xbd>;
|
|
samsung,iommu-group = <0xbe>;
|
|
samsung,tzmp;
|
|
clock-names = "aclk";
|
|
clocks = <0x04 0x2bd>;
|
|
max_win = <0x10>;
|
|
op_mode = <0x00>;
|
|
trig_mode = <0x00>;
|
|
out_type = <0x10>;
|
|
te_from = <0x00>;
|
|
ppc = <0x02>;
|
|
line_mem_cnt = <0x04>;
|
|
cycle_per_line = <0x08>;
|
|
dpps = <0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9>;
|
|
connector = <0x100>;
|
|
phandle = <0x2aa>;
|
|
};
|
|
|
|
dpu_debug {
|
|
compatible = "samsung,dpu-debug";
|
|
devfreq-mif = <0x00>;
|
|
devfreq-int = <0x01>;
|
|
devfreq-disdp = <0x03>;
|
|
};
|
|
|
|
dpm {
|
|
phandle = <0x2ab>;
|
|
};
|
|
|
|
dss {
|
|
compatible = "samsung,debug-snapshot";
|
|
panic_to_wdt = <0x00>;
|
|
freq_names = "LIT\0MID\0BIG\0INT\0MIF\0CAM\0DISP\0INTCAM\0AUD\0DSP\0DNC\0MFC\0NPU\0TNR\0DSU\0VPC\0CSIS\0ISP\0MFC1\0G3D";
|
|
memory-region = <0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2>;
|
|
phandle = <0x2ac>;
|
|
};
|
|
|
|
hardlockup-debugger {
|
|
compatible = "samsung,hardlockup-debug";
|
|
use_multistage_wdt_irq = <0x3ce>;
|
|
};
|
|
|
|
hardlockup-watchdog {
|
|
compatible = "samsung,hardlockup-watchdog";
|
|
};
|
|
|
|
dss-qdump {
|
|
compatible = "debug-snapshot,qdump";
|
|
};
|
|
|
|
dss-sfrdump {
|
|
compatible = "debug-snapshot,sfrdump";
|
|
};
|
|
|
|
exynos-debug-test {
|
|
compatible = "samsung,exynos-debug-test";
|
|
ps_hold_control_offset = <0x30c>;
|
|
nr_cpu = <0x08>;
|
|
nr_little_cpu = <0x04>;
|
|
nr_mid_cpu = <0x03>;
|
|
nr_big_cpu = <0x01>;
|
|
little_cpu_start = <0x00>;
|
|
mid_cpu_start = <0x04>;
|
|
big_cpu_start = <0x07>;
|
|
};
|
|
|
|
exynos-adv_tracer {
|
|
compatible = "samsung,exynos-adv-tracer";
|
|
reg = <0x00 0x158d0000 0x1000>;
|
|
reg-names = "mailbox";
|
|
interrupts = <0x00 0x10 0x04>;
|
|
status = "ok";
|
|
};
|
|
|
|
exynos_adv_tracer_s2d {
|
|
compatible = "samsung,exynos-adv-tracer-s2d";
|
|
plugin-len = <0x03>;
|
|
plugin-name = "S2D";
|
|
pmu-burnin-ctrl = <0xa08>;
|
|
sel-scanmode-bit = <0x19>;
|
|
dbgsel-sw-bit = <0x04>;
|
|
status = "ok";
|
|
phandle = <0x2ad>;
|
|
};
|
|
|
|
exynos-itmon {
|
|
compatible = "samsung,exynos-itmon";
|
|
interrupts = <0x00 0x2c 0x04 0x00 0x2f 0x04 0x00 0x1e 0x04 0x00 0x1f 0x04 0x00 0x8a 0x04 0x00 0x8b 0x04 0x00 0x8c 0x04 0x00 0x20 0x04 0x00 0x2d 0x04 0x00 0x30 0x04>;
|
|
panic_count = <0x05>;
|
|
phandle = <0x2ae>;
|
|
};
|
|
|
|
exynos-ehld {
|
|
compatible = "samsung,exynos-ehld";
|
|
reg = <0x00 0x1d0d0000 0x1000 0x00 0x1d0e0000 0x1000 0x00 0x1d0b0000 0x1000 0x00 0x1d0c0000 0x1000>;
|
|
cs_base = <0x1e000000>;
|
|
|
|
cpu0 {
|
|
dbg-offset = <0x810000>;
|
|
};
|
|
|
|
cpu1 {
|
|
dbg-offset = <0x910000>;
|
|
};
|
|
|
|
cpu2 {
|
|
dbg-offset = <0xa10000>;
|
|
};
|
|
|
|
cpu3 {
|
|
dbg-offset = <0xb10000>;
|
|
};
|
|
|
|
cpu4 {
|
|
dbg-offset = <0xc10000>;
|
|
};
|
|
|
|
cpu5 {
|
|
dbg-offset = <0xd10000>;
|
|
};
|
|
|
|
cpu6 {
|
|
dbg-offset = <0xe10000>;
|
|
};
|
|
|
|
cpu7 {
|
|
dbg-offset = <0xf10000>;
|
|
};
|
|
|
|
dbgc {
|
|
plugin-len = <0x04>;
|
|
plugin-name = "ELD";
|
|
support = <0x01>;
|
|
interval = <0x64>;
|
|
warn-count = <0x05>;
|
|
use-tick-timer = <0x00>;
|
|
phandle = <0x2af>;
|
|
};
|
|
};
|
|
|
|
coresight@1e000000 {
|
|
compatible = "samsung,exynos-coresight";
|
|
dbg_base = <0x1e810000 0x1e910000 0x1ea10000 0x1eb10000 0x1ec10000 0x1ed10000 0x1ee10000 0x1ef10000>;
|
|
cti_base = <0x1e820000 0x1e920000 0x1ea20000 0x1eb20000 0x1ec20000 0x1ed20000 0x1ee20000 0x1ef20000>;
|
|
pmu_base = <0x1e830000 0x1e930000 0x1ea30000 0x1eb30000 0x1ec30000 0x1ed30000 0x1ee30000 0x1ef30000>;
|
|
gpr_base = <0x1e001000>;
|
|
dbgack-mask = <0xff00000>;
|
|
halt = <0x00>;
|
|
retention = <0x00>;
|
|
};
|
|
|
|
exynos-ecc-handler {
|
|
compatible = "samsung,exynos-ecc-handler";
|
|
interrupts = <0x00 0x91 0x04 0x00 0x92 0x04 0x00 0x93 0x04 0x00 0x94 0x04 0x00 0x95 0x04 0x00 0x96 0x04 0x00 0x97 0x04 0x00 0x98 0x04 0x00 0x99 0x04>;
|
|
interrupt-names = "Uncorrectable errors Cache(L3) tag RAMs or SCU snoop filter RAMs\0Core0, Uncorrectable errors in the L1 tag or dirty RAMs, or in the L2 tag RAMs\0Core1, Uncorrectable errors in the L1 tag or dirty RAMs, or in the L2 tag RAMs\0Core2, Uncorrectable errors in the L1 tag or dirty RAMs, or in the L2 tag RAMs\0Core3, Uncorrectable errors in the L1 tag or dirty RAMs, or in the L2 tag RAMs\0Core4, Uncorrectable errors in the L1 tag or dirty RAMs, or in the L2 tag RAMs\0Core5, Uncorrectable errors in the L1 tag or dirty RAMs, or in the L2 tag RAMs\0Core6, Uncorrectable errors in the L1 tag or dirty RAMs, or in the L2 tag RAMs\0Core7, Uncorrectable errors in the L1 tag or dirty RAMs, or in the L2 tag RAMs";
|
|
};
|
|
|
|
etm@1e840000 {
|
|
compatible = "arm,coresight-etm4x\0arm,primecell";
|
|
arm,primecell-periphid = <0xbbd05>;
|
|
reg = <0x00 0x1e840000 0x1000>;
|
|
clocks = <0x04 0x356>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <0x93>;
|
|
phandle = <0x2b0>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0xe3>;
|
|
phandle = <0xf2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@1e940000 {
|
|
compatible = "arm,coresight-etm4x\0arm,primecell";
|
|
arm,primecell-periphid = <0xbbd05>;
|
|
reg = <0x00 0x1e940000 0x1000>;
|
|
clocks = <0x04 0x356>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <0x94>;
|
|
phandle = <0x2b1>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0xe4>;
|
|
phandle = <0xf3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@1ea40000 {
|
|
compatible = "arm,coresight-etm4x\0arm,primecell";
|
|
arm,primecell-periphid = <0xbbd05>;
|
|
reg = <0x00 0x1ea40000 0x1000>;
|
|
clocks = <0x04 0x356>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <0x95>;
|
|
phandle = <0x2b2>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0xe5>;
|
|
phandle = <0xf4>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@1eb40000 {
|
|
compatible = "arm,coresight-etm4x\0arm,primecell";
|
|
arm,primecell-periphid = <0xbbd05>;
|
|
reg = <0x00 0x1eb40000 0x1000>;
|
|
clocks = <0x04 0x356>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <0x96>;
|
|
phandle = <0x2b3>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0xe6>;
|
|
phandle = <0xf5>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@1ec40000 {
|
|
compatible = "arm,coresight-etm4x\0arm,primecell";
|
|
arm,primecell-periphid = <0xbbd41>;
|
|
reg = <0x00 0x1ec40000 0x1000>;
|
|
clocks = <0x04 0x356>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <0x97>;
|
|
is-etm;
|
|
phandle = <0x2b4>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0xe7>;
|
|
phandle = <0xf8>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@1ed40000 {
|
|
compatible = "arm,coresight-etm4x\0arm,primecell";
|
|
arm,primecell-periphid = <0xbbd41>;
|
|
reg = <0x00 0x1ed40000 0x1000>;
|
|
clocks = <0x04 0x356>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <0x98>;
|
|
phandle = <0x2b5>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0xe8>;
|
|
phandle = <0xf9>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@1ee40000 {
|
|
compatible = "arm,coresight-etm4x\0arm,primecell";
|
|
arm,primecell-periphid = <0xbbd41>;
|
|
reg = <0x00 0x1ee40000 0x1000>;
|
|
clocks = <0x04 0x356>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <0x99>;
|
|
phandle = <0x2b6>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0xe9>;
|
|
phandle = <0xfa>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etm@1ef40000 {
|
|
compatible = "arm,coresight-etm4x\0arm,primecell";
|
|
arm,primecell-periphid = <0xbbd44>;
|
|
reg = <0x00 0x1ef40000 0x1000>;
|
|
clocks = <0x04 0x356>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <0x9a>;
|
|
phandle = <0x2b7>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0xea>;
|
|
phandle = <0xf6>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etf0@1e004000 {
|
|
compatible = "arm,coresight-tmc\0arm,primecell";
|
|
arm,primecell-periphid = <0x1bb961>;
|
|
reg = <0x00 0x1e004000 0x1000>;
|
|
clocks = <0x04 0x356>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x2b8>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0xeb>;
|
|
phandle = <0xf1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0xec>;
|
|
phandle = <0xfd>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etf1@1e005000 {
|
|
compatible = "arm,coresight-tmc\0arm,primecell";
|
|
arm,primecell-periphid = <0x1bb961>;
|
|
reg = <0x00 0x1e005000 0x1000>;
|
|
clocks = <0x04 0x356>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x2b9>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0xed>;
|
|
phandle = <0xf7>;
|
|
};
|
|
};
|
|
};
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0xee>;
|
|
phandle = <0xfe>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
etr@1e00a000 {
|
|
compatible = "arm,coresight-tmc\0arm,primecell";
|
|
arm,primecell-periphid = <0x1bb961>;
|
|
reg = <0x00 0x1e00a000 0x1000>;
|
|
clocks = <0x04 0x356>;
|
|
clock-names = "apb_pclk";
|
|
samsung,cs-sfr = <0x1e00c000 0x100>;
|
|
samsung,q-offset = <0x2c>;
|
|
phandle = <0x2ba>;
|
|
|
|
in-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0xef>;
|
|
phandle = <0xfc>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
stm@1e00b000 {
|
|
compatible = "arm,coresight-stm\0arm,primecell";
|
|
arm,primecell-periphid = <0xbb963>;
|
|
reg = <0x00 0x1e00b000 0x1000 0x00 0x1e200000 0x200000>;
|
|
reg-names = "stm-base\0stm-stimulus-base";
|
|
clocks = <0x04 0x356>;
|
|
clock-names = "apb_pclk";
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0xf0>;
|
|
phandle = <0xfb>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel0@1e007000 {
|
|
compatible = "arm,coresight-funnel\0arm,primecell";
|
|
arm,primecell-periphid = <0x1bb908>;
|
|
reg = <0x00 0x1e007000 0x1000>;
|
|
clocks = <0x04 0x356>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x2bb>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0xf1>;
|
|
phandle = <0xeb>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0xf2>;
|
|
phandle = <0xe3>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0xf3>;
|
|
phandle = <0xe4>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0xf4>;
|
|
phandle = <0xe5>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <0x03>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0xf5>;
|
|
phandle = <0xe6>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <0x04>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0xf6>;
|
|
phandle = <0xea>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel1@1e008000 {
|
|
compatible = "arm,coresight-funnel\0arm,primecell";
|
|
arm,primecell-periphid = <0x1bb908>;
|
|
reg = <0x00 0x1e008000 0x1000>;
|
|
clocks = <0x04 0x356>;
|
|
clock-names = "apb_pclk";
|
|
phandle = <0x2bc>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0xf7>;
|
|
phandle = <0xed>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0xf8>;
|
|
phandle = <0xe7>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0xf9>;
|
|
phandle = <0xe8>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <0x02>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0xfa>;
|
|
phandle = <0xe9>;
|
|
};
|
|
};
|
|
|
|
port@7 {
|
|
reg = <0x07>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0xfb>;
|
|
phandle = <0xf0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnelm@1e009000 {
|
|
compatible = "arm,coresight-funnel\0arm,primecell";
|
|
reg = <0x00 0x1e009000 0x1000>;
|
|
clocks = <0x04 0x356>;
|
|
clock-names = "apb_pclk";
|
|
arm,primecell-periphid = <0x1bb908>;
|
|
phandle = <0x2bd>;
|
|
|
|
out-ports {
|
|
|
|
port {
|
|
|
|
endpoint {
|
|
remote-endpoint = <0xfc>;
|
|
phandle = <0xef>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <0x01>;
|
|
#size-cells = <0x00>;
|
|
|
|
port@0 {
|
|
reg = <0x00>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0xfd>;
|
|
phandle = <0xec>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <0x01>;
|
|
|
|
endpoint {
|
|
slave-mode;
|
|
remote-endpoint = <0xfe>;
|
|
phandle = <0xee>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
mali@18500000 {
|
|
compatible = "arm,mali";
|
|
reg = <0x00 0x18500000 0x5000>;
|
|
sysreg_g3d = <0x18420000>;
|
|
interrupts = <0x00 0x153 0x04 0x00 0x154 0x04 0x00 0x152 0x04>;
|
|
interrupt-names = "JOB\0MMU\0GPU";
|
|
g3d_cmu_cal_id = <0xb04000b>;
|
|
system-coherency = <0x00>;
|
|
power-domains = <0xff>;
|
|
g3d_genpd_name = "pd-embedded_g3d";
|
|
#cooling-cells = <0x02>;
|
|
ect-coeff-index = <0x03>;
|
|
governor = "interactive";
|
|
interactive_info = <0x62638 0x5e 0x00>;
|
|
gpu_dvfs_table_size = <0x0a 0x09>;
|
|
gpu_dvfs_table = <0xe7b08 0x4e 0x64 0x05 0x3066a0 0xd1790 0x00 0x00 0x10 0xd1790 0x4e 0x64 0x05 0x3066a0 0xd1790 0x00 0x00 0x10 0xbb418 0x4e 0x62 0x05 0x29a810 0xd1790 0x00 0x00 0x10 0xa50a0 0x4e 0x5f 0x03 0x26ae58 0xd1790 0x00 0x00 0x10 0x8ed28 0x4e 0x5f 0x01 0x22e980 0xd1790 0x00 0x00 0x10 0x789b0 0x4e 0x5f 0x01 0x1ef1e0 0xd1790 0x00 0x00 0x10 0x62638 0x4e 0x5f 0x01 0x1ef1e0 0xd1790 0x00 0x00 0x00 0x4c2c0 0x4e 0x5a 0x01 0x177bb8 0x00 0x00 0x00 0x00 0x35f48 0x4e 0x55 0x01 0xf78f0 0x00 0x00 0x00 0x00 0x1fbd0 0x00 0x55 0x01 0xa50a0 0x00 0x00 0x00 0x00>;
|
|
gpu_cl_pmqos_table_size = <0x09 0x05>;
|
|
gpu_cl_pmqos_table = <0xd1790 0x1ef1e0 0xd1790 0x00 0x00 0xbb418 0x1a2f20 0xd1790 0x00 0x00 0xa50a0 0x177bb8 0xd1790 0x00 0x00 0x8ed28 0x14a140 0xd1790 0x00 0x00 0x789b0 0x14a140 0xd1790 0x00 0x00 0x62638 0xf78f0 0xd1790 0x00 0x00 0x4c2c0 0xf78f0 0x00 0x00 0x00 0x35f48 0xa50a0 0x00 0x00 0x00 0x1fbd0 0x854d0 0x00 0x00 0x00>;
|
|
gpu_pmqos_cpu_cluster_num = <0x03>;
|
|
gpu_pmu_status_reg_offset = <0x2304>;
|
|
gpu_pmu_status_local_pwr_mask = <0x01>;
|
|
gpu_max_clock = <0xe7b08>;
|
|
gpu_max_clock_limit = <0xe7b08>;
|
|
gpu_min_clock = <0x1fbd0>;
|
|
gpu_dvfs_start_clock = <0x35f48>;
|
|
gpu_dvfs_bl_config_clock = <0x35f48>;
|
|
gpu_default_voltage = <0xcf850>;
|
|
gpu_cold_minimum_vol = <0x00>;
|
|
gpu_voltage_offset_margin = <0x927c>;
|
|
gpu_tmu_control = <0x01>;
|
|
gpu_temp_throttling_level_num = <0x06>;
|
|
gpu_temp_throttling = <0xe7b08 0xd1790 0xbb418 0xa50a0 0x8ed28 0x789b0>;
|
|
gpu_power_coeff = <0x271>;
|
|
gpu_dvfs_time_interval = <0x05>;
|
|
gpu_default_wakeup_lock = <0x01>;
|
|
gpu_dynamic_abb = <0x00>;
|
|
gpu_early_clk_gating = <0x00>;
|
|
gpu_dvs = <0x00>;
|
|
gpu_inter_frame_pm = <0x01>;
|
|
gpu_inter_frame_dynamic_util = <0x32>;
|
|
gpu_inter_frame_dynamic_freq = <0xbb418>;
|
|
gpu_perf_gathering = <0x00>;
|
|
gpu_runtime_pm_delay_time = <0x32>;
|
|
gpu_dvfs_polling_time = <0x1e>;
|
|
gpu_weight_table_idx_0 = <0x05>;
|
|
gpu_weight_table_idx_1 = <0x05>;
|
|
gpu_pmqos_int_disable = <0x01>;
|
|
gpu_pmqos_mif_max_clock = <0x3066a0>;
|
|
gpu_pmqos_mif_max_clock_base = <0x9eb10>;
|
|
gpu_cl_dvfs_start_base = <0x35f48>;
|
|
gpu_debug_level = <0x03>;
|
|
gpu_trace_level = <0x08>;
|
|
gpu_mo_min_clock = <0x62638>;
|
|
gpu_boost_gpu_min_lock = <0x00>;
|
|
gpu_boost_egl_min_lock = <0x00>;
|
|
gpu_vk_boost_max_lock = <0x4c2c0>;
|
|
gpu_vk_boost_mif_min_lock = <0xf78f0>;
|
|
gpu_neg_boost_clock = <0x4c2c0>;
|
|
gpu_sustainable_clock = <0x789b0>;
|
|
gpu_bts_support = <0x01>;
|
|
phandle = <0x120>;
|
|
};
|
|
|
|
system_dma_heap {
|
|
compatible = "samsung,dma_heap,system";
|
|
dma_heap,name = "system";
|
|
};
|
|
|
|
video_system_dma_heap {
|
|
compatible = "samsung,dma_heap,system";
|
|
dma_heap,name = "video_system";
|
|
dma_heap,video_aligned;
|
|
};
|
|
|
|
crypto_dma_heap {
|
|
compatible = "samsung,dma_heap,cma";
|
|
memory-region = <0x100>;
|
|
dma_heap,name = "crypto";
|
|
};
|
|
|
|
video_stream_dma_heap {
|
|
compatible = "samsung,dma_heap,cma";
|
|
memory-region = <0x101>;
|
|
dma_heap,name = "vstream";
|
|
dma_heap,video_aligned;
|
|
dma_heap,secure;
|
|
dma_heap,protection_id = <0x03>;
|
|
dma_heap,alignment = <0x10000>;
|
|
};
|
|
|
|
video_frame_dma_heap {
|
|
compatible = "samsung,dma_heap,cma";
|
|
memory-region = <0x102>;
|
|
dma_heap,name = "vframe";
|
|
dma_heap,secure;
|
|
dma_heap,protection_id = <0x05>;
|
|
dma_heap,alignment = <0x10000>;
|
|
};
|
|
|
|
video_scaler_dma_heap {
|
|
compatible = "samsung,dma_heap,cma";
|
|
memory-region = <0x103>;
|
|
dma_heap,name = "vscaler";
|
|
dma_heap,secure;
|
|
dma_heap,protection_id = <0x06>;
|
|
dma_heap,alignment = <0x10000>;
|
|
};
|
|
|
|
gpu_buffer_dma_heap {
|
|
compatible = "samsung,dma_heap,cma";
|
|
memory-region = <0x104>;
|
|
dma_heap,name = "gpu_buffer";
|
|
dma_heap,secure;
|
|
dma_heap,protection_id = <0x09>;
|
|
dma_heap,alignment = <0x10000>;
|
|
};
|
|
|
|
sysreg_hsi0@10A20000 {
|
|
compatible = "samsung,sysreg-hsi0\0syscon";
|
|
reg = <0x00 0x10a20000 0x10000>;
|
|
phandle = <0x106>;
|
|
};
|
|
|
|
exynos-usb-audio-offloading {
|
|
compatible = "exynos-usb-audio-offloading";
|
|
};
|
|
|
|
usb@10B00000 {
|
|
compatible = "samsung,exynos-dwusb";
|
|
clocks = <0x04 0x3f5 0x04 0x3e9 0x04 0x1ce>;
|
|
clock-names = "aclk\0sclk\0bus";
|
|
reg = <0x00 0x10b00000 0x10000>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
status = "disabled";
|
|
power-domains = <0x105>;
|
|
samsung,sysreg-hsi0 = <0x106>;
|
|
interrupts = <0x00 0x160 0x04>;
|
|
tx-fifo-resize = <0x00>;
|
|
exynos,adj-sof-accuracy = <0x01>;
|
|
exynos,usb_host_device_timeout = <0xc8>;
|
|
exynos,enable_sprs_transfer = <0x01>;
|
|
phys = <0x107 0x00 0x107 0x01>;
|
|
phy-names = "usb2-phy\0usb3-phy";
|
|
xhci_l2_support = <0x01>;
|
|
usb_audio_offloading = <0x01>;
|
|
ldos = <0x03>;
|
|
ldo_number = <0x0a 0x0b 0x0c>;
|
|
phandle = <0x108>;
|
|
|
|
dwc3 {
|
|
compatible = "synopsys,dwc3";
|
|
clocks = <0x04 0x3f5 0x04 0x3e9 0x04 0x1ce>;
|
|
clock-names = "aclk\0sclk\0bus";
|
|
reg = <0x00 0x10b00000 0x10000>;
|
|
interrupts = <0x00 0x160 0x04>;
|
|
dr_mode = "peripheral";
|
|
phys = <0x107 0x00 0x107 0x01>;
|
|
phy-names = "usb2-phy\0usb3-phy";
|
|
xhci_l2_support = <0x01>;
|
|
usb_audio_offloading = <0x01>;
|
|
phandle = <0x2be>;
|
|
};
|
|
};
|
|
|
|
phy@10C00000 {
|
|
compatible = "samsung,exynos-usbdrd-phy";
|
|
reg = <0x00 0x10c00000 0x200 0x00 0x10ae0000 0x2800 0x00 0x10af0000 0x800 0x00 0x10b00000 0x10000>;
|
|
interrupts = <0x00 0x15d 0x04 0x00 0x15b 0x04>;
|
|
clocks = <0x04 0x01 0x04 0x3f5>;
|
|
clock-names = "ext_xtal\0aclk";
|
|
samsung,pmu-syscon = <0xbf>;
|
|
power-domains = <0x105>;
|
|
pmu_mask = <0x00>;
|
|
pmu_offset = <0x72c>;
|
|
pmu_offset_dp = <0x730>;
|
|
phy_version = <0x301>;
|
|
phyclk_mux = "none";
|
|
phy_refclk = "ext_xtal";
|
|
has_other_phy = <0x00>;
|
|
has_combo_phy = <0x01>;
|
|
sub_phy_version = <0x400>;
|
|
ip_type = <0x00>;
|
|
phy_refsel_clockcore = <0x01>;
|
|
phy_refsel_ext_osc = <0x00>;
|
|
phy_refsel_xtal = <0x00>;
|
|
phy_refsel_diff_pad = <0x00>;
|
|
phy_refsel_diff_internal = <0x00>;
|
|
phy_refsel_diff_single = <0x00>;
|
|
use_io_for_ovc = <0x00>;
|
|
common_block_disable = <0x01>;
|
|
is_not_vbus_pad = <0x01>;
|
|
used_phy_port = <0x00>;
|
|
status = "disabled";
|
|
#phy-cells = <0x01>;
|
|
ranges;
|
|
phandle = <0x107>;
|
|
};
|
|
|
|
usb_notifier {
|
|
compatible = "samsung,usb-notifier";
|
|
udc = <0x108>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie@113B0000 {
|
|
compatible = "samsung,exynos-pcie";
|
|
gpios = <0x109 0x01 0x01>;
|
|
reg = <0x00 0x113b0000 0x1000 0x00 0x113e0000 0x1000 0x00 0x11021044 0x10 0x00 0x113f0000 0x1000 0x00 0x113d0000 0x1fc 0x00 0x20ffe000 0x2000 0x00 0x11390000 0x1000>;
|
|
reg-names = "elbi\0phy\0sysreg\0dbi\0pcs\0config\0ia";
|
|
interrupts = <0x00 0x165 0x04>;
|
|
#interrupt-cells = <0x01>;
|
|
interrupt-map-mask = <0x00 0x00 0x00 0x00>;
|
|
interrupt-map = <0x00 0x00 0x00 0x00 0x01 0x00 0x165 0x04>;
|
|
samsung,syscon-phandle = <0xbf>;
|
|
clocks = <0x04 0x41f 0x04 0x420 0x04 0x421 0x04 0x422 0x04 0x423 0x04 0x424>;
|
|
clock-names = "bus\0pcie";
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <0x10a 0x10b>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x02>;
|
|
device_type = "pci";
|
|
ranges = <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0xff0000>;
|
|
ip-ver = <0x984000>;
|
|
ep-ver = <0x4375>;
|
|
num-lanes = <0x01>;
|
|
ch-num = <0x00>;
|
|
pcie-clk-num = <0x00>;
|
|
phy-clk-num = <0x00>;
|
|
pcie-pm-qos-int = <0x412f8>;
|
|
use-cache-coherency = "false";
|
|
use-msi = "false";
|
|
use-sicd = "true";
|
|
use-sysmmu = "false";
|
|
use-ia = "true";
|
|
pmu-offset = <0x71c>;
|
|
use-nclkoff-en = "false";
|
|
max-link-speed = <0x01>;
|
|
status = "disabled";
|
|
phandle = <0x2bf>;
|
|
};
|
|
|
|
pcie@11320000 {
|
|
compatible = "samsung,exynos-pcie-rc";
|
|
gpios = <0x109 0x03 0x01>;
|
|
reg = <0x00 0x11320000 0x2000 0x00 0x11350000 0x2000 0x00 0x11021054 0x10 0x00 0x11400000 0x301000 0x00 0x11340000 0x1000 0x00 0x40ffe000 0x2000 0x00 0x11300000 0x1000>;
|
|
reg-names = "elbi\0phy\0sysreg\0dbi\0pcs\0config\0ia";
|
|
interrupts = <0x00 0x166 0x04>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <0x01>;
|
|
samsung,syscon-phandle = <0xbf>;
|
|
clocks = <0x04 0x425 0x04 0x426 0x04 0x427 0x04 0x428 0x04 0x429 0x04 0x42a>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <0x10c 0x10d>;
|
|
#address-cells = <0x03>;
|
|
#size-cells = <0x02>;
|
|
device_type = "pci";
|
|
ranges = <0x82000000 0x00 0x40000000 0x00 0x40000000 0x00 0xff0000>;
|
|
ip-ver = <0x984000>;
|
|
num-lanes = <0x02>;
|
|
ch-num = <0x01>;
|
|
pcie-clk-num = <0x00>;
|
|
phy-clk-num = <0x00>;
|
|
pcie-pm-qos-int = <0x412f8>;
|
|
use-cache-coherency = "true";
|
|
use-pcieon-sleep = "true";
|
|
use-msi = "false";
|
|
use-sicd = "true";
|
|
use-sysmmu = "false";
|
|
use-ia = "false";
|
|
pmu-offset = <0x720>;
|
|
max-link-speed = <0x03>;
|
|
status = "disabled";
|
|
phandle = <0x2c0>;
|
|
};
|
|
|
|
acpm {
|
|
compatible = "samsung,exynos-acpm";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
acpm-ipc-channel = <0x04>;
|
|
fvmap_offset = <0xf800>;
|
|
reg = <0x00 0x15830000 0x1000>;
|
|
reg-names = "timer_apm";
|
|
peritimer-cnt = <0xffff>;
|
|
};
|
|
|
|
acpm_ipc {
|
|
compatible = "samsung,exynos-acpm-ipc";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
interrupts = <0x00 0x0a 0x04>;
|
|
reg = <0x00 0x15900000 0x1000 0x00 0x2039000 0x41000>;
|
|
initdata-base = <0x8000>;
|
|
num-timestamps = <0x20>;
|
|
debug-log-level = <0x00>;
|
|
logging-period = <0x1f4>;
|
|
dump-base = <0x203d000>;
|
|
dump-size = <0x3d000>;
|
|
dram-dump-base = <0x90014000>;
|
|
board-id = <0x10>;
|
|
board-rev = <0x00>;
|
|
};
|
|
|
|
acpm_mfd_bus@15960000 {
|
|
compatible = "samsung,exynos-acpm-mfd-bus";
|
|
status = "okay";
|
|
phandle = <0x2c1>;
|
|
};
|
|
|
|
acpm_mfd_bus@15961000 {
|
|
compatible = "samsung,exynos-acpm-mfd-bus";
|
|
status = "okay";
|
|
phandle = <0x2c2>;
|
|
};
|
|
|
|
exynos-dm@17000000 {
|
|
compatible = "samsung,exynos-dvfs-manager";
|
|
reg = <0x00 0x17000000 0x00>;
|
|
acpm-ipc-channel = <0x01>;
|
|
phandle = <0x2c3>;
|
|
|
|
dm_domains {
|
|
|
|
cpufreq_cl0 {
|
|
dm-index = <0x00>;
|
|
available = "true";
|
|
cal_id = <0xb040002>;
|
|
dm_type_name = "dm_cpu_cl0";
|
|
};
|
|
|
|
cpufreq_cl1 {
|
|
dm-index = <0x01>;
|
|
available = "true";
|
|
cal_id = <0xb040003>;
|
|
dm_type_name = "dm_cpu_cl1";
|
|
};
|
|
|
|
cpufreq_cl2 {
|
|
dm-index = <0x02>;
|
|
available = "true";
|
|
cal_id = <0xb040004>;
|
|
dm_type_name = "dm_cpu_cl2";
|
|
};
|
|
|
|
devfreq_mif {
|
|
dm-index = <0x03>;
|
|
available = "true";
|
|
policy_use = "true";
|
|
cal_id = <0xb040000>;
|
|
dm_type_name = "dm_mif";
|
|
};
|
|
|
|
devfreq_int {
|
|
dm-index = <0x04>;
|
|
available = "true";
|
|
policy_use = "true";
|
|
cal_id = <0xb040001>;
|
|
dm_type_name = "dm_int";
|
|
};
|
|
|
|
devfreq_npu {
|
|
dm-index = <0x05>;
|
|
available = "true";
|
|
cal_id = <0xb040005>;
|
|
dm_type_name = "dm_npu";
|
|
};
|
|
|
|
devfreq_disp {
|
|
dm-index = <0x07>;
|
|
available = "true";
|
|
cal_id = <0xb040007>;
|
|
dm_type_name = "dm_disp";
|
|
};
|
|
|
|
devfreq_aud {
|
|
dm-index = <0x08>;
|
|
available = "true";
|
|
cal_id = <0xb040008>;
|
|
dm_type_name = "dm_aud";
|
|
};
|
|
|
|
devfreq_GPU {
|
|
dm-index = <0x09>;
|
|
available = "false";
|
|
cal_id = <0xb04000b>;
|
|
dm_type_name = "dm_gpu";
|
|
};
|
|
|
|
devfreq_intcam {
|
|
dm-index = <0x0a>;
|
|
available = "true";
|
|
cal_id = <0xb04000c>;
|
|
dm_type_name = "dm_intcam";
|
|
};
|
|
|
|
devfreq_cam {
|
|
dm-index = <0x0b>;
|
|
available = "true";
|
|
cal_id = <0xb04000d>;
|
|
dm_type_name = "dm_cam";
|
|
};
|
|
|
|
devfreq_vpc {
|
|
dm-index = <0x0d>;
|
|
available = "true";
|
|
cal_id = <0xb040010>;
|
|
dm_type_name = "dm_vpc";
|
|
};
|
|
|
|
devfreq_dsu {
|
|
dm-index = <0x06>;
|
|
available = "true";
|
|
cal_id = <0xb040006>;
|
|
dm_type_name = "dm_dsu";
|
|
};
|
|
|
|
devfreq_mfc {
|
|
dm-index = <0x0e>;
|
|
available = "true";
|
|
cal_id = <0xb040011>;
|
|
dm_type_name = "dm_mfc";
|
|
};
|
|
|
|
devfreq_csis {
|
|
dm-index = <0x0c>;
|
|
available = "true";
|
|
cal_id = <0xb04000e>;
|
|
dm_type_name = "dm_csis";
|
|
};
|
|
|
|
devfreq_isp {
|
|
dm-index = <0x0f>;
|
|
available = "true";
|
|
cal_id = <0xb04000f>;
|
|
dm_type_name = "dm_isp";
|
|
};
|
|
|
|
devfreq_mfc1 {
|
|
dm-index = <0x10>;
|
|
available = "true";
|
|
cal_id = <0xb040012>;
|
|
dm_type_name = "dm_mfc1";
|
|
};
|
|
};
|
|
};
|
|
|
|
exynos_devfreq {
|
|
compatible = "samsung,exynos-devfreq-root";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
|
|
devfreq_mif@17000010 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000010 0x00>;
|
|
devfreq_type = <0x00>;
|
|
devfreq_domain_name = "MIF";
|
|
pm_qos_class = <0x0e>;
|
|
pm_qos_class_max = <0x0f>;
|
|
ess_flag = <0x04>;
|
|
dm-index = <0x03>;
|
|
clocks = <0x04 0x640>;
|
|
clock-names = "DEVFREQ";
|
|
use_delay_time = "false";
|
|
freq_info = <0x3066a0 0x66c88 0x66c88 0x66c88 0x3066a0 0xf78f0>;
|
|
boot_info = <0x28 0x3066a0>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040000>;
|
|
acpm-ipc-channel = <0x01>;
|
|
use_acpm = "true";
|
|
use_migov = "true";
|
|
use_get_dev = "true";
|
|
um_count = <0x06>;
|
|
um_list = <0x1a100000 0x1a110000 0x1a120000 0x1a130000 0x1a140000 0x1a150000>;
|
|
use_alt_dvfs;
|
|
polling_ms = <0x00>;
|
|
phandle = <0x173>;
|
|
|
|
alt_mode {
|
|
default_mode = <0x00>;
|
|
|
|
mode_0 {
|
|
mode_id = <0x00>;
|
|
target_load = "60 676000:84 845000:90 1014000:95 1352000:97 2028000:99";
|
|
min_sample_time = <0x32>;
|
|
hold_sample_time = <0x64>;
|
|
hispeed_load = <0x62>;
|
|
hispeed_freq = <0xf78f0>;
|
|
};
|
|
|
|
mode_1 {
|
|
mode_id = <0x01>;
|
|
target_load = "3 3172000:3";
|
|
min_sample_time = <0x32>;
|
|
hold_sample_time = <0x64>;
|
|
hispeed_load = <0x03>;
|
|
hispeed_freq = <0x3066a0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
devfreq_int@17000020 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000020 0x00>;
|
|
devfreq_type = <0x01>;
|
|
devfreq_domain_name = "INT";
|
|
pm_qos_class = <0x0a>;
|
|
pm_qos_class_max = <0x0c>;
|
|
ess_flag = <0x03>;
|
|
dm-index = <0x04>;
|
|
use_delay_time = "false";
|
|
freq_info = <0xc3500 0x20788 0x13880 0x13880 0xc3500 0x61a80>;
|
|
boot_info = <0x28 0xc3500>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040001>;
|
|
acpm-ipc-channel = <0x01>;
|
|
use_acpm = "true";
|
|
phandle = <0x2c4>;
|
|
};
|
|
|
|
devfreq_intcam@17000030 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000030 0x00>;
|
|
devfreq_type = <0x02>;
|
|
devfreq_domain_name = "INTCAM";
|
|
pm_qos_class = <0x0b>;
|
|
pm_qos_class_max = <0x0d>;
|
|
ess_flag = <0x07>;
|
|
dm-index = <0x0a>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x975e0 0x975e0 0x975e0 0x975e0 0xa8750 0x975e0>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb04000c>;
|
|
phandle = <0x2c5>;
|
|
};
|
|
|
|
devfreq_disp@17000040 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000040 0x00>;
|
|
devfreq_type = <0x03>;
|
|
devfreq_domain_name = "DISP";
|
|
pm_qos_class = <0x10>;
|
|
pm_qos_class_max = <0x11>;
|
|
ess_flag = <0x06>;
|
|
dm-index = <0x07>;
|
|
use_delay_time = "false";
|
|
freq_info = <0xa1dd8 0xc350 0xc350 0xc350 0xa1dd8 0x82208>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040007>;
|
|
phandle = <0x2c6>;
|
|
};
|
|
|
|
devfreq_cam@17000050 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000050 0x00>;
|
|
devfreq_type = <0x04>;
|
|
devfreq_domain_name = "CAM";
|
|
pm_qos_class = <0x12>;
|
|
pm_qos_class_max = <0x14>;
|
|
ess_flag = <0x05>;
|
|
dm-index = <0x0b>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x975e0 0x975e0 0x975e0 0x975e0 0xa8750 0x975e0>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb04000d>;
|
|
phandle = <0x2c7>;
|
|
};
|
|
|
|
devfreq_npu@17000060 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000060 0x00>;
|
|
devfreq_type = <0x05>;
|
|
devfreq_domain_name = "NPU";
|
|
pm_qos_class = <0x17>;
|
|
pm_qos_class_max = <0x19>;
|
|
ess_flag = <0x0c>;
|
|
dm-index = <0x05>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x186a0 0x186a0 0x186a0 0x186a0 0x14a140 0x186a0>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040005>;
|
|
use_dtm = "true";
|
|
#cooling-cells = <0x02>;
|
|
tz-cooling-name = "NPU";
|
|
phandle = <0x12d>;
|
|
|
|
skew {
|
|
|
|
skew_0 {
|
|
master_dm_name = "NPU";
|
|
constraint_dm_type = <0x03>;
|
|
constraint_type = <0x00>;
|
|
};
|
|
|
|
skew_1 {
|
|
master_dm_name = "NPU-INT";
|
|
constraint_dm_type = <0x04>;
|
|
constraint_type = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
devfreq_aud@17000070 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000070 0x00>;
|
|
devfreq_type = <0x06>;
|
|
devfreq_domain_name = "AUD";
|
|
pm_qos_class = <0x13>;
|
|
pm_qos_class_max = <0x15>;
|
|
ess_flag = <0x08>;
|
|
dm-index = <0x08>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x24220 0x24220 0x182b8 0x182b8 0x120160 0x24220>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040008>;
|
|
pd_name = "pd-aud";
|
|
phandle = <0x2c8>;
|
|
};
|
|
|
|
devfreq_vpc@17000080 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000080 0x00>;
|
|
devfreq_type = <0x07>;
|
|
devfreq_domain_name = "VPC";
|
|
pm_qos_class = <0x1c>;
|
|
pm_qos_class_max = <0x1d>;
|
|
ess_flag = <0x0f>;
|
|
dm-index = <0x0d>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x186a0 0x186a0 0x186a0 0x186a0 0x14a140 0x186a0>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040010>;
|
|
phandle = <0x2c9>;
|
|
|
|
skew {
|
|
|
|
skew_0 {
|
|
master_dm_name = "VPC";
|
|
constraint_dm_type = <0x03>;
|
|
constraint_type = <0x00>;
|
|
};
|
|
|
|
skew_1 {
|
|
master_dm_name = "VPC-INT";
|
|
constraint_dm_type = <0x04>;
|
|
constraint_type = <0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
devfreq_mfc@17000090 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x17000090 0x00>;
|
|
devfreq_type = <0x08>;
|
|
devfreq_domain_name = "MFC0";
|
|
pm_qos_class = <0x16>;
|
|
pm_qos_class_max = <0x18>;
|
|
ess_flag = <0x0b>;
|
|
dm-index = <0x0e>;
|
|
use_delay_time = "false";
|
|
freq_info = <0xc350 0xc350 0xc350 0xc350 0xae8f8 0xc350>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040011>;
|
|
phandle = <0x2ca>;
|
|
};
|
|
|
|
devfreq_csis@170000A0 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x170000a0 0x00>;
|
|
devfreq_type = <0x09>;
|
|
devfreq_domain_name = "CSIS";
|
|
pm_qos_class = <0x1e>;
|
|
pm_qos_class_max = <0x1f>;
|
|
ess_flag = <0x10>;
|
|
dm-index = <0x0c>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x975e0 0x975e0 0x975e0 0x975e0 0xa8750 0x975e0>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb04000e>;
|
|
phandle = <0x2cb>;
|
|
};
|
|
|
|
devfreq_isp@170000B0 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x170000b0 0x00>;
|
|
devfreq_type = <0x0a>;
|
|
devfreq_domain_name = "ISP";
|
|
pm_qos_class = <0x20>;
|
|
pm_qos_class_max = <0x21>;
|
|
ess_flag = <0x11>;
|
|
dm-index = <0x0f>;
|
|
use_delay_time = "false";
|
|
freq_info = <0x975e0 0x975e0 0x975e0 0x975e0 0xa8750 0x975e0>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb04000f>;
|
|
phandle = <0x2cc>;
|
|
};
|
|
|
|
devfreq_mfc1@170000C0 {
|
|
compatible = "samsung,exynos-devfreq";
|
|
reg = <0x00 0x170000c0 0x00>;
|
|
devfreq_type = <0x0b>;
|
|
devfreq_domain_name = "MFC1";
|
|
pm_qos_class = <0x22>;
|
|
pm_qos_class_max = <0x23>;
|
|
ess_flag = <0x12>;
|
|
dm-index = <0x10>;
|
|
use_delay_time = "false";
|
|
freq_info = <0xc350 0xc350 0xc350 0xc350 0xae8f8 0xc350>;
|
|
governor = <0x00>;
|
|
dfs_id = <0xb040012>;
|
|
phandle = <0x2cd>;
|
|
};
|
|
};
|
|
|
|
BIG@10090000 {
|
|
compatible = "samsung,exynos-tmu-v2";
|
|
reg = <0x00 0x10090000 0x800>;
|
|
interrupts = <0x00 0x3bb 0x04>;
|
|
tmu_name = "BIG";
|
|
id = <0x00>;
|
|
hotplug_enable = <0x01>;
|
|
hotplug_in_threshold = <0x5b>;
|
|
hotplug_out_threshold = <0x60>;
|
|
cpu_domain = "7";
|
|
#thermal-sensor-cells = <0x00>;
|
|
use-pi-thermal;
|
|
polling_delay_on = <0x32>;
|
|
polling_delay_off = <0x3e8>;
|
|
k_po = <0x00>;
|
|
k_pu = <0x00>;
|
|
k_i = <0x00>;
|
|
i_max = <0x00>;
|
|
integral_cutoff = <0x00>;
|
|
sustainable_power = <0x00>;
|
|
phandle = <0x10e>;
|
|
};
|
|
|
|
MID@10090000 {
|
|
compatible = "samsung,exynos-tmu-v2";
|
|
reg = <0x00 0x10090000 0x800>;
|
|
interrupts = <0x00 0x3bb 0x04>;
|
|
tmu_name = "MID";
|
|
hotplug_enable = <0x01>;
|
|
hotplug_in_threshold = <0x5b>;
|
|
hotplug_out_threshold = <0x60>;
|
|
cpu_domain = "4-6";
|
|
id = <0x01>;
|
|
#thermal-sensor-cells = <0x00>;
|
|
use-pi-thermal;
|
|
polling_delay_on = <0x32>;
|
|
polling_delay_off = <0x3e8>;
|
|
k_po = <0x00>;
|
|
k_pu = <0x00>;
|
|
k_i = <0x00>;
|
|
i_max = <0x00>;
|
|
integral_cutoff = <0x00>;
|
|
sustainable_power = <0x00>;
|
|
phandle = <0x111>;
|
|
};
|
|
|
|
LITTLE@10090000 {
|
|
compatible = "samsung,exynos-tmu-v2";
|
|
reg = <0x00 0x10090000 0x800>;
|
|
interrupts = <0x00 0x3bb 0x04>;
|
|
tmu_name = "LITTLE";
|
|
id = <0x02>;
|
|
#thermal-sensor-cells = <0x00>;
|
|
phandle = <0x114>;
|
|
};
|
|
|
|
G3D@100A0000 {
|
|
compatible = "samsung,exynos-tmu-v2";
|
|
reg = <0x00 0x100a0000 0x800>;
|
|
interrupts = <0x00 0x3bc 0x04>;
|
|
tmu_name = "G3D";
|
|
id = <0x03>;
|
|
#thermal-sensor-cells = <0x00>;
|
|
use-pi-thermal;
|
|
polling_delay_on = <0x64>;
|
|
polling_delay_off = <0x3e8>;
|
|
k_po = <0x00>;
|
|
k_pu = <0x00>;
|
|
k_i = <0x00>;
|
|
i_max = <0x00>;
|
|
integral_cutoff = <0x00>;
|
|
sustainable_power = <0x00>;
|
|
phandle = <0x11e>;
|
|
};
|
|
|
|
ISP@100A0000 {
|
|
compatible = "samsung,exynos-tmu-v2";
|
|
reg = <0x00 0x10090000 0x800>;
|
|
interrupts = <0x00 0x3bb 0x04>;
|
|
tmu_name = "ISP";
|
|
id = <0x04>;
|
|
#thermal-sensor-cells = <0x00>;
|
|
phandle = <0x121>;
|
|
};
|
|
|
|
NPU@100A0000 {
|
|
compatible = "samsung,exynos-tmu-v2";
|
|
reg = <0x00 0x100a0000 0x800>;
|
|
interrupts = <0x00 0x3bc 0x04>;
|
|
tmu_name = "NPU";
|
|
id = <0x05>;
|
|
#thermal-sensor-cells = <0x00>;
|
|
phandle = <0x12b>;
|
|
};
|
|
|
|
CP@10080000 {
|
|
compatible = "samsung,exynos-tmu-v2";
|
|
reg = <0x00 0x100b0000 0x800>;
|
|
interrupts = <0x00 0x3bc 0x04>;
|
|
tmu_name = "CP";
|
|
id = <0x06>;
|
|
#thermal-sensor-cells = <0x00>;
|
|
phandle = <0x135>;
|
|
};
|
|
|
|
acpm_tmu {
|
|
acpm-ipc-channel = <0x09>;
|
|
};
|
|
|
|
exynos_isp_thermal {
|
|
#cooling-cells = <0x02>;
|
|
phandle = <0x123>;
|
|
};
|
|
|
|
thermal-zones {
|
|
|
|
BIG {
|
|
zone_name = "BIG_THERMAL";
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x10e>;
|
|
phandle = <0x2ce>;
|
|
|
|
trips {
|
|
|
|
big-cold {
|
|
temperature = <0x4e20>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x2cf>;
|
|
};
|
|
|
|
big-switch-on {
|
|
temperature = <0xea60>;
|
|
hysteresis = <0x7d0>;
|
|
type = "active";
|
|
phandle = <0x2d0>;
|
|
};
|
|
|
|
big-control-temp {
|
|
temperature = <0x11170>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x10f>;
|
|
};
|
|
|
|
big-alert0 {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x2d1>;
|
|
};
|
|
|
|
big-alert1 {
|
|
temperature = <0x186a0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x2d2>;
|
|
};
|
|
|
|
big-alert2 {
|
|
temperature = <0x19a28>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x2d3>;
|
|
};
|
|
|
|
big-alert3 {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x2d4>;
|
|
};
|
|
|
|
big-hot {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "hot";
|
|
phandle = <0x2d5>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x10f>;
|
|
cooling-device = <0x110 0x00 0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
MID {
|
|
zone_name = "MID_THERMAL";
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x111>;
|
|
phandle = <0x2d6>;
|
|
|
|
trips {
|
|
|
|
mid-cold {
|
|
temperature = <0x4e20>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x2d7>;
|
|
};
|
|
|
|
mid-switch-on {
|
|
temperature = <0xea60>;
|
|
hysteresis = <0x7d0>;
|
|
type = "active";
|
|
phandle = <0x2d8>;
|
|
};
|
|
|
|
mid-control-temp {
|
|
temperature = <0x11170>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x112>;
|
|
};
|
|
|
|
mid-alert0 {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x2d9>;
|
|
};
|
|
|
|
mid-alert1 {
|
|
temperature = <0x186a0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x2da>;
|
|
};
|
|
|
|
mid-alert2 {
|
|
temperature = <0x19a28>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x2db>;
|
|
};
|
|
|
|
mid-alert3 {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x2dc>;
|
|
};
|
|
|
|
mid-hot {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "hot";
|
|
phandle = <0x2dd>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x112>;
|
|
cooling-device = <0x113 0x00 0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
LITTLE {
|
|
zone_name = "LITTLE_THERMAL";
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x114>;
|
|
phandle = <0x2de>;
|
|
|
|
trips {
|
|
|
|
little-alert0 {
|
|
temperature = <0x4e20>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x115>;
|
|
};
|
|
|
|
little-alert1 {
|
|
temperature = <0x128e0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x117>;
|
|
};
|
|
|
|
little-alert2 {
|
|
temperature = <0x13c68>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x118>;
|
|
};
|
|
|
|
little-alert3 {
|
|
temperature = <0x14ff0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x119>;
|
|
};
|
|
|
|
little-alert4 {
|
|
temperature = <0x16378>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x11a>;
|
|
};
|
|
|
|
little-alert5 {
|
|
temperature = <0x17700>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x11b>;
|
|
};
|
|
|
|
little-alert6 {
|
|
temperature = <0x18a88>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x11c>;
|
|
};
|
|
|
|
little-hot {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "hot";
|
|
phandle = <0x11d>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x115>;
|
|
cooling-device = <0x116 0x00 0x00>;
|
|
};
|
|
|
|
map1 {
|
|
trip = <0x117>;
|
|
cooling-device = <0x116 0x00 0x00>;
|
|
};
|
|
|
|
map2 {
|
|
trip = <0x118>;
|
|
cooling-device = <0x116 0x00 0x00>;
|
|
};
|
|
|
|
map3 {
|
|
trip = <0x119>;
|
|
cooling-device = <0x116 0x00 0x00>;
|
|
};
|
|
|
|
map4 {
|
|
trip = <0x11a>;
|
|
cooling-device = <0x116 0x00 0x00>;
|
|
};
|
|
|
|
map5 {
|
|
trip = <0x11b>;
|
|
cooling-device = <0x116 0x00 0x00>;
|
|
};
|
|
|
|
map6 {
|
|
trip = <0x11c>;
|
|
cooling-device = <0x116 0x00 0x00>;
|
|
};
|
|
|
|
map7 {
|
|
trip = <0x11d>;
|
|
cooling-device = <0x116 0x00 0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
G3D {
|
|
zone_name = "G3D_THERMAL";
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x11e>;
|
|
phandle = <0x2df>;
|
|
|
|
trips {
|
|
|
|
gpu-cold {
|
|
temperature = <0x4e20>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x2e0>;
|
|
};
|
|
|
|
gpu-switch-on {
|
|
temperature = <0xfde8>;
|
|
hysteresis = <0x7d0>;
|
|
type = "active";
|
|
phandle = <0x2e1>;
|
|
};
|
|
|
|
gpu-control-temp {
|
|
temperature = <0x11170>;
|
|
hysteresis = <0x1388>;
|
|
type = "passive";
|
|
phandle = <0x11f>;
|
|
};
|
|
|
|
gpu-alert0 {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x2e2>;
|
|
};
|
|
|
|
gpu-alert1 {
|
|
temperature = <0x186a0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x2e3>;
|
|
};
|
|
|
|
gpu-alert2 {
|
|
temperature = <0x19a28>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x2e4>;
|
|
};
|
|
|
|
gpu-alert3 {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x2e5>;
|
|
};
|
|
|
|
gpu-hot {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "hot";
|
|
phandle = <0x2e6>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x11f>;
|
|
cooling-device = <0x120 0x00 0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
ISP {
|
|
zone_name = "ISP_THERMAL";
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x121>;
|
|
phandle = <0x2e7>;
|
|
|
|
trips {
|
|
|
|
isp-alert0 {
|
|
temperature = <0x4e20>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x122>;
|
|
};
|
|
|
|
isp-alert1 {
|
|
temperature = <0x17318>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x124>;
|
|
};
|
|
|
|
isp-alert2 {
|
|
temperature = <0x186a0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x125>;
|
|
};
|
|
|
|
isp-alert3 {
|
|
temperature = <0x19a28>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x126>;
|
|
};
|
|
|
|
isp-alert4 {
|
|
temperature = <0x1adb0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x127>;
|
|
};
|
|
|
|
isp-alert5 {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x128>;
|
|
};
|
|
|
|
isp-alert6 {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x129>;
|
|
};
|
|
|
|
isp-hot {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "hot";
|
|
phandle = <0x12a>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x122>;
|
|
cooling-device = <0x123 0x00 0x00>;
|
|
};
|
|
|
|
map1 {
|
|
trip = <0x124>;
|
|
cooling-device = <0x123 0x00 0x00>;
|
|
};
|
|
|
|
map2 {
|
|
trip = <0x125>;
|
|
cooling-device = <0x123 0x00 0x00>;
|
|
};
|
|
|
|
map3 {
|
|
trip = <0x126>;
|
|
cooling-device = <0x123 0x00 0x00>;
|
|
};
|
|
|
|
map4 {
|
|
trip = <0x127>;
|
|
cooling-device = <0x123 0x00 0x00>;
|
|
};
|
|
|
|
map5 {
|
|
trip = <0x128>;
|
|
cooling-device = <0x123 0x00 0x00>;
|
|
};
|
|
|
|
map6 {
|
|
trip = <0x129>;
|
|
cooling-device = <0x123 0x00 0x00>;
|
|
};
|
|
|
|
map7 {
|
|
trip = <0x12a>;
|
|
cooling-device = <0x123 0x00 0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
NPU {
|
|
zone_name = "NPU_THERMAL";
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x12b>;
|
|
phandle = <0x2e8>;
|
|
|
|
trips {
|
|
|
|
npu-alert0 {
|
|
temperature = <0x4e20>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x12c>;
|
|
};
|
|
|
|
npu-alert1 {
|
|
temperature = <0x128e0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x12e>;
|
|
};
|
|
|
|
npu-alert2 {
|
|
temperature = <0x13c68>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x12f>;
|
|
};
|
|
|
|
npu-alert3 {
|
|
temperature = <0x14ff0>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x130>;
|
|
};
|
|
|
|
npu-alert4 {
|
|
temperature = <0x16378>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x131>;
|
|
};
|
|
|
|
npu-alert5 {
|
|
temperature = <0x17700>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x132>;
|
|
};
|
|
|
|
npu-alert6 {
|
|
temperature = <0x18a88>;
|
|
hysteresis = <0x1388>;
|
|
type = "active";
|
|
phandle = <0x133>;
|
|
};
|
|
|
|
npu-hot {
|
|
temperature = <0x1c138>;
|
|
hysteresis = <0x1388>;
|
|
type = "hot";
|
|
phandle = <0x134>;
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
|
|
map0 {
|
|
trip = <0x12c>;
|
|
cooling-device = <0x12d 0x00 0x00>;
|
|
};
|
|
|
|
map1 {
|
|
trip = <0x12e>;
|
|
cooling-device = <0x12d 0x00 0x00>;
|
|
};
|
|
|
|
map2 {
|
|
trip = <0x12f>;
|
|
cooling-device = <0x12d 0x00 0x00>;
|
|
};
|
|
|
|
map3 {
|
|
trip = <0x130>;
|
|
cooling-device = <0x12d 0x00 0x00>;
|
|
};
|
|
|
|
map4 {
|
|
trip = <0x131>;
|
|
cooling-device = <0x12d 0x00 0x00>;
|
|
};
|
|
|
|
map5 {
|
|
trip = <0x132>;
|
|
cooling-device = <0x12d 0x00 0x00>;
|
|
};
|
|
|
|
map6 {
|
|
trip = <0x133>;
|
|
cooling-device = <0x12d 0x00 0x00>;
|
|
};
|
|
|
|
map7 {
|
|
trip = <0x134>;
|
|
cooling-device = <0x12d 0x00 0x00>;
|
|
};
|
|
};
|
|
};
|
|
|
|
CP {
|
|
zone_name = "CP_THERMAL";
|
|
polling-delay-passive = <0x00>;
|
|
polling-delay = <0x00>;
|
|
thermal-sensors = <0x135>;
|
|
phandle = <0x2e9>;
|
|
};
|
|
};
|
|
|
|
mcinfo@1c030000 {
|
|
compatible = "samsung,exynos-mcinfo";
|
|
reg = <0x00 0x1c03f04c 0x04 0x00 0x1c13f04c 0x04 0x00 0x1c23f04c 0x04 0x00 0x1c33f04c 0x04>;
|
|
bit_field = <0x18 0x05>;
|
|
basecnt = <0x04>;
|
|
irqcnt = <0x04>;
|
|
interrupts = <0x00 0x1c0 0x04 0x00 0x1c8 0x04 0x00 0x1d1 0x04 0x00 0x1d9 0x04>;
|
|
phandle = <0x2ea>;
|
|
};
|
|
|
|
cal_if {
|
|
compatible = "samsung,exynos_cal_if";
|
|
reg = <0x00 0x1a330000 0x8000 0x00 0x18c00000 0x1000 0x00 0x1a030000 0x1000 0x00 0x1d040000 0x1000 0x00 0x1d050000 0x1000 0x00 0x1d060000 0x1000 0x00 0x1d030000 0x1000 0x00 0x10020000 0x1000>;
|
|
acpm-ipc-channel = <0x00>;
|
|
};
|
|
|
|
ect {
|
|
parameter_address = <0x90000000>;
|
|
parameter_size = <0x52000>;
|
|
};
|
|
|
|
exynos-ect {
|
|
compatible = "samsung,exynos-ect";
|
|
memory-region = <0x136>;
|
|
};
|
|
|
|
acpm_dvfs {
|
|
compatible = "samsung,exynos-acpm-dvfs";
|
|
acpm-ipc-channel = <0x05>;
|
|
};
|
|
|
|
pd-aud@15861880 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb1380000>;
|
|
need_smc = <0x18d10204>;
|
|
cmu_id = <0x18c00000>;
|
|
status = "okay";
|
|
power-down-ok = <0x01>;
|
|
#power-domain-cells = <0x00>;
|
|
skip-idle-ip;
|
|
phandle = <0xb1>;
|
|
};
|
|
|
|
pd-csis@15861D80 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb1380001>;
|
|
need_smc = <0x17010204>;
|
|
cmu_id = <0x17000000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0xa6>;
|
|
};
|
|
|
|
pd-vpc@15861E00 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb1380002>;
|
|
need_smc = <0x16610204>;
|
|
cmu_id = <0x16600000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0xb3>;
|
|
};
|
|
|
|
pd-itp@15862580 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb138000b>;
|
|
need_smc = <0x17410204>;
|
|
cmu_id = <0x17400000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x137>;
|
|
};
|
|
|
|
pd-dns@15861E80 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb1380003>;
|
|
need_smc = <0x17510204>;
|
|
cmu_id = <0x17500000>;
|
|
status = "okay";
|
|
parent = <0x137>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0xaa>;
|
|
};
|
|
|
|
pd-hsi0@15862400 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb138000a>;
|
|
need_smc = <0x10a10204>;
|
|
cmu_id = <0x10a00000>;
|
|
status = "okay";
|
|
power-down-ok = <0x03>;
|
|
#power-domain-cells = <0x00>;
|
|
skip-idle-ip;
|
|
phandle = <0x105>;
|
|
};
|
|
|
|
pd-dpub@15861F00 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb1380004>;
|
|
need_smc = <0x19e10204>;
|
|
cmu_id = <0x19e00000>;
|
|
status = "okay";
|
|
parent = <0x105>;
|
|
#power-domain-cells = <0x00>;
|
|
skip-idle-ip;
|
|
phandle = <0x138>;
|
|
};
|
|
|
|
pd-dpuf0@15861F80 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb1380005>;
|
|
need_smc = <0x19c10204>;
|
|
cmu_id = <0x19c00000>;
|
|
status = "okay";
|
|
parent = <0x138>;
|
|
#power-domain-cells = <0x00>;
|
|
pd-boot-on;
|
|
skip-idle-ip;
|
|
phandle = <0xa4>;
|
|
};
|
|
|
|
pd-dpuf1@15862000 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb1380006>;
|
|
need_smc = <0x1ae10204>;
|
|
cmu_id = <0x1ae00000>;
|
|
status = "okay";
|
|
parent = <0x138>;
|
|
#power-domain-cells = <0x00>;
|
|
pd-boot-on;
|
|
skip-idle-ip;
|
|
phandle = <0xa5>;
|
|
};
|
|
|
|
pd-vpd0@15862080 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb1380007>;
|
|
need_smc = <0x16810204>;
|
|
cmu_id = <0x16800000>;
|
|
status = "okay";
|
|
parent = <0xb3>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x139>;
|
|
};
|
|
|
|
pd-vpd1@15862100 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb1380008>;
|
|
need_smc = <0x16910204>;
|
|
cmu_id = <0x16900000>;
|
|
status = "okay";
|
|
parent = <0x139>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x13c>;
|
|
};
|
|
|
|
pd-embedded_g3d@15862280 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb1380009>;
|
|
need_smc = <0x18410204>;
|
|
cmu_id = <0x18400000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0xff>;
|
|
};
|
|
|
|
pd-m2m@15862600 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb138000c>;
|
|
need_smc = <0x18910204>;
|
|
cmu_id = <0x18900000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0xb0>;
|
|
};
|
|
|
|
pd-mcsc@15862680 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb138000d>;
|
|
need_smc = <0x15c10204>;
|
|
cmu_id = <0x15c00000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0xab>;
|
|
};
|
|
|
|
pd-mfc0@15862700 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb138000e>;
|
|
need_smc = <0x18610204>;
|
|
cmu_id = <0x18600000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0xae>;
|
|
};
|
|
|
|
pd-mfc1@15862780 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb138000f>;
|
|
need_smc = <0x18810204>;
|
|
cmu_id = <0x18800000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0xaf>;
|
|
};
|
|
|
|
pd-npus@15862C00 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb1380013>;
|
|
need_smc = <0x17c10204>;
|
|
cmu_id = <0x17c00000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0xb2>;
|
|
};
|
|
|
|
pd-npu00@15862A00 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb1380010>;
|
|
need_smc = <0x19810204>;
|
|
cmu_id = <0x19800000>;
|
|
status = "okay";
|
|
parent = <0xb2>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x13a>;
|
|
};
|
|
|
|
pd-npu01@15862A80 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb1380011>;
|
|
need_smc = <0x19910204>;
|
|
cmu_id = <0x19900000>;
|
|
status = "okay";
|
|
parent = <0x13a>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x13b>;
|
|
};
|
|
|
|
pd-npu10@15862B00 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb1380012>;
|
|
need_smc = <0x19a10204>;
|
|
cmu_id = <0x19a00000>;
|
|
status = "okay";
|
|
parent = <0x13b>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0x13d>;
|
|
};
|
|
|
|
pd-lme@15862C80 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb1380014>;
|
|
need_smc = <0x17710204>;
|
|
cmu_id = <0x17700000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0xa7>;
|
|
};
|
|
|
|
pd-embedded_ssp@15862F80 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb1380016>;
|
|
cmu_id = <0x18200000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
skip-idle-ip;
|
|
phandle = <0x13e>;
|
|
};
|
|
|
|
pd-taa@15863080 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb1380017>;
|
|
need_smc = <0x16e10204>;
|
|
cmu_id = <0x16e00000>;
|
|
status = "okay";
|
|
parent = <0xa6>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0xa8>;
|
|
};
|
|
|
|
pd-mcfp0@15863100 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb1380018>;
|
|
need_smc = <0x17810204>;
|
|
cmu_id = <0x17800000>;
|
|
status = "okay";
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0xad>;
|
|
};
|
|
|
|
pd-mcfp1@15863180 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb1380019>;
|
|
need_smc = <0x17a10204>;
|
|
cmu_id = <0x17a00000>;
|
|
status = "okay";
|
|
parent = <0xad>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0xac>;
|
|
};
|
|
|
|
pd-vts@15863200 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb138001a>;
|
|
need_smc = <0x15410204>;
|
|
cmu_id = <0x15500000>;
|
|
status = "okay";
|
|
power-down-ok = <0x02>;
|
|
#power-domain-cells = <0x00>;
|
|
skip-idle-ip;
|
|
phandle = <0x13f>;
|
|
};
|
|
|
|
pd-yuvpp@15863280 {
|
|
compatible = "samsung,exynos-pd";
|
|
cal_id = <0xb138001b>;
|
|
need_smc = <0x18010204>;
|
|
cmu_id = <0x18000000>;
|
|
status = "okay";
|
|
parent = <0xab>;
|
|
#power-domain-cells = <0x00>;
|
|
phandle = <0xa9>;
|
|
};
|
|
|
|
dbgdev-pd-aud {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xb1>;
|
|
};
|
|
|
|
dbgdev-pd-csis {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xa6>;
|
|
};
|
|
|
|
dbgdev-pd-vpc {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xb3>;
|
|
};
|
|
|
|
dbgdev-pd-dns {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xaa>;
|
|
};
|
|
|
|
dbgdev-pd-dpub {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x138>;
|
|
};
|
|
|
|
dbgdev-pd-dpuf0 {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xa4>;
|
|
};
|
|
|
|
dbgdev-pd-dpuf1 {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xa5>;
|
|
};
|
|
|
|
dbgdev-pd-vpd0 {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x139>;
|
|
};
|
|
|
|
dbgdev-pd-vpd1 {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x13c>;
|
|
};
|
|
|
|
dbgdev-pd-embedded_g3d {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xff>;
|
|
};
|
|
|
|
dbgdev-pd-hsi0 {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x105>;
|
|
};
|
|
|
|
dbgdev-pd-itp {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x137>;
|
|
};
|
|
|
|
dbgdev-pd-m2m {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xb0>;
|
|
};
|
|
|
|
dbgdev-pd-mcsc {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xab>;
|
|
};
|
|
|
|
dbgdev-pd-mfc0 {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xae>;
|
|
};
|
|
|
|
dbgdev-pd-mfc1 {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xaf>;
|
|
};
|
|
|
|
dbgdev-pd-npu00 {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x13a>;
|
|
};
|
|
|
|
dbgdev-pd-npu01 {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x13b>;
|
|
};
|
|
|
|
dbgdev-pd-npu10 {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x13d>;
|
|
};
|
|
|
|
dbgdev-pd-npus {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xb2>;
|
|
};
|
|
|
|
dbgdev-pd-lme {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xa7>;
|
|
};
|
|
|
|
dbgdev-pd-embedded_ssp {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x13e>;
|
|
};
|
|
|
|
dbgdev-pd-taa {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xa8>;
|
|
};
|
|
|
|
dbgdev-pd-mcfp0 {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xad>;
|
|
};
|
|
|
|
dbgdev-pd-mcfp1 {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xac>;
|
|
};
|
|
|
|
dbgdev-pd-vts {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0x13f>;
|
|
};
|
|
|
|
dbgdev-pd-yuvpp {
|
|
compatible = "samsung,exynos-pd-dbg";
|
|
power-domains = <0xa9>;
|
|
};
|
|
|
|
exynos-bts {
|
|
compatible = "samsung,exynos-bts";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
list-scen = "default\0cp_throughput\0mfc_uhd\0mfc_uhd_10bit\0mfc_8k_dec30\0g3d_heavy\0g3d_performance\0dp_default\0camera_default\0npu_normal\0mfc_uhd_enc60\0camera_heavy\0npu_performance";
|
|
|
|
bts_irp0 {
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
reg = <0x00 0x1a8a4000 0x400>;
|
|
status = "okay";
|
|
bts-type = <0x02>;
|
|
};
|
|
|
|
bts_irp1 {
|
|
reg = <0x00 0x1a8b4000 0x400>;
|
|
status = "okay";
|
|
bts-type = <0x02>;
|
|
};
|
|
|
|
bts_irp2 {
|
|
reg = <0x00 0x1a8c4000 0x400>;
|
|
status = "okay";
|
|
bts-type = <0x02>;
|
|
};
|
|
|
|
bts_irp3 {
|
|
reg = <0x00 0x1a8d4000 0x400>;
|
|
status = "okay";
|
|
bts-type = <0x02>;
|
|
};
|
|
|
|
bts_smc0 {
|
|
reg = <0x00 0x1c03f258 0x04>;
|
|
status = "okay";
|
|
bts-type = <0x04>;
|
|
};
|
|
|
|
bts_smc1 {
|
|
reg = <0x00 0x1c13f258 0x04>;
|
|
status = "okay";
|
|
bts-type = <0x04>;
|
|
};
|
|
|
|
bts_smc2 {
|
|
reg = <0x00 0x1c23f258 0x04>;
|
|
status = "okay";
|
|
bts-type = <0x04>;
|
|
};
|
|
|
|
bts_smc3 {
|
|
reg = <0x00 0x1c33f258 0x04>;
|
|
status = "okay";
|
|
bts-type = <0x04>;
|
|
};
|
|
|
|
bts_bus2_0 {
|
|
reg = <0x00 0x1b782000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x05>;
|
|
};
|
|
|
|
bts_bus2_1 {
|
|
reg = <0x00 0x1b792000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x05>;
|
|
};
|
|
|
|
bts_bus2_2 {
|
|
reg = <0x00 0x1b7a2000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x05>;
|
|
};
|
|
|
|
bts_bus2_3 {
|
|
reg = <0x00 0x1b7b2000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x05>;
|
|
};
|
|
|
|
bts_bus1_0 {
|
|
reg = <0x00 0x1b482000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x05>;
|
|
};
|
|
|
|
bts_bus1_1 {
|
|
reg = <0x00 0x1b492000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x05>;
|
|
};
|
|
|
|
bts_bus0_0 {
|
|
reg = <0x00 0x1b0e2000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x05>;
|
|
};
|
|
|
|
bts_bus0_1 {
|
|
reg = <0x00 0x1b0f2000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x05>;
|
|
};
|
|
|
|
bts_bus0_2 {
|
|
reg = <0x00 0x1b102000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x05>;
|
|
};
|
|
|
|
bts_bus0_3 {
|
|
reg = <0x00 0x1b112000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x05>;
|
|
};
|
|
|
|
bts_csis0 {
|
|
reg = <0x00 0x1b600000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x0c>;
|
|
awqos = <0x0c>;
|
|
rmo = <0xffff>;
|
|
wmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
qurgent_th_w = <0x0d>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_csis1 {
|
|
reg = <0x00 0x1b610000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x0c>;
|
|
awqos = <0x0c>;
|
|
rmo = <0xffff>;
|
|
wmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
qurgent_th_w = <0x0d>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_csis2 {
|
|
reg = <0x00 0x1b620000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x0c>;
|
|
awqos = <0x0c>;
|
|
rmo = <0xffff>;
|
|
wmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
qurgent_th_w = <0x0d>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_csis3 {
|
|
reg = <0x00 0x1b630000 0x5000>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x0c>;
|
|
awqos = <0x0c>;
|
|
rmo = <0xffff>;
|
|
wmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
qurgent_th_w = <0x0d>;
|
|
blocking_on = <0x00>;
|
|
vc-cfg = <0x01>;
|
|
};
|
|
};
|
|
|
|
bts_taa {
|
|
reg = <0x00 0x1b640000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x0c>;
|
|
awqos = <0x0c>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
qurgent_th_w = <0x0d>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mcfp00 {
|
|
reg = <0x00 0x1b650000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x0a>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mcfp01 {
|
|
reg = <0x00 0x1b660000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0a>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mcfp02 {
|
|
reg = <0x00 0x1b670000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0a>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mcfp03 {
|
|
reg = <0x00 0x1b680000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0a>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mcfp10 {
|
|
reg = <0x00 0x1b690000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0a>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_dns0 {
|
|
reg = <0x00 0x1b6a0000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0a>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_dns1 {
|
|
reg = <0x00 0x1b6b0000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x1c>;
|
|
wmo = <0x0a>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mcsc0 {
|
|
reg = <0x00 0x1b6c0000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mcsc1 {
|
|
reg = <0x00 0x1b6d0000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mcsc2 {
|
|
reg = <0x00 0x1b6e0000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x18>;
|
|
wmo = <0x30>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_yuvpp {
|
|
reg = <0x00 0x1b6f0000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0c>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0c>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0c>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0c>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0c>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0c>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0c>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0c>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0e>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0c>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0c>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x32>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0c>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_lme {
|
|
reg = <0x00 0x1b700000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x06>;
|
|
wmo = <0x06>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x14>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mfc00 {
|
|
reg = <0x00 0x1b710000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x14>;
|
|
wmo = <0x14>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x40>;
|
|
wmo = <0x40>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x14>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x12>;
|
|
wmo = <0x12>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x40>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mfc01 {
|
|
reg = <0x00 0x1b720000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x14>;
|
|
wmo = <0x14>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x40>;
|
|
wmo = <0x40>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x18>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x12>;
|
|
wmo = <0x12>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x40>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mfc10 {
|
|
reg = <0x00 0x1b730000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x14>;
|
|
wmo = <0x14>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x40>;
|
|
wmo = <0x40>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x14>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x12>;
|
|
wmo = <0x12>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x40>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mfc11 {
|
|
reg = <0x00 0x1b740000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x14>;
|
|
wmo = <0x14>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x40>;
|
|
wmo = <0x40>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x18>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x12>;
|
|
wmo = <0x12>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x40>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_hsi1 {
|
|
reg = <0x00 0x1b750000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0c>;
|
|
wmo = <0x0c>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
};
|
|
|
|
bts_m2m {
|
|
reg = <0x00 0x1b760000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x18>;
|
|
wmo = <0x18>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x08>;
|
|
qmax0_limit_w = <0x08>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x18>;
|
|
wmo = <0x18>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x08>;
|
|
qmax0_limit_w = <0x08>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x18>;
|
|
wmo = <0x18>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x08>;
|
|
qmax0_limit_w = <0x08>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x18>;
|
|
wmo = <0x18>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x08>;
|
|
qmax0_limit_w = <0x08>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x18>;
|
|
wmo = <0x18>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x08>;
|
|
qmax0_limit_w = <0x08>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x18>;
|
|
wmo = <0x18>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x08>;
|
|
qmax0_limit_w = <0x08>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x18>;
|
|
wmo = <0x18>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x08>;
|
|
qmax0_limit_w = <0x08>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x18>;
|
|
wmo = <0x18>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x08>;
|
|
qmax0_limit_w = <0x08>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x08>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_ssp {
|
|
reg = <0x00 0x1b770000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
};
|
|
|
|
bts_dpu00 {
|
|
reg = <0x00 0x1b400000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x0c>;
|
|
qurgent_th_w = <0x06>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_dpu01 {
|
|
reg = <0x00 0x1b410000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x0c>;
|
|
qurgent_th_w = <0x06>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_dpu10 {
|
|
reg = <0x00 0x1b420000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x0c>;
|
|
qurgent_th_w = <0x06>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_dpu11 {
|
|
reg = <0x00 0x1b430000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x0c>;
|
|
qurgent_th_w = <0x06>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x08>;
|
|
awqos = <0x08>;
|
|
rmo = <0x40>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_hsi0 {
|
|
reg = <0x00 0x1b440000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
};
|
|
|
|
bts_dit {
|
|
reg = <0x00 0x1b450000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0f>;
|
|
wmo = <0x0f>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
};
|
|
|
|
bts_sbic {
|
|
reg = <0x00 0x1b460000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x01>;
|
|
qmax0_limit_r = <0x01>;
|
|
qmax0_limit_w = <0x01>;
|
|
};
|
|
};
|
|
|
|
bts_vpc0 {
|
|
reg = <0x00 0x1b000000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x18>;
|
|
wmo = <0x18>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0xffff>;
|
|
wmo = <0xffff>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_vpc1 {
|
|
reg = <0x00 0x1b010000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x18>;
|
|
wmo = <0x18>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0xffff>;
|
|
wmo = <0xffff>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_vpc2 {
|
|
reg = <0x00 0x1b020000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x18>;
|
|
wmo = <0x18>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0xffff>;
|
|
wmo = <0xffff>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_npus0 {
|
|
reg = <0x00 0x1b030000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x36>;
|
|
wmo = <0x36>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x48>;
|
|
wmo = <0x48>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_npus1 {
|
|
reg = <0x00 0x1b040000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x36>;
|
|
wmo = <0x36>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x48>;
|
|
wmo = <0x48>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_npus2 {
|
|
reg = <0x00 0x1b050000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x36>;
|
|
wmo = <0x36>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x0b>;
|
|
wmo = <0x0b>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x60>;
|
|
wmo = <0x60>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_cp0 {
|
|
reg = <0x00 0x1a840000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x0d>;
|
|
awqos = <0x0d>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
qurgent_th_w = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_cp1 {
|
|
reg = <0x00 0x1a850000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x0a>;
|
|
awqos = <0x0a>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_cp2 {
|
|
reg = <0x00 0x1a860000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x08>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_aud {
|
|
reg = <0x00 0x1a870000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x09>;
|
|
awqos = <0x09>;
|
|
qurgent_on = <0x0c>;
|
|
qurgent_th_r = <0x14>;
|
|
qurgent_th_w = <0x14>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_coresight {
|
|
reg = <0x00 0x1a880000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_mmug3d {
|
|
reg = <0x00 0x1a890000 0x100>;
|
|
status = "okay";
|
|
bts-type = <0x01>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x04>;
|
|
awqos = <0x04>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
qurgent_on = <0x00>;
|
|
blocking_on = <0x00>;
|
|
};
|
|
};
|
|
|
|
bts_g3d0 {
|
|
reg = <0x00 0x1a000010 0x20 0x00 0x1a021220 0x10>;
|
|
status = "okay";
|
|
bts-type = <0x03>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
};
|
|
};
|
|
|
|
bts_g3d1 {
|
|
reg = <0x00 0x1a000038 0x20 0x00 0x1a021230 0x10>;
|
|
status = "okay";
|
|
bts-type = <0x03>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
};
|
|
};
|
|
|
|
bts_g3d2 {
|
|
reg = <0x00 0x1a000060 0x20 0x00 0x1a021240 0x10>;
|
|
status = "okay";
|
|
bts-type = <0x03>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
};
|
|
};
|
|
|
|
bts_g3d3 {
|
|
reg = <0x00 0x1a000088 0x20 0x00 0x1a021250 0x10>;
|
|
status = "okay";
|
|
bts-type = <0x03>;
|
|
|
|
default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x10>;
|
|
wmo = <0x10>;
|
|
};
|
|
|
|
cp_throughput {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
mfc_uhd {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
mfc_uhd_10bit {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
mfc_8k_dec30 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
g3d_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
};
|
|
|
|
g3d_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
};
|
|
|
|
dp_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
camera_default {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
npu_normal {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
mfc_uhd_enc60 {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
camera_heavy {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x04>;
|
|
wmo = <0x04>;
|
|
};
|
|
|
|
npu_performance {
|
|
stat_on = <0x01>;
|
|
bypass = <0x00>;
|
|
arqos = <0x00>;
|
|
awqos = <0x00>;
|
|
rmo = <0x20>;
|
|
wmo = <0x20>;
|
|
};
|
|
};
|
|
};
|
|
|
|
s2mpu {
|
|
compatible = "samsung,exynos-s2mpu";
|
|
memory_region = <0x140>;
|
|
subsystem-num = <0x0d>;
|
|
subsystem-names = "DPU\0CAMERA\0MFC0\0MFC1\0AUD\0NPUS\0VPC\0PCIE_GEN2\0VTS\0DIT\0G3D\0PCIE_GEN4\0DEFAULT";
|
|
instance-num = <0x2a>;
|
|
instance-names = "dpuf0_d0\0dpuf0_d1\0dpuf1_d0\0dpuf1_d1\0csis_d0\0csis_d1\0csis_d2\0csis_d3\0lme\0taa\0yuvpp\0dns_d0\0dns_d1\0mcsc_d0\0mcsc_d1\0mcsc_d2\0mcfp0_d0\0mcfp0_d1\0mcfp0_d2\0mcfp0_d3\0mcfp1\0mfc0_d0\0mfc0_d1\0mfc1_d0\0mfc1_d1\0m2m\0aud\0npus_d0\0npus_d1\0npus_d2\0vpc_d0\0vpc_d1\0vpc_d2\0hsi0\0hsi1\0acvps\0dit\0sbic\0g3d_d0\0g3d_d1\0g3d_d2\0g3d_d3";
|
|
channel = <0x2a>;
|
|
irqcnt = <0x2a>;
|
|
interrupts = <0x00 0x12f 0x04 0x00 0x132 0x04 0x00 0x147 0x04 0x00 0x14a 0x04 0x00 0xd9 0x04 0x00 0xdc 0x04 0x00 0xe3 0x04 0x00 0xe6 0x04 0x00 0x17b 0x04 0x00 0x249 0x04 0x00 0x276 0x04 0x00 0xf2 0x04 0x00 0xf5 0x04 0x00 0x1a5 0x04 0x00 0x1a8 0x04 0x00 0x1ab 0x04 0x00 0x187 0x04 0x00 0x18a 0x04 0x00 0x18d 0x04 0x00 0x190 0x04 0x00 0x195 0x04 0x00 0x1af 0x04 0x00 0x1b2 0x04 0x00 0x1b7 0x04 0x00 0x1ba 0x04 0x00 0x183 0x04 0x00 0x1d 0x04 0x00 0x1e5 0x04 0x00 0x1e8 0x04 0x00 0x1eb 0x04 0x00 0x269 0x04 0x00 0x26c 0x04 0x00 0x26f 0x04 0x00 0x15a 0x04 0x00 0x16f 0x04 0x00 0x29 0x04 0x00 0x2a 0x04 0x00 0x2b 0x04 0x00 0x85 0x04 0x00 0x86 0x04 0x00 0x87 0x04 0x00 0x88 0x04>;
|
|
};
|
|
|
|
el2_dynamic_lv3 {
|
|
compatible = "samsung,exynos-el2-dynamic-lv3";
|
|
interrupts = <0x00 0x28a 0x04>;
|
|
};
|
|
|
|
tee {
|
|
compatible = "samsung,exynos-tee";
|
|
interrupts = <0x00 0xdf 0x04>;
|
|
};
|
|
|
|
tee-tui {
|
|
compatible = "samsung,exynos-tui";
|
|
samsung,tzmp;
|
|
};
|
|
|
|
seclog {
|
|
compatible = "samsung,exynos-seclog";
|
|
interrupts = <0x00 0xe0 0x04>;
|
|
memory-region = <0x141>;
|
|
};
|
|
|
|
tzasc {
|
|
compatible = "samsung,exynos-tzasc";
|
|
channel = <0x04>;
|
|
interleaving_shift = <0x00>;
|
|
has_privileged = <0x00>;
|
|
irqcnt = <0x04>;
|
|
interrupts = <0x00 0x1c2 0x04 0x00 0x1ca 0x04 0x00 0x1d3 0x04 0x00 0x1db 0x04>;
|
|
};
|
|
|
|
ppmpu {
|
|
compatible = "samsung,exynos-ppmpu";
|
|
channel = <0x04>;
|
|
irqcnt = <0x04>;
|
|
interrupts = <0x00 0x1bd 0x04 0x00 0x1c5 0x04 0x00 0x1ce 0x04 0x00 0x1d6 0x04>;
|
|
};
|
|
|
|
hdcp {
|
|
compatible = "samsung,exynos-hdcp";
|
|
interrupts = <0x00 0xde 0x04>;
|
|
};
|
|
|
|
secmem {
|
|
compatible = "samsung,exynos-secmem";
|
|
power-domains = <0x105>;
|
|
dma-coherent;
|
|
};
|
|
|
|
ufs-srpmb {
|
|
compatible = "samsung,ufs-srpmb";
|
|
interrupts = <0x00 0xe1 0x04>;
|
|
};
|
|
|
|
ssp {
|
|
compatible = "samsung,exynos-ssp";
|
|
power-domains = <0x13e>;
|
|
};
|
|
|
|
mfc {
|
|
compatible = "samsung,exynos-mfc";
|
|
iommus = <0x142 0x143 0x144 0x145>;
|
|
samsung,iommu-group = <0x146>;
|
|
samsung,iommu-reserved-map = <0x00 0x00 0x10000000 0x00 0x10000000 0x100000 0x00 0x10100000 0x100000>;
|
|
samsung,iommu-identity-map = <0x00 0x15e1f000 0x10000>;
|
|
samsung,tzmp;
|
|
memory-region = <0x147>;
|
|
ip_ver = <0x1500010c>;
|
|
debug_mode = <0x01>;
|
|
nal_q_entry_size = <0x300>;
|
|
nal_q_dump_size = <0x178>;
|
|
nal_q = <0x01 0x00>;
|
|
skype = <0x01 0x00>;
|
|
black_bar = <0x01 0x00>;
|
|
color_aspect_dec = <0x01 0x00>;
|
|
static_info_dec = <0x01 0x00>;
|
|
color_aspect_enc = <0x01 0x00>;
|
|
static_info_enc = <0x01 0x180314>;
|
|
hdr10_plus = <0x01 0x180709>;
|
|
vp9_stride_align = <0x01 0x00>;
|
|
sbwc_uncomp = <0x01 0x190702>;
|
|
mem_clear = <0x01 0x00>;
|
|
wait_fw_status = <0x01 0x190122>;
|
|
wait_nalq_status = <0x01 0x191107>;
|
|
drm_switch_predict = <0x01 0x00>;
|
|
sbwc_enc_src_ctrl = <0x01 0x200110>;
|
|
metadata_interface = <0x01 0x200910>;
|
|
hdr10_plus_full = <0x01 0x200910>;
|
|
average_qp = <0x01 0x201030>;
|
|
mv_search_mode = <0x01 0x201118>;
|
|
support_av1_dec = <0x01>;
|
|
av1_film_grain = <0x01 0x200717>;
|
|
P010_decoding = <0x01>;
|
|
dithering_enable = <0x00>;
|
|
support_10bit = <0x01>;
|
|
support_422 = <0x01>;
|
|
support_rgb = <0x01>;
|
|
support_sbwc = <0x01>;
|
|
support_sbwcl = <0x01>;
|
|
sbwc_dec_max_width = <0x780>;
|
|
sbwc_dec_max_height = <0x440>;
|
|
sbwc_dec_max_inst_num = <0x01>;
|
|
sbwc_dec_hdr10_off = <0x00>;
|
|
max_hdr_win = <0x01>;
|
|
display_err_type = <0x02>;
|
|
security_ctrl = <0x00>;
|
|
display_framerate = <0x00>;
|
|
enc_param_num = <0x19>;
|
|
enc_param_addr = <0xf7b4 0xf7b8 0xf7b0 0xf798 0xfa2c 0xf790 0xfa34 0xfa38 0xfa3c 0xf7c0 0xf7c8 0xf7cc 0xfa60 0xfdd4 0xfddc 0xfb54 0xfb58 0xfba8 0xfd90 0xfd94 0xfd40 0xfd48 0xfd4c 0xfd50 0xfd80>;
|
|
enc_param_val = <0x80 0x80 0x00 0x4000 0x3fd00 0x00 0x00 0x2710 0x3e8 0x00 0x00 0x00 0x00 0x8050d211 0x00 0x3011 0x00 0x00 0x2d 0xa00 0x1d 0xf4240 0x33003300 0x02 0x01>;
|
|
bw_enc_h264 = <0xb190 0xdb30 0x2ba2>;
|
|
bw_enc_hevc = <0xb6a4 0xce1e 0x2623>;
|
|
bw_enc_hevc_10bit = <0xd269 0xfcf1 0x310c>;
|
|
bw_enc_vp8 = <0xfa00 0x106f6 0x57f6>;
|
|
bw_enc_vp9 = <0x11a86 0xe94e 0x4092>;
|
|
bw_enc_vp9_10bit = <0x2465d 0x1c0f0 0x7abb>;
|
|
bw_enc_mpeg4 = <0xae67 0xd81c 0x253b>;
|
|
bw_dec_h264 = <0x7f5d 0x864d 0x530f>;
|
|
bw_dec_hevc = <0x7515 0x70b3 0x4482>;
|
|
bw_dec_hevc_10bit = <0xce7b 0xb4a5 0x7a77>;
|
|
bw_dec_vp8 = <0x7000 0x7704 0x5734>;
|
|
bw_dec_vp9 = <0x47af 0x4a03 0x41ed>;
|
|
bw_dec_vp9_10bit = <0xa590 0x8694 0x7c16>;
|
|
bw_dec_av1 = <0x5ceb 0x4c72 0x3df0>;
|
|
bw_dec_av1_10bit = <0xa1bf 0x8aa2 0x7403>;
|
|
bw_dec_mpeg4 = <0x7b34 0x6318 0x3d9a>;
|
|
sbwc_bw_enc_h264 = <0x7b86 0x7db7 0x1b99>;
|
|
sbwc_bw_enc_hevc = <0x5dec 0x6b86 0x1700>;
|
|
sbwc_bw_enc_hevc_10bit = <0x7f9a 0x92da 0x2289>;
|
|
sbwc_bw_enc_vp8 = <0x7f9a 0x92da 0x2289>;
|
|
sbwc_bw_enc_vp9 = <0x5aec 0x6904 0x21fe>;
|
|
sbwc_bw_enc_vp9_10bit = <0xa53e 0xa09c 0x36e4>;
|
|
sbwc_bw_enc_mpeg4 = <0x7f9a 0x92da 0x2289>;
|
|
sbwc_bw_dec_h264 = <0x5ccd 0x48ab 0x3534>;
|
|
sbwc_bw_dec_hevc = <0x3bcd 0x3c1b 0x2827>;
|
|
sbwc_bw_dec_hevc_10bit = <0x5148 0x507a 0x3a14>;
|
|
sbwc_bw_dec_vp8 = <0x4333 0x4769 0x3452>;
|
|
sbwc_bw_dec_vp9 = <0x2b71 0x25db 0x2327>;
|
|
sbwc_bw_dec_vp9_10bit = <0x457b 0x3cde 0x384d>;
|
|
sbwc_bw_dec_mpeg4 = <0x49ec 0x3b75 0x24f6>;
|
|
num_mfc_freq = <0x07>;
|
|
mfc_freqs = <0x2b750 0x39210 0x57288 0x72420 0x82208 0xa1dd8 0xae8f8>;
|
|
max_Kbps = <0x3c000 0x14000>;
|
|
qos_weight_h264_hevc = <0x64>;
|
|
qos_weight_vp8_vp9 = <0x64>;
|
|
qos_weight_av1 = <0x46>;
|
|
qos_weight_other_codec = <0x19>;
|
|
qos_weight_3plane = <0x50>;
|
|
qos_weight_10bit = <0x4b>;
|
|
qos_weight_422 = <0x46>;
|
|
qos_weight_bframe = <0x32>;
|
|
qos_weight_num_of_ref = <0x3c>;
|
|
qos_weight_gpb = <0x32>;
|
|
qos_weight_num_of_tile = <0x4b>;
|
|
qos_weight_super64_bframe = <0x3c>;
|
|
core_balance = <0x36>;
|
|
iova_threshold = <0x6a4>;
|
|
idle_clk_ctrl = <0x01>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
phandle = <0x2eb>;
|
|
|
|
MFC-0 {
|
|
compatible = "samsung,exynos-mfc-core";
|
|
id = <0x00>;
|
|
reg = <0x00 0x186d0000 0x10000>;
|
|
interrupts = <0x00 0x1ac 0x04>;
|
|
clock-names = "aclk_mfc";
|
|
clocks = <0x04 0x5dc>;
|
|
iommus = <0x142 0x143>;
|
|
samsung,iommu-group = <0x146>;
|
|
samsung,iommu-reserved-map = <0x00 0x10000000 0x100000>;
|
|
samsung,iommu-identity-map = <0x00 0x15e1f000 0x10000>;
|
|
samsung,tzmp;
|
|
samsung,imgloader-s2mpu-support;
|
|
ip_ver = <0x1500010c>;
|
|
share_sysmmu = <0x00>;
|
|
axid_mask = <0x07>;
|
|
mfc_fault_num = <0x00>;
|
|
trans_info_offset = <0x1004>;
|
|
tsmux_axid = <0x01>;
|
|
llc = <0x01>;
|
|
need_llc_flush = <0x00>;
|
|
mfc_votf_base = <0x18700000>;
|
|
gdc_votf_base = <0x15e1f000>;
|
|
num_default_qos_steps = <0x09>;
|
|
num_encoder_qos_steps = <0x08>;
|
|
max_mb = <0x511b61>;
|
|
max_hw_mb = <0x3b5380>;
|
|
mfc_freq_control = <0x01>;
|
|
mo_control = <0x01>;
|
|
bw_control = <0x01>;
|
|
#dma-address-cells = <0x01>;
|
|
#dma-size-cells = <0x01>;
|
|
dma-window = <0x00 0xd0000000>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
phandle = <0x2ec>;
|
|
|
|
iommu {
|
|
reg = <0x00 0x18670000 0x9000 0x00 0x186a0000 0x9000>;
|
|
};
|
|
|
|
hwfc {
|
|
reg = <0x00 0x19cba164 0x04>;
|
|
};
|
|
|
|
votf {
|
|
reg = <0x00 0x18700000 0x1000>;
|
|
};
|
|
|
|
mfc_default_qos_table {
|
|
|
|
mfc_d_qos_variant_0 {
|
|
thrd_mb = <0x00>;
|
|
freq_mfc = <0x2b750>;
|
|
freq_int = <0x13880>;
|
|
freq_mif = <0x66c88>;
|
|
time_fw = <0x5c2>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_d_qos_variant_1 {
|
|
thrd_mb = <0x4136d>;
|
|
freq_mfc = <0x2b750>;
|
|
freq_int = <0x13880>;
|
|
freq_mif = <0x66c88>;
|
|
time_fw = <0x5c2>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_d_qos_variant_2 {
|
|
thrd_mb = <0x87973>;
|
|
freq_mfc = <0x39210>;
|
|
freq_int = <0x412f8>;
|
|
freq_mif = <0xa50a0>;
|
|
time_fw = <0x308>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_d_qos_variant_3 {
|
|
thrd_mb = <0x11a494>;
|
|
freq_mfc = <0x57288>;
|
|
freq_int = <0x412f8>;
|
|
freq_mif = <0xf78f0>;
|
|
time_fw = <0x243>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_d_qos_variant_4 {
|
|
thrd_mb = <0x1bd06e>;
|
|
freq_mfc = <0x57288>;
|
|
freq_int = <0x61a80>;
|
|
freq_mif = <0xf78f0>;
|
|
time_fw = <0x1fa>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_d_qos_variant_5 {
|
|
thrd_mb = <0x1f918d>;
|
|
freq_mfc = <0x72420>;
|
|
freq_int = <0x61a80>;
|
|
freq_mif = <0x14a140>;
|
|
time_fw = <0x19b>;
|
|
bts_scen = "mfc_uhd";
|
|
};
|
|
|
|
mfc_d_qos_variant_6 {
|
|
thrd_mb = <0x263e9f>;
|
|
freq_mfc = <0x72420>;
|
|
freq_int = <0x82208>;
|
|
freq_mif = <0x177bb8>;
|
|
time_fw = <0x169>;
|
|
bts_scen = "mfc_uhd";
|
|
};
|
|
|
|
mfc_d_qos_variant_7 {
|
|
thrd_mb = <0x303b6d>;
|
|
freq_mfc = <0xae8f8>;
|
|
freq_int = <0x82208>;
|
|
freq_mif = <0x26ae58>;
|
|
time_fw = <0x111>;
|
|
bts_scen = "mfc_uhd";
|
|
};
|
|
|
|
mfc_d_qos_variant_8 {
|
|
thrd_mb = <0x416455>;
|
|
freq_mfc = <0xae8f8>;
|
|
freq_int = "\0\f5";
|
|
freq_mif = <0x29a810>;
|
|
time_fw = <0xe4>;
|
|
bts_scen = "mfc_uhd_10bit";
|
|
};
|
|
};
|
|
|
|
mfc_encoder_qos_table {
|
|
|
|
mfc_e_qos_variant_0 {
|
|
thrd_mb = <0x00>;
|
|
freq_mfc = <0x2b750>;
|
|
freq_int = <0x13880>;
|
|
freq_mif = <0x66c88>;
|
|
time_fw = <0x5c2>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_e_qos_variant_1 {
|
|
thrd_mb = <0x4136d>;
|
|
freq_mfc = <0x2b750>;
|
|
freq_int = <0x13880>;
|
|
freq_mif = <0x66c88>;
|
|
time_fw = <0x5c2>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_e_qos_variant_2 {
|
|
thrd_mb = <0x87973>;
|
|
freq_mfc = <0x39210>;
|
|
freq_int = <0x412f8>;
|
|
freq_mif = <0xa50a0>;
|
|
time_fw = <0x308>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_e_qos_variant_3 {
|
|
thrd_mb = <0x11a494>;
|
|
freq_mfc = <0x57288>;
|
|
freq_int = <0x412f8>;
|
|
freq_mif = <0xf78f0>;
|
|
time_fw = <0x243>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_e_qos_variant_4 {
|
|
thrd_mb = <0x1bd06e>;
|
|
freq_mfc = <0x57288>;
|
|
freq_int = <0x412f8>;
|
|
freq_mif = <0x14a140>;
|
|
time_fw = <0x203>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_e_qos_variant_5 {
|
|
thrd_mb = <0x1f9633>;
|
|
freq_mfc = <0x72420>;
|
|
freq_int = <0x61a80>;
|
|
freq_mif = <0x14a140>;
|
|
time_fw = <0x19b>;
|
|
bts_scen = "mfc_uhd";
|
|
};
|
|
|
|
mfc_e_qos_variant_6 {
|
|
thrd_mb = <0x263e9f>;
|
|
freq_mfc = <0x61a80>;
|
|
freq_int = <0x61a80>;
|
|
freq_mif = <0x177bb8>;
|
|
time_fw = <0x169>;
|
|
bts_scen = "mfc_uhd";
|
|
};
|
|
|
|
mfc_e_qos_variant_7 {
|
|
thrd_mb = <0x3068b2>;
|
|
freq_mfc = <0x82208>;
|
|
freq_int = <0x82208>;
|
|
freq_mif = <0x1ef1e0>;
|
|
time_fw = <0x128>;
|
|
bts_scen = "mfc_uhd";
|
|
};
|
|
};
|
|
|
|
mfc_perf_boost_table {
|
|
num_cluster = <0x03>;
|
|
freq_cluster = <0x1a94b0 0x1cf610 0x163780>;
|
|
freq_mfc = <0xa2990>;
|
|
freq_int = <0x825f0>;
|
|
freq_mif = <0x29a810>;
|
|
bts_scen = "mfc_uhd_10bit";
|
|
};
|
|
};
|
|
|
|
MFC-1 {
|
|
compatible = "samsung,exynos-mfc-core";
|
|
id = <0x01>;
|
|
reg = <0x00 0x188d0000 0x10000>;
|
|
interrupts = <0x00 0x1b4 0x04>;
|
|
clock-names = "aclk_mfc";
|
|
clocks = <0x04 0x60e>;
|
|
iommus = <0x144 0x145>;
|
|
samsung,iommu-group = <0x146>;
|
|
samsung,iommu-reserved-map = <0x00 0x10100000 0x100000>;
|
|
samsung,tzmp;
|
|
samsung,imgloader-s2mpu-support;
|
|
ip_ver = <0x1500010d>;
|
|
share_sysmmu = <0x00>;
|
|
axid_mask = <0xffff>;
|
|
mfc_fault_num = <0x00>;
|
|
trans_info_offset = <0x1004>;
|
|
llc = <0x01>;
|
|
need_llc_flush = <0x00>;
|
|
num_default_qos_steps = <0x09>;
|
|
num_encoder_qos_steps = <0x08>;
|
|
max_mb = <0x511b61>;
|
|
max_hw_mb = <0x3b5380>;
|
|
mfc_freq_control = <0x01>;
|
|
mo_control = <0x01>;
|
|
bw_control = <0x01>;
|
|
#dma-address-cells = <0x01>;
|
|
#dma-size-cells = <0x01>;
|
|
dma-window = <0x00 0xd0000000>;
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
phandle = <0x2ed>;
|
|
|
|
iommu {
|
|
reg = <0x00 0x18870000 0x9000 0x00 0x188a0000 0x9000>;
|
|
};
|
|
|
|
mfc_default_qos_table {
|
|
|
|
mfc_d_qos_variant_0 {
|
|
thrd_mb = <0x00>;
|
|
freq_mfc = <0x2b750>;
|
|
freq_int = <0x13880>;
|
|
freq_mif = <0x66c88>;
|
|
time_fw = <0x5c2>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_d_qos_variant_1 {
|
|
thrd_mb = <0x4136d>;
|
|
freq_mfc = <0x2b750>;
|
|
freq_int = <0x13880>;
|
|
freq_mif = <0x66c88>;
|
|
time_fw = <0x5c2>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_d_qos_variant_2 {
|
|
thrd_mb = <0x87973>;
|
|
freq_mfc = <0x39210>;
|
|
freq_int = <0x412f8>;
|
|
freq_mif = <0xa50a0>;
|
|
time_fw = <0x308>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_d_qos_variant_3 {
|
|
thrd_mb = <0x11a494>;
|
|
freq_mfc = <0x57288>;
|
|
freq_int = <0x412f8>;
|
|
freq_mif = <0xf78f0>;
|
|
time_fw = <0x243>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_d_qos_variant_4 {
|
|
thrd_mb = <0x1bd06e>;
|
|
freq_mfc = <0x57288>;
|
|
freq_int = <0x61a80>;
|
|
freq_mif = <0xf78f0>;
|
|
time_fw = <0x1fa>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_d_qos_variant_5 {
|
|
thrd_mb = <0x1f918d>;
|
|
freq_mfc = <0x72420>;
|
|
freq_int = <0x61a80>;
|
|
freq_mif = <0x14a140>;
|
|
time_fw = <0x19b>;
|
|
bts_scen = "mfc_uhd";
|
|
};
|
|
|
|
mfc_d_qos_variant_6 {
|
|
thrd_mb = <0x263e9f>;
|
|
freq_mfc = <0x72420>;
|
|
freq_int = <0x82208>;
|
|
freq_mif = <0x177bb8>;
|
|
time_fw = <0x169>;
|
|
bts_scen = "mfc_uhd";
|
|
};
|
|
|
|
mfc_d_qos_variant_7 {
|
|
thrd_mb = <0x303b6d>;
|
|
freq_mfc = <0xae8f8>;
|
|
freq_int = <0x82208>;
|
|
freq_mif = <0x26ae58>;
|
|
time_fw = <0x111>;
|
|
bts_scen = "mfc_uhd";
|
|
};
|
|
|
|
mfc_d_qos_variant_8 {
|
|
thrd_mb = <0x416455>;
|
|
freq_mfc = <0xae8f8>;
|
|
freq_int = "\0\f5";
|
|
freq_mif = <0x29a810>;
|
|
time_fw = <0xe4>;
|
|
bts_scen = "mfc_uhd_10bit";
|
|
};
|
|
};
|
|
|
|
mfc_encoder_qos_table {
|
|
|
|
mfc_e_qos_variant_0 {
|
|
thrd_mb = <0x00>;
|
|
freq_mfc = <0x2b750>;
|
|
freq_int = <0x13880>;
|
|
freq_mif = <0x66c88>;
|
|
time_fw = <0x5c2>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_e_qos_variant_1 {
|
|
thrd_mb = <0x4136d>;
|
|
freq_mfc = <0x2b750>;
|
|
freq_int = <0x13880>;
|
|
freq_mif = <0x66c88>;
|
|
time_fw = <0x5c2>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_e_qos_variant_2 {
|
|
thrd_mb = <0x87973>;
|
|
freq_mfc = <0x39210>;
|
|
freq_int = <0x412f8>;
|
|
freq_mif = <0xa50a0>;
|
|
time_fw = <0x308>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_e_qos_variant_3 {
|
|
thrd_mb = <0x11a494>;
|
|
freq_mfc = <0x57288>;
|
|
freq_int = <0x412f8>;
|
|
freq_mif = <0xf78f0>;
|
|
time_fw = <0x243>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_e_qos_variant_4 {
|
|
thrd_mb = <0x1bd06e>;
|
|
freq_mfc = <0x57288>;
|
|
freq_int = <0x412f8>;
|
|
freq_mif = <0x14a140>;
|
|
time_fw = <0x203>;
|
|
bts_scen = "default";
|
|
};
|
|
|
|
mfc_e_qos_variant_5 {
|
|
thrd_mb = <0x1f9633>;
|
|
freq_mfc = <0x72420>;
|
|
freq_int = <0x61a80>;
|
|
freq_mif = <0x14a140>;
|
|
time_fw = <0x19b>;
|
|
bts_scen = "mfc_uhd";
|
|
};
|
|
|
|
mfc_e_qos_variant_6 {
|
|
thrd_mb = <0x263e9f>;
|
|
freq_mfc = <0x61a80>;
|
|
freq_int = <0x61a80>;
|
|
freq_mif = <0x177bb8>;
|
|
time_fw = <0x169>;
|
|
bts_scen = "mfc_uhd";
|
|
};
|
|
|
|
mfc_e_qos_variant_7 {
|
|
thrd_mb = <0x3068b2>;
|
|
freq_mfc = <0x82208>;
|
|
freq_int = <0x82208>;
|
|
freq_mif = <0x1ef1e0>;
|
|
time_fw = <0x128>;
|
|
bts_scen = "mfc_uhd";
|
|
};
|
|
};
|
|
|
|
mfc_perf_boost_table {
|
|
num_cluster = <0x03>;
|
|
freq_cluster = <0x1a94b0 0x1cf610 0x163780>;
|
|
freq_mfc = <0xa2990>;
|
|
freq_int = <0x825f0>;
|
|
freq_mif = <0x29a810>;
|
|
bts_scen = "mfc_uhd_10bit";
|
|
};
|
|
};
|
|
};
|
|
|
|
smfc@18940000 {
|
|
compatible = "samsung,exynos8890-jpeg";
|
|
dma-coherent;
|
|
reg = <0x00 0x18940000 0x1000>;
|
|
interrupts = <0x00 0x17d 0x04>;
|
|
clocks = <0x04 0x4e4>;
|
|
clock-names = "gate";
|
|
iommus = <0x148>;
|
|
samsung,iommu-group = <0x149>;
|
|
smfc,int_qos_minlock = "\0\f5";
|
|
phandle = <0x2ee>;
|
|
};
|
|
|
|
smfc@18950000 {
|
|
compatible = "samsung,exynos8890-jpeg";
|
|
dma-coherent;
|
|
reg = <0x00 0x18950000 0x1000>;
|
|
interrupts = <0x00 0x17e 0x04>;
|
|
clocks = <0x04 0x4e5>;
|
|
clock-names = "gate";
|
|
iommus = <0x148>;
|
|
samsung,iommu-group = <0x149>;
|
|
smfc,int_qos_minlock = "\0\f5";
|
|
phandle = <0x2ef>;
|
|
};
|
|
|
|
scaler@18960000 {
|
|
compatible = "samsung,exynos5-scaler";
|
|
reg = <0x00 0x18960000 0x3000>;
|
|
interrupts = <0x00 0x180 0x04>;
|
|
clocks = <0x04 0x4e7>;
|
|
clock-names = "gate";
|
|
itmon,master = "MSCL";
|
|
itmon,dest = "M2M";
|
|
dma-coherent;
|
|
iommus = <0x148>;
|
|
samsung,iommu-group = <0x149>;
|
|
samsung,tzmp;
|
|
#dma-address-cells = <0x01>;
|
|
#dma-size-cells = <0x01>;
|
|
dma-window = <0x00 0xe0000000>;
|
|
mscl_qos_table = <0x00 0xc3500 0xa1dd8 0x00 0x82208 0x61a80 0x00 0x61a80 0x50eec 0x00 0x412f8 0x30d40 0x00 0x13880 0xc350>;
|
|
mscl_ppc_table = <0x0c 0x1e4 0x1dc 0x10 0x16e 0x16e 0x18 0x131 0x131 0x20 0xbd 0xb9 0x64 0xde 0xe1>;
|
|
mscl_mif_ref = <0x854d0>;
|
|
mscl_bw_ref = <0x2e593c>;
|
|
#mscl-votf-address-cells = <0x01>;
|
|
#mscl-votf-size-cells = <0x01>;
|
|
mscl_votf_reg = <0x189e0000 0x10000>;
|
|
samsung,mscl-votf_targets = <0x14a 0x19cb0000 0x10000 0x19ca0000 0x10000 0x14a 0x1aeb0000 0x10000 0x1aea0000 0x10000>;
|
|
phandle = <0x2f0>;
|
|
};
|
|
|
|
tsmux@186E0000 {
|
|
compatible = "samsung,exynos-tsmux";
|
|
reg = <0x00 0x186e0000 0x1000>;
|
|
interrupts = <0x00 0x1b3 0x04>;
|
|
iommus = <0x143>;
|
|
samsung,iommu-group = <0x146>;
|
|
power-domains = <0xae>;
|
|
phandle = <0x2f1>;
|
|
};
|
|
|
|
repeater@0 {
|
|
compatible = "samsung,exynos-repeater";
|
|
power-domains = <0xa4>;
|
|
phandle = <0x2f2>;
|
|
};
|
|
|
|
abox-gic@18cf0000 {
|
|
compatible = "samsung,abox-gic";
|
|
reg = <0x00 0x18cf1000 0x1000 0x00 0x18cf2000 0x1004>;
|
|
reg-names = "gicd\0gicc";
|
|
interrupts = <0x00 0x19 0x04>;
|
|
phandle = <0x14e>;
|
|
};
|
|
|
|
abox@18c50000 {
|
|
compatible = "samsung,abox";
|
|
reg = <0x00 0x18c50000 0x40000 0x00 0x18c10000 0x10000 0x00 0x18e00000 0x15a000 0x00 0x18ce0000 0x10000 0x00 0x15500000 0x100000>;
|
|
reg-names = "sfr\0sysreg\0sram\0timer\0mailbox_apm";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
iommus = <0x14b>;
|
|
memory-region = <0x14c>;
|
|
samsung,iommu-group = <0x14d>;
|
|
power-domains = <0xb1>;
|
|
clocks = <0x04 0x9a 0x04 0x9b 0x04 0x86 0x04 0x8e 0x04 0x90 0x04 0x9c 0x04 0x9d>;
|
|
clock-names = "pll\0pll1\0audif\0bus\0cnt\0cp_pcmc\0aud_pcmc";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX";
|
|
samsung,quirks = "try to asrc off\0silent reset";
|
|
samsung,ipc-tx-area = <0x01 0x850000 0x18000>;
|
|
samsung,ipc-rx-area = <0x01 0x868000 0x18000>;
|
|
samsung,shm-area = <0x01 0x8bc000 0x4000>;
|
|
samsung,handshake-area = <0x00 0x2f2e0 0x20>;
|
|
samsung,abox-gic = <0x14e>;
|
|
samsung,uaif-max-div = <0x200>;
|
|
samsung,pm-qos-int = <0x00 0x00 0x00 0x00 0x00>;
|
|
samsung,pm-qos-aud = <0x120160 0x104410 0xc3500 0x900b0 0x60310 0x30188 0x00>;
|
|
samsung,pm-qos-stable-min = <0x24220>;
|
|
samsung,abox-llc-way = <0x06 0x0a 0x00 0x00>;
|
|
phandle = <0x2f3>;
|
|
|
|
abox-core@18c55000 {
|
|
compatible = "samsung,abox-core";
|
|
reg = <0x00 0x18c55000 0x80>;
|
|
reg-names = "gpr";
|
|
samsung,id = <0x00>;
|
|
samsung,type = "CA32";
|
|
samsung,pmu_power = <0x36c0 0x01>;
|
|
samsung,pmu_enable = <0x36cc 0x01>;
|
|
samsung,pmu_standby = <0x36e4 0x11>;
|
|
phandle = <0x2f4>;
|
|
|
|
abox-firmware-sram0 {
|
|
samsung,name = "calliope_sram.bin";
|
|
samsung,area = <0x00>;
|
|
samsung,offset = <0x00>;
|
|
samsung,fw-signed;
|
|
samsung,fw-id = <0x00>;
|
|
phandle = <0x2f5>;
|
|
};
|
|
|
|
abox-firmware-dram0 {
|
|
samsung,name = "calliope_dram.bin";
|
|
samsung,area = <0x01>;
|
|
samsung,offset = <0x00>;
|
|
phandle = <0x2f6>;
|
|
};
|
|
};
|
|
|
|
abox-core@18c55080 {
|
|
compatible = "samsung,abox-core";
|
|
reg = <0x00 0x18c55080 0x80 0x00 0x18c55100 0x04>;
|
|
reg-names = "gpr\0status";
|
|
samsung,id = <0x01>;
|
|
samsung,type = "CA32";
|
|
samsung,pmu_power = <0x3700 0x01>;
|
|
samsung,pmu_enable = <0x3720 0x01>;
|
|
samsung,pmu_standby = <0x3724 0x01>;
|
|
phandle = <0x2f7>;
|
|
|
|
abox-firmware-sram1 {
|
|
samsung,name = "calliope_sram_2.bin";
|
|
samsung,area = <0x00>;
|
|
samsung,offset = <0x32000>;
|
|
phandle = <0x2f8>;
|
|
};
|
|
|
|
abox-firmware-dram1 {
|
|
samsung,name = "calliope_dram_2.bin";
|
|
samsung,area = <0x01>;
|
|
samsung,offset = <0x280000>;
|
|
phandle = <0x2f9>;
|
|
};
|
|
};
|
|
|
|
abox-rdma@18c51000 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51000 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x00>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA0";
|
|
phandle = <0x2fa>;
|
|
};
|
|
|
|
abox-rdma@18c51100 {
|
|
compatible = "samsung,abox-rdma-compr";
|
|
reg = <0x00 0x18c51100 0x100 0x00 0x18e2f600 0x70>;
|
|
reg-names = "sfr\0mailbox";
|
|
memory-region = <0x14f>;
|
|
samsung,id = <0x01>;
|
|
samsung,type = "compress";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX ComprTx0";
|
|
phandle = <0x2fb>;
|
|
};
|
|
|
|
abox-rdma@18c51200 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51200 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x02>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "ion";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA2";
|
|
phandle = <0x2fc>;
|
|
};
|
|
|
|
abox-rdma@18c51300 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51300 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x03>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
samsung,asrc-id = <0x07>;
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA3";
|
|
phandle = <0x2fd>;
|
|
};
|
|
|
|
abox-rdma@18c51400 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51400 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x04>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA4";
|
|
phandle = <0x2fe>;
|
|
};
|
|
|
|
abox-rdma@18c51500 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51500 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x05>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA5";
|
|
phandle = <0x2ff>;
|
|
};
|
|
|
|
abox-rdma@18c51600 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51600 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x06>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA6";
|
|
phandle = <0x300>;
|
|
};
|
|
|
|
abox-rdma@18c51700 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51700 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x07>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA7";
|
|
phandle = <0x301>;
|
|
};
|
|
|
|
abox-rdma@18c51800 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51800 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x08>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA8";
|
|
phandle = <0x302>;
|
|
};
|
|
|
|
abox-rdma@18c51900 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51900 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x09>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA9";
|
|
phandle = <0x303>;
|
|
};
|
|
|
|
abox-rdma@18c51a00 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51a00 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x0a>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA10";
|
|
phandle = <0x304>;
|
|
};
|
|
|
|
abox-rdma@18c51b00 {
|
|
compatible = "samsung,abox-rdma";
|
|
reg = <0x00 0x18c51b00 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x0b>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX RDMA11";
|
|
phandle = <0x305>;
|
|
};
|
|
|
|
abox-wdma@18c53000 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53000 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x00>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA0";
|
|
phandle = <0x306>;
|
|
};
|
|
|
|
abox-wdma@18c53100 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53100 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x01>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "ion";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA1";
|
|
phandle = <0x307>;
|
|
};
|
|
|
|
abox-wdma@18c53200 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53200 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x02>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA2";
|
|
phandle = <0x308>;
|
|
};
|
|
|
|
abox-wdma@18c53300 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53300 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x03>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA3";
|
|
phandle = <0x309>;
|
|
};
|
|
|
|
abox-wdma@18c53400 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53400 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x04>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA4";
|
|
phandle = <0x30a>;
|
|
};
|
|
|
|
abox-wdma@18c53500 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53500 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x05>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA5";
|
|
phandle = <0x30b>;
|
|
};
|
|
|
|
abox-wdma@18c53600 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53600 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x06>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "ion";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA6";
|
|
phandle = <0x30c>;
|
|
};
|
|
|
|
abox-wdma@18c53700 {
|
|
compatible = "samsung,abox-wdma";
|
|
reg = <0x00 0x18c53700 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x07>;
|
|
samsung,type = "normal";
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "ABOX WDMA7";
|
|
phandle = <0x30d>;
|
|
};
|
|
|
|
abox-dual@18c53080 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53080 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x00>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA0 DUAL";
|
|
phandle = <0x30e>;
|
|
};
|
|
|
|
abox-dual@18c53180 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53180 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x01>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA1 DUAL";
|
|
phandle = <0x30f>;
|
|
};
|
|
|
|
abox-dual@18c53280 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53280 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x02>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA2 DUAL";
|
|
phandle = <0x310>;
|
|
};
|
|
|
|
abox-dual@18c53380 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53380 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x03>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA3 DUAL";
|
|
phandle = <0x311>;
|
|
};
|
|
|
|
abox-dual@18c53480 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53480 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x04>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA4 DUAL";
|
|
phandle = <0x312>;
|
|
};
|
|
|
|
abox-dual@18c53580 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53580 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x05>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA5 DUAL";
|
|
phandle = <0x313>;
|
|
};
|
|
|
|
abox-dual@18c53680 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53680 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x06>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA6 DUAL";
|
|
phandle = <0x314>;
|
|
};
|
|
|
|
abox-dual@18c53780 {
|
|
compatible = "samsung,abox-dual";
|
|
reg = <0x00 0x18c53780 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x07>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX WDMA7 DUAL";
|
|
phandle = <0x315>;
|
|
};
|
|
|
|
abox-ddma@18c53800 {
|
|
compatible = "samsung,abox-ddma";
|
|
reg = <0x00 0x18c53800 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x00>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX DBG0";
|
|
phandle = <0x316>;
|
|
};
|
|
|
|
abox-ddma@18c53900 {
|
|
compatible = "samsung,abox-ddma";
|
|
reg = <0x00 0x18c53900 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x01>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX DBG1";
|
|
phandle = <0x317>;
|
|
};
|
|
|
|
abox-ddma@18c53a00 {
|
|
compatible = "samsung,abox-ddma";
|
|
reg = <0x00 0x18c53a00 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x02>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX DBG2";
|
|
phandle = <0x318>;
|
|
};
|
|
|
|
abox-ddma@18c53b00 {
|
|
compatible = "samsung,abox-ddma";
|
|
reg = <0x00 0x18c53b00 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x03>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX DBG3";
|
|
phandle = <0x319>;
|
|
};
|
|
|
|
abox-ddma@18c53c00 {
|
|
compatible = "samsung,abox-ddma";
|
|
reg = <0x00 0x18c53c00 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x04>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX DBG4";
|
|
phandle = <0x31a>;
|
|
};
|
|
|
|
abox-ddma@18c53d00 {
|
|
compatible = "samsung,abox-ddma";
|
|
reg = <0x00 0x18c53d00 0x100>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x05>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX DBG5";
|
|
phandle = <0x31b>;
|
|
};
|
|
|
|
abox-uaif@18c50c00 {
|
|
compatible = "samsung,abox-uaif";
|
|
reg = <0x00 0x18c50c00 0x10>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x00>;
|
|
clocks = <0x04 0x89 0x04 0x67>;
|
|
clock-names = "bclk\0bclk_gate";
|
|
pinctrl-names = "active\0idle";
|
|
pinctrl-0 = <0x150>;
|
|
pinctrl-1 = <0x151>;
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UAIF0";
|
|
phandle = <0x31c>;
|
|
};
|
|
|
|
abox-uaif@18c50c10 {
|
|
compatible = "samsung,abox-uaif";
|
|
reg = <0x00 0x18c50c10 0x10>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x01>;
|
|
clocks = <0x04 0x8a 0x04 0x68>;
|
|
clock-names = "bclk\0bclk_gate";
|
|
pinctrl-names = "active\0idle";
|
|
pinctrl-0 = <0x152>;
|
|
pinctrl-1 = <0x153>;
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UAIF1";
|
|
phandle = <0x31d>;
|
|
};
|
|
|
|
abox-uaif@18c50c20 {
|
|
compatible = "samsung,abox-uaif";
|
|
reg = <0x00 0x18c50c20 0x10>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x02>;
|
|
clocks = <0x04 0x8b 0x04 0x69>;
|
|
clock-names = "bclk\0bclk_gate";
|
|
pinctrl-names = "active\0idle";
|
|
pinctrl-0 = <0x154>;
|
|
pinctrl-1 = <0x155>;
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UAIF2";
|
|
phandle = <0x31e>;
|
|
};
|
|
|
|
abox-uaif@18c50c30 {
|
|
compatible = "samsung,abox-uaif";
|
|
reg = <0x00 0x18c50c30 0x10>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x03>;
|
|
clocks = <0x04 0x8c 0x04 0x6a>;
|
|
clock-names = "bclk\0bclk_gate";
|
|
pinctrl-names = "active\0idle";
|
|
pinctrl-0 = <0x156>;
|
|
pinctrl-1 = <0x157>;
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UAIF3";
|
|
phandle = <0x31f>;
|
|
};
|
|
|
|
abox-uaif@18c50c40 {
|
|
compatible = "samsung,abox-uaif";
|
|
reg = <0x00 0x18c50c40 0x10>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x04>;
|
|
clocks = <0x04 0x91 0x04 0x6c>;
|
|
clock-names = "bclk\0bclk_gate";
|
|
pinctrl-names = "active\0idle";
|
|
pinctrl-0 = <0x158>;
|
|
pinctrl-1 = <0x159>;
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UAIF4";
|
|
phandle = <0x320>;
|
|
};
|
|
|
|
abox-uaif@18c50c50 {
|
|
compatible = "samsung,abox-uaif";
|
|
reg = <0x00 0x18c50c50 0x10>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x05>;
|
|
clocks = <0x04 0x92 0x04 0x6e>;
|
|
clock-names = "bclk\0bclk_gate";
|
|
pinctrl-names = "active\0idle";
|
|
pinctrl-0 = <0x15a>;
|
|
pinctrl-1 = <0x15b>;
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UAIF5";
|
|
phandle = <0x321>;
|
|
};
|
|
|
|
abox-uaif@18c50c60 {
|
|
compatible = "samsung,abox-uaif";
|
|
reg = <0x00 0x18c50c60 0x10>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x06>;
|
|
clocks = <0x04 0x95 0x04 0x71 0x04 0x64>;
|
|
clock-names = "bclk\0bclk_gate\0mux";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UAIF6";
|
|
phandle = <0x322>;
|
|
};
|
|
|
|
abox-dsif@18c50cf0 {
|
|
compatible = "samsung,abox-dsif";
|
|
reg = <0x00 0x18c50cf0 0x10>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x07>;
|
|
clocks = <0x04 0x88 0x04 0x66>;
|
|
clock-names = "bclk\0bclk_gate";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX DSIF";
|
|
phandle = <0x323>;
|
|
};
|
|
|
|
abox-udma-rd@18c5c100 {
|
|
compatible = "samsung,abox-udma-rd";
|
|
reg = <0x00 0x18c5c100 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x00>;
|
|
samsung,buffer_type = "ram";
|
|
samsung,buffer-address = <0x03 0x10ffd000 0x2000>;
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UDMA RD0";
|
|
phandle = <0x324>;
|
|
};
|
|
|
|
abox-udma-rd@18c5c200 {
|
|
compatible = "samsung,abox-udma-rd";
|
|
reg = <0x00 0x18c5c200 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x01>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UDMA RD1";
|
|
phandle = <0x325>;
|
|
};
|
|
|
|
abox-udma-wr@18c5c700 {
|
|
compatible = "samsung,abox-udma-wr";
|
|
reg = <0x00 0x18c5c700 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x00>;
|
|
samsung,buffer_type = "ram";
|
|
samsung,buffer-address = <0x03 0x10ff4000 0x9000>;
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UDMA WR0";
|
|
phandle = <0x326>;
|
|
};
|
|
|
|
abox-udma-wr@18c5c800 {
|
|
compatible = "samsung,abox-udma-wr";
|
|
reg = <0x00 0x18c5c800 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x01>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UDMA WR1";
|
|
phandle = <0x327>;
|
|
};
|
|
|
|
abox-udma-wr-dual@18c5c780 {
|
|
compatible = "samsung,abox-udma-wr-dual";
|
|
reg = <0x00 0x18c5c780 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x00>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UDMA WR0 DUAL";
|
|
phandle = <0x328>;
|
|
};
|
|
|
|
abox-udma-wr-dual@18c5c880 {
|
|
compatible = "samsung,abox-udma-wr-dual";
|
|
reg = <0x00 0x18c5c880 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x01>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UDMA WR1 DUAL";
|
|
phandle = <0x329>;
|
|
};
|
|
|
|
abox-udma-wr-debug@18c5cd00 {
|
|
compatible = "samsung,abox-udma-wr-debug";
|
|
reg = <0x00 0x18c5cd00 0x80>;
|
|
reg-names = "sfr";
|
|
samsung,id = <0x00>;
|
|
samsung,buffer_type = "dma";
|
|
#sound-dai-cells = <0x00>;
|
|
sound-name-prefix = "ABOX UDMA DBG0";
|
|
phandle = <0x32a>;
|
|
};
|
|
|
|
abox-effect@18e2e000 {
|
|
compatible = "samsung,abox-effect";
|
|
reg = <0x00 0x18e2e000 0x1000>;
|
|
reg-names = "reg";
|
|
phandle = <0x32b>;
|
|
};
|
|
|
|
abox-debug@0 {
|
|
compatible = "samsung,abox-debug";
|
|
memory-region = <0x15c 0x15d>;
|
|
reg = <0x00 0x00 0x00>;
|
|
phandle = <0x32c>;
|
|
};
|
|
|
|
abox-vss@0 {
|
|
compatible = "samsung,abox-vss";
|
|
samsung,magic-offset = <0x700000>;
|
|
reg = <0x00 0x00 0x00>;
|
|
phandle = <0x32d>;
|
|
};
|
|
|
|
abox-tplg@0 {
|
|
compatible = "samsung,abox-tplg";
|
|
reg = <0x00 0x00 0x00>;
|
|
sound-name-prefix = "ABOX";
|
|
phandle = <0x32e>;
|
|
};
|
|
|
|
ext-bin@0 {
|
|
compatible = "samsung,abox-ext-bin";
|
|
samsung,name = "calliope2.dt";
|
|
samsung,area = <0x01>;
|
|
samsung,offset = <0x11fe000>;
|
|
phandle = <0x32f>;
|
|
};
|
|
|
|
ext-bin@1 {
|
|
compatible = "samsung,abox-ext-bin";
|
|
samsung,name = "usbout.bin";
|
|
samsung,area = <0x01>;
|
|
samsung,offset = <0x1100000>;
|
|
phandle = <0x330>;
|
|
};
|
|
|
|
ext-bin@2 {
|
|
compatible = "samsung,abox-ext-bin";
|
|
samsung,name = "usbin.bin";
|
|
samsung,area = <0x01>;
|
|
samsung,offset = <0x1110000>;
|
|
phandle = <0x331>;
|
|
};
|
|
|
|
ext-bin@3 {
|
|
compatible = "samsung,abox-ext-bin";
|
|
samsung,name = "txse1.bin";
|
|
samsung,area = <0x01>;
|
|
samsung,offset = <0x1800000>;
|
|
phandle = <0x332>;
|
|
};
|
|
|
|
ext-bin@4 {
|
|
compatible = "samsung,abox-ext-bin";
|
|
samsung,name = "rxse.bin";
|
|
samsung,area = <0x01>;
|
|
samsung,offset = <0x1e4f000>;
|
|
phandle = <0x333>;
|
|
};
|
|
|
|
ext-bin@5 {
|
|
compatible = "samsung,abox-ext-bin";
|
|
samsung,name = "txse2.bin";
|
|
samsung,area = <0x01>;
|
|
samsung,offset = <0x19e4000>;
|
|
phandle = <0x334>;
|
|
};
|
|
};
|
|
|
|
mailbox@0x155a0000 {
|
|
compatible = "samsung,mailbox-asoc";
|
|
reg = <0x00 0x155a0000 0x1000>;
|
|
reg-names = "sfr";
|
|
interrupts = <0x00 0x270 0x04>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x01>;
|
|
phandle = <0x16b>;
|
|
};
|
|
|
|
vts@0x15510000 {
|
|
compatible = "samsung,vts";
|
|
sicd-base = <0x2053400>;
|
|
sicd-size = <0x400>;
|
|
reg = <0x00 0x15510000 0x1004 0x00 0x15420000 0x10010 0x00 0x15570000 0x08 0x00 0x155d0000 0x08 0x00 0x15600000 0x104000 0x00 0x155f0000 0x50 0x00 0x153d0000 0x08 0x00 0x153e0000 0x08 0x00 0x153f0000 0x08>;
|
|
reg-names = "sfr\0baaw\0dmic\0dmic1\0sram\0gpr\0intmem_code\0intmem_data\0intmem_pcm";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
ranges;
|
|
pinctrl-names = "dmic_default\0amic_default\0dmic1_default\0s_lif_0_idle\0s_lif_1_default\0s_lif_1_idle\0s_lif_2_default\0s_lif_2_idle\0idle\0default";
|
|
pinctrl-0 = <0x15e 0x15f>;
|
|
pinctrl-1 = <0x160 0x161>;
|
|
pinctrl-2 = <0x160 0x162>;
|
|
pinctrl-3 = <0x163 0x164>;
|
|
pinctrl-4 = <0x160 0x162>;
|
|
pinctrl-5 = <0x165 0x166>;
|
|
pinctrl-6 = <0x167 0x168>;
|
|
pinctrl-7 = <0x169 0x16a>;
|
|
pinctrl-8 = <0x163 0x165 0x164>;
|
|
pinctrl-9;
|
|
power-domains = <0x13f>;
|
|
clocks = <0x04 0x943 0x04 0x946 0x04 0x937 0x04 0x938 0x04 0x939>;
|
|
clock-names = "rco\0mux_dmic_if\0dmic_if\0dmic_sync\0sysclk";
|
|
mailbox = <0x16b>;
|
|
#sound-dai-cells = <0x01>;
|
|
sound-name-prefix = "VTS";
|
|
interrupt-parent = <0x16b>;
|
|
interrupts = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0b 0x0f>;
|
|
interrupt-names = "error\0boot_completed\0ipc_received\0voice_triggered\0trigger_period_elapsed\0record_period_elapsed\0debuglog_bufzero\0debuglog_bufone\0audio_dump\0log_dump\0slif_dump\0cp_wakeup";
|
|
samsung,imgloader-vts-support;
|
|
samsung,fw-id = <0x00>;
|
|
phandle = <0x16c>;
|
|
|
|
vts_dma@0 {
|
|
compatible = "samsung,vts-dma";
|
|
vts = <0x16c>;
|
|
id = <0x00>;
|
|
type = "vts-trigger";
|
|
pinctrl-names = "default";
|
|
pinctrl-0;
|
|
phandle = <0x335>;
|
|
};
|
|
|
|
vts_dma@1 {
|
|
compatible = "samsung,vts-dma";
|
|
vts = <0x16c>;
|
|
id = <0x01>;
|
|
type = "vts-record";
|
|
pinctrl-names = "default";
|
|
pinctrl-0;
|
|
phandle = <0x336>;
|
|
};
|
|
|
|
vts_s_lif@0x15340000 {
|
|
compatible = "samsung,vts-s-lif";
|
|
status = "okay";
|
|
vts = <0x16c>;
|
|
id = <0x00>;
|
|
reg = <0x00 0x15340000 0x400 0x00 0x15511010 0x10 0x00 0x15350000 0x20 0x00 0x15360000 0x20 0x00 0x15370000 0x20>;
|
|
reg-names = "sfr\0sys_sfr\0dmic_aud0\0dmic_aud1\0dmic_aud2";
|
|
pinctrl-names = "default";
|
|
pinctrl-0;
|
|
clocks = <0x04 0x942 0x04 0x940 0x04 0x941 0x04 0x944 0x04 0x945 0x04 0x93a 0x04 0x93b 0x04 0x93c>;
|
|
clock-names = "rco\0aud0\0aud1\0mux_dmic_aud\0mux_serial_lif\0dmic_aud\0dmic_aud_div2\0serial_lif";
|
|
#sound-dai-cells = <0x01>;
|
|
phandle = <0x337>;
|
|
};
|
|
};
|
|
|
|
dp_dma {
|
|
#sound-dai-cells = <0x01>;
|
|
compatible = "samsung,displayport-adma";
|
|
memory-region = <0x16d>;
|
|
phandle = <0x338>;
|
|
|
|
dp_dma@0 {
|
|
compatible = "samsung,dp-dma";
|
|
id = <0x00>;
|
|
dmas = <0x16e 0x1c>;
|
|
dma-names = "tx";
|
|
fifo_addr = <0x10ab5818>;
|
|
sound-name-prefix = "DP AUDIO0";
|
|
phandle = <0x339>;
|
|
};
|
|
|
|
dp_dma@1 {
|
|
compatible = "samsung,dp-dma";
|
|
id = <0x01>;
|
|
dmas = <0x16e 0x1d>;
|
|
dma-names = "tx";
|
|
fifo_addr = <0x10ab6818>;
|
|
sound-name-prefix = "DP AUDIO1";
|
|
phandle = <0x33a>;
|
|
};
|
|
};
|
|
|
|
fixed-rate-clocks {
|
|
|
|
oscclk {
|
|
compatible = "samsung,exynos2100-oscclk";
|
|
clock-frequency = <0x18cba80>;
|
|
};
|
|
};
|
|
|
|
ext_26m {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0x00>;
|
|
clock-frequency = <0x18cba80>;
|
|
clock-output-names = "ext-26m";
|
|
phandle = <0x170>;
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "console=ram no_console_suspend androidboot.boot_devices=13100000.ufs clocksource=arch_sys_counter androidboot.debug_level=0x4948 firmware_class.path=/vendor/firmware nr_cpus=8 androidboot.dtbo_idx=0 androidboot.hardware=exynos2100 log_buf_len=256K irqaffinity=0 loop.max_part=7 rcupdate.rcu_expedited=1 s3c2410_wdt.tmr_atboot=1 s3c2410_wdt.tmr_margin=80 printk.devkmsg=on swiotlb=noforce";
|
|
linux,initrd-start = <0x84000000>;
|
|
linux,initrd-end = <0x841fffff>;
|
|
phandle = <0x33b>;
|
|
};
|
|
|
|
interrupt-controller@10200000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <0x03>;
|
|
interrupt-controller;
|
|
reg = <0x00 0x10200000 0x10000 0x00 0x10240000 0x200000>;
|
|
interrupts = <0x01 0x09 0x04>;
|
|
class0-cpus = "0-3";
|
|
class1-cpus = "4-7";
|
|
phandle = <0x01>;
|
|
};
|
|
|
|
clock-controller@0x1A330000 {
|
|
compatible = "samsung,exynos2100-clock";
|
|
reg = <0x00 0x1a330000 0x8000 0x00 0x18c00000 0x1000 0x00 0x1a030000 0x1000 0x00 0x1d040000 0x1000 0x00 0x1d050000 0x1000 0x00 0x1d060000 0x1000 0x00 0x1d030000 0x1000 0x00 0x10020000 0x1000>;
|
|
#clock-cells = <0x01>;
|
|
acpm-ipc-channel = <0x00>;
|
|
phandle = <0x04>;
|
|
};
|
|
|
|
arm-pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
interrupts = <0x01 0x07 0xff04>;
|
|
};
|
|
|
|
chipid@10000000 {
|
|
compatible = "samsung,exynos2100-chipid";
|
|
reg = <0x00 0x10000000 0x100>;
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <0x01 0x0d 0xff08 0x01 0x0e 0xff08 0x01 0x0b 0xff08 0x01 0x0a 0xff08>;
|
|
clock-frequency = <0x18cba80>;
|
|
use-physical-timer;
|
|
};
|
|
|
|
exynos-reboot {
|
|
compatible = "samsung,exynos-reboot";
|
|
samsung,syscon-phandle = <0xbf>;
|
|
shutdown-offset = <0x30c>;
|
|
shutdown-trigger = <0x100>;
|
|
reboot-offset = <0x3c00>;
|
|
reboot-trigger = <0x02>;
|
|
reboot-cmd-offset = <0x810>;
|
|
status = "okay";
|
|
};
|
|
|
|
mct@10040000 {
|
|
compatible = "samsung,exynos4210-mct";
|
|
reg = <0x00 0x10040000 0x800>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x01>;
|
|
interrupt-parent = <0x16f>;
|
|
interrupts = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b>;
|
|
clocks = <0x170 0x170>;
|
|
clock-names = "fin_pll\0mct";
|
|
|
|
mct-map {
|
|
#interrupt-cells = <0x01>;
|
|
#address-cells = <0x00>;
|
|
#size-cells = <0x00>;
|
|
interrupt-map = <0x00 0x01 0x00 0x3af 0x04 0x01 0x01 0x00 0x3b0 0x04 0x02 0x01 0x00 0x3b1 0x04 0x03 0x01 0x00 0x3b2 0x04 0x04 0x01 0x00 0x3b3 0x04 0x05 0x01 0x00 0x3b4 0x04 0x06 0x01 0x00 0x3b5 0x04 0x07 0x01 0x00 0x3b6 0x04 0x08 0x01 0x00 0x3b7 0x04 0x09 0x01 0x00 0x3b8 0x04 0x0a 0x01 0x00 0x3b9 0x04 0x0b 0x01 0x00 0x3ba 0x04>;
|
|
phandle = <0x16f>;
|
|
};
|
|
};
|
|
|
|
rtc@15920000 {
|
|
compatible = "samsung,exynos8-rtc";
|
|
reg = <0x00 0x15920000 0x100>;
|
|
interrupts = <0x00 0x14 0x04 0x00 0x15 0x04>;
|
|
status = "disabled";
|
|
phandle = <0x33c>;
|
|
};
|
|
|
|
watchdog_cl0@10050000 {
|
|
compatible = "samsung,exynos2100-v1-wdt";
|
|
reg = <0x00 0x10050000 0x100>;
|
|
interrupts = <0x00 0x3ad 0x04>;
|
|
clocks = <0x04 0x01 0x04 0x7dd>;
|
|
clock-names = "rate_watchdog\0gate_watchdog";
|
|
timeout-sec = <0x1e>;
|
|
samsung,syscon-phandle = <0xbf>;
|
|
index = <0x00>;
|
|
status = "okay";
|
|
};
|
|
|
|
watchdog_cl1@10060000 {
|
|
compatible = "samsung,exynos2100-v2-wdt";
|
|
reg = <0x00 0x10060000 0x100>;
|
|
interrupts = <0x00 0x3ae 0x04>;
|
|
clocks = <0x04 0x01 0x04 0x7de>;
|
|
clock-names = "rate_watchdog\0gate_watchdog";
|
|
timeout-sec = <0x1e>;
|
|
samsung,syscon-phandle = <0xbf>;
|
|
index = <0x01>;
|
|
use_multistage_wdt;
|
|
status = "okay";
|
|
};
|
|
|
|
exynos-pmu {
|
|
compatible = "samsung,exynos-pmu";
|
|
samsung,syscon-phandle = <0xbf>;
|
|
reg = <0x00 0x15860000 0x10000>;
|
|
reg-names = "pmu_alive";
|
|
};
|
|
|
|
system-controller@15860000 {
|
|
compatible = "samsung,exynos991-pmu\0syscon";
|
|
reg = <0x00 0x15860000 0x10000>;
|
|
phandle = <0xbf>;
|
|
};
|
|
|
|
exynos-pm {
|
|
compatible = "samsung,exynos-pm";
|
|
reg = <0x00 0x14ec0000 0x1000 0x00 0x10200200 0x100 0x00 0x159a0000 0x1000>;
|
|
reg-names = "gpio_alive_base\0gicd_ispendrn_base\0sysreg_vgpio2pmu";
|
|
num-eint = <0x22>;
|
|
num-gic = <0x1d>;
|
|
suspend_mode_idx = <0x08>;
|
|
suspend_psci_idx = <0x400>;
|
|
wakeup_stat_offset = <0x3b50 0x3b54>;
|
|
wakeup_int_en_offset = <0x3b44 0x3b64>;
|
|
wakeup_int_en = <0x52f6f 0x9b>;
|
|
usbl2_wakeup_int_en = <0x00 0x18>;
|
|
eint_wakeup_mask_offset = <0x60c 0x610>;
|
|
wakeup-stat-eint = <0x0d>;
|
|
wakeup-stat-rtc = <0x00>;
|
|
vgpio_wakeup_inten = <0x19>;
|
|
vgpio_wakeup_inten_offset = <0x288>;
|
|
wake_lock = <0x00>;
|
|
};
|
|
|
|
exynos-powermode {
|
|
reg = <0x00 0x159a0000 0x1000>;
|
|
reg-names = "sysreg_vgpio2pmu";
|
|
eint-wakeup-mask = <0x60c>;
|
|
eint-wakeup-mask2 = <0x610>;
|
|
|
|
wakeup-masks {
|
|
|
|
wakeup-mask {
|
|
mask = <0x7ff81aff 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x52f6f 0x52f6f 0x52f6f 0x00 0x00 0x52f6f>;
|
|
mask-offset = <0x3b44>;
|
|
stat-offset = <0x3b50>;
|
|
};
|
|
|
|
wakeup-mask2 {
|
|
mask = <0x1f 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xfb 0xfb 0xfb 0x00 0x00 0xfb>;
|
|
mask-offset = <0x3b64>;
|
|
stat-offset = <0x3b54>;
|
|
};
|
|
};
|
|
|
|
vgpio-wakeup-inten {
|
|
mask = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x19 0x19 0x19 0x00 0x19 0x19>;
|
|
inten-offset = <0x288>;
|
|
};
|
|
};
|
|
|
|
exynos_flexpmu_dbg {
|
|
compatible = "samsung,exynos-flexpmu-dbg";
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
data-base = <0x2053400>;
|
|
data-size = <0x400>;
|
|
mid-dvs-en = <0x00>;
|
|
reg = <0x00 0x15920000 0x1000>;
|
|
};
|
|
|
|
iommu_group_dpu {
|
|
compatible = "samsung,sysmmu-group";
|
|
phandle = <0xbe>;
|
|
};
|
|
|
|
iommu_group_mfc {
|
|
compatible = "samsung,sysmmu-group";
|
|
phandle = <0x146>;
|
|
};
|
|
|
|
iommu_group_is {
|
|
compatible = "samsung,sysmmu-group";
|
|
phandle = <0x33d>;
|
|
};
|
|
|
|
iommu_group_g2d {
|
|
compatible = "samsung,sysmmu-group";
|
|
phandle = <0x33e>;
|
|
};
|
|
|
|
iommu_group_mscl_smfc {
|
|
compatible = "samsung,sysmmu-group";
|
|
phandle = <0x149>;
|
|
};
|
|
|
|
iommu_group_aud {
|
|
compatible = "samsung,sysmmu-group";
|
|
phandle = <0x14d>;
|
|
};
|
|
|
|
iommu_group_npu {
|
|
compatible = "samsung,sysmmu-group";
|
|
phandle = <0x33f>;
|
|
};
|
|
|
|
iommu_group_vpc {
|
|
compatible = "samsung,sysmmu-group";
|
|
phandle = <0x340>;
|
|
};
|
|
|
|
amba {
|
|
#address-cells = <0x02>;
|
|
#size-cells = <0x01>;
|
|
compatible = "arm,amba-bus";
|
|
interrupt-parent = <0x01>;
|
|
ranges;
|
|
|
|
pdma0@1A510000 {
|
|
compatible = "arm,pl330\0arm,primecell";
|
|
reg = <0x00 0x1a510000 0x1000>;
|
|
interrupts = <0x00 0x26 0x04>;
|
|
clocks = <0x04 0x100>;
|
|
clock-names = "apb_pclk";
|
|
#dma-cells = <0x01>;
|
|
#dma-channels = <0x08>;
|
|
#dma-requests = <0x20>;
|
|
#dma-multi-irq = <0x01>;
|
|
dma-arwrapper = <0x1a514400 0x1a514420 0x1a514440 0x1a514460 0x1a514480 0x1a5144a0 0x1a5144c0 0x1a5144e0>;
|
|
dma-awwrapper = <0x1a514404 0x1a514424 0x1a514444 0x1a514464 0x1a514484 0x1a5144a4 0x1a5144c4 0x1a5144e4>;
|
|
dma-instwrapper = <0x1a514500>;
|
|
dma-mask-bit = <0x24>;
|
|
coherent-mask-bit = <0x24>;
|
|
phandle = <0x16e>;
|
|
};
|
|
};
|
|
|
|
exynos-sci_dbg {
|
|
compatible = "samsung,exynos-sci_dbg";
|
|
memory-region = <0x171>;
|
|
};
|
|
|
|
exynos-sci {
|
|
compatible = "samsung,exynos-sci";
|
|
memory-region = <0x172>;
|
|
interrupts = <0x00 0x9a 0x04 0x00 0x9b 0x04>;
|
|
nr_irq = <0x02>;
|
|
acpm-ipc-channel = <0x0b>;
|
|
use_init_llc_region = <0x01>;
|
|
initial_llc_region = <0x01>;
|
|
ret_enable = <0x00>;
|
|
llc_enable = <0x01>;
|
|
hfreq_rate = <0x1e>;
|
|
freq_th = <0x1ef1e0>;
|
|
on_time_th = <0xbebc200>;
|
|
off_time_th = "SrN";
|
|
llc_gov_en = <0x01>;
|
|
region_name = "LLC_REGION_DISABLE\0LLC_REGION_CPU\0LLC_REGION_CALL\0LLC_REGION_OFFLOAD\0LLC_REGION_CPD2\0LLC_REGION_CPCPU\0LLC_REGION_DPU\0LLC_REGION_MFC0_INT\0LLC_REGION_MFC1_INT\0LLC_REGION_MFC0_DPB\0LLC_REGION_MFC1_DPB\0LLC_REGION_GPU\0LLC_REGION_NPU0\0LLC_REGION_NPU1\0LLC_REGION_NPU2\0LLC_REGION_DSP0\0LLC_REGION_DSP1\0LLC_REGION_CAM_MCFP\0LLC_REGION_CAM_CSIS";
|
|
region_priority = <0x00 0x01 0x02 0x03 0x04 0x0b 0x05 0x08 0x09 0x06 0x07 0x0a 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12>;
|
|
cpu_min_region = <0x00>;
|
|
devfreq = <0x173>;
|
|
};
|
|
|
|
exynos-bcmdbg {
|
|
compatible = "samsung,exynos-bcm_dbg";
|
|
memory-region = <0x174>;
|
|
pd-name = "pd-trex\0pd-aud\0pd-csis\0pd-dns\0pd-dpuf0\0pd-dpuf1\0pd-g2d\0pd-hsi0\0pd-lme\0pd-m2m\0pd-mcfp0\0pd-mcfp1\0pd-mcsc\0pd-mfc0\0pd-mfc1\0pd-npus\0pd-ssp\0pd-taa\0pd-vpc\0pd-yuvpp";
|
|
max_define_event = <0x08>;
|
|
define_events = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x04 0x02 0x26 0x24 0x05 0x03 0x27 0x25 0x02 0x04 0x00 0x24 0x24 0x05 0x01 0x25 0x25 0x03 0x04 0x02 0x04 0x26 0x05 0x03 0x05 0x27 0x04 0x02 0x10 0x10 0x26 0x03 0x11 0x11 0x27 0x05 0x04 0x12 0x12 0x06 0x05 0x13 0x13 0x14 0x06 0x02 0x15 0x18 0x1b 0x03 0x16 0x19 0x1c 0x07 0x04 0x05 0x20 0x23 0x00 0x01 0x24 0x25>;
|
|
default_define_event = <0x01>;
|
|
define_filter_id = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x00 0x00 0x03 0x00 0x00 0x04 0x00 0x00 0x05 0x00 0x00 0x06 0x00 0x00 0x07 0x00 0x00>;
|
|
define_filter_id_active = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x04 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
define_filter_other_0 = <0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x04 0x00 0x00 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x07 0x00 0x00 0x00>;
|
|
define_filter_other_1 = <0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x04 0x00 0x00 0x00 0x05 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x07 0x00 0x00 0x00>;
|
|
define_filter_other_active = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x04 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x06 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
define_sample_id = <0x00 0x00 0x00 0x01 0x00 0x00 0x02 0x00 0x00 0x03 0x00 0x00 0x04 0x00 0x00 0x05 0x00 0x00 0x06 0x00 0x00 0x07 0x00 0x00>;
|
|
define_sample_id_enable = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x01 0x00 0x00 0x00 0x01 0x00 0x02 0x00 0x00 0x01 0x00 0x00 0x00 0x01 0x00 0x03 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01 0x04 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01 0x05 0x00 0x00 0x01 0x00 0x00 0x00 0x01 0x00 0x06 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
|
|
bcm_cnt_nr = <0x08>;
|
|
bcm_ip_nr = <0x47>;
|
|
bcm_ip_print_nr = <0x0a>;
|
|
initial_run_bcm_ip = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46>;
|
|
initial_bcm_run = <0x00>;
|
|
initial_period = <0x01>;
|
|
initial_bcm_mode = <0x00>;
|
|
available_stop_owner = <0x00 0x01 0x02 0x03>;
|
|
buff_size = <0x200000>;
|
|
glb_auto_en = <0x01>;
|
|
bcm_calc_num_ip = <0x04>;
|
|
bcm_calc_ip_idx = <0x01 0x03 0x3e 0x43>;
|
|
bcm_calc_ip_name = "CPUCL0_0\0G3D0\0IRPS0\0MIF0";
|
|
bcm_calc_ip_cnt = <0x02 0x04 0x04 0x04>;
|
|
bcm_calc_bus_width = <0x20 0x10 0x20 0x10>;
|
|
bcm_calc_sample_time = <0x32>;
|
|
perf_define_event = <0x07>;
|
|
|
|
ipc_bcm_event {
|
|
plugin-len = <0x05>;
|
|
plugin-name = "BCM";
|
|
};
|
|
};
|
|
|
|
samsung,memlogger {
|
|
compatible = "samsung,memlogger";
|
|
memory-region = <0x175>;
|
|
samsung,bl-node = <0x176>;
|
|
phandle = <0x341>;
|
|
};
|
|
|
|
samsung,memlog_policy {
|
|
samsung,log-level = <0x04>;
|
|
samsung,file-default-status = <0x01>;
|
|
samsung,mem-constraint = <0x00>;
|
|
samsung,mem-to-file-allow = <0x01>;
|
|
phandle = <0x342>;
|
|
};
|
|
|
|
__symbols__ {
|
|
reserved_memory = "/reserved-memory";
|
|
ect_binary = "/reserved-memory/ect_binary";
|
|
dss_rmem = "/reserved-memory/debug_snapshot";
|
|
header = "/reserved-memory/debug_snapshot/header";
|
|
log_kernel = "/reserved-memory/debug_snapshot/log_kernel";
|
|
log_platform = "/reserved-memory/debug_snapshot/log_platform";
|
|
log_s2d = "/reserved-memory/debug_snapshot/log_s2d";
|
|
log_first = "/reserved-memory/debug_snapshot/log_first";
|
|
log_arrdumpreset = "/reserved-memory/debug_snapshot/log_arrdumpreset";
|
|
log_arrdumppanic = "/reserved-memory/debug_snapshot/log_arrdumppanic";
|
|
log_kevents = "/reserved-memory/debug_snapshot/log_kevents";
|
|
log_last = "/reserved-memory/debug_snapshot/log_last";
|
|
log_bcm = "/reserved-memory/log_bcm";
|
|
log_llc = "/reserved-memory/log_llc";
|
|
log_ppc = "/reserved-memory/log_ppc";
|
|
seclog_mem = "/reserved-memory/seclog_mem";
|
|
s2mpu_table = "/reserved-memory/s2mpu_table";
|
|
cp_rmem = "/reserved-memory/cp_rmem";
|
|
cp_rmem1 = "/reserved-memory/cp_rmem1";
|
|
dummy_heap = "/reserved-memory/dummy_heap";
|
|
abox_dbg = "/reserved-memory/abox-dbg";
|
|
abox_slog = "/reserved-memory/abox-slog";
|
|
abox_rmem = "/reserved-memory/abox-rmem";
|
|
abox_rdma_compr = "/reserved-memory/abox-rdma-compr";
|
|
dp_ado_rmem = "/reserved-memory/dpado-rmem";
|
|
memlog_mem = "/reserved-memory/memlog_region";
|
|
dsp_shmem = "/reserved-memory/dsp-shmem";
|
|
dsp_master_rmem = "/reserved-memory/dsp-master-rmem";
|
|
mfc_fw_rmem = "/reserved-memory/mfc_fw_rmem";
|
|
crypto = "/reserved-memory/crypto";
|
|
vstream = "/reserved-memory/vstream";
|
|
vframe = "/reserved-memory/vframe";
|
|
vscaler = "/reserved-memory/vscaler";
|
|
gpu_buffer = "/reserved-memory/gpu_buffer";
|
|
memlog_bl_base = "/memlog_bl_base";
|
|
pinctrl_0 = "/pinctrl@15850000";
|
|
gpq0 = "/pinctrl@15850000/gpq0";
|
|
gpq1 = "/pinctrl@15850000/gpq1";
|
|
gpq2 = "/pinctrl@15850000/gpq2";
|
|
gpb5 = "/pinctrl@15850000/gpb5";
|
|
uart1_bus_single = "/pinctrl@15850000/uart1-bus";
|
|
uart1_bus_rts = "/pinctrl@15850000/uart1-bus-rts";
|
|
uart1_bus_tx_dat = "/pinctrl@15850000/uart1-bus-tx-dat";
|
|
uart1_bus_tx_con = "/pinctrl@15850000/uart1-bus-tx-con";
|
|
aud_i2s5_bus = "/pinctrl@15850000/aud-i2s5-bus";
|
|
aud_i2s5_idle = "/pinctrl@15850000/aud-i2s5-idle";
|
|
pinctrl_1 = "/pinctrl@14E30000";
|
|
gpm0 = "/pinctrl@14E30000/gpm0";
|
|
gpm1 = "/pinctrl@14E30000/gpm1";
|
|
gpm2 = "/pinctrl@14E30000/gpm2";
|
|
gpm3 = "/pinctrl@14E30000/gpm3";
|
|
gpm4 = "/pinctrl@14E30000/gpm4";
|
|
gpm5 = "/pinctrl@14E30000/gpm5";
|
|
gpm6 = "/pinctrl@14E30000/gpm6";
|
|
gpm7 = "/pinctrl@14E30000/gpm7";
|
|
gpm8 = "/pinctrl@14E30000/gpm8";
|
|
gpm9 = "/pinctrl@14E30000/gpm9";
|
|
gpm10 = "/pinctrl@14E30000/gpm10";
|
|
gpm11 = "/pinctrl@14E30000/gpm11";
|
|
gpm12 = "/pinctrl@14E30000/gpm12";
|
|
gpm13 = "/pinctrl@14E30000/gpm13";
|
|
gpm14 = "/pinctrl@14E30000/gpm14";
|
|
gpm15 = "/pinctrl@14E30000/gpm15";
|
|
gpm16 = "/pinctrl@14E30000/gpm16";
|
|
gpm17 = "/pinctrl@14E30000/gpm17";
|
|
gpm18 = "/pinctrl@14E30000/gpm18";
|
|
gpm19 = "/pinctrl@14E30000/gpm19";
|
|
gpm20 = "/pinctrl@14E30000/gpm20";
|
|
gpm21 = "/pinctrl@14E30000/gpm21";
|
|
gpm22 = "/pinctrl@14E30000/gpm22";
|
|
gpm23 = "/pinctrl@14E30000/gpm23";
|
|
gpm24 = "/pinctrl@14E30000/gpm24";
|
|
gpm25 = "/pinctrl@14E30000/gpm25";
|
|
hsi2c38_bus = "/pinctrl@14E30000/hsi2c38-bus";
|
|
hsi2c39_bus = "/pinctrl@14E30000/hsi2c39-bus";
|
|
hsi2c40_bus = "/pinctrl@14E30000/hsi2c40-bus";
|
|
hsi2c41_bus = "/pinctrl@14E30000/hsi2c41-bus";
|
|
hsi2c42_bus = "/pinctrl@14E30000/hsi2c42-bus";
|
|
hsi2c43_bus = "/pinctrl@14E30000/hsi2c43-bus";
|
|
hsi2c44_bus = "/pinctrl@14E30000/hsi2c44-bus";
|
|
hsi2c45_bus = "/pinctrl@14E30000/hsi2c45-bus";
|
|
spi19_bus = "/pinctrl@14E30000/spi19-bus";
|
|
spi19_cs = "/pinctrl@14E30000/spi19-cs";
|
|
spi19_cs_func = "/pinctrl@14E30000/spi19-cs-func";
|
|
spi20_bus = "/pinctrl@14E30000/spi20-bus";
|
|
spi20_cs = "/pinctrl@14E30000/spi20-cs";
|
|
spi20_cs_func = "/pinctrl@14E30000/spi20-cs-func";
|
|
spi21_bus = "/pinctrl@14E30000/spi21-bus";
|
|
spi21_cs = "/pinctrl@14E30000/spi21-cs";
|
|
spi21_cs_func = "/pinctrl@14E30000/spi21-cs-func";
|
|
spi22_bus = "/pinctrl@14E30000/spi22-bus";
|
|
spi22_cs = "/pinctrl@14E30000/spi22-cs";
|
|
spi22_cs_func = "/pinctrl@14E30000/spi22-cs-func";
|
|
uart21_bus_single = "/pinctrl@14E30000/uart21-bus";
|
|
uart21_bus_dual = "/pinctrl@14E30000/uart21-bus-dual";
|
|
uart22_bus_single = "/pinctrl@14E30000/uart22-bus";
|
|
uart22_bus_dual = "/pinctrl@14E30000/uart22-bus-dual";
|
|
uart23_bus_single = "/pinctrl@14E30000/uart23-bus";
|
|
uart23_bus_dual = "/pinctrl@14E30000/uart23-bus-dual";
|
|
uart24_bus_single = "/pinctrl@14E30000/uart24-bus";
|
|
uart24_bus_dual = "/pinctrl@14E30000/uart24-bus-dual";
|
|
pinctrl_2 = "/pinctrl@14EC0000";
|
|
gpa0 = "/pinctrl@14EC0000/gpa0";
|
|
gpa1 = "/pinctrl@14EC0000/gpa1";
|
|
gpa2 = "/pinctrl@14EC0000/gpa2";
|
|
gpa3 = "/pinctrl@14EC0000/gpa3";
|
|
gpa4 = "/pinctrl@14EC0000/gpa4";
|
|
pinctrl_3 = "/pinctrl@11040000";
|
|
gpf0 = "/pinctrl@11040000/gpf0";
|
|
gpf1 = "/pinctrl@11040000/gpf1";
|
|
gpf2 = "/pinctrl@11040000/gpf2";
|
|
pcie0_clkreq = "/pinctrl@11040000/pcie0_clkreq";
|
|
pcie0_perst = "/pinctrl@11040000/pcie0_perst";
|
|
pcie1_clkreq = "/pinctrl@11040000/pcie1_clkreq";
|
|
pcie1_perst = "/pinctrl@11040000/pcie1_perst";
|
|
ufs_rst_n = "/pinctrl@11040000/ufs-rst-n";
|
|
ufs_refclk_out = "/pinctrl@11040000/ufs-refclk-out";
|
|
sd2_clk = "/pinctrl@11040000/sd2-clk";
|
|
sd2_cmd = "/pinctrl@11040000/sd2-cmd";
|
|
sd2_bus1 = "/pinctrl@11040000/sd2-bus-width1";
|
|
sd2_bus4 = "/pinctrl@11040000/sd2-bus-width4";
|
|
sd2_clk_fast_slew_rate_1x = "/pinctrl@11040000/sd2-clk_fast_slew_rate_1x";
|
|
sd2_clk_fast_slew_rate_1_5x = "/pinctrl@11040000/sd2-clk_fast_slew_rate_1_5x";
|
|
sd2_clk_fast_slew_rate_2x = "/pinctrl@11040000/sd2-clk_fast_slew_rate_2x";
|
|
sd2_clk_fast_slew_rate_2_5x = "/pinctrl@11040000/sd2-clk_fast_slew_rate_2_5x";
|
|
sd2_clk_fast_slew_rate_3x = "/pinctrl@11040000/sd2-clk_fast_slew_rate_3x";
|
|
sd2_clk_fast_slew_rate_4x = "/pinctrl@11040000/sd2-clk_fast_slew_rate_4x";
|
|
sd2_pins_as_pdn = "/pinctrl@11040000/sd2-pins-as-pdn";
|
|
pinctrl_4 = "/pinctrl@10430000";
|
|
gpp0 = "/pinctrl@10430000/gpp0";
|
|
gpp1 = "/pinctrl@10430000/gpp1";
|
|
gpp2 = "/pinctrl@10430000/gpp2";
|
|
gpp3 = "/pinctrl@10430000/gpp3";
|
|
gpp4 = "/pinctrl@10430000/gpp4";
|
|
gpp5 = "/pinctrl@10430000/gpp5";
|
|
gpp13 = "/pinctrl@10430000/gpp13";
|
|
gpp14 = "/pinctrl@10430000/gpp14";
|
|
gpp15 = "/pinctrl@10430000/gpp15";
|
|
gpg0 = "/pinctrl@10430000/gpg0";
|
|
uart0_bus = "/pinctrl@10430000/uart0-bus";
|
|
hsi2c0_bus = "/pinctrl@10430000/hsi2c0-bus";
|
|
hsi2c1_bus = "/pinctrl@10430000/hsi2c1-bus";
|
|
hsi2c2_bus = "/pinctrl@10430000/hsi2c2-bus";
|
|
hsi2c3_bus = "/pinctrl@10430000/hsi2c3-bus";
|
|
hsi2c4_bus = "/pinctrl@10430000/hsi2c4-bus";
|
|
hsi2c5_bus = "/pinctrl@10430000/hsi2c5-bus";
|
|
hsi2c6_bus = "/pinctrl@10430000/hsi2c6-bus";
|
|
hsi2c7_bus = "/pinctrl@10430000/hsi2c7-bus";
|
|
hsi2c8_bus = "/pinctrl@10430000/hsi2c8-bus";
|
|
hsi2c9_bus = "/pinctrl@10430000/hsi2c9-bus";
|
|
hsi2c10_bus = "/pinctrl@10430000/hsi2c10-bus";
|
|
hsi2c11_bus = "/pinctrl@10430000/hsi2c11-bus";
|
|
hsi2c26_bus = "/pinctrl@10430000/hsi2c26-bus";
|
|
hsi2c27_bus = "/pinctrl@10430000/hsi2c27-bus";
|
|
hsi2c28_bus = "/pinctrl@10430000/hsi2c28-bus";
|
|
hsi2c29_bus = "/pinctrl@10430000/hsi2c29-bus";
|
|
hsi2c30_bus = "/pinctrl@10430000/hsi2c30-bus";
|
|
hsi2c31_bus = "/pinctrl@10430000/hsi2c31-bus";
|
|
spi0_bus = "/pinctrl@10430000/spi0-bus";
|
|
spi0_cs = "/pinctrl@10430000/spi0-cs";
|
|
spi0_cs_func = "/pinctrl@10430000/spi0-cs-func";
|
|
spi1_bus = "/pinctrl@10430000/spi1-bus";
|
|
spi1_cs = "/pinctrl@10430000/spi1-cs";
|
|
spi1_cs_func = "/pinctrl@10430000/spi1-cs-func";
|
|
spi2_bus = "/pinctrl@10430000/spi2-bus";
|
|
spi2_cs = "/pinctrl@10430000/spi2-cs";
|
|
spi2_cs_func = "/pinctrl@10430000/spi2-cs-func";
|
|
spi3_bus = "/pinctrl@10430000/spi3-bus";
|
|
spi3_cs = "/pinctrl@10430000/spi3-cs";
|
|
spi3_cs_func = "/pinctrl@10430000/spi3-cs-func";
|
|
spi4_bus = "/pinctrl@10430000/spi4-bus";
|
|
spi4_cs = "/pinctrl@10430000/spi4-cs";
|
|
spi4_cs_func = "/pinctrl@10430000/spi4-cs-func";
|
|
spi5_bus = "/pinctrl@10430000/spi5-bus";
|
|
spi5_cs = "/pinctrl@10430000/spi5-cs";
|
|
spi5_cs_func = "/pinctrl@10430000/spi5-cs-func";
|
|
spi13_bus = "/pinctrl@10430000/spi13-bus";
|
|
spi13_cs = "/pinctrl@10430000/spi13-cs";
|
|
spi13_cs_func = "/pinctrl@10430000/spi13-cs-func";
|
|
spi14_bus = "/pinctrl@10430000/spi14-bus";
|
|
spi14_cs = "/pinctrl@10430000/spi14-cs";
|
|
spi14_cs_func = "/pinctrl@10430000/spi14-cs-func";
|
|
spi15_bus = "/pinctrl@10430000/spi15-bus";
|
|
spi15_cs = "/pinctrl@10430000/spi15-cs";
|
|
spi15_cs_func = "/pinctrl@10430000/spi15-cs-func";
|
|
uart2_bus_single = "/pinctrl@10430000/uart2-bus";
|
|
uart2_bus_dual = "/pinctrl@10430000/uart2-bus-dual";
|
|
uart3_bus_single = "/pinctrl@10430000/uart3-bus";
|
|
uart3_bus_dual = "/pinctrl@10430000/uart3-bus-dual";
|
|
uart4_bus_single = "/pinctrl@10430000/uart4-bus";
|
|
uart4_bus_dual = "/pinctrl@10430000/uart4-bus-dual";
|
|
uart5_bus_single = "/pinctrl@10430000/uart5-bus";
|
|
uart5_bus_dual = "/pinctrl@10430000/uart5-bus-dual";
|
|
uart6_bus_single = "/pinctrl@10430000/uart6-bus";
|
|
uart6_bus_dual = "/pinctrl@10430000/uart6-bus-dual";
|
|
uart7_bus_single = "/pinctrl@10430000/uart7-bus";
|
|
uart7_bus_dual = "/pinctrl@10430000/uart7-bus-dual";
|
|
uart15_bus_single = "/pinctrl@10430000/uart15-bus";
|
|
uart15_bus_dual = "/pinctrl@10430000/uart15-bus-dual";
|
|
uart16_bus_single = "/pinctrl@10430000/uart16-bus";
|
|
uart16_bus_dual = "/pinctrl@10430000/uart16-bus-dual";
|
|
uart17_bus_single = "/pinctrl@10430000/uart17-bus";
|
|
uart17_bus_dual = "/pinctrl@10430000/uart17-bus-dual";
|
|
pinctrl_5 = "/pinctrl@10730000";
|
|
gpb3 = "/pinctrl@10730000/gpb3";
|
|
gpb4 = "/pinctrl@10730000/gpb4";
|
|
gpp11 = "/pinctrl@10730000/gpp11";
|
|
gpp12 = "/pinctrl@10730000/gpp12";
|
|
gpp16 = "/pinctrl@10730000/gpp16";
|
|
gpp17 = "/pinctrl@10730000/gpp17";
|
|
gpp18 = "/pinctrl@10730000/gpp18";
|
|
gpg1 = "/pinctrl@10730000/gpg1";
|
|
gpg2 = "/pinctrl@10730000/gpg2";
|
|
gpb0 = "/pinctrl@10730000/gpb0";
|
|
gpb1 = "/pinctrl@10730000/gpb1";
|
|
gpb2 = "/pinctrl@10730000/gpb2";
|
|
hsi2c22_bus = "/pinctrl@10730000/hsi2c22-bus";
|
|
hsi2c23_bus = "/pinctrl@10730000/hsi2c23-bus";
|
|
hsi2c24_bus = "/pinctrl@10730000/hsi2c24-bus";
|
|
hsi2c25_bus = "/pinctrl@10730000/hsi2c25-bus";
|
|
hsi2c32_bus = "/pinctrl@10730000/hsi2c32-bus";
|
|
hsi2c33_bus = "/pinctrl@10730000/hsi2c33-bus";
|
|
hsi2c34_bus = "/pinctrl@10730000/hsi2c34-bus";
|
|
hsi2c35_bus = "/pinctrl@10730000/hsi2c35-bus";
|
|
hsi2c36_bus = "/pinctrl@10730000/hsi2c36-bus";
|
|
hsi2c37_bus = "/pinctrl@10730000/hsi2c37-bus";
|
|
spi11_bus = "/pinctrl@10730000/spi11-bus";
|
|
spi11_cs = "/pinctrl@10730000/spi11-cs";
|
|
spi11_cs_func = "/pinctrl@10730000/spi11-cs-func";
|
|
spi12_bus = "/pinctrl@10730000/spi12-bus";
|
|
spi12_cs = "/pinctrl@10730000/spi12-cs";
|
|
spi12_cs_func = "/pinctrl@10730000/spi12-cs-func";
|
|
spi16_bus = "/pinctrl@10730000/spi16-bus";
|
|
spi16_cs = "/pinctrl@10730000/spi16-cs";
|
|
spi16_cs_func = "/pinctrl@10730000/spi16-cs-func";
|
|
spi17_bus = "/pinctrl@10730000/spi17-bus";
|
|
spi17_cs = "/pinctrl@10730000/spi17-cs";
|
|
spi17_cs_func = "/pinctrl@10730000/spi17-cs-func";
|
|
spi18_bus = "/pinctrl@10730000/spi18-bus";
|
|
spi18_cs = "/pinctrl@10730000/spi18-cs";
|
|
spi18_cs_func = "/pinctrl@10730000/spi18-cs-func";
|
|
uart13_bus_single = "/pinctrl@10730000/uart13-bus";
|
|
uart13_bus_dual = "/pinctrl@10730000/uart13-bus-dual";
|
|
uart14_bus_single = "/pinctrl@10730000/uart14-bus";
|
|
uart14_bus_dual = "/pinctrl@10730000/uart14-bus-dual";
|
|
uart18_bus_single = "/pinctrl@10730000/uart18-bus";
|
|
uart18_bus_dual = "/pinctrl@10730000/uart18-bus-dual";
|
|
uart19_bus_single = "/pinctrl@10730000/uart19-bus";
|
|
uart19_bus_dual = "/pinctrl@10730000/uart19-bus-dual";
|
|
uart20_bus_single = "/pinctrl@10730000/uart20-bus";
|
|
uart20_bus_dual = "/pinctrl@10730000/uart20-bus-dual";
|
|
aud_i2s0_bus = "/pinctrl@10730000/aud-i2s0-bus";
|
|
aud_i2s0_idle = "/pinctrl@10730000/aud-i2s0-idle";
|
|
aud_i2s1_bus = "/pinctrl@10730000/aud-i2s1-bus";
|
|
aud_i2s1_idle = "/pinctrl@10730000/aud-i2s1-idle";
|
|
aud_i2s2_bus = "/pinctrl@10730000/aud-i2s2-bus";
|
|
aud_i2s2_idle = "/pinctrl@10730000/aud-i2s2-idle";
|
|
aud_i2s3_bus = "/pinctrl@10730000/aud-i2s3-bus";
|
|
aud_i2s3_idle = "/pinctrl@10730000/aud-i2s3-idle";
|
|
aud_i2s4_bus = "/pinctrl@10730000/aud-i2s4-bus";
|
|
aud_i2s4_idle = "/pinctrl@10730000/aud-i2s4-idle";
|
|
aud_dsd_bus = "/pinctrl@10730000/aud-dsd-bus";
|
|
aud_dsd_idle = "/pinctrl@10730000/aud-dsd-idle";
|
|
decon_0_te_on = "/pinctrl@10730000/decon_0_te_on";
|
|
decon_0_te_off = "/pinctrl@10730000/decon_0_te_off";
|
|
sensor_mclk0_out = "/pinctrl@10730000/sensor-mclk0-out";
|
|
sensor_mclk1_out = "/pinctrl@10730000/sensor-mclk1-out";
|
|
sensor_mclk2_out = "/pinctrl@10730000/sensor-mclk2-out";
|
|
sensor_mclk3_out = "/pinctrl@10730000/sensor-mclk3-out";
|
|
sensor_mclk4_out = "/pinctrl@10730000/sensor-mclk4-out";
|
|
sensor_mclk5_out = "/pinctrl@10730000/sensor-mclk5-out";
|
|
sensor_mclk0_fn = "/pinctrl@10730000/sensor-mclk0-fn";
|
|
sensor_mclk1_fn = "/pinctrl@10730000/sensor-mclk1-fn";
|
|
sensor_mclk2_fn = "/pinctrl@10730000/sensor-mclk2-fn";
|
|
sensor_mclk3_fn = "/pinctrl@10730000/sensor-mclk3-fn";
|
|
sensor_mclk4_fn = "/pinctrl@10730000/sensor-mclk4-fn";
|
|
sensor_mclk5_fn = "/pinctrl@10730000/sensor-mclk5-fn";
|
|
ufs_boot_ldo = "/pinctrl@10730000/ufs-boot-ldo";
|
|
pinctrl_6 = "/pinctrl@11D30000";
|
|
gpp6 = "/pinctrl@11D30000/gpp6";
|
|
gpp7 = "/pinctrl@11D30000/gpp7";
|
|
gpp8 = "/pinctrl@11D30000/gpp8";
|
|
gpp9 = "/pinctrl@11D30000/gpp9";
|
|
gpp10 = "/pinctrl@11D30000/gpp10";
|
|
hsi2c12_bus = "/pinctrl@11D30000/hsi2c12-bus";
|
|
hsi2c13_bus = "/pinctrl@11D30000/hsi2c13-bus";
|
|
hsi2c14_bus = "/pinctrl@11D30000/hsi2c14-bus";
|
|
hsi2c15_bus = "/pinctrl@11D30000/hsi2c15-bus";
|
|
hsi2c16_bus = "/pinctrl@11D30000/hsi2c16-bus";
|
|
hsi2c17_bus = "/pinctrl@11D30000/hsi2c17-bus";
|
|
hsi2c18_bus = "/pinctrl@11D30000/hsi2c18-bus";
|
|
hsi2c19_bus = "/pinctrl@11D30000/hsi2c19-bus";
|
|
hsi2c20_bus = "/pinctrl@11D30000/hsi2c20-bus";
|
|
hsi2c21_bus = "/pinctrl@11D30000/hsi2c21-bus";
|
|
spi6_bus = "/pinctrl@11D30000/spi6-bus";
|
|
spi6_cs = "/pinctrl@11D30000/spi6-cs";
|
|
spi6_cs_func = "/pinctrl@11D30000/spi6-cs-func";
|
|
spi7_bus = "/pinctrl@11D30000/spi7-bus";
|
|
spi7_cs = "/pinctrl@11D30000/spi7-cs";
|
|
spi7_cs_func = "/pinctrl@11D30000/spi7-cs-func";
|
|
spi8_bus = "/pinctrl@11D30000/spi8-bus";
|
|
spi8_cs = "/pinctrl@11D30000/spi8-cs";
|
|
spi8_cs_func = "/pinctrl@11D30000/spi8-cs-func";
|
|
spi9_bus = "/pinctrl@11D30000/spi9-bus";
|
|
spi9_cs = "/pinctrl@11D30000/spi9-cs";
|
|
spi9_cs_func = "/pinctrl@11D30000/spi9-cs-func";
|
|
spi10_bus = "/pinctrl@11D30000/spi10-bus";
|
|
spi10_cs = "/pinctrl@11D30000/spi10-cs";
|
|
spi10_cs_func = "/pinctrl@11D30000/spi10-cs-func";
|
|
uart8_bus_single = "/pinctrl@11D30000/uart8-bus";
|
|
uart8_bus_dual = "/pinctrl@11D30000/uart8-bus-dual";
|
|
uart9_bus_single = "/pinctrl@11D30000/uart9-bus";
|
|
uart9_bus_dual = "/pinctrl@11D30000/uart9-bus-dual";
|
|
uart10_bus_single = "/pinctrl@11D30000/uart10-bus";
|
|
uart10_bus_dual = "/pinctrl@11D30000/uart10-bus-dual";
|
|
uart11_bus_single = "/pinctrl@11D30000/uart11-bus";
|
|
uart11_bus_dual = "/pinctrl@11D30000/uart11-bus-dual";
|
|
uart12_bus_single = "/pinctrl@11D30000/uart12-bus";
|
|
uart12_bus_dual = "/pinctrl@11D30000/uart12-bus-dual";
|
|
pinctrl_7 = "/pinctrl@15580000";
|
|
gpv0 = "/pinctrl@15580000/gpv0";
|
|
dmic_bus_clk = "/pinctrl@15580000/dmic-bus-clk";
|
|
dmic_bus_clk_idle = "/pinctrl@15580000/dmic-bus-clk-idle";
|
|
dmic_bus_clk1 = "/pinctrl@15580000/dmic-bus-clk1";
|
|
dmic_bus_clk1_idle = "/pinctrl@15580000/dmic-bus-clk1-idle";
|
|
dmic_bus_clk2 = "/pinctrl@15580000/dmic-bus-clk2";
|
|
dmic_bus_clk2_idle = "/pinctrl@15580000/dmic-bus-clk2-idle";
|
|
dmic_pdm = "/pinctrl@15580000/dmic-pdm";
|
|
amic_pdm = "/pinctrl@15580000/amic-pdm";
|
|
dmic_pdm_idle = "/pinctrl@15580000/dmic-pdm-idle";
|
|
dmic_pdm1_bus = "/pinctrl@15580000/dmic-pdm1-bus";
|
|
dmic_pdm1_idle = "/pinctrl@15580000/dmic-pdm1-idle";
|
|
dmic_pdm2_bus = "/pinctrl@15580000/dmic-pdm2-bus";
|
|
dmic_pdm2_idle = "/pinctrl@15580000/dmic-pdm2-idle";
|
|
sysreg_peric0_usi = "/syscon@10421000";
|
|
sysreg_peric1_1_usi = "/syscon@10721000";
|
|
sysreg_peric1_2_usi = "/syscon@10722000";
|
|
sysreg_peric2_usi = "/syscon@11D21000";
|
|
sysreg_cmgp_usi = "/syscon@14E22000";
|
|
usi_18 = "/usi@10722008";
|
|
hsi2c_0 = "/hsi2c@10550000";
|
|
hsi2c_1 = "/hsi2c@10560000";
|
|
hsi2c_2 = "/hsi2c@10570000";
|
|
hsi2c_3 = "/hsi2c@10580000";
|
|
hsi2c_4 = "/hsi2c@10590000";
|
|
hsi2c_5 = "/hsi2c@105A0000";
|
|
hsi2c_6 = "/hsi2c@105B0000";
|
|
hsi2c_7 = "/hsi2c@105C0000";
|
|
hsi2c_8 = "/hsi2c@105D0000";
|
|
hsi2c_9 = "/hsi2c@105E0000";
|
|
hsi2c_10 = "/hsi2c@105F0000";
|
|
hsi2c_11 = "/hsi2c@10600000";
|
|
hsi2c_12 = "/hsi2c@11EA0000";
|
|
hsi2c_13 = "/hsi2c@11EB0000";
|
|
hsi2c_14 = "/hsi2c@11EC0000";
|
|
hsi2c_15 = "/hsi2c@11ED0000";
|
|
hsi2c_16 = "/hsi2c@11EE0000";
|
|
hsi2c_17 = "/hsi2c@11EF0000";
|
|
hsi2c_18 = "/hsi2c@11f00000";
|
|
hsi2c_19 = "/hsi2c@11f10000";
|
|
hsi2c_20 = "/hsi2c@11f20000";
|
|
hsi2c_21 = "/hsi2c@11f30000";
|
|
hsi2c_22 = "/hsi2c@10940000";
|
|
hsi2c_23 = "/hsi2c@10950000";
|
|
hsi2c_24 = "/hsi2c@109C0000";
|
|
hsi2c_25 = "/hsi2c@109D0000";
|
|
hsi2c_26 = "/hsi2c@10630000";
|
|
hsi2c_27 = "/hsi2c@10640000";
|
|
hsi2c_28 = "/hsi2c@10650000";
|
|
hsi2c_29 = "/hsi2c@10660000";
|
|
hsi2c_30 = "/hsi2c@10670000";
|
|
hsi2c_31 = "/hsi2c@10680000";
|
|
hsi2c_32 = "/hsi2c@10960000";
|
|
hsi2c_33 = "/hsi2c@10970000";
|
|
hsi2c_34 = "/hsi2c@10990000";
|
|
hsi2c_35 = "/hsi2c@109A0000";
|
|
hsi2c_36 = "/hsi2c@109E0000";
|
|
hsi2c_37 = "/hsi2c@109F0000";
|
|
hsi2c_38 = "/hsi2c@14F00000";
|
|
hsi2c_39 = "/hsi2c@14F10000";
|
|
hsi2c_40 = "/hsi2c@14F20000";
|
|
hsi2c_41 = "/hsi2c@14F30000";
|
|
hsi2c_42 = "/hsi2c@14F40000";
|
|
hsi2c_43 = "/hsi2c@14F50000";
|
|
hsi2c_44 = "/hsi2c@14F60000";
|
|
hsi2c_45 = "/hsi2c@14F70000";
|
|
spi_0 = "/spi@10550000";
|
|
spi_1 = "/spi@10570000";
|
|
spi_2 = "/spi@10590000";
|
|
spi_3 = "/spi@105B0000";
|
|
spi_4 = "/spi@105D0000";
|
|
spi_5 = "/spi@105F0000";
|
|
spi_6 = "/spi@11EA0000";
|
|
spi_7 = "/spi@11EC0000";
|
|
spi_8 = "/spi@11EE0000";
|
|
spi_9 = "/spi@11f00000";
|
|
spi_10 = "/spi@11f20000";
|
|
spi_11 = "/spi@10940000";
|
|
spi_12 = "/spi@109C0000";
|
|
spi_13 = "/spi@10630000";
|
|
spi_14 = "/spi@10650000";
|
|
spi_15 = "/spi@10670000";
|
|
spi_16 = "/spi@10960000";
|
|
spi_17 = "/spi@10990000";
|
|
spi_18 = "/spi@109E0000";
|
|
spi_19 = "/spi@14F00000";
|
|
spi_20 = "/spi@14F20000";
|
|
spi_21 = "/spi@14F40000";
|
|
spi_22 = "/spi@14F60000";
|
|
serial_0 = "/uart@10540000";
|
|
serial_1 = "/uart@10840000";
|
|
serial_2 = "/uart@10550000";
|
|
serial_3 = "/uart@10570000";
|
|
serial_4 = "/uart@10590000";
|
|
serial_5 = "/uart@105B0000";
|
|
serial_6 = "/uart@105D0000";
|
|
serial_7 = "/uart@105F0000";
|
|
serial_8 = "/uart@11EA0000";
|
|
serial_9 = "/uart@11EC0000";
|
|
serial_10 = "/uart@11EE0000";
|
|
serial_11 = "/uart@11f00000";
|
|
serial_12 = "/uart@11f20000";
|
|
serial_13 = "/uart@10940000";
|
|
serial_14 = "/uart@109C0000";
|
|
serial_15 = "/uart@10630000";
|
|
serial_16 = "/uart@10650000";
|
|
serial_17 = "/uart@10670000";
|
|
serial_18 = "/uart@10960000";
|
|
serial_19 = "/uart@10990000";
|
|
serial_20 = "/uart@109E0000";
|
|
serial_21 = "/uart@14F00000";
|
|
serial_22 = "/uart@14F20000";
|
|
serial_23 = "/uart@14F40000";
|
|
serial_24 = "/uart@14F60000";
|
|
set0 = "/set@0000";
|
|
set0_1 = "/set@0001";
|
|
set0_2 = "/set@0002";
|
|
set1 = "/set@0100";
|
|
set1_1 = "/set@0101";
|
|
set1_2 = "/set@0102";
|
|
set2 = "/set@0200";
|
|
set2_1 = "/set@0201";
|
|
set2_2 = "/set@0202";
|
|
set3 = "/set@0300";
|
|
set3_1 = "/set@0301";
|
|
set3_2 = "/set@0302";
|
|
set4 = "/set@0400";
|
|
set4_1 = "/set@0401";
|
|
set4_2 = "/set@0402";
|
|
cpu0 = "/cpus/cpu@0000";
|
|
cpu1 = "/cpus/cpu@0100";
|
|
cpu2 = "/cpus/cpu@0200";
|
|
cpu3 = "/cpus/cpu@0300";
|
|
cpu4 = "/cpus/cpu@0400";
|
|
cpu5 = "/cpus/cpu@0500";
|
|
cpu6 = "/cpus/cpu@0600";
|
|
cpu7 = "/cpus/cpu@0700";
|
|
ANANKE_CPU_SLEEP = "/cpus/idle-states/ananke-cpu-sleep";
|
|
HERCULES_CPU_SLEEP = "/cpus/idle-states/hercules-cpu-sleep";
|
|
HERA_CPU_SLEEP = "/cpus/idle-states/hera-cpu-sleep";
|
|
cpufreq_domain0 = "/exynos-acme/domain@0";
|
|
cpufreq_domain1 = "/exynos-acme/domain@1";
|
|
cpufreq_domain2 = "/exynos-acme/domain@2";
|
|
lit_dsu_perf = "/dm-tables/dm-table@0000";
|
|
med_dsu_perf = "/dm-tables/dm-table@0001";
|
|
big_dsu_perf = "/dm-tables/dm-table@0002";
|
|
lit_mif_perf = "/dm-tables/dm-table@0003";
|
|
med_mif_perf = "/dm-tables/dm-table@0004";
|
|
big_mif_perf = "/dm-tables/dm-table@0005";
|
|
afm_domain1 = "/exynos-afm/domain@1";
|
|
afm_domain2 = "/exynos-afm/domain@2";
|
|
sysmmu_d0_dpuf0 = "/sysmmu@19D00000";
|
|
sysmmu_d1_dpuf0 = "/sysmmu@19D10000";
|
|
sysmmu_d0_dpuf1 = "/sysmmu@1AF00000";
|
|
sysmmu_d1_dpuf1 = "/sysmmu@1AF10000";
|
|
sysmmu_d0_csis = "/sysmmu@17110000";
|
|
sysmmu_d1_csis = "/sysmmu@17140000";
|
|
sysmmu_d2_csis = "/sysmmu@17170000";
|
|
sysmmu_d3_csis = "/sysmmu@171A0000";
|
|
sysmmu_d_lme = "/sysmmu@17770000";
|
|
sysmmu_d_taa = "/sysmmu@16E40000";
|
|
sysmmu_d_yuvpp = "/sysmmu@18080000";
|
|
sysmmu_d0_dns = "/sysmmu@17540000";
|
|
sysmmu_d1_dns = "/sysmmu@17580000";
|
|
sysmmu_d0_mcsc = "/sysmmu@15CA0000";
|
|
sysmmu_d1_mcsc = "/sysmmu@15CD0000";
|
|
sysmmu_d2_mcsc = "/sysmmu@15D00000";
|
|
sysmmu_d0_mcfp0 = "/sysmmu@178A0000";
|
|
sysmmu_d1_mcfp0 = "/sysmmu@178D0000";
|
|
sysmmu_d2_mcfp0 = "/sysmmu@17900000";
|
|
sysmmu_d3_mcfp0 = "/sysmmu@17930000";
|
|
sysmmu_d0_mcfp1 = "/sysmmu@17A70000";
|
|
sysmmu_d0_mfc0 = "/sysmmu@18670000";
|
|
sysmmu_d1_mfc0 = "/sysmmu@186A0000";
|
|
sysmmu_d0_mfc1 = "/sysmmu@18870000";
|
|
sysmmu_d1_mfc1 = "/sysmmu@188A0000";
|
|
sysmmu_d_m2m = "/sysmmu@18A00000";
|
|
sysmmu_d_aud = "/sysmmu@18D50000";
|
|
sysmmu_d0_npus = "/sysmmu@17C50000";
|
|
sysmmu_d1_npus = "/sysmmu@17C80000";
|
|
sysmmu_d2_npus = "/sysmmu@17CB0000";
|
|
sysmmu_d0_vpc = "/sysmmu@16650000";
|
|
sysmmu_d1_vpc = "/sysmmu@16680000";
|
|
sysmmu_d2_vpc = "/sysmmu@166B0000";
|
|
sysreg_hsi1_ufs = "/sysreg_hsi1_ufs@11020000";
|
|
ufs = "/ufs@0x13100000";
|
|
ufs_fixed_vcc = "/fixedregulator@0";
|
|
emul_display = "/fragment@lcd/__overlay__/emul_display";
|
|
s6e3hf4 = "/fragment@lcd/__overlay__/s6e3hf4_wqhd";
|
|
s6e3ha2k = "/fragment@lcd/__overlay__/s6e3ha2k_wqhd";
|
|
s6e3ha3 = "/fragment@lcd/__overlay__/s6e3ha3_wqhd";
|
|
s6e3ha6 = "/fragment@lcd/__overlay__/s6e3ha6_ddi";
|
|
s6e3ha8 = "/fragment@lcd/__overlay__/s6e3ha8_ddi";
|
|
s6e3ha9 = "/fragment@lcd/__overlay__/s6e3ha9_ddi";
|
|
s6e3hab = "/fragment@lcd/__overlay__/s6e3hab_ddi";
|
|
s6e3fa0 = "/fragment@lcd/__overlay__/s6e3fa0_fhd";
|
|
s6e3fa0_vid = "/fragment@lcd/__overlay__/s6e3fa0_fhd_vid";
|
|
s6e3fab = "/fragment@lcd/__overlay__/s6e3fab_ddi";
|
|
s6e3had = "/fragment@lcd/__overlay__/s6e3had_ddi";
|
|
dpp_0 = "/dpp@0x19CB0000";
|
|
dpp_1 = "/dpp@0x19CB1000";
|
|
dpp_2 = "/dpp@0x19CB2000";
|
|
dpp_3 = "/dpp@0x19CB3000";
|
|
dpp_4 = "/dpp@0x19CB4000";
|
|
dpp_5 = "/dpp@0x19CB5000";
|
|
dpp_6 = "/dpp@0x19CB6000";
|
|
dpp_7 = "/dpp@0x19CB7000";
|
|
dpp_8 = "/dpp@0x1AEB1000";
|
|
dpp_9 = "/dpp@0x1AEB2000";
|
|
dpp_10 = "/dpp@0x1AEB3000";
|
|
dpp_11 = "/dpp@0x1AEB4000";
|
|
dpp_12 = "/dpp@0x1AEB5000";
|
|
dpp_13 = "/dpp@0x1AEB6000";
|
|
dpp_14 = "/dpp@0x1AEB7000";
|
|
dpp_15 = "/dpp@0x1AEB8000";
|
|
dpp_16 = "/dpp@0x19CBC000";
|
|
dma_dsimfc_0 = "/fcmd@0x19CBC000";
|
|
dma_dsimfc_1 = "/fcmd@0x19CBD000";
|
|
dma_dsimfc_2 = "/fcmd@0x1AEBC000";
|
|
disp_ss = "/disp_ss@0x19E20000";
|
|
mipi_phy_dsim0_m4m4 = "/dphy_m4m4_dsim0@0x15860000";
|
|
dsim_0 = "/dsim@0x19EC0000";
|
|
panel_0 = "/panel_0";
|
|
displayport = "/displayport@0x10AB0000";
|
|
decon_0 = "/decon_0@0x19F00000";
|
|
decon_1 = "/decon_1@0x19F01000";
|
|
decon_2 = "/decon_2@0x19F02000";
|
|
decon_3 = "/decon_3@0x19F03000";
|
|
dsim_modes = "/dsim_modes";
|
|
drmdpp0 = "/drmdpp@0x19CB0000";
|
|
drmdpp1 = "/drmdpp@0x19CB1000";
|
|
drmdpp2 = "/drmdpp@0x19CB2000";
|
|
drmdpp3 = "/drmdpp@0x19CB3000";
|
|
drmdpp4 = "/drmdpp@0x19CB4000";
|
|
drmdpp5 = "/drmdpp@0x19CB5000";
|
|
drmdpp6 = "/drmdpp@0x19CB6000";
|
|
drmdpp7 = "/drmdpp@0x19CB7000";
|
|
drmdpp8 = "/drmdpp@0x1AEB1000";
|
|
drmdpp9 = "/drmdpp@0x1AEB2000";
|
|
drmdpp10 = "/drmdpp@0x1AEB3000";
|
|
drmdpp11 = "/drmdpp@0x1AEB4000";
|
|
drmdpp12 = "/drmdpp@0x1AEB5000";
|
|
drmdpp13 = "/drmdpp@0x1AEB6000";
|
|
drmdpp14 = "/drmdpp@0x1AEB7000";
|
|
drmdpp15 = "/drmdpp@0x1AEB8000";
|
|
drmdpp16 = "/drmdpp@0x19CBC000";
|
|
drmdsim0 = "/drmdsim@0x19EC0000";
|
|
drmpanel0 = "/drmdsim@0x19EC0000/drmpanel";
|
|
drmdp = "/drmdp@0x10AB0000";
|
|
drmdecon0 = "/drmdecon@0x19F00000";
|
|
drmdecon1 = "/drmdecon@0x19F01000";
|
|
drmdecon2 = "/drmdecon@0x19F02000";
|
|
drmdecon3 = "/drmdecon@0x19F03000";
|
|
dpm = "/dpm";
|
|
dss = "/dss";
|
|
s2d = "/exynos_adv_tracer_s2d";
|
|
itmon = "/exynos-itmon";
|
|
ehld_dbgc = "/exynos-ehld/dbgc";
|
|
etm0 = "/etm@1e840000";
|
|
etm0_out = "/etm@1e840000/out-ports/port/endpoint";
|
|
etm1 = "/etm@1e940000";
|
|
etm1_out = "/etm@1e940000/out-ports/port/endpoint";
|
|
etm2 = "/etm@1ea40000";
|
|
etm2_out = "/etm@1ea40000/out-ports/port/endpoint";
|
|
etm3 = "/etm@1eb40000";
|
|
etm3_out = "/etm@1eb40000/out-ports/port/endpoint";
|
|
etm4 = "/etm@1ec40000";
|
|
etm4_out = "/etm@1ec40000/out-ports/port/endpoint";
|
|
etm5 = "/etm@1ed40000";
|
|
etm5_out = "/etm@1ed40000/out-ports/port/endpoint";
|
|
etm6 = "/etm@1ee40000";
|
|
etm6_out = "/etm@1ee40000/out-ports/port/endpoint";
|
|
etm7 = "/etm@1ef40000";
|
|
etm7_out = "/etm@1ef40000/out-ports/port/endpoint";
|
|
etf0 = "/etf0@1e004000";
|
|
etf0_in = "/etf0@1e004000/in-ports/port/endpoint";
|
|
etf0_out = "/etf0@1e004000/out-ports/port/endpoint";
|
|
etf1 = "/etf1@1e005000";
|
|
etf1_in = "/etf1@1e005000/in-ports/port/endpoint";
|
|
etf1_out = "/etf1@1e005000/out-ports/port/endpoint";
|
|
etr = "/etr@1e00a000";
|
|
etr_in = "/etr@1e00a000/in-ports/port/endpoint";
|
|
stm_out = "/stm@1e00b000/out-ports/port/endpoint";
|
|
funnel0 = "/funnel0@1e007000";
|
|
funnel0_out0 = "/funnel0@1e007000/out-ports/port/endpoint";
|
|
funnel0_in0 = "/funnel0@1e007000/in-ports/port@0/endpoint";
|
|
funnel0_in1 = "/funnel0@1e007000/in-ports/port@1/endpoint";
|
|
funnel0_in2 = "/funnel0@1e007000/in-ports/port@2/endpoint";
|
|
funnel0_in3 = "/funnel0@1e007000/in-ports/port@3/endpoint";
|
|
funnel0_in4 = "/funnel0@1e007000/in-ports/port@4/endpoint";
|
|
funnel1 = "/funnel1@1e008000";
|
|
funnel1_out0 = "/funnel1@1e008000/out-ports/port/endpoint";
|
|
funnel1_in0 = "/funnel1@1e008000/in-ports/port@0/endpoint";
|
|
funnel1_in1 = "/funnel1@1e008000/in-ports/port@1/endpoint";
|
|
funnel1_in2 = "/funnel1@1e008000/in-ports/port@2/endpoint";
|
|
funnel1_in7 = "/funnel1@1e008000/in-ports/port@7/endpoint";
|
|
funnelm = "/funnelm@1e009000";
|
|
funnelm_out0 = "/funnelm@1e009000/out-ports/port/endpoint";
|
|
funnelm_in0 = "/funnelm@1e009000/in-ports/port@0/endpoint";
|
|
funnelm_in1 = "/funnelm@1e009000/in-ports/port@1/endpoint";
|
|
mali = "/mali@18500000";
|
|
sysreg_hsi0 = "/sysreg_hsi0@10A20000";
|
|
udc = "/usb@10B00000";
|
|
usbdrd_dwc3 = "/usb@10B00000/dwc3";
|
|
usbdrd_phy0 = "/phy@10C00000";
|
|
pcie_0 = "/pcie@113B0000";
|
|
pcie_1 = "/pcie@11320000";
|
|
acpm_mfd_bus0 = "/acpm_mfd_bus@15960000";
|
|
acpm_mfd_bus1 = "/acpm_mfd_bus@15961000";
|
|
exynos_dm = "/exynos-dm@17000000";
|
|
devfreq_0 = "/exynos_devfreq/devfreq_mif@17000010";
|
|
devfreq_1 = "/exynos_devfreq/devfreq_int@17000020";
|
|
devfreq_2 = "/exynos_devfreq/devfreq_intcam@17000030";
|
|
devfreq_3 = "/exynos_devfreq/devfreq_disp@17000040";
|
|
devfreq_4 = "/exynos_devfreq/devfreq_cam@17000050";
|
|
devfreq_5 = "/exynos_devfreq/devfreq_npu@17000060";
|
|
devfreq_6 = "/exynos_devfreq/devfreq_aud@17000070";
|
|
devfreq_7 = "/exynos_devfreq/devfreq_vpc@17000080";
|
|
devfreq_8 = "/exynos_devfreq/devfreq_mfc@17000090";
|
|
devfreq_9 = "/exynos_devfreq/devfreq_csis@170000A0";
|
|
devfreq_10 = "/exynos_devfreq/devfreq_isp@170000B0";
|
|
devfreq_11 = "/exynos_devfreq/devfreq_mfc1@170000C0";
|
|
tmuctrl_0 = "/BIG@10090000";
|
|
tmuctrl_1 = "/MID@10090000";
|
|
tmuctrl_2 = "/LITTLE@10090000";
|
|
tmuctrl_3 = "/G3D@100A0000";
|
|
tmuctrl_4 = "/ISP@100A0000";
|
|
tmuctrl_5 = "/NPU@100A0000";
|
|
tmuctrl_6 = "/CP@10080000";
|
|
exynos_isp_thermal = "/exynos_isp_thermal";
|
|
big_thermal = "/thermal-zones/BIG";
|
|
big_cold = "/thermal-zones/BIG/trips/big-cold";
|
|
big_switch_on = "/thermal-zones/BIG/trips/big-switch-on";
|
|
big_control_temp = "/thermal-zones/BIG/trips/big-control-temp";
|
|
big_alert0 = "/thermal-zones/BIG/trips/big-alert0";
|
|
big_alert1 = "/thermal-zones/BIG/trips/big-alert1";
|
|
big_alert2 = "/thermal-zones/BIG/trips/big-alert2";
|
|
big_alert3 = "/thermal-zones/BIG/trips/big-alert3";
|
|
big_hot = "/thermal-zones/BIG/trips/big-hot";
|
|
mid_thermal = "/thermal-zones/MID";
|
|
mid_cold = "/thermal-zones/MID/trips/mid-cold";
|
|
mid_switch_on = "/thermal-zones/MID/trips/mid-switch-on";
|
|
mid_control_temp = "/thermal-zones/MID/trips/mid-control-temp";
|
|
mid_alert0 = "/thermal-zones/MID/trips/mid-alert0";
|
|
mid_alert1 = "/thermal-zones/MID/trips/mid-alert1";
|
|
mid_alert2 = "/thermal-zones/MID/trips/mid-alert2";
|
|
mid_alert3 = "/thermal-zones/MID/trips/mid-alert3";
|
|
mid_hot = "/thermal-zones/MID/trips/mid-hot";
|
|
little_thermal = "/thermal-zones/LITTLE";
|
|
little_alert0 = "/thermal-zones/LITTLE/trips/little-alert0";
|
|
little_alert1 = "/thermal-zones/LITTLE/trips/little-alert1";
|
|
little_alert2 = "/thermal-zones/LITTLE/trips/little-alert2";
|
|
little_alert3 = "/thermal-zones/LITTLE/trips/little-alert3";
|
|
little_alert4 = "/thermal-zones/LITTLE/trips/little-alert4";
|
|
little_alert5 = "/thermal-zones/LITTLE/trips/little-alert5";
|
|
little_alert6 = "/thermal-zones/LITTLE/trips/little-alert6";
|
|
little_hot = "/thermal-zones/LITTLE/trips/little-hot";
|
|
gpu_thermal = "/thermal-zones/G3D";
|
|
gpu_cold = "/thermal-zones/G3D/trips/gpu-cold";
|
|
gpu_switch_on = "/thermal-zones/G3D/trips/gpu-switch-on";
|
|
gpu_control_temp = "/thermal-zones/G3D/trips/gpu-control-temp";
|
|
gpu_alert0 = "/thermal-zones/G3D/trips/gpu-alert0";
|
|
gpu_alert1 = "/thermal-zones/G3D/trips/gpu-alert1";
|
|
gpu_alert2 = "/thermal-zones/G3D/trips/gpu-alert2";
|
|
gpu_alert3 = "/thermal-zones/G3D/trips/gpu-alert3";
|
|
gpu_hot = "/thermal-zones/G3D/trips/gpu-hot";
|
|
isp_thermal = "/thermal-zones/ISP";
|
|
isp_alert0 = "/thermal-zones/ISP/trips/isp-alert0";
|
|
isp_alert1 = "/thermal-zones/ISP/trips/isp-alert1";
|
|
isp_alert2 = "/thermal-zones/ISP/trips/isp-alert2";
|
|
isp_alert3 = "/thermal-zones/ISP/trips/isp-alert3";
|
|
isp_alert4 = "/thermal-zones/ISP/trips/isp-alert4";
|
|
isp_alert5 = "/thermal-zones/ISP/trips/isp-alert5";
|
|
isp_alert6 = "/thermal-zones/ISP/trips/isp-alert6";
|
|
isp_hot = "/thermal-zones/ISP/trips/isp-hot";
|
|
npu_thermal = "/thermal-zones/NPU";
|
|
npu_alert0 = "/thermal-zones/NPU/trips/npu-alert0";
|
|
npu_alert1 = "/thermal-zones/NPU/trips/npu-alert1";
|
|
npu_alert2 = "/thermal-zones/NPU/trips/npu-alert2";
|
|
npu_alert3 = "/thermal-zones/NPU/trips/npu-alert3";
|
|
npu_alert4 = "/thermal-zones/NPU/trips/npu-alert4";
|
|
npu_alert5 = "/thermal-zones/NPU/trips/npu-alert5";
|
|
npu_alert6 = "/thermal-zones/NPU/trips/npu-alert6";
|
|
npu_hot = "/thermal-zones/NPU/trips/npu-hot";
|
|
cp_thermal = "/thermal-zones/CP";
|
|
smc_info = "/mcinfo@1c030000";
|
|
pd_aud = "/pd-aud@15861880";
|
|
pd_csis = "/pd-csis@15861D80";
|
|
pd_vpc = "/pd-vpc@15861E00";
|
|
pd_itp = "/pd-itp@15862580";
|
|
pd_dns = "/pd-dns@15861E80";
|
|
pd_hsi0 = "/pd-hsi0@15862400";
|
|
pd_dpub = "/pd-dpub@15861F00";
|
|
pd_dpuf0 = "/pd-dpuf0@15861F80";
|
|
pd_dpuf1 = "/pd-dpuf1@15862000";
|
|
pd_vpd0 = "/pd-vpd0@15862080";
|
|
pd_vpd1 = "/pd-vpd1@15862100";
|
|
pd_embedded_g3d = "/pd-embedded_g3d@15862280";
|
|
pd_m2m = "/pd-m2m@15862600";
|
|
pd_mcsc = "/pd-mcsc@15862680";
|
|
pd_mfc0 = "/pd-mfc0@15862700";
|
|
pd_mfc1 = "/pd-mfc1@15862780";
|
|
pd_npus = "/pd-npus@15862C00";
|
|
pd_npu00 = "/pd-npu00@15862A00";
|
|
pd_npu01 = "/pd-npu01@15862A80";
|
|
pd_npu10 = "/pd-npu10@15862B00";
|
|
pd_lme = "/pd-lme@15862C80";
|
|
pd_embedded_ssp = "/pd-embedded_ssp@15862F80";
|
|
pd_taa = "/pd-taa@15863080";
|
|
pd_mcfp0 = "/pd-mcfp0@15863100";
|
|
pd_mcfp1 = "/pd-mcfp1@15863180";
|
|
pd_vts = "/pd-vts@15863200";
|
|
pd_yuvpp = "/pd-yuvpp@15863280";
|
|
mfc = "/mfc";
|
|
mfc_core0 = "/mfc/MFC-0";
|
|
mfc_core1 = "/mfc/MFC-1";
|
|
smfc_0 = "/smfc@18940000";
|
|
smfc_1 = "/smfc@18950000";
|
|
scaler_0 = "/scaler@18960000";
|
|
tsmux = "/tsmux@186E0000";
|
|
repeater = "/repeater@0";
|
|
abox_gic = "/abox-gic@18cf0000";
|
|
abox = "/abox@18c50000";
|
|
abox_core0 = "/abox@18c50000/abox-core@18c55000";
|
|
abox_firmware_sram0 = "/abox@18c50000/abox-core@18c55000/abox-firmware-sram0";
|
|
abox_firmware_dram0 = "/abox@18c50000/abox-core@18c55000/abox-firmware-dram0";
|
|
abox_core1 = "/abox@18c50000/abox-core@18c55080";
|
|
abox_firmware_sram1 = "/abox@18c50000/abox-core@18c55080/abox-firmware-sram1";
|
|
abox_firmware_dram1 = "/abox@18c50000/abox-core@18c55080/abox-firmware-dram1";
|
|
abox_rdma_0 = "/abox@18c50000/abox-rdma@18c51000";
|
|
abox_rdma_1 = "/abox@18c50000/abox-rdma@18c51100";
|
|
abox_rdma_2 = "/abox@18c50000/abox-rdma@18c51200";
|
|
abox_rdma_3 = "/abox@18c50000/abox-rdma@18c51300";
|
|
abox_rdma_4 = "/abox@18c50000/abox-rdma@18c51400";
|
|
abox_rdma_5 = "/abox@18c50000/abox-rdma@18c51500";
|
|
abox_rdma_6 = "/abox@18c50000/abox-rdma@18c51600";
|
|
abox_rdma_7 = "/abox@18c50000/abox-rdma@18c51700";
|
|
abox_rdma_8 = "/abox@18c50000/abox-rdma@18c51800";
|
|
abox_rdma_9 = "/abox@18c50000/abox-rdma@18c51900";
|
|
abox_rdma_10 = "/abox@18c50000/abox-rdma@18c51a00";
|
|
abox_rdma_11 = "/abox@18c50000/abox-rdma@18c51b00";
|
|
abox_wdma_0 = "/abox@18c50000/abox-wdma@18c53000";
|
|
abox_wdma_1 = "/abox@18c50000/abox-wdma@18c53100";
|
|
abox_wdma_2 = "/abox@18c50000/abox-wdma@18c53200";
|
|
abox_wdma_3 = "/abox@18c50000/abox-wdma@18c53300";
|
|
abox_wdma_4 = "/abox@18c50000/abox-wdma@18c53400";
|
|
abox_wdma_5 = "/abox@18c50000/abox-wdma@18c53500";
|
|
abox_wdma_6 = "/abox@18c50000/abox-wdma@18c53600";
|
|
abox_wdma_7 = "/abox@18c50000/abox-wdma@18c53700";
|
|
abox_dual_0 = "/abox@18c50000/abox-dual@18c53080";
|
|
abox_dual_1 = "/abox@18c50000/abox-dual@18c53180";
|
|
abox_dual_2 = "/abox@18c50000/abox-dual@18c53280";
|
|
abox_dual_3 = "/abox@18c50000/abox-dual@18c53380";
|
|
abox_dual_4 = "/abox@18c50000/abox-dual@18c53480";
|
|
abox_dual_5 = "/abox@18c50000/abox-dual@18c53580";
|
|
abox_dual_6 = "/abox@18c50000/abox-dual@18c53680";
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abox_dual_7 = "/abox@18c50000/abox-dual@18c53780";
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abox_ddma_0 = "/abox@18c50000/abox-ddma@18c53800";
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abox_ddma_1 = "/abox@18c50000/abox-ddma@18c53900";
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abox_ddma_2 = "/abox@18c50000/abox-ddma@18c53a00";
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abox_ddma_3 = "/abox@18c50000/abox-ddma@18c53b00";
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abox_ddma_4 = "/abox@18c50000/abox-ddma@18c53c00";
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abox_ddma_5 = "/abox@18c50000/abox-ddma@18c53d00";
|
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abox_uaif_0 = "/abox@18c50000/abox-uaif@18c50c00";
|
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abox_uaif_1 = "/abox@18c50000/abox-uaif@18c50c10";
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abox_uaif_2 = "/abox@18c50000/abox-uaif@18c50c20";
|
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abox_uaif_3 = "/abox@18c50000/abox-uaif@18c50c30";
|
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abox_uaif_4 = "/abox@18c50000/abox-uaif@18c50c40";
|
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abox_uaif_5 = "/abox@18c50000/abox-uaif@18c50c50";
|
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abox_uaif_6 = "/abox@18c50000/abox-uaif@18c50c60";
|
|
abox_dsif = "/abox@18c50000/abox-dsif@18c50cf0";
|
|
abox_udma_rd_0 = "/abox@18c50000/abox-udma-rd@18c5c100";
|
|
abox_udma_rd_1 = "/abox@18c50000/abox-udma-rd@18c5c200";
|
|
abox_udma_wr_0 = "/abox@18c50000/abox-udma-wr@18c5c700";
|
|
abox_udma_wr_1 = "/abox@18c50000/abox-udma-wr@18c5c800";
|
|
abox_udma_wr_dual_0 = "/abox@18c50000/abox-udma-wr-dual@18c5c780";
|
|
abox_udma_wr_dual_1 = "/abox@18c50000/abox-udma-wr-dual@18c5c880";
|
|
abox_udma_wr_debug_0 = "/abox@18c50000/abox-udma-wr-debug@18c5cd00";
|
|
abox_effect = "/abox@18c50000/abox-effect@18e2e000";
|
|
abox_debug = "/abox@18c50000/abox-debug@0";
|
|
abox_vss = "/abox@18c50000/abox-vss@0";
|
|
abox_tplg = "/abox@18c50000/abox-tplg@0";
|
|
ext_bin_0 = "/abox@18c50000/ext-bin@0";
|
|
ext_bin_1 = "/abox@18c50000/ext-bin@1";
|
|
ext_bin_2 = "/abox@18c50000/ext-bin@2";
|
|
ext_bin_3 = "/abox@18c50000/ext-bin@3";
|
|
ext_bin_4 = "/abox@18c50000/ext-bin@4";
|
|
ext_bin_5 = "/abox@18c50000/ext-bin@5";
|
|
mailbox_vts = "/mailbox@0x155a0000";
|
|
vts = "/vts@0x15510000";
|
|
vts_dma0 = "/vts@0x15510000/vts_dma@0";
|
|
vts_dma1 = "/vts@0x15510000/vts_dma@1";
|
|
vts_s_lif = "/vts@0x15510000/vts_s_lif@0x15340000";
|
|
displayport_adma = "/dp_dma";
|
|
dp_dma0 = "/dp_dma/dp_dma@0";
|
|
dp_dma1 = "/dp_dma/dp_dma@1";
|
|
ext_26m = "/ext_26m";
|
|
chosen = "/chosen";
|
|
gic = "/interrupt-controller@10200000";
|
|
clock = "/clock-controller@0x1A330000";
|
|
mct_map = "/mct@10040000/mct-map";
|
|
sec_rtc = "/rtc@15920000";
|
|
pmu_system_controller = "/system-controller@15860000";
|
|
iommu_group_dpu = "/iommu_group_dpu";
|
|
iommu_group_mfc = "/iommu_group_mfc";
|
|
iommu_group_is = "/iommu_group_is";
|
|
iommu_group_g2d = "/iommu_group_g2d";
|
|
iommu_group_mscl_smfc = "/iommu_group_mscl_smfc";
|
|
iommu_group_aud = "/iommu_group_aud";
|
|
iommu_group_npu = "/iommu_group_npu";
|
|
iommu_group_vpc = "/iommu_group_vpc";
|
|
pdma0 = "/amba/pdma0@1A510000";
|
|
memlogger = "/samsung,memlogger";
|
|
memlogger_policy = "/samsung,memlog_policy";
|
|
};
|
|
};
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