293 lines
12 KiB
C
Executable file
293 lines
12 KiB
C
Executable file
/****************************************************************************
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*
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* Copyright (c) 2014 - 2020 Samsung Electronics Co., Ltd. All rights reserved
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*
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****************************************************************************/
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#ifndef __MIF_REG_9815_H
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#define __MIF_REG_9815_H
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/*********************************/
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/* PLATFORM register definitions */
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/*********************************/
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#define NUM_MBOX_PLAT 4
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#define NUM_SEMAPHORE 12
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/********************************************/
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/* MAILBOX_AP_WLBT_BASE 0x109F0000 */
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/********************************************/
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#define MCUCTRL 0x000 /* MCU Controller Register */
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#define MAILBOX_WLBT_BASE 0x0000
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#define MAILBOX_WLBT_REG(r) (MAILBOX_WLBT_BASE + (r))
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/* WLBT to AP */
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#define INTGR0 0x008 /* Interrupt Generation Register 0 (r/w) */
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#define INTCR0 0x00C /* Interrupt Clear Register 0 (w) */
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#define INTMR0 0x010 /* Interrupt Mask Register 0 (r/w) */
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#define INTSR0 0x014 /* Interrupt Status Register 0 (r) */
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#define INTMSR0 0x018 /* Interrupt Mask Status Register 0 (r) */
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/* AP to WLBT */
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#define INTGR1 0x01c /* Interrupt Generation Register 1 */
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#define INTCR1 0x020 /* Interrupt Clear Register 1 */
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#define INTMR1 0x024 /* Interrupt Mask Register 1 */
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#define INTSR1 0x028 /* Interrupt Status Register 1 */
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#define INTMSR1 0x02c /* Interrupt Mask Status Register 1 */
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/* Shared register */
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#define ISSR_BASE 0x100 /* IS_Shared_Register Base address */
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#define ISSR(r) (ISSR_BASE + (4 * (r)))
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#define MIF_INIT 0x06c /* MIF_init */
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#define IS_VERSION 0x070 /* Version Information Register */
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/********************************************/
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/* END MAILBOX_AP_WLBT_BASE 0x109F0000 */
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/********************************************/
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/********************************************/
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/* PMU_ALIVE_BASE 0x10860000 */
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/********************************************/
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#define WLBT_STAT 0x0058
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#define WLBT_PWRDN_DONE BIT(0) /* Check WLBT power-down status.*/
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#define WLBT_ACCESS_MIF BIT(4) /* Check whether WLBT accesses MIF domain */
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#define WLBT_DEBUG 0x005C /* MIF sleep, wakeup debugging control */
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#define MASK_CLKREQ_WLBT BIT(8) /* When this field is set to HIGH, ALIVE ignores
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* CLKREQ from WLBT.
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*/
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#define WLBT_CONFIGURATION 0x3900
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#define LOCAL_PWR_CFG BIT(0) /* Control power state 0: Power down 1: Power on */
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#define WLBT_STATUS 0x3904
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#define WLBT_STATUS_BIT0 BIT(0) /* Status 0 : Power down 1 : Power on */
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#define WLBT_STATES 0x3908 /* STATES [7:0] States index for debugging
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* 0x00 : Reset
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* 0x10 : Power up
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* 0x80 : Power down
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* */
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#define WLBT_OPTION 0x390C
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#define WLBT_OPTION_DATA BIT(3)
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#define WLBT_CTRL_NS 0x3910
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#define WLBT_ACTIVE_CLR BIT(8) /* WLBT_ACTIVE_REQ is clear internally on WAKEUP */
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#define WLBT_ACTIVE_EN BIT(7) /* Enable of WIFI_ACTIVE_REQ */
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#define SW_TCXO_REQ BIT(6) /* SW TCXO Request register, if MASK_TCXO_REQ
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* filed value is 1, This register value control TCXO Request*/
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#define MASK_TCXO_REQ BIT(5) /* 1:mask TCXO_REQ coming from CP,
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* 0:enable request source
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*/
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#define TCXO_GATE BIT(4) /* TCXO gate control 0: TCXO enabled 1: TCXO gated */
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#define RTC_OUT_EN BIT(0) /* RTC output enable 0:Disable 1:Enable */
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#define WLBT_CTRL_S 0x3914 /* WLBT Control SFR secure */
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#define WLBT_START BIT(3) /* CP control enable 0: Disable 1: Enable */
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#define WLBT_OUT 0x3920
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#define INISO_EN BIT(19)
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#define TCXO_ACK BIT(18)
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#define PWR_ACK BIT(17)
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#define INTREQ_ACTIVE BIT(14)
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#define SWEEPER_BYPASS BIT(13) /* SWEEPER bypass mode control(WLBT2AP path) If
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* this bit is set to 1, SWEEPER is bypass mode.
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*/
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#define SWEEPER_PND_CLR_REQ BIT(7) /* SWEEPER_CLEAN Request. SWPPER is the IP
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* that can clean up hung transaction in the Long hop
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* async Bus Interface, when <SUBSYS> get hung
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* state. 0: Normal 1: SWEEPER CLEAN Requested
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*/
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#define WLBT_IN 0x3924
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#define SHIFTING_DONE_OTP_BLK BIT(5) /* OTP shifting controls feedback 0:None 1:Shifting done */
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#define BUS_READY BIT(4) /* BUS ready indication signal when reset released. 0:
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* Normal 1: BUS ready state */
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#define PWRDOWN_IND BIT(2) /* PWRDOWN state indication 0: Normal 1: In the
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* power down state */
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#define SWEEPER_PND_CLR_ACK BIT(0) /* SWEEPER_CLEAN ACK signal. SWPPER is the IP
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* that can clean up hung transaction in the Long hop
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* async Bus Interface, when <SUBSYS> get hung
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* state. 0: Normal 1: SWEEPER CLEAN
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* Acknowledged */
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#define WLBT_INT_IN 0x3940
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#define PWR_REQ_R BIT(2)
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#define PWR_REQ_F BIT(3)
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#define TCXO_REQ_R BIT(4)
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#define TCXO_REQ_F BIT(5)
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#define WLBT_INT_EN 0x3944
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#define WLBT_INT_TYPE 0x3948
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#define WLBT_INT_DIR 0x394c
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/* TODO: check if this is needed in Orange */
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#define WAKEUP_INT_IN 0x3c40
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#define WAKEUP_INT_EN 0x3c44
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#define WAKEUP_INT_TYPE 0x3c48
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#define RESETREQ_WLBT BIT(18) /* Interrupt type 0:Edge, 1:Level */
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/* New access type : set-bit-atomic
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* write at Base_addr + (offset|0xc0000) "value"
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* then only Base_addr+offset's "value" bit will be updated.
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* changed method from 'write' to 'set-bit-atomic'
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* Add SYSTEM_OUT_ATOMIC for (offset|0xC000)
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* updated PWRRGTON_WLBT BIT(27) -> 0x1B (27)
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*/
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#define SYSTEM_OUT 0x3d20
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#define SYSTEM_OUT_ATOMIC_CMD ((SYSTEM_OUT) | (0xC000))
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#define PWRRGTON_WLBT_CMD 0x1B /* 27 for update 27th bit */
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/********************************************/
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/* END PMU_ALIVE_BASE 0x10860000 */
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/********************************************/
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/********************************************/
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/* PBUS_BASE 0x15A00000 */
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/********************************************/
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#define PADDR_WLBT_PBUS_BASE 0x00000
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/*********************************/
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/*********************************/
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#define WLBT_PBUS_D_TZPC_SFR 0x10000
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/*********************************/
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/*********************************/
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/* REGISTERS */
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#define WLBT_PBUS_BAAW_DBUS 0x0
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#define BAAW_D_WLBT_START ((WLBT_PBUS_BAAW_DBUS) + 0x0)
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#define BAAW_D_WLBT_END ((WLBT_PBUS_BAAW_DBUS) + 0x4)
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#define BAAW_D_WLBT_REMAP ((WLBT_PBUS_BAAW_DBUS) + 0x8)
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#define BAAW_D_WLBT_INIT_DONE ((WLBT_PBUS_BAAW_DBUS) + 0xc)
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/* VALUES */
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#define WLBT_DBUS_BAAW_0_START 0x80000000 /* Start of DRAM for WLBT R7 */
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#if IS_ENABLED(CONFIG_SCSC_MEMLOG)
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#define WLBT_DBUS_BAAW_0_END 0x80800000 /* 8 MB */
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#define WLBT_DBUS_BAAW_1_START (WLBT_DBUS_BAAW_0_END) /* Start of DRAM for sable */
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#define WLBT_DBUS_BAAW_1_END (WLBT_DBUS_BAAW_1_START + 0x800000) /* 8MB */
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#else
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#define WLBT_DBUS_BAAW_0_END 0x81000000
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#endif
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/* TODO document says SET only 0 bit 0xC init done */
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#define WLBT_BAAW_CON_INIT_DONE (1 << 31)
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#define WLBT_BAAW_CON_EN_WRITE (1 << 1)
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#define WLBT_BAAW_CON_EN_READ (1 << 0)
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#define WLBT_BAAW_ACCESS_CTRL (WLBT_BAAW_CON_INIT_DONE | WLBT_BAAW_CON_EN_WRITE | WLBT_BAAW_CON_EN_READ)
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/*********************************/
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/*********************************/
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#define WLBT_PBUS_BAAW_CBUS 0x0
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/* REGISTERS WLBT_PBUS_BAAW_CBUS0 */
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#define BAAW_C_WLBT_START_0 ((WLBT_PBUS_BAAW_CBUS) + 0x00)
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#define BAAW_C_WLBT_END_0 ((WLBT_PBUS_BAAW_CBUS) + 0x04)
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#define BAAW_C_WLBT_REMAP_0 ((WLBT_PBUS_BAAW_CBUS) + 0x08)
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#define BAAW_C_WLBT_INIT_DONE_0 ((WLBT_PBUS_BAAW_CBUS) + 0x0c)
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/* VALUES */
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#define WLBT_MAILBOX_CP_WLBT_BASE 0x10A20000
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#define WLBT_CBUS_BAAW_0_START 0xA0000000 /* APM_BAAW0: CP */
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#define WLBT_CBUS_BAAW_0_END 0xA0010000
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/* REGISTERS WLBT_PBUS_BAAW_CBUS1 */
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#define BAAW_C_WLBT_START_1 ((WLBT_PBUS_BAAW_CBUS) + 0x10)
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#define BAAW_C_WLBT_END_1 ((WLBT_PBUS_BAAW_CBUS) + 0x14)
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#define BAAW_C_WLBT_REMAP_1 ((WLBT_PBUS_BAAW_CBUS) + 0x18)
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#define BAAW_C_WLBT_INIT_DONE_1 ((WLBT_PBUS_BAAW_CBUS) + 0x1c)
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/* VALUES */
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#define WLBT_MAILBOX_WLBT_CHUB_BASE 0x109D0000
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#define WLBT_CBUS_BAAW_1_START 0xA0010000 /* APM_BAAW1: CHUB, ABOX, AP, APM, GNSS*/
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#define WLBT_CBUS_BAAW_1_END 0xA0060000 /* REGISTERS WLBT_PBUS_BAAW_CBUS2 */
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/* REGISTERS WLBT_PBUS_BAAW_CBUS2 */
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#define BAAW_C_WLBT_START_2 ((WLBT_PBUS_BAAW_CBUS) + 0x20)
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#define BAAW_C_WLBT_END_2 ((WLBT_PBUS_BAAW_CBUS) + 0x24)
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#define BAAW_C_WLBT_REMAP_2 ((WLBT_PBUS_BAAW_CBUS) + 0x28)
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#define BAAW_C_WLBT_INIT_DONE_2 ((WLBT_PBUS_BAAW_CBUS) + 0x2c)
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/* VALUES */
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#define WLBT_GPIO_CMGP_BASE 0x11C30000
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#define WLBT_CBUS_BAAW_2_START 0xA0060000 /* APM BAAW2: GPIO_CMGP */
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#define WLBT_CBUS_BAAW_2_END 0xA0070000 /* REGISTERS WLBT_PBUS_BAAW_CBUS3 */
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/* REGISTERS WLBT_PBUS_BAAW_CBUS3 */
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#define BAAW_C_WLBT_START_3 ((WLBT_PBUS_BAAW_CBUS) + 0x30)
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#define BAAW_C_WLBT_END_3 ((WLBT_PBUS_BAAW_CBUS) + 0x34)
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#define BAAW_C_WLBT_REMAP_3 ((WLBT_PBUS_BAAW_CBUS) + 0x38)
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#define BAAW_C_WLBT_INIT_DONE_3 ((WLBT_PBUS_BAAW_CBUS) + 0x3c)
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/* VALUES */
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#define WLBT_SYSREG_CMGP2APM_BASE 0x11C60000
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#define WLBT_CBUS_BAAW_3_START 0xA0070000 /* APM BAAW3: CMGP2PMU_APM , PMU_AP, CP, CHUB, GNSS */
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#define WLBT_CBUS_BAAW_3_END 0xA00C0000 /* REGISTERS WLBT_PBUS_BAAW_CBUS4 */
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/* REGISTERS WLBT_PBUS_BAAW_CBUS4 */
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#define BAAW_C_WLBT_START_4 ((WLBT_PBUS_BAAW_CBUS) + 0x40)
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#define BAAW_C_WLBT_END_4 ((WLBT_PBUS_BAAW_CBUS) + 0x44)
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#define BAAW_C_WLBT_REMAP_4 ((WLBT_PBUS_BAAW_CBUS) + 0x48)
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#define BAAW_C_WLBT_INIT_DONE_4 ((WLBT_PBUS_BAAW_CBUS) + 0x4c)
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/* VALUES */
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#define WLBT_SYSREG_CMGP2WLBT_BASE 0x11CB0000
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#define WLBT_CBUS_BAAW_4_START 0xA00C0000 /* APM BAAW4: CMGP2WLBT */
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#define WLBT_CBUS_BAAW_4_END 0xA00D0000 /* REGISTERS WLBT_PBUS_BAAW_CBUS5 */
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/* REGISTERS WLBT_PBUS_BAAW_CBUS5 */
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#define BAAW_C_WLBT_START_5 ((WLBT_PBUS_BAAW_CBUS) + 0x50)
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#define BAAW_C_WLBT_END_5 ((WLBT_PBUS_BAAW_CBUS) + 0x54)
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#define BAAW_C_WLBT_REMAP_5 ((WLBT_PBUS_BAAW_CBUS) + 0x58)
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#define BAAW_C_WLBT_INIT_DONE_5 ((WLBT_PBUS_BAAW_CBUS) + 0x5c)
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/* VALUES */
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#define WLBT_SHUB_USICHUB0_BASE 0x11270000 //Orange3:0xA0 todo SCSC
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#define WLBT_CBUS_BAAW_5_START 0xA00D0000 /* APM BAAW5: USI_CHUB0 */
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#define WLBT_CBUS_BAAW_5_END 0xA0190000
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/* REGISTERS WLBT_PBUS_BAAW_CBUS6 */
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#define BAAW_C_WLBT_START_6 ((WLBT_PBUS_BAAW_CBUS) + 0x60)
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#define BAAW_C_WLBT_END_6 ((WLBT_PBUS_BAAW_CBUS) + 0x64)
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#define BAAW_C_WLBT_REMAP_6 ((WLBT_PBUS_BAAW_CBUS) + 0x68)
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#define BAAW_C_WLBT_INIT_DONE_6 ((WLBT_PBUS_BAAW_CBUS) + 0x6c)
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/* VALUES */
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#define WLBT_SHUB_BASE 0x11300000 //Orange3:0xA0 todo SCSC
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#define WLBT_CBUS_BAAW_6_START 0xA0190000 /* APM BAAW5: CHUB INSR ?????? */
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#define WLBT_CBUS_BAAW_6_END 0xA01C0000
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/*********************************/
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/*********************************/
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#define WLBT_PBUS_SMAPPER 0x40000
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/*********************************/
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/*********************************/
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#define WLBT_PBUS_SYSREG 0x0
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#define PROC_RMP_BOOT ((WLBT_PBUS_SYSREG) + 0x0400)
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#define CHIP_VERSION_ID_OFFSET ((WLBT_PBUS_SYSREG) + 0x0410)
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#define CHIP_VERSION_ID_VER_MASK 0xFFFFFFFF /* [00:31] Version ID */
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#define CHIP_VERSION_ID_IP_PMU 0x0000F000 /* [12:15] PMU ROM Rev */
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#define CHIP_VERSION_ID_IP_MINOR 0x000F0000 /* [16:19] Minor Rev */
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#define CHIP_VERSION_ID_IP_MAJOR 0x00F00000 /* [20:23] Major Rev */
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#define CHIP_VERSION_ID_IP_PMU_SHIFT 12
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#define CHIP_VERSION_ID_IP_MINOR_SHIFT 16
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#define CHIP_VERSION_ID_IP_MAJOR_SHIFT 20
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/*********************************/
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/*********************************/
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#define WLBT_PBUS_BOOT 0x0
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#define PMU_BOOT (WLBT_PBUS_BOOT + 0x0000)
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#define PMU_BOOT_PMU_ACC 0x0 /* PMU has access to KARAM */
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#define PMU_BOOT_AP_ACC 0x1 /* AP has access to KARAM */
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#define PMU_BOOT_ACK (WLBT_PBUS_BOOT + 0x0004)
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#define PMU_BOOT_COMPLETE 0x1 /* Boot ACK complete */
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#define PMU_BOOT_RAM_START (WLBT_PBUS_BOOT + 0x1000)
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#define PMU_BOOT_RAM_END (PMU_BOOT_RAM_START + 0xfff)
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/********************************************/
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/* END PBUS_BASE 0x15A00000 */
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/********************************************/
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/********************************************/
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/* IC3 0x10960000 */
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/********************************************/
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#define VGPIO_TX_MONITOR 0x1700
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#define VGPIO_TX_MON_BIT12 BIT(12)
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/********************************************/
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/* END IC3 0x10960000 */
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/********************************************/
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/* TODO: check TZ stuff*/
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/* TZASC (TrustZone Address Space Controller) configuration for Katmai onwards */
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#define EXYNOS_SET_CONN_TZPC 0
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#define SMC_CMD_CONN_IF (0x82000710)
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#endif /* __MIF_REG_9815_H */
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