16810 lines
1.8 MiB
Executable file
16810 lines
1.8 MiB
Executable file
#include "../../cmucal.h"
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#include "cmucal-sfr.h"
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unsigned int cmucal_sfr_block_size = 50;
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struct sfr_block cmucal_sfr_block_list[] = {
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SFR_BLOCK(CMU_AUD, 0x18c00000, 0x8000),
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SFR_BLOCK(CMU_TOP, 0x1a320000, 0x8000),
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SFR_BLOCK(CMU_CPUCL0, 0x1d040000, 0x8000),
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SFR_BLOCK(CMU_CPUCL1, 0x1d050000, 0x8000),
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SFR_BLOCK(CMU_CPUCL2, 0x1d060000, 0x8000),
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SFR_BLOCK(CMU_DSU, 0x1d030000, 0x8000),
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SFR_BLOCK(CMU_G3DCORE, 0x16c30000, 0x8000),
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SFR_BLOCK(CMU_MIF, 0x1c000000, 0x8000),
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SFR_BLOCK(CMU_S2D, 0x15a30000, 0x8000),
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SFR_BLOCK(CMU_ALIVE, 0x15800000, 0x8000),
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SFR_BLOCK(CMU_CHUB, 0x14800000, 0x8000),
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SFR_BLOCK(CMU_CHUBVTS, 0x15500000, 0x8000),
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SFR_BLOCK(CMU_CMGP, 0x14e00000, 0x8000),
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SFR_BLOCK(CMU_CSIS, 0x17000000, 0x8000),
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SFR_BLOCK(CMU_DNC, 0x16000000, 0x8000),
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SFR_BLOCK(CMU_DSP, 0x16800000, 0x8000),
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SFR_BLOCK(CMU_GNPU, 0x19800000, 0x8000),
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SFR_BLOCK(CMU_HSI0, 0x10a00000, 0x8000),
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SFR_BLOCK(CMU_NOCL0, 0x1a030000, 0x8000),
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SFR_BLOCK(CMU_NOCL1A, 0x1a700000, 0x8000),
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SFR_BLOCK(CMU_NOCL1B, 0x1a400000, 0x8000),
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SFR_BLOCK(CMU_NOCL1C, 0x1a600000, 0x8000),
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SFR_BLOCK(CMU_PERIC0, 0x10400000, 0x8000),
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SFR_BLOCK(CMU_PERIC1, 0x10700000, 0x8000),
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SFR_BLOCK(CMU_PERIC2, 0x11c00000, 0x8000),
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SFR_BLOCK(CMU_SDMA, 0x16b00000, 0x8000),
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SFR_BLOCK(CMU_UFD, 0x15000000, 0x8000),
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SFR_BLOCK(CMU_VTS, 0x15300000, 0x8000),
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SFR_BLOCK(CMU_BRP, 0x17400000, 0x8000),
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SFR_BLOCK(CMU_CPUCL0_GLB, 0x1d020000, 0x8000),
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SFR_BLOCK(CMU_CSTAT, 0x18400000, 0x8000),
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SFR_BLOCK(CMU_DBGCORE, 0x15b30000, 0x8000),
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SFR_BLOCK(CMU_DPUB, 0x19e00000, 0x8000),
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SFR_BLOCK(CMU_DPUF, 0x1ac00000, 0x8000),
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SFR_BLOCK(CMU_DPUF1, 0x1ae00000, 0x8000),
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SFR_BLOCK(CMU_DRCP, 0x17400000, 0x8000),
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SFR_BLOCK(CMU_G3D, 0x16c20000, 0x8000),
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SFR_BLOCK(CMU_HSI1, 0x11200000, 0x8000),
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SFR_BLOCK(CMU_LME, 0x17600000, 0x8000),
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SFR_BLOCK(CMU_M2M, 0x18900000, 0x8000),
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SFR_BLOCK(CMU_MCSC, 0x15c00000, 0x8000),
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SFR_BLOCK(CMU_MFC0, 0x18600000, 0x8000),
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SFR_BLOCK(CMU_MFC1, 0x18800000, 0x8000),
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SFR_BLOCK(CMU_PERIS, 0x10020000, 0x8000),
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SFR_BLOCK(CMU_SSP, 0x18200000, 0x8000),
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SFR_BLOCK(CMU_UFS, 0x11000000, 0x8000),
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SFR_BLOCK(CMU_YUVP, 0x18000000, 0x8000),
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SFR_BLOCK(CMU_ALLCSIS, 0x170e0000, 0x8000),
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SFR_BLOCK(CMU_GNSS, 0x14650000, 0x7000),
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SFR_BLOCK(CMU_STRONG, 0x18300000, 0x8000),
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};
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unsigned int dbg_offset = 0x4000;
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unsigned int cmucal_sfr_size = 4293;
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struct sfr cmucal_sfr_list[] = {
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SFR(PLL_LOCKTIME_PLL_AUD, 0x0, CMU_AUD),
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SFR(PLL_CON3_PLL_AUD, 0x10c, CMU_AUD),
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SFR(PLL_CON8_PLL_AUD, 0x120, CMU_AUD),
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SFR(PLL_LOCKTIME_PLL_MMC, 0x0, CMU_TOP),
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SFR(PLL_CON3_PLL_MMC, 0x10c, CMU_TOP),
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SFR(PLL_CON8_PLL_MMC, 0x120, CMU_TOP),
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SFR(PLL_LOCKTIME_PLL_SHARED0, 0x4, CMU_TOP),
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SFR(PLL_CON3_PLL_SHARED0, 0x14c, CMU_TOP),
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SFR(PLL_CON8_PLL_SHARED0, 0x160, CMU_TOP),
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SFR(PLL_LOCKTIME_PLL_SHARED1, 0x8, CMU_TOP),
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SFR(PLL_CON3_PLL_SHARED1, 0x18c, CMU_TOP),
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SFR(PLL_CON8_PLL_SHARED1, 0x1a0, CMU_TOP),
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SFR(PLL_LOCKTIME_PLL_SHARED2, 0xc, CMU_TOP),
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SFR(PLL_CON3_PLL_SHARED2, 0x1cc, CMU_TOP),
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SFR(PLL_CON8_PLL_SHARED2, 0x1e0, CMU_TOP),
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SFR(PLL_LOCKTIME_PLL_SHARED3, 0x10, CMU_TOP),
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SFR(PLL_CON3_PLL_SHARED3, 0x20c, CMU_TOP),
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SFR(PLL_CON8_PLL_SHARED3, 0x220, CMU_TOP),
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SFR(PLL_LOCKTIME_PLL_SHARED4, 0x14, CMU_TOP),
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SFR(PLL_CON3_PLL_SHARED4, 0x24c, CMU_TOP),
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SFR(PLL_CON8_PLL_SHARED4, 0x260, CMU_TOP),
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SFR(PLL_LOCKTIME_PLL_SHARED_MIF, 0x18, CMU_TOP),
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SFR(PLL_CON3_PLL_SHARED_MIF, 0x28c, CMU_TOP),
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SFR(PLL_CON8_PLL_SHARED_MIF, 0x2a0, CMU_TOP),
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SFR(PLL_LOCKTIME_PLL_CPUCL0, 0x0, CMU_CPUCL0),
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SFR(PLL_CON3_PLL_CPUCL0, 0x10c, CMU_CPUCL0),
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SFR(PLL_CON8_PLL_CPUCL0, 0x120, CMU_CPUCL0),
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SFR(PLL_LOCKTIME_PLL_CPUCL1, 0x0, CMU_CPUCL1),
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SFR(PLL_CON3_PLL_CPUCL1, 0x10c, CMU_CPUCL1),
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SFR(PLL_CON8_PLL_CPUCL1, 0x120, CMU_CPUCL1),
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SFR(PLL_LOCKTIME_PLL_CPUCL2, 0x0, CMU_CPUCL2),
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SFR(PLL_CON3_PLL_CPUCL2, 0x10c, CMU_CPUCL2),
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SFR(PLL_CON8_PLL_CPUCL2, 0x120, CMU_CPUCL2),
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SFR(PLL_LOCKTIME_PLL_DSU, 0x0, CMU_DSU),
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SFR(PLL_CON3_PLL_DSU, 0x10c, CMU_DSU),
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SFR(PLL_CON8_PLL_DSU, 0x120, CMU_DSU),
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SFR(PLL_LOCKTIME_PLL_G3D, 0x0, CMU_G3DCORE),
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SFR(PLL_CON3_PLL_G3D, 0x10c, CMU_G3DCORE),
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SFR(PLL_CON8_PLL_G3D, 0x120, CMU_G3DCORE),
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SFR(PLL_LOCKTIME_PLL_G3D1, 0x4, CMU_G3DCORE),
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SFR(PLL_CON3_PLL_G3D1, 0x14c, CMU_G3DCORE),
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SFR(PLL_CON8_PLL_G3D1, 0x160, CMU_G3DCORE),
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SFR(PLL_LOCKTIME_PLL_MIF_MAIN, 0x0, CMU_MIF),
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SFR(PLL_CON3_PLL_MIF_MAIN, 0x10c, CMU_MIF),
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SFR(PLL_LOCKTIME_PLL_MIF_SUB, 0x4, CMU_MIF),
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SFR(PLL_CON3_PLL_MIF_SUB, 0x14c, CMU_MIF),
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SFR(PLL_LOCKTIME_PLL_MIF_S2D, 0x0, CMU_S2D),
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SFR(PLL_CON3_PLL_MIF_S2D, 0x10c, CMU_S2D),
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SFR(CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC, 0x1028, CMU_ALIVE),
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SFR(CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC, 0x1008, CMU_ALIVE),
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SFR(CLK_CON_MUX_MUX_CLK_ALIVE_NOC, 0x1034, CMU_ALIVE),
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SFR(CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI, 0x100c, CMU_ALIVE),
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SFR(CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI, 0x1004, CMU_ALIVE),
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SFR(CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC, 0x1010, CMU_ALIVE),
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SFR(CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC, 0x1014, CMU_ALIVE),
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SFR(CLK_CON_MUX_MUX_CLK_ALIVE_TIMER, 0x1040, CMU_ALIVE),
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SFR(CLK_CON_MUX_MUX_CLK_ALIVE_SPMI, 0x103c, CMU_ALIVE),
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SFR(CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART, 0x1030, CMU_ALIVE),
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SFR(CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC, 0x101c, CMU_ALIVE),
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SFR(CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC, 0x1020, CMU_ALIVE),
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SFR(CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC, 0x1024, CMU_ALIVE),
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SFR(CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB, 0x1038, CMU_ALIVE),
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SFR(CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC, 0x1018, CMU_ALIVE),
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SFR(CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC, 0x1044, CMU_ALIVE),
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SFR(CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC, 0x1048, CMU_ALIVE),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0x102c, CMU_AUD),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0x1028, CMU_AUD),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0x1024, CMU_AUD),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0x1020, CMU_AUD),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_CPU, 0x1004, CMU_AUD),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_DSIF, 0x1008, CMU_AUD),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0x1030, CMU_AUD),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0x1034, CMU_AUD),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0x1038, CMU_AUD),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_NOC, 0x100c, CMU_AUD),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_PCMC, 0x1010, CMU_AUD),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_AUDIF, 0x1000, CMU_AUD),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_SCLK, 0x1014, CMU_AUD),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF, 0x1018, CMU_AUD),
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SFR(CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_CORE, 0x101c, CMU_AUD),
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SFR(CLK_CON_MUX_MUX_CHUB_TIMER, 0x1000, CMU_CHUB),
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SFR(CLK_CON_MUX_MUX_CLK_CHUB_USI0, 0x1018, CMU_CHUB),
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SFR(CLK_CON_MUX_MUX_CLK_CHUB_USI1, 0x101c, CMU_CHUB),
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SFR(CLK_CON_MUX_MUX_CLK_CHUB_USI3, 0x1024, CMU_CHUB),
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SFR(CLK_CON_MUX_MUX_CLK_CHUB_I2C, 0x1008, CMU_CHUB),
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SFR(CLK_CON_MUX_MUX_CLK_CHUB_USI2, 0x1020, CMU_CHUB),
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SFR(CLK_CON_MUX_MUX_CLK_CHUB_SPI_MS_CTRL, 0x1014, CMU_CHUB),
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SFR(CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C0, 0x100c, CMU_CHUB),
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SFR(CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C1, 0x1010, CMU_CHUB),
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SFR(CLK_CON_MUX_MUX_CLK_CHUB_NOC, 0x1004, CMU_CHUB),
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SFR(CLK_CON_MUX_MUX_CLK_CHUBVTS_DMAILBOX_CCLK, 0x1000, CMU_CHUBVTS),
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SFR(CLK_CON_MUX_MUX_CLK_CHUBVTS_NOC, 0x1004, CMU_CHUBVTS),
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SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI4, 0x1024, CMU_CMGP),
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SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI0, 0x1014, CMU_CMGP),
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SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI1, 0x1018, CMU_CMGP),
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SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI2, 0x101c, CMU_CMGP),
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SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI3, 0x1020, CMU_CMGP),
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SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI5, 0x1028, CMU_CMGP),
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SFR(CLK_CON_MUX_MUX_CLK_CMGP_USI6, 0x102c, CMU_CMGP),
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SFR(CLK_CON_MUX_MUX_CLK_CMGP_I2C, 0x1000, CMU_CMGP),
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SFR(CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL, 0x1010, CMU_CMGP),
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SFR(CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0, 0x1008, CMU_CMGP),
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SFR(CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1, 0x100c, CMU_CMGP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC, 0x1118, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0, 0x1150, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_DSP_NOC, 0x10f8, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0x10b8, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC, 0x1164, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0x1160, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_BRP_NOC, 0x107c, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC, 0x11b4, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0x1074, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC, 0x10b0, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0x1080, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0x1084, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0x1088, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0x108c, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CMU_CMUREF, 0x11b8, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC, 0x1180, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC, 0x118c, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC, 0x11a0, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0x112c, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC, 0x110c, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC, 0x1068, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC, 0x1128, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD, 0x1154, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP, 0x115c, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0, 0x1178, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0, 0x1184, CMU_TOP),
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SFR(CLK_CON_MUX_CLKCMU_DPUF_NOC, 0x1024, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT, 0x10e8, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0x10bc, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC, 0x111c, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF, 0x10ac, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0x1090, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_DPUF, 0x10e4, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0x10a0, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC, 0x10c8, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC, 0x114c, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU, 0x10cc, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0x1094, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU, 0x10a8, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_M2M_NOC, 0x1140, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT, 0x10dc, CMU_TOP),
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SFR(CLK_CON_MUX_CLKCMU_DPUB_NOC, 0x1020, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_DPUB, 0x10d8, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1, 0x1158, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_LME_NOC, 0x1138, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD, 0x1120, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0x1114, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_AUD_NOC, 0x1078, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY, 0x10c4, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CP_HISPEEDY_CLK, 0x11bc, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1, 0x117c, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1, 0x1188, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_SSP_NOC, 0x11ac, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0x1104, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0, 0x1190, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC, 0x1198, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1, 0x1194, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP, 0x10b4, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH, 0x10fc, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP, 0x1100, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC, 0x10d0, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM, 0x10e0, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_DNC_NOC, 0x10d4, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 0x10c0, CMU_TOP),
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SFR(CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC, 0x11a8, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 0x1098, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC, 0x1174, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CP_SHARED0_CLK, 0x11c0, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CP_SHARED1_CLK, 0x11c4, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CP_SHARED2_CLK, 0x11c8, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM, 0x10a4, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC, 0x11b0, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0, 0x106c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1, 0x1070, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC, 0x119c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 0x109c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0, 0x116c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC, 0x1168, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1, 0x1170, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_LME_LME, 0x1134, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_M2M_FRC, 0x11d8, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0x1148, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD, 0x1130, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_UFS_NOC, 0x11dc, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD, 0x1124, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_AUD_CPU, 0x1008, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_AUD_AUDIF0, 0x1000, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_AUD_AUDIF1, 0x1004, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH, 0x1010, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH, 0x1014, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH, 0x1018, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_DSU_SWITCH, 0x1030, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC, 0x100c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_DNC_NOC, 0x101c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_SDMA_NOC, 0x1058, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_DSP_NOC, 0x102c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_G3D_SWITCH, 0x1034, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_GNPU_NOC, 0x103c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_M2M_NOC, 0x1044, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_M2M_FRC, 0x11cc, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_MCSC_NOC, 0x11d4, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_MCSC_MCSC, 0x11d0, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_NOCL0_NOC, 0x1048, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_NOCL1A_NOC, 0x104c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_NOCL1B_NOC0, 0x1050, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_NOCL1C_NOC, 0x1054, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CP_SHARED0_CLK, 0x1060, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CP_SHARED2_CLK, 0x1064, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CP_HISPEEDY_CLK, 0x105c, CMU_TOP),
|
|
SFR(CLK_CON_MUX_CLKCMU_UFS_MMC_CARD, 0x1040, CMU_TOP),
|
|
SFR(CLK_CON_MUX_MUX_CPUCL0_CMUREF, 0x1018, CMU_CPUCL0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL0_IDLECLKDOWN, 0x100c, CMU_CPUCL0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYMUX, 0x1008, CMU_CPUCL0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYCHAIN, 0x1004, CMU_CPUCL0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL0_POWERIP, 0x1010, CMU_CPUCL0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL0_DDD, 0x1000, CMU_CPUCL0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL0_HTU, 0x101c, CMU_CPUCL0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_0, 0x1024, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CPUCL1_CMUREF, 0x1040, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_0, 0x100c, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_0, 0x1018, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_POWERIP, 0x1030, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_0, 0x1000, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_1, 0x1028, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_1, 0x101c, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_1, 0x1004, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_1, 0x1010, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_2, 0x102c, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_2, 0x1020, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_2, 0x1008, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_2, 0x1014, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_HTU, 0x1044, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CPUCL2_CMUREF, 0x1018, CMU_CPUCL2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL2_IDLECLKDOWN, 0x100c, CMU_CPUCL2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYCHAIN, 0x1004, CMU_CPUCL2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYMUX, 0x1008, CMU_CPUCL2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL2_POWERIP, 0x1010, CMU_CPUCL2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL2_DDD, 0x1000, CMU_CPUCL2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL2_HTU, 0x101c, CMU_CPUCL2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CSIS_NOC, 0x1004, CMU_CSIS),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CSIS_DCPHY, 0x1000, CMU_CSIS),
|
|
SFR(CLK_CON_MUX_MUX_CLK_DNC_NOC, 0x1000, CMU_DNC),
|
|
SFR(CLK_CON_MUX_MUX_CLK_DSP_NOC, 0x1000, CMU_DSP),
|
|
SFR(CLK_CON_MUX_MUX_CLK_DSU_IDLECLKDOWN, 0x100c, CMU_DSU),
|
|
SFR(CLK_CON_MUX_MUX_DSU_CMUREF, 0x1018, CMU_DSU),
|
|
SFR(CLK_CON_MUX_MUX_CLK_DSU_DELAYCHAIN, 0x1004, CMU_DSU),
|
|
SFR(CLK_CON_MUX_MUX_CLK_DSU_DELAYMUX, 0x1008, CMU_DSU),
|
|
SFR(CLK_CON_MUX_MUX_CLK_DSU_POWERIP, 0x1010, CMU_DSU),
|
|
SFR(CLK_CON_MUX_MUX_CLK_DSU_DDD, 0x1000, CMU_DSU),
|
|
SFR(CLK_CON_MUX_MUX_CLK_DSU_HTU, 0x101c, CMU_DSU),
|
|
SFR(CLK_CON_MUX_MUX_CLK_G3D_CORE, 0x1000, CMU_G3DCORE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_G3D_DDD, 0x1004, CMU_G3DCORE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_G3D_DELAYCHAIN, 0x1008, CMU_G3DCORE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_G3D_DELAYMUX, 0x100c, CMU_G3DCORE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_G3D_PLL, 0x1014, CMU_G3DCORE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_GNPU_NOC, 0x1000, CMU_GNPU),
|
|
SFR(CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD, 0x1008, CMU_HSI0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_HSI0_NOC, 0x1000, CMU_HSI0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK, 0x1004, CMU_HSI0),
|
|
SFR(CLK_CON_MUX_MUX_MIF_CMUREF, 0x1000, CMU_MIF),
|
|
SFR(CLK_CON_MUX_MUX_NOCL0_CMUREF, 0x1000, CMU_NOCL0),
|
|
SFR(CLK_CON_MUX_MUX_NOCL1A_CMUREF, 0x1000, CMU_NOCL1A),
|
|
SFR(CLK_CON_MUX_MUX_NOCL1B_CMUREF, 0x1000, CMU_NOCL1B),
|
|
SFR(CLK_CON_MUX_MUX_NOCL1C_CMUREF, 0x1000, CMU_NOCL1C),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC0_USI04, 0x1010, CMU_PERIC0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC0_I2C, 0x1000, CMU_PERIC0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT, 0x1008, CMU_PERIC1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC1_I2C, 0x1000, CMU_PERIC1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC1_USI07, 0x100c, CMU_PERIC1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC1_USI08, 0x1014, CMU_PERIC1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC1_USI09, 0x101c, CMU_PERIC1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC1_USI10, 0x1020, CMU_PERIC1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL, 0x1004, CMU_PERIC1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C, 0x1010, CMU_PERIC1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C, 0x1018, CMU_PERIC1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC2_I2C, 0x1000, CMU_PERIC2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC2_USI00, 0x100c, CMU_PERIC2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC2_USI01, 0x1014, CMU_PERIC2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC2_USI02, 0x101c, CMU_PERIC2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC2_USI03, 0x1020, CMU_PERIC2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC2_USI05, 0x1024, CMU_PERIC2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC2_USI06, 0x1028, CMU_PERIC2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL, 0x1004, CMU_PERIC2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC2_USI11, 0x102c, CMU_PERIC2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG, 0x1008, CMU_PERIC2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C, 0x1010, CMU_PERIC2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C, 0x1018, CMU_PERIC2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_S2D_CORE, 0x1000, CMU_S2D),
|
|
SFR(CLK_CON_MUX_MUX_CLK_SDMA_NOC, 0x1000, CMU_SDMA),
|
|
SFR(CLK_CON_MUX_MUX_CLK_UFD_NOC, 0x1000, CMU_UFD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD, 0x100c, CMU_VTS),
|
|
SFR(CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1, 0x1000, CMU_VTS),
|
|
SFR(CLK_CON_MUX_MUX_CLK_VTS_NOC, 0x1004, CMU_VTS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_ALIVE_NOC_USER, 0x600, CMU_ALIVE),
|
|
SFR(PLL_CON1_MUX_CLKCMU_ALIVE_NOC_USER, 0x604, CMU_ALIVE),
|
|
SFR(PLL_CON0_MUX_CLK_RCO_ALIVE_USER, 0x620, CMU_ALIVE),
|
|
SFR(PLL_CON1_MUX_CLK_RCO_ALIVE_USER, 0x624, CMU_ALIVE),
|
|
SFR(PLL_CON0_MUX_CLKMUX_ALIVE_RCO_SPMI_USER, 0x610, CMU_ALIVE),
|
|
SFR(PLL_CON1_MUX_CLKMUX_ALIVE_RCO_SPMI_USER, 0x614, CMU_ALIVE),
|
|
SFR(PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 0x620, CMU_AUD),
|
|
SFR(PLL_CON1_MUX_CLKCMU_AUD_CPU_USER, 0x624, CMU_AUD),
|
|
SFR(PLL_CON0_MUX_CLKCMU_AUD_NOC_USER, 0x630, CMU_AUD),
|
|
SFR(PLL_CON1_MUX_CLKCMU_AUD_NOC_USER, 0x634, CMU_AUD),
|
|
SFR(PLL_CON0_MUX_CP_PCMC_CLK_USER, 0x670, CMU_AUD),
|
|
SFR(PLL_CON1_MUX_CP_PCMC_CLK_USER, 0x674, CMU_AUD),
|
|
SFR(PLL_CON0_MUX_CLK_AUD_RCO_USER, 0x660, CMU_AUD),
|
|
SFR(PLL_CON1_MUX_CLK_AUD_RCO_USER, 0x664, CMU_AUD),
|
|
SFR(PLL_CON0_MUX_CLKCMU_AUD_AUDIF0_USER, 0x600, CMU_AUD),
|
|
SFR(PLL_CON1_MUX_CLKCMU_AUD_AUDIF0_USER, 0x604, CMU_AUD),
|
|
SFR(PLL_CON0_MUX_CLKCMU_AUD_AUDIF1_USER, 0x610, CMU_AUD),
|
|
SFR(PLL_CON1_MUX_CLKCMU_AUD_AUDIF1_USER, 0x614, CMU_AUD),
|
|
SFR(PLL_CON0_MUX_CLKVTS_AUD_DMIC0_USER, 0x640, CMU_AUD),
|
|
SFR(PLL_CON1_MUX_CLKVTS_AUD_DMIC0_USER, 0x644, CMU_AUD),
|
|
SFR(PLL_CON0_MUX_CLKVTS_AUD_DMIC1_USER, 0x650, CMU_AUD),
|
|
SFR(PLL_CON1_MUX_CLKVTS_AUD_DMIC1_USER, 0x654, CMU_AUD),
|
|
SFR(PLL_CON0_MUX_CLKCMU_BRP_NOC_USER, 0x600, CMU_BRP),
|
|
SFR(PLL_CON1_MUX_CLKCMU_BRP_NOC_USER, 0x604, CMU_BRP),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_CHUB_NOC_USER, 0x600, CMU_CHUB),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_CHUB_NOC_USER, 0x604, CMU_CHUB),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_CHUB_PERI_USER, 0x610, CMU_CHUB),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_CHUB_PERI_USER, 0x614, CMU_CHUB),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_CHUB_RCO_USER, 0x620, CMU_CHUB),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_CHUB_RCO_USER, 0x624, CMU_CHUB),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_CHUBVTS_NOC_USER, 0x600, CMU_CHUBVTS),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_CHUBVTS_NOC_USER, 0x604, CMU_CHUBVTS),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_CHUBVTS_RCO_USER, 0x610, CMU_CHUBVTS),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_CHUBVTS_RCO_USER, 0x614, CMU_CHUBVTS),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_CMGP_NOC_USER, 0x610, CMU_CMGP),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_CMGP_NOC_USER, 0x614, CMU_CMGP),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_CMGP_PERI_USER, 0x620, CMU_CMGP),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_CMGP_PERI_USER, 0x624, CMU_CMGP),
|
|
SFR(PLL_CON0_MUX_CP_MPLL_CLK_USER, 0x610, CMU_TOP),
|
|
SFR(PLL_CON1_MUX_CP_MPLL_CLK_USER, 0x614, CMU_TOP),
|
|
SFR(PLL_CON0_MUX_CP_MPLL_CLK_D2_USER, 0x600, CMU_TOP),
|
|
SFR(PLL_CON1_MUX_CP_MPLL_CLK_D2_USER, 0x604, CMU_TOP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 0x610, CMU_CPUCL0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER, 0x614, CMU_CPUCL0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER, 0x600, CMU_CPUCL0_GLB),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_NOC_USER, 0x604, CMU_CPUCL0_GLB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, 0x610, CMU_CPUCL0_GLB),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, 0x614, CMU_CPUCL0_GLB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 0x610, CMU_CPUCL1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER, 0x614, CMU_CPUCL1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER, 0x610, CMU_CPUCL2),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER, 0x614, CMU_CPUCL2),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CSIS_DCPHY_USER, 0x620, CMU_CSIS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CSIS_DCPHY_USER, 0x624, CMU_CSIS),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_CSIS_RCO_USER, 0x610, CMU_CSIS),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_CSIS_RCO_USER, 0x614, CMU_CSIS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER, 0x630, CMU_CSIS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CSIS_NOC_USER, 0x634, CMU_CSIS),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_CSIS_NOC_USER, 0x600, CMU_CSIS),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_CSIS_NOC_USER, 0x604, CMU_CSIS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER, 0x640, CMU_CSIS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CSIS_OIS_MCU_USER, 0x644, CMU_CSIS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_CSTAT_NOC_USER, 0x600, CMU_CSTAT),
|
|
SFR(PLL_CON1_MUX_CLKCMU_CSTAT_NOC_USER, 0x604, CMU_CSTAT),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_DBGCORE_NOC_USER, 0x600, CMU_DBGCORE),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_DBGCORE_NOC_USER, 0x604, CMU_DBGCORE),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DNC_NOC_USER, 0x620, CMU_DNC),
|
|
SFR(PLL_CON1_MUX_CLKCMU_DNC_NOC_USER, 0x624, CMU_DNC),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_DNC_RCO_USER, 0x610, CMU_DNC),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_DNC_RCO_USER, 0x614, CMU_DNC),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_DNC_NOC_USER, 0x600, CMU_DNC),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_DNC_NOC_USER, 0x604, CMU_DNC),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DPUB_NOC_USER, 0x610, CMU_DPUB),
|
|
SFR(PLL_CON1_MUX_CLKCMU_DPUB_NOC_USER, 0x614, CMU_DPUB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DPUB_DSIM_USER, 0x600, CMU_DPUB),
|
|
SFR(PLL_CON1_MUX_CLKCMU_DPUB_DSIM_USER, 0x604, CMU_DPUB),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DPUF_NOC_USER, 0x600, CMU_DPUF),
|
|
SFR(PLL_CON1_MUX_CLKCMU_DPUF_NOC_USER, 0x604, CMU_DPUF),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DPUF1_NOC_USER, 0x600, CMU_DPUF1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_DPUF1_NOC_USER, 0x604, CMU_DPUF1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DRCP_NOC_USER, 0x600, CMU_DRCP),
|
|
SFR(PLL_CON1_MUX_CLKCMU_DRCP_NOC_USER, 0x604, CMU_DRCP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DSP_NOC_USER, 0x600, CMU_DSP),
|
|
SFR(PLL_CON1_MUX_CLKCMU_DSP_NOC_USER, 0x604, CMU_DSP),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_DSP_RCO_USER, 0x620, CMU_DSP),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_DSP_RCO_USER, 0x624, CMU_DSP),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_DSP_NOC_USER, 0x610, CMU_DSP),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_DSP_NOC_USER, 0x614, CMU_DSP),
|
|
SFR(PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER, 0x610, CMU_DSU),
|
|
SFR(PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER, 0x614, CMU_DSU),
|
|
SFR(PLL_CON0_MUX_CLKCMU_G3D_NOCP_USER, 0x600, CMU_G3D),
|
|
SFR(PLL_CON1_MUX_CLKCMU_G3D_NOCP_USER, 0x604, CMU_G3D),
|
|
SFR(PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 0x600, CMU_G3DCORE),
|
|
SFR(PLL_CON1_MUX_CLKCMU_G3D_SWITCH_USER, 0x604, CMU_G3DCORE),
|
|
SFR(PLL_CON0_MUX_CLKCMU_GNPU_NOC_USER, 0x620, CMU_GNPU),
|
|
SFR(PLL_CON1_MUX_CLKCMU_GNPU_NOC_USER, 0x624, CMU_GNPU),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_GNPU_NOC_USER, 0x600, CMU_GNPU),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_GNPU_NOC_USER, 0x604, CMU_GNPU),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_GNPU_RCO_USER, 0x610, CMU_GNPU),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_GNPU_RCO_USER, 0x614, CMU_GNPU),
|
|
SFR(PLL_CON0_MUX_CLKCMU_HSI0_DPOSC_USER, 0x620, CMU_HSI0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_HSI0_DPOSC_USER, 0x624, CMU_HSI0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, 0x630, CMU_HSI0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER, 0x634, CMU_HSI0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_HSI0_USB32DRD_USER, 0x640, CMU_HSI0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_HSI0_USB32DRD_USER, 0x644, CMU_HSI0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER, 0x610, CMU_HSI0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER, 0x614, CMU_HSI0),
|
|
SFR(PLL_CON0_MUX_CLKAUD_HSI0_NOC_USER, 0x600, CMU_HSI0),
|
|
SFR(PLL_CON1_MUX_CLKAUD_HSI0_NOC_USER, 0x604, CMU_HSI0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER, 0x610, CMU_HSI1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_HSI1_NOC_USER, 0x614, CMU_HSI1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER, 0x620, CMU_HSI1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER, 0x624, CMU_HSI1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_LME_NOC_USER, 0x610, CMU_LME),
|
|
SFR(PLL_CON1_MUX_CLKCMU_LME_NOC_USER, 0x614, CMU_LME),
|
|
SFR(PLL_CON0_MUX_CLKCMU_LME_LME_USER, 0x600, CMU_LME),
|
|
SFR(PLL_CON1_MUX_CLKCMU_LME_LME_USER, 0x604, CMU_LME),
|
|
SFR(PLL_CON0_MUX_CLKCMU_M2M_NOC_USER, 0x600, CMU_M2M),
|
|
SFR(PLL_CON1_MUX_CLKCMU_M2M_NOC_USER, 0x604, CMU_M2M),
|
|
SFR(PLL_CON0_MUX_CLKCMU_M2M_FRC_USER, 0x610, CMU_M2M),
|
|
SFR(PLL_CON1_MUX_CLKCMU_M2M_FRC_USER, 0x614, CMU_M2M),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MCSC_NOC_USER, 0x610, CMU_MCSC),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MCSC_NOC_USER, 0x614, CMU_MCSC),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER, 0x600, CMU_MCSC),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER, 0x604, CMU_MCSC),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER, 0x600, CMU_MFC0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MFC0_MFC0_USER, 0x604, CMU_MFC0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER, 0x610, CMU_MFC0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MFC0_WFD_USER, 0x614, CMU_MFC0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER, 0x600, CMU_MFC1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MFC1_MFC1_USER, 0x604, CMU_MFC1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER, 0x610, CMU_MIF),
|
|
SFR(PLL_CON1_MUX_CLKCMU_MIF_NOCP_USER, 0x614, CMU_MIF),
|
|
SFR(PLL_CON0_CLKMUX_MIF_DDRPHY2X, 0x600, CMU_MIF),
|
|
SFR(PLL_CON1_CLKMUX_MIF_DDRPHY2X, 0x604, CMU_MIF),
|
|
SFR(PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER, 0x600, CMU_NOCL0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_NOCL0_NOC_USER, 0x604, CMU_NOCL0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER, 0x600, CMU_NOCL1A),
|
|
SFR(PLL_CON1_MUX_CLKCMU_NOCL1A_NOC_USER, 0x604, CMU_NOCL1A),
|
|
SFR(PLL_CON0_MUX_CLKCMU_NOCL1B_NOC0_USER, 0x600, CMU_NOCL1B),
|
|
SFR(PLL_CON1_MUX_CLKCMU_NOCL1B_NOC0_USER, 0x604, CMU_NOCL1B),
|
|
SFR(PLL_CON0_MUX_CLKCMU_NOCL1B_NOC1_USER, 0x610, CMU_NOCL1B),
|
|
SFR(PLL_CON1_MUX_CLKCMU_NOCL1B_NOC1_USER, 0x614, CMU_NOCL1B),
|
|
SFR(PLL_CON0_MUX_CLKCMU_NOCL1C_NOC_USER, 0x600, CMU_NOCL1C),
|
|
SFR(PLL_CON1_MUX_CLKCMU_NOCL1C_NOC_USER, 0x604, CMU_NOCL1C),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER, 0x620, CMU_PERIC0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER, 0x624, CMU_PERIC0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER, 0x600, CMU_PERIC0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIC0_IP0_USER, 0x604, CMU_PERIC0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER, 0x610, CMU_PERIC0),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIC0_IP1_USER, 0x614, CMU_PERIC0),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, 0x620, CMU_PERIC1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER, 0x624, CMU_PERIC1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER, 0x600, CMU_PERIC1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIC1_IP0_USER, 0x604, CMU_PERIC1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER, 0x610, CMU_PERIC1),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIC1_IP1_USER, 0x614, CMU_PERIC1),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER, 0x600, CMU_PERIC2),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIC2_IP0_USER, 0x604, CMU_PERIC2),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER, 0x610, CMU_PERIC2),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIC2_IP1_USER, 0x614, CMU_PERIC2),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIC2_NOC_USER, 0x620, CMU_PERIC2),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIC2_NOC_USER, 0x624, CMU_PERIC2),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER, 0x610, CMU_PERIS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIS_NOC_USER, 0x614, CMU_PERIS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_PERIS_GIC_USER, 0x600, CMU_PERIS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_PERIS_GIC_USER, 0x604, CMU_PERIS),
|
|
SFR(PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D, 0x600, CMU_S2D),
|
|
SFR(PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D, 0x604, CMU_S2D),
|
|
SFR(PLL_CON0_MUX_CLKCMU_SDMA_NOC_USER, 0x620, CMU_SDMA),
|
|
SFR(PLL_CON1_MUX_CLKCMU_SDMA_NOC_USER, 0x624, CMU_SDMA),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_SDMA_RCO_USER, 0x610, CMU_SDMA),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_SDMA_RCO_USER, 0x614, CMU_SDMA),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_SDMA_NOC_USER, 0x600, CMU_SDMA),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_SDMA_NOC_USER, 0x604, CMU_SDMA),
|
|
SFR(PLL_CON0_MUX_CLKCMU_SSP_NOC_USER, 0x600, CMU_SSP),
|
|
SFR(PLL_CON1_MUX_CLKCMU_SSP_NOC_USER, 0x604, CMU_SSP),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_UFD_NOC_USER, 0x600, CMU_UFD),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_UFD_NOC_USER, 0x604, CMU_UFD),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_UFD_RCO_USER, 0x610, CMU_UFD),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_UFD_RCO_USER, 0x614, CMU_UFD),
|
|
SFR(PLL_CON0_MUX_CLKCMU_UFS_UFS_EMBD_USER, 0x620, CMU_UFS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_UFS_UFS_EMBD_USER, 0x624, CMU_UFS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_UFS_NOC_USER, 0x610, CMU_UFS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_UFS_NOC_USER, 0x614, CMU_UFS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_UFS_MMC_CARD_USER, 0x600, CMU_UFS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_UFS_MMC_CARD_USER, 0x604, CMU_UFS),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_VTS_NOC_USER, 0x600, CMU_VTS),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_VTS_NOC_USER, 0x604, CMU_VTS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER, 0x620, CMU_VTS),
|
|
SFR(PLL_CON1_MUX_CLKCMU_VTS_DMIC_USER, 0x624, CMU_VTS),
|
|
SFR(PLL_CON0_MUX_CLKALIVE_VTS_RCO_USER, 0x610, CMU_VTS),
|
|
SFR(PLL_CON1_MUX_CLKALIVE_VTS_RCO_USER, 0x614, CMU_VTS),
|
|
SFR(PLL_CON0_MUX_CLKCMU_YUVP_NOC_USER, 0x600, CMU_YUVP),
|
|
SFR(PLL_CON1_MUX_CLKCMU_YUVP_NOC_USER, 0x604, CMU_YUVP),
|
|
SFR(CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU, 0x103c, CMU_AUD),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL0_STRMUX, 0x1014, CMU_CPUCL0),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_0, 0x1034, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_1, 0x1038, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_2, 0x103c, CMU_CPUCL1),
|
|
SFR(CLK_CON_MUX_MUX_CLK_CPUCL2_STRMUX, 0x1014, CMU_CPUCL2),
|
|
SFR(CLK_CON_MUX_MUX_CLK_DBGCORE_NOC, 0x1000, CMU_DBGCORE),
|
|
SFR(CLK_CON_MUX_MUX_OSCCLK_DBGCORE, 0x1008, CMU_DBGCORE),
|
|
SFR(CLK_CON_MUX_MUX_FREE_OSCCLK_DBGCORE, 0x1004, CMU_DBGCORE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_DSU_STRMUX, 0x1014, CMU_DSU),
|
|
SFR(CLK_CON_MUX_MUX_CLK_G3D_STRMUX, 0x1010, CMU_G3DCORE),
|
|
SFR(CLK_CON_MUX_MUX_CLK_PERIS_GIC, 0x1000, CMU_PERIS),
|
|
SFR(CLK_CON_DIV_CLKALIVE_UFD_NOC, 0x1824, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_ALIVE_NOC, 0x1830, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_CLKALIVE_CMGP_NOC, 0x1808, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_ALIVE_SPMI, 0x1838, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_CLKALIVE_CMGP_PERI, 0x180c, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART, 0x182c, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_CLKALIVE_CHUB_PERI, 0x1804, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_CLKALIVE_DBGCORE_NOC, 0x1810, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_CLKALIVE_DNC_NOC, 0x1814, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_CLKALIVE_GNPU_NOC, 0x181c, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_CLKALIVE_SDMA_NOC, 0x1820, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB, 0x1834, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC, 0x1818, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_CLKALIVE_CSIS_NOC, 0x183c, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_CLKALIVE_DSP_NOC, 0x1840, CMU_ALIVE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0x1818, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_DSIF, 0x1824, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0x1840, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0x1844, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0x1848, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0x184c, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0x1814, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_NOC, 0x1828, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_NOCP, 0x182c, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_CNT, 0x1810, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0x1850, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0x1854, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0x1858, CMU_AUD),
|
|
SFR(CLK_CON_DIV_CLKAUD_HSI0_NOC, 0x1800, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_PCMC, 0x1830, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0x180c, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF, 0x1838, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_CORE, 0x183c, CMU_AUD),
|
|
SFR(CLK_CON_DIV_CLK_AUD_MCLK, 0x1808, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP, 0x1804, CMU_AUD),
|
|
SFR(CLK_CON_DIV_DIV_CLK_BRP_NOCP, 0x1808, CMU_BRP),
|
|
SFR(CLK_CON_DIV_CLK_BRP_ADD_CH_CLK, 0x1800, CMU_BRP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUB_NOC, 0x1808, CMU_CHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUB_USI0, 0x1818, CMU_CHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUB_USI1, 0x181c, CMU_CHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUB_USI3, 0x1824, CMU_CHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUB_I2C, 0x1804, CMU_CHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUB_USI2, 0x1820, CMU_CHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUB_SPI_MS_CTRL, 0x1814, CMU_CHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C0, 0x180c, CMU_CHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C1, 0x1810, CMU_CHUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUBVTS_NOC, 0x1804, CMU_CHUBVTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CHUBVTS_DMAILBOX_CCLK, 0x1800, CMU_CHUBVTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI4, 0x1824, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI1, 0x1818, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI0, 0x1814, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI2, 0x181c, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI3, 0x1820, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI5, 0x1828, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_USI6, 0x182c, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_I2C, 0x1800, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL, 0x1810, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0, 0x1808, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1, 0x180c, CMU_CMGP),
|
|
SFR(CLK_CON_DIV_CLKCMU_ALIVE_NOC, 0x1800, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_HSI0_DPOSC, 0x1844, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC0_NOC, 0x1890, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIS_NOC, 0x18b0, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT, 0x1934, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MFC0_MFC0, 0x1874, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM, 0x1944, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC1_NOC, 0x189c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM, 0x190c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM, 0x197c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_BRP_NOC, 0x1808, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_YUVP_NOC, 0x18c0, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM, 0x18dc, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM, 0x1904, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0, 0x18e0, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1, 0x18e4, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2, 0x18e8, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3, 0x18ec, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF, 0x1818, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM, 0x1964, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MFC0_WFD, 0x1878, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MIF_NOCP, 0x1880, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC0_IP0, 0x1888, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC1_IP0, 0x1894, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_DPUF, 0x1930, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM, 0x1914, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_HSI0_NOC, 0x1848, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4, 0x18f0, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CMU_BOOST, 0x180c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CSIS_NOC, 0x1824, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM, 0x19d0, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_HSI1_NOC, 0x1850, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU, 0x1828, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5, 0x18f4, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU, 0x1814, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM, 0x1974, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT, 0x192c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_DPUB, 0x1928, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_MFC1_MFC1, 0x187c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_LME_NOC, 0x1860, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM, 0x1984, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_HSI0_USB32DRD, 0x184c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0x1840, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_AUD_NOC, 0x1804, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CSIS_DCPHY, 0x1820, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM, 0x19ac, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CP_SHARED1_CLK, 0x18c4, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM, 0x19a4, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC0_IP1, 0x188c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC1_IP1, 0x1898, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_SSP_NOC, 0x18b8, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM, 0x1954, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC2_NOC, 0x18a8, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC2_IP0, 0x18a0, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIC2_IP1, 0x18a4, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CPUCL0_NOCP, 0x181c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM, 0x194c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_G3D_NOCP, 0x1838, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CSTAT_NOC, 0x182c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_DPUB_DSIM, 0x1830, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM, 0x1924, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM, 0x191c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM, 0x199c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM, 0x19b4, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6, 0x18f8, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM, 0x1994, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM, 0x198c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM, 0x1810, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_VTS_DMIC, 0x18bc, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM, 0x18cc, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM, 0x18d4, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_PERIS_GIC, 0x18ac, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7, 0x18fc, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_NOCL1B_NOC1, 0x1884, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_LME_LME, 0x1834, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM, 0x19c0, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM, 0x19c8, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD, 0x1858, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM, 0x196c, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLKCMU_UFS_NOC, 0x19b8, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_AUD_CPU, 0x18d8, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0, 0x18c8, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1, 0x18d0, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH, 0x1908, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH, 0x1910, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH, 0x1918, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH, 0x1948, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC, 0x1900, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_DNC_NOC, 0x1920, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC, 0x1998, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_DSP_NOC, 0x1940, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH, 0x1950, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC, 0x1960, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_M2M_NOC, 0x1970, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_M2M_FRC, 0x19bc, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC, 0x19cc, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC, 0x19c4, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC, 0x1978, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC, 0x1980, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0, 0x1988, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC, 0x1990, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CP_HISPEEDY_CLK, 0x19a0, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CP_SHARED2_CLK, 0x19b0, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CP_SHARED0_CLK, 0x19a8, CMU_TOP),
|
|
SFR(CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD, 0x1968, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK, 0x1800, CMU_CPUCL0),
|
|
SFR(CLK_CON_DIV_CLK_CPUCL0_DDD, 0x1804, CMU_CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC, 0x1800, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG, 0x1804, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_DIV_CLK_CPUCL1_ADD_CH_CLK, 0x1800, CMU_CPUCL1),
|
|
SFR(CLK_CON_DIV_CLK_CPUCL1_DDD_0, 0x1804, CMU_CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_1, 0x1820, CMU_CPUCL1),
|
|
SFR(CLK_CON_DIV_CLK_CPUCL1_DDD_1, 0x1808, CMU_CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_2, 0x1824, CMU_CPUCL1),
|
|
SFR(CLK_CON_DIV_CLK_CPUCL1_DDD_2, 0x180c, CMU_CPUCL1),
|
|
SFR(CLK_CON_DIV_CLK_CPUCL2_ADD_CH_CLK, 0x1800, CMU_CPUCL2),
|
|
SFR(CLK_CON_DIV_CLK_CPUCL2_DDD, 0x1804, CMU_CPUCL2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CSIS_NOCP, 0x1804, CMU_CSIS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CSIS_DCPHY, 0x1800, CMU_CSIS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CSTAT_NOCP, 0x1808, CMU_CSTAT),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DNC_NOCP, 0x180c, CMU_DNC),
|
|
SFR(CLK_CON_DIV_CLK_DNC_ADD_CH_CLK, 0x1800, CMU_DNC),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DPUB_NOCP, 0x1800, CMU_DPUB),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DPUF_NOCP, 0x1800, CMU_DPUF),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DPUF1_NOCP, 0x1800, CMU_DPUF1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DRCP_NOCP, 0x1804, CMU_DRCP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DSP_NOCP, 0x1804, CMU_DSP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK, 0x180c, CMU_DSU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK, 0x1810, CMU_DSU),
|
|
SFR(CLK_CON_DIV_CLK_DSU_DDD, 0x1800, CMU_DSU),
|
|
SFR(CLK_CON_DIV_CLK_DSU_STR_DEM_CLK, 0x1808, CMU_DSU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER_ACPCLK, 0x1820, CMU_DSU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER_MPCLK, 0x1828, CMU_DSU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CLUSTER_MPACTCLK, 0x1824, CMU_DSU),
|
|
SFR(CLK_CON_DIV_CLK_G3D_ADD_CH_CLK, 0x1800, CMU_G3DCORE),
|
|
SFR(CLK_CON_DIV_CLK_G3D_DDD, 0x1804, CMU_G3DCORE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_GNPU_NOCP, 0x1804, CMU_GNPU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_HSI0_EUSB, 0x1800, CMU_HSI0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_LME_NOCP, 0x1808, CMU_LME),
|
|
SFR(CLK_CON_DIV_DIV_CLK_M2M_NOCP, 0x1800, CMU_M2M),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MCSC_NOCP, 0x1808, CMU_MCSC),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MFC0_NOCP, 0x1800, CMU_MFC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MFC1_NOCP, 0x1800, CMU_MFC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_NOCL0_NOCP, 0x1800, CMU_NOCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP, 0x1800, CMU_NOCL1A),
|
|
SFR(CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP, 0x1800, CMU_NOCL1B),
|
|
SFR(CLK_CON_DIV_DIV_CLK_NOCL1C_NOCP, 0x1800, CMU_NOCL1C),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI04, 0x1810, CMU_PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC0_I2C, 0x1800, CMU_PERIC0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT, 0x1808, CMU_PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_I2C, 0x1800, CMU_PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI07, 0x180c, CMU_PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI08, 0x1814, CMU_PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI09, 0x181c, CMU_PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI10, 0x1820, CMU_PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL, 0x1804, CMU_PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C, 0x1810, CMU_PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C, 0x1818, CMU_PERIC1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC2_I2C, 0x1800, CMU_PERIC2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC2_USI00, 0x180c, CMU_PERIC2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC2_USI01, 0x1814, CMU_PERIC2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC2_USI02, 0x181c, CMU_PERIC2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC2_USI03, 0x1820, CMU_PERIC2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC2_USI05, 0x1824, CMU_PERIC2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC2_USI06, 0x1828, CMU_PERIC2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL, 0x1804, CMU_PERIC2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC2_USI11, 0x182c, CMU_PERIC2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG, 0x1808, CMU_PERIC2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C, 0x1810, CMU_PERIC2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C, 0x1818, CMU_PERIC2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_SDMA_NOCP, 0x1804, CMU_SDMA),
|
|
SFR(CLK_CON_DIV_DIV_CLK_SSP_NOCP, 0x1800, CMU_SSP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF, 0x1814, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2, 0x1818, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_NOC, 0x181c, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF, 0x1820, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE, 0x1824, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_VTS_CPU, 0x1808, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0, 0x1800, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1, 0x1804, CMU_VTS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_YUVP_NOCP, 0x180c, CMU_YUVP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_BRP_NOC, 0x1804, CMU_BRP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_CORE, 0x180c, CMU_CPUCL0),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_0, 0x181c, CMU_CPUCL1),
|
|
SFR(CLK_CON_DIV_DIV_CLK_CPUCL2_CORE, 0x180c, CMU_CPUCL2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DNC_NOC, 0x1808, CMU_DNC),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DRCP_NOC, 0x1800, CMU_DRCP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DSP_NOC, 0x1800, CMU_DSP),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DSU_CLUSTER, 0x181c, CMU_DSU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_G3D_CORE, 0x180c, CMU_G3DCORE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_GNPU_NOC, 0x1800, CMU_GNPU),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MCSC_NOC, 0x1804, CMU_MCSC),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MCSC_MCSC, 0x1800, CMU_MCSC),
|
|
SFR(CLK_CON_DIV_DIV_CLK_SDMA_NOC, 0x1800, CMU_SDMA),
|
|
SFR(CLK_CON_DIV_DIV_CLK_YUVP_NOC, 0x1808, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_GATE_CLKALIVE_UFD_NOC, 0x2160, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK, 0x20d0, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK, 0x2020, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GATE_CLKALIVE_CMGP_NOC, 0x2144, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GATE_CLKALIVE_CMGP_PERI, 0x2148, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, 0x2034, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK, 0x20e0, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK, 0x202c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK, 0x2028, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK, 0x2030, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK, 0x212c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK, 0x2044, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK, 0x2048, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK, 0x204c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK, 0x2054, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, 0x2058, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK, 0x205c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK, 0x211c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK, 0x20ec, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK, 0x20f0, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK, 0x20f8, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK, 0x20fc, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK, 0x2068, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK, 0x2108, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, 0x206c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK, 0x2074, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK, 0x2084, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK, 0x2088, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, 0x208c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, 0x20ac, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK, 0x20c0, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK, 0x20c8, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK, 0x20d4, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK, 0x2120, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK, 0x2124, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK, 0x2130, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK, 0x2134, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK, 0x2138, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK, 0x20cc, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GATE_CLKALIVE_CHUB_PERI, 0x2140, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK, 0x2040, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK, 0x20e8, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK, 0x2070, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK, 0x2078, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK, 0x207c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK, 0x2080, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK, 0x2090, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK, 0x2094, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK, 0x2098, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK, 0x209c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK, 0x20a0, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK, 0x20a4, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK, 0x210c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK, 0x2060, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK, 0x20b0, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK, 0x2100, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK, 0x20f4, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GATE_CLKALIVE_DBGCORE_NOC, 0x214c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GATE_CLKALIVE_DNC_NOC, 0x2150, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK, 0x20d8, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK, 0x2110, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK, 0x2114, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK, 0x2038, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GATE_CLKALIVE_GNPU_NOC, 0x2158, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK, 0x2064, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLKALIVE_GNSS_NOC, 0x2010, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLKALIVE_UFD_RCO, 0x2018, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLKALIVE_DNC_RCO, 0x2004, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLKALIVE_GNPU_RCO, 0x200c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GATE_CLKALIVE_SDMA_NOC, 0x215c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLKALIVE_SDMA_RCO, 0x2014, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, 0x2024, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB, 0x20b4, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK, 0x20a8, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK, 0x2128, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK, 0x203c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK, 0x2118, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK, 0x20dc, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK, 0x20c4, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLKALIVE_CHUBVTS_RCO, 0x2000, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GATE_CLKALIVE_CHUBVTS_NOC, 0x2164, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GATE_CLKALIVE_CSIS_NOC, 0x2168, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLKALIVE_CSIS_RCO, 0x2008, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_GATE_CLKALIVE_DSP_NOC, 0x216c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLKALIVE_DSP_RCO, 0x201c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK, 0x2104, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK, 0x20b8, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK, 0x2154, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2050, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK, 0x20bc, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK, 0x20e4, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK, 0x213c, CMU_ALIVE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_AD_APB_CSIS_WDMA_IPCLKPORT_PCLKM, 0x200c, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA, 0x2018, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_EBUF_BNS, 0x201c, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0, 0x2020, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1, 0x2024, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK, 0x2028, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK, 0x202c, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF_CSISBRP_IPCLKPORT_I_CLK, 0x2048, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF0_BRPCSIS_IPCLKPORT_I_CLK, 0x2030, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK, 0x2038, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF1_BRPCSIS_IPCLKPORT_I_CLK, 0x2034, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK, 0x203c, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK, 0x2040, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK, 0x2044, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK, 0x2050, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK, 0x2054, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK, 0x2058, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK, 0x2064, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_ACLK, 0x2068, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_PCLK, 0x206c, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_ACLK, 0x2070, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_PCLK, 0x2074, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_ACLK, 0x2078, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_PCLK, 0x207c, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_ACLK, 0x2080, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_PCLK, 0x2084, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_ACLK, 0x2088, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_PCLK, 0x208c, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_ACLK, 0x2090, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_PCLK, 0x2094, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_ACLK, 0x2098, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_PCLK, 0x209c, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_ACLK, 0x20a0, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_PCLK, 0x20a4, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_ACLK, 0x20a8, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_PCLK, 0x20ac, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SIU_G_PPMU_CSIS_IPCLKPORT_I_ACLK, 0x20cc, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AST_SI_G_PPMU_CSIS_IPCLKPORT_I_CLK, 0x20d0, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_P0_CSIS_IPCLKPORT_ACLK, 0x2108, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_SI_LP_CSISPERIC2_IPCLKPORT_I_CLK, 0x20d8, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1, 0x20dc, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2, 0x20e0, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1, 0x20e4, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2, 0x20e8, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1, 0x20ec, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2, 0x20f0, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK, 0x20f4, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK, 0x20f8, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK, 0x20fc, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK, 0x2100, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK, 0x2104, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK, 0x20b0, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK, 0x20b4, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK, 0x20c0, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK, 0x20bc, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK, 0x20b8, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK, 0x20c8, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK, 0x20c4, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK, 0x20d4, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK, 0x205c, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK, 0x2060, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_MI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK, 0x204c, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_ALLCSIS_CMU_ALLCSIS_IPCLKPORT_PCLK, 0x2010, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_BLK_CSIS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2014, CMU_ALLCSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK, 0x2060, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK, 0x2000, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ, 0x2004, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT, 0x2008, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF, 0x200c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0, 0x2010, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1, 0x2014, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2, 0x2018, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3, 0x201c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4, 0x2020, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5, 0x2024, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6, 0x2028, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK, 0x202c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK, 0x2030, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB, 0x2034, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32, 0x2038, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP, 0x203c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK, 0x2040, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK0, 0x2044, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM, 0x2050, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM, 0x2054, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM, 0x2058, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK, 0x2064, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_BAAW_D_AUDCHUBVTS_IPCLKPORT_I_PCLK, 0x2068, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK, 0x2098, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_LD_HSI0AUD_IPCLKPORT_I_CLK, 0x2170, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK, 0x2174, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_LH_QDI_SI_D_AUD_IPCLKPORT_I_CLK, 0x209c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK, 0x217c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK, 0x20a0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK, 0x20a4, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK, 0x20a8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK, 0x20ac, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK, 0x20b8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK, 0x20bc, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCD_IPCLKPORT_CLK, 0x20ec, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCP_IPCLKPORT_CLK, 0x20f0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK, 0x20c0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK, 0x20c4, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK, 0x20c8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK, 0x20d0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK, 0x20d4, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK, 0x20d8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK, 0x20e4, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK, 0x20f4, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK, 0x2100, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK, 0x2104, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK, 0x2108, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK, 0x210c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK, 0x2110, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK, 0x2114, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK, 0x2118, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1, 0x2180, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2, 0x2184, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK, 0x2188, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK, 0x218c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK, 0x2190, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK, 0x2198, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK1, 0x2048, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK2, 0x204c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LD_AUDHSI0_IPCLKPORT_I_CLK, 0x2178, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_IPCLKPORT_CLK, 0x20cc, CMU_AUD),
|
|
SFR(CLK_CON_GAT_GATE_CLKAUD_HSI0_NOC, 0x219c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK, 0x2194, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_VGEN_LITE_IPCLKPORT_PCLKM, 0x205c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_CCLK, 0x2164, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK, 0x20f8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK, 0x20fc, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK, 0x206c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_BCLK, 0x2160, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_ACLK, 0x215c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AST_SI_G_PPMU_AUD_IPCLKPORT_I_CLK, 0x216c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK, 0x2074, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK, 0x2078, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK, 0x2080, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK, 0x2084, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK, 0x208c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK, 0x2090, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC0_IPCLKPORT_CLK, 0x20dc, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC1_IPCLKPORT_CLK, 0x20e0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_PCLK, 0x2168, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_PCLK, 0x207c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_PCLK, 0x2094, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_PCLK, 0x2088, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCD_IPCLKPORT_CLK, 0x2130, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK, 0x2128, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK, 0x2140, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK, 0x2144, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK, 0x2148, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK, 0x214c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK, 0x2150, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK, 0x2154, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK, 0x2158, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCP_IPCLKPORT_CLK, 0x2134, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK, 0x213c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK, 0x2138, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC0_IPCLKPORT_CLK, 0x2120, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC1_IPCLKPORT_CLK, 0x2124, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK, 0x211c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK, 0x20e8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK, 0x212c, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_ACLK, 0x21a4, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP, 0x20b4, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK, 0x21b8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_BLK_AUD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x21a0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_SI_PERI_ASB_IPCLKPORT_I_CLK, 0x21b4, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_MI_PERI_ASB_IPCLKPORT_I_CLK, 0x21b0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_PCLK, 0x21ac, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK, 0x21bc, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACP_IPCLKPORT_CLK, 0x21c0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ACP, 0x2070, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ASB, 0x20b0, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_CCLK, 0x21a8, CMU_AUD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_BRP_CMU_BRP_IPCLKPORT_PCLK, 0x2008, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_BYRP_IPCLKPORT_PCLKM, 0x2004, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_D_TZPC_BRP_IPCLKPORT_PCLK, 0x200c, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D0_BRP_IPCLKPORT_I_CLK, 0x2014, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_ACLK, 0x2018, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_PCLK, 0x201c, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCP_IPCLKPORT_CLK, 0x2024, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S1, 0x2044, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSREG_BRP_IPCLKPORT_PCLK, 0x204c, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D0_BRP_IPCLKPORT_ACLK, 0x2054, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AXI_MI_P_BRP_IPCLKPORT_I_CLK, 0x2040, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCD_IPCLKPORT_CLK, 0x2020, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK, 0x2030, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_ZSL, 0x2038, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_BYR, 0x2034, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S2, 0x2048, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_BYRP_IPCLKPORT_CLK, 0x2050, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AST_SI_G_PPMU_BRP_IPCLKPORT_I_CLK, 0x203c, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCD_IPCLKPORT_CLK, 0x202c, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_RGBP_IPCLKPORT_PCLKM, 0x2058, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D1_BRP_IPCLKPORT_I_CLK, 0x2078, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D2_BRP_IPCLKPORT_I_CLK, 0x207c, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S1, 0x20b8, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S2, 0x20bc, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S1, 0x20b0, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S2, 0x20b4, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_ACLK, 0x2084, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_PCLK, 0x2088, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_ACLK, 0x208c, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_PCLK, 0x2090, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK, 0x2094, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF0, 0x2098, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF1, 0x209c, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D1_BRP_IPCLKPORT_ACLK, 0x20c4, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D2_BRP_IPCLKPORT_ACLK, 0x20c8, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_RGBP_IPCLKPORT_CLK, 0x20c0, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF0_BRPCSIS_IPCLKPORT_I_CLK, 0x206c, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_MI_OTF_CSISBRP_IPCLKPORT_I_CLK, 0x2068, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF1_BRPCSIS_IPCLKPORT_I_CLK, 0x2070, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF_BRPMCSC_IPCLKPORT_I_CLK, 0x2074, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_L_SIU_BRP_IPCLKPORT_I_ACLK, 0x2080, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCP_IPCLKPORT_CLK, 0x20a8, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_BLK_BRP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x205c, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_POWERIP_IPCLKPORT_CLK, 0x20ac, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CH_CLK, 0x2010, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CLK, 0x2028, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_CLK_CORE, 0x2060, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_PCLK, 0x2064, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_POWERIP_IPCLKPORT_CLK, 0x20a0, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_FREE_OSCCLK_IPCLKPORT_CLK, 0x20a4, CMU_BRP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK, 0x2030, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK, 0x206c, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_TIMER_IPCLKPORT_CLK, 0x2078, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK, 0x2034, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_MI_IP_VC2CHUB_IPCLKPORT_I_CLK, 0x2094, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_SI_ID_CHUB2VC_IPCLKPORT_I_CLK, 0x209c, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0, 0x2058, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_NOC_IPCLKPORT_CLK, 0x2068, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK, 0x20b8, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK, 0x20c4, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK, 0x20e8, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK, 0x2064, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI0_IPCLKPORT_CLK, 0x207c, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI1_IPCLKPORT_CLK, 0x2080, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI2_IPCLKPORT_CLK, 0x2084, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI3_IPCLKPORT_CLK, 0x2088, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_PCLK, 0x2048, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_PCLK, 0x204c, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK, 0x20cc, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK, 0x20d4, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK, 0x20e4, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK, 0x20dc, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_IPCLK, 0x2044, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_SCLK, 0x2050, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK, 0x20c8, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK, 0x20d0, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK, 0x20d8, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK, 0x20e0, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK, 0x2000, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK, 0x2004, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK, 0x20c0, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK, 0x20bc, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_ASYNCINTERRUPT_IPCLKPORT_CLK, 0x200c, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_DNC_IPCLKPORT_PCLK, 0x2054, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_PCLK, 0x20a4, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_PCLK, 0x20ac, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_MULTI_SLV_Q_CTRL_CHUB_IPCLKPORT_CLK, 0x20b0, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_MS_CTRL_IPCLKPORT_CLK, 0x208c, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK, 0x2060, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_IPCLK, 0x20a0, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_IPCLK, 0x20a8, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C0_IPCLKPORT_CLK, 0x2070, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C1_IPCLKPORT_CLK, 0x2074, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK, 0x2008, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_AXI2AHB_CHUB_IPCLKPORT_CLK, 0x2010, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_ABOX_IPCLKPORT_PCLK, 0x2014, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_NOC_IPCLKPORT_CLK, 0x2020, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_I2C_IPCLKPORT_CLK, 0x201c, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK, 0x2018, CMU_CHUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK, 0x2020, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2VTS_IPCLKPORT_I_CLK, 0x2048, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2CHUB_IPCLKPORT_I_CLK, 0x2044, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SWEEPER_LD_CHUBVTS_IPCLKPORT_ACLK, 0x2078, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK, 0x2070, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_ALIVECHUBVTS_IPCLKPORT_I_CLK, 0x2018, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_CCLK, 0x2030, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_PCLK, 0x2034, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_ACLK, 0x202c, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_VTS2VC_IPCLKPORT_I_CLK, 0x2040, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK, 0x2038, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_PDMA_CHUBVTS_IPCLKPORT_ACLK, 0x2050, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_CHUB2VC_IPCLKPORT_I_CLK, 0x203c, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK, 0x206c, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK, 0x2084, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APBIF_UPMU_CHUB_IPCLKPORT_PCLK, 0x2000, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK, 0x207c, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_UPMU_CHUB_ACLK, 0x2028, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_RSTNSYNCH_CLK, 0x2024, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_SI_LD_CHUBVTS_IPCLKPORT_I_CLK, 0x2074, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK, 0x2080, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_DNCCHUBVTS_IPCLKPORT_I_CLK, 0x201c, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK, 0x2068, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_NOC_IPCLKPORT_CLK, 0x2058, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_PDMA_IPCLKPORT_PCLK, 0x2008, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_DMAILBOX_IPCLKPORT_PCLK, 0x2004, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_NOC_IPCLKPORT_CLK, 0x2064, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_FREE_OSCCLK_IPCLKPORT_CLK, 0x2060, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BLK_CHUBVTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2014, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_DMAILBOX_CCLK_IPCLKPORT_CLK, 0x205c, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_LD_CHUBVTS_IPCLKPORT_I_PCLK, 0x2010, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK, 0x204c, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK, 0x200c, CMU_CHUBVTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK, 0x2004, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK, 0x2000, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK, 0x2010, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK, 0x2088, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK, 0x2090, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK, 0x2018, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK, 0x2020, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK, 0x207c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK, 0x2050, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK, 0x206c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK, 0x2070, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK, 0x2074, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK, 0x205c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK, 0x2060, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK, 0x2064, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK, 0x2068, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK, 0x20ac, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK, 0x2098, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK, 0x20a0, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK, 0x20a8, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK, 0x20b0, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK, 0x20b4, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK, 0x20b8, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK, 0x20bc, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK, 0x20c0, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK, 0x20c4, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK, 0x20cc, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK, 0x20c8, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK, 0x209c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK, 0x20a4, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK, 0x2048, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK, 0x2028, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK, 0x2024, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK, 0x2014, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK, 0x201c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK, 0x2030, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK, 0x2038, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK, 0x2034, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK, 0x202c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK, 0x20d4, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK, 0x20d0, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK, 0x20dc, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK, 0x20d8, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK, 0x20e4, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK, 0x20e0, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK, 0x2094, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK, 0x2080, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK, 0x2078, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK, 0x2044, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK, 0x2084, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK, 0x208c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK, 0x2008, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK, 0x200c, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK, 0x2054, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK, 0x2058, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK, 0x2040, CMU_CMGP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC, 0x200c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC, 0x20f0, CMU_TOP),
|
|
SFR(CLK_CON_GAT_CLKCMU_MIF01_SWITCH, 0x2000, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0, 0x212c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC, 0x2104, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT, 0x20ac, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC, 0x2188, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC, 0x2168, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC, 0x2174, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_BRP_NOC, 0x202c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC, 0x21a0, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM, 0x2024, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 0x2108, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 0x2030, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 0x2034, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 0x203c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 0x2038, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD, 0x2130, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP, 0x2138, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0, 0x2160, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0, 0x216c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DPUF, 0x20a8, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC, 0x20f4, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 0x2040, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC, 0x2088, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM, 0x21d8, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU, 0x208c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 0x2044, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM, 0x211c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT, 0x20a0, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DPUB, 0x209c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1, 0x2134, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_LME_NOC, 0x2114, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD, 0x20f8, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 0x20ec, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_AUD_NOC, 0x2028, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY, 0x2084, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CP_SHARED1_CLK, 0x21b4, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1, 0x2164, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1, 0x2170, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_SSP_NOC, 0x2198, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0, 0x2178, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC, 0x2180, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1, 0x217c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_CLKCMU_MIF23_SWITCH, 0x2004, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP, 0x2068, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP, 0x20cc, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC, 0x2090, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM, 0x20a4, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 0x2048, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM, 0x2148, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM, 0x2140, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM, 0x2070, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM, 0x2078, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM, 0x2080, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM, 0x20c8, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM, 0x2064, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM, 0x2098, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM, 0x2194, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM, 0x20e4, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM, 0x20c0, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM, 0x21b0, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM, 0x21a8, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM, 0x20d4, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM, 0x21bc, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM, 0x215c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM, 0x2150, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 0x2050, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU, 0x2058, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF, 0x205c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM, 0x2054, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC, 0x219c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM, 0x2014, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM, 0x201c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC, 0x2184, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 0x204c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1, 0x2154, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_LME_LME, 0x2110, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM, 0x21c8, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM, 0x21d0, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM, 0x2100, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD, 0x210c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_UFS_NOC, 0x21c0, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 0x2020, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0, 0x2010, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1, 0x2018, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 0x206c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 0x2074, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 0x207c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH, 0x20c4, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC, 0x2060, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DNC_NOC, 0x2094, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC, 0x2190, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_DSP_NOC, 0x20bc, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 0x20d0, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC, 0x20e0, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_M2M_NOC, 0x2118, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_M2M_FRC, 0x21c4, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC, 0x21d4, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 0x21cc, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC, 0x213c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC, 0x2144, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0, 0x214c, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC, 0x2158, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CP_HISPEEDY_CLK, 0x21a4, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CP_SHARED2_CLK, 0x21b8, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CP_SHARED0_CLK, 0x21ac, CMU_TOP),
|
|
SFR(CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD, 0x20fc, CMU_TOP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK, 0x2008, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE, 0x200c, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE, 0x2014, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK, 0x202c, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, 0x201c, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK, 0x2010, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK, 0x2018, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK, 0x2028, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK, 0x2004, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CPUCL0_CPM, 0x2038, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX0CLK, 0x2020, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX1CLK, 0x2024, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_STR_CPUCL0_0_IPCLKPORT_DEM_CLK, 0x2030, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_HTU_IPCLKPORT_CLK, 0x2040, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK, 0x203c, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK, 0x2044, CMU_CPUCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM, 0x2000, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK, 0x201c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_IPCLKPORT_PCLKM, 0x2004, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK, 0x2008, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG, 0x2024, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK, 0x2020, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK, 0x2028, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_CLUSTER0_IPCLKPORT_I_CLK, 0x2038, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK, 0x2054, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK, 0x2084, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK, 0x2088, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK, 0x208c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_ETR_IPCLKPORT_I_CLK, 0x2090, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_STM_IPCLKPORT_I_CLK, 0x2094, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK, 0x2098, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK, 0x205c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK, 0x209c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK, 0x20a0, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_ETR_IPCLKPORT_I_CLK, 0x20a4, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_NOCP_IPCLKPORT_CLK, 0x207c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK, 0x2068, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK, 0x2064, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK, 0x206c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK, 0x2074, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK, 0x2070, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK, 0x2080, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, 0x20ac, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK, 0x20b0, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK, 0x20b4, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK, 0x20b8, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK, 0x20bc, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_STM_IPCLKPORT_I_CLK, 0x20a8, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_PMU_PCSM_PM_IPCLKPORT_PCLK, 0x2060, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_0_IPCLKPORT_PCLK_S0, 0x200c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_1_IPCLKPORT_PCLK_S0, 0x2010, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCDSU_IPCLKPORT_I_CLK, 0x2040, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_DDCG3D_IPCLKPORT_I_CLK, 0x2058, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCLIT_IPCLKPORT_I_CLK, 0x2044, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID0_IPCLKPORT_I_CLK, 0x2048, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID1_IPCLKPORT_I_CLK, 0x204c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID2_IPCLKPORT_I_CLK, 0x2050, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCBIG_IPCLKPORT_I_CLK, 0x203c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CFM_CPUCL0_IPCLKPORT_PCLK, 0x2018, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK, 0x2078, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_OTP_DESERIAL_SECJTAG_IPCLKPORT_I_CLK, 0x202c, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BLK_CPUCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2014, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_NOCP_IPCLKPORT_CLK, 0x20d4, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK, 0x2034, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK, 0x20c4, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK, 0x20c8, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK, 0x2030, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK, 0x20d0, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK, 0x20cc, CMU_CPUCL0_GLB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK, 0x2008, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE, 0x200c, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE, 0x2014, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_CLK, 0x2020, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK, 0x203c, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_HTU_IPCLKPORT_CLK, 0x2038, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, 0x201c, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK, 0x2010, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK, 0x2018, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_PCLK, 0x2024, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK, 0x2004, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CPUCL1_CPM0, 0x2050, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CPUCL1_CPM1, 0x2054, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CPUCL1_CPM2, 0x2058, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_CLK, 0x2028, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_PCLK, 0x202c, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_CLK, 0x2030, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_PCLK, 0x2034, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_STR_CPUCL0_1_IPCLKPORT_DEM_CLK, 0x2040, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK, 0x205c, CMU_CPUCL1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK, 0x2008, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE, 0x200c, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE, 0x2014, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK, 0x2020, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK, 0x202c, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_HTU_IPCLKPORT_CLK, 0x2028, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK, 0x2010, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK, 0x2018, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK, 0x2024, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK, 0x2004, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK, 0x201c, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CPUCL2_CPM, 0x2038, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_STR_CPUCL0_2_IPCLKPORT_DEM_CLK, 0x2030, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK, 0x203c, CMU_CPUCL2),
|
|
SFR(CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCD, 0x2000, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCP, 0x2004, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLKCSIS_ALLCSIS_OIC_MCU, 0x2008, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK, 0x2010, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK, 0x2014, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0, 0x201c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1, 0x2020, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2, 0x2024, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3, 0x2028, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4, 0x202c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5, 0x2030, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS6, 0x2034, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_I_FD_ACLK, 0x2054, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS0, 0x2038, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS1, 0x203c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS2, 0x2040, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS4, 0x2048, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS3, 0x2044, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS5, 0x204c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS6, 0x2050, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_XIU_P1_CSIS_IPCLKPORT_ACLK, 0x2078, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_AD_APB_MIPI_PHY_IPCLKPORT_PCLKM, 0x200c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AXI_MI_LP_UFDCSIS_IPCLKPORT_I_CLK, 0x2070, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK, 0x2074, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AST_SI_OTF_CSISUFD_IPCLKPORT_I_CLK, 0x206c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_LH_AXI_MI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK, 0x2018, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_DCPHY_IPCLKPORT_CLK, 0x2058, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK, 0x205c, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK, 0x2060, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCD_IPCLKPORT_CLK, 0x2064, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCP_IPCLKPORT_CLK, 0x2068, CMU_CSIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_CSTAT_CMU_CSTAT_IPCLKPORT_PCLK, 0x2004, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_D_TZPC_CSTAT_IPCLKPORT_PCLK, 0x2008, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_AD_APB_CSTAT0_IPCLKPORT_PCLKM, 0x2000, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AXI_MI_P_CSTAT_IPCLKPORT_I_CLK, 0x204c, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_ACLK, 0x2020, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_PCLK, 0x2024, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S1, 0x2050, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AXI_SI_D_CSTAT_IPCLKPORT_I_CLK, 0x201c, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSREG_CSTAT_IPCLKPORT_PCLK, 0x2058, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_XIU_D_CSTAT_IPCLKPORT_ACLK, 0x2068, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCD_IPCLKPORT_CLK, 0x2028, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCP_IPCLKPORT_CLK, 0x202c, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK, 0x200c, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK, 0x2010, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK, 0x2014, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK, 0x2018, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK, 0x2034, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2RD, 0x2044, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2DS, 0x2040, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S2, 0x2054, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT0_IPCLKPORT_CLK, 0x205c, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT1_IPCLKPORT_CLK, 0x2060, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AST_SI_G_PPMU_CSTAT_IPCLKPORT_I_CLK, 0x2048, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCD_IPCLKPORT_CLK, 0x2030, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCP_IPCLKPORT_CLK, 0x203c, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_CSTAT_UID_BLK_CSTAT_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2038, CMU_CSTAT),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_AHB_BUSMATRIX_DBGCORE_IPCLKPORT_HCLK, 0x2004, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_GREBEINTEGRATION_DBGCORE_IPCLKPORT_HCLK, 0x2018, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_NOC_IPCLKPORT_CLK, 0x202c, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_MI_IP_APM_IPCLKPORT_I_CLK, 0x2030, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK, 0x2034, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK, 0x2038, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_ID_DBGCORE_IPCLKPORT_I_CLK, 0x203c, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_IPCLKPORT_PCLK, 0x2044, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_WDT_DBGCORE_IPCLKPORT_PCLK, 0x2048, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_XHB_DBGCORE_IPCLKPORT_CLK, 0x204c, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_DBGCORE_CMU_DBGCORE_IPCLKPORT_PCLK, 0x2010, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_GREBE_IPCLKPORT_CLK, 0x2028, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_PCLK, 0x2020, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_CORE_IPCLKPORT_PCLK, 0x2040, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_D_TZPC_DBGCORE_IPCLKPORT_PCLK, 0x2014, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_APBIF_S2D_DBGCORE_IPCLKPORT_I_PCLK, 0x2008, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_ASYNCAHBMASTER_DBGCORE_IPCLKPORT_HCLKM, 0x200c, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_OSCCLK, 0x201c, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_FREE_OSCCLK_IPCLKPORT_CLK, 0x2024, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_SR_CLK_DBGCORE_NOC_IPCLKPORT_CLK, 0x2050, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SS_DBGCORE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2054, CMU_DBGCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SHMEM_IPCLKPORT_I_CLK, 0x2058, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU0DNC_SHMEM_IPCLKPORT_I_CLK, 0x2064, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU1DNC_SHMEM_IPCLKPORT_I_CLK, 0x2068, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_DNC_CMU_DNC_IPCLKPORT_PCLK, 0x2034, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU0_IPCLKPORT_I_CLK, 0x2120, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SFR_IPCLKPORT_I_CLK, 0x2054, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU1_IPCLKPORT_I_CLK, 0x2124, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_P_DNC_IPCLKPORT_I_CLK, 0x2138, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU0_IPCLKPORT_I_CLK, 0x20a8, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LP_IPDNC_IPCLKPORT_I_CLK, 0x209c, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU1_IPCLKPORT_I_CLK, 0x20ac, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_IPDNC_IPCLKPORT_I_CLK, 0x20cc, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK, 0x2098, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK, 0x2094, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK, 0x2090, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_ADM_DAP_DNC_IPCLKPORT_DAPCLKM, 0x200c, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK, 0x208c, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU0_IPCLKPORT_I_CLK, 0x204c, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU1_IPCLKPORT_I_CLK, 0x2050, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_DSP0DNC_CACHE_IPCLKPORT_I_CLK, 0x2128, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU0_IPCLKPORT_I_CLK, 0x20a0, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU1_IPCLKPORT_I_CLK, 0x20a4, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_CLK, 0x2048, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_DMA_IPCLKPORT_I_CLK, 0x20b8, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSREG_DNC_IPCLKPORT_PCLK, 0x217c, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_SFR_IPCLKPORT_I_CLK, 0x20bc, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_D_TZPC_DNC_IPCLKPORT_PCLK, 0x2038, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK, 0x2078, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK, 0x2074, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK, 0x2070, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK, 0x206c, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK, 0x2088, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU1_IPCLKPORT_I_CLK, 0x20b4, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK, 0x2084, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU0_IPCLKPORT_I_CLK, 0x20b0, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK, 0x2080, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK, 0x207c, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCD_IPCLKPORT_CLK, 0x2100, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCP_IPCLKPORT_CLK, 0x2104, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_ACLK, 0x20d0, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_PCLK, 0x20d4, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_ACLK, 0x20d8, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_PCLK, 0x20dc, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_ACLK, 0x20e0, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_PCLK, 0x20e4, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_ACLK, 0x20e8, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_PCLK, 0x20ec, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_ACLK, 0x20f0, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_PCLK, 0x20f4, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S1, 0x2154, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S1, 0x215c, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S2, 0x2160, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S2, 0x2158, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S1, 0x2164, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S2, 0x2168, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S1, 0x216c, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S2, 0x2170, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S1, 0x2174, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S2, 0x2178, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_ACLK, 0x2180, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_PCLK, 0x2184, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_APBAS_S1_NS_SDMA0_IPCLKPORT_PCLKM, 0x2010, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_CLK, 0x2040, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_PCLK, 0x2044, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_PCLK, 0x2028, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_PCLK, 0x2020, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_CLK_CORE, 0x201c, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CH_CLK, 0x2004, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK, 0x2140, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_BAAW_DNCCHUBVTS_IPCLKPORT_I_PCLK, 0x2018, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_POWERIP_IPCLKPORT_CLK, 0x2108, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_ATCLK, 0x2024, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CLK, 0x2008, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_DDD_DNC_IPCLKPORT_CK_IN, 0x2030, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_DNCSDMA_IPCLKPORT_I_CLK, 0x20c8, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SIU_G_PPMU_DNC_IPCLKPORT_I_ACLK, 0x2110, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AST_SI_G_PPMU_DNC_IPCLKPORT_I_CLK, 0x2114, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU0_IPCLKPORT_I_CLK, 0x2144, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU1_IPCLKPORT_I_CLK, 0x2148, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LP_ALIVEDNC_IPCLKPORT_I_CLK, 0x2134, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_DNC_IPCLKPORT_CLK, 0x2188, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_LITE_DNC_IPCLKPORT_CLK, 0x218c, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCD_IPCLKPORT_CLK, 0x210c, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_UFDDNC_IPCLKPORT_I_CLK, 0x2130, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK, 0x20fc, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_XIU_P_DNC_IPCLKPORT_ACLK, 0x2190, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_MI_OTF_UFDDNC_IPCLKPORT_I_CLK, 0x211c, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_GLUE_OTF_UFDDNC_IPCLKPORT_CLK, 0x2118, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCP_IPCLKPORT_CLK, 0x2060, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DSP0_IPCLKPORT_I_CLK, 0x20c4, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_SDMA_IPCLKPORT_I_CLK, 0x20f8, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_BLK_DNC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2014, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_POWERIP_IPCLKPORT_CLK, 0x20c0, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK, 0x205c, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_DDD_CTRL_IPCLKPORT_CLK, 0x203c, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_DAPCLK, 0x202c, CMU_DNC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK, 0x2004, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM, 0x2000, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON, 0x2008, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK, 0x2018, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUB_UID_SLH_AXI_MI_P_DPUB_IPCLKPORT_I_CLK, 0x202c, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCD_IPCLKPORT_CLK, 0x201c, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCP_IPCLKPORT_CLK, 0x2020, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK, 0x2030, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM1, 0x2010, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM2, 0x2014, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM0, 0x200c, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUB_UID_UPI_M0_IPCLKPORT_PCLK, 0x2034, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCD_IPCLKPORT_CLK, 0x2028, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCP_IPCLKPORT_CLK, 0x2048, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM0, 0x2038, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM1, 0x203c, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM2, 0x2040, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUB_UID_BLK_DPUB_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2024, CMU_DPUB),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_CMU_DPUF_IPCLKPORT_PCLK, 0x2004, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM, 0x2000, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF0, 0x2008, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF_IPCLKPORT_PCLK, 0x2010, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_MI_P_DPUF_IPCLKPORT_I_CLK, 0x2044, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_LH_AXI_SI_D1_DPUF_IPCLKPORT_I_CLK, 0x201c, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_ACLK, 0x2020, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_PCLK, 0x2024, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_ACLK, 0x2028, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_PCLK, 0x202c, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCD_IPCLKPORT_CLK, 0x2030, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCP_IPCLKPORT_CLK, 0x2034, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S2, 0x2050, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S1, 0x2054, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSREG_DPUF_IPCLKPORT_PCLK, 0x205c, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S1, 0x204c, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S2, 0x2058, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF0, 0x200c, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D0_DPUF_IPCLKPORT_ACLK, 0x2060, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D1_DPUF_IPCLKPORT_ACLK, 0x2064, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_SIU_DPUF_IPCLKPORT_I_ACLK, 0x203c, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AST_SI_G_PPMU_DPUF_IPCLKPORT_I_CLK, 0x2040, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_SI_D0_DPUF_IPCLKPORT_I_CLK, 0x2048, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCD_IPCLKPORT_CLK, 0x2038, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM, 0x2014, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF1, 0x2068, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF1, 0x2070, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_SRAMC, 0x206c, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_ACLK, 0x2080, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_PCLK, 0x2084, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_ACLK, 0x2078, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_PCLK, 0x207c, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S1, 0x208c, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S2, 0x2090, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S1, 0x2094, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S2, 0x2098, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK, 0x2074, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCP_IPCLKPORT_CLK, 0x2088, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF_UID_BLK_DPUF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2018, CMU_DPUF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK, 0x2004, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPUF, 0x2008, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_VOTF, 0x200c, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_AXI_MI_P_DPUF1_IPCLKPORT_I_CLK, 0x2040, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK, 0x201c, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK, 0x2020, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK, 0x2024, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK, 0x2028, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCD_IPCLKPORT_CLK, 0x202c, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCP_IPCLKPORT_CLK, 0x2030, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1, 0x2044, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1, 0x204c, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK, 0x2054, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2, 0x2048, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2, 0x2050, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SIU_DPUF1_IPCLKPORT_I_ACLK, 0x2038, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D0_DPUF1DPUF0_IPCLKPORT_I_CLK, 0x2014, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D1_DPUF1DPUF0_IPCLKPORT_I_CLK, 0x2018, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_ASTL_SI_G_PPMU_DPUF1_IPCLKPORT_I_CLK, 0x203c, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_SR_CLK_DPUF1_NOCD_IPCLKPORT_CLK, 0x2034, CMU_DPUF1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_CMU_DRCP_IPCLKPORT_PCLK, 0x2008, CMU_DRCP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DRCP_UID_AD_APB_DRCP_IPCLKPORT_PCLKM, 0x2004, CMU_DRCP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_IPCLKPORT_CLK, 0x200c, CMU_DRCP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_PCLK, 0x2024, CMU_DRCP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_ACLK, 0x2020, CMU_DRCP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S2, 0x2040, CMU_DRCP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S1, 0x203c, CMU_DRCP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DRCP_UID_D_TZPC_DRCP_IPCLKPORT_PCLK, 0x2010, CMU_DRCP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DRCP_UID_XIU_D_DRCP_IPCLKPORT_ACLK, 0x204c, CMU_DRCP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCD_IPCLKPORT_CLK, 0x2028, CMU_DRCP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCP_IPCLKPORT_CLK, 0x202c, CMU_DRCP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSREG_DRCP_IPCLKPORT_PCLK, 0x2044, CMU_DRCP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_AXI_MI_P_DRCP_IPCLKPORT_I_CLK, 0x2038, CMU_DRCP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_MI_OTF_YUVPDRCP_IPCLKPORT_I_CLK, 0x2014, CMU_DRCP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_SI_OTF_DRCPMCSC_IPCLKPORT_I_CLK, 0x2018, CMU_DRCP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AXI_SI_D_DRCP_IPCLKPORT_I_CLK, 0x201c, CMU_DRCP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DRCP_UID_VGEN_LITE_D_DRCP_IPCLKPORT_CLK, 0x2048, CMU_DRCP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_ASTL_SI_G_PPMU_DRCP_IPCLKPORT_I_CLK, 0x2034, CMU_DRCP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_SR_CLK_DRCP_NOCD_IPCLKPORT_CLK, 0x2030, CMU_DRCP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SHMEM_IPCLKPORT_I_CLK, 0x2020, CMU_DSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK, 0x2004, CMU_DSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCD_IPCLKPORT_CLK, 0x2024, CMU_DSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCP_IPCLKPORT_CLK, 0x2028, CMU_DSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK, 0x2038, CMU_DSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSP_UID_D_TZPC_DSP_IPCLKPORT_PCLK, 0x2008, CMU_DSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_MI_LP_DSP_IPCLKPORT_I_CLK, 0x2030, CMU_DSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_DMA_IPCLKPORT_I_CLK, 0x2014, CMU_DSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_SFR_IPCLKPORT_I_CLK, 0x2018, CMU_DSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_SI_LD_DSPDNC_CACHE_IPCLKPORT_I_CLK, 0x2034, CMU_DSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SFR_IPCLKPORT_I_CLK, 0x201c, CMU_DSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSP_UID_IP_DSP_IPCLKPORT_CLK, 0x200c, CMU_DSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AST_MI_LD_STRM_SDMADSP_IPCLKPORT_I_CLK, 0x2010, CMU_DSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCD_IPCLKPORT_CLK, 0x202c, CMU_DSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCP_IPCLKPORT_CLK, 0x2040, CMU_DSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSP_UID_BLK_DSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x203c, CMU_DSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK, 0x2018, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK, 0x201c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK, 0x2010, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE, 0x2008, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ATB_SI_IT_CLUSTER0_IPCLKPORT_I_CLK, 0x203c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK, 0x2048, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK, 0x2050, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK, 0x2058, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK, 0x2060, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK, 0x206c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK, 0x2074, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK, 0x2070, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK, 0x2078, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_DSU_POWERIP_IPCLKPORT_CLK, 0x207c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK, 0x2028, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK, 0x200c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK, 0x2030, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK, 0x204c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK, 0x2054, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK, 0x205c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK, 0x2064, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D0_CLUSTER0_IPCLKPORT_I_CLK, 0x2040, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D1_CLUSTER0_IPCLKPORT_I_CLK, 0x2044, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_GRAY2BIN_CNTVALUEB_IPCLKPORT_CLK, 0x202c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_SCLK, 0x2024, CMU_DSU),
|
|
SFR(CLK_CON_GAT_DSU_CPM, 0x20a4, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK, 0x2068, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_STR_CPUCL0_3_IPCLKPORT_DEM_CLK, 0x2090, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_HTU_IPCLKPORT_CLK, 0x2100, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK, 0x2084, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_LP_PPU_IPCLKPORT_I_CLK, 0x210c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_PPUWAKEUP_CLUSTER0_IPCLKPORT_CLK, 0x2120, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_UTILITY_IPCLKPORT_ACLK, 0x2128, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_IP_UTILITY_IPCLKPORT_I_CLK, 0x2108, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK, 0x2094, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK, 0x2098, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK, 0x2034, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PPUCLK, 0x2080, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACLK, 0x2014, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK, 0x20c8, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK, 0x20d4, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACLK_IPCLKPORT_CLK, 0x20d8, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK, 0x20e0, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK, 0x20e4, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PCLK_IPCLKPORT_CLK, 0x20f0, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK, 0x20f4, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK, 0x20f8, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_SCLK_IPCLKPORT_CLK, 0x20fc, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK, 0x20c4, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK, 0x20d0, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK, 0x20dc, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_PERIPHERAL_IPCLKPORT_ACLK, 0x2124, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_IP_UTILITY_IPCLKPORT_I_CLK, 0x2110, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D0_ACP_IPCLKPORT_I_CLK, 0x2088, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D1_ACP_IPCLKPORT_I_CLK, 0x208c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_D_CPUCL0_ACP_IPCLKPORT_ACLK, 0x212c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK, 0x2114, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACPCLK, 0x2020, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_MPCLK, 0x2038, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_ACPWAKEUP_CLUSTER0_IPCLKPORT_CLK, 0x2118, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_ACLK, 0x20b4, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_DIVCLK, 0x20b8, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_ACLK, 0x20bc, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_DIVCLK, 0x20c0, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D0_IPCLKPORT_I_CLK, 0x209c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D1_IPCLKPORT_I_CLK, 0x20a8, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D2_IPCLKPORT_I_CLK, 0x20ac, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D3_IPCLKPORT_I_CLK, 0x20b0, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK, 0x20e8, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_POWERIP_IPCLKPORT_CLK, 0x2104, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK, 0x20cc, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_IRITWAKEUP_CLUSTER0_IPCLKPORT_CLK, 0x211c, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK, 0x20ec, CMU_DSU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, 0x2010, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_SI_P_INT_G3D_IPCLKPORT_I_CLK, 0x2024, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, 0x2028, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK, 0x200c, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK, 0x2020, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK, 0x201c, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_CFM_G3D_IPCLKPORT_PCLK, 0x2008, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_BG3D_PWRCTL_IPCLKPORT_CLK, 0x2000, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK, 0x2018, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK, 0x2004, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_NOCP_IPCLKPORT_CLK, 0x2014, CMU_G3D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CLK, 0x2010, CMU_G3DCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CH_CLK, 0x200c, CMU_G3DCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE, 0x2004, CMU_G3DCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3D_POWERIP_IPCLKPORT_CLK, 0x203c, CMU_G3DCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK, 0x2008, CMU_G3DCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_PCLK, 0x2030, CMU_G3DCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_G3DCORE_CMU_G3DCORE_IPCLKPORT_PCLK, 0x2024, CMU_G3DCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_GPU_IPCLKPORT_PCLK, 0x2028, CMU_G3DCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADM_DAP_G_G3D_IPCLKPORT_DAPCLKM, 0x2014, CMU_G3DCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_CLK, 0x202c, CMU_G3DCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_NOCP_IPCLKPORT_CLK, 0x2038, CMU_G3DCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_BUSIF_DDC_G3D_IPCLKPORT_PCLK_S0, 0x2018, CMU_G3DCORE),
|
|
SFR(CLK_CON_GAT_G3DCORE_CPM, 0x2048, CMU_G3DCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK, 0x2034, CMU_G3DCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK, 0x201c, CMU_G3DCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_NOCP_IPCLKPORT_CLK, 0x2020, CMU_G3DCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3D_POWERIP_IPCLKPORT_CLK, 0x2040, CMU_G3DCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_PCLK, 0x2054, CMU_G3DCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_CLK_CORE, 0x204c, CMU_G3DCORE),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNPU_UID_GNPU_CMU_GNPU_IPCLKPORT_PCLK, 0x2008, CMU_GNPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_CORE, 0x200c, CMU_GNPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_SRAM, 0x2010, CMU_GNPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD_CTRL_GNPU_IPCLKPORT_I_CLK, 0x20c8, CMU_GNPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_RQ_GNPU_IPCLKPORT_I_CLK, 0x20cc, CMU_GNPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD1_GNPU_IPCLKPORT_I_CLK, 0x20c4, CMU_GNPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNPU_UID_D_TZPC_GNPU_IPCLKPORT_PCLK, 0x2004, CMU_GNPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_MI_LP_GNPU_IPCLKPORT_I_CLK, 0x20e0, CMU_GNPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_SI_LD_CMDQ_GNPU_IPCLKPORT_I_CLK, 0x20e4, CMU_GNPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNPU_UID_SYSREG_GNPU_IPCLKPORT_PCLK, 0x20e8, CMU_GNPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD0_GNPU_IPCLKPORT_I_CLK, 0x20c0, CMU_GNPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_GNPUDNC_SHMEM_IPCLKPORT_I_CLK, 0x20d0, CMU_GNPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_0_IPCLKPORT_ACLK, 0x20ec, CMU_GNPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_1_IPCLKPORT_ACLK, 0x20f0, CMU_GNPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCD_IPCLKPORT_CLK, 0x20d4, CMU_GNPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCP_IPCLKPORT_CLK, 0x20d8, CMU_GNPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCD_IPCLKPORT_CLK, 0x20dc, CMU_GNPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCP_IPCLKPORT_CLK, 0x2018, CMU_GNPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNPU_UID_BLK_GNPU_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2014, CMU_GNPU),
|
|
SFR(CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK, 0x2004, CMU_GNSS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK, 0x202c, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK, 0x2008, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK, 0x2014, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK, 0x2004, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK, 0x200c, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK, 0x2010, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK, 0x2034, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK, 0x2028, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK, 0x2038, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK, 0x201c, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK, 0x2018, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK, 0x2024, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2, 0x2040, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK, 0x2044, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK, 0x2064, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK, 0x2058, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK, 0x205c, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK, 0x2068, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK, 0x206c, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK, 0x2060, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40, 0x2054, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK, 0x2030, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK, 0x2048, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK, 0x2070, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK, 0x2050, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK, 0x204c, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM, 0x2000, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK, 0x2020, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK, 0x207c, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK, 0x2074, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK, 0x2080, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x203c, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK, 0x2078, CMU_HSI0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_A_G2X1_PHY_REFCLK_IN, 0x2040, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK, 0x2004, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK, 0x200c, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK, 0x2090, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK, 0x2014, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, 0x2020, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PIPE_PAL_GEN2_X1_PCIE_INST_0_I_APB_PCLK, 0x2034, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 0x202c, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, 0x2024, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, 0x2048, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, 0x204c, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, 0x2050, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 0x2044, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PHY_UDBG_I_APB_PCLK, 0x2054, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK, 0x2058, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK, 0x206c, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK, 0x2074, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK, 0x2070, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK, 0x207c, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1, 0x2098, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK, 0x20a0, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK, 0x20b0, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK, 0x20b4, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK, 0x20b8, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK, 0x2010, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK, 0x2068, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, 0x2028, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SUB_CTRL_A_G3X2_PHY_REFCLK_IN, 0x2064, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2, 0x209c, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_SF_PCIEPHY_X1_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, 0x2038, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AST_SI_G_PPMU_HSI1_IPCLKPORT_I_CLK, 0x208c, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_NOC_IPCLKPORT_CLK, 0x2088, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SOC_CTRL_GEN3A_IPCLK, 0x2060, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_SF_PCIEPHY_X2_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, 0x205c, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PHY_UDBG_I_APB_PCLK, 0x2030, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK, 0x2078, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK, 0x2084, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SOC_CTRL_GEN2_IPCLK, 0x203c, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_BLK_HSI1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2000, CMU_HSI1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK, 0x2024, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_LH_ACEL_SI_D_LME_IPCLKPORT_I_CLK, 0x2020, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_PCLK, 0x203c, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_ACLK, 0x2038, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AXI_MI_P_LME_IPCLKPORT_I_CLK, 0x2070, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK, 0x207c, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK, 0x2018, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1, 0x2074, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK, 0x2084, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCD_IPCLKPORT_CLK, 0x205c, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCP_IPCLKPORT_CLK, 0x2060, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_ACLK, 0x2050, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_PCLK, 0x2054, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2, 0x2078, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AST_SI_G_PPMU_LME_IPCLKPORT_I_CLK, 0x206c, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_LME_IPCLKPORT_CLK, 0x2030, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCD_IPCLKPORT_CLK, 0x2040, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM, 0x2004, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_GDC_IPCLKPORT_PCLKM, 0x2000, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_LME_IPCLKPORT_CLK, 0x202c, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_M, 0x200c, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_S, 0x2010, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_CLK, 0x2014, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_MI_ID_LME_IPCLKPORT_I_CLK, 0x201c, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_SI_ID_LME_IPCLKPORT_I_CLK, 0x2028, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_LME_IPCLKPORT_CLK, 0x2034, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCP_IPCLKPORT_CLK, 0x2044, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_GDC_IPCLKPORT_CLK, 0x2048, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_LME_IPCLKPORT_CLK, 0x204c, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_LME_UID_BLK_LME_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2008, CMU_LME),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK, 0x201c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM, 0x2004, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK, 0x2008, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK, 0x206c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_LH_ACEL_SI_D_M2M_IPCLKPORT_I_CLK, 0x2018, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK, 0x2020, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1, 0x2024, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF, 0x2028, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK, 0x202c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK, 0x2030, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK, 0x2040, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK, 0x2048, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK, 0x2050, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK, 0x2054, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCD_IPCLKPORT_CLK, 0x205c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCP_IPCLKPORT_CLK, 0x2060, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S1, 0x2070, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S2, 0x2074, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK, 0x2078, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK, 0x2080, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK, 0x2058, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK, 0x200c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK, 0x2010, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK, 0x2014, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK, 0x203c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK, 0x2044, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK, 0x204c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK, 0x207c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AST_SI_G_PPMU_M2M_IPCLKPORT_I_CLK, 0x2068, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCD_IPCLKPORT_CLK, 0x2064, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_FRC_MC_IPCLKPORT_I_CLK, 0x2084, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_ACLK, 0x2090, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_PCLK, 0x2094, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_FRC_IPCLKPORT_CLK, 0x209c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_FRC_IPCLKPORT_CLK, 0x2098, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_FRC_MC_IPCLKPORT_PCLKM, 0x2034, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_BLK_M2M_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2038, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCP_IPCLKPORT_CLK, 0x20a0, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_MI_FRC_MC_IPCLKPORT_I_CLK, 0x2088, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_SI_FRC_MC_IPCLKPORT_I_CLK, 0x208c, CMU_M2M),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK, 0x2030, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK, 0x2010, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK, 0x2080, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK, 0x2028, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK, 0x202c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK, 0x2044, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK, 0x2048, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK, 0x204c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK, 0x2050, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK, 0x2054, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCD_IPCLKPORT_CLK, 0x205c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK, 0x2060, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK, 0x2058, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1, 0x208c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1, 0x2094, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK, 0x209c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK, 0x20ac, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK, 0x20b0, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2, 0x2090, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2, 0x2098, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK, 0x20a4, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AST_SI_G_PPMU_MCSC_IPCLKPORT_I_CLK, 0x2078, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_SIU_G_PPMU_MCSC_IPCLKPORT_I_ACLK, 0x2070, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCD_IPCLKPORT_CLK, 0x206c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_MCSC_IPCLKPORT_CLK, 0x2068, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCFP_IPCLKPORT_PCLKM, 0x2008, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM, 0x200c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK, 0x20d8, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_ACLK, 0x20dc, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_PCLK, 0x20e0, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_ACLK, 0x20e4, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_PCLK, 0x20e8, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1, 0x20f4, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2, 0x20f8, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S1, 0x20fc, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S2, 0x2100, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S1, 0x2104, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S2, 0x2108, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK, 0x20f0, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D3_MCSC_IPCLKPORT_I_CLK, 0x2084, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D4_MCSC_IPCLKPORT_I_CLK, 0x2088, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D3_MCSC_IPCLKPORT_ACLK, 0x2114, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D4_MCSC_IPCLKPORT_ACLK, 0x2118, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK, 0x210c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D2_MCSC_IPCLKPORT_CLK, 0x2110, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK, 0x20cc, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK, 0x20d0, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK, 0x20d4, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCFP_IPCLKPORT_CLK, 0x20c8, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_SI_OTF_MCSCYUVP_IPCLKPORT_I_CLK, 0x2024, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF_BRPMCSC_IPCLKPORT_I_CLK, 0x2020, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCP_IPCLKPORT_CLK, 0x20ec, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC6_IPCLKPORT_I_CLK, 0x207c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC0_IPCLKPORT_I_CLK, 0x2034, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC1_IPCLKPORT_I_CLK, 0x2038, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC2_IPCLKPORT_I_CLK, 0x203c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC3_IPCLKPORT_I_CLK, 0x2040, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC4_IPCLKPORT_I_CLK, 0x2064, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC5_IPCLKPORT_I_CLK, 0x2074, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC0_IPCLKPORT_I_CLK, 0x20a0, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC1_IPCLKPORT_I_CLK, 0x20a8, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC2_IPCLKPORT_I_CLK, 0x20b4, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC3_IPCLKPORT_I_CLK, 0x20b8, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC4_IPCLKPORT_I_CLK, 0x20bc, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC5_IPCLKPORT_I_CLK, 0x20c0, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC6_IPCLKPORT_I_CLK, 0x20c4, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_BLK_MCSC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2014, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK, 0x2018, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK, 0x201c, CMU_MCSC),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK, 0x2044, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK, 0x20d4, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK, 0x20d0, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1, 0x20b8, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCP_IPCLKPORT_CLK, 0x20a0, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_IPCLKPORT_CLK, 0x209c, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK, 0x2098, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK, 0x2094, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK, 0x2090, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK, 0x208c, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK, 0x2088, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK, 0x2084, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK, 0x2080, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK, 0x207c, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK, 0x2078, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK, 0x2070, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK, 0x2074, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK, 0x206c, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK, 0x2068, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK, 0x2064, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK, 0x2058, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK, 0x205c, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK, 0x2050, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK, 0x2054, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK, 0x2048, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK, 0x204c, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI, 0x2038, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI, 0x2034, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D1_MFC0_IPCLKPORT_I_CLK, 0x2040, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D0_MFC0_IPCLKPORT_I_CLK, 0x203c, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK, 0x202c, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK, 0x2028, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK, 0x2024, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AXI_MI_P_MFC0_IPCLKPORT_I_CLK, 0x20b4, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK, 0x2020, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK, 0x201c, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK, 0x2018, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK, 0x2014, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK, 0x2010, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS, 0x2000, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM, 0x2004, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM, 0x2008, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK, 0x20c8, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK, 0x2030, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2, 0x20bc, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1, 0x20c0, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2, 0x20c4, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AST_SI_G_PPMU_MFC0_IPCLKPORT_I_CLK, 0x20b0, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_SIU_G_PPMU_MFC0_IPCLKPORT_I_ACLK, 0x20ac, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_VGEN_LITE_MFC0_IPCLKPORT_CLK, 0x20cc, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK, 0x2060, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK, 0x20a4, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCP_IPCLKPORT_CLK, 0x20e4, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_ID_MFC0_IPCLKPORT_I_CLK, 0x20d8, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_MI_ID_MFC0_IPCLKPORT_I_CLK, 0x20a8, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_BLK_MFC0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x200c, CMU_MFC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK, 0x20dc, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK, 0x20e0, CMU_MFC0),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK, 0x2034, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK, 0x2098, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1, 0x2088, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCP_IPCLKPORT_CLK, 0x2074, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK, 0x2070, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK, 0x206c, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK, 0x2068, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK, 0x2064, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK, 0x2060, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK, 0x205c, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK, 0x2058, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK, 0x200c, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK, 0x2008, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM, 0x2004, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM, 0x2000, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK, 0x2010, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK, 0x2014, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK, 0x2018, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AXI_MI_P_MFC1_IPCLKPORT_I_CLK, 0x2084, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK, 0x201c, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK, 0x2020, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK, 0x2024, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK, 0x2028, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D0_MFC1_IPCLKPORT_I_CLK, 0x202c, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D1_MFC1_IPCLKPORT_I_CLK, 0x2030, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK, 0x2038, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK, 0x203c, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK, 0x2040, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK, 0x2048, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK, 0x2044, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK, 0x204c, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK, 0x2050, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK, 0x2054, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2, 0x208c, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1, 0x2090, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2, 0x2094, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK, 0x209c, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AST_SI_G_PPMU_MFC1_IPCLKPORT_I_CLK, 0x2080, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_SIU_G_PPMU_MFC1_IPCLKPORT_I_ACLK, 0x207c, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK, 0x2078, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCP_IPCLKPORT_CLK, 0x20a8, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_BLK_MFC1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x20a0, CMU_MFC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK, 0x20a4, CMU_MFC1),
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|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, 0x2024, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK, 0x2038, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DDRPHY_IPCLKPORT_PCLK, 0x2000, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DMC_IPCLKPORT_PCLK, 0x2004, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK, 0x201c, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK, 0x204c, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK, 0x202c, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK, 0x203c, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, 0x2054, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_SPC_MIF_IPCLKPORT_PCLK, 0x2050, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_PRIVATE_MIF_IPCLKPORT_PCLK, 0x2058, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AST_SI_G_PPMU_MIF_IPCLKPORT_I_CLK, 0x2048, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK, 0x2034, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_PCLK, 0x200c, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_ATCLK, 0x2008, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_DDD_MIF_IPCLKPORT_CK_IN, 0x2010, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCP_IPCLKPORT_CLK, 0x2044, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK, 0x2028, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_DEBUG_IPCLKPORT_CLK, 0x2030, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_DDD_CTRL_IPCLKPORT_CLK, 0x2018, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK, 0x2020, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_BLK_MIF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2014, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_IPCLKPORT_CLK, 0x2040, CMU_MIF),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK, 0x20a8, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_CLK, 0x203c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G0_PPMU_NOCL0_IPCLKPORT_I_ACLK, 0x213c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G1_PPMU_NOCL0_IPCLKPORT_I_ACLK, 0x2140, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_SYSMMU_S2_G3D_IPCLKPORT_PCLKM, 0x2004, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_CP_IPCLKPORT_I_PCLK, 0x2028, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK, 0x202c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK, 0x2030, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK, 0x2044, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D2_MODEM_IPCLKPORT_I_CLK, 0x2190, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D0_CLUSTER0_IPCLKPORT_I_CLK, 0x2084, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK, 0x204c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D1_CLUSTER0_IPCLKPORT_I_CLK, 0x2088, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK, 0x2050, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK, 0x2054, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK, 0x2058, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK, 0x2188, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK, 0x218c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_QDI_MI_D_AUD_IPCLKPORT_I_CLK, 0x208c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK, 0x2080, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK, 0x2078, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK, 0x2198, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK, 0x219c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK, 0x21a0, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK, 0x21a4, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK, 0x21bc, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERISGIC_IPCLKPORT_I_CLK, 0x21c0, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_0_IPCLKPORT_CLK, 0x2090, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_1_IPCLKPORT_CLK, 0x2094, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK, 0x2098, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK, 0x209c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK, 0x20a0, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK, 0x20a4, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK, 0x20b4, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK, 0x20b8, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK, 0x20cc, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK, 0x20d0, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK, 0x20d4, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK, 0x20d8, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_ACLK, 0x20dc, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_PCLK, 0x20e0, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_ACLK, 0x20e4, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_PCLK, 0x20e8, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_ACLK, 0x20ec, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_PCLK, 0x20f0, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_ACLK, 0x20f4, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_PCLK, 0x20f8, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_ACLK, 0x20fc, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_ACLK, 0x2104, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_ACLK, 0x210c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_ACLK, 0x2114, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK, 0x2128, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK, 0x212c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D0, 0x21d8, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2, 0x21cc, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK, 0x21e8, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK, 0x21f0, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK, 0x21f4, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK, 0x21fc, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK, 0x2214, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_NOCL0, 0x21f8, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK, 0x21ac, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK, 0x21b0, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK, 0x21b4, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK, 0x21b8, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_APM_IPCLKPORT_CLK_S2, 0x21d0, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK, 0x207c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK, 0x21a8, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK, 0x2194, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D1, 0x21dc, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D2, 0x21e0, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D3, 0x21e4, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_ACLK, 0x2034, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_PCLK, 0x2038, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_NOCL0, 0x2200, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S1, 0x21c8, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_ACLK, 0x20c4, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_PCLK, 0x20c8, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_UFD_IPCLKPORT_I_CLK, 0x205c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_SSP_IPCLKPORT_I_CLK, 0x2060, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK, 0x206c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK, 0x2070, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1C_IPCLKPORT_I_CLK, 0x2074, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_ACLK, 0x2228, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_PCLK, 0x222c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_ACLK, 0x2250, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_PCLK, 0x2254, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_ACLK, 0x2258, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_PCLK, 0x225c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_ACLK, 0x2260, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_PCLK, 0x2264, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_ACLK, 0x2268, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_PCLK, 0x226c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_CLK, 0x2270, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_PCLK, 0x2274, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_ACLK, 0x20bc, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_ACLK, 0x2218, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_PCLK, 0x221c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_ACLK, 0x2220, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_PCLK, 0x2224, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_ACLK, 0x2230, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_PCLK, 0x2234, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_MPTW, 0x21d4, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_AUD_IPCLKPORT_I_CLK, 0x2158, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MODEM_IPCLKPORT_I_CLK, 0x216c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK, 0x2170, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK, 0x2174, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G2_PPMU_NOCL0_IPCLKPORT_I_ACLK, 0x2144, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G3_PPMU_NOCL0_IPCLKPORT_I_ACLK, 0x2148, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G4_PPMU_NOCL0_IPCLKPORT_I_ACLK, 0x214c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G5_PPMU_NOCL0_IPCLKPORT_I_ACLK, 0x2150, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_ETR_IPCLKPORT_PCLKM, 0x2000, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_ETR_64_NOCL0_IPCLKPORT_CLK, 0x2048, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF0_IPCLKPORT_I_CLK, 0x215c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF1_IPCLKPORT_I_CLK, 0x2160, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF2_IPCLKPORT_I_CLK, 0x2164, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF3_IPCLKPORT_I_CLK, 0x2168, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_ACLK, 0x211c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_PCLK, 0x2120, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D0_MODEM_IPCLKPORT_I_PCLK, 0x20ac, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D1_MODEM_IPCLKPORT_I_PCLK, 0x20b0, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK, 0x2134, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK, 0x2138, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_ACLK, 0x2238, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_PCLK, 0x223c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_ACLK, 0x2240, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_PCLK, 0x2244, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_ACLK, 0x2248, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_PCLK, 0x224c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D0_G3D_IPCLKPORT_CLK, 0x2204, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D1_G3D_IPCLKPORT_CLK, 0x2208, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D2_G3D_IPCLKPORT_CLK, 0x220c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D3_G3D_IPCLKPORT_CLK, 0x2210, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK, 0x217c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK, 0x2178, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D0_G3D_IPCLKPORT_PCLKM, 0x2008, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D1_G3D_IPCLKPORT_PCLKM, 0x200c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D2_G3D_IPCLKPORT_PCLKM, 0x2010, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D3_G3D_IPCLKPORT_PCLKM, 0x2014, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_PCLK, 0x20c0, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_PCLK, 0x2100, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_PCLK, 0x2108, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_PCLK, 0x2110, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_PCLK, 0x2118, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_PCLK, 0x2040, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK, 0x2124, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK, 0x2130, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_GNSS_IPCLKPORT_I_CLK, 0x227c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCIF_CMUTOPC_IPCLKPORT_PCLK, 0x2154, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK, 0x2290, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIS_IPCLKPORT_I_CLK, 0x2298, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK, 0x2280, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK, 0x2018, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_SSP_IPCLKPORT_I_CLK, 0x229c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_UFD_IPCLKPORT_I_CLK, 0x22a0, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_ACEL_MI_D_SSP_IPCLKPORT_I_CLK, 0x21ec, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D_UFD_IPCLKPORT_I_CLK, 0x228c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK, 0x2288, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK, 0x2284, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK, 0x2294, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK, 0x2068, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK, 0x2064, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D0_ACP_IPCLKPORT_I_CLK, 0x2020, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_ACLK, 0x22a4, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_PCLK, 0x22a8, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_ACLK, 0x22ac, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_PCLK, 0x22b0, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D1_ACP_IPCLKPORT_I_CLK, 0x2024, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D0_ACP_IPCLKPORT_ACLK, 0x22b4, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D1_ACP_IPCLKPORT_ACLK, 0x22b8, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D2_ACP_IPCLKPORT_ACLK, 0x22bc, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D3_ACP_IPCLKPORT_ACLK, 0x22c0, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK, 0x2180, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_CCI_IPCLKPORT_CLK, 0x2184, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK, 0x21c4, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BLK_NOCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x201c, CMU_NOCL0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK, 0x2028, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK, 0x20a0, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK, 0x20a8, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK, 0x20a4, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK, 0x2080, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC1_IPCLKPORT_I_CLK, 0x2090, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC1_IPCLKPORT_I_CLK, 0x201c, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK, 0x200c, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC0_IPCLKPORT_I_CLK, 0x2018, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC0_IPCLKPORT_I_CLK, 0x208c, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK, 0x2000, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_LME_IPCLKPORT_I_CLK, 0x2020, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK, 0x20ac, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_NOCL1A, 0x20b0, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC1_IPCLKPORT_I_CLK, 0x2014, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_LME_IPCLKPORT_I_CLK, 0x2084, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC0_IPCLKPORT_I_CLK, 0x2010, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK, 0x2034, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK, 0x2004, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_HSI1_IPCLKPORT_I_CLK, 0x2050, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_LME_IPCLKPORT_I_CLK, 0x2054, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC0_IPCLKPORT_I_CLK, 0x205c, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC1_IPCLKPORT_I_CLK, 0x2060, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK, 0x2070, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_2X1_P0_NOCL1A_IPCLKPORT_I_ACLK, 0x2040, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_4X1_P0_NOCL1A_IPCLKPORT_I_ACLK, 0x2044, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_8X1_P0_NOCL1A_IPCLKPORT_I_ACLK, 0x2048, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK, 0x2094, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC2_IPCLKPORT_I_CLK, 0x2098, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK, 0x203c, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK, 0x206c, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK, 0x2074, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK, 0x2078, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK, 0x207c, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_DPUF_IPCLKPORT_I_CLK, 0x2030, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DNC_IPCLKPORT_I_CLK, 0x2064, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DPUF_IPCLKPORT_I_CLK, 0x2068, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_MI_D0_DPUF_IPCLKPORT_I_CLK, 0x209c, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DNC_IPCLKPORT_I_CLK, 0x20b4, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUB_IPCLKPORT_I_CLK, 0x20b8, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUF_IPCLKPORT_I_CLK, 0x20bc, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BAAW_P_DNC_IPCLKPORT_I_PCLK, 0x2008, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_M2M_IPCLKPORT_I_CLK, 0x202c, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK, 0x20c0, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_M2M_IPCLKPORT_I_CLK, 0x2088, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK, 0x204c, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_RET_IPCLKPORT_CLK, 0x2058, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_RET_IPCLKPORT_CLK, 0x2038, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BLK_NOCL1A_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2024, CMU_NOCL1A),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK, 0x2058, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK, 0x2044, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK, 0x20ac, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK, 0x2110, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK, 0x2050, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_PCLK, 0x2074, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_PCLK, 0x207c, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK, 0x2090, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK, 0x2138, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK, 0x213c, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK, 0x2140, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_NOCL1B, 0x2148, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK, 0x2144, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_UFS_IPCLKPORT_I_CLK, 0x2120, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_PCLK, 0x206c, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_PCLK, 0x2064, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_HSI0_IPCLKPORT_I_CLK, 0x20c0, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK, 0x20d0, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK, 0x2088, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_DIT_IPCLKPORT_PCLKM, 0x2000, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_PDMA_IPCLKPORT_PCLKM, 0x2004, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM, 0x2008, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM, 0x200c, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_TT_IPCLKPORT_PCLKM, 0x2010, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PDMA_IPCLKPORT_ACLK, 0x205c, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SPDMA_IPCLKPORT_ACLK, 0x2128, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_ACLK, 0x2070, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_ACLK, 0x2078, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_DIT_IPCLKPORT_ICLKL2A, 0x2040, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_XIU_D_TT_IPCLKPORT_ACLK, 0x2160, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_TT_IPCLKPORT_CLK_S2, 0x2134, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2, 0x212c, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_LITE_NOCL1B_IPCLKPORT_CLK, 0x2154, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_SPDMA_IPCLKPORT_CLK, 0x215c, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_PDMA_IPCLKPORT_CLK, 0x2158, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_ACLK, 0x2060, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_ACLK, 0x2068, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK, 0x208c, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_ID_DIT_IPCLKPORT_I_CLK, 0x2048, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_SI_ID_DIT_IPCLKPORT_I_CLK, 0x204c, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_LITE_NOCL1B_IPCLKPORT_PCLKM, 0x201c, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM, 0x2020, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_SPDMA_IPCLKPORT_PCLKM, 0x2024, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_IPCLKPORT_CLK, 0x2098, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK, 0x20a0, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_TREXP_IPCLKPORT_I_CLK, 0x20d8, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK, 0x20dc, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_DIT_IPCLKPORT_I_CLK, 0x20d4, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_TREXP_IPCLKPORT_I_CLK, 0x20c8, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK, 0x20cc, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_DIT_IPCLKPORT_I_CLK, 0x20c4, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK, 0x20e0, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK, 0x20e4, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_D_UFS_IPCLKPORT_I_CLK, 0x2018, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_UFS_IPCLKPORT_I_CLK, 0x2080, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SIU_8X1_P0_NOCL1B_IPCLKPORT_I_ACLK, 0x2054, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_ID_TT_IPCLKPORT_I_CLK, 0x2028, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_ID_TT_IPCLKPORT_I_CLK, 0x202c, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK, 0x2034, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK, 0x2038, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_RET_IPCLKPORT_CLK, 0x203c, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_RET_IPCLKPORT_CLK, 0x2030, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_BLK_NOCL1B_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2014, CMU_NOCL1B),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_NOCL1C_CMU_NOCL1C_IPCLKPORT_PCLK, 0x2048, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK, 0x2030, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SYSREG_NOCL1C_IPCLKPORT_PCLK, 0x20c8, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_PCLK, 0x20d0, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_ACLK, 0x20cc, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSTAT_IPCLKPORT_I_CLK, 0x20b0, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D_CSTAT_IPCLKPORT_I_CLK, 0x2040, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK, 0x20ac, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK, 0x2018, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK, 0x2004, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK, 0x20d4, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_NOCL1C, 0x20d8, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_YUVP_IPCLKPORT_I_CLK, 0x20c4, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AST_SI_G_NOCL1C_IPCLKPORT_I_CLK, 0x2008, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK, 0x2020, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK, 0x20bc, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK, 0x200c, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_D_TZPC_NOCL1C_IPCLKPORT_PCLK, 0x2000, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK, 0x2028, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_CLK_NOCL1C_NOCP_IPCLKPORT_CLK, 0x2050, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSIS_IPCLKPORT_I_CLK, 0x2068, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSTAT_IPCLKPORT_I_CLK, 0x206c, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_MCSC_IPCLKPORT_I_CLK, 0x2078, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_YUVP_IPCLKPORT_I_CLK, 0x2080, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK, 0x2088, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCD_IPCLKPORT_CLK, 0x2054, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK, 0x2084, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK, 0x208c, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK, 0x2090, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK, 0x2094, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D3_MCSC_IPCLKPORT_I_CLK, 0x2034, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D4_MCSC_IPCLKPORT_I_CLK, 0x2038, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_BRP_IPCLKPORT_I_CLK, 0x2014, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_BRP_IPCLKPORT_I_CLK, 0x2024, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_BRP_IPCLKPORT_I_CLK, 0x202c, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_YUVP_IPCLKPORT_I_CLK, 0x201c, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D1_YUVP_IPCLKPORT_I_CLK, 0x2058, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_BRP_IPCLKPORT_I_CLK, 0x205c, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_BRP_IPCLKPORT_I_CLK, 0x204c, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SIU_8X1_P0_NOCL1C_IPCLKPORT_I_ACLK, 0x2044, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCP_IPCLKPORT_CLK, 0x203c, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_BLK_NOCL1C_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2010, CMU_NOCL1C),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, 0x2008, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, 0x2020, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK, 0x2010, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, 0x2004, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK, 0x201c, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK, 0x2018, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK, 0x2014, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, 0x2000, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK, 0x2030, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK, 0x2028, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK, 0x2024, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK, 0x202c, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK, 0x200c, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK, 0x2034, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK, 0x2038, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK, 0x203c, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK, 0x2040, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK, 0x2044, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK, 0x2048, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK, 0x204c, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK, 0x2050, CMU_PERIC0),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, 0x2028, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK, 0x2038, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, 0x200c, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, 0x2008, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK, 0x205c, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK, 0x2034, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK, 0x203c, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, 0x2064, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK, 0x20a8, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK, 0x2004, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK, 0x2074, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK, 0x206c, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK, 0x2084, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK, 0x2044, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK, 0x204c, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK, 0x2050, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK, 0x2000, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK, 0x2070, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK, 0x207c, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK, 0x2080, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK, 0x208c, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK, 0x2088, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK, 0x209c, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK, 0x2098, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK, 0x2094, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK, 0x2090, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK, 0x20a4, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK, 0x20a0, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK, 0x2060, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK, 0x2054, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK, 0x202c, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK, 0x2068, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK, 0x2078, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK, 0x2040, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK, 0x2048, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK, 0x2010, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK, 0x2014, CMU_PERIC1),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK, 0x2058, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK, 0x2008, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK, 0x200c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK, 0x2098, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK, 0x2068, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK, 0x2064, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK, 0x20a0, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK, 0x2070, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK, 0x2078, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK, 0x2080, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK, 0x2084, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK, 0x2088, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK, 0x208c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK, 0x20a8, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK, 0x20b8, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK, 0x20c8, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK, 0x20c4, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK, 0x20d8, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK, 0x20d4, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK, 0x20e8, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK, 0x20e4, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK, 0x20f8, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK, 0x20f4, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK, 0x20b0, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK, 0x20ac, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK, 0x20c0, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK, 0x20d0, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK, 0x20cc, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK, 0x20e0, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK, 0x20dc, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK, 0x20f0, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK, 0x2100, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK, 0x20fc, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK, 0x20bc, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK, 0x2028, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK, 0x2030, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK, 0x2038, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK, 0x2040, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK, 0x2048, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK, 0x2050, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK, 0x202c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK, 0x2034, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK, 0x203c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK, 0x2044, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK, 0x204c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK, 0x2054, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK, 0x209c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK, 0x20ec, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK, 0x2090, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK, 0x2108, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK, 0x2104, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK, 0x2110, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK, 0x210c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK, 0x2010, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK, 0x2018, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK, 0x2020, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK, 0x2024, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK, 0x201c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK, 0x2014, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK, 0x206c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK, 0x2004, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK, 0x2000, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0, 0x205c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK, 0x2094, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK, 0x2060, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK, 0x20a4, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK, 0x20b4, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK, 0x2074, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK, 0x207c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK, 0x211c, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK, 0x2120, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK, 0x2114, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK, 0x2118, CMU_PERIC2),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK, 0x2030, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK, 0x200c, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK, 0x2010, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK, 0x2014, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK, 0x2048, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK, 0x2044, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK, 0x2018, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK, 0x201c, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK, 0x202c, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK, 0x2040, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK, 0x203c, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK, 0x204c, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK, 0x2050, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK, 0x2054, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK, 0x2058, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK, 0x205c, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, 0x2024, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, 0x2020, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 0x2028, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK, 0x2038, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK, 0x2004, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK, 0x2000, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN, 0x2008, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK, 0x206c, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK, 0x2068, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK, 0x2064, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK, 0x2060, CMU_PERIS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK, 0x2010, CMU_S2D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK, 0x200c, CMU_S2D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK, 0x2004, CMU_S2D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK, 0x2000, CMU_S2D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK, 0x2014, CMU_S2D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK, 0x2008, CMU_S2D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_SR_CLK_S2D_CORE_IPCLKPORT_CLK, 0x201c, CMU_S2D),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_SDMA_CMU_SDMA_IPCLKPORT_PCLK, 0x2054, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK, 0x201c, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK, 0x2018, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK, 0x2024, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK, 0x2020, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK, 0x203c, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_SLH_AXI_MI_LP_SDMA_IPCLKPORT_I_CLK, 0x2058, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_SYSREG_SDMA_IPCLKPORT_PCLK, 0x205c, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK, 0x2038, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_D_TZPC_SDMA_IPCLKPORT_PCLK, 0x2004, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCD_IPCLKPORT_CLK, 0x2048, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCP_IPCLKPORT_CLK, 0x204c, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AST_SI_LD_STRM_SDMADSP0_IPCLKPORT_I_CLK, 0x200c, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_IP_SDMA_IPCLKPORT_I_CLK, 0x2008, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_MI_LP_DNCSDMA_IPCLKPORT_I_CLK, 0x2014, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCD_IPCLKPORT_CLK, 0x2050, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK, 0x2028, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK, 0x202c, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK, 0x2030, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK, 0x2034, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK, 0x2040, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK, 0x2044, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCP_IPCLKPORT_CLK, 0x2060, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SDMA_UID_BLK_SDMA_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2010, CMU_SDMA),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK, 0x2060, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK, 0x2008, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK, 0x2010, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_LH_AXI_MI_L_STRONG_IPCLKPORT_I_CLK, 0x2014, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AXI_MI_P_SSP_IPCLKPORT_I_CLK, 0x205c, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_ACEL_SI_D_SSP_IPCLKPORT_I_CLK, 0x2054, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK, 0x2018, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK, 0x201c, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_ACLK, 0x2030, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_PCLK, 0x2034, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK, 0x2028, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK, 0x202c, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCD_IPCLKPORT_CLK, 0x2040, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCP_IPCLKPORT_CLK, 0x2044, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK, 0x2064, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_SYSREG_SSP_IPCLKPORT_PCLK, 0x2074, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_VGEN_LITE_SSP_IPCLKPORT_CLK, 0x207c, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK, 0x2080, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK, 0x2068, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_AD_APB_SYSMMU_SSP_IPCLKPORT_PCLKM, 0x2004, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_SYSMMU_SSP_IPCLKPORT_CLK_S2, 0x2070, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AST_SI_G_PPMU_SSP_IPCLKPORT_I_CLK, 0x2058, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCD_IPCLKPORT_CLK, 0x2048, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK, 0x203c, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_OTP_DESERIAL_SSS_HIDE_SECKEY_IPCLKPORT_I_CLK, 0x2020, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK, 0x200c, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCP_IPCLKPORT_CLK, 0x2038, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_BLK_SSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2000, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK, 0x2024, CMU_SSP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_STRONG_UID_STRONG_CMU_STRONG_IPCLKPORT_PCLK, 0x2000, CMU_STRONG),
|
|
SFR(CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_IPCLKPORT_CLK, 0x2008, CMU_STRONG),
|
|
SFR(CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_IPCLKPORT_CLK, 0x2004, CMU_STRONG),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_CMU_UFD_IPCLKPORT_PCLK, 0x204c, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_D_TZPC_UFD_IPCLKPORT_PCLK, 0x2004, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_IPCLKPORT_CLK, 0x2018, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_LP_CMGPUFD_IPCLKPORT_I_CLK, 0x2024, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_P_UFD_IPCLKPORT_I_CLK, 0x2028, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_PDMA_UFD_IPCLKPORT_ACLK, 0x2014, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_IPCLKPORT_PCLK, 0x2044, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_IPCLKPORT_CLK, 0x2050, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_DP_UFD_IPCLKPORT_ACLK, 0x2058, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_PCLK, 0x203c, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_ACLK, 0x2038, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_VGEN_LITE_D_UFD_IPCLKPORT_CLK, 0x2054, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_D_UFD_IPCLKPORT_I_CLK, 0x202c, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_D_UFD_IPCLKPORT_ACLK, 0x205c, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LD_UFDDNC_IPCLKPORT_I_CLK, 0x2030, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_SRAM_MIU_UFD_IPCLKPORT_ACLK, 0x2040, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_PCLK, 0x2008, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_SCLK, 0x200c, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_BAAW_D_UFDDNC_IPCLKPORT_I_PCLK, 0x2000, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_SECURE_IPCLKPORT_PCLK, 0x2048, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_IPCLKPORT_CLK, 0x201c, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_ID_COMP_UFD_IPCLKPORT_I_CLK, 0x2010, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LP_UFDCSIS_IPCLKPORT_I_CLK, 0x2034, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_MI_OTF_CSISUFD_IPCLKPORT_I_CLK, 0x2020, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S1, 0x2080, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S2, 0x2084, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_SI_G_PPMU_UFD_IPCLKPORT_I_CLK, 0x207c, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_LH_AST_SI_OTF_UFDDNC_IPCLKPORT_I_CLK, 0x206c, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_BLK_UFD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2068, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_IPCLKPORT_CLK, 0x2074, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_IPCLKPORT_CLK, 0x2078, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_IPCLKPORT_CLK, 0x2070, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_US_32TO128_UFD_IPCLKPORT_ACLK, 0x2064, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_DS_128TO32_UFD_IPCLKPORT_MAINCLK, 0x2060, CMU_UFD),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK, 0x2058, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK, 0x2048, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK, 0x2044, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK, 0x2028, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK, 0x2024, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK, 0x2054, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK, 0x2070, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN, 0x2018, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK, 0x2014, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK, 0x2010, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK, 0x2004, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK, 0x204c, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK, 0x2008, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK, 0x200c, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2, 0x2050, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, 0x2060, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, 0x2064, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK, 0x205c, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK, 0x2068, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK, 0x206c, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK, 0x2030, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK, 0x2034, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK, 0x2038, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK, 0x203c, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK, 0x202c, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK, 0x201c, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK, 0x2040, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2000, CMU_UFS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK, 0x2070, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK, 0x2074, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK, 0x2078, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK, 0x207c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK, 0x2080, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK, 0x2084, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK, 0x2088, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK, 0x2090, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK, 0x20ac, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK, 0x20b0, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK, 0x20b4, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK, 0x20b8, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK, 0x20bc, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK, 0x20c0, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK, 0x20c4, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK, 0x20c8, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK, 0x20cc, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK, 0x20d0, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK, 0x20ec, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK, 0x2104, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK, 0x2108, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK, 0x210c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0, 0x212c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1, 0x2130, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2, 0x2134, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK, 0x213c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK, 0x2154, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK, 0x2068, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK, 0x2158, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK, 0x206c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK, 0x2150, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK, 0x2148, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK, 0x2140, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK, 0x2144, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK, 0x20f8, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN, 0x215c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK, 0x20d4, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK, 0x2164, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK, 0x2034, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK, 0x2160, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLKVTS_AUD_DMIC1, 0x2004, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLKVTS_AUD_DMIC0, 0x2000, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK, 0x2128, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK, 0x20fc, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU, 0x2124, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK, 0x200c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK, 0x2010, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2030, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK, 0x202c, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK, 0x2008, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK, 0x2024, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK, 0x2020, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK, 0x2018, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK, 0x2028, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK, 0x2014, CMU_VTS),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_CMU_YUVP_IPCLKPORT_PCLK, 0x207c, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_AD_APB_YUVP_IPCLKPORT_PCLKM, 0x200c, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_MI_P_YUVP_IPCLKPORT_I_CLK, 0x2060, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCD_IPCLKPORT_CLK, 0x204c, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCP_IPCLKPORT_CLK, 0x2050, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSREG_YUVP_IPCLKPORT_PCLK, 0x2070, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_ACLK, 0x203c, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_PCLK, 0x2040, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S1, 0x2068, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D0_YUVP_IPCLKPORT_ACLK, 0x2078, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK, 0x2080, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_MI_OTF_MCSCYUVP_IPCLKPORT_I_CLK, 0x2030, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_D_TZPC_YUVP_IPCLKPORT_PCLK, 0x2028, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S2, 0x206c, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK, 0x2038, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_PCLK, 0x201c, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_DDD_YUVP_IPCLKPORT_CK_IN, 0x2024, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D0_YUVP_IPCLKPORT_CLK, 0x2074, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_ATCLK, 0x2018, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AST_SI_G_PPMU_YUVP_IPCLKPORT_I_CLK, 0x205c, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCD_IPCLKPORT_CLK, 0x2058, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_ACLK, 0x2044, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_PCLK, 0x2064, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AXI_SI_D0_YUVP_IPCLKPORT_I_CLK, 0x2034, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_SI_D1_YUVP_IPCLKPORT_I_CLK, 0x2098, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D1_YUVP_IPCLKPORT_ACLK, 0x20a8, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S1, 0x209c, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S2, 0x20a0, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_SIU_G_PPMU_YUVP_IPCLKPORT_I_ACLK, 0x2094, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D1_YUVP_IPCLKPORT_CLK, 0x20a4, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF0, 0x20ac, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF1, 0x20b0, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCP_IPCLKPORT_CLK, 0x208c, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_BLK_YUVP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, 0x2020, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK, 0x202c, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_DDD_CTRL_IPCLKPORT_CLK, 0x2084, CMU_YUVP),
|
|
SFR(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_FREE_OSCCLK_IPCLKPORT_CLK, 0x2088, CMU_YUVP),
|
|
SFR(CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0x1854, CMU_TOP),
|
|
SFR(CLK_CON_DIV_CLK_CPUCL0_DDD_CTRL, 0x1808, CMU_CPUCL0),
|
|
SFR(CLK_CON_DIV_CLK_CPUCL1_DDD_CTRL_0, 0x1810, CMU_CPUCL1),
|
|
SFR(CLK_CON_DIV_CLK_CPUCL1_DDD_CTRL_1, 0x1814, CMU_CPUCL1),
|
|
SFR(CLK_CON_DIV_CLK_CPUCL1_DDD_CTRL_2, 0x1818, CMU_CPUCL1),
|
|
SFR(CLK_CON_DIV_CLK_CPUCL2_DDD_CTRL, 0x1808, CMU_CPUCL2),
|
|
SFR(CLK_CON_DIV_DIV_CLK_DNC_DDD_CTRL, 0x1804, CMU_DNC),
|
|
SFR(CLK_CON_DIV_CLK_DSU_DDD_CTRL, 0x1804, CMU_DSU),
|
|
SFR(CLK_CON_DIV_CLK_G3D_DDD_CTRL, 0x1808, CMU_G3DCORE),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MIF_NOCD, 0x1804, CMU_MIF),
|
|
SFR(CLK_CON_DIV_DIV_CLK_MIF_DDD_CTRL, 0x1800, CMU_MIF),
|
|
SFR(CLK_CON_DIV_CLKCMU_OTP, 0x1800, CMU_PERIS),
|
|
SFR(CLK_CON_DIV_DIV_CLK_PERIS_DDD_CTRL, 0x1804, CMU_PERIS),
|
|
SFR(CLK_CON_DIV_CLK_MIF_NOCD_S2D, 0x1800, CMU_S2D),
|
|
SFR(CLK_CON_DIV_DIV_CLK_YUVP_DDD_CTRL, 0x1804, CMU_YUVP),
|
|
SFR(QCH_CON_ALIVE_CMU_ALIVE_QCH, 0x3040, CMU_ALIVE),
|
|
SFR(QCH_CON_APBIF_GPIO_ALIVE_QCH, 0x3044, CMU_ALIVE),
|
|
SFR(QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH, 0x304c, CMU_ALIVE),
|
|
SFR(QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH, 0x3048, CMU_ALIVE),
|
|
SFR(QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH, 0x3050, CMU_ALIVE),
|
|
SFR(QCH_CON_APBIF_PMU_ALIVE_QCH, 0x3054, CMU_ALIVE),
|
|
SFR(QCH_CON_APM_DMA_QCH_APB, 0x3058, CMU_ALIVE),
|
|
SFR(QCH_CON_CHUB_RTC_QCH, 0x305c, CMU_ALIVE),
|
|
SFR(QCH_CON_CLKMON_QCH, 0x3060, CMU_ALIVE),
|
|
SFR(QCH_CON_DBGCORE_UART_QCH, 0x3064, CMU_ALIVE),
|
|
SFR(QCH_CON_DTZPC_ALIVE_QCH, 0x3068, CMU_ALIVE),
|
|
SFR(QCH_CON_GREBEINTEGRATION_QCH_GREBE, 0x3070, CMU_ALIVE),
|
|
SFR(QCH_CON_GREBEINTEGRATION_QCH_DBG, 0x306c, CMU_ALIVE),
|
|
SFR(QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH, 0x3074, CMU_ALIVE),
|
|
SFR(QCH_CON_INTMEM_QCH, 0x3078, CMU_ALIVE),
|
|
SFR(QCH_CON_LH_AXI_SI_D_APM_QCH, 0x307c, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_APM_AP_QCH, 0x3080, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_APM_AUD_QCH, 0x30b8, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_APM_CHUB_QCH, 0x3084, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_APM_CP_QCH, 0x3088, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_APM_CP_1_QCH, 0x3010, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_APM_GNSS_QCH, 0x308c, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_APM_VTS_QCH, 0x3090, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_AP_CHUB_QCH, 0x3094, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_AP_CP_QCH, 0x3098, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_AP_CP_S_QCH, 0x309c, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_AP_DBGCORE_QCH, 0x30a0, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_AP_GNSS_QCH, 0x30a4, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_CP_CHUB_QCH, 0x30a8, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_CP_GNSS_QCH, 0x30ac, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_GNSS_CHUB_QCH, 0x30b0, CMU_ALIVE),
|
|
SFR(QCH_CON_MAILBOX_SHARED_SRAM_QCH, 0x30b4, CMU_ALIVE),
|
|
SFR(QCH_CON_MCT_ALIVE_QCH, 0x30bc, CMU_ALIVE),
|
|
SFR(QCH_CON_PMU_QCH_PMU, 0x30c8, CMU_ALIVE),
|
|
SFR(QCH_CON_PMU_QCH_PMLINK, 0x30c4, CMU_ALIVE),
|
|
SFR(QCH_CON_PMU_INTR_GEN_QCH, 0x30c0, CMU_ALIVE),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH, 0x30d0, CMU_ALIVE),
|
|
SFR(QCH_CON_RTC_QCH, 0x30d4, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_MI_ID_DBGCORE_QCH, 0x30e8, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_MI_LD_CHUBVTS_QCH, 0x30e4, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_MI_LD_GNSS_QCH, 0x30dc, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_MI_LP_MODEM_QCH, 0x30e0, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_APM_QCH, 0x30ec, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_SI_IP_APM_QCH, 0x30f4, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_SI_LP_ALIVEDNC_QCH, 0x3104, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH, 0x30fc, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_SI_LP_CMGP_QCH, 0x30f0, CMU_ALIVE),
|
|
SFR(QCH_CON_SLH_AXI_SI_LP_PPU_QCH, 0x3100, CMU_ALIVE),
|
|
SFR(QCH_CON_SPC_ALIVE_QCH, 0x3108, CMU_ALIVE),
|
|
SFR(QCH_CON_SPMI_MASTER_PMIC_QCH_P, 0x310c, CMU_ALIVE),
|
|
SFR(QCH_CON_SPMI_MASTER_PMIC_QCH_S, 0x3110, CMU_ALIVE),
|
|
SFR(QCH_CON_SWEEPER_P_ALIVE_QCH, 0x3114, CMU_ALIVE),
|
|
SFR(QCH_CON_SYSREG_ALIVE_QCH, 0x3118, CMU_ALIVE),
|
|
SFR(QCH_CON_TOP_RTC_QCH, 0x311c, CMU_ALIVE),
|
|
SFR(QCH_CON_VGEN_LITE_ALIVE_QCH, 0x3120, CMU_ALIVE),
|
|
SFR(QCH_CON_WDT_ALIVE_QCH, 0x3124, CMU_ALIVE),
|
|
SFR(QCH_CON_ALLCSIS_CMU_ALLCSIS_QCH, 0x3040, CMU_ALLCSIS),
|
|
SFR(QCH_CON_CSIS_PDP_QCH_VOTF0, 0x3054, CMU_ALLCSIS),
|
|
SFR(QCH_CON_CSIS_PDP_QCH_DMA, 0x3044, CMU_ALLCSIS),
|
|
SFR(QCH_CON_CSIS_PDP_QCH_MCB, 0x3048, CMU_ALLCSIS),
|
|
SFR(QCH_CON_CSIS_PDP_QCH_VOTF1, 0x3058, CMU_ALLCSIS),
|
|
SFR(QCH_CON_CSIS_PDP_QCH_PDP, 0x304c, CMU_ALLCSIS),
|
|
SFR(QCH_CON_CSIS_PDP_QCH_PDP_VOTF, 0x3050, CMU_ALLCSIS),
|
|
SFR(QCH_CON_LH_AST_MI_OTF0_BRPCSIS_QCH, 0x305c, CMU_ALLCSIS),
|
|
SFR(QCH_CON_LH_AST_MI_OTF1_BRPCSIS_QCH, 0x3060, CMU_ALLCSIS),
|
|
SFR(QCH_CON_LH_AST_SI_OTF0_CSISCSTAT_QCH, 0x3064, CMU_ALLCSIS),
|
|
SFR(QCH_CON_LH_AST_SI_OTF1_CSISCSTAT_QCH, 0x3068, CMU_ALLCSIS),
|
|
SFR(QCH_CON_LH_AST_SI_OTF2_CSISCSTAT_QCH, 0x306c, CMU_ALLCSIS),
|
|
SFR(QCH_CON_LH_AST_SI_OTF3_CSISCSTAT_QCH, 0x3070, CMU_ALLCSIS),
|
|
SFR(QCH_CON_LH_AST_SI_OTF_CSISBRP_QCH, 0x3074, CMU_ALLCSIS),
|
|
SFR(QCH_CON_LH_AXI_MI_LP_INT_P0OIS_CSIS_QCH, 0x3078, CMU_ALLCSIS),
|
|
SFR(QCH_CON_LH_AXI_SI_D0_CSIS_QCH, 0x307c, CMU_ALLCSIS),
|
|
SFR(QCH_CON_LH_AXI_SI_D1_CSIS_QCH, 0x3080, CMU_ALLCSIS),
|
|
SFR(QCH_CON_LH_AXI_SI_D2_CSIS_QCH, 0x3084, CMU_ALLCSIS),
|
|
SFR(QCH_CON_LH_AXI_SI_LP_INT_P0OIS_CSIS_QCH, 0x3088, CMU_ALLCSIS),
|
|
SFR(QCH_CON_LH_AXI_SI_LP_INT_P0P1_CSIS_QCH, 0x308c, CMU_ALLCSIS),
|
|
SFR(QCH_CON_OIS_MCU_TOP_QCH, 0x3090, CMU_ALLCSIS),
|
|
SFR(QCH_CON_PPMU_D0_QCH, 0x3094, CMU_ALLCSIS),
|
|
SFR(QCH_CON_PPMU_D1_QCH, 0x3098, CMU_ALLCSIS),
|
|
SFR(QCH_CON_PPMU_D2_QCH, 0x309c, CMU_ALLCSIS),
|
|
SFR(QCH_CON_QE_CSIS_WDMA0_QCH, 0x30a0, CMU_ALLCSIS),
|
|
SFR(QCH_CON_QE_CSIS_WDMA1_QCH, 0x30a4, CMU_ALLCSIS),
|
|
SFR(QCH_CON_QE_CSIS_WDMA2_QCH, 0x30a8, CMU_ALLCSIS),
|
|
SFR(QCH_CON_QE_CSIS_WDMA3_QCH, 0x30ac, CMU_ALLCSIS),
|
|
SFR(QCH_CON_QE_CSIS_WDMA4_QCH, 0x30b0, CMU_ALLCSIS),
|
|
SFR(QCH_CON_QE_PDP_D0_QCH, 0x30b4, CMU_ALLCSIS),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCD_QCH, 0x30bc, CMU_ALLCSIS),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCP_QCH, 0x30c0, CMU_ALLCSIS),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_QCH, 0x30c8, CMU_ALLCSIS),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_QCH, 0x30c4, CMU_ALLCSIS),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_QCH, 0x30cc, CMU_ALLCSIS),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_QCH, 0x30d0, CMU_ALLCSIS),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_QCH, 0x30d4, CMU_ALLCSIS),
|
|
SFR(QCH_CON_SIU_G_PPMU_CSIS_QCH, 0x30d8, CMU_ALLCSIS),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_CSIS_QCH, 0x30dc, CMU_ALLCSIS),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_CSIS_QCH, 0x30e0, CMU_ALLCSIS),
|
|
SFR(QCH_CON_SLH_AXI_SI_LP_CSISPERIC2_QCH, 0x30e4, CMU_ALLCSIS),
|
|
SFR(QCH_CON_SYSMMU_D0_CSIS_QCH_S1, 0x30e8, CMU_ALLCSIS),
|
|
SFR(QCH_CON_SYSMMU_D0_CSIS_QCH_S2, 0x30ec, CMU_ALLCSIS),
|
|
SFR(QCH_CON_SYSMMU_D1_CSIS_QCH_S1, 0x30f0, CMU_ALLCSIS),
|
|
SFR(QCH_CON_SYSMMU_D1_CSIS_QCH_S2, 0x30f4, CMU_ALLCSIS),
|
|
SFR(QCH_CON_SYSMMU_D2_CSIS_QCH_S1, 0x30f8, CMU_ALLCSIS),
|
|
SFR(QCH_CON_SYSMMU_D2_CSIS_QCH_S2, 0x30fc, CMU_ALLCSIS),
|
|
SFR(QCH_CON_VGEN_LITE_D0_QCH, 0x3100, CMU_ALLCSIS),
|
|
SFR(QCH_CON_VGEN_LITE_D1_QCH, 0x3104, CMU_ALLCSIS),
|
|
SFR(QCH_CON_ABOX_QCH_ACLK, 0x3080, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK_DSIF, 0x30a0, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK0, 0x3084, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK1, 0x3088, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK2, 0x308c, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK3, 0x3090, CMU_AUD),
|
|
SFR(DMYQCH_CON_ABOX_QCH_CPU, 0x3000, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK4, 0x3094, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_CNT, 0x30b0, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK5, 0x3098, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_CCLK_ASB, 0x30ac, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_BCLK6, 0x309c, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_XCLK0, 0x30d4, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_PCMC_CLK, 0x30d0, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_C2A0, 0x30a4, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_C2A1, 0x30a8, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_XCLK1, 0x30d8, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_XCLK2, 0x30dc, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_CPU0, 0x30b4, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_CPU1, 0x30b8, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_CPU2, 0x30bc, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_NEON0, 0x30c4, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_NEON1, 0x30c8, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_NEON2, 0x30cc, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_L2, 0x30c0, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_CCLK_ACP, 0x3164, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_ACLK_ACP, 0x315c, CMU_AUD),
|
|
SFR(QCH_CON_ABOX_QCH_ACLK_ASB, 0x3160, CMU_AUD),
|
|
SFR(QCH_CON_AUD_CMU_AUD_QCH, 0x30e0, CMU_AUD),
|
|
SFR(QCH_CON_BAAW_D_AUDCHUBVTS_QCH, 0x30e4, CMU_AUD),
|
|
SFR(DMYQCH_CON_DFTMUX_AUD_QCH, 0x3004, CMU_AUD),
|
|
SFR(QCH_CON_DMAILBOX_AUD_QCH_PCLK, 0x3170, CMU_AUD),
|
|
SFR(QCH_CON_DMAILBOX_AUD_QCH_ACLK, 0x3168, CMU_AUD),
|
|
SFR(QCH_CON_DMAILBOX_AUD_QCH_CCLK, 0x316c, CMU_AUD),
|
|
SFR(QCH_CON_DMIC_AUD0_QCH_PCLK, 0x30e8, CMU_AUD),
|
|
SFR(DMYQCH_CON_DMIC_AUD0_QCH_DMIC, 0x3008, CMU_AUD),
|
|
SFR(QCH_CON_DMIC_AUD1_QCH_PCLK, 0x30ec, CMU_AUD),
|
|
SFR(DMYQCH_CON_DMIC_AUD1_QCH_DMIC, 0x300c, CMU_AUD),
|
|
SFR(QCH_CON_DMIC_AUD2_QCH_PCLK, 0x30f0, CMU_AUD),
|
|
SFR(DMYQCH_CON_DMIC_AUD2_QCH_DMIC, 0x3010, CMU_AUD),
|
|
SFR(QCH_CON_D_TZPC_AUD_QCH, 0x30f4, CMU_AUD),
|
|
SFR(QCH_CON_LH_AXI_MI_PERI_ASB_QCH, 0x3174, CMU_AUD),
|
|
SFR(QCH_CON_LH_AXI_SI_PERI_ASB_QCH, 0x3178, CMU_AUD),
|
|
SFR(QCH_CON_LH_QDI_SI_D_AUD_QCH, 0x30f8, CMU_AUD),
|
|
SFR(QCH_CON_MAILBOX_AUD0_QCH, 0x30fc, CMU_AUD),
|
|
SFR(QCH_CON_MAILBOX_AUD1_QCH, 0x3100, CMU_AUD),
|
|
SFR(QCH_CON_MAILBOX_AUD2_QCH, 0x3104, CMU_AUD),
|
|
SFR(QCH_CON_MAILBOX_AUD3_QCH, 0x3108, CMU_AUD),
|
|
SFR(QCH_CON_PPMU_AUD_QCH, 0x310c, CMU_AUD),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH, 0x3110, CMU_AUD),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH, 0x3114, CMU_AUD),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH, 0x3118, CMU_AUD),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH, 0x311c, CMU_AUD),
|
|
SFR(QCH_CON_SERIAL_LIF_QCH_PCLK, 0x3124, CMU_AUD),
|
|
SFR(QCH_CON_SERIAL_LIF_QCH_BCLK, 0x3014, CMU_AUD),
|
|
SFR(QCH_CON_SERIAL_LIF_QCH_ACLK, 0x3120, CMU_AUD),
|
|
SFR(QCH_CON_SERIAL_LIF_QCH_CCLK, 0x317c, CMU_AUD),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_AUD_QCH, 0x3128, CMU_AUD),
|
|
SFR(QCH_CON_SLH_AXI_MI_LD_HSI0AUD_QCH, 0x312c, CMU_AUD),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_AUD_QCH, 0x3130, CMU_AUD),
|
|
SFR(QCH_CON_SLH_AXI_SI_LD_AUDHSI0_QCH, 0x3134, CMU_AUD),
|
|
SFR(QCH_CON_SLH_AXI_SI_LP_AUDCHUBVTS_QCH, 0x3138, CMU_AUD),
|
|
SFR(QCH_CON_SMMU_AUD_QCH_S1, 0x313c, CMU_AUD),
|
|
SFR(QCH_CON_SMMU_AUD_QCH_S2, 0x3140, CMU_AUD),
|
|
SFR(QCH_CON_SYSREG_AUD_QCH, 0x3144, CMU_AUD),
|
|
SFR(QCH_CON_TREX_AUD_QCH, 0x3148, CMU_AUD),
|
|
SFR(QCH_CON_VGEN_LITE_AUD_QCH, 0x314c, CMU_AUD),
|
|
SFR(QCH_CON_WDT_AUD_QCH, 0x3150, CMU_AUD),
|
|
SFR(DMYQCH_CON_ADD_BRP_QCH, 0x3000, CMU_BRP),
|
|
SFR(QCH_CON_BRP_CMU_BRP_QCH, 0x301c, CMU_BRP),
|
|
SFR(QCH_CON_BUSIF_ADD_BRP_QCH, 0x305c, CMU_BRP),
|
|
SFR(QCH_CON_BYRP_QCH, 0x3030, CMU_BRP),
|
|
SFR(QCH_CON_BYRP_QCH_C2S_ZSL, 0x3038, CMU_BRP),
|
|
SFR(QCH_CON_BYRP_QCH_C2S_BYR, 0x3034, CMU_BRP),
|
|
SFR(QCH_CON_D_TZPC_BRP_QCH, 0x3020, CMU_BRP),
|
|
SFR(QCH_CON_LH_AST_MI_OTF_CSISBRP_QCH, 0x3060, CMU_BRP),
|
|
SFR(QCH_CON_LH_AST_SI_OTF0_BRPCSIS_QCH, 0x3064, CMU_BRP),
|
|
SFR(QCH_CON_LH_AST_SI_OTF1_BRPCSIS_QCH, 0x3068, CMU_BRP),
|
|
SFR(QCH_CON_LH_AST_SI_OTF_BRPMCSC_QCH, 0x306c, CMU_BRP),
|
|
SFR(QCH_CON_LH_AXI_SI_D0_BRP_QCH, 0x3028, CMU_BRP),
|
|
SFR(QCH_CON_LH_AXI_SI_D1_BRP_QCH, 0x3070, CMU_BRP),
|
|
SFR(QCH_CON_LH_AXI_SI_D2_BRP_QCH, 0x3074, CMU_BRP),
|
|
SFR(QCH_CON_L_SIU_BRP_QCH, 0x3078, CMU_BRP),
|
|
SFR(QCH_CON_PPMU_D0_BRP_QCH, 0x302c, CMU_BRP),
|
|
SFR(QCH_CON_PPMU_D1_BRP_QCH, 0x307c, CMU_BRP),
|
|
SFR(QCH_CON_PPMU_D2_BRP_QCH, 0x3080, CMU_BRP),
|
|
SFR(QCH_CON_RGBP_QCH, 0x3084, CMU_BRP),
|
|
SFR(QCH_CON_RGBP_QCH_VOTF0, 0x3088, CMU_BRP),
|
|
SFR(QCH_CON_RGBP_QCH_VOTF1, 0x308c, CMU_BRP),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_BRP_QCH, 0x303c, CMU_BRP),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_BRP_QCH, 0x3040, CMU_BRP),
|
|
SFR(QCH_CON_SYSMMU_D0_BRP_QCH_S1, 0x3044, CMU_BRP),
|
|
SFR(QCH_CON_SYSMMU_D0_BRP_QCH_S2, 0x3048, CMU_BRP),
|
|
SFR(QCH_CON_SYSMMU_D1_BRP_QCH_S1, 0x3090, CMU_BRP),
|
|
SFR(QCH_CON_SYSMMU_D1_BRP_QCH_S2, 0x3094, CMU_BRP),
|
|
SFR(QCH_CON_SYSMMU_D2_BRP_QCH_S1, 0x3098, CMU_BRP),
|
|
SFR(QCH_CON_SYSMMU_D2_BRP_QCH_S2, 0x309c, CMU_BRP),
|
|
SFR(QCH_CON_SYSREG_BRP_QCH, 0x304c, CMU_BRP),
|
|
SFR(QCH_CON_VGEN_LITE_BYRP_QCH, 0x3050, CMU_BRP),
|
|
SFR(QCH_CON_VGEN_LITE_RGBP_QCH, 0x30a0, CMU_BRP),
|
|
SFR(QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH, 0x302c, CMU_CHUB),
|
|
SFR(QCH_CON_APBIF_GPIO_CHUB_QCH, 0x3030, CMU_CHUB),
|
|
SFR(QCH_CON_CHUB_CMU_CHUB_QCH, 0x3048, CMU_CHUB),
|
|
SFR(QCH_CON_CM4_CHUB_QCH_CPU, 0x304c, CMU_CHUB),
|
|
SFR(QCH_CON_I2C_CHUB_QCH, 0x305c, CMU_CHUB),
|
|
SFR(QCH_CON_I3C_CHUB_QCH_S, 0x3064, CMU_CHUB),
|
|
SFR(QCH_CON_I3C_CHUB_QCH_P, 0x3060, CMU_CHUB),
|
|
SFR(QCH_CON_LH_AXI_MI_IP_VC2CHUB_QCH, 0x3078, CMU_CHUB),
|
|
SFR(QCH_CON_LH_AXI_SI_ID_CHUB2VC_QCH, 0x3080, CMU_CHUB),
|
|
SFR(QCH_CON_MAILBOX_CHUB_ABOX_QCH, 0x3018, CMU_CHUB),
|
|
SFR(QCH_CON_MAILBOX_CHUB_DNC_QCH, 0x306c, CMU_CHUB),
|
|
SFR(QCH_CON_PWM_CHUB_QCH, 0x3070, CMU_CHUB),
|
|
SFR(QCH_CON_SPI_I2C_CHUB0_QCH, 0x3084, CMU_CHUB),
|
|
SFR(QCH_CON_SPI_I2C_CHUB1_QCH, 0x3088, CMU_CHUB),
|
|
SFR(QCH_CON_SPI_MULTI_SLV_Q_CTRL_CHUB_QCH, 0x308c, CMU_CHUB),
|
|
SFR(QCH_CON_SYSREG_CHUB_QCH, 0x3094, CMU_CHUB),
|
|
SFR(QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH, 0x309c, CMU_CHUB),
|
|
SFR(QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH, 0x3098, CMU_CHUB),
|
|
SFR(QCH_CON_TIMER_CHUB_QCH, 0x30a0, CMU_CHUB),
|
|
SFR(QCH_CON_USI_CHUB0_QCH, 0x30a4, CMU_CHUB),
|
|
SFR(QCH_CON_USI_CHUB1_QCH, 0x30a8, CMU_CHUB),
|
|
SFR(QCH_CON_USI_CHUB2_QCH, 0x30ac, CMU_CHUB),
|
|
SFR(QCH_CON_USI_CHUB3_QCH, 0x30b0, CMU_CHUB),
|
|
SFR(QCH_CON_WDT_CHUB_QCH, 0x30b4, CMU_CHUB),
|
|
SFR(QCH_CON_APBIF_UPMU_CHUB_QCH, 0x3020, CMU_CHUBVTS),
|
|
SFR(QCH_CON_APB_SEMA_DMAILBOX_QCH, 0x3024, CMU_CHUBVTS),
|
|
SFR(QCH_CON_APB_SEMA_PDMA_QCH, 0x3028, CMU_CHUBVTS),
|
|
SFR(QCH_CON_BAAW_CHUB_QCH, 0x302c, CMU_CHUBVTS),
|
|
SFR(QCH_CON_BAAW_LD_CHUBVTS_QCH, 0x3030, CMU_CHUBVTS),
|
|
SFR(QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH, 0x3034, CMU_CHUBVTS),
|
|
SFR(QCH_CON_CHUB_ALV_QCH_PMU, 0x3038, CMU_CHUBVTS),
|
|
SFR(QCH_CON_DMAILBOX_CHUBVTS_QCH_PCLK, 0x3044, CMU_CHUBVTS),
|
|
SFR(QCH_CON_DMAILBOX_CHUBVTS_QCH_ACLK, 0x303c, CMU_CHUBVTS),
|
|
SFR(QCH_CON_DMAILBOX_CHUBVTS_QCH_CCLK, 0x3040, CMU_CHUBVTS),
|
|
SFR(QCH_CON_D_TZPC_CHUBVTS_QCH, 0x3048, CMU_CHUBVTS),
|
|
SFR(QCH_CON_LH_AXI_MI_ID_CHUB2VC_QCH, 0x304c, CMU_CHUBVTS),
|
|
SFR(QCH_CON_LH_AXI_MI_ID_VTS2VC_QCH, 0x3050, CMU_CHUBVTS),
|
|
SFR(QCH_CON_LH_AXI_SI_IP_VC2CHUB_QCH, 0x3054, CMU_CHUBVTS),
|
|
SFR(QCH_CON_LH_AXI_SI_IP_VC2VTS_QCH, 0x3058, CMU_CHUBVTS),
|
|
SFR(QCH_CON_MAILBOX_VTS_CHUB_QCH, 0x305c, CMU_CHUBVTS),
|
|
SFR(QCH_CON_PDMA_CHUBVTS_QCH, 0x3060, CMU_CHUBVTS),
|
|
SFR(QCH_CON_SLH_AXI_MI_LP_AUDCHUBVTS_QCH, 0x3064, CMU_CHUBVTS),
|
|
SFR(QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH, 0x3068, CMU_CHUBVTS),
|
|
SFR(QCH_CON_SLH_AXI_MI_LP_DNCCHUBVTS_QCH, 0x306c, CMU_CHUBVTS),
|
|
SFR(QCH_CON_SLH_AXI_SI_LD_CHUBVTS_QCH, 0x3070, CMU_CHUBVTS),
|
|
SFR(QCH_CON_SWEEPER_LD_CHUBVTS_QCH, 0x3074, CMU_CHUBVTS),
|
|
SFR(QCH_CON_SYSREG_CHUBVTS_QCH, 0x3078, CMU_CHUBVTS),
|
|
SFR(QCH_CON_VGEN_LITE_CHUBVTS_QCH, 0x307c, CMU_CHUBVTS),
|
|
SFR(QCH_CON_APBIF_GPIO_CMGP_QCH, 0x3008, CMU_CMGP),
|
|
SFR(QCH_CON_CMGP_CMU_CMGP_QCH, 0x300c, CMU_CMGP),
|
|
SFR(QCH_CON_CMGP_I2C_QCH, 0x3010, CMU_CMGP),
|
|
SFR(QCH_CON_D_TZPC_CMGP_QCH, 0x3014, CMU_CMGP),
|
|
SFR(QCH_CON_I2C_CMGP2_QCH, 0x3018, CMU_CMGP),
|
|
SFR(QCH_CON_I2C_CMGP3_QCH, 0x301c, CMU_CMGP),
|
|
SFR(QCH_CON_I2C_CMGP4_QCH, 0x3020, CMU_CMGP),
|
|
SFR(QCH_CON_I2C_CMGP5_QCH, 0x3024, CMU_CMGP),
|
|
SFR(QCH_CON_I2C_CMGP6_QCH, 0x3028, CMU_CMGP),
|
|
SFR(QCH_CON_SLH_AXI_MI_LP_CMGP_QCH, 0x3034, CMU_CMGP),
|
|
SFR(QCH_CON_SLH_AXI_SI_LP_CMGPUFD_QCH, 0x3038, CMU_CMGP),
|
|
SFR(QCH_CON_SPI_I2C_CMGP0_QCH, 0x303c, CMU_CMGP),
|
|
SFR(QCH_CON_SPI_I2C_CMGP1_QCH, 0x3040, CMU_CMGP),
|
|
SFR(QCH_CON_SPI_MULTI_SLV_Q_CTRL_CMGP_QCH, 0x3044, CMU_CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP_QCH, 0x305c, CMU_CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2APM_QCH, 0x3048, CMU_CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2CHUB_QCH, 0x304c, CMU_CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2CP_QCH, 0x3050, CMU_CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2GNSS_QCH, 0x3054, CMU_CMGP),
|
|
SFR(QCH_CON_SYSREG_CMGP2PMU_AP_QCH, 0x3058, CMU_CMGP),
|
|
SFR(QCH_CON_USI_CMGP0_QCH, 0x3060, CMU_CMGP),
|
|
SFR(QCH_CON_USI_CMGP1_QCH, 0x3064, CMU_CMGP),
|
|
SFR(QCH_CON_USI_CMGP2_QCH, 0x3068, CMU_CMGP),
|
|
SFR(QCH_CON_USI_CMGP3_QCH, 0x306c, CMU_CMGP),
|
|
SFR(QCH_CON_USI_CMGP4_QCH, 0x3070, CMU_CMGP),
|
|
SFR(QCH_CON_USI_CMGP5_QCH, 0x3074, CMU_CMGP),
|
|
SFR(QCH_CON_USI_CMGP6_QCH, 0x3078, CMU_CMGP),
|
|
SFR(DMYQCH_CON_CMU_TOP_CMUREF_QCH, 0x3000, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0, 0x3004, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1, 0x3008, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2, 0x300c, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3, 0x3010, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4, 0x3014, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5, 0x3018, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6, 0x301c, CMU_TOP),
|
|
SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7, 0x3020, CMU_TOP),
|
|
SFR(DMYQCH_CON_ADD_CPUCL0_0_QCH, 0x3000, CMU_CPUCL0),
|
|
SFR(QCH_CON_BUSIF_ADD_CPUCL0_0_QCH, 0x3010, CMU_CPUCL0),
|
|
SFR(QCH_CON_BUSIF_STR_CPUCL0_0_QCH, 0x3014, CMU_CPUCL0),
|
|
SFR(QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE, 0x3018, CMU_CPUCL0),
|
|
SFR(DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH, 0x3004, CMU_CPUCL0),
|
|
SFR(QCH_CON_CPUCL0_QCH_CORE0, 0x3028, CMU_CPUCL0),
|
|
SFR(QCH_CON_CPUCL0_QCH_CORE1, 0x302c, CMU_CPUCL0),
|
|
SFR(QCH_CON_CPUCL0_QCH_CORE2, 0x3030, CMU_CPUCL0),
|
|
SFR(QCH_CON_CPUCL0_QCH_CORE3, 0x3034, CMU_CPUCL0),
|
|
SFR(QCH_CON_CPUCL0_QCH_COMPLEX0, 0x3020, CMU_CPUCL0),
|
|
SFR(QCH_CON_CPUCL0_QCH_COMPLEX1, 0x3024, CMU_CPUCL0),
|
|
SFR(QCH_CON_CPUCL0_CMU_CPUCL0_QCH, 0x301c, CMU_CPUCL0),
|
|
SFR(QCH_CON_HTU_CPUCL0_QCH_PCLK, 0x3038, CMU_CPUCL0),
|
|
SFR(QCH_CON_HTU_CPUCL0_QCH_CLK, 0x3044, CMU_CPUCL0),
|
|
SFR(QCH_CON_LH_ATB_SI_IT_DDCLIT_QCH, 0x303c, CMU_CPUCL0),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CPUCL0_POWERIP_QCH, 0x3048, CMU_CPUCL0),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_HTU_QCH, 0x304c, CMU_CPUCL0),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_QCH, 0x3050, CMU_CPUCL0),
|
|
SFR(DMYQCH_CON_STR_CPUCL0_0_QCH, 0x3008, CMU_CPUCL0),
|
|
SFR(QCH_CON_U_DDD_CTRL_CORE__CPUCL0_QCH, 0x3040, CMU_CPUCL0),
|
|
SFR(QCH_CON_BPS_CPUCL0_QCH, 0x305c, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_BUSIF_DDC_CPUCL0_0_QCH, 0x3060, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_BUSIF_DDC_CPUCL0_1_QCH, 0x3064, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_CFM_CPUCL0_QCH, 0x306c, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH, 0x3070, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_CSSYS_QCH, 0x3074, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_D_TZPC_CPUCL0_QCH, 0x3078, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LH_ATB_MI_IT_CLUSTER0_QCH, 0x307c, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LH_ATB_MI_IT_DDCBIG_QCH, 0x3080, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LH_ATB_MI_IT_DDCDSU_QCH, 0x3084, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LH_ATB_MI_IT_DDCLIT_QCH, 0x3088, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LH_ATB_MI_IT_DDCMID0_QCH, 0x308c, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LH_ATB_MI_IT_DDCMID1_QCH, 0x3090, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LH_ATB_MI_IT_DDCMID2_QCH, 0x3094, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LH_ATB_MI_T_BDU_QCH, 0x3098, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LH_ATB_MI_T_DDCG3D_QCH, 0x309c, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_LH_AXI_SI_G_CSSYS_QCH, 0x30a0, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_PMU_PCSM_PM_QCH, 0x30a4, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH, 0x30a8, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH, 0x30ac, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SECJTAG_QCH, 0x30b0, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH, 0x30b4, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SLH_AXI_MI_IG_CSSYS_QCH, 0x30b8, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SLH_AXI_MI_IG_DBGCORE_QCH, 0x30bc, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SLH_AXI_MI_IG_ETR_QCH, 0x30c0, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SLH_AXI_MI_IG_STM_QCH, 0x30c4, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH, 0x30c8, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SLH_AXI_SI_IG_CSSYS_QCH, 0x30cc, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SLH_AXI_SI_IG_DBGCORE_QCH, 0x30d0, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SLH_AXI_SI_IG_ETR_QCH, 0x30d4, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SLH_AXI_SI_IG_STM_QCH, 0x30d8, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_SYSREG_CPUCL0_QCH, 0x30dc, CMU_CPUCL0_GLB),
|
|
SFR(QCH_CON_TREX_CPUCL0_QCH, 0x30e0, CMU_CPUCL0_GLB),
|
|
SFR(DMYQCH_CON_ADD_CPUCL0_1_QCH, 0x3000, CMU_CPUCL1),
|
|
SFR(QCH_CON_BUSIF_ADD_CPUCL0_1_QCH, 0x3018, CMU_CPUCL1),
|
|
SFR(QCH_CON_BUSIF_STR_CPUCL0_1_QCH, 0x301c, CMU_CPUCL1),
|
|
SFR(QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE, 0x3020, CMU_CPUCL1),
|
|
SFR(DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH, 0x3004, CMU_CPUCL1),
|
|
SFR(QCH_CON_CPUCL1_QCH_CORE4, 0x3028, CMU_CPUCL1),
|
|
SFR(QCH_CON_CPUCL1_QCH_CORE5, 0x302c, CMU_CPUCL1),
|
|
SFR(QCH_CON_CPUCL1_QCH_CORE6, 0x3030, CMU_CPUCL1),
|
|
SFR(QCH_CON_CPUCL1_CMU_CPUCL1_QCH, 0x3024, CMU_CPUCL1),
|
|
SFR(QCH_CON_HTU_CPUCL1_0_QCH_PCLK, 0x3038, CMU_CPUCL1),
|
|
SFR(QCH_CON_HTU_CPUCL1_0_QCH_CLK, 0x3034, CMU_CPUCL1),
|
|
SFR(QCH_CON_HTU_CPUCL1_1_QCH_PCLK, 0x3040, CMU_CPUCL1),
|
|
SFR(QCH_CON_HTU_CPUCL1_1_QCH_CLK, 0x303c, CMU_CPUCL1),
|
|
SFR(QCH_CON_HTU_CPUCL1_2_QCH_CLK, 0x3044, CMU_CPUCL1),
|
|
SFR(QCH_CON_HTU_CPUCL1_2_QCH_PCLK, 0x3048, CMU_CPUCL1),
|
|
SFR(QCH_CON_LH_ATB_SI_IT_DDCMID0_QCH, 0x304c, CMU_CPUCL1),
|
|
SFR(QCH_CON_LH_ATB_SI_IT_DDCMID1_QCH, 0x3050, CMU_CPUCL1),
|
|
SFR(QCH_CON_LH_ATB_SI_IT_DDCMID2_QCH, 0x3054, CMU_CPUCL1),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CPUCL1_POWERIP_QCH, 0x3064, CMU_CPUCL1),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_HTU_QCH, 0x3068, CMU_CPUCL1),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_QCH, 0x306c, CMU_CPUCL1),
|
|
SFR(DMYQCH_CON_STR_CPUCL0_1_QCH, 0x3008, CMU_CPUCL1),
|
|
SFR(QCH_CON_U_DDD_CTRL_CORE__CPUCL1_0_QCH, 0x3058, CMU_CPUCL1),
|
|
SFR(QCH_CON_U_DDD_CTRL_CORE__CPUCL1_1_QCH, 0x305c, CMU_CPUCL1),
|
|
SFR(QCH_CON_U_DDD_CTRL_CORE__CPUCL1_2_QCH, 0x3060, CMU_CPUCL1),
|
|
SFR(DMYQCH_CON_ADD_CPUCL0_2_QCH, 0x3000, CMU_CPUCL2),
|
|
SFR(QCH_CON_BUSIF_ADD_CPUCL0_2_QCH, 0x3010, CMU_CPUCL2),
|
|
SFR(QCH_CON_BUSIF_STR_CPUCL0_2_QCH, 0x3014, CMU_CPUCL2),
|
|
SFR(QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE, 0x3018, CMU_CPUCL2),
|
|
SFR(DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH, 0x3004, CMU_CPUCL2),
|
|
SFR(QCH_CON_CPUCL2_QCH_CORE7, 0x3020, CMU_CPUCL2),
|
|
SFR(QCH_CON_CPUCL2_CMU_CPUCL2_QCH, 0x301c, CMU_CPUCL2),
|
|
SFR(QCH_CON_HTU_CPUCL2_QCH_PCLK, 0x3028, CMU_CPUCL2),
|
|
SFR(QCH_CON_HTU_CPUCL2_QCH_CLK, 0x3024, CMU_CPUCL2),
|
|
SFR(QCH_CON_LH_ATB_SI_IT_DDCBIG_QCH, 0x302c, CMU_CPUCL2),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CPUCL2_POWERIP_QCH, 0x3034, CMU_CPUCL2),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_HTU_QCH, 0x3038, CMU_CPUCL2),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_QCH, 0x303c, CMU_CPUCL2),
|
|
SFR(DMYQCH_CON_STR_CPUCL0_2_QCH, 0x3008, CMU_CPUCL2),
|
|
SFR(QCH_CON_U_DDD_CTRL_CORE__CPUCL2_QCH, 0x3030, CMU_CPUCL2),
|
|
SFR(QCH_CON_CSIS_CMU_CSIS_QCH, 0x302c, CMU_CSIS),
|
|
SFR(QCH_CON_D_TZPC_CSIS_QCH, 0x3030, CMU_CSIS),
|
|
SFR(QCH_CON_LH_AXI_MI_LP_INT_P0P1_CSIS_QCH, 0x3034, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0, 0x3038, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1, 0x303c, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2, 0x3040, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3, 0x3044, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4, 0x3048, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5, 0x304c, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6, 0x3050, CMU_CSIS),
|
|
SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_UFD, 0x3054, CMU_CSIS),
|
|
SFR(QCH_CON_SLH_AST_SI_OTF_CSISUFD_QCH, 0x3058, CMU_CSIS),
|
|
SFR(QCH_CON_SLH_AXI_MI_LP_UFDCSIS_QCH, 0x305c, CMU_CSIS),
|
|
SFR(QCH_CON_SYSREG_CSIS_QCH, 0x3060, CMU_CSIS),
|
|
SFR(QCH_CON_CSTAT_CMU_CSTAT_QCH, 0x3028, CMU_CSTAT),
|
|
SFR(QCH_CON_D_TZPC_CSTAT_QCH, 0x302c, CMU_CSTAT),
|
|
SFR(QCH_CON_LH_AST_MI_OTF0_CSISCSTAT_QCH, 0x3030, CMU_CSTAT),
|
|
SFR(QCH_CON_LH_AST_MI_OTF1_CSISCSTAT_QCH, 0x3034, CMU_CSTAT),
|
|
SFR(QCH_CON_LH_AST_MI_OTF2_CSISCSTAT_QCH, 0x3038, CMU_CSTAT),
|
|
SFR(QCH_CON_LH_AST_MI_OTF3_CSISCSTAT_QCH, 0x303c, CMU_CSTAT),
|
|
SFR(QCH_CON_LH_AXI_SI_D_CSTAT_QCH, 0x3040, CMU_CSTAT),
|
|
SFR(QCH_CON_PPMU_CSTAT_QCH, 0x3044, CMU_CSTAT),
|
|
SFR(QCH_CON_SIPU_CSTAT_QCH, 0x3048, CMU_CSTAT),
|
|
SFR(QCH_CON_SIPU_CSTAT_QCH_C2RD, 0x3058, CMU_CSTAT),
|
|
SFR(QCH_CON_SIPU_CSTAT_QCH_C2DS, 0x3054, CMU_CSTAT),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_CSTAT_QCH, 0x305c, CMU_CSTAT),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_CSTAT_QCH, 0x3060, CMU_CSTAT),
|
|
SFR(QCH_CON_SYSMMU_D_CSTAT_QCH_S1, 0x3064, CMU_CSTAT),
|
|
SFR(QCH_CON_SYSMMU_D_CSTAT_QCH_S2, 0x3068, CMU_CSTAT),
|
|
SFR(QCH_CON_SYSREG_CSTAT_QCH, 0x306c, CMU_CSTAT),
|
|
SFR(QCH_CON_VGEN_LITE_CSTAT0_QCH, 0x3070, CMU_CSTAT),
|
|
SFR(QCH_CON_VGEN_LITE_CSTAT1_QCH, 0x3074, CMU_CSTAT),
|
|
SFR(QCH_CON_APBIF_S2D_DBGCORE_QCH, 0x3018, CMU_DBGCORE),
|
|
SFR(QCH_CON_ASYNCAHBMASTER_DBGCORE_QCH, 0x301c, CMU_DBGCORE),
|
|
SFR(QCH_CON_DBGCORE_CMU_DBGCORE_QCH, 0x3020, CMU_DBGCORE),
|
|
SFR(QCH_CON_D_TZPC_DBGCORE_QCH, 0x3024, CMU_DBGCORE),
|
|
SFR(QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_DBG, 0x3028, CMU_DBGCORE),
|
|
SFR(QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_GREBE, 0x302c, CMU_DBGCORE),
|
|
SFR(QCH_CON_MDIS_DBGCORE_QCH, 0x3030, CMU_DBGCORE),
|
|
SFR(QCH_CON_MDIS_DBGCORE_QCH_OSC, 0x3034, CMU_DBGCORE),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_DBGCORE_GREBE_QCH, 0x3038, CMU_DBGCORE),
|
|
SFR(QCH_CON_SLH_AXI_MI_IP_APM_QCH, 0x303c, CMU_DBGCORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH, 0x3040, CMU_DBGCORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH, 0x3044, CMU_DBGCORE),
|
|
SFR(QCH_CON_SLH_AXI_SI_ID_DBGCORE_QCH, 0x3048, CMU_DBGCORE),
|
|
SFR(QCH_CON_SYSREG_DBGCORE_QCH, 0x3050, CMU_DBGCORE),
|
|
SFR(QCH_CON_SYSREG_DBGCORE_CORE_QCH, 0x304c, CMU_DBGCORE),
|
|
SFR(QCH_CON_WDT_DBGCORE_QCH, 0x3054, CMU_DBGCORE),
|
|
SFR(DMYQCH_CON_ADD_DNC_QCH, 0x3000, CMU_DNC),
|
|
SFR(DMYQCH_CON_ADM_DAP_DNC_QCH, 0x3004, CMU_DNC),
|
|
SFR(QCH_CON_BAAW_DNCCHUBVTS_QCH, 0x3100, CMU_DNC),
|
|
SFR(QCH_CON_BUSIF_ADD_DNC_QCH, 0x3104, CMU_DNC),
|
|
SFR(QCH_CON_BUSIF_DDD_DNC_QCH, 0x3108, CMU_DNC),
|
|
SFR(QCH_CON_DNC_CMU_DNC_QCH, 0x3110, CMU_DNC),
|
|
SFR(QCH_CON_D_TZPC_DNC_QCH, 0x3114, CMU_DNC),
|
|
SFR(QCH_CON_HTU_DNC_QCH_PCLK, 0x311c, CMU_DNC),
|
|
SFR(QCH_CON_HTU_DNC_QCH_CLK, 0x3118, CMU_DNC),
|
|
SFR(QCH_CON_IP_DNC_QCH, 0x3120, CMU_DNC),
|
|
SFR(QCH_CON_LH_AST_MI_OTF_UFDDNC_QCH, 0x31c4, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_DSP0DNC_SFR_QCH, 0x312c, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_DSP0DNC_SHMEM_QCH, 0x3130, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_GNPU0DNC_SHMEM_QCH, 0x313c, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_GNPU1DNC_SHMEM_QCH, 0x3140, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_RQ_GNPU0_QCH, 0x3124, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_RQ_GNPU1_QCH, 0x3128, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA0_QCH, 0x3144, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA1_QCH, 0x3148, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA2_QCH, 0x314c, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA3_QCH, 0x3150, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA4_QCH, 0x3154, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA5_QCH, 0x3158, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA6_QCH, 0x315c, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA7_QCH, 0x3160, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU0_QCH, 0x3164, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU1_QCH, 0x3168, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU2_QCH, 0x316c, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU3_QCH, 0x3170, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_MI_LP_IPDNC_QCH, 0x3174, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_SI_LD0_GNPU0_QCH, 0x3178, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_SI_LD0_GNPU1_QCH, 0x317c, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_SI_LD1_GNPU0_QCH, 0x3180, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_SI_LD1_GNPU1_QCH, 0x3184, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_CTRL_GNPU0_QCH, 0x3188, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_CTRL_GNPU1_QCH, 0x318c, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_DNCDSP0_DMA_QCH, 0x3190, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_DNCDSP0_SFR_QCH, 0x3194, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_SI_LP_DNCSDMA_QCH, 0x31a0, CMU_DNC),
|
|
SFR(QCH_CON_LH_AXI_SI_LP_IPDNC_QCH, 0x31a4, CMU_DNC),
|
|
SFR(QCH_CON_PPMU_IPDNC_QCH, 0x31a8, CMU_DNC),
|
|
SFR(QCH_CON_PPMU_SDMA0_QCH, 0x31ac, CMU_DNC),
|
|
SFR(QCH_CON_PPMU_SDMA1_QCH, 0x31b0, CMU_DNC),
|
|
SFR(QCH_CON_PPMU_SDMA2_QCH, 0x31b4, CMU_DNC),
|
|
SFR(QCH_CON_PPMU_SDMA3_QCH, 0x31b8, CMU_DNC),
|
|
SFR(QCH_CON_SIU_G_PPMU_DNC_QCH, 0x31bc, CMU_DNC),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_DNC_QCH, 0x31c0, CMU_DNC),
|
|
SFR(QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU0_QCH, 0x31c8, CMU_DNC),
|
|
SFR(QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU1_QCH, 0x31cc, CMU_DNC),
|
|
SFR(QCH_CON_SLH_AXI_MI_LD_DSP0DNC_CACHE_QCH, 0x31d0, CMU_DNC),
|
|
SFR(QCH_CON_SLH_AXI_MI_LD_UFDDNC_QCH, 0x31d8, CMU_DNC),
|
|
SFR(QCH_CON_SLH_AXI_MI_LP_ALIVEDNC_QCH, 0x31dc, CMU_DNC),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_DNC_QCH, 0x31e0, CMU_DNC),
|
|
SFR(QCH_CON_SLH_AXI_SI_LP_DNCCHUBVTS_QCH, 0x31e8, CMU_DNC),
|
|
SFR(QCH_CON_SLH_AXI_SI_LP_DSP0_QCH, 0x30ac, CMU_DNC),
|
|
SFR(QCH_CON_SLH_AXI_SI_LP_GNPU0_QCH, 0x31ec, CMU_DNC),
|
|
SFR(QCH_CON_SLH_AXI_SI_LP_GNPU1_QCH, 0x31f0, CMU_DNC),
|
|
SFR(QCH_CON_SLH_AXI_SI_LP_SDMA_QCH, 0x30b0, CMU_DNC),
|
|
SFR(QCH_CON_SYSMMU_IPDNC_QCH_S1, 0x31fc, CMU_DNC),
|
|
SFR(QCH_CON_SYSMMU_IPDNC_QCH_S2, 0x3200, CMU_DNC),
|
|
SFR(QCH_CON_SYSMMU_SDMA0_QCH_S1, 0x3204, CMU_DNC),
|
|
SFR(QCH_CON_SYSMMU_SDMA0_QCH_S2, 0x3208, CMU_DNC),
|
|
SFR(QCH_CON_SYSMMU_SDMA1_QCH_S1, 0x320c, CMU_DNC),
|
|
SFR(QCH_CON_SYSMMU_SDMA1_QCH_S2, 0x3210, CMU_DNC),
|
|
SFR(QCH_CON_SYSMMU_SDMA2_QCH_S1, 0x3214, CMU_DNC),
|
|
SFR(QCH_CON_SYSMMU_SDMA2_QCH_S2, 0x3218, CMU_DNC),
|
|
SFR(QCH_CON_SYSMMU_SDMA3_QCH_S1, 0x321c, CMU_DNC),
|
|
SFR(QCH_CON_SYSMMU_SDMA3_QCH_S2, 0x3220, CMU_DNC),
|
|
SFR(QCH_CON_SYSREG_DNC_QCH, 0x3224, CMU_DNC),
|
|
SFR(QCH_CON_TREX_D_DNC_QCH, 0x3228, CMU_DNC),
|
|
SFR(QCH_CON_VGEN_DNC_QCH, 0x322c, CMU_DNC),
|
|
SFR(QCH_CON_VGEN_LITE_DNC_QCH, 0x3230, CMU_DNC),
|
|
SFR(QCH_CON_DPUB_QCH_DECON, 0x300c, CMU_DPUB),
|
|
SFR(QCH_CON_DPUB_QCH_ALV_DSIM0, 0x3010, CMU_DPUB),
|
|
SFR(QCH_CON_DPUB_QCH_ALV_DSIM1, 0x3014, CMU_DPUB),
|
|
SFR(QCH_CON_DPUB_QCH_ALV_DSIM2, 0x3018, CMU_DPUB),
|
|
SFR(QCH_CON_DPUB_QCH_OSC_DSIM0, 0x3030, CMU_DPUB),
|
|
SFR(QCH_CON_DPUB_QCH_OSC_DSIM1, 0x3034, CMU_DPUB),
|
|
SFR(QCH_CON_DPUB_QCH_OSC_DSIM2, 0x3038, CMU_DPUB),
|
|
SFR(QCH_CON_DPUB_CMU_DPUB_QCH, 0x3008, CMU_DPUB),
|
|
SFR(QCH_CON_D_TZPC_DPUB_QCH, 0x301c, CMU_DPUB),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_DPUB_QCH, 0x3020, CMU_DPUB),
|
|
SFR(QCH_CON_SYSREG_DPUB_QCH, 0x3024, CMU_DPUB),
|
|
SFR(QCH_CON_UPI_M0_QCH, 0x3028, CMU_DPUB),
|
|
SFR(QCH_CON_DPUF_QCH_DPUF0, 0x3030, CMU_DPUF),
|
|
SFR(QCH_CON_DPUF_QCH_VOTF0, 0x3034, CMU_DPUF),
|
|
SFR(QCH_CON_DPUF_QCH_DPUF1, 0x307c, CMU_DPUF),
|
|
SFR(QCH_CON_DPUF_QCH_VOTF1, 0x3084, CMU_DPUF),
|
|
SFR(QCH_CON_DPUF_QCH_SRAMC, 0x3080, CMU_DPUF),
|
|
SFR(QCH_CON_DPUF_CMU_DPUF_QCH, 0x302c, CMU_DPUF),
|
|
SFR(QCH_CON_D_TZPC_DPUF_QCH, 0x3038, CMU_DPUF),
|
|
SFR(QCH_CON_D_TZPC_DPUF1_QCH, 0x3088, CMU_DPUF),
|
|
SFR(QCH_CON_LH_AXI_SI_D1_DPUF_QCH, 0x3044, CMU_DPUF),
|
|
SFR(QCH_CON_PPMU_D0_DPUF0_QCH, 0x3048, CMU_DPUF),
|
|
SFR(QCH_CON_PPMU_D0_DPUF1_QCH, 0x308c, CMU_DPUF),
|
|
SFR(QCH_CON_PPMU_D1_DPUF0_QCH, 0x304c, CMU_DPUF),
|
|
SFR(QCH_CON_PPMU_D1_DPUF1_QCH, 0x3090, CMU_DPUF),
|
|
SFR(QCH_CON_SIU_DPUF_QCH, 0x3050, CMU_DPUF),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_DPUF_QCH, 0x3054, CMU_DPUF),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_DPUF_QCH, 0x3058, CMU_DPUF),
|
|
SFR(QCH_CON_SLH_AXI_SI_D0_DPUF_QCH, 0x305c, CMU_DPUF),
|
|
SFR(QCH_CON_SYSMMU_D0_DPUF0_QCH_S1, 0x3060, CMU_DPUF),
|
|
SFR(QCH_CON_SYSMMU_D0_DPUF0_QCH_S2, 0x3064, CMU_DPUF),
|
|
SFR(QCH_CON_SYSMMU_D0_DPUF1_QCH_S1, 0x3094, CMU_DPUF),
|
|
SFR(QCH_CON_SYSMMU_D0_DPUF1_QCH_S2, 0x3098, CMU_DPUF),
|
|
SFR(QCH_CON_SYSMMU_D1_DPUF0_QCH_S1, 0x3068, CMU_DPUF),
|
|
SFR(QCH_CON_SYSMMU_D1_DPUF0_QCH_S2, 0x306c, CMU_DPUF),
|
|
SFR(QCH_CON_SYSMMU_D1_DPUF1_QCH_S1, 0x309c, CMU_DPUF),
|
|
SFR(QCH_CON_SYSMMU_D1_DPUF1_QCH_S2, 0x30a0, CMU_DPUF),
|
|
SFR(QCH_CON_SYSREG_DPUF_QCH, 0x3070, CMU_DPUF),
|
|
SFR(QCH_CON_DPUF1_QCH_DPUF, 0x3028, CMU_DPUF1),
|
|
SFR(QCH_CON_DPUF1_QCH_VOTF, 0x302c, CMU_DPUF1),
|
|
SFR(QCH_CON_DPUF1_CMU_DPUF1_QCH, 0x3024, CMU_DPUF1),
|
|
SFR(QCH_CON_LH_AXI_SI_D0_DPUF1DPUF0_QCH, 0x3034, CMU_DPUF1),
|
|
SFR(QCH_CON_LH_AXI_SI_D1_DPUF1DPUF0_QCH, 0x3038, CMU_DPUF1),
|
|
SFR(QCH_CON_PPMU_DPUF1D0_QCH, 0x303c, CMU_DPUF1),
|
|
SFR(QCH_CON_PPMU_DPUF1D1_QCH, 0x3040, CMU_DPUF1),
|
|
SFR(QCH_CON_SIU_DPUF1_QCH, 0x3044, CMU_DPUF1),
|
|
SFR(QCH_CON_SLH_ASTL_SI_G_PPMU_DPUF1_QCH, 0x3048, CMU_DPUF1),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_DPUF1_QCH, 0x304c, CMU_DPUF1),
|
|
SFR(QCH_CON_SYSMMU_DPUF1D0_QCH_S1, 0x3050, CMU_DPUF1),
|
|
SFR(QCH_CON_SYSMMU_DPUF1D0_QCH_S2, 0x3054, CMU_DPUF1),
|
|
SFR(QCH_CON_SYSMMU_DPUF1D1_QCH_S1, 0x3058, CMU_DPUF1),
|
|
SFR(QCH_CON_SYSMMU_DPUF1D1_QCH_S2, 0x305c, CMU_DPUF1),
|
|
SFR(QCH_CON_SYSREG_DPUF1_QCH, 0x3060, CMU_DPUF1),
|
|
SFR(QCH_CON_DRCP_QCH, 0x3024, CMU_DRCP),
|
|
SFR(QCH_CON_DRCP_CMU_DRCP_QCH, 0x3020, CMU_DRCP),
|
|
SFR(QCH_CON_D_TZPC_DRCP_QCH, 0x3028, CMU_DRCP),
|
|
SFR(QCH_CON_LH_AST_MI_OTF_YUVPDRCP_QCH, 0x302c, CMU_DRCP),
|
|
SFR(QCH_CON_LH_AST_SI_OTF_DRCPMCSC_QCH, 0x3030, CMU_DRCP),
|
|
SFR(QCH_CON_LH_AXI_SI_D_DRCP_QCH, 0x3034, CMU_DRCP),
|
|
SFR(QCH_CON_PPMU_D_DRCP_QCH, 0x3038, CMU_DRCP),
|
|
SFR(QCH_CON_SLH_ASTL_SI_G_PPMU_DRCP_QCH, 0x303c, CMU_DRCP),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_DRCP_QCH, 0x3040, CMU_DRCP),
|
|
SFR(QCH_CON_SYSMMU_D_DRCP_QCH_S2, 0x3048, CMU_DRCP),
|
|
SFR(QCH_CON_SYSMMU_D_DRCP_QCH_S1, 0x3044, CMU_DRCP),
|
|
SFR(QCH_CON_SYSREG_DRCP_QCH, 0x304c, CMU_DRCP),
|
|
SFR(QCH_CON_VGEN_LITE_D_DRCP_QCH, 0x3050, CMU_DRCP),
|
|
SFR(QCH_CON_DSP_CMU_DSP_QCH, 0x3020, CMU_DSP),
|
|
SFR(QCH_CON_D_TZPC_DSP_QCH, 0x3024, CMU_DSP),
|
|
SFR(QCH_CON_IP_DSP_QCH, 0x3028, CMU_DSP),
|
|
SFR(QCH_CON_LH_AST_MI_LD_STRM_SDMADSP_QCH, 0x302c, CMU_DSP),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_DNCDSP_DMA_QCH, 0x3030, CMU_DSP),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_DNCDSP_SFR_QCH, 0x3034, CMU_DSP),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_DSPDNC_SFR_QCH, 0x3038, CMU_DSP),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_DSPDNC_SHMEM_QCH, 0x303c, CMU_DSP),
|
|
SFR(QCH_CON_SLH_AXI_MI_LP_DSP_QCH, 0x3040, CMU_DSP),
|
|
SFR(QCH_CON_SLH_AXI_SI_LD_DSPDNC_CACHE_QCH, 0x3044, CMU_DSP),
|
|
SFR(QCH_CON_SYSREG_DSP_QCH, 0x3048, CMU_DSP),
|
|
SFR(QCH_CON_BUSIF_STR_CPUCL0_3_QCH, 0x3030, CMU_DSU),
|
|
SFR(QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE, 0x3034, CMU_DSU),
|
|
SFR(QCH_CON_CLUSTER0_QCH_SCLK, 0x3054, CMU_DSU),
|
|
SFR(QCH_CON_CLUSTER0_QCH_ATCLK, 0x3038, CMU_DSU),
|
|
SFR(QCH_CON_CLUSTER0_QCH_PDBGCLK, 0x3048, CMU_DSU),
|
|
SFR(QCH_CON_CLUSTER0_QCH_PCLK, 0x3044, CMU_DSU),
|
|
SFR(QCH_CON_CLUSTER0_QCH_PERIPHCLK, 0x304c, CMU_DSU),
|
|
SFR(QCH_CON_CLUSTER0_QCH_PPUCLK, 0x3050, CMU_DSU),
|
|
SFR(QCH_CON_CLUSTER0_QCH_GIC, 0x3040, CMU_DSU),
|
|
SFR(DMYQCH_CON_CMU_DSU_CMUREF_QCH, 0x3000, CMU_DSU),
|
|
SFR(QCH_CON_DSU_CMU_DSU_QCH, 0x3058, CMU_DSU),
|
|
SFR(QCH_CON_HTU_DSU_QCH_PCLK, 0x305c, CMU_DSU),
|
|
SFR(QCH_CON_HTU_DSU_QCH_CLK, 0x30a0, CMU_DSU),
|
|
SFR(QCH_CON_LH_ACEL_MI_D0_ACP_QCH, 0x30a4, CMU_DSU),
|
|
SFR(QCH_CON_LH_ACEL_MI_D1_ACP_QCH, 0x30a8, CMU_DSU),
|
|
SFR(QCH_CON_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_QCH, 0x3060, CMU_DSU),
|
|
SFR(QCH_CON_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_QCH, 0x3064, CMU_DSU),
|
|
SFR(QCH_CON_LH_ATB_SI_IT_CLUSTER0_QCH, 0x3068, CMU_DSU),
|
|
SFR(QCH_CON_LH_ATB_SI_IT_DDCDSU_QCH, 0x306c, CMU_DSU),
|
|
SFR(QCH_CON_LH_CHI_SI_D0_CLUSTER0_QCH, 0x3070, CMU_DSU),
|
|
SFR(QCH_CON_LH_CHI_SI_D1_CLUSTER0_QCH, 0x3074, CMU_DSU),
|
|
SFR(QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH, 0x3078, CMU_DSU),
|
|
SFR(QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH, 0x307c, CMU_DSU),
|
|
SFR(QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH, 0x3080, CMU_DSU),
|
|
SFR(QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH, 0x3084, CMU_DSU),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CLUSTER_ACLK_QCH, 0x30ac, CMU_DSU),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CLUSTER_ATCLK_QCH, 0x30b0, CMU_DSU),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CLUSTER_GICCLK_QCH, 0x30b4, CMU_DSU),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CLUSTER_MPACTCLK_QCH, 0x30b8, CMU_DSU),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CLUSTER_PCLK_QCH, 0x30bc, CMU_DSU),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_QCH, 0x30c0, CMU_DSU),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CLUSTER_PPUCLK_QCH, 0x30c4, CMU_DSU),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_CLUSTER_SCLK_QCH, 0x30c8, CMU_DSU),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_DSU_POWERIP_QCH, 0x30cc, CMU_DSU),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_DSU_HTU_QCH, 0x30d0, CMU_DSU),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_DSU_POWERIP_QCH, 0x30d4, CMU_DSU),
|
|
SFR(QCH_CON_SLH_AXI_MI_IP_UTILITY_QCH, 0x3088, CMU_DSU),
|
|
SFR(QCH_CON_SLH_AXI_MI_LP_PPU_QCH, 0x308c, CMU_DSU),
|
|
SFR(QCH_CON_SLH_AXI_SI_IP_UTILITY_QCH, 0x3090, CMU_DSU),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_CLUSTER0_NOCL0_QCH, 0x3094, CMU_DSU),
|
|
SFR(DMYQCH_CON_STR_CPUCL0_3_QCH, 0x3004, CMU_DSU),
|
|
SFR(QCH_CON_U_DDD_CTRL_CORE__DSU_QCH, 0x3098, CMU_DSU),
|
|
SFR(DMYQCH_CON_BG3D_PWRCTL_QCH, 0x3000, CMU_G3D),
|
|
SFR(QCH_CON_CFM_G3D_QCH, 0x3010, CMU_G3D),
|
|
SFR(QCH_CON_D_TZPC_G3D_QCH, 0x3014, CMU_G3D),
|
|
SFR(QCH_CON_G3D_CMU_G3D_QCH, 0x3018, CMU_G3D),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_G3D_QCH, 0x301c, CMU_G3D),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_INT_G3D_QCH, 0x3020, CMU_G3D),
|
|
SFR(QCH_CON_SYSREG_G3D_QCH, 0x3024, CMU_G3D),
|
|
SFR(QCH_CON_ADD_APBIF_G3D_QCH, 0x3028, CMU_G3DCORE),
|
|
SFR(DMYQCH_CON_ADD_G3D_QCH, 0x3000, CMU_G3DCORE),
|
|
SFR(DMYQCH_CON_ADM_DAP_G_G3D_QCH, 0x3004, CMU_G3DCORE),
|
|
SFR(QCH_CON_ASB_G3D_QCH_LH_D0_G3D, 0x302c, CMU_G3DCORE),
|
|
SFR(QCH_CON_ASB_G3D_QCH_LH_D1_G3D, 0x3030, CMU_G3DCORE),
|
|
SFR(QCH_CON_ASB_G3D_QCH_LH_D2_G3D, 0x3034, CMU_G3DCORE),
|
|
SFR(QCH_CON_ASB_G3D_QCH_LH_D3_G3D, 0x3038, CMU_G3DCORE),
|
|
SFR(QCH_CON_ASB_G3D_QCH_S_LH_P_G3D, 0x303c, CMU_G3DCORE),
|
|
SFR(QCH_CON_BUSIF_DDC_G3D_QCH, 0x3040, CMU_G3DCORE),
|
|
SFR(QCH_CON_G3DCORE_CMU_G3DCORE_QCH, 0x304c, CMU_G3DCORE),
|
|
SFR(DMYQCH_CON_GPU_QCH_CLK, 0x3008, CMU_G3DCORE),
|
|
SFR(DMYQCH_CON_GPU_QCH_PCLK, 0x300c, CMU_G3DCORE),
|
|
SFR(QCH_CON_HTU_G3D_QCH_PCLK, 0x3054, CMU_G3DCORE),
|
|
SFR(QCH_CON_HTU_G3D_QCH_CLK, 0x3050, CMU_G3DCORE),
|
|
SFR(QCH_CON_LH_ATB_SI_T_DDCG3D_QCH, 0x3058, CMU_G3DCORE),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_QCH, 0x3044, CMU_G3DCORE),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_G3DCORE_NOCP_QCH, 0x3048, CMU_G3DCORE),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_G3D_POWERIP_QCH, 0x3060, CMU_G3DCORE),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_QCH, 0x3064, CMU_G3DCORE),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_NOCP_QCH, 0x3068, CMU_G3DCORE),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_G3D_POWERIP_QCH, 0x306c, CMU_G3DCORE),
|
|
SFR(QCH_CON_STR_MUX_G3D_QCH_PCLK, 0x3074, CMU_G3DCORE),
|
|
SFR(QCH_CON_STR_MUX_G3D_QCH_CORE, 0x3070, CMU_G3DCORE),
|
|
SFR(QCH_CON_U_DDD_CTRL_CORE__G3D_QCH, 0x305c, CMU_G3DCORE),
|
|
SFR(QCH_CON_D_TZPC_GNPU_QCH, 0x30d0, CMU_GNPU),
|
|
SFR(QCH_CON_GNPU_CMU_GNPU_QCH, 0x30d4, CMU_GNPU),
|
|
SFR(QCH_CON_IP_NPUCORE_QCH_CORE, 0x30d8, CMU_GNPU),
|
|
SFR(QCH_CON_IP_NPUCORE_QCH_SRAM, 0x30dc, CMU_GNPU),
|
|
SFR(QCH_CON_LH_AXI_MI_LD0_GNPU_QCH, 0x318c, CMU_GNPU),
|
|
SFR(QCH_CON_LH_AXI_MI_LD1_GNPU_QCH, 0x3190, CMU_GNPU),
|
|
SFR(QCH_CON_LH_AXI_MI_LD_CTRL_GNPU_QCH, 0x3194, CMU_GNPU),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH, 0x319c, CMU_GNPU),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_RQ_GNPU_QCH, 0x3198, CMU_GNPU),
|
|
SFR(QCH_CON_SLH_AXI_MI_LP_GNPU_QCH, 0x31a0, CMU_GNPU),
|
|
SFR(QCH_CON_SLH_AXI_SI_LD_CMDQ_GNPU_QCH, 0x31a4, CMU_GNPU),
|
|
SFR(QCH_CON_SYSREG_GNPU_QCH, 0x31a8, CMU_GNPU),
|
|
SFR(QCH_CON_GNSS_CMU_GNSS_QCH, 0x3000, CMU_GNSS),
|
|
SFR(QCH_CON_DP_LINK_QCH_OSC_CLK, 0x3024, CMU_HSI0),
|
|
SFR(QCH_CON_DP_LINK_QCH_PCLK, 0x3028, CMU_HSI0),
|
|
SFR(QCH_CON_DP_LINK_QCH_GTC_CLK, 0x3020, CMU_HSI0),
|
|
SFR(QCH_CON_D_TZPC_HSI0_QCH, 0x302c, CMU_HSI0),
|
|
SFR(QCH_CON_HSI0_CMU_HSI0_QCH, 0x3030, CMU_HSI0),
|
|
SFR(QCH_CON_PPMU_HSI0_BUS1_QCH, 0x3034, CMU_HSI0),
|
|
SFR(QCH_CON_SLH_ACEL_SI_D_HSI0_QCH, 0x3038, CMU_HSI0),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_HSI0_QCH, 0x303c, CMU_HSI0),
|
|
SFR(QCH_CON_SLH_AXI_MI_LD_AUDHSI0_QCH, 0x3040, CMU_HSI0),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_HSI0_QCH, 0x3044, CMU_HSI0),
|
|
SFR(QCH_CON_SLH_AXI_SI_LD_HSI0AUD_QCH, 0x3048, CMU_HSI0),
|
|
SFR(QCH_CON_SPC_HSI0_QCH, 0x304c, CMU_HSI0),
|
|
SFR(QCH_CON_SYSMMU_D_HSI0_QCH, 0x3050, CMU_HSI0),
|
|
SFR(QCH_CON_SYSREG_HSI0_QCH, 0x3054, CMU_HSI0),
|
|
SFR(QCH_CON_USB32DRD_QCH_S_SUBCTRL, 0x3068, CMU_HSI0),
|
|
SFR(QCH_CON_USB32DRD_QCH_S_LINK, 0x3064, CMU_HSI0),
|
|
SFR(QCH_CON_USB32DRD_QCH_S_CTRL, 0x3058, CMU_HSI0),
|
|
SFR(QCH_CON_USB32DRD_QCH_S_TCA, 0x306c, CMU_HSI0),
|
|
SFR(QCH_CON_USB32DRD_QCH_S_EUSBCTL, 0x305c, CMU_HSI0),
|
|
SFR(QCH_CON_USB32DRD_QCH_S_EUSBPHY, 0x3060, CMU_HSI0),
|
|
SFR(QCH_CON_VGEN_LITE_HSI0_QCH, 0x3070, CMU_HSI0),
|
|
SFR(QCH_CON_D_TZPC_HSI1_QCH, 0x3028, CMU_HSI1),
|
|
SFR(QCH_CON_GPIO_HSI1_QCH, 0x3030, CMU_HSI1),
|
|
SFR(QCH_CON_HSI1_CMU_HSI1_QCH, 0x3034, CMU_HSI1),
|
|
SFR(QCH_CON_LH_ACEL_SI_D_HSI1_QCH, 0x3038, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN2_QCH_AXI, 0x3044, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN2_QCH_PCS_APB, 0x304c, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN2_QCH_DBI, 0x3048, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN2_QCH_APB, 0x3040, CMU_HSI1),
|
|
SFR(DMYQCH_CON_PCIE_GEN2_QCH_REF, 0x3000, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN2_QCH_PMA_APB, 0x3050, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN2_QCH_UDBG_APB, 0x3054, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN3_QCH_APB, 0x3058, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN3_QCH_DBI, 0x3060, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN3_QCH_AXI, 0x305c, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN3_QCH_PCS_APB, 0x3064, CMU_HSI1),
|
|
SFR(DMYQCH_CON_PCIE_GEN3_QCH_REF, 0x3004, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN3_QCH_UDBG_APB, 0x306c, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_GEN3_QCH_PMA_APB, 0x3068, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_IA_GEN2_QCH, 0x3070, CMU_HSI1),
|
|
SFR(QCH_CON_PCIE_IA_GEN3_QCH, 0x3074, CMU_HSI1),
|
|
SFR(QCH_CON_PPMU_HSI1_QCH, 0x3078, CMU_HSI1),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_HSI1_QCH, 0x307c, CMU_HSI1),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_HSI1_QCH, 0x3080, CMU_HSI1),
|
|
SFR(QCH_CON_SYSMMU_HSI1_QCH_S1, 0x3088, CMU_HSI1),
|
|
SFR(QCH_CON_SYSMMU_HSI1_QCH_S2, 0x308c, CMU_HSI1),
|
|
SFR(QCH_CON_SYSREG_HSI1_QCH, 0x3090, CMU_HSI1),
|
|
SFR(QCH_CON_VGEN_LITE_HSI1_QCH, 0x309c, CMU_HSI1),
|
|
SFR(QCH_CON_D_TZPC_LME_QCH, 0x301c, CMU_LME),
|
|
SFR(QCH_CON_GDC_QCH, 0x3058, CMU_LME),
|
|
SFR(QCH_CON_GDC_QCH_C2_M, 0x305c, CMU_LME),
|
|
SFR(QCH_CON_GDC_QCH_C2_S, 0x3060, CMU_LME),
|
|
SFR(QCH_CON_LH_ACEL_SI_D_LME_QCH, 0x3024, CMU_LME),
|
|
SFR(QCH_CON_LH_AXI_MI_ID_LME_QCH, 0x3064, CMU_LME),
|
|
SFR(QCH_CON_LH_AXI_SI_ID_LME_QCH, 0x3068, CMU_LME),
|
|
SFR(QCH_CON_LME_QCH_0, 0x302c, CMU_LME),
|
|
SFR(QCH_CON_LME_CMU_LME_QCH, 0x3028, CMU_LME),
|
|
SFR(QCH_CON_PPMU_D_LME_QCH, 0x3034, CMU_LME),
|
|
SFR(QCH_CON_QE_D1_LME_QCH, 0x303c, CMU_LME),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_LME_QCH, 0x3040, CMU_LME),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_LME_QCH, 0x3044, CMU_LME),
|
|
SFR(QCH_CON_SYSMMU_D_LME_QCH_S1, 0x3048, CMU_LME),
|
|
SFR(QCH_CON_SYSMMU_D_LME_QCH_S2, 0x304c, CMU_LME),
|
|
SFR(QCH_CON_SYSREG_LME_QCH, 0x3050, CMU_LME),
|
|
SFR(QCH_CON_VGEN_LITE_D_GDC_QCH, 0x306c, CMU_LME),
|
|
SFR(QCH_CON_VGEN_LITE_D_LME_QCH, 0x3054, CMU_LME),
|
|
SFR(QCH_CON_D_TZPC_M2M_QCH, 0x302c, CMU_M2M),
|
|
SFR(QCH_CON_FRC_MC_QCH, 0x307c, CMU_M2M),
|
|
SFR(QCH_CON_JPEG0_QCH, 0x3030, CMU_M2M),
|
|
SFR(QCH_CON_JPEG1_QCH, 0x3034, CMU_M2M),
|
|
SFR(QCH_CON_JSQZ_QCH, 0x3038, CMU_M2M),
|
|
SFR(QCH_CON_LH_ACEL_SI_D_M2M_QCH, 0x303c, CMU_M2M),
|
|
SFR(QCH_CON_LH_AXI_MI_FRC_MC_QCH, 0x3080, CMU_M2M),
|
|
SFR(QCH_CON_LH_AXI_SI_FRC_MC_QCH, 0x3084, CMU_M2M),
|
|
SFR(QCH_CON_M2M_QCH, 0x3044, CMU_M2M),
|
|
SFR(QCH_CON_M2M_QCH_VOTF, 0x3048, CMU_M2M),
|
|
SFR(QCH_CON_M2M_CMU_M2M_QCH, 0x3040, CMU_M2M),
|
|
SFR(QCH_CON_PPMU_D_M2M_QCH, 0x304c, CMU_M2M),
|
|
SFR(QCH_CON_QE_FRC_MC_QCH, 0x3088, CMU_M2M),
|
|
SFR(QCH_CON_QE_JPEG0_QCH, 0x3054, CMU_M2M),
|
|
SFR(QCH_CON_QE_JPEG1_QCH, 0x3058, CMU_M2M),
|
|
SFR(QCH_CON_QE_JSQZ_QCH, 0x305c, CMU_M2M),
|
|
SFR(QCH_CON_QE_M2M_QCH, 0x3060, CMU_M2M),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_M2M_QCH, 0x3064, CMU_M2M),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_M2M_QCH, 0x3068, CMU_M2M),
|
|
SFR(QCH_CON_SYSMMU_D_M2M_PM_QCH_S2, 0x3070, CMU_M2M),
|
|
SFR(QCH_CON_SYSMMU_D_M2M_PM_QCH_S1, 0x306c, CMU_M2M),
|
|
SFR(QCH_CON_SYSREG_M2M_QCH, 0x3074, CMU_M2M),
|
|
SFR(QCH_CON_VGEN_LITE_M2M_QCH, 0x3078, CMU_M2M),
|
|
SFR(QCH_CON_D_TZPC_MCSC_QCH, 0x3040, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AST_MI_OTF0_YUVPMCSC_QCH, 0x30bc, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AST_MI_OTF1_YUVPMCSC_QCH, 0x30c0, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AST_MI_OTF_BRPMCSC_QCH, 0x30c4, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AST_SI_OTF_MCSCYUVP_QCH, 0x30c8, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_MI_ID_MCSC0_QCH, 0x30cc, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_MI_ID_MCSC1_QCH, 0x30d0, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_MI_ID_MCSC2_QCH, 0x30d4, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_MI_ID_MCSC3_QCH, 0x30d8, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_MI_ID_MCSC4_QCH, 0x30dc, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_MI_ID_MCSC5_QCH, 0x30e0, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_MI_ID_MCSC6_QCH, 0x30e4, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_SI_D1_MCSC_QCH, 0x3058, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_SI_D2_MCSC_QCH, 0x305c, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_SI_D3_MCSC_QCH, 0x30e8, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_SI_D4_MCSC_QCH, 0x30ec, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_SI_ID_MCSC0_QCH, 0x30f0, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_SI_ID_MCSC1_QCH, 0x30f4, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_SI_ID_MCSC2_QCH, 0x30f8, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_SI_ID_MCSC3_QCH, 0x30fc, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_SI_ID_MCSC4_QCH, 0x3100, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_SI_ID_MCSC5_QCH, 0x3104, CMU_MCSC),
|
|
SFR(QCH_CON_LH_AXI_SI_ID_MCSC6_QCH, 0x3108, CMU_MCSC),
|
|
SFR(QCH_CON_MCFP_QCH, 0x310c, CMU_MCSC),
|
|
SFR(QCH_CON_MCSC_QCH, 0x3064, CMU_MCSC),
|
|
SFR(QCH_CON_MCSC_QCH_C2R, 0x3068, CMU_MCSC),
|
|
SFR(QCH_CON_MCSC_QCH_C2W, 0x306c, CMU_MCSC),
|
|
SFR(QCH_CON_MCSC_CMU_MCSC_QCH, 0x3060, CMU_MCSC),
|
|
SFR(QCH_CON_PPMU_D0_MCSC_QCH, 0x3070, CMU_MCSC),
|
|
SFR(QCH_CON_PPMU_D1_MCSC_QCH, 0x3074, CMU_MCSC),
|
|
SFR(QCH_CON_PPMU_D2_MCSC_QCH, 0x3078, CMU_MCSC),
|
|
SFR(QCH_CON_PPMU_D3_MCSC_QCH, 0x3110, CMU_MCSC),
|
|
SFR(QCH_CON_PPMU_D4_MCSC_QCH, 0x3114, CMU_MCSC),
|
|
SFR(QCH_CON_SIU_G_PPMU_MCSC_QCH, 0x307c, CMU_MCSC),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_MCSC_QCH, 0x3084, CMU_MCSC),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_MCSC_QCH, 0x308c, CMU_MCSC),
|
|
SFR(QCH_CON_SLH_AXI_SI_D0_MCSC_QCH, 0x3118, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D0_MCSC_QCH_S1, 0x3090, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D0_MCSC_QCH_S2, 0x3094, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D1_MCSC_QCH_S1, 0x3098, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D1_MCSC_QCH_S2, 0x309c, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D2_MCSC_QCH_S1, 0x30a0, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D2_MCSC_QCH_S2, 0x30a4, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D3_MCSC_QCH_S1, 0x311c, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D3_MCSC_QCH_S2, 0x3120, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D4_MCSC_QCH_S1, 0x3124, CMU_MCSC),
|
|
SFR(QCH_CON_SYSMMU_D4_MCSC_QCH_S2, 0x3128, CMU_MCSC),
|
|
SFR(QCH_CON_SYSREG_MCSC_QCH, 0x30a8, CMU_MCSC),
|
|
SFR(QCH_CON_VGEN_LITE_D0_MCSC_QCH, 0x30ac, CMU_MCSC),
|
|
SFR(QCH_CON_VGEN_LITE_D1_MCSC_QCH, 0x30b0, CMU_MCSC),
|
|
SFR(QCH_CON_VGEN_LITE_D2_MCSC_QCH, 0x312c, CMU_MCSC),
|
|
SFR(QCH_CON_D_TZPC_MFC0_QCH, 0x304c, CMU_MFC0),
|
|
SFR(QCH_CON_LH_AST_MI_OTF0_MFC1MFC0_QCH, 0x3050, CMU_MFC0),
|
|
SFR(QCH_CON_LH_AST_MI_OTF1_MFC1MFC0_QCH, 0x3054, CMU_MFC0),
|
|
SFR(QCH_CON_LH_AST_MI_OTF2_MFC1MFC0_QCH, 0x3058, CMU_MFC0),
|
|
SFR(QCH_CON_LH_AST_MI_OTF3_MFC1MFC0_QCH, 0x305c, CMU_MFC0),
|
|
SFR(QCH_CON_LH_AST_SI_OTF0_MFC0MFC1_QCH, 0x3060, CMU_MFC0),
|
|
SFR(QCH_CON_LH_AST_SI_OTF1_MFC0MFC1_QCH, 0x3064, CMU_MFC0),
|
|
SFR(QCH_CON_LH_AST_SI_OTF2_MFC0MFC1_QCH, 0x3068, CMU_MFC0),
|
|
SFR(QCH_CON_LH_AST_SI_OTF3_MFC0MFC1_QCH, 0x306c, CMU_MFC0),
|
|
SFR(QCH_CON_LH_ATB_MFC0_QCH_MI, 0x3070, CMU_MFC0),
|
|
SFR(QCH_CON_LH_ATB_MFC0_QCH_SI, 0x3074, CMU_MFC0),
|
|
SFR(QCH_CON_LH_AXI_MI_ID_MFC0_QCH, 0x30f4, CMU_MFC0),
|
|
SFR(QCH_CON_LH_AXI_SI_D0_MFC0_QCH, 0x3078, CMU_MFC0),
|
|
SFR(QCH_CON_LH_AXI_SI_D1_MFC0_QCH, 0x307c, CMU_MFC0),
|
|
SFR(QCH_CON_LH_AXI_SI_ID_MFC0_QCH, 0x30f8, CMU_MFC0),
|
|
SFR(QCH_CON_MFC0_QCH, 0x3084, CMU_MFC0),
|
|
SFR(QCH_CON_MFC0_QCH_VOTF, 0x3088, CMU_MFC0),
|
|
SFR(QCH_CON_MFC0_CMU_MFC0_QCH, 0x3080, CMU_MFC0),
|
|
SFR(QCH_CON_PPMU_MFC0D0_QCH, 0x308c, CMU_MFC0),
|
|
SFR(QCH_CON_PPMU_MFC0D1_QCH, 0x3090, CMU_MFC0),
|
|
SFR(QCH_CON_PPMU_WFD_QCH, 0x3094, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH, 0x30c0, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH, 0x30c4, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH, 0x3098, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH, 0x309c, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH, 0x30a0, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH, 0x30a4, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH, 0x30a8, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH, 0x30ac, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH, 0x30b0, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH, 0x30b4, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH, 0x30b8, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH, 0x30bc, CMU_MFC0),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH, 0x3100, CMU_MFC0),
|
|
SFR(QCH_CON_SIU_G_PPMU_MFC0_QCH, 0x30c8, CMU_MFC0),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_MFC0_QCH, 0x30cc, CMU_MFC0),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_MFC0_QCH, 0x30d0, CMU_MFC0),
|
|
SFR(QCH_CON_SYSMMU_MFC0D0_QCH_S1, 0x30d4, CMU_MFC0),
|
|
SFR(QCH_CON_SYSMMU_MFC0D0_QCH_S2, 0x30d8, CMU_MFC0),
|
|
SFR(QCH_CON_SYSMMU_MFC0D1_QCH_S1, 0x30dc, CMU_MFC0),
|
|
SFR(QCH_CON_SYSMMU_MFC0D1_QCH_S2, 0x30e0, CMU_MFC0),
|
|
SFR(QCH_CON_SYSREG_MFC0_QCH, 0x30e4, CMU_MFC0),
|
|
SFR(QCH_CON_VGEN_LITE_MFC0_QCH, 0x30e8, CMU_MFC0),
|
|
SFR(QCH_CON_WFD_QCH, 0x30f0, CMU_MFC0),
|
|
SFR(DMYQCH_CON_ADM_APB_MFC0MFC1_QCH, 0x3000, CMU_MFC1),
|
|
SFR(QCH_CON_D_TZPC_MFC1_QCH, 0x3048, CMU_MFC1),
|
|
SFR(QCH_CON_LH_AST_MI_OTF0_MFC0MFC1_QCH, 0x304c, CMU_MFC1),
|
|
SFR(QCH_CON_LH_AST_MI_OTF1_MFC0MFC1_QCH, 0x3050, CMU_MFC1),
|
|
SFR(QCH_CON_LH_AST_MI_OTF2_MFC0MFC1_QCH, 0x3054, CMU_MFC1),
|
|
SFR(QCH_CON_LH_AST_MI_OTF3_MFC0MFC1_QCH, 0x3058, CMU_MFC1),
|
|
SFR(QCH_CON_LH_AST_SI_OTF0_MFC1MFC0_QCH, 0x305c, CMU_MFC1),
|
|
SFR(QCH_CON_LH_AST_SI_OTF1_MFC1MFC0_QCH, 0x3060, CMU_MFC1),
|
|
SFR(QCH_CON_LH_AST_SI_OTF2_MFC1MFC0_QCH, 0x3064, CMU_MFC1),
|
|
SFR(QCH_CON_LH_AST_SI_OTF3_MFC1MFC0_QCH, 0x3068, CMU_MFC1),
|
|
SFR(QCH_CON_LH_AXI_SI_D0_MFC1_QCH, 0x306c, CMU_MFC1),
|
|
SFR(QCH_CON_LH_AXI_SI_D1_MFC1_QCH, 0x3070, CMU_MFC1),
|
|
SFR(QCH_CON_MFC1_QCH, 0x3078, CMU_MFC1),
|
|
SFR(QCH_CON_MFC1_CMU_MFC1_QCH, 0x3074, CMU_MFC1),
|
|
SFR(QCH_CON_PPMU_MFC1D0_QCH, 0x307c, CMU_MFC1),
|
|
SFR(QCH_CON_PPMU_MFC1D1_QCH, 0x3080, CMU_MFC1),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH, 0x30a4, CMU_MFC1),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH, 0x3084, CMU_MFC1),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH, 0x3088, CMU_MFC1),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH, 0x308c, CMU_MFC1),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH, 0x3090, CMU_MFC1),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH, 0x3094, CMU_MFC1),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH, 0x3098, CMU_MFC1),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH, 0x309c, CMU_MFC1),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH, 0x30a0, CMU_MFC1),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH, 0x30cc, CMU_MFC1),
|
|
SFR(QCH_CON_SIU_G_PPMU_MFC1_QCH, 0x30a8, CMU_MFC1),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_MFC1_QCH, 0x30ac, CMU_MFC1),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_MFC1_QCH, 0x30b0, CMU_MFC1),
|
|
SFR(QCH_CON_SYSMMU_MFC1D0_QCH_S1, 0x30b4, CMU_MFC1),
|
|
SFR(QCH_CON_SYSMMU_MFC1D0_QCH_S2, 0x30b8, CMU_MFC1),
|
|
SFR(QCH_CON_SYSMMU_MFC1D1_QCH_S1, 0x30bc, CMU_MFC1),
|
|
SFR(QCH_CON_SYSMMU_MFC1D1_QCH_S2, 0x30c0, CMU_MFC1),
|
|
SFR(QCH_CON_SYSREG_MFC1_QCH, 0x30c4, CMU_MFC1),
|
|
SFR(QCH_CON_VGEN_MFC1_QCH, 0x30c8, CMU_MFC1),
|
|
SFR(QCH_CON_BUSIF_DDD_MIF_QCH, 0x3018, CMU_MIF),
|
|
SFR(DMYQCH_CON_CMU_MIF_CMUREF_QCH, 0x3000, CMU_MIF),
|
|
SFR(QCH_CON_DMC_QCH, 0x301c, CMU_MIF),
|
|
SFR(QCH_CON_D_TZPC_MIF_QCH, 0x3020, CMU_MIF),
|
|
SFR(QCH_CON_MIF_CMU_MIF_QCH, 0x3028, CMU_MIF),
|
|
SFR(QCH_CON_QCH_ADAPTER_DDRPHY_QCH, 0x3010, CMU_MIF),
|
|
SFR(QCH_CON_QCH_ADAPTER_DMC_QCH, 0x3014, CMU_MIF),
|
|
SFR(QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH, 0x302c, CMU_MIF),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_MIF_QCH, 0x3030, CMU_MIF),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_MIF_QCH, 0x3034, CMU_MIF),
|
|
SFR(QCH_CON_SPC_MIF_QCH, 0x3038, CMU_MIF),
|
|
SFR(QCH_CON_SYSREG_MIF_QCH, 0x303c, CMU_MIF),
|
|
SFR(QCH_CON_SYSREG_PRIVATE_MIF_QCH, 0x3040, CMU_MIF),
|
|
SFR(QCH_CON_BAAW_CP_QCH, 0x30f4, CMU_NOCL0),
|
|
SFR(QCH_CON_BAAW_P_GNSS_QCH, 0x3294, CMU_NOCL0),
|
|
SFR(QCH_CON_BDU_QCH, 0x30f8, CMU_NOCL0),
|
|
SFR(QCH_CON_CACHEAID_NOCL0_QCH, 0x30fc, CMU_NOCL0),
|
|
SFR(DMYQCH_CON_CCI_QCH, 0x3000, CMU_NOCL0),
|
|
SFR(QCH_CON_CCI_QCH_S, 0x3100, CMU_NOCL0),
|
|
SFR(DMYQCH_CON_CMU_NOCL0_CMUREF_QCH, 0x3004, CMU_NOCL0),
|
|
SFR(QCH_CON_D_TZPC_NOCL0_QCH, 0x3104, CMU_NOCL0),
|
|
SFR(QCH_CON_LH_ACEL_MI_D0_G3D_QCH, 0x3108, CMU_NOCL0),
|
|
SFR(QCH_CON_LH_ACEL_MI_D1_G3D_QCH, 0x310c, CMU_NOCL0),
|
|
SFR(QCH_CON_LH_ACEL_MI_D2_G3D_QCH, 0x3110, CMU_NOCL0),
|
|
SFR(QCH_CON_LH_ACEL_MI_D3_G3D_QCH, 0x3114, CMU_NOCL0),
|
|
SFR(QCH_CON_LH_ACEL_SI_D0_ACP_QCH, 0x3298, CMU_NOCL0),
|
|
SFR(QCH_CON_LH_ACEL_SI_D1_ACP_QCH, 0x329c, CMU_NOCL0),
|
|
SFR(QCH_CON_LH_AST_MI_G_NOCL1A_QCH, 0x3128, CMU_NOCL0),
|
|
SFR(QCH_CON_LH_AST_MI_G_NOCL1B_QCH, 0x312c, CMU_NOCL0),
|
|
SFR(QCH_CON_LH_AST_MI_G_NOCL1C_QCH, 0x3130, CMU_NOCL0),
|
|
SFR(QCH_CON_LH_ATB_SI_T_BDU_QCH, 0x3134, CMU_NOCL0),
|
|
SFR(QCH_CON_LH_AXI_MI_D_APM_QCH, 0x3138, CMU_NOCL0),
|
|
SFR(QCH_CON_LH_AXI_MI_G_CSSYS_QCH, 0x313c, CMU_NOCL0),
|
|
SFR(QCH_CON_LH_AXI_MI_IG_CSSYS_NOCL0_QCH, 0x3120, CMU_NOCL0),
|
|
SFR(QCH_CON_LH_AXI_SI_IG_CSSYS_NOCL0_QCH, 0x32a0, CMU_NOCL0),
|
|
SFR(QCH_CON_LH_CHI_MI_D0_CLUSTER0_QCH, 0x3140, CMU_NOCL0),
|
|
SFR(QCH_CON_LH_CHI_MI_D1_CLUSTER0_QCH, 0x3144, CMU_NOCL0),
|
|
SFR(QCH_CON_LH_QDI_MI_D_AUD_QCH, 0x3148, CMU_NOCL0),
|
|
SFR(QCH_CON_NOCIF_CMUTOPC_QCH, 0x32a4, CMU_NOCL0),
|
|
SFR(QCH_CON_NOCL0_CMU_NOCL0_QCH, 0x314c, CMU_NOCL0),
|
|
SFR(QCH_CON_PBHA_GEN_D0_MODEM_QCH, 0x3150, CMU_NOCL0),
|
|
SFR(QCH_CON_PBHA_GEN_D1_MODEM_QCH, 0x3154, CMU_NOCL0),
|
|
SFR(QCH_CON_PPC_SCI_QCH, 0x3158, CMU_NOCL0),
|
|
SFR(QCH_CON_PPMU_APM_QCH, 0x315c, CMU_NOCL0),
|
|
SFR(QCH_CON_PPMU_CPUCL0_0_QCH, 0x3160, CMU_NOCL0),
|
|
SFR(QCH_CON_PPMU_CPUCL0_1_QCH, 0x3164, CMU_NOCL0),
|
|
SFR(QCH_CON_PPMU_G3D0_QCH, 0x3168, CMU_NOCL0),
|
|
SFR(QCH_CON_PPMU_G3D1_QCH, 0x316c, CMU_NOCL0),
|
|
SFR(QCH_CON_PPMU_G3D2_QCH, 0x3170, CMU_NOCL0),
|
|
SFR(QCH_CON_PPMU_G3D3_QCH, 0x3174, CMU_NOCL0),
|
|
SFR(DMYQCH_CON_PPMU_SYNC_GEN_QCH, 0x3008, CMU_NOCL0),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_NOCL0_NOCD_CCI_QCH, 0x32a8, CMU_NOCL0),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_NOCL0_NOCP_CCI_QCH, 0x32ac, CMU_NOCL0),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_QCH, 0x32b0, CMU_NOCL0),
|
|
SFR(QCH_CON_SIU_G0_PPMU_NOCL0_QCH, 0x3178, CMU_NOCL0),
|
|
SFR(QCH_CON_SIU_G1_PPMU_NOCL0_QCH, 0x317c, CMU_NOCL0),
|
|
SFR(QCH_CON_SIU_G2_PPMU_NOCL0_QCH, 0x3180, CMU_NOCL0),
|
|
SFR(QCH_CON_SIU_G3_PPMU_NOCL0_QCH, 0x3184, CMU_NOCL0),
|
|
SFR(QCH_CON_SIU_G4_PPMU_NOCL0_QCH, 0x3188, CMU_NOCL0),
|
|
SFR(QCH_CON_SIU_G5_PPMU_NOCL0_QCH, 0x318c, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_ACEL_MI_D_SSP_QCH, 0x32b4, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_AUD_QCH, 0x3194, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_GNSS_QCH, 0x32b8, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_MIF0_QCH, 0x3198, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_MIF1_QCH, 0x319c, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_MIF2_QCH, 0x31a0, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_MIF3_QCH, 0x31a4, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_MODEM_QCH, 0x31a8, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_NOCL1A_QCH, 0x31ac, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_NOCL1B_QCH, 0x31b0, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_NOCL1C_QCH, 0x32bc, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_SSP_QCH, 0x311c, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_UFD_QCH, 0x3118, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_QCH, 0x31bc, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AST_MI_IG_PPMU_P_CLUSTER0_QCH, 0x31b4, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_QCH, 0x31c0, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AST_SI_IG_PPMU_P_CLUSTER0_QCH, 0x31b8, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_MI_D0_MODEM_QCH, 0x31c4, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_MI_D1_MODEM_QCH, 0x31c8, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_MI_D2_MODEM_QCH, 0x31cc, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_MI_D_UFD_QCH, 0x32c0, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_CLUSTER0_NOCL0_QCH, 0x31d0, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_APM_QCH, 0x31d4, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_AUD_QCH, 0x31d8, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH, 0x31dc, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_G3D_QCH, 0x31e0, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_GNSS_QCH, 0x32c4, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_MCW_QCH, 0x31e4, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_MIF0_QCH, 0x31e8, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_MIF1_QCH, 0x31ec, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_MIF2_QCH, 0x31f0, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_MIF3_QCH, 0x31f4, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_MODEM_QCH, 0x31f8, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_PERIC1_QCH, 0x32c8, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_PERIS_QCH, 0x32cc, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_PERISGIC_QCH, 0x31fc, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_SSP_QCH, 0x3124, CMU_NOCL0),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_UFD_QCH, 0x32d0, CMU_NOCL0),
|
|
SFR(QCH_CON_SYSMMU_MODEM_QCH_S1, 0x3204, CMU_NOCL0),
|
|
SFR(QCH_CON_SYSMMU_MODEM_QCH_S2, 0x3208, CMU_NOCL0),
|
|
SFR(QCH_CON_SYSMMU_S2_APM_QCH, 0x320c, CMU_NOCL0),
|
|
SFR(QCH_CON_SYSMMU_S2_G3D_QCH_S0, 0x3210, CMU_NOCL0),
|
|
SFR(QCH_CON_SYSMMU_S2_G3D_QCH_S1, 0x3214, CMU_NOCL0),
|
|
SFR(QCH_CON_SYSMMU_S2_G3D_QCH_S2, 0x3218, CMU_NOCL0),
|
|
SFR(QCH_CON_SYSMMU_S2_G3D_QCH_S3, 0x321c, CMU_NOCL0),
|
|
SFR(QCH_CON_SYSMMU_S2_G3D_QCH_S4, 0x3220, CMU_NOCL0),
|
|
SFR(QCH_CON_SYSREG_NOCL0_QCH, 0x3224, CMU_NOCL0),
|
|
SFR(QCH_CON_TREX_D0_ACP_QCH, 0x32d4, CMU_NOCL0),
|
|
SFR(QCH_CON_TREX_D1_ACP_QCH, 0x32d8, CMU_NOCL0),
|
|
SFR(QCH_CON_TREX_D_NOCL0_QCH, 0x322c, CMU_NOCL0),
|
|
SFR(QCH_CON_TREX_P_NOCL0_QCH, 0x3230, CMU_NOCL0),
|
|
SFR(QCH_CON_VGEN_D0_G3D_QCH, 0x3234, CMU_NOCL0),
|
|
SFR(QCH_CON_VGEN_D1_G3D_QCH, 0x3238, CMU_NOCL0),
|
|
SFR(QCH_CON_VGEN_D2_G3D_QCH, 0x323c, CMU_NOCL0),
|
|
SFR(QCH_CON_VGEN_D3_G3D_QCH, 0x3240, CMU_NOCL0),
|
|
SFR(QCH_CON_VGEN_LITE_MODEM_QCH, 0x3244, CMU_NOCL0),
|
|
SFR(QCH_CON_WOW_DVFS_D0_CPUCL0_QCH, 0x3248, CMU_NOCL0),
|
|
SFR(QCH_CON_WOW_DVFS_D0_G3D_QCH, 0x324c, CMU_NOCL0),
|
|
SFR(QCH_CON_WOW_DVFS_D0_MIF_QCH, 0x3250, CMU_NOCL0),
|
|
SFR(QCH_CON_WOW_DVFS_D1_CPUCL0_QCH, 0x3254, CMU_NOCL0),
|
|
SFR(QCH_CON_WOW_DVFS_D1_MIF_QCH, 0x3258, CMU_NOCL0),
|
|
SFR(QCH_CON_WOW_DVFS_D2_MIF_QCH, 0x325c, CMU_NOCL0),
|
|
SFR(QCH_CON_WOW_DVFS_D3_MIF_QCH, 0x3260, CMU_NOCL0),
|
|
SFR(QCH_CON_WOW_DVFS_IRPS0_QCH, 0x3264, CMU_NOCL0),
|
|
SFR(QCH_CON_WOW_DVFS_IRPS1_QCH, 0x3268, CMU_NOCL0),
|
|
SFR(QCH_CON_WOW_DVFS_IRPS2_QCH, 0x326c, CMU_NOCL0),
|
|
SFR(QCH_CON_WOW_DVFS_IRPS3_QCH, 0x3270, CMU_NOCL0),
|
|
SFR(QCH_CON_WOW_DVFS_NOCL0_QCH, 0x3274, CMU_NOCL0),
|
|
SFR(QCH_CON_BAAW_P_DNC_QCH, 0x30c8, CMU_NOCL1A),
|
|
SFR(DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH, 0x3000, CMU_NOCL1A),
|
|
SFR(QCH_CON_D_TZPC_NOCL1A_QCH, 0x3084, CMU_NOCL1A),
|
|
SFR(QCH_CON_LH_ACEL_MI_D_HSI1_QCH, 0x3088, CMU_NOCL1A),
|
|
SFR(QCH_CON_LH_ACEL_MI_D_LME_QCH, 0x30a4, CMU_NOCL1A),
|
|
SFR(QCH_CON_LH_ACEL_MI_D_M2M_QCH, 0x30d4, CMU_NOCL1A),
|
|
SFR(QCH_CON_LH_AST_SI_G_NOCL1A_QCH, 0x3090, CMU_NOCL1A),
|
|
SFR(QCH_CON_LH_AXI_MI_D0_MFC0_QCH, 0x3094, CMU_NOCL1A),
|
|
SFR(QCH_CON_LH_AXI_MI_D0_MFC1_QCH, 0x3098, CMU_NOCL1A),
|
|
SFR(QCH_CON_LH_AXI_MI_D1_DPUF_QCH, 0x30d8, CMU_NOCL1A),
|
|
SFR(QCH_CON_LH_AXI_MI_D1_MFC0_QCH, 0x309c, CMU_NOCL1A),
|
|
SFR(QCH_CON_LH_AXI_MI_D1_MFC1_QCH, 0x30a0, CMU_NOCL1A),
|
|
SFR(QCH_CON_NOCL1A_CMU_NOCL1A_QCH, 0x30ac, CMU_NOCL1A),
|
|
SFR(QCH_CON_SIU_2X1_P0_NOCL1A_QCH, 0x30b0, CMU_NOCL1A),
|
|
SFR(QCH_CON_SIU_4X1_P0_NOCL1A_QCH, 0x30b4, CMU_NOCL1A),
|
|
SFR(QCH_CON_SIU_8X1_P0_NOCL1A_QCH, 0x30b8, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_DNC_QCH, 0x30f8, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_DPUF_QCH, 0x310c, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_HSI1_QCH, 0x30c0, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_LME_QCH, 0x30c4, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_M2M_QCH, 0x311c, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_MFC0_QCH, 0x30cc, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_MFC1_QCH, 0x30d0, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_QCH, 0x30e8, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1A_QCH, 0x30dc, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_NOCL1A_QCH, 0x30e0, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_QCH, 0x30ec, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1A_QCH, 0x30e4, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AXI_MI_D0_DPUF_QCH, 0x3120, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_DNC_QCH, 0x3124, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_DPUB_QCH, 0x3128, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_DPUF_QCH, 0x312c, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_HSI1_QCH, 0x30f0, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_LME_QCH, 0x30f4, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_M2M_QCH, 0x3130, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_MFC0_QCH, 0x30fc, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_MFC1_QCH, 0x3100, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_PERIC0_QCH, 0x3104, CMU_NOCL1A),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_PERIC2_QCH, 0x3108, CMU_NOCL1A),
|
|
SFR(QCH_CON_SYSREG_NOCL1A_QCH, 0x3110, CMU_NOCL1A),
|
|
SFR(QCH_CON_TREX_D_NOCL1A_QCH, 0x3114, CMU_NOCL1A),
|
|
SFR(QCH_CON_TREX_P_NOCL1A_QCH, 0x3118, CMU_NOCL1A),
|
|
SFR(DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH, 0x3000, CMU_NOCL1B),
|
|
SFR(QCH_CON_DIT_QCH, 0x30bc, CMU_NOCL1B),
|
|
SFR(QCH_CON_D_TZPC_NOCL1B_QCH, 0x30c0, CMU_NOCL1B),
|
|
SFR(QCH_CON_LH_ACEL_MI_D_UFS_QCH, 0x3068, CMU_NOCL1B),
|
|
SFR(QCH_CON_LH_ACEL_MI_ID_DIT_QCH, 0x30c4, CMU_NOCL1B),
|
|
SFR(QCH_CON_LH_ACEL_SI_ID_DIT_QCH, 0x30c8, CMU_NOCL1B),
|
|
SFR(QCH_CON_LH_AST_SI_G_NOCL1B_QCH, 0x30cc, CMU_NOCL1B),
|
|
SFR(QCH_CON_LH_AXI_MI_ID_TT_QCH, 0x306c, CMU_NOCL1B),
|
|
SFR(QCH_CON_LH_AXI_SI_ID_TT_QCH, 0x3070, CMU_NOCL1B),
|
|
SFR(QCH_CON_NOCL1B_CMU_NOCL1B_QCH, 0x30d4, CMU_NOCL1B),
|
|
SFR(QCH_CON_PDMA_QCH, 0x30d8, CMU_NOCL1B),
|
|
SFR(QCH_CON_PPMU_DIT_QCH, 0x30dc, CMU_NOCL1B),
|
|
SFR(QCH_CON_PPMU_D_TT_QCH, 0x30e0, CMU_NOCL1B),
|
|
SFR(QCH_CON_QE_PDMA_QCH, 0x30e4, CMU_NOCL1B),
|
|
SFR(QCH_CON_QE_SPDMA_QCH, 0x30e8, CMU_NOCL1B),
|
|
SFR(QCH_CON_SIU_8X1_P0_NOCL1B_QCH, 0x307c, CMU_NOCL1B),
|
|
SFR(QCH_CON_SLH_ACEL_MI_D_HSI0_QCH, 0x30f4, CMU_NOCL1B),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_HSI0_QCH, 0x3108, CMU_NOCL1B),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_UFS_QCH, 0x3088, CMU_NOCL1B),
|
|
SFR(QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_QCH, 0x3128, CMU_NOCL1B),
|
|
SFR(QCH_CON_SLH_AST_MI_IG_PPMU_DIT_QCH, 0x310c, CMU_NOCL1B),
|
|
SFR(QCH_CON_SLH_AST_MI_IG_PPMU_TREXP_QCH, 0x3110, CMU_NOCL1B),
|
|
SFR(QCH_CON_SLH_AST_MI_IG_PPMU_XIU_D_TT_QCH, 0x3114, CMU_NOCL1B),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_NOCL1B_QCH, 0x3118, CMU_NOCL1B),
|
|
SFR(QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_QCH, 0x312c, CMU_NOCL1B),
|
|
SFR(QCH_CON_SLH_AST_SI_IG_PPMU_DIT_QCH, 0x311c, CMU_NOCL1B),
|
|
SFR(QCH_CON_SLH_AST_SI_IG_PPMU_TREXP_QCH, 0x3120, CMU_NOCL1B),
|
|
SFR(QCH_CON_SLH_AST_SI_IG_PPMU_XIU_D_TT_QCH, 0x3124, CMU_NOCL1B),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_HSI0_QCH, 0x3158, CMU_NOCL1B),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_UFS_QCH, 0x3168, CMU_NOCL1B),
|
|
SFR(QCH_CON_SPDMA_QCH, 0x3170, CMU_NOCL1B),
|
|
SFR(QCH_CON_SYSMMU_S2_DIT_QCH, 0x3174, CMU_NOCL1B),
|
|
SFR(QCH_CON_SYSMMU_S2_TT_QCH, 0x317c, CMU_NOCL1B),
|
|
SFR(QCH_CON_SYSREG_NOCL1B_QCH, 0x3180, CMU_NOCL1B),
|
|
SFR(QCH_CON_TREX_D_NOCL1B_QCH, 0x3184, CMU_NOCL1B),
|
|
SFR(QCH_CON_TREX_P_NOCL1B_QCH, 0x3188, CMU_NOCL1B),
|
|
SFR(QCH_CON_VGEN_LITE_NOCL1B_QCH, 0x3190, CMU_NOCL1B),
|
|
SFR(QCH_CON_VGEN_PDMA_QCH, 0x3194, CMU_NOCL1B),
|
|
SFR(QCH_CON_VGEN_SPDMA_QCH, 0x3198, CMU_NOCL1B),
|
|
SFR(DMYQCH_CON_CMU_NOCL1C_CMUREF_QCH, 0x3000, CMU_NOCL1C),
|
|
SFR(QCH_CON_D_TZPC_NOCL1C_QCH, 0x30b4, CMU_NOCL1C),
|
|
SFR(QCH_CON_LH_AST_SI_G_NOCL1C_QCH, 0x30bc, CMU_NOCL1C),
|
|
SFR(QCH_CON_LH_AXI_MI_D0_BRP_QCH, 0x3048, CMU_NOCL1C),
|
|
SFR(QCH_CON_LH_AXI_MI_D0_CSIS_QCH, 0x30c0, CMU_NOCL1C),
|
|
SFR(QCH_CON_LH_AXI_MI_D0_YUVP_QCH, 0x3054, CMU_NOCL1C),
|
|
SFR(QCH_CON_LH_AXI_MI_D1_BRP_QCH, 0x3058, CMU_NOCL1C),
|
|
SFR(QCH_CON_LH_AXI_MI_D1_CSIS_QCH, 0x30cc, CMU_NOCL1C),
|
|
SFR(QCH_CON_LH_AXI_MI_D1_MCSC_QCH, 0x30d4, CMU_NOCL1C),
|
|
SFR(QCH_CON_LH_AXI_MI_D2_BRP_QCH, 0x3060, CMU_NOCL1C),
|
|
SFR(QCH_CON_LH_AXI_MI_D2_CSIS_QCH, 0x30dc, CMU_NOCL1C),
|
|
SFR(QCH_CON_LH_AXI_MI_D2_MCSC_QCH, 0x30e4, CMU_NOCL1C),
|
|
SFR(QCH_CON_LH_AXI_MI_D3_MCSC_QCH, 0x307c, CMU_NOCL1C),
|
|
SFR(QCH_CON_LH_AXI_MI_D4_MCSC_QCH, 0x3080, CMU_NOCL1C),
|
|
SFR(QCH_CON_LH_AXI_MI_D_CSTAT_QCH, 0x30f4, CMU_NOCL1C),
|
|
SFR(QCH_CON_NOCL1C_CMU_NOCL1C_QCH, 0x30fc, CMU_NOCL1C),
|
|
SFR(QCH_CON_SIU_8X1_P0_NOCL1C_QCH, 0x3084, CMU_NOCL1C),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_BRP_QCH, 0x3088, CMU_NOCL1C),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_CSIS_QCH, 0x3110, CMU_NOCL1C),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_CSTAT_QCH, 0x3114, CMU_NOCL1C),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_MCSC_QCH, 0x3120, CMU_NOCL1C),
|
|
SFR(QCH_CON_SLH_AST_MI_G_PPMU_YUVP_QCH, 0x3128, CMU_NOCL1C),
|
|
SFR(QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_QCH, 0x3138, CMU_NOCL1C),
|
|
SFR(QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1C_QCH, 0x312c, CMU_NOCL1C),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_NOCL1C_QCH, 0x3130, CMU_NOCL1C),
|
|
SFR(QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_QCH, 0x313c, CMU_NOCL1C),
|
|
SFR(QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1C_QCH, 0x3134, CMU_NOCL1C),
|
|
SFR(QCH_CON_SLH_AXI_MI_D0_MCSC_QCH, 0x30b8, CMU_NOCL1C),
|
|
SFR(QCH_CON_SLH_AXI_MI_D1_YUVP_QCH, 0x308c, CMU_NOCL1C),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_BRP_QCH, 0x3098, CMU_NOCL1C),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_CSIS_QCH, 0x3154, CMU_NOCL1C),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_CSTAT_QCH, 0x3158, CMU_NOCL1C),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_MCSC_QCH, 0x3164, CMU_NOCL1C),
|
|
SFR(QCH_CON_SLH_AXI_SI_P_YUVP_QCH, 0x316c, CMU_NOCL1C),
|
|
SFR(QCH_CON_SYSREG_NOCL1C_QCH, 0x3170, CMU_NOCL1C),
|
|
SFR(QCH_CON_TREX_D_NOCL1C_QCH, 0x3174, CMU_NOCL1C),
|
|
SFR(QCH_CON_TREX_P_NOCL1C_QCH, 0x3178, CMU_NOCL1C),
|
|
SFR(QCH_CON_D_TZPC_PERIC0_QCH, 0x3008, CMU_PERIC0),
|
|
SFR(QCH_CON_GPIO_PERIC0_QCH, 0x300c, CMU_PERIC0),
|
|
SFR(QCH_CON_I3C00_QCH_S, 0x3014, CMU_PERIC0),
|
|
SFR(QCH_CON_I3C00_QCH_P, 0x3004, CMU_PERIC0),
|
|
SFR(QCH_CON_I3C01_QCH_S, 0x302c, CMU_PERIC0),
|
|
SFR(QCH_CON_I3C01_QCH_P, 0x3028, CMU_PERIC0),
|
|
SFR(QCH_CON_I3C02_QCH_S, 0x3034, CMU_PERIC0),
|
|
SFR(QCH_CON_I3C02_QCH_P, 0x3030, CMU_PERIC0),
|
|
SFR(QCH_CON_PERIC0_CMU_PERIC0_QCH, 0x3010, CMU_PERIC0),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_PERIC0_QCH, 0x3018, CMU_PERIC0),
|
|
SFR(QCH_CON_SYSREG_PERIC0_QCH, 0x301c, CMU_PERIC0),
|
|
SFR(QCH_CON_USI04_I2C_QCH, 0x3020, CMU_PERIC0),
|
|
SFR(QCH_CON_USI04_USI_QCH, 0x3024, CMU_PERIC0),
|
|
SFR(QCH_CON_BT_UART_QCH, 0x3008, CMU_PERIC1),
|
|
SFR(QCH_CON_D_TZPC_PERIC1_QCH, 0x300c, CMU_PERIC1),
|
|
SFR(QCH_CON_GPIO_PERIC1_QCH, 0x3010, CMU_PERIC1),
|
|
SFR(QCH_CON_PERIC1_CMU_PERIC1_QCH, 0x3044, CMU_PERIC1),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_PERIC1_QCH, 0x304c, CMU_PERIC1),
|
|
SFR(QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH, 0x3050, CMU_PERIC1),
|
|
SFR(QCH_CON_SYSREG_PERIC1_QCH, 0x3054, CMU_PERIC1),
|
|
SFR(QCH_CON_USI07_SPI_I2C_QCH, 0x3058, CMU_PERIC1),
|
|
SFR(QCH_CON_USI07_USI_QCH, 0x305c, CMU_PERIC1),
|
|
SFR(QCH_CON_USI08_SPI_I2C_QCH, 0x3060, CMU_PERIC1),
|
|
SFR(QCH_CON_USI08_USI_QCH, 0x3064, CMU_PERIC1),
|
|
SFR(QCH_CON_USI09_I2C_QCH, 0x3068, CMU_PERIC1),
|
|
SFR(QCH_CON_USI09_USI_QCH, 0x306c, CMU_PERIC1),
|
|
SFR(QCH_CON_USI10_I2C_QCH, 0x3070, CMU_PERIC1),
|
|
SFR(QCH_CON_USI10_USI_QCH, 0x3074, CMU_PERIC1),
|
|
SFR(QCH_CON_DBG_UART_QCH, 0x3004, CMU_PERIC2),
|
|
SFR(QCH_CON_D_TZPC_PERIC2_QCH, 0x3008, CMU_PERIC2),
|
|
SFR(QCH_CON_GPIO_PERIC2_QCH, 0x300c, CMU_PERIC2),
|
|
SFR(QCH_CON_I3C03_OIS_QCH_S, 0x3014, CMU_PERIC2),
|
|
SFR(QCH_CON_I3C03_OIS_QCH_P, 0x3010, CMU_PERIC2),
|
|
SFR(QCH_CON_I3C04_QCH_S, 0x301c, CMU_PERIC2),
|
|
SFR(QCH_CON_I3C04_QCH_P, 0x3018, CMU_PERIC2),
|
|
SFR(QCH_CON_I3C05_QCH_S, 0x3024, CMU_PERIC2),
|
|
SFR(QCH_CON_I3C05_QCH_P, 0x3020, CMU_PERIC2),
|
|
SFR(QCH_CON_I3C06_QCH_S, 0x302c, CMU_PERIC2),
|
|
SFR(QCH_CON_I3C06_QCH_P, 0x3028, CMU_PERIC2),
|
|
SFR(QCH_CON_I3C07_QCH_S, 0x3034, CMU_PERIC2),
|
|
SFR(QCH_CON_I3C07_QCH_P, 0x3030, CMU_PERIC2),
|
|
SFR(QCH_CON_I3C08_QCH_S, 0x303c, CMU_PERIC2),
|
|
SFR(QCH_CON_I3C08_QCH_P, 0x3038, CMU_PERIC2),
|
|
SFR(QCH_CON_I3C09_QCH_S, 0x3044, CMU_PERIC2),
|
|
SFR(QCH_CON_I3C09_QCH_P, 0x3040, CMU_PERIC2),
|
|
SFR(QCH_CON_I3C10_QCH_S, 0x304c, CMU_PERIC2),
|
|
SFR(QCH_CON_I3C10_QCH_P, 0x3048, CMU_PERIC2),
|
|
SFR(QCH_CON_I3C11_QCH_S, 0x3054, CMU_PERIC2),
|
|
SFR(QCH_CON_I3C11_QCH_P, 0x3050, CMU_PERIC2),
|
|
SFR(QCH_CON_PERIC2_CMU_PERIC2_QCH, 0x3058, CMU_PERIC2),
|
|
SFR(QCH_CON_PWM_QCH, 0x305c, CMU_PERIC2),
|
|
SFR(QCH_CON_SLH_AXI_MI_LP_CSISPERIC2_QCH, 0x30a8, CMU_PERIC2),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_PERIC2_QCH, 0x3060, CMU_PERIC2),
|
|
SFR(QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH, 0x3064, CMU_PERIC2),
|
|
SFR(QCH_CON_SYSREG_PERIC2_QCH, 0x3068, CMU_PERIC2),
|
|
SFR(QCH_CON_USI00_SPI_I2C_QCH, 0x306c, CMU_PERIC2),
|
|
SFR(QCH_CON_USI00_USI_QCH, 0x3070, CMU_PERIC2),
|
|
SFR(QCH_CON_USI01_SPI_I2C_QCH, 0x3074, CMU_PERIC2),
|
|
SFR(QCH_CON_USI01_USI_QCH, 0x3078, CMU_PERIC2),
|
|
SFR(QCH_CON_USI02_I2C_QCH, 0x307c, CMU_PERIC2),
|
|
SFR(QCH_CON_USI02_USI_QCH, 0x3080, CMU_PERIC2),
|
|
SFR(QCH_CON_USI03_I2C_QCH, 0x3084, CMU_PERIC2),
|
|
SFR(QCH_CON_USI03_USI_QCH, 0x3088, CMU_PERIC2),
|
|
SFR(QCH_CON_USI05_I2C_QCH, 0x308c, CMU_PERIC2),
|
|
SFR(QCH_CON_USI05_USI_OIS_QCH, 0x3090, CMU_PERIC2),
|
|
SFR(QCH_CON_USI06_I2C_QCH, 0x3094, CMU_PERIC2),
|
|
SFR(QCH_CON_USI06_USI_OIS_QCH, 0x3098, CMU_PERIC2),
|
|
SFR(QCH_CON_USI11_I2C_QCH, 0x309c, CMU_PERIC2),
|
|
SFR(QCH_CON_USI11_USI_QCH, 0x30a0, CMU_PERIC2),
|
|
SFR(QCH_CON_BUSIF_DDD_PERIS_QCH, 0x3014, CMU_PERIS),
|
|
SFR(DMYQCH_CON_DFTMUX_PERIS_QCH, 0x3000, CMU_PERIS),
|
|
SFR(QCH_CON_D_TZPC_PERIS_QCH, 0x3018, CMU_PERIS),
|
|
SFR(QCH_CON_GIC_QCH, 0x301c, CMU_PERIS),
|
|
SFR(QCH_CON_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_QCH, 0x3020, CMU_PERIS),
|
|
SFR(QCH_CON_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_QCH, 0x3024, CMU_PERIS),
|
|
SFR(QCH_CON_MCT_QCH, 0x3028, CMU_PERIS),
|
|
SFR(QCH_CON_OTP_CON_BIRA_QCH, 0x302c, CMU_PERIS),
|
|
SFR(QCH_CON_OTP_CON_TOP_QCH, 0x3030, CMU_PERIS),
|
|
SFR(QCH_CON_PERIS_CMU_PERIS_QCH, 0x3034, CMU_PERIS),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_PERIS_QCH, 0x303c, CMU_PERIS),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_PERISGIC_QCH, 0x3038, CMU_PERIS),
|
|
SFR(QCH_CON_SYSREG_PERIS_QCH, 0x3040, CMU_PERIS),
|
|
SFR(QCH_CON_TMU_SUB_QCH, 0x3044, CMU_PERIS),
|
|
SFR(QCH_CON_TMU_TOP_QCH, 0x3048, CMU_PERIS),
|
|
SFR(QCH_CON_WDT0_QCH, 0x304c, CMU_PERIS),
|
|
SFR(QCH_CON_WDT1_QCH, 0x3050, CMU_PERIS),
|
|
SFR(DMYQCH_CON_BIS_S2D_QCH, 0x3000, CMU_S2D),
|
|
SFR(QCH_CON_S2D_CMU_S2D_QCH, 0x3008, CMU_S2D),
|
|
SFR(QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH, 0x300c, CMU_S2D),
|
|
SFR(QCH_CON_D_TZPC_SDMA_QCH, 0x3048, CMU_SDMA),
|
|
SFR(QCH_CON_IP_SDMA_QCH, 0x304c, CMU_SDMA),
|
|
SFR(QCH_CON_LH_AST_SI_LD_STRM_SDMADSP0_QCH, 0x3050, CMU_SDMA),
|
|
SFR(QCH_CON_LH_AXI_MI_LP_DNCSDMA_QCH, 0x305c, CMU_SDMA),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA0_QCH, 0x3060, CMU_SDMA),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA1_QCH, 0x3064, CMU_SDMA),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA2_QCH, 0x3068, CMU_SDMA),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA3_QCH, 0x306c, CMU_SDMA),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA4_QCH, 0x303c, CMU_SDMA),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA5_QCH, 0x3040, CMU_SDMA),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA6_QCH, 0x3054, CMU_SDMA),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA7_QCH, 0x3058, CMU_SDMA),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU0_QCH, 0x3080, CMU_SDMA),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU1_QCH, 0x3084, CMU_SDMA),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU2_QCH, 0x3070, CMU_SDMA),
|
|
SFR(QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU3_QCH, 0x3074, CMU_SDMA),
|
|
SFR(QCH_CON_SDMA_CMU_SDMA_QCH, 0x3090, CMU_SDMA),
|
|
SFR(QCH_CON_SLH_AXI_MI_LP_SDMA_QCH, 0x3094, CMU_SDMA),
|
|
SFR(QCH_CON_SYSREG_SDMA_QCH, 0x3098, CMU_SDMA),
|
|
SFR(QCH_CON_BAAW_SSS_QCH, 0x301c, CMU_SSP),
|
|
SFR(QCH_CON_D_TZPC_SSP_QCH, 0x3020, CMU_SSP),
|
|
SFR(QCH_CON_HW_APBSEMA_MEC_QCH, 0x302c, CMU_SSP),
|
|
SFR(QCH_CON_LH_AXI_MI_L_STRONG_QCH, 0x3024, CMU_SSP),
|
|
SFR(QCH_CON_PPMU_SSP_QCH, 0x3028, CMU_SSP),
|
|
SFR(QCH_CON_QE_SSS_QCH, 0x3030, CMU_SSP),
|
|
SFR(QCH_CON_QE_STRONG_QCH, 0x3034, CMU_SSP),
|
|
SFR(QCH_CON_SLH_ACEL_SI_D_SSP_QCH, 0x3040, CMU_SSP),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_SSP_QCH, 0x3044, CMU_SSP),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_SSP_QCH, 0x3048, CMU_SSP),
|
|
SFR(QCH_CON_SSP_CMU_SSP_QCH, 0x304c, CMU_SSP),
|
|
SFR(QCH_CON_SSS_QCH, 0x3050, CMU_SSP),
|
|
SFR(QCH_CON_SYSMMU_SSP_QCH, 0x3058, CMU_SSP),
|
|
SFR(QCH_CON_SYSREG_SSP_QCH, 0x305c, CMU_SSP),
|
|
SFR(QCH_CON_VGEN_LITE_SSP_QCH, 0x3060, CMU_SSP),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_QCH, 0x300c, CMU_STRONG),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_QCH, 0x3008, CMU_STRONG),
|
|
SFR(QCH_CON_STRONG_CMU_STRONG_QCH, 0x3004, CMU_STRONG),
|
|
SFR(QCH_CON_BAAW_D_UFDDNC_QCH, 0x3020, CMU_UFD),
|
|
SFR(QCH_CON_D_TZPC_UFD_QCH, 0x3024, CMU_UFD),
|
|
SFR(QCH_CON_I3C_UFD_QCH_PCLK, 0x3028, CMU_UFD),
|
|
SFR(QCH_CON_I3C_UFD_QCH_SCLK, 0x302c, CMU_UFD),
|
|
SFR(QCH_CON_LH_AST_SI_OTF_UFDDNC_QCH, 0x3078, CMU_UFD),
|
|
SFR(QCH_CON_PDMA_UFD_QCH, 0x3030, CMU_UFD),
|
|
SFR(QCH_CON_PPMU_D_UFD_QCH, 0x304c, CMU_UFD),
|
|
SFR(QCH_CON_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_QCH, 0x307c, CMU_UFD),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_QCH, 0x3080, CMU_UFD),
|
|
SFR(QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_QCH, 0x3084, CMU_UFD),
|
|
SFR(QCH_CON_SLH_AST_MI_OTF_CSISUFD_QCH, 0x3034, CMU_UFD),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_UFD_QCH, 0x3088, CMU_UFD),
|
|
SFR(QCH_CON_SLH_AXI_MI_LP_CMGPUFD_QCH, 0x3038, CMU_UFD),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_UFD_QCH, 0x303c, CMU_UFD),
|
|
SFR(QCH_CON_SLH_AXI_SI_D_UFD_QCH, 0x3040, CMU_UFD),
|
|
SFR(QCH_CON_SLH_AXI_SI_LD_UFDDNC_QCH, 0x3044, CMU_UFD),
|
|
SFR(QCH_CON_SLH_AXI_SI_LP_UFDCSIS_QCH, 0x3048, CMU_UFD),
|
|
SFR(QCH_CON_SRAM_MIU_UFD_QCH, 0x3050, CMU_UFD),
|
|
SFR(QCH_CON_SYSMMU_D_UFD_QCH_S1, 0x308c, CMU_UFD),
|
|
SFR(QCH_CON_SYSMMU_D_UFD_QCH_S2, 0x3090, CMU_UFD),
|
|
SFR(QCH_CON_SYSREG_UFD_QCH, 0x3054, CMU_UFD),
|
|
SFR(QCH_CON_SYSREG_UFD_SECURE_QCH, 0x3058, CMU_UFD),
|
|
SFR(QCH_CON_UFD_CMU_UFD_QCH, 0x305c, CMU_UFD),
|
|
SFR(QCH_CON_VGEN_LITE_D_UFD_QCH, 0x3064, CMU_UFD),
|
|
SFR(QCH_CON_UFD_QCH, 0x3060, CMU_UFD),
|
|
SFR(QCH_CON_D_TZPC_UFS_QCH, 0x3038, CMU_UFS),
|
|
SFR(QCH_CON_GPIO_HSI1UFS_QCH, 0x303c, CMU_UFS),
|
|
SFR(QCH_CON_GPIO_UFS_QCH, 0x3040, CMU_UFS),
|
|
SFR(QCH_CON_LH_ACEL_SI_D_UFS_QCH, 0x3044, CMU_UFS),
|
|
SFR(QCH_CON_MMC_CARD_QCH, 0x3048, CMU_UFS),
|
|
SFR(QCH_CON_PPMU_UFS_QCH, 0x304c, CMU_UFS),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_UFS_QCH, 0x3050, CMU_UFS),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_UFS_QCH, 0x3054, CMU_UFS),
|
|
SFR(QCH_CON_SPC_UFS_QCH, 0x3058, CMU_UFS),
|
|
SFR(QCH_CON_SYSMMU_UFS_QCH_S2, 0x305c, CMU_UFS),
|
|
SFR(QCH_CON_SYSREG_UFS_QCH, 0x3060, CMU_UFS),
|
|
SFR(QCH_CON_UFS_CMU_UFS_QCH, 0x3064, CMU_UFS),
|
|
SFR(QCH_CON_UFS_EMBD_QCH_FMP, 0x306c, CMU_UFS),
|
|
SFR(QCH_CON_UFS_EMBD_QCH, 0x3068, CMU_UFS),
|
|
SFR(QCH_CON_VGEN_LITE_UFS_QCH, 0x3070, CMU_UFS),
|
|
SFR(QCH_CON_ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT, 0x3044, CMU_VTS),
|
|
SFR(QCH_CON_BAAW_VTS_QCH, 0x3038, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_IF0_QCH_PCLK, 0x3064, CMU_VTS),
|
|
SFR(DMYQCH_CON_DMIC_IF0_QCH_DMIC, 0x3000, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_IF1_QCH_PCLK, 0x3068, CMU_VTS),
|
|
SFR(DMYQCH_CON_DMIC_IF1_QCH_DMIC, 0x3004, CMU_VTS),
|
|
SFR(QCH_CON_DMIC_IF2_QCH_PCLK, 0x306c, CMU_VTS),
|
|
SFR(DMYQCH_CON_DMIC_IF2_QCH_DMIC, 0x3008, CMU_VTS),
|
|
SFR(QCH_CON_GPIO_VTS_QCH, 0x3074, CMU_VTS),
|
|
SFR(QCH_CON_INTMEM_CODE_QCH, 0x3084, CMU_VTS),
|
|
SFR(QCH_CON_INTMEM_DATA0_QCH, 0x3088, CMU_VTS),
|
|
SFR(QCH_CON_INTMEM_DATA1_QCH, 0x308c, CMU_VTS),
|
|
SFR(QCH_CON_INTMEM_PCM_QCH, 0x3090, CMU_VTS),
|
|
SFR(QCH_CON_LH_AXI_MI_IP_VC2VTS_QCH, 0x303c, CMU_VTS),
|
|
SFR(QCH_CON_LH_AXI_SI_ID_VTS2VC_QCH, 0x3040, CMU_VTS),
|
|
SFR(QCH_CON_MAILBOX_ABOX_VTS_QCH, 0x3094, CMU_VTS),
|
|
SFR(QCH_CON_MAILBOX_AP_VTS_QCH, 0x3098, CMU_VTS),
|
|
SFR(QCH_CON_MAILBOX_DNC_VTS_QCH, 0x309c, CMU_VTS),
|
|
SFR(QCH_CON_SERIAL_LIF_VT_QCH_PCLK, 0x30b0, CMU_VTS),
|
|
SFR(QCH_CON_SERIAL_LIF_VT_QCH_CCLK, 0x30ac, CMU_VTS),
|
|
SFR(QCH_CON_SERIAL_LIF_VT_QCH_ACLK, 0x30a4, CMU_VTS),
|
|
SFR(QCH_CON_SERIAL_LIF_VT_QCH_BCLK, 0x30a8, CMU_VTS),
|
|
SFR(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0, 0x3010, CMU_VTS),
|
|
SFR(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1, 0x3014, CMU_VTS),
|
|
SFR(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2, 0x3018, CMU_VTS),
|
|
SFR(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK, 0x300c, CMU_VTS),
|
|
SFR(QCH_CON_SYSREG_VTS_QCH, 0x30cc, CMU_VTS),
|
|
SFR(QCH_CON_TIMER_QCH, 0x30d8, CMU_VTS),
|
|
SFR(QCH_CON_TIMER1_QCH, 0x30d0, CMU_VTS),
|
|
SFR(QCH_CON_TIMER2_QCH, 0x30d4, CMU_VTS),
|
|
SFR(QCH_CON_VTS_CMU_VTS_QCH, 0x30e0, CMU_VTS),
|
|
SFR(QCH_CON_WDT_VTS_QCH, 0x30e4, CMU_VTS),
|
|
SFR(QCH_CON_YAMIN_MCU_VTS_QCH_CLKIN, 0x30e8, CMU_VTS),
|
|
SFR(QCH_CON_YAMIN_MCU_VTS_QCH_DBGCLK, 0x30ec, CMU_VTS),
|
|
SFR(QCH_CON_BUSIF_DDD_YUVP_QCH, 0x302c, CMU_YUVP),
|
|
SFR(QCH_CON_D_TZPC_YUVP_QCH, 0x3034, CMU_YUVP),
|
|
SFR(QCH_CON_LH_AST_MI_OTF_MCSCYUVP_QCH, 0x3038, CMU_YUVP),
|
|
SFR(QCH_CON_LH_AST_SI_OTF0_YUVPMCSC_QCH, 0x3040, CMU_YUVP),
|
|
SFR(QCH_CON_LH_AST_SI_OTF1_YUVPMCSC_QCH, 0x3014, CMU_YUVP),
|
|
SFR(QCH_CON_LH_AXI_SI_D0_YUVP_QCH, 0x3024, CMU_YUVP),
|
|
SFR(QCH_CON_PPMU_D0_YUVP_QCH, 0x3044, CMU_YUVP),
|
|
SFR(QCH_CON_PPMU_D1_YUVP_QCH, 0x3030, CMU_YUVP),
|
|
SFR(QCH_CON_SIU_G_PPMU_YUVP_QCH, 0x303c, CMU_YUVP),
|
|
SFR(QCH_CON_SLH_AST_SI_G_PPMU_YUVP_QCH, 0x3048, CMU_YUVP),
|
|
SFR(QCH_CON_SLH_AXI_MI_P_YUVP_QCH, 0x304c, CMU_YUVP),
|
|
SFR(QCH_CON_SLH_AXI_SI_D1_YUVP_QCH, 0x3050, CMU_YUVP),
|
|
SFR(QCH_CON_SYSMMU_D0_YUVP_QCH_S1, 0x3054, CMU_YUVP),
|
|
SFR(QCH_CON_SYSMMU_D0_YUVP_QCH_S2, 0x3058, CMU_YUVP),
|
|
SFR(QCH_CON_SYSMMU_D1_YUVP_QCH_S1, 0x306c, CMU_YUVP),
|
|
SFR(QCH_CON_SYSMMU_D1_YUVP_QCH_S2, 0x3070, CMU_YUVP),
|
|
SFR(QCH_CON_SYSREG_YUVP_QCH, 0x305c, CMU_YUVP),
|
|
SFR(QCH_CON_VGEN_LITE_D0_YUVP_QCH, 0x3060, CMU_YUVP),
|
|
SFR(QCH_CON_VGEN_LITE_D1_YUVP_QCH, 0x3074, CMU_YUVP),
|
|
SFR(QCH_CON_YUVP_QCH, 0x3068, CMU_YUVP),
|
|
SFR(QCH_CON_YUVP_QCH_VOTF0, 0x3078, CMU_YUVP),
|
|
SFR(QCH_CON_YUVP_QCH_VOTF1, 0x307c, CMU_YUVP),
|
|
SFR(QCH_CON_YUVP_CMU_YUVP_QCH, 0x3064, CMU_YUVP),
|
|
SFR(ALIVE_CMU_ALIVE_CONTROLLER_OPTION, 0x800, CMU_ALIVE),
|
|
SFR(ALLCSIS_CMU_ALLCSIS_CONTROLLER_OPTION, 0x800, CMU_ALLCSIS),
|
|
SFR(AUD_CMU_AUD_CONTROLLER_OPTION, 0x800, CMU_AUD),
|
|
SFR(BRP_CMU_BRP_CONTROLLER_OPTION, 0x800, CMU_BRP),
|
|
SFR(CHUB_CMU_CHUB_CONTROLLER_OPTION, 0x800, CMU_CHUB),
|
|
SFR(CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION, 0x800, CMU_CHUBVTS),
|
|
SFR(CMGP_CMU_CMGP_CONTROLLER_OPTION, 0x800, CMU_CMGP),
|
|
SFR(CMU_CMU_TOP_CONTROLLER_OPTION, 0x800, CMU_TOP),
|
|
SFR(CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION, 0x800, CMU_CPUCL0),
|
|
SFR(CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION, 0x800, CMU_CPUCL0_GLB),
|
|
SFR(CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION, 0x800, CMU_CPUCL1),
|
|
SFR(CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION, 0x800, CMU_CPUCL2),
|
|
SFR(CSIS_CMU_CSIS_CONTROLLER_OPTION, 0x800, CMU_CSIS),
|
|
SFR(CSTAT_CMU_CSTAT_CONTROLLER_OPTION, 0x800, CMU_CSTAT),
|
|
SFR(DBGCORE_CMU_DBGCORE_CONTROLLER_OPTION, 0x800, CMU_DBGCORE),
|
|
SFR(DNC_CMU_DNC_CONTROLLER_OPTION, 0x800, CMU_DNC),
|
|
SFR(DPUB_CMU_DPUB_CONTROLLER_OPTION, 0x800, CMU_DPUB),
|
|
SFR(DPUF_CMU_DPUF_CONTROLLER_OPTION, 0x800, CMU_DPUF),
|
|
SFR(DPUF1_CMU_DPUF1_CONTROLLER_OPTION, 0x800, CMU_DPUF1),
|
|
SFR(DRCP_CMU_DRCP_CONTROLLER_OPTION, 0x800, CMU_DRCP),
|
|
SFR(DSP_CMU_DSP_CONTROLLER_OPTION, 0x800, CMU_DSP),
|
|
SFR(DSU_CMU_DSU_CONTROLLER_OPTION, 0x800, CMU_DSU),
|
|
SFR(G3D_CMU_G3D_CONTROLLER_OPTION, 0x800, CMU_G3D),
|
|
SFR(G3DCORE_CMU_G3DCORE_CONTROLLER_OPTION, 0x800, CMU_G3DCORE),
|
|
SFR(GNPU_CMU_GNPU_CONTROLLER_OPTION, 0x800, CMU_GNPU),
|
|
SFR(GNSS_CMU_GNSS_CONTROLLER_OPTION, 0x800, CMU_GNSS),
|
|
SFR(HSI0_CMU_HSI0_CONTROLLER_OPTION, 0x800, CMU_HSI0),
|
|
SFR(HSI1_CMU_HSI1_CONTROLLER_OPTION, 0x800, CMU_HSI1),
|
|
SFR(LME_CMU_LME_CONTROLLER_OPTION, 0x800, CMU_LME),
|
|
SFR(M2M_CMU_M2M_CONTROLLER_OPTION, 0x800, CMU_M2M),
|
|
SFR(MCSC_CMU_MCSC_CONTROLLER_OPTION, 0x800, CMU_MCSC),
|
|
SFR(MFC0_CMU_MFC0_CONTROLLER_OPTION, 0x800, CMU_MFC0),
|
|
SFR(MFC1_CMU_MFC1_CONTROLLER_OPTION, 0x800, CMU_MFC1),
|
|
SFR(MIF_CMU_MIF_CONTROLLER_OPTION, 0x800, CMU_MIF),
|
|
SFR(NOCL0_CMU_NOCL0_CONTROLLER_OPTION, 0x800, CMU_NOCL0),
|
|
SFR(NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION, 0x800, CMU_NOCL1A),
|
|
SFR(NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION, 0x800, CMU_NOCL1B),
|
|
SFR(NOCL1C_CMU_NOCL1C_CONTROLLER_OPTION, 0x800, CMU_NOCL1C),
|
|
SFR(PERIC0_CMU_PERIC0_CONTROLLER_OPTION, 0x800, CMU_PERIC0),
|
|
SFR(PERIC1_CMU_PERIC1_CONTROLLER_OPTION, 0x800, CMU_PERIC1),
|
|
SFR(PERIC2_CMU_PERIC2_CONTROLLER_OPTION, 0x800, CMU_PERIC2),
|
|
SFR(PERIS_CMU_PERIS_CONTROLLER_OPTION, 0x800, CMU_PERIS),
|
|
SFR(S2D_CMU_S2D_CONTROLLER_OPTION, 0x800, CMU_S2D),
|
|
SFR(SDMA_CMU_SDMA_CONTROLLER_OPTION, 0x800, CMU_SDMA),
|
|
SFR(SSP_CMU_SSP_CONTROLLER_OPTION, 0x800, CMU_SSP),
|
|
SFR(STRONG_CMU_STRONG_CONTROLLER_OPTION, 0x800, CMU_STRONG),
|
|
SFR(UFD_CMU_UFD_CONTROLLER_OPTION, 0x800, CMU_UFD),
|
|
SFR(UFS_CMU_UFS_CONTROLLER_OPTION, 0x800, CMU_UFS),
|
|
SFR(VTS_CMU_VTS_CONTROLLER_OPTION, 0x800, CMU_VTS),
|
|
SFR(YUVP_CMU_YUVP_CONTROLLER_OPTION, 0x800, CMU_YUVP),
|
|
};
|
|
|
|
unsigned int cmucal_sfr_access_size = 12451;
|
|
struct sfr_access cmucal_sfr_access_list[] = {
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_AUD_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD_ENABLE, 31, 1, PLL_CON3_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD_STABLE, 29, 1, PLL_CON3_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD_DIV_P, 8, 6, PLL_CON3_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD_DIV_M, 16, 10, PLL_CON3_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON3_PLL_AUD_DIV_S, 0, 3, PLL_CON3_PLL_AUD),
|
|
SFR_ACCESS(PLL_CON8_PLL_AUD_F, 0, 32, PLL_CON8_PLL_AUD),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_MMC_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_ENABLE, 31, 1, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_STABLE, 29, 1, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_DIV_P, 8, 6, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_DIV_M, 16, 10, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON3_PLL_MMC_DIV_S, 0, 3, PLL_CON3_PLL_MMC),
|
|
SFR_ACCESS(PLL_CON8_PLL_MMC_F, 0, 32, PLL_CON8_PLL_MMC),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED0_ENABLE, 31, 1, PLL_CON3_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED0_STABLE, 29, 1, PLL_CON3_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED0_DIV_P, 8, 6, PLL_CON3_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED0_DIV_M, 16, 10, PLL_CON3_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED0_DIV_S, 0, 3, PLL_CON3_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_CON8_PLL_SHARED0_F, 0, 32, PLL_CON8_PLL_SHARED0),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED1_ENABLE, 31, 1, PLL_CON3_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED1_STABLE, 29, 1, PLL_CON3_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED1_DIV_P, 8, 6, PLL_CON3_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED1_DIV_M, 16, 10, PLL_CON3_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED1_DIV_S, 0, 3, PLL_CON3_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_CON8_PLL_SHARED1_F, 0, 32, PLL_CON8_PLL_SHARED1),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED2_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED2_ENABLE, 31, 1, PLL_CON3_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED2_STABLE, 29, 1, PLL_CON3_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED2_DIV_P, 8, 6, PLL_CON3_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED2_DIV_M, 16, 10, PLL_CON3_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED2_DIV_S, 0, 3, PLL_CON3_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_CON8_PLL_SHARED2_F, 0, 32, PLL_CON8_PLL_SHARED2),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED3_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED3),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED3_ENABLE, 31, 1, PLL_CON3_PLL_SHARED3),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED3_STABLE, 29, 1, PLL_CON3_PLL_SHARED3),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED3_DIV_P, 8, 6, PLL_CON3_PLL_SHARED3),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED3_DIV_M, 16, 10, PLL_CON3_PLL_SHARED3),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED3_DIV_S, 0, 3, PLL_CON3_PLL_SHARED3),
|
|
SFR_ACCESS(PLL_CON8_PLL_SHARED3_F, 0, 32, PLL_CON8_PLL_SHARED3),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED4_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED4),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED4_ENABLE, 31, 1, PLL_CON3_PLL_SHARED4),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED4_STABLE, 29, 1, PLL_CON3_PLL_SHARED4),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED4_DIV_P, 8, 6, PLL_CON3_PLL_SHARED4),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED4_DIV_M, 16, 10, PLL_CON3_PLL_SHARED4),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED4_DIV_S, 0, 3, PLL_CON3_PLL_SHARED4),
|
|
SFR_ACCESS(PLL_CON8_PLL_SHARED4_F, 0, 32, PLL_CON8_PLL_SHARED4),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED_MIF_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED_MIF),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED_MIF_ENABLE, 31, 1, PLL_CON3_PLL_SHARED_MIF),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED_MIF_STABLE, 29, 1, PLL_CON3_PLL_SHARED_MIF),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED_MIF_DIV_P, 8, 6, PLL_CON3_PLL_SHARED_MIF),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED_MIF_DIV_M, 16, 10, PLL_CON3_PLL_SHARED_MIF),
|
|
SFR_ACCESS(PLL_CON3_PLL_SHARED_MIF_DIV_S, 0, 3, PLL_CON3_PLL_SHARED_MIF),
|
|
SFR_ACCESS(PLL_CON8_PLL_SHARED_MIF_F, 0, 32, PLL_CON8_PLL_SHARED_MIF),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL0_ENABLE, 31, 1, PLL_CON3_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL0_STABLE, 29, 1, PLL_CON3_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL0_DIV_P, 8, 6, PLL_CON3_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL0_DIV_M, 16, 10, PLL_CON3_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL0_DIV_S, 0, 3, PLL_CON3_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_CON8_PLL_CPUCL0_F, 0, 32, PLL_CON8_PLL_CPUCL0),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL1_ENABLE, 31, 1, PLL_CON3_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL1_STABLE, 29, 1, PLL_CON3_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL1_DIV_P, 8, 6, PLL_CON3_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL1_DIV_M, 16, 10, PLL_CON3_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL1_DIV_S, 0, 3, PLL_CON3_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_CON8_PLL_CPUCL1_F, 0, 32, PLL_CON8_PLL_CPUCL1),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL2_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_CPUCL2),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL2_ENABLE, 31, 1, PLL_CON3_PLL_CPUCL2),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL2_STABLE, 29, 1, PLL_CON3_PLL_CPUCL2),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL2_DIV_P, 8, 6, PLL_CON3_PLL_CPUCL2),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL2_DIV_M, 16, 10, PLL_CON3_PLL_CPUCL2),
|
|
SFR_ACCESS(PLL_CON3_PLL_CPUCL2_DIV_S, 0, 3, PLL_CON3_PLL_CPUCL2),
|
|
SFR_ACCESS(PLL_CON8_PLL_CPUCL2_F, 0, 32, PLL_CON8_PLL_CPUCL2),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_DSU_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON3_PLL_DSU_ENABLE, 31, 1, PLL_CON3_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON3_PLL_DSU_STABLE, 29, 1, PLL_CON3_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON3_PLL_DSU_DIV_P, 8, 6, PLL_CON3_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON3_PLL_DSU_DIV_M, 16, 10, PLL_CON3_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON3_PLL_DSU_DIV_S, 0, 3, PLL_CON3_PLL_DSU),
|
|
SFR_ACCESS(PLL_CON8_PLL_DSU_F, 0, 32, PLL_CON8_PLL_DSU),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D_ENABLE, 31, 1, PLL_CON3_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D_STABLE, 29, 1, PLL_CON3_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D_DIV_P, 8, 6, PLL_CON3_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D_DIV_M, 16, 10, PLL_CON3_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D_DIV_S, 0, 3, PLL_CON3_PLL_G3D),
|
|
SFR_ACCESS(PLL_CON8_PLL_G3D_F, 0, 32, PLL_CON8_PLL_G3D),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_G3D1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_G3D1),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D1_ENABLE, 31, 1, PLL_CON3_PLL_G3D1),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D1_STABLE, 29, 1, PLL_CON3_PLL_G3D1),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D1_DIV_P, 8, 6, PLL_CON3_PLL_G3D1),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D1_DIV_M, 16, 10, PLL_CON3_PLL_G3D1),
|
|
SFR_ACCESS(PLL_CON3_PLL_G3D1_DIV_S, 0, 3, PLL_CON3_PLL_G3D1),
|
|
SFR_ACCESS(PLL_CON8_PLL_G3D1_F, 0, 32, PLL_CON8_PLL_G3D1),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_MAIN_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MIF_MAIN),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_MAIN_ENABLE, 31, 1, PLL_CON3_PLL_MIF_MAIN),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_MAIN_STABLE, 29, 1, PLL_CON3_PLL_MIF_MAIN),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_MAIN_DIV_P, 8, 6, PLL_CON3_PLL_MIF_MAIN),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_MAIN_DIV_M, 16, 10, PLL_CON3_PLL_MIF_MAIN),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_MAIN_DIV_S, 0, 3, PLL_CON3_PLL_MIF_MAIN),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_SUB_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MIF_SUB),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_SUB_ENABLE, 31, 1, PLL_CON3_PLL_MIF_SUB),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_SUB_STABLE, 29, 1, PLL_CON3_PLL_MIF_SUB),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_SUB_DIV_P, 8, 6, PLL_CON3_PLL_MIF_SUB),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_SUB_DIV_M, 16, 10, PLL_CON3_PLL_MIF_SUB),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_SUB_DIV_S, 0, 3, PLL_CON3_PLL_MIF_SUB),
|
|
SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_S2D_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_ENABLE, 31, 1, PLL_CON3_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_STABLE, 29, 1, PLL_CON3_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_DIV_P, 8, 6, PLL_CON3_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_DIV_M, 16, 10, PLL_CON3_PLL_MIF_S2D),
|
|
SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_DIV_S, 0, 3, PLL_CON3_PLL_MIF_S2D),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_ALIVE_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_ALIVE_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_ALIVE_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_TIMER_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_ALIVE_TIMER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_TIMER_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_ALIVE_TIMER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_TIMER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_ALIVE_TIMER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_SPMI_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_ALIVE_SPMI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_SPMI_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_ALIVE_SPMI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_SPMI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_ALIVE_SPMI),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF3_SELECT, 0, 3, CLK_CON_MUX_MUX_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF3_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF2_SELECT, 0, 3, CLK_CON_MUX_MUX_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF1_SELECT, 0, 3, CLK_CON_MUX_MUX_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF0_SELECT, 0, 3, CLK_CON_MUX_MUX_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_DSIF_SELECT, 0, 3, CLK_CON_MUX_MUX_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_DSIF_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF4_SELECT, 0, 3, CLK_CON_MUX_MUX_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF4_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF5_SELECT, 0, 3, CLK_CON_MUX_MUX_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF5_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF6_SELECT, 0, 3, CLK_CON_MUX_MUX_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF6_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_UAIF6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_AUD_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_PCMC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_PCMC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_PCMC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_AUDIF_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_AUDIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_AUDIF_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_AUDIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_AUDIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_SCLK_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_AUD_SCLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_SCLK_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_SCLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_SCLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_CORE_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_CORE_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CHUB_TIMER_SELECT, 0, 1, CLK_CON_MUX_MUX_CHUB_TIMER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CHUB_TIMER_BUSY, 16, 1, CLK_CON_MUX_MUX_CHUB_TIMER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CHUB_TIMER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CHUB_TIMER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI3_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI3_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_I2C_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_I2C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_USI2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_USI2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_SPI_MS_CTRL_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_SPI_MS_CTRL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_NOC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUB_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUB_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUB_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUB_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUBVTS_DMAILBOX_CCLK_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUBVTS_DMAILBOX_CCLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUBVTS_DMAILBOX_CCLK_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUBVTS_DMAILBOX_CCLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUBVTS_DMAILBOX_CCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUBVTS_DMAILBOX_CCLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUBVTS_NOC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CHUBVTS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUBVTS_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CHUBVTS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CHUBVTS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CHUBVTS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI4_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI4_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI3_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI3_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI5_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI5_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI6_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI6),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI6_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI6),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_USI6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_USI6),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSP_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_DSP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSP_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DSP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DSP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BRP_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_BRP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BRP_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_BRP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BRP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_BRP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CMU_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DPUF_NOC_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_DPUF_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DPUF_NOC_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_DPUF_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DPUF_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_DPUF_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUF_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_DPUF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUF_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DPUF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DPUF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_M2M_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_M2M_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_M2M_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_M2M_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_M2M_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_M2M_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DPUB_NOC_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_DPUB_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DPUB_NOC_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_DPUB_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DPUB_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_DPUB_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUB_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_DPUB),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUB_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DPUB),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DPUB),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_LME_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_LME_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_LME_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_LME_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_LME_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_LME_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_AUD_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_HISPEEDY_CLK_SELECT, 0, 1, CLK_CON_MUX_MUX_CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_HISPEEDY_CLK_BUSY, 16, 1, CLK_CON_MUX_MUX_CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SSP_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_SSP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SSP_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_SSP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SSP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_SSP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DNC_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_DNC_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DNC_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DNC_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DNC_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_SHARED0_CLK_SELECT, 0, 2, CLK_CON_MUX_MUX_CP_SHARED0_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_SHARED0_CLK_BUSY, 16, 1, CLK_CON_MUX_MUX_CP_SHARED0_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CP_SHARED0_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_SHARED1_CLK_SELECT, 0, 2, CLK_CON_MUX_MUX_CP_SHARED1_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_SHARED1_CLK_BUSY, 16, 1, CLK_CON_MUX_MUX_CP_SHARED1_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_SHARED1_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CP_SHARED1_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_SHARED2_CLK_SELECT, 0, 2, CLK_CON_MUX_MUX_CP_SHARED2_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_SHARED2_CLK_BUSY, 16, 1, CLK_CON_MUX_MUX_CP_SHARED2_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CP_SHARED2_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_LME_LME_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_LME_LME),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_LME_LME_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_LME_LME),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_LME_LME_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_LME_LME),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_M2M_FRC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_M2M_FRC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_M2M_FRC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_M2M_FRC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_M2M_FRC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_M2M_FRC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_UFS_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_UFS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_UFS_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_UFS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_UFS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_UFS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_AUD_CPU_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_AUD_CPU_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_AUD_AUDIF0_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_AUD_AUDIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_AUD_AUDIF0_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_AUD_AUDIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_AUD_AUDIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_AUD_AUDIF0),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_AUD_AUDIF1_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_AUD_AUDIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_AUD_AUDIF1_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_AUD_AUDIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_AUD_AUDIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_AUD_AUDIF1),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DSU_SWITCH_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DSU_SWITCH_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DNC_NOC_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_DNC_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DNC_NOC_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_DNC_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_DNC_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_SDMA_NOC_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_SDMA_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_SDMA_NOC_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_SDMA_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_SDMA_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DSP_NOC_SELECT, 0, 2, CLK_CON_MUX_CLKCMU_DSP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DSP_NOC_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_DSP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_DSP_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_G3D_SWITCH_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_G3D_SWITCH_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_GNPU_NOC_SELECT, 0, 2, CLK_CON_MUX_CLKCMU_GNPU_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_GNPU_NOC_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_GNPU_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_GNPU_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_M2M_NOC_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_M2M_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_M2M_NOC_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_M2M_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_M2M_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_M2M_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_M2M_FRC_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_M2M_FRC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_M2M_FRC_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_M2M_FRC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_M2M_FRC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_M2M_FRC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_MCSC_NOC_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_MCSC_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_MCSC_NOC_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_MCSC_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_MCSC_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_MCSC_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_MCSC_MCSC_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_MCSC_MCSC_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_NOCL0_NOC_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_NOCL0_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_NOCL0_NOC_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_NOCL0_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_NOCL0_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_NOCL1A_NOC_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_NOCL1A_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_NOCL1A_NOC_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_NOCL1A_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_NOCL1A_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_NOCL1B_NOC0_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_NOCL1B_NOC0),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_NOCL1B_NOC0_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_NOCL1B_NOC0),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_NOCL1B_NOC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_NOCL1B_NOC0),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_NOCL1C_NOC_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_NOCL1C_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_NOCL1C_NOC_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_NOCL1C_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_NOCL1C_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_NOCL1C_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_CP_SHARED0_CLK_SELECT, 0, 1, CLK_CON_MUX_CP_SHARED0_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_CP_SHARED0_CLK_BUSY, 16, 1, CLK_CON_MUX_CP_SHARED0_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CP_SHARED0_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_CP_SHARED2_CLK_SELECT, 0, 1, CLK_CON_MUX_CP_SHARED2_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_CP_SHARED2_CLK_BUSY, 16, 1, CLK_CON_MUX_CP_SHARED2_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CP_SHARED2_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_CP_HISPEEDY_CLK_SELECT, 0, 1, CLK_CON_MUX_CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_CP_HISPEEDY_CLK_BUSY, 16, 1, CLK_CON_MUX_CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_UFS_MMC_CARD_SELECT, 0, 1, CLK_CON_MUX_CLKCMU_UFS_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_UFS_MMC_CARD_BUSY, 16, 1, CLK_CON_MUX_CLKCMU_UFS_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_CLKCMU_UFS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKCMU_UFS_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL0_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CPUCL0_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL0_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CPUCL0_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CPUCL0_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_IDLECLKDOWN_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL0_IDLECLKDOWN),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_IDLECLKDOWN_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_IDLECLKDOWN),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_IDLECLKDOWN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_IDLECLKDOWN),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYMUX_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYMUX),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYMUX_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYMUX),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYMUX_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYMUX),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYCHAIN_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYCHAIN),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYCHAIN_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYCHAIN),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYCHAIN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYCHAIN),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_POWERIP_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL0_POWERIP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_POWERIP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_POWERIP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_POWERIP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_POWERIP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_DDD_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_DDD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_DDD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_DDD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_DDD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_DDD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_HTU_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL0_HTU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_HTU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_HTU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_HTU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_HTU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_0_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL1_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CPUCL1_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL1_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CPUCL1_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CPUCL1_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_0_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_0),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_0),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_0),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_0),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_POWERIP_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL1_POWERIP),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_POWERIP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_POWERIP),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_POWERIP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_POWERIP),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_0),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_0),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_0),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_1_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_1),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_1),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_1),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_1),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_1),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_1),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_1),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_1),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_1),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_1_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_1),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_1),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_1),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_2_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_2),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_2),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_2),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_2),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_2),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_2),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_2),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_2),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_2),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_2_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_2),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_2),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_2),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_HTU_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL1_HTU),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_HTU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_HTU),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_HTU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_HTU),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL2_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CPUCL2_CMUREF),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL2_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CPUCL2_CMUREF),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL2_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CPUCL2_CMUREF),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_IDLECLKDOWN_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL2_IDLECLKDOWN),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_IDLECLKDOWN_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_IDLECLKDOWN),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_IDLECLKDOWN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_IDLECLKDOWN),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYCHAIN_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYCHAIN),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYCHAIN_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYCHAIN),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYCHAIN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYCHAIN),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYMUX_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYMUX),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYMUX_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYMUX),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYMUX_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYMUX),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_POWERIP_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL2_POWERIP),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_POWERIP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_POWERIP),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_POWERIP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_POWERIP),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_DDD_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_DDD),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_DDD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_DDD),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_DDD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_DDD),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_HTU_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL2_HTU),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_HTU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_HTU),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_HTU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_HTU),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CSIS_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CSIS_NOC),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CSIS_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CSIS_NOC),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CSIS_NOC),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CSIS_DCPHY_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CSIS_DCPHY),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CSIS_DCPHY_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CSIS_DCPHY),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CSIS_DCPHY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CSIS_DCPHY),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DNC_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_DNC_NOC),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DNC_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_DNC_NOC),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_DNC_NOC),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSP_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_DSP_NOC),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSP_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_DSP_NOC),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_DSP_NOC),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_IDLECLKDOWN_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_DSU_IDLECLKDOWN),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_IDLECLKDOWN_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_DSU_IDLECLKDOWN),
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SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_IDLECLKDOWN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_DSU_IDLECLKDOWN),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_DSU_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_DSU_CMUREF),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_DSU_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_DSU_CMUREF),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_DSU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_DSU_CMUREF),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_DELAYCHAIN_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_DSU_DELAYCHAIN),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_DELAYCHAIN_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_DSU_DELAYCHAIN),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_DELAYCHAIN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_DSU_DELAYCHAIN),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_DELAYMUX_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_DSU_DELAYMUX),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_DELAYMUX_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_DSU_DELAYMUX),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_DELAYMUX_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_DSU_DELAYMUX),
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|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_POWERIP_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_DSU_POWERIP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_POWERIP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_DSU_POWERIP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_POWERIP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_DSU_POWERIP),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_DDD_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_DSU_DDD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_DDD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_DSU_DDD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_DDD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_DSU_DDD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_HTU_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_DSU_HTU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_HTU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_DSU_HTU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_HTU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_DSU_HTU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_CORE_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_G3D_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_CORE_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_G3D_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_G3D_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_DDD_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_G3D_DDD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_DDD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_G3D_DDD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_DDD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_G3D_DDD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_DELAYCHAIN_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_G3D_DELAYCHAIN),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_DELAYCHAIN_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_G3D_DELAYCHAIN),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_DELAYCHAIN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_G3D_DELAYCHAIN),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_DELAYMUX_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_G3D_DELAYMUX),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_DELAYMUX_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_G3D_DELAYMUX),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_DELAYMUX_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_G3D_DELAYMUX),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_PLL_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_G3D_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_PLL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_G3D_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_G3D_PLL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_GNPU_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_GNPU_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_GNPU_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_GNPU_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_GNPU_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_NOC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_HSI0_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_HSI0_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_HSI0_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_MIF_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_MIF_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_MIF_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_NOCL0_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_NOCL0_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_NOCL0_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_NOCL0_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_NOCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_NOCL0_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_NOCL1A_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_NOCL1A_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_NOCL1A_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_NOCL1A_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_NOCL1A_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_NOCL1A_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_NOCL1B_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_NOCL1B_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_NOCL1B_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_NOCL1B_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_NOCL1B_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_NOCL1B_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_NOCL1C_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_NOCL1C_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_NOCL1C_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_NOCL1C_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_NOCL1C_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_NOCL1C_CMUREF),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI04_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC0_USI04),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI04_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI04),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_USI04_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC0_USI04),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_I2C_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC0_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_I2C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC0_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC0_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC0_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_I2C_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC1_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_I2C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC1_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC1_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC1_USI07),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI07_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI07),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI07_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI07),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC1_USI08),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI08_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI08),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI08_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI08),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI09_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC1_USI09),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI09_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI09),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI09_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI09),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI10_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC1_USI10),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI10_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI10),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI10_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI10),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_I2C_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC2_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_I2C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC2_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC2_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC2_USI00),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI00_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI00),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI00_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI00),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC2_USI01),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI01_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI01),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI01_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI01),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI02_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC2_USI02),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI02_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI02),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI02_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI02),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI03_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC2_USI03),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI03_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI03),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI03_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI03),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI05_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC2_USI05),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI05_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI05),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI05_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI05),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI06_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC2_USI06),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI06_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI06),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI06_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI06),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI11_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC2_USI11),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI11_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI11),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI11_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI11),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_S2D_CORE_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_S2D_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_S2D_CORE_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_S2D_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_S2D_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_S2D_CORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_SDMA_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_SDMA_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_SDMA_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_SDMA_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_SDMA_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_UFD_NOC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_UFD_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_UFD_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_UFD_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_UFD_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_UFD_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_NOC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_VTS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_VTS_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_VTS_NOC),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ALIVE_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_ALIVE_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ALIVE_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_ALIVE_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_ALIVE_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_ALIVE_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLK_RCO_ALIVE_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLK_RCO_ALIVE_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLK_RCO_ALIVE_USER_BUSY, 16, 1, PLL_CON0_MUX_CLK_RCO_ALIVE_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLK_RCO_ALIVE_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLK_RCO_ALIVE_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKMUX_ALIVE_RCO_SPMI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKMUX_ALIVE_RCO_SPMI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKMUX_ALIVE_RCO_SPMI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKMUX_ALIVE_RCO_SPMI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKMUX_ALIVE_RCO_SPMI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKMUX_ALIVE_RCO_SPMI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUD_CPU_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_AUD_CPU_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_AUD_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_AUD_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUD_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_AUD_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CP_PCMC_CLK_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CP_PCMC_CLK_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CP_PCMC_CLK_USER_BUSY, 16, 1, PLL_CON0_MUX_CP_PCMC_CLK_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CP_PCMC_CLK_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CP_PCMC_CLK_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLK_AUD_RCO_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLK_AUD_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLK_AUD_RCO_USER_BUSY, 16, 1, PLL_CON0_MUX_CLK_AUD_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLK_AUD_RCO_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLK_AUD_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_AUDIF0_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_AUD_AUDIF0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_AUDIF0_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_AUD_AUDIF0_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUD_AUDIF0_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_AUD_AUDIF0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_AUDIF1_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_AUD_AUDIF1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUD_AUDIF1_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_AUD_AUDIF1_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUD_AUDIF1_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_AUD_AUDIF1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKVTS_AUD_DMIC0_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKVTS_AUD_DMIC0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKVTS_AUD_DMIC0_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKVTS_AUD_DMIC0_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKVTS_AUD_DMIC0_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKVTS_AUD_DMIC0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKVTS_AUD_DMIC1_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKVTS_AUD_DMIC1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKVTS_AUD_DMIC1_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKVTS_AUD_DMIC1_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKVTS_AUD_DMIC1_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKVTS_AUD_DMIC1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BRP_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_BRP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BRP_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_BRP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_BRP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_BRP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_CHUB_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_CHUB_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_CHUB_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_CHUB_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_CHUB_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_CHUB_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_CHUB_PERI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_CHUB_PERI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_CHUB_PERI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_CHUB_PERI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_CHUB_PERI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_CHUB_PERI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_CHUB_RCO_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_CHUB_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_CHUB_RCO_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_CHUB_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_CHUB_RCO_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_CHUB_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_CHUBVTS_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_CHUBVTS_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_CHUBVTS_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_CHUBVTS_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_CHUBVTS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_CHUBVTS_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_CHUBVTS_RCO_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_CHUBVTS_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_CHUBVTS_RCO_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_CHUBVTS_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_CHUBVTS_RCO_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_CHUBVTS_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_CMGP_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_CMGP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_CMGP_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_CMGP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_CMGP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_CMGP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_CMGP_PERI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_CMGP_PERI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_CMGP_PERI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_CMGP_PERI_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_CMGP_PERI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_CMGP_PERI_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CP_MPLL_CLK_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CP_MPLL_CLK_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CP_MPLL_CLK_USER_BUSY, 16, 1, PLL_CON0_MUX_CP_MPLL_CLK_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CP_MPLL_CLK_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CP_MPLL_CLK_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CP_MPLL_CLK_D2_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CP_MPLL_CLK_D2_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CP_MPLL_CLK_D2_USER_BUSY, 16, 1, PLL_CON0_MUX_CP_MPLL_CLK_D2_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CP_MPLL_CLK_D2_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CP_MPLL_CLK_D2_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_GLB_NOCP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_GLB_NOCP_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_GLB_NOCP_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_GLB_NOCP_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_GLB_NOCP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_GLB_NOCP_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CSIS_DCPHY_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CSIS_DCPHY_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CSIS_DCPHY_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CSIS_DCPHY_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CSIS_DCPHY_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CSIS_DCPHY_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_CSIS_RCO_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_CSIS_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_CSIS_RCO_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_CSIS_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_CSIS_RCO_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_CSIS_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CSIS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CSIS_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_CSIS_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_CSIS_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_CSIS_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_CSIS_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_CSIS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_CSIS_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CSIS_OIS_MCU_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CSIS_OIS_MCU_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CSTAT_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CSTAT_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CSTAT_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CSTAT_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CSTAT_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CSTAT_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_DBGCORE_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_DBGCORE_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_DBGCORE_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_DBGCORE_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_DBGCORE_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_DBGCORE_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DNC_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DNC_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DNC_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_DNC_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DNC_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_DNC_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_DNC_RCO_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_DNC_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_DNC_RCO_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_DNC_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_DNC_RCO_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_DNC_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_DNC_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_DNC_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_DNC_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_DNC_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_DNC_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_DNC_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPUB_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DPUB_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPUB_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_DPUB_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DPUB_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_DPUB_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPUB_DSIM_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DPUB_DSIM_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPUB_DSIM_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_DPUB_DSIM_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DPUB_DSIM_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_DPUB_DSIM_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPUF_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DPUF_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPUF_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_DPUF_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DPUF_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_DPUF_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPUF1_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DPUF1_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPUF1_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_DPUF1_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DPUF1_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_DPUF1_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DRCP_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DRCP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DRCP_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_DRCP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DRCP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_DRCP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DSP_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DSP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DSP_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_DSP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DSP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_DSP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_DSP_RCO_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_DSP_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_DSP_RCO_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_DSP_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_DSP_RCO_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_DSP_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_DSP_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_DSP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_DSP_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_DSP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_DSP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_DSP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_NOCP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G3D_NOCP_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_NOCP_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_G3D_NOCP_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G3D_NOCP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_G3D_NOCP_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G3D_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_G3D_SWITCH_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_GNPU_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_GNPU_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_GNPU_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_GNPU_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_GNPU_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_GNPU_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_GNPU_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_GNPU_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_GNPU_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_GNPU_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_GNPU_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_GNPU_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_GNPU_RCO_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_GNPU_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_GNPU_RCO_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_GNPU_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_GNPU_RCO_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_GNPU_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_DPOSC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI0_DPOSC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_DPOSC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI0_DPOSC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_DPOSC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI0_DPOSC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_USB32DRD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI0_USB32DRD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_USB32DRD_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI0_USB32DRD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_USB32DRD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI0_USB32DRD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKAUD_HSI0_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKAUD_HSI0_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKAUD_HSI0_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKAUD_HSI0_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKAUD_HSI0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKAUD_HSI0_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI1_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI1_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_LME_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_LME_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_LME_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_LME_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_LME_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_LME_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_LME_LME_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_LME_LME_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_LME_LME_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_LME_LME_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_LME_LME_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_LME_LME_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_M2M_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_M2M_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_M2M_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_M2M_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_M2M_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_M2M_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_M2M_FRC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_M2M_FRC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_M2M_FRC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_M2M_FRC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_M2M_FRC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_M2M_FRC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCSC_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MCSC_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCSC_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MCSC_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCSC_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MCSC_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MFC0_MFC0_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MFC0_MFC0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MFC0_WFD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MFC0_WFD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MFC1_MFC1_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MFC1_MFC1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MIF_NOCP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MIF_NOCP_USER),
|
|
SFR_ACCESS(PLL_CON0_CLKMUX_MIF_DDRPHY2X_MUX_SEL, 4, 2, PLL_CON0_CLKMUX_MIF_DDRPHY2X),
|
|
SFR_ACCESS(PLL_CON0_CLKMUX_MIF_DDRPHY2X_BUSY, 16, 1, PLL_CON0_CLKMUX_MIF_DDRPHY2X),
|
|
SFR_ACCESS(PLL_CON1_CLKMUX_MIF_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_CLKMUX_MIF_DDRPHY2X),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NOCL0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_NOCL0_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NOCL1A_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_NOCL1A_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NOCL1B_NOC0_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_NOCL1B_NOC0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NOCL1B_NOC0_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_NOCL1B_NOC0_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NOCL1B_NOC0_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_NOCL1B_NOC0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NOCL1B_NOC1_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_NOCL1B_NOC1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NOCL1B_NOC1_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_NOCL1B_NOC1_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NOCL1B_NOC1_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_NOCL1B_NOC1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NOCL1C_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_NOCL1C_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NOCL1C_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_NOCL1C_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NOCL1C_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_NOCL1C_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_IP0_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC0_IP0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_IP1_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC0_IP1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_IP0_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC1_IP0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_IP1_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC1_IP1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC2_IP0_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC2_IP0_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC2_IP1_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC2_IP1_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC2_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC2_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC2_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC2_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC2_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC2_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIS_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIS_GIC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIS_GIC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIS_GIC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIS_GIC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIS_GIC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIS_GIC_USER),
|
|
SFR_ACCESS(PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_MUX_SEL, 4, 2, PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D),
|
|
SFR_ACCESS(PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_BUSY, 16, 1, PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D),
|
|
SFR_ACCESS(PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_SDMA_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_SDMA_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_SDMA_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_SDMA_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_SDMA_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_SDMA_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_SDMA_RCO_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_SDMA_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_SDMA_RCO_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_SDMA_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_SDMA_RCO_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_SDMA_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_SDMA_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_SDMA_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_SDMA_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_SDMA_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_SDMA_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_SDMA_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_SSP_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_SSP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_SSP_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_SSP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_SSP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_SSP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_UFD_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_UFD_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_UFD_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_UFD_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_UFD_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_UFD_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_UFD_RCO_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_UFD_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_UFD_RCO_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_UFD_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_UFD_RCO_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_UFD_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_UFS_UFS_EMBD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_UFS_UFS_EMBD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_UFS_UFS_EMBD_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_UFS_UFS_EMBD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_UFS_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_UFS_UFS_EMBD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_UFS_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_UFS_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_UFS_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_UFS_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_UFS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_UFS_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_UFS_MMC_CARD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_UFS_MMC_CARD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_UFS_MMC_CARD_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_UFS_MMC_CARD_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_UFS_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_UFS_MMC_CARD_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_VTS_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_VTS_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_VTS_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_VTS_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_VTS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_VTS_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_VTS_DMIC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_VTS_DMIC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_VTS_RCO_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKALIVE_VTS_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKALIVE_VTS_RCO_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKALIVE_VTS_RCO_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKALIVE_VTS_RCO_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKALIVE_VTS_RCO_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_YUVP_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_YUVP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON0_MUX_CLKCMU_YUVP_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_YUVP_NOC_USER),
|
|
SFR_ACCESS(PLL_CON1_MUX_CLKCMU_YUVP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_YUVP_NOC_USER),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_BUSY, 16, 1, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_STRMUX_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_STRMUX),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_STRMUX_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_STRMUX),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_0),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_1),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_2),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_STRMUX_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_STRMUX),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_STRMUX_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_STRMUX),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DBGCORE_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_DBGCORE_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DBGCORE_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_DBGCORE_NOC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_OSCCLK_DBGCORE_BUSY, 16, 1, CLK_CON_MUX_MUX_OSCCLK_DBGCORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_OSCCLK_DBGCORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_OSCCLK_DBGCORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_FREE_OSCCLK_DBGCORE_BUSY, 16, 1, CLK_CON_MUX_MUX_FREE_OSCCLK_DBGCORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_FREE_OSCCLK_DBGCORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_FREE_OSCCLK_DBGCORE),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_STRMUX_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_DSU_STRMUX),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_DSU_STRMUX_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_DSU_STRMUX),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_STRMUX_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_G3D_STRMUX),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_STRMUX_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_G3D_STRMUX),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIS_GIC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIS_GIC),
|
|
SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIS_GIC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_UFD_NOC_DIVRATIO, 0, 3, CLK_CON_DIV_CLKALIVE_UFD_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_UFD_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKALIVE_UFD_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_UFD_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKALIVE_UFD_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_NOC_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_ALIVE_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ALIVE_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ALIVE_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_CMGP_NOC_DIVRATIO, 0, 3, CLK_CON_DIV_CLKALIVE_CMGP_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_CMGP_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKALIVE_CMGP_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_CMGP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKALIVE_CMGP_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_SPMI_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLK_ALIVE_SPMI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_SPMI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ALIVE_SPMI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_SPMI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ALIVE_SPMI),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_CMGP_PERI_DIVRATIO, 0, 3, CLK_CON_DIV_CLKALIVE_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_CMGP_PERI_BUSY, 16, 1, CLK_CON_DIV_CLKALIVE_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKALIVE_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_CHUB_PERI_DIVRATIO, 0, 3, CLK_CON_DIV_CLKALIVE_CHUB_PERI),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_CHUB_PERI_BUSY, 16, 1, CLK_CON_DIV_CLKALIVE_CHUB_PERI),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_CHUB_PERI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKALIVE_CHUB_PERI),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_DBGCORE_NOC_DIVRATIO, 0, 3, CLK_CON_DIV_CLKALIVE_DBGCORE_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_DBGCORE_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKALIVE_DBGCORE_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_DBGCORE_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKALIVE_DBGCORE_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_DNC_NOC_DIVRATIO, 0, 3, CLK_CON_DIV_CLKALIVE_DNC_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_DNC_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKALIVE_DNC_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKALIVE_DNC_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_GNPU_NOC_DIVRATIO, 0, 3, CLK_CON_DIV_CLKALIVE_GNPU_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_GNPU_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKALIVE_GNPU_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKALIVE_GNPU_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_SDMA_NOC_DIVRATIO, 0, 3, CLK_CON_DIV_CLKALIVE_SDMA_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_SDMA_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKALIVE_SDMA_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKALIVE_SDMA_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC_DIVRATIO, 0, 3, CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_CSIS_NOC_DIVRATIO, 0, 3, CLK_CON_DIV_CLKALIVE_CSIS_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_CSIS_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKALIVE_CSIS_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKALIVE_CSIS_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_DSP_NOC_DIVRATIO, 0, 3, CLK_CON_DIV_CLKALIVE_DSP_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_DSP_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKALIVE_DSP_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKALIVE_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKALIVE_DSP_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DSIF_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DSIF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_DSIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF0_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF1_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF2_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF3_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF3_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_AUD_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_NOCP_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_AUD_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CNT_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_AUD_CNT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CNT_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CNT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CNT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CNT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF4_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF4_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF5_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF5_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF5),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF6_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF6_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_UAIF6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_UAIF6),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_HSI0_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKAUD_HSI0_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_HSI0_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKAUD_HSI0_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKAUD_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKAUD_HSI0_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_PCMC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_PCMC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_PCMC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_PCMC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_AUDIF_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_AUDIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_AUDIF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_AUDIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_AUDIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_CORE_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_CORE_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_CORE),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_AUD_MCLK_DIVRATIO, 0, 4, CLK_CON_DIV_CLK_AUD_MCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_AUD_MCLK_BUSY, 16, 1, CLK_CON_DIV_CLK_AUD_MCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_AUD_MCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_AUD_MCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BRP_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_BRP_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BRP_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_BRP_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BRP_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_BRP_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_BRP_ADD_CH_CLK_DIVRATIO, 0, 5, CLK_CON_DIV_CLK_BRP_ADD_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_BRP_ADD_CH_CLK_BUSY, 16, 1, CLK_CON_DIV_CLK_BRP_ADD_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_BRP_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_BRP_ADD_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_NOC_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CHUB_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUB_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUB_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI0_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CHUB_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI1_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CHUB_USI1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI3_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CHUB_USI3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI3_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUB_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI2_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CHUB_USI2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_USI2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUB_USI2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_SPI_MS_CTRL_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CHUB_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_SPI_MS_CTRL_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUB_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUB_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C0_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C1_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUBVTS_NOC_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CHUBVTS_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUBVTS_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUBVTS_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUBVTS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUBVTS_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUBVTS_DMAILBOX_CCLK_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLK_CHUBVTS_DMAILBOX_CCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUBVTS_DMAILBOX_CCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CHUBVTS_DMAILBOX_CCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CHUBVTS_DMAILBOX_CCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CHUBVTS_DMAILBOX_CCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI4_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI4_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI1_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI0_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI2_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI3_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI3_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI5_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI5),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI5_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI5),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI5),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI6_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_USI6),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI6_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI6),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_USI6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_USI6),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ALIVE_NOC_DIVRATIO, 0, 2, CLK_CON_DIV_CLKCMU_ALIVE_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ALIVE_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_ALIVE_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_ALIVE_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_ALIVE_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_DPOSC_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_HSI0_DPOSC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_DPOSC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI0_DPOSC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_DPOSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI0_DPOSC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC0_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC0_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC0_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIS_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIS_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIS_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIS_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIS_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC0_MFC0_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MFC0_MFC0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC0_MFC0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MFC0_MFC0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MFC0_MFC0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BRP_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_BRP_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BRP_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_BRP_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_BRP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_BRP_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_YUVP_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_YUVP_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_YUVP_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_YUVP_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_YUVP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_YUVP_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC0_WFD_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MFC0_WFD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC0_WFD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MFC0_WFD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC0_WFD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MFC0_WFD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_NOCP_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MIF_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_NOCP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MIF_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MIF_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_IP0_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC0_IP0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_IP0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC0_IP0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_IP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC0_IP0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_IP0_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_IP0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_IP0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_IP0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_IP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_IP0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUF_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_DPUF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_DPUF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_DPUF),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_HSI0_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI0_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI0_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CMU_BOOST),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CSIS_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CSIS_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CSIS_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_HSI1_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI1_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI1_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUB_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_DPUB),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUB_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_DPUB),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPUB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_DPUB),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC1_MFC1_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MFC1_MFC1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC1_MFC1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MFC1_MFC1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MFC1_MFC1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_LME_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_LME_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_LME_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_LME_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_LME_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_LME_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_USB32DRD_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_HSI0_USB32DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_USB32DRD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI0_USB32DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_USB32DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI0_USB32DRD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_DPGTC_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_HSI0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_DPGTC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_AUD_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_AUD_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUD_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_AUD_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_DCPHY_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CSIS_DCPHY),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_DCPHY_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CSIS_DCPHY),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_DCPHY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CSIS_DCPHY),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_CP_SHARED1_CLK_DIVRATIO, 0, 3, CLK_CON_DIV_CP_SHARED1_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CP_SHARED1_CLK_BUSY, 16, 1, CLK_CON_DIV_CP_SHARED1_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CP_SHARED1_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CP_SHARED1_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_IP1_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC0_IP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_IP1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC0_IP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_IP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC0_IP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_IP1_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_IP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_IP1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_IP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_IP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_IP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_SSP_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_SSP_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_SSP_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_SSP_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_SSP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_SSP_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC2_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC2_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC2_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC2_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC2_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC2_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC2_IP0_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC2_IP0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC2_IP0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC2_IP0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC2_IP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC2_IP0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC2_IP1_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC2_IP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC2_IP1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC2_IP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC2_IP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC2_IP1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_NOCP_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CPUCL0_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_NOCP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL0_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL0_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_G3D_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_NOCP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_G3D_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_G3D_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSTAT_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CSTAT_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSTAT_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CSTAT_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSTAT_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CSTAT_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DPUB_DSIM_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DPUB_DSIM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DPUB_DSIM_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DPUB_DSIM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_DPUB_DSIM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DPUB_DSIM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VTS_DMIC_DIVRATIO, 0, 6, CLK_CON_DIV_CLKCMU_VTS_DMIC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VTS_DMIC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_VTS_DMIC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_VTS_DMIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_VTS_DMIC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM_DIVRATIO, 0, 6, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM_DIVRATIO, 0, 6, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIS_GIC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIS_GIC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIS_GIC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIS_GIC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIS_GIC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_NOCL1B_NOC1_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_NOCL1B_NOC1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_NOCL1B_NOC1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_NOCL1B_NOC1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_NOCL1B_NOC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_NOCL1B_NOC1),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_LME_LME_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_LME_LME),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_LME_LME_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_LME_LME),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_LME_LME_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_LME_LME),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_UFS_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_UFS_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_UFS_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_UFS_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_CLKCMU_UFS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_UFS_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_AUD_CPU),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_DIVRATIO, 0, 6, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_DIVRATIO, 0, 6, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_DNC_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_DNC_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_DNC_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_DSP_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_DSP_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_DSP_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_M2M_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_M2M_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_M2M_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_M2M_FRC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_M2M_FRC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_M2M_FRC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CP_HISPEEDY_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CP_SHARED2_CLK_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CP_SHARED2_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CP_SHARED2_CLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CP_SHARED2_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CP_SHARED2_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CP_SHARED0_CLK_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CP_SHARED0_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CP_SHARED0_CLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CP_SHARED0_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CP_SHARED0_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK_DIVRATIO, 0, 5, CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK_BUSY, 16, 1, CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL0_DDD_DIVRATIO, 0, 2, CLK_CON_DIV_CLK_CPUCL0_DDD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL0_DDD_BUSY, 16, 1, CLK_CON_DIV_CLK_CPUCL0_DDD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL0_DDD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_CPUCL0_DDD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL1_ADD_CH_CLK_DIVRATIO, 0, 5, CLK_CON_DIV_CLK_CPUCL1_ADD_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL1_ADD_CH_CLK_BUSY, 16, 1, CLK_CON_DIV_CLK_CPUCL1_ADD_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL1_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_CPUCL1_ADD_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL1_DDD_0_DIVRATIO, 0, 2, CLK_CON_DIV_CLK_CPUCL1_DDD_0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL1_DDD_0_BUSY, 16, 1, CLK_CON_DIV_CLK_CPUCL1_DDD_0),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL1_DDD_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_CPUCL1_DDD_0),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_1_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_1),
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|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL1_DDD_1_DIVRATIO, 0, 2, CLK_CON_DIV_CLK_CPUCL1_DDD_1),
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|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL1_DDD_1_BUSY, 16, 1, CLK_CON_DIV_CLK_CPUCL1_DDD_1),
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|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL1_DDD_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_CPUCL1_DDD_1),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_2_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_2),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_2),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_2),
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|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL1_DDD_2_DIVRATIO, 0, 2, CLK_CON_DIV_CLK_CPUCL1_DDD_2),
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|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL1_DDD_2_BUSY, 16, 1, CLK_CON_DIV_CLK_CPUCL1_DDD_2),
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|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL1_DDD_2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_CPUCL1_DDD_2),
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|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL2_ADD_CH_CLK_DIVRATIO, 0, 5, CLK_CON_DIV_CLK_CPUCL2_ADD_CH_CLK),
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SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL2_ADD_CH_CLK_BUSY, 16, 1, CLK_CON_DIV_CLK_CPUCL2_ADD_CH_CLK),
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SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL2_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_CPUCL2_ADD_CH_CLK),
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|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL2_DDD_DIVRATIO, 0, 2, CLK_CON_DIV_CLK_CPUCL2_DDD),
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|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL2_DDD_BUSY, 16, 1, CLK_CON_DIV_CLK_CPUCL2_DDD),
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|
SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL2_DDD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_CPUCL2_DDD),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CSIS_NOCP),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CSIS_NOCP),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CSIS_NOCP),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_DCPHY_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_CSIS_DCPHY),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_DCPHY_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CSIS_DCPHY),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_DCPHY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CSIS_DCPHY),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSTAT_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CSTAT_NOCP),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSTAT_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CSTAT_NOCP),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSTAT_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CSTAT_NOCP),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DNC_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DNC_NOCP),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DNC_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DNC_NOCP),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DNC_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DNC_NOCP),
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|
SFR_ACCESS(CLK_CON_DIV_CLK_DNC_ADD_CH_CLK_DIVRATIO, 0, 5, CLK_CON_DIV_CLK_DNC_ADD_CH_CLK),
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|
SFR_ACCESS(CLK_CON_DIV_CLK_DNC_ADD_CH_CLK_BUSY, 16, 1, CLK_CON_DIV_CLK_DNC_ADD_CH_CLK),
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|
SFR_ACCESS(CLK_CON_DIV_CLK_DNC_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_DNC_ADD_CH_CLK),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPUB_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DPUB_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPUB_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DPUB_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPUB_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DPUB_NOCP),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPUF_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DPUF_NOCP),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPUF_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DPUF_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPUF_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DPUF_NOCP),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPUF1_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DPUF1_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPUF1_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DPUF1_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPUF1_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DPUF1_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DRCP_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DRCP_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DRCP_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DRCP_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DRCP_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DRCP_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSP_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DSP_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSP_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DSP_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSP_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DSP_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_DSU_DDD_DIVRATIO, 0, 2, CLK_CON_DIV_CLK_DSU_DDD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_DSU_DDD_BUSY, 16, 1, CLK_CON_DIV_CLK_DSU_DDD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_DSU_DDD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_DSU_DDD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_DSU_STR_DEM_CLK_DIVRATIO, 0, 5, CLK_CON_DIV_CLK_DSU_STR_DEM_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_DSU_STR_DEM_CLK_BUSY, 16, 1, CLK_CON_DIV_CLK_DSU_STR_DEM_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_DSU_STR_DEM_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_DSU_STR_DEM_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_ACPCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER_ACPCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_ACPCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_ACPCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_ACPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_ACPCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_MPCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER_MPCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_MPCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_MPCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_MPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_MPCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_MPACTCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER_MPACTCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_MPACTCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_MPACTCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER_MPACTCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER_MPACTCLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_DIVRATIO, 0, 5, CLK_CON_DIV_CLK_G3D_ADD_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_BUSY, 16, 1, CLK_CON_DIV_CLK_G3D_ADD_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_G3D_ADD_CH_CLK),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_G3D_DDD_DIVRATIO, 0, 2, CLK_CON_DIV_CLK_G3D_DDD),
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|
SFR_ACCESS(CLK_CON_DIV_CLK_G3D_DDD_BUSY, 16, 1, CLK_CON_DIV_CLK_G3D_DDD),
|
|
SFR_ACCESS(CLK_CON_DIV_CLK_G3D_DDD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_G3D_DDD),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GNPU_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_GNPU_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GNPU_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_GNPU_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GNPU_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_GNPU_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI0_EUSB_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_HSI0_EUSB),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI0_EUSB_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_HSI0_EUSB),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI0_EUSB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_HSI0_EUSB),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_LME_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_LME_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_LME_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_LME_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_LME_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_LME_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_M2M_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_M2M_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_M2M_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_M2M_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_M2M_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_M2M_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MCSC_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MCSC_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MCSC_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC0_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MFC0_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC0_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MFC0_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC0_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MFC0_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC1_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MFC1_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC1_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MFC1_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC1_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MFC1_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1C_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_NOCL1C_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1C_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NOCL1C_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1C_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NOCL1C_NOCP),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI04_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC0_USI04),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI04_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI04),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI04_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI04),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI07_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC1_USI07),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI07_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI07),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI07_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI07),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI08_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC1_USI08),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI08_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI08),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI08_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI08),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI09_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC1_USI09),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI09_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI09),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI09_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI09),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI10_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC1_USI10),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI10_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI10),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI10_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI10),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC2_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC2_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC2_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI00_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC2_USI00),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI00_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI00),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI00_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI00),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI01_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC2_USI01),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI01_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI01),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI01_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI01),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI02_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC2_USI02),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI02_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI02),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI02_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI02),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI03_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC2_USI03),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI03_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI03),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI03_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI03),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI05_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC2_USI05),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI05_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI05),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI05_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI05),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI06_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC2_USI06),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI06_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI06),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI06_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI06),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI11_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_PERIC2_USI11),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI11_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI11),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI11_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI11),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SDMA_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_SDMA_NOCP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SDMA_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_SDMA_NOCP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SDMA_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_SDMA_NOCP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SSP_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_SSP_NOCP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SSP_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_SSP_NOCP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SSP_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_SSP_NOCP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_NOC_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_VTS_NOC),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_NOC),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_NOC),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_CPU_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_VTS_CPU),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_CPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_CPU),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_CPU),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_YUVP_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_YUVP_NOCP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_YUVP_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_YUVP_NOCP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_YUVP_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_YUVP_NOCP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BRP_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_BRP_NOC),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BRP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_BRP_NOC),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CORE_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CORE),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CORE),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_0),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_0),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL2_CORE_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL2_CORE),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL2_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL2_CORE),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DNC_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DNC_NOC),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DNC_NOC),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DRCP_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DRCP_NOC),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DRCP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DRCP_NOC),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSP_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DSP_NOC),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DSP_NOC),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DSU_CLUSTER),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DSU_CLUSTER),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_CORE_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G3D_CORE),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G3D_CORE),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GNPU_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_GNPU_NOC),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_GNPU_NOC),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MCSC_NOC),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MCSC_NOC),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_MCSC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MCSC_MCSC),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MCSC_MCSC),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SDMA_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_SDMA_NOC),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_SDMA_NOC),
|
|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_YUVP_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_YUVP_NOC),
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|
SFR_ACCESS(CLK_CON_DIV_DIV_CLK_YUVP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_YUVP_NOC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_UFD_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKALIVE_UFD_NOC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_UFD_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKALIVE_UFD_NOC),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_UFD_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKALIVE_UFD_NOC),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK),
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|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_CMGP_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKALIVE_CMGP_NOC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_CMGP_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKALIVE_CMGP_NOC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_CMGP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKALIVE_CMGP_NOC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_CMGP_PERI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKALIVE_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_CMGP_PERI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKALIVE_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKALIVE_CMGP_PERI),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK),
|
|
SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_CHUB_PERI_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKALIVE_CHUB_PERI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_CHUB_PERI_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKALIVE_CHUB_PERI),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_CHUB_PERI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKALIVE_CHUB_PERI),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_DBGCORE_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKALIVE_DBGCORE_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_DBGCORE_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKALIVE_DBGCORE_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_DBGCORE_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKALIVE_DBGCORE_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_DNC_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKALIVE_DNC_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_DNC_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKALIVE_DNC_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKALIVE_DNC_NOC),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_GNPU_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKALIVE_GNPU_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_GNPU_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKALIVE_GNPU_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKALIVE_GNPU_NOC),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_GNSS_NOC_CG_VAL, 21, 1, CLK_CON_GAT_CLKALIVE_GNSS_NOC),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_GNSS_NOC_MANUAL, 20, 1, CLK_CON_GAT_CLKALIVE_GNSS_NOC),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_GNSS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKALIVE_GNSS_NOC),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_UFD_RCO_CG_VAL, 21, 1, CLK_CON_GAT_CLKALIVE_UFD_RCO),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_UFD_RCO_MANUAL, 20, 1, CLK_CON_GAT_CLKALIVE_UFD_RCO),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_UFD_RCO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKALIVE_UFD_RCO),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_DNC_RCO_CG_VAL, 21, 1, CLK_CON_GAT_CLKALIVE_DNC_RCO),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_DNC_RCO_MANUAL, 20, 1, CLK_CON_GAT_CLKALIVE_DNC_RCO),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_DNC_RCO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKALIVE_DNC_RCO),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_GNPU_RCO_CG_VAL, 21, 1, CLK_CON_GAT_CLKALIVE_GNPU_RCO),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_GNPU_RCO_MANUAL, 20, 1, CLK_CON_GAT_CLKALIVE_GNPU_RCO),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_GNPU_RCO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKALIVE_GNPU_RCO),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_SDMA_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKALIVE_SDMA_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_SDMA_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKALIVE_SDMA_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKALIVE_SDMA_NOC),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_SDMA_RCO_CG_VAL, 21, 1, CLK_CON_GAT_CLKALIVE_SDMA_RCO),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_SDMA_RCO_MANUAL, 20, 1, CLK_CON_GAT_CLKALIVE_SDMA_RCO),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_SDMA_RCO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKALIVE_SDMA_RCO),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_CHUBVTS_RCO_CG_VAL, 21, 1, CLK_CON_GAT_CLKALIVE_CHUBVTS_RCO),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_CHUBVTS_RCO_MANUAL, 20, 1, CLK_CON_GAT_CLKALIVE_CHUBVTS_RCO),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_CHUBVTS_RCO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKALIVE_CHUBVTS_RCO),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_CHUBVTS_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKALIVE_CHUBVTS_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_CHUBVTS_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKALIVE_CHUBVTS_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_CHUBVTS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKALIVE_CHUBVTS_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_CSIS_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKALIVE_CSIS_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_CSIS_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKALIVE_CSIS_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKALIVE_CSIS_NOC),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_CSIS_RCO_CG_VAL, 21, 1, CLK_CON_GAT_CLKALIVE_CSIS_RCO),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_CSIS_RCO_MANUAL, 20, 1, CLK_CON_GAT_CLKALIVE_CSIS_RCO),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_CSIS_RCO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKALIVE_CSIS_RCO),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_DSP_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKALIVE_DSP_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_DSP_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKALIVE_DSP_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKALIVE_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKALIVE_DSP_NOC),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_DSP_RCO_CG_VAL, 21, 1, CLK_CON_GAT_CLKALIVE_DSP_RCO),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_DSP_RCO_MANUAL, 20, 1, CLK_CON_GAT_CLKALIVE_DSP_RCO),
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SFR_ACCESS(CLK_CON_GAT_CLKALIVE_DSP_RCO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKALIVE_DSP_RCO),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_AD_APB_CSIS_WDMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_AD_APB_CSIS_WDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_AD_APB_CSIS_WDMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_AD_APB_CSIS_WDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_AD_APB_CSIS_WDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_AD_APB_CSIS_WDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_EBUF_BNS_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_EBUF_BNS),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_EBUF_BNS_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_EBUF_BNS),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_EBUF_BNS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_EBUF_BNS),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF_CSISBRP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF_CSISBRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF_CSISBRP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF_CSISBRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF_CSISBRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF_CSISBRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF0_BRPCSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF0_BRPCSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF0_BRPCSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF0_BRPCSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF0_BRPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF0_BRPCSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF1_BRPCSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF1_BRPCSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF1_BRPCSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF1_BRPCSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF1_BRPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF1_BRPCSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SIU_G_PPMU_CSIS_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SIU_G_PPMU_CSIS_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SIU_G_PPMU_CSIS_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SIU_G_PPMU_CSIS_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SIU_G_PPMU_CSIS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SIU_G_PPMU_CSIS_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AST_SI_G_PPMU_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AST_SI_G_PPMU_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AST_SI_G_PPMU_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AST_SI_G_PPMU_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AST_SI_G_PPMU_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AST_SI_G_PPMU_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_P0_CSIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_P0_CSIS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_P0_CSIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_P0_CSIS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_P0_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_P0_CSIS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_SI_LP_CSISPERIC2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_SI_LP_CSISPERIC2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_SI_LP_CSISPERIC2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_SI_LP_CSISPERIC2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_SI_LP_CSISPERIC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_SI_LP_CSISPERIC2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_MI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_MI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_MI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_MI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_MI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_MI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_ALLCSIS_CMU_ALLCSIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_ALLCSIS_CMU_ALLCSIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_ALLCSIS_CMU_ALLCSIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_ALLCSIS_CMU_ALLCSIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_ALLCSIS_CMU_ALLCSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_ALLCSIS_CMU_ALLCSIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_BLK_CSIS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_BLK_CSIS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_BLK_CSIS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_BLK_CSIS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_BLK_CSIS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_BLK_CSIS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_BAAW_D_AUDCHUBVTS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_BAAW_D_AUDCHUBVTS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_BAAW_D_AUDCHUBVTS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_BAAW_D_AUDCHUBVTS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_BAAW_D_AUDCHUBVTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_BAAW_D_AUDCHUBVTS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_LD_HSI0AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_LD_HSI0AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_LD_HSI0AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_LD_HSI0AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_LD_HSI0AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_LD_HSI0AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_LH_QDI_SI_D_AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_LH_QDI_SI_D_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_LH_QDI_SI_D_AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_LH_QDI_SI_D_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_LH_QDI_SI_D_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_LH_QDI_SI_D_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LD_AUDHSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LD_AUDHSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LD_AUDHSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LD_AUDHSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LD_AUDHSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LD_AUDHSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKAUD_HSI0_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKAUD_HSI0_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKAUD_HSI0_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKAUD_HSI0_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKAUD_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKAUD_HSI0_NOC),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_VGEN_LITE_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_VGEN_LITE_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_VGEN_LITE_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_VGEN_LITE_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_VGEN_LITE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_VGEN_LITE_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_CCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_CCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_CCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_CCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_CCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_BCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_BCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_BCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_BCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_BCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_BCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AST_SI_G_PPMU_AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AST_SI_G_PPMU_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AST_SI_G_PPMU_AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AST_SI_G_PPMU_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AST_SI_G_PPMU_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AST_SI_G_PPMU_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_BLK_AUD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_BLK_AUD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_BLK_AUD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_BLK_AUD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_BLK_AUD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_BLK_AUD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_SI_PERI_ASB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_SI_PERI_ASB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_SI_PERI_ASB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_SI_PERI_ASB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_SI_PERI_ASB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_SI_PERI_ASB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_MI_PERI_ASB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_MI_PERI_ASB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_MI_PERI_ASB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_MI_PERI_ASB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_MI_PERI_ASB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_MI_PERI_ASB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ACP_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ACP),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ACP_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ACP),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ACP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ACP),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ASB_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ASB),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ASB_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ASB),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ASB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ASB),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_CCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_CCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_CCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_CCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_CCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BRP_CMU_BRP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BRP_CMU_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BRP_CMU_BRP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BRP_CMU_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BRP_CMU_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BRP_CMU_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_BYRP_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_BYRP_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_BYRP_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_BYRP_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_BYRP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_BYRP_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_D_TZPC_BRP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_D_TZPC_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_D_TZPC_BRP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_D_TZPC_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_D_TZPC_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_D_TZPC_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D0_BRP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D0_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D0_BRP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D0_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D0_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D0_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSREG_BRP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSREG_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSREG_BRP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSREG_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSREG_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSREG_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D0_BRP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D0_BRP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D0_BRP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D0_BRP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D0_BRP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D0_BRP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AXI_MI_P_BRP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AXI_MI_P_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AXI_MI_P_BRP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AXI_MI_P_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AXI_MI_P_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AXI_MI_P_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_ZSL_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_ZSL),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_ZSL_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_ZSL),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_ZSL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_ZSL),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_BYR_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_BYR),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_BYR_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_BYR),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_BYR_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_BYR),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_BYRP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_BYRP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_BYRP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_BYRP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_BYRP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_BYRP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AST_SI_G_PPMU_BRP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AST_SI_G_PPMU_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AST_SI_G_PPMU_BRP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AST_SI_G_PPMU_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AST_SI_G_PPMU_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AST_SI_G_PPMU_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_RGBP_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_RGBP_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_RGBP_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_RGBP_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_RGBP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_RGBP_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D1_BRP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D1_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D1_BRP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D1_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D1_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D1_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D2_BRP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D2_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D2_BRP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D2_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D2_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D2_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D1_BRP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D1_BRP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D1_BRP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D1_BRP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D1_BRP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D1_BRP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D2_BRP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D2_BRP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D2_BRP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D2_BRP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D2_BRP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D2_BRP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_RGBP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_RGBP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_RGBP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_RGBP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_RGBP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_RGBP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF0_BRPCSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF0_BRPCSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF0_BRPCSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF0_BRPCSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF0_BRPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF0_BRPCSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_MI_OTF_CSISBRP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_MI_OTF_CSISBRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_MI_OTF_CSISBRP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_MI_OTF_CSISBRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_MI_OTF_CSISBRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_MI_OTF_CSISBRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF1_BRPCSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF1_BRPCSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF1_BRPCSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF1_BRPCSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF1_BRPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF1_BRPCSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF_BRPMCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF_BRPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF_BRPMCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF_BRPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF_BRPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF_BRPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_L_SIU_BRP_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_L_SIU_BRP_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_L_SIU_BRP_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_L_SIU_BRP_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_L_SIU_BRP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_L_SIU_BRP_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BLK_BRP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BLK_BRP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BLK_BRP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BLK_BRP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BLK_BRP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BLK_BRP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_POWERIP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_POWERIP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CH_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CH_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_POWERIP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_POWERIP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_TIMER_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_TIMER_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_TIMER_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_TIMER_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_TIMER_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_TIMER_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_MI_IP_VC2CHUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_MI_IP_VC2CHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_MI_IP_VC2CHUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_MI_IP_VC2CHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_MI_IP_VC2CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_MI_IP_VC2CHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_SI_ID_CHUB2VC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_SI_ID_CHUB2VC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_SI_ID_CHUB2VC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_SI_ID_CHUB2VC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_SI_ID_CHUB2VC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_SI_ID_CHUB2VC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI3_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI3_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI3_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI3_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI3_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_ASYNCINTERRUPT_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_ASYNCINTERRUPT_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_ASYNCINTERRUPT_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_ASYNCINTERRUPT_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_ASYNCINTERRUPT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_ASYNCINTERRUPT_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_DNC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_DNC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_MULTI_SLV_Q_CTRL_CHUB_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_MULTI_SLV_Q_CTRL_CHUB_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_MULTI_SLV_Q_CTRL_CHUB_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_MULTI_SLV_Q_CTRL_CHUB_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_MULTI_SLV_Q_CTRL_CHUB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_MULTI_SLV_Q_CTRL_CHUB_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_MS_CTRL_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_MS_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_MS_CTRL_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_MS_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_MS_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_MS_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_AXI2AHB_CHUB_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_AXI2AHB_CHUB_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_AXI2AHB_CHUB_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_AXI2AHB_CHUB_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_AXI2AHB_CHUB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_AXI2AHB_CHUB_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_ABOX_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_ABOX_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_ABOX_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_ABOX_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_ABOX_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2VTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2VTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2VTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2CHUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2CHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2CHUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2CHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2CHUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SWEEPER_LD_CHUBVTS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SWEEPER_LD_CHUBVTS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SWEEPER_LD_CHUBVTS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SWEEPER_LD_CHUBVTS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SWEEPER_LD_CHUBVTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SWEEPER_LD_CHUBVTS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_ALIVECHUBVTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_ALIVECHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_ALIVECHUBVTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_ALIVECHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_ALIVECHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_ALIVECHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_CCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_CCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_CCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_CCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_CCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_VTS2VC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_VTS2VC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_VTS2VC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_VTS2VC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_VTS2VC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_VTS2VC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_PDMA_CHUBVTS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_PDMA_CHUBVTS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_PDMA_CHUBVTS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_PDMA_CHUBVTS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_PDMA_CHUBVTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_PDMA_CHUBVTS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_CHUB2VC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_CHUB2VC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_CHUB2VC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_CHUB2VC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_CHUB2VC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_CHUB2VC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APBIF_UPMU_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APBIF_UPMU_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APBIF_UPMU_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APBIF_UPMU_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APBIF_UPMU_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APBIF_UPMU_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_UPMU_CHUB_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_UPMU_CHUB_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_UPMU_CHUB_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_UPMU_CHUB_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_UPMU_CHUB_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_UPMU_CHUB_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_RSTNSYNCH_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_RSTNSYNCH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_RSTNSYNCH_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_RSTNSYNCH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_RSTNSYNCH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_RSTNSYNCH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_SI_LD_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_SI_LD_CHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_SI_LD_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_SI_LD_CHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_SI_LD_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_SI_LD_CHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_DNCCHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_DNCCHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_DNCCHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_PDMA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_PDMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_PDMA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_PDMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_PDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_PDMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_DMAILBOX_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_DMAILBOX_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_DMAILBOX_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_DMAILBOX_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_DMAILBOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_DMAILBOX_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BLK_CHUBVTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BLK_CHUBVTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BLK_CHUBVTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BLK_CHUBVTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BLK_CHUBVTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BLK_CHUBVTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_DMAILBOX_CCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_DMAILBOX_CCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_DMAILBOX_CCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_DMAILBOX_CCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_DMAILBOX_CCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_DMAILBOX_CCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_LD_CHUBVTS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_LD_CHUBVTS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_LD_CHUBVTS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_LD_CHUBVTS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_LD_CHUBVTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_LD_CHUBVTS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC),
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SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF01_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_MIF01_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF01_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_MIF01_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF01_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_MIF01_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BRP_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_BRP_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BRP_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_BRP_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BRP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_BRP_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUF_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DPUF),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUF_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DPUF),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DPUF),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUB_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DPUB),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUB_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DPUB),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DPUB),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_LME_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_LME_NOC),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_LME_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_LME_NOC),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_LME_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_LME_NOC),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_NOC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_NOC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_NOC),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED1_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CP_SHARED1_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED1_CLK_MANUAL, 20, 1, CLK_CON_GAT_GATE_CP_SHARED1_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED1_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CP_SHARED1_CLK),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1),
|
|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SSP_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_SSP_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SSP_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_SSP_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SSP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_SSP_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1),
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SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF23_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_MIF23_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF23_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_MIF23_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF23_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_MIF23_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_LME_LME_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_LME_LME),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_LME_LME_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_LME_LME),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_LME_LME_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_LME_LME),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM),
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|
SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_UFS_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_UFS_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_UFS_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_UFS_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_UFS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_UFS_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DNC_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DNC_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DNC_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DSP_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DSP_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DSP_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_M2M_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_M2M_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_M2M_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_M2M_FRC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_M2M_FRC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_M2M_FRC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC),
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SFR_ACCESS(CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CP_HISPEEDY_CLK),
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SFR_ACCESS(CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_MANUAL, 20, 1, CLK_CON_GAT_GATE_CP_HISPEEDY_CLK),
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SFR_ACCESS(CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CP_HISPEEDY_CLK),
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SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CP_SHARED2_CLK),
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SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED2_CLK_MANUAL, 20, 1, CLK_CON_GAT_GATE_CP_SHARED2_CLK),
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SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CP_SHARED2_CLK),
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SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED0_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CP_SHARED0_CLK),
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SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED0_CLK_MANUAL, 20, 1, CLK_CON_GAT_GATE_CP_SHARED0_CLK),
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SFR_ACCESS(CLK_CON_GAT_GATE_CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CP_SHARED0_CLK),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD),
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SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CPUCL0_CPM_CG_VAL, 21, 1, CLK_CON_GAT_CPUCL0_CPM),
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SFR_ACCESS(CLK_CON_GAT_CPUCL0_CPM_MANUAL, 20, 1, CLK_CON_GAT_CPUCL0_CPM),
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SFR_ACCESS(CLK_CON_GAT_CPUCL0_CPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CPUCL0_CPM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX0CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX0CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX0CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX0CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX0CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX0CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX1CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX1CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX1CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX1CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX1CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX1CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_STR_CPUCL0_0_IPCLKPORT_DEM_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_STR_CPUCL0_0_IPCLKPORT_DEM_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_STR_CPUCL0_0_IPCLKPORT_DEM_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_STR_CPUCL0_0_IPCLKPORT_DEM_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_STR_CPUCL0_0_IPCLKPORT_DEM_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_STR_CPUCL0_0_IPCLKPORT_DEM_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_HTU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_HTU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_HTU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_HTU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_HTU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_ETR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_ETR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_ETR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_ETR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_ETR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_STM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_STM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_STM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_STM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_STM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_STM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_ETR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_ETR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_ETR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_ETR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_ETR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_STM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_STM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_STM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_STM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_STM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_STM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_PMU_PCSM_PM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_PMU_PCSM_PM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_PMU_PCSM_PM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_PMU_PCSM_PM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_PMU_PCSM_PM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_PMU_PCSM_PM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_0_IPCLKPORT_PCLK_S0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_0_IPCLKPORT_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_0_IPCLKPORT_PCLK_S0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_0_IPCLKPORT_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_0_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_0_IPCLKPORT_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_1_IPCLKPORT_PCLK_S0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_1_IPCLKPORT_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_1_IPCLKPORT_PCLK_S0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_1_IPCLKPORT_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_1_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_1_IPCLKPORT_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCDSU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCDSU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCDSU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCDSU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCDSU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCDSU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_DDCG3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_DDCG3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_DDCG3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_DDCG3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_DDCG3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_DDCG3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCLIT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCLIT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCLIT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCLIT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCLIT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCLIT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCBIG_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCBIG_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCBIG_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCBIG_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCBIG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCBIG_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CFM_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CFM_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CFM_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CFM_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CFM_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CFM_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_OTP_DESERIAL_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_OTP_DESERIAL_SECJTAG_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_OTP_DESERIAL_SECJTAG_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_OTP_DESERIAL_SECJTAG_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_OTP_DESERIAL_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_OTP_DESERIAL_SECJTAG_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BLK_CPUCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BLK_CPUCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BLK_CPUCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BLK_CPUCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BLK_CPUCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BLK_CPUCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_HTU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_HTU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_HTU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_HTU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_HTU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CPUCL1_CPM0_CG_VAL, 21, 1, CLK_CON_GAT_CPUCL1_CPM0),
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SFR_ACCESS(CLK_CON_GAT_CPUCL1_CPM0_MANUAL, 20, 1, CLK_CON_GAT_CPUCL1_CPM0),
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SFR_ACCESS(CLK_CON_GAT_CPUCL1_CPM0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CPUCL1_CPM0),
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SFR_ACCESS(CLK_CON_GAT_CPUCL1_CPM1_CG_VAL, 21, 1, CLK_CON_GAT_CPUCL1_CPM1),
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SFR_ACCESS(CLK_CON_GAT_CPUCL1_CPM1_MANUAL, 20, 1, CLK_CON_GAT_CPUCL1_CPM1),
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SFR_ACCESS(CLK_CON_GAT_CPUCL1_CPM1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CPUCL1_CPM1),
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SFR_ACCESS(CLK_CON_GAT_CPUCL1_CPM2_CG_VAL, 21, 1, CLK_CON_GAT_CPUCL1_CPM2),
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SFR_ACCESS(CLK_CON_GAT_CPUCL1_CPM2_MANUAL, 20, 1, CLK_CON_GAT_CPUCL1_CPM2),
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SFR_ACCESS(CLK_CON_GAT_CPUCL1_CPM2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CPUCL1_CPM2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_STR_CPUCL0_1_IPCLKPORT_DEM_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_STR_CPUCL0_1_IPCLKPORT_DEM_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_STR_CPUCL0_1_IPCLKPORT_DEM_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_STR_CPUCL0_1_IPCLKPORT_DEM_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_STR_CPUCL0_1_IPCLKPORT_DEM_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_STR_CPUCL0_1_IPCLKPORT_DEM_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_HTU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_HTU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_HTU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_HTU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_HTU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CPUCL2_CPM_CG_VAL, 21, 1, CLK_CON_GAT_CPUCL2_CPM),
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SFR_ACCESS(CLK_CON_GAT_CPUCL2_CPM_MANUAL, 20, 1, CLK_CON_GAT_CPUCL2_CPM),
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SFR_ACCESS(CLK_CON_GAT_CPUCL2_CPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CPUCL2_CPM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_STR_CPUCL0_2_IPCLKPORT_DEM_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_STR_CPUCL0_2_IPCLKPORT_DEM_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_STR_CPUCL0_2_IPCLKPORT_DEM_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_STR_CPUCL0_2_IPCLKPORT_DEM_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_STR_CPUCL0_2_IPCLKPORT_DEM_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_STR_CPUCL0_2_IPCLKPORT_DEM_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCD_CG_VAL, 21, 1, CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCD),
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SFR_ACCESS(CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCD_MANUAL, 20, 1, CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCD),
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SFR_ACCESS(CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCD),
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SFR_ACCESS(CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCP_CG_VAL, 21, 1, CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCP),
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SFR_ACCESS(CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCP_MANUAL, 20, 1, CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCP),
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SFR_ACCESS(CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCP),
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SFR_ACCESS(CLK_CON_GAT_CLKCSIS_ALLCSIS_OIC_MCU_CG_VAL, 21, 1, CLK_CON_GAT_CLKCSIS_ALLCSIS_OIC_MCU),
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SFR_ACCESS(CLK_CON_GAT_CLKCSIS_ALLCSIS_OIC_MCU_MANUAL, 20, 1, CLK_CON_GAT_CLKCSIS_ALLCSIS_OIC_MCU),
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SFR_ACCESS(CLK_CON_GAT_CLKCSIS_ALLCSIS_OIC_MCU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCSIS_ALLCSIS_OIC_MCU),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS6_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS6),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS6_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS6),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS6),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_I_FD_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_I_FD_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_I_FD_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_I_FD_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_I_FD_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_I_FD_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS4_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS4),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS4_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS4),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS4),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS3_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS3),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS3_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS3),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS3),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS5_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS5),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS5_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS5),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS5),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS6_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS6),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS6_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS6),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS6),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_XIU_P1_CSIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_XIU_P1_CSIS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_XIU_P1_CSIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_XIU_P1_CSIS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_XIU_P1_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_XIU_P1_CSIS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_AD_APB_MIPI_PHY_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_AD_APB_MIPI_PHY_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_AD_APB_MIPI_PHY_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_AD_APB_MIPI_PHY_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_AD_APB_MIPI_PHY_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_AD_APB_MIPI_PHY_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AXI_MI_LP_UFDCSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AXI_MI_LP_UFDCSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AXI_MI_LP_UFDCSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AXI_MI_LP_UFDCSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AXI_MI_LP_UFDCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AXI_MI_LP_UFDCSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AST_SI_OTF_CSISUFD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AST_SI_OTF_CSISUFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AST_SI_OTF_CSISUFD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AST_SI_OTF_CSISUFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AST_SI_OTF_CSISUFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AST_SI_OTF_CSISUFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_LH_AXI_MI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_LH_AXI_MI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_LH_AXI_MI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_LH_AXI_MI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_LH_AXI_MI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_LH_AXI_MI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_DCPHY_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_DCPHY_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_DCPHY_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_DCPHY_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_DCPHY_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_DCPHY_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_CSTAT_CMU_CSTAT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_CSTAT_CMU_CSTAT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_CSTAT_CMU_CSTAT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_CSTAT_CMU_CSTAT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_CSTAT_CMU_CSTAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_CSTAT_CMU_CSTAT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_D_TZPC_CSTAT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_D_TZPC_CSTAT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_D_TZPC_CSTAT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_D_TZPC_CSTAT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_D_TZPC_CSTAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_D_TZPC_CSTAT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_AD_APB_CSTAT0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_AD_APB_CSTAT0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_AD_APB_CSTAT0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_AD_APB_CSTAT0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_AD_APB_CSTAT0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_AD_APB_CSTAT0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AXI_MI_P_CSTAT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AXI_MI_P_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AXI_MI_P_CSTAT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AXI_MI_P_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AXI_MI_P_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AXI_MI_P_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AXI_SI_D_CSTAT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AXI_SI_D_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AXI_SI_D_CSTAT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AXI_SI_D_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AXI_SI_D_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AXI_SI_D_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSREG_CSTAT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSREG_CSTAT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSREG_CSTAT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSREG_CSTAT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSREG_CSTAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSREG_CSTAT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_XIU_D_CSTAT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_XIU_D_CSTAT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_XIU_D_CSTAT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_XIU_D_CSTAT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_XIU_D_CSTAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_XIU_D_CSTAT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2RD_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2RD),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2RD_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2RD),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2RD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2RD),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2DS_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2DS),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2DS_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2DS),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2DS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2DS),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AST_SI_G_PPMU_CSTAT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AST_SI_G_PPMU_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AST_SI_G_PPMU_CSTAT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AST_SI_G_PPMU_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AST_SI_G_PPMU_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AST_SI_G_PPMU_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_BLK_CSTAT_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_BLK_CSTAT_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_BLK_CSTAT_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_BLK_CSTAT_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSTAT_UID_BLK_CSTAT_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSTAT_UID_BLK_CSTAT_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_AHB_BUSMATRIX_DBGCORE_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_AHB_BUSMATRIX_DBGCORE_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_AHB_BUSMATRIX_DBGCORE_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_AHB_BUSMATRIX_DBGCORE_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_AHB_BUSMATRIX_DBGCORE_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_AHB_BUSMATRIX_DBGCORE_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_GREBEINTEGRATION_DBGCORE_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_GREBEINTEGRATION_DBGCORE_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_GREBEINTEGRATION_DBGCORE_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_GREBEINTEGRATION_DBGCORE_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_GREBEINTEGRATION_DBGCORE_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_GREBEINTEGRATION_DBGCORE_IPCLKPORT_HCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_MI_IP_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_MI_IP_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_MI_IP_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_MI_IP_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_MI_IP_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_MI_IP_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_ID_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_ID_DBGCORE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_ID_DBGCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_ID_DBGCORE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_ID_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_ID_DBGCORE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_WDT_DBGCORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_WDT_DBGCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_WDT_DBGCORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_WDT_DBGCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_WDT_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_WDT_DBGCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_XHB_DBGCORE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_XHB_DBGCORE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_XHB_DBGCORE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_XHB_DBGCORE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_XHB_DBGCORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_XHB_DBGCORE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_DBGCORE_CMU_DBGCORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_DBGCORE_CMU_DBGCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_DBGCORE_CMU_DBGCORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_DBGCORE_CMU_DBGCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_DBGCORE_CMU_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_DBGCORE_CMU_DBGCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_GREBE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_GREBE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_GREBE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_GREBE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_GREBE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_GREBE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_CORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_D_TZPC_DBGCORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_D_TZPC_DBGCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_D_TZPC_DBGCORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_D_TZPC_DBGCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_D_TZPC_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_D_TZPC_DBGCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_APBIF_S2D_DBGCORE_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_APBIF_S2D_DBGCORE_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_APBIF_S2D_DBGCORE_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_APBIF_S2D_DBGCORE_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_APBIF_S2D_DBGCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_APBIF_S2D_DBGCORE_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_ASYNCAHBMASTER_DBGCORE_IPCLKPORT_HCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_ASYNCAHBMASTER_DBGCORE_IPCLKPORT_HCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_ASYNCAHBMASTER_DBGCORE_IPCLKPORT_HCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_ASYNCAHBMASTER_DBGCORE_IPCLKPORT_HCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_ASYNCAHBMASTER_DBGCORE_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_ASYNCAHBMASTER_DBGCORE_IPCLKPORT_HCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_OSCCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_OSCCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_OSCCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_OSCCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_OSCCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_SR_CLK_DBGCORE_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_SR_CLK_DBGCORE_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_SR_CLK_DBGCORE_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_SR_CLK_DBGCORE_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_SR_CLK_DBGCORE_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_SR_CLK_DBGCORE_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SS_DBGCORE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SS_DBGCORE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SS_DBGCORE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SS_DBGCORE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SS_DBGCORE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SS_DBGCORE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SHMEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SHMEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SHMEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SHMEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SHMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SHMEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU0DNC_SHMEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU0DNC_SHMEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU0DNC_SHMEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU0DNC_SHMEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU0DNC_SHMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU0DNC_SHMEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU1DNC_SHMEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU1DNC_SHMEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU1DNC_SHMEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU1DNC_SHMEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU1DNC_SHMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU1DNC_SHMEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_DNC_CMU_DNC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_DNC_CMU_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_DNC_CMU_DNC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_DNC_CMU_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_DNC_CMU_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_DNC_CMU_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SFR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SFR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_P_DNC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_P_DNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_P_DNC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_P_DNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_P_DNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_P_DNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LP_IPDNC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LP_IPDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LP_IPDNC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LP_IPDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LP_IPDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LP_IPDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_IPDNC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_IPDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_IPDNC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_IPDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_IPDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_IPDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_ADM_DAP_DNC_IPCLKPORT_DAPCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_ADM_DAP_DNC_IPCLKPORT_DAPCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_ADM_DAP_DNC_IPCLKPORT_DAPCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_ADM_DAP_DNC_IPCLKPORT_DAPCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_ADM_DAP_DNC_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_ADM_DAP_DNC_IPCLKPORT_DAPCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_DSP0DNC_CACHE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_DSP0DNC_CACHE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_DSP0DNC_CACHE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_DSP0DNC_CACHE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_DSP0DNC_CACHE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_DSP0DNC_CACHE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_DMA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_DMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_DMA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_DMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_DMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_DMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSREG_DNC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSREG_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSREG_DNC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSREG_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSREG_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSREG_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_SFR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_SFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_SFR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_SFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_SFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_D_TZPC_DNC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_D_TZPC_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_D_TZPC_DNC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_D_TZPC_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_D_TZPC_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_D_TZPC_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_APBAS_S1_NS_SDMA0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_APBAS_S1_NS_SDMA0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_APBAS_S1_NS_SDMA0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_APBAS_S1_NS_SDMA0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_APBAS_S1_NS_SDMA0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_APBAS_S1_NS_SDMA0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CH_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CH_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_BAAW_DNCCHUBVTS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_BAAW_DNCCHUBVTS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_BAAW_DNCCHUBVTS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_BAAW_DNCCHUBVTS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_BAAW_DNCCHUBVTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_BAAW_DNCCHUBVTS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_POWERIP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_POWERIP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_ATCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_ATCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_DDD_DNC_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_DDD_DNC_IPCLKPORT_CK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_DDD_DNC_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_DDD_DNC_IPCLKPORT_CK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_DDD_DNC_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_DDD_DNC_IPCLKPORT_CK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_DNCSDMA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_DNCSDMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_DNCSDMA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_DNCSDMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_DNCSDMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_DNCSDMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SIU_G_PPMU_DNC_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SIU_G_PPMU_DNC_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SIU_G_PPMU_DNC_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SIU_G_PPMU_DNC_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SIU_G_PPMU_DNC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SIU_G_PPMU_DNC_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AST_SI_G_PPMU_DNC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AST_SI_G_PPMU_DNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AST_SI_G_PPMU_DNC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AST_SI_G_PPMU_DNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AST_SI_G_PPMU_DNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AST_SI_G_PPMU_DNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LP_ALIVEDNC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LP_ALIVEDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LP_ALIVEDNC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LP_ALIVEDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LP_ALIVEDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LP_ALIVEDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_DNC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_DNC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_DNC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_DNC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_DNC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_DNC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_LITE_DNC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_LITE_DNC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_LITE_DNC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_LITE_DNC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_LITE_DNC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_LITE_DNC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_UFDDNC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_UFDDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_UFDDNC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_UFDDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_UFDDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_UFDDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_XIU_P_DNC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_XIU_P_DNC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_XIU_P_DNC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_XIU_P_DNC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_XIU_P_DNC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_XIU_P_DNC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_MI_OTF_UFDDNC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_MI_OTF_UFDDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_MI_OTF_UFDDNC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_MI_OTF_UFDDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_MI_OTF_UFDDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_MI_OTF_UFDDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_GLUE_OTF_UFDDNC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_GLUE_OTF_UFDDNC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_GLUE_OTF_UFDDNC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_GLUE_OTF_UFDDNC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_GLUE_OTF_UFDDNC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_GLUE_OTF_UFDDNC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DSP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DSP0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DSP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DSP0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DSP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DSP0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_SDMA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_SDMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_SDMA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_SDMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_SDMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_SDMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_BLK_DNC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_BLK_DNC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_BLK_DNC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_BLK_DNC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_BLK_DNC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_BLK_DNC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_POWERIP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_POWERIP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_DDD_CTRL_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_DDD_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_DDD_CTRL_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_DDD_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_DDD_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_DDD_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_DAPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_DAPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_DAPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_DAPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_DAPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_DAPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_SLH_AXI_MI_P_DPUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_SLH_AXI_MI_P_DPUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_SLH_AXI_MI_P_DPUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_SLH_AXI_MI_P_DPUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_SLH_AXI_MI_P_DPUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_SLH_AXI_MI_P_DPUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_UPI_M0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_UPI_M0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_UPI_M0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_UPI_M0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_UPI_M0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_UPI_M0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_BLK_DPUB_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_BLK_DPUB_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_BLK_DPUB_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_BLK_DPUB_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUB_UID_BLK_DPUB_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUB_UID_BLK_DPUB_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_CMU_DPUF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_CMU_DPUF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_CMU_DPUF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_CMU_DPUF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_CMU_DPUF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_CMU_DPUF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_MI_P_DPUF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_MI_P_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_MI_P_DPUF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_MI_P_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_MI_P_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_MI_P_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_LH_AXI_SI_D1_DPUF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_LH_AXI_SI_D1_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_LH_AXI_SI_D1_DPUF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_LH_AXI_SI_D1_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_LH_AXI_SI_D1_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_LH_AXI_SI_D1_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSREG_DPUF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSREG_DPUF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSREG_DPUF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSREG_DPUF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSREG_DPUF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSREG_DPUF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D0_DPUF_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D0_DPUF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D0_DPUF_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D0_DPUF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D0_DPUF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D0_DPUF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D1_DPUF_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D1_DPUF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D1_DPUF_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D1_DPUF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D1_DPUF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D1_DPUF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SIU_DPUF_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SIU_DPUF_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SIU_DPUF_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SIU_DPUF_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SIU_DPUF_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SIU_DPUF_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AST_SI_G_PPMU_DPUF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AST_SI_G_PPMU_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AST_SI_G_PPMU_DPUF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AST_SI_G_PPMU_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AST_SI_G_PPMU_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AST_SI_G_PPMU_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_SI_D0_DPUF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_SI_D0_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_SI_D0_DPUF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_SI_D0_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_SI_D0_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_SI_D0_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_SRAMC_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_SRAMC),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_SRAMC_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_SRAMC),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_SRAMC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_SRAMC),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_BLK_DPUF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_BLK_DPUF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_BLK_DPUF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_BLK_DPUF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF_UID_BLK_DPUF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF_UID_BLK_DPUF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPUF_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPUF),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPUF_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPUF),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPUF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPUF),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_VOTF_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_VOTF),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_VOTF_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_VOTF),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_VOTF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_VOTF),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_AXI_MI_P_DPUF1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_AXI_MI_P_DPUF1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_AXI_MI_P_DPUF1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_AXI_MI_P_DPUF1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_AXI_MI_P_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_AXI_MI_P_DPUF1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SIU_DPUF1_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SIU_DPUF1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SIU_DPUF1_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SIU_DPUF1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SIU_DPUF1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SIU_DPUF1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D0_DPUF1DPUF0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D0_DPUF1DPUF0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D0_DPUF1DPUF0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D0_DPUF1DPUF0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D0_DPUF1DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D0_DPUF1DPUF0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D1_DPUF1DPUF0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D1_DPUF1DPUF0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D1_DPUF1DPUF0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D1_DPUF1DPUF0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D1_DPUF1DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D1_DPUF1DPUF0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_ASTL_SI_G_PPMU_DPUF1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_ASTL_SI_G_PPMU_DPUF1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_ASTL_SI_G_PPMU_DPUF1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_ASTL_SI_G_PPMU_DPUF1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_ASTL_SI_G_PPMU_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_ASTL_SI_G_PPMU_DPUF1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_SR_CLK_DPUF1_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_SR_CLK_DPUF1_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_SR_CLK_DPUF1_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_SR_CLK_DPUF1_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_SR_CLK_DPUF1_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_SR_CLK_DPUF1_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_CMU_DRCP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_CMU_DRCP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_CMU_DRCP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_CMU_DRCP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_CMU_DRCP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_CMU_DRCP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_AD_APB_DRCP_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_AD_APB_DRCP_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_AD_APB_DRCP_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_AD_APB_DRCP_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_AD_APB_DRCP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_AD_APB_DRCP_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_D_TZPC_DRCP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_D_TZPC_DRCP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_D_TZPC_DRCP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_D_TZPC_DRCP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_D_TZPC_DRCP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_D_TZPC_DRCP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_XIU_D_DRCP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_XIU_D_DRCP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_XIU_D_DRCP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_XIU_D_DRCP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_XIU_D_DRCP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_XIU_D_DRCP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSREG_DRCP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSREG_DRCP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSREG_DRCP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSREG_DRCP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSREG_DRCP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSREG_DRCP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_AXI_MI_P_DRCP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_AXI_MI_P_DRCP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_AXI_MI_P_DRCP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_AXI_MI_P_DRCP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_AXI_MI_P_DRCP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_AXI_MI_P_DRCP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_MI_OTF_YUVPDRCP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_MI_OTF_YUVPDRCP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_MI_OTF_YUVPDRCP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_MI_OTF_YUVPDRCP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_MI_OTF_YUVPDRCP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_MI_OTF_YUVPDRCP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_SI_OTF_DRCPMCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_SI_OTF_DRCPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_SI_OTF_DRCPMCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_SI_OTF_DRCPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_SI_OTF_DRCPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_SI_OTF_DRCPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AXI_SI_D_DRCP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AXI_SI_D_DRCP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AXI_SI_D_DRCP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AXI_SI_D_DRCP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AXI_SI_D_DRCP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AXI_SI_D_DRCP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_VGEN_LITE_D_DRCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_VGEN_LITE_D_DRCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_VGEN_LITE_D_DRCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_VGEN_LITE_D_DRCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_VGEN_LITE_D_DRCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_VGEN_LITE_D_DRCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_ASTL_SI_G_PPMU_DRCP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_ASTL_SI_G_PPMU_DRCP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_ASTL_SI_G_PPMU_DRCP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_ASTL_SI_G_PPMU_DRCP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_ASTL_SI_G_PPMU_DRCP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_ASTL_SI_G_PPMU_DRCP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_SR_CLK_DRCP_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_SR_CLK_DRCP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_SR_CLK_DRCP_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_SR_CLK_DRCP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_SR_CLK_DRCP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_SR_CLK_DRCP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SHMEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SHMEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SHMEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SHMEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SHMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SHMEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_D_TZPC_DSP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_D_TZPC_DSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_D_TZPC_DSP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_D_TZPC_DSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_D_TZPC_DSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_D_TZPC_DSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_MI_LP_DSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_MI_LP_DSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_MI_LP_DSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_MI_LP_DSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_MI_LP_DSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_MI_LP_DSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_DMA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_DMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_DMA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_DMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_DMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_DMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_SFR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_SFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_SFR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_SFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_SFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_SI_LD_DSPDNC_CACHE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_SI_LD_DSPDNC_CACHE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_SI_LD_DSPDNC_CACHE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_SI_LD_DSPDNC_CACHE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_SI_LD_DSPDNC_CACHE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_SI_LD_DSPDNC_CACHE_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SFR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SFR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SFR_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_IP_DSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_IP_DSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_IP_DSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_IP_DSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_IP_DSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_IP_DSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AST_MI_LD_STRM_SDMADSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AST_MI_LD_STRM_SDMADSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AST_MI_LD_STRM_SDMADSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AST_MI_LD_STRM_SDMADSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AST_MI_LD_STRM_SDMADSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AST_MI_LD_STRM_SDMADSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_BLK_DSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_BLK_DSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_BLK_DSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_BLK_DSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_BLK_DSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_BLK_DSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ATB_SI_IT_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ATB_SI_IT_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ATB_SI_IT_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ATB_SI_IT_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ATB_SI_IT_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ATB_SI_IT_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_DSU_POWERIP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_DSU_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_DSU_POWERIP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_DSU_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_DSU_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_DSU_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D0_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D0_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D0_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D1_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D1_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D1_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_GRAY2BIN_CNTVALUEB_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_GRAY2BIN_CNTVALUEB_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_GRAY2BIN_CNTVALUEB_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_GRAY2BIN_CNTVALUEB_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_GRAY2BIN_CNTVALUEB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_GRAY2BIN_CNTVALUEB_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_SCLK),
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SFR_ACCESS(CLK_CON_GAT_DSU_CPM_CG_VAL, 21, 1, CLK_CON_GAT_DSU_CPM),
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SFR_ACCESS(CLK_CON_GAT_DSU_CPM_MANUAL, 20, 1, CLK_CON_GAT_DSU_CPM),
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SFR_ACCESS(CLK_CON_GAT_DSU_CPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_DSU_CPM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_STR_CPUCL0_3_IPCLKPORT_DEM_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_STR_CPUCL0_3_IPCLKPORT_DEM_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_STR_CPUCL0_3_IPCLKPORT_DEM_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_STR_CPUCL0_3_IPCLKPORT_DEM_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_STR_CPUCL0_3_IPCLKPORT_DEM_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_STR_CPUCL0_3_IPCLKPORT_DEM_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_HTU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_HTU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_HTU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_HTU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_HTU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_LP_PPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_LP_PPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_LP_PPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_LP_PPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_LP_PPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_LP_PPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_PPUWAKEUP_CLUSTER0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_PPUWAKEUP_CLUSTER0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_PPUWAKEUP_CLUSTER0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_PPUWAKEUP_CLUSTER0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_PPUWAKEUP_CLUSTER0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_PPUWAKEUP_CLUSTER0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_UTILITY_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_UTILITY_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_UTILITY_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_UTILITY_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_UTILITY_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_UTILITY_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_IP_UTILITY_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_IP_UTILITY_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_IP_UTILITY_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_IP_UTILITY_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_IP_UTILITY_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_IP_UTILITY_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PPUCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PPUCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PPUCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PPUCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PPUCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PPUCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_SCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_SCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_SCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_PERIPHERAL_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_PERIPHERAL_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_PERIPHERAL_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_PERIPHERAL_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_PERIPHERAL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_PERIPHERAL_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_IP_UTILITY_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_IP_UTILITY_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_IP_UTILITY_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_IP_UTILITY_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_IP_UTILITY_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_IP_UTILITY_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D0_ACP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D0_ACP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D0_ACP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D0_ACP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D0_ACP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D0_ACP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D1_ACP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D1_ACP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D1_ACP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D1_ACP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D1_ACP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D1_ACP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_D_CPUCL0_ACP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_D_CPUCL0_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_D_CPUCL0_ACP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_D_CPUCL0_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_D_CPUCL0_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_D_CPUCL0_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_MPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_MPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_MPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_MPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_MPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_MPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_ACPWAKEUP_CLUSTER0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_ACPWAKEUP_CLUSTER0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_ACPWAKEUP_CLUSTER0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_ACPWAKEUP_CLUSTER0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_ACPWAKEUP_CLUSTER0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_ACPWAKEUP_CLUSTER0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_DIVCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_DIVCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_DIVCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_DIVCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_DIVCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_DIVCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_DIVCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_DIVCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_DIVCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_DIVCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_DIVCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_DIVCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D3_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D3_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_POWERIP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_POWERIP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_IRITWAKEUP_CLUSTER0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_IRITWAKEUP_CLUSTER0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_IRITWAKEUP_CLUSTER0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_IRITWAKEUP_CLUSTER0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_IRITWAKEUP_CLUSTER0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_IRITWAKEUP_CLUSTER0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_SI_P_INT_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_SI_P_INT_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_SI_P_INT_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_SI_P_INT_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_SI_P_INT_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_SI_P_INT_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_CFM_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_CFM_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_CFM_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_CFM_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_CFM_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_CFM_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_BG3D_PWRCTL_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_BG3D_PWRCTL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_BG3D_PWRCTL_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_BG3D_PWRCTL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_BG3D_PWRCTL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_BG3D_PWRCTL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CH_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CH_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CH_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3D_POWERIP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3D_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3D_POWERIP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3D_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3D_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3D_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_G3DCORE_CMU_G3DCORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_G3DCORE_CMU_G3DCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_G3DCORE_CMU_G3DCORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_G3DCORE_CMU_G3DCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_G3DCORE_CMU_G3DCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_G3DCORE_CMU_G3DCORE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_GPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_GPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_GPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_GPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_GPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_GPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADM_DAP_G_G3D_IPCLKPORT_DAPCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADM_DAP_G_G3D_IPCLKPORT_DAPCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADM_DAP_G_G3D_IPCLKPORT_DAPCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADM_DAP_G_G3D_IPCLKPORT_DAPCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADM_DAP_G_G3D_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADM_DAP_G_G3D_IPCLKPORT_DAPCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_BUSIF_DDC_G3D_IPCLKPORT_PCLK_S0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_BUSIF_DDC_G3D_IPCLKPORT_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_BUSIF_DDC_G3D_IPCLKPORT_PCLK_S0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_BUSIF_DDC_G3D_IPCLKPORT_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_BUSIF_DDC_G3D_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_BUSIF_DDC_G3D_IPCLKPORT_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_G3DCORE_CPM_CG_VAL, 21, 1, CLK_CON_GAT_G3DCORE_CPM),
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SFR_ACCESS(CLK_CON_GAT_G3DCORE_CPM_MANUAL, 20, 1, CLK_CON_GAT_G3DCORE_CPM),
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SFR_ACCESS(CLK_CON_GAT_G3DCORE_CPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_G3DCORE_CPM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3D_POWERIP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3D_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3D_POWERIP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3D_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3D_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3D_POWERIP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_GNPU_CMU_GNPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_GNPU_CMU_GNPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_GNPU_CMU_GNPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_GNPU_CMU_GNPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_GNPU_CMU_GNPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_GNPU_CMU_GNPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_CORE),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_SRAM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_SRAM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_SRAM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_SRAM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_SRAM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_SRAM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD_CTRL_GNPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD_CTRL_GNPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD_CTRL_GNPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD_CTRL_GNPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD_CTRL_GNPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD_CTRL_GNPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_RQ_GNPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_RQ_GNPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_RQ_GNPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_RQ_GNPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_RQ_GNPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_RQ_GNPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD1_GNPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD1_GNPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD1_GNPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD1_GNPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD1_GNPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD1_GNPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_D_TZPC_GNPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_D_TZPC_GNPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_D_TZPC_GNPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_D_TZPC_GNPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_D_TZPC_GNPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_D_TZPC_GNPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_MI_LP_GNPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_MI_LP_GNPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_MI_LP_GNPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_MI_LP_GNPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_MI_LP_GNPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_MI_LP_GNPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_SI_LD_CMDQ_GNPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_SI_LD_CMDQ_GNPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_SI_LD_CMDQ_GNPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_SI_LD_CMDQ_GNPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_SI_LD_CMDQ_GNPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_SI_LD_CMDQ_GNPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_SYSREG_GNPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_SYSREG_GNPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_SYSREG_GNPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_SYSREG_GNPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_SYSREG_GNPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_SYSREG_GNPU_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD0_GNPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD0_GNPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD0_GNPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD0_GNPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD0_GNPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD0_GNPU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_GNPUDNC_SHMEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_GNPUDNC_SHMEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_GNPUDNC_SHMEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_GNPUDNC_SHMEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_GNPUDNC_SHMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_GNPUDNC_SHMEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_BLK_GNPU_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_BLK_GNPU_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_BLK_GNPU_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_BLK_GNPU_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNPU_UID_BLK_GNPU_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNPU_UID_BLK_GNPU_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_A_G2X1_PHY_REFCLK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_A_G2X1_PHY_REFCLK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_A_G2X1_PHY_REFCLK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_A_G2X1_PHY_REFCLK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_A_G2X1_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_A_G2X1_PHY_REFCLK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PIPE_PAL_GEN2_X1_PCIE_INST_0_I_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PIPE_PAL_GEN2_X1_PCIE_INST_0_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PIPE_PAL_GEN2_X1_PCIE_INST_0_I_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PIPE_PAL_GEN2_X1_PCIE_INST_0_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PIPE_PAL_GEN2_X1_PCIE_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PIPE_PAL_GEN2_X1_PCIE_INST_0_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PHY_UDBG_I_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PHY_UDBG_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PHY_UDBG_I_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PHY_UDBG_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PHY_UDBG_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SUB_CTRL_A_G3X2_PHY_REFCLK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SUB_CTRL_A_G3X2_PHY_REFCLK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SUB_CTRL_A_G3X2_PHY_REFCLK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SUB_CTRL_A_G3X2_PHY_REFCLK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SUB_CTRL_A_G3X2_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SUB_CTRL_A_G3X2_PHY_REFCLK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_SF_PCIEPHY_X1_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_SF_PCIEPHY_X1_QCH_TM_WRAPPER_INST_0_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_SF_PCIEPHY_X1_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_SF_PCIEPHY_X1_QCH_TM_WRAPPER_INST_0_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_SF_PCIEPHY_X1_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_SF_PCIEPHY_X1_QCH_TM_WRAPPER_INST_0_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AST_SI_G_PPMU_HSI1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AST_SI_G_PPMU_HSI1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AST_SI_G_PPMU_HSI1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AST_SI_G_PPMU_HSI1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AST_SI_G_PPMU_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AST_SI_G_PPMU_HSI1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SOC_CTRL_GEN3A_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SOC_CTRL_GEN3A_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SOC_CTRL_GEN3A_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SOC_CTRL_GEN3A_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SOC_CTRL_GEN3A_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SOC_CTRL_GEN3A_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_SF_PCIEPHY_X2_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_SF_PCIEPHY_X2_QCH_TM_WRAPPER_INST_0_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_SF_PCIEPHY_X2_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_SF_PCIEPHY_X2_QCH_TM_WRAPPER_INST_0_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_SF_PCIEPHY_X2_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_SF_PCIEPHY_X2_QCH_TM_WRAPPER_INST_0_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PHY_UDBG_I_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PHY_UDBG_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PHY_UDBG_I_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PHY_UDBG_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PHY_UDBG_I_APB_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SOC_CTRL_GEN2_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SOC_CTRL_GEN2_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SOC_CTRL_GEN2_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SOC_CTRL_GEN2_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SOC_CTRL_GEN2_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SOC_CTRL_GEN2_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_BLK_HSI1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_BLK_HSI1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_BLK_HSI1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_BLK_HSI1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_BLK_HSI1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_BLK_HSI1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_LH_ACEL_SI_D_LME_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_LH_ACEL_SI_D_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_LH_ACEL_SI_D_LME_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_LH_ACEL_SI_D_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_LH_ACEL_SI_D_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_LH_ACEL_SI_D_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AXI_MI_P_LME_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AXI_MI_P_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AXI_MI_P_LME_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AXI_MI_P_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AXI_MI_P_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AXI_MI_P_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AST_SI_G_PPMU_LME_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AST_SI_G_PPMU_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AST_SI_G_PPMU_LME_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AST_SI_G_PPMU_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AST_SI_G_PPMU_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AST_SI_G_PPMU_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_LME_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_LME_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_LME_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_LME_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_LME_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_LME_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_GDC_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_GDC_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_GDC_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_GDC_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_GDC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_GDC_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_LME_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_LME_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_LME_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_LME_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_LME_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_LME_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_M_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_M),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_M_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_M),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_M_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_M),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_S_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_S),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_S_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_S),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_S_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_S),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_MI_ID_LME_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_MI_ID_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_MI_ID_LME_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_MI_ID_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_MI_ID_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_MI_ID_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_SI_ID_LME_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_SI_ID_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_SI_ID_LME_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_SI_ID_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_SI_ID_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_SI_ID_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_LME_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_LME_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_LME_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_LME_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_LME_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_LME_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_GDC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_GDC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_GDC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_GDC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_GDC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_LME_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_LME_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_LME_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_LME_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_LME_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_LME_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_BLK_LME_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_LME_UID_BLK_LME_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_BLK_LME_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_LME_UID_BLK_LME_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_LME_UID_BLK_LME_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_LME_UID_BLK_LME_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_LH_ACEL_SI_D_M2M_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_LH_ACEL_SI_D_M2M_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_LH_ACEL_SI_D_M2M_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_LH_ACEL_SI_D_M2M_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_LH_ACEL_SI_D_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_LH_ACEL_SI_D_M2M_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AST_SI_G_PPMU_M2M_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AST_SI_G_PPMU_M2M_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AST_SI_G_PPMU_M2M_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AST_SI_G_PPMU_M2M_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AST_SI_G_PPMU_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AST_SI_G_PPMU_M2M_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_FRC_MC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_FRC_MC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_FRC_MC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_FRC_MC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_FRC_MC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_FRC_MC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_FRC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_FRC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_FRC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_FRC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_FRC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_FRC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_FRC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_FRC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_FRC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_FRC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_FRC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_FRC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_FRC_MC_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_FRC_MC_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_FRC_MC_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_FRC_MC_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_FRC_MC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_FRC_MC_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_BLK_M2M_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_BLK_M2M_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_BLK_M2M_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_BLK_M2M_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_BLK_M2M_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_BLK_M2M_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_MI_FRC_MC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_MI_FRC_MC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_MI_FRC_MC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_MI_FRC_MC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_MI_FRC_MC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_MI_FRC_MC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_SI_FRC_MC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_SI_FRC_MC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_SI_FRC_MC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_SI_FRC_MC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_SI_FRC_MC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_SI_FRC_MC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AST_SI_G_PPMU_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AST_SI_G_PPMU_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AST_SI_G_PPMU_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AST_SI_G_PPMU_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AST_SI_G_PPMU_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AST_SI_G_PPMU_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SIU_G_PPMU_MCSC_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SIU_G_PPMU_MCSC_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SIU_G_PPMU_MCSC_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SIU_G_PPMU_MCSC_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SIU_G_PPMU_MCSC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SIU_G_PPMU_MCSC_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_MCSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_MCSC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_MCSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_MCSC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_MCSC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCFP_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCFP_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCFP_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCFP_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCFP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCFP_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D3_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D3_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D3_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D3_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D3_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D3_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D4_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D4_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D4_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D4_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D4_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D4_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D3_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D3_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D3_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D3_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D3_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D3_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D4_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D4_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D4_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D4_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D4_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D4_MCSC_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D2_MCSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D2_MCSC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D2_MCSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D2_MCSC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D2_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D2_MCSC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCFP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCFP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCFP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCFP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCFP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCFP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_SI_OTF_MCSCYUVP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_SI_OTF_MCSCYUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_SI_OTF_MCSCYUVP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_SI_OTF_MCSCYUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_SI_OTF_MCSCYUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_SI_OTF_MCSCYUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF_BRPMCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF_BRPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF_BRPMCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF_BRPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF_BRPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF_BRPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC6_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC6_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC6_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC6_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC6_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC6_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC3_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC3_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC4_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC4_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC4_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC4_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC4_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC4_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC5_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC5_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC5_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC5_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC5_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC5_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC3_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC3_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC4_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC4_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC4_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC4_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC4_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC4_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC5_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC5_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC5_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC5_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC5_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC5_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC6_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC6_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC6_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC6_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC6_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC6_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_BLK_MCSC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_BLK_MCSC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_BLK_MCSC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_BLK_MCSC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_BLK_MCSC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_BLK_MCSC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D1_MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D1_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D1_MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D1_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D1_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D1_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D0_MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D0_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D0_MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D0_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D0_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D0_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AXI_MI_P_MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AXI_MI_P_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AXI_MI_P_MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AXI_MI_P_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AXI_MI_P_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AXI_MI_P_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AST_SI_G_PPMU_MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AST_SI_G_PPMU_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AST_SI_G_PPMU_MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AST_SI_G_PPMU_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AST_SI_G_PPMU_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AST_SI_G_PPMU_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SIU_G_PPMU_MFC0_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SIU_G_PPMU_MFC0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SIU_G_PPMU_MFC0_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SIU_G_PPMU_MFC0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_SIU_G_PPMU_MFC0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_SIU_G_PPMU_MFC0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_VGEN_LITE_MFC0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_VGEN_LITE_MFC0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_VGEN_LITE_MFC0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_VGEN_LITE_MFC0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_VGEN_LITE_MFC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_VGEN_LITE_MFC0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_ID_MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_ID_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_ID_MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_ID_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_ID_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_ID_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_MI_ID_MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_MI_ID_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_MI_ID_MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_MI_ID_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_MI_ID_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_MI_ID_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_BLK_MFC0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_BLK_MFC0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_BLK_MFC0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_BLK_MFC0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_BLK_MFC0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_BLK_MFC0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AXI_MI_P_MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AXI_MI_P_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AXI_MI_P_MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AXI_MI_P_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AXI_MI_P_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AXI_MI_P_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D0_MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D0_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D0_MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D0_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D0_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D0_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D1_MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D1_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D1_MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D1_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D1_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D1_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AST_SI_G_PPMU_MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AST_SI_G_PPMU_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AST_SI_G_PPMU_MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AST_SI_G_PPMU_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AST_SI_G_PPMU_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AST_SI_G_PPMU_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SIU_G_PPMU_MFC1_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SIU_G_PPMU_MFC1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SIU_G_PPMU_MFC1_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SIU_G_PPMU_MFC1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_SIU_G_PPMU_MFC1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_SIU_G_PPMU_MFC1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_BLK_MFC1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_BLK_MFC1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_BLK_MFC1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_BLK_MFC1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_BLK_MFC1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_BLK_MFC1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DDRPHY_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DDRPHY_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DDRPHY_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DDRPHY_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DDRPHY_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DMC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DMC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DMC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DMC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DMC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_SPC_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_SPC_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_SPC_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_SPC_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_SPC_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_SPC_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_PRIVATE_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_PRIVATE_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_PRIVATE_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_PRIVATE_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_PRIVATE_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_PRIVATE_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AST_SI_G_PPMU_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AST_SI_G_PPMU_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AST_SI_G_PPMU_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AST_SI_G_PPMU_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AST_SI_G_PPMU_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AST_SI_G_PPMU_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_ATCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_ATCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_DDD_MIF_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_DDD_MIF_IPCLKPORT_CK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_DDD_MIF_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_DDD_MIF_IPCLKPORT_CK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_DDD_MIF_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_DDD_MIF_IPCLKPORT_CK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_DEBUG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_DEBUG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_DEBUG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_DEBUG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_DEBUG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_DEBUG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_DDD_CTRL_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_DDD_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_DDD_CTRL_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_DDD_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_DDD_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_DDD_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_BLK_MIF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_BLK_MIF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_BLK_MIF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_BLK_MIF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_BLK_MIF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_BLK_MIF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G0_PPMU_NOCL0_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G0_PPMU_NOCL0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G0_PPMU_NOCL0_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G0_PPMU_NOCL0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G0_PPMU_NOCL0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G0_PPMU_NOCL0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G1_PPMU_NOCL0_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G1_PPMU_NOCL0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G1_PPMU_NOCL0_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G1_PPMU_NOCL0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G1_PPMU_NOCL0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G1_PPMU_NOCL0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_SYSMMU_S2_G3D_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_SYSMMU_S2_G3D_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_SYSMMU_S2_G3D_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_SYSMMU_S2_G3D_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_SYSMMU_S2_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_SYSMMU_S2_G3D_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_CP_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_CP_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_CP_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_CP_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_CP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_CP_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D2_MODEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D2_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D2_MODEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D2_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D2_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D2_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D0_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D0_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D0_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D1_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D1_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D1_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_QDI_MI_D_AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_QDI_MI_D_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_QDI_MI_D_AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_QDI_MI_D_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_QDI_MI_D_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_QDI_MI_D_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERISGIC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERISGIC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERISGIC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERISGIC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERISGIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERISGIC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_NOCL0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_NOCL0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_NOCL0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_NOCL0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_NOCL0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_NOCL0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_APM_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_APM_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_APM_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_APM_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_APM_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_APM_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D3_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D3),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D3_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D3),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D3),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_NOCL0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_NOCL0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_NOCL0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_NOCL0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_NOCL0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_NOCL0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_UFD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_UFD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_SSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_SSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_SSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_SSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_SSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1C_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1C_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_MPTW_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_MPTW),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_MPTW_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_MPTW),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_MPTW_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_MPTW),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_AUD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MODEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MODEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MODEM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G2_PPMU_NOCL0_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G2_PPMU_NOCL0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G2_PPMU_NOCL0_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G2_PPMU_NOCL0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G2_PPMU_NOCL0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G2_PPMU_NOCL0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G3_PPMU_NOCL0_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G3_PPMU_NOCL0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G3_PPMU_NOCL0_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G3_PPMU_NOCL0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G3_PPMU_NOCL0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G3_PPMU_NOCL0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G4_PPMU_NOCL0_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G4_PPMU_NOCL0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G4_PPMU_NOCL0_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G4_PPMU_NOCL0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G4_PPMU_NOCL0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G4_PPMU_NOCL0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G5_PPMU_NOCL0_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G5_PPMU_NOCL0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G5_PPMU_NOCL0_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G5_PPMU_NOCL0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G5_PPMU_NOCL0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G5_PPMU_NOCL0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_ETR_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_ETR_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_ETR_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_ETR_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_ETR_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_ETR_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_ETR_64_NOCL0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_ETR_64_NOCL0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_ETR_64_NOCL0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_ETR_64_NOCL0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_ETR_64_NOCL0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_ETR_64_NOCL0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF3_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF3_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D0_MODEM_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D0_MODEM_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D0_MODEM_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D0_MODEM_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D0_MODEM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D0_MODEM_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D1_MODEM_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D1_MODEM_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D1_MODEM_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D1_MODEM_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D1_MODEM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D1_MODEM_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D0_G3D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D0_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D0_G3D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D0_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D0_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D0_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D1_G3D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D1_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D1_G3D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D1_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D1_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D1_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D2_G3D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D2_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D2_G3D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D2_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D2_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D2_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D3_G3D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D3_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D3_G3D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D3_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D3_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D3_G3D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D0_G3D_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D0_G3D_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D0_G3D_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D0_G3D_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D0_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D0_G3D_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D1_G3D_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D1_G3D_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D1_G3D_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D1_G3D_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D1_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D1_G3D_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D2_G3D_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D2_G3D_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D2_G3D_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D2_G3D_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D2_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D2_G3D_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D3_G3D_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D3_G3D_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D3_G3D_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D3_G3D_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D3_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D3_G3D_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_GNSS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_GNSS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCIF_CMUTOPC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCIF_CMUTOPC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCIF_CMUTOPC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCIF_CMUTOPC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCIF_CMUTOPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCIF_CMUTOPC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_SSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_SSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_SSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_SSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_SSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_UFD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_UFD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_ACEL_MI_D_SSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_ACEL_MI_D_SSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_ACEL_MI_D_SSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_ACEL_MI_D_SSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_ACEL_MI_D_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_ACEL_MI_D_SSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D_UFD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D_UFD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D0_ACP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D0_ACP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D0_ACP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D0_ACP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D0_ACP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D0_ACP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D1_ACP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D1_ACP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D1_ACP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D1_ACP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D1_ACP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D1_ACP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D0_ACP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D0_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D0_ACP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D0_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D0_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D0_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D1_ACP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D1_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D1_ACP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D1_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D1_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D1_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D2_ACP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D2_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D2_ACP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D2_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D2_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D2_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D3_ACP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D3_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D3_ACP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D3_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D3_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D3_ACP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_CCI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_CCI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_CCI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_CCI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_CCI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BLK_NOCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BLK_NOCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BLK_NOCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BLK_NOCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_BLK_NOCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BLK_NOCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_LME_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_LME_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_NOCL1A_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_NOCL1A),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_NOCL1A_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_NOCL1A),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_NOCL1A_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_NOCL1A),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_LME_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_LME_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_HSI1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_HSI1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_HSI1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_HSI1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_HSI1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_LME_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_LME_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_LME_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_2X1_P0_NOCL1A_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_2X1_P0_NOCL1A_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_2X1_P0_NOCL1A_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_2X1_P0_NOCL1A_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_2X1_P0_NOCL1A_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_2X1_P0_NOCL1A_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_4X1_P0_NOCL1A_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_4X1_P0_NOCL1A_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_4X1_P0_NOCL1A_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_4X1_P0_NOCL1A_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_4X1_P0_NOCL1A_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_4X1_P0_NOCL1A_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_8X1_P0_NOCL1A_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_8X1_P0_NOCL1A_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_8X1_P0_NOCL1A_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_8X1_P0_NOCL1A_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_8X1_P0_NOCL1A_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_8X1_P0_NOCL1A_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_DPUF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_DPUF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DNC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DNC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DPUF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DPUF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_MI_D0_DPUF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_MI_D0_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_MI_D0_DPUF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_MI_D0_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_MI_D0_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_MI_D0_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DNC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DNC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUB_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUB_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUB_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUF_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BAAW_P_DNC_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BAAW_P_DNC_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BAAW_P_DNC_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BAAW_P_DNC_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BAAW_P_DNC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BAAW_P_DNC_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_M2M_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_M2M_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_M2M_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_M2M_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_M2M_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_M2M_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_M2M_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_M2M_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_M2M_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_M2M_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_RET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_RET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_RET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_RET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_RET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_RET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_RET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_RET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_RET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_RET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_RET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_RET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BLK_NOCL1A_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BLK_NOCL1A_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BLK_NOCL1A_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BLK_NOCL1A_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BLK_NOCL1A_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BLK_NOCL1A_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_NOCL1B_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_NOCL1B),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_NOCL1B_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_NOCL1B),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_NOCL1B_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_NOCL1B),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_UFS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_UFS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_UFS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_UFS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_UFS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_UFS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_HSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_HSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_HSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_HSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_HSI0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_DIT_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_DIT_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_DIT_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_DIT_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_DIT_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_PDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_PDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_PDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_TT_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_TT_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_TT_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_TT_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_TT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_TT_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PDMA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PDMA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PDMA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PDMA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PDMA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SPDMA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SPDMA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SPDMA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SPDMA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SPDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SPDMA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_DIT_IPCLKPORT_ICLKL2A_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_DIT_IPCLKPORT_ICLKL2A),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_DIT_IPCLKPORT_ICLKL2A_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_DIT_IPCLKPORT_ICLKL2A),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_DIT_IPCLKPORT_ICLKL2A_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_DIT_IPCLKPORT_ICLKL2A),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_XIU_D_TT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_XIU_D_TT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_XIU_D_TT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_XIU_D_TT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_XIU_D_TT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_XIU_D_TT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_TT_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_TT_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_TT_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_TT_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_TT_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_TT_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_LITE_NOCL1B_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_LITE_NOCL1B_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_LITE_NOCL1B_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_LITE_NOCL1B_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_LITE_NOCL1B_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_LITE_NOCL1B_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_SPDMA_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_SPDMA_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_SPDMA_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_SPDMA_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_SPDMA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_SPDMA_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_PDMA_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_PDMA_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_PDMA_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_PDMA_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_PDMA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_PDMA_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_ID_DIT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_ID_DIT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_ID_DIT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_ID_DIT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_ID_DIT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_ID_DIT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_SI_ID_DIT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_SI_ID_DIT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_SI_ID_DIT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_SI_ID_DIT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_SI_ID_DIT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_SI_ID_DIT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_LITE_NOCL1B_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_LITE_NOCL1B_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_LITE_NOCL1B_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_LITE_NOCL1B_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_LITE_NOCL1B_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_LITE_NOCL1B_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_SPDMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_SPDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_SPDMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_SPDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_SPDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_SPDMA_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_TREXP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_TREXP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_TREXP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_TREXP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_TREXP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_TREXP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_DIT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_DIT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_DIT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_DIT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_DIT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_DIT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_TREXP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_TREXP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_TREXP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_TREXP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_TREXP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_TREXP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_DIT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_DIT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_DIT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_DIT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_DIT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_DIT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_D_UFS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_D_UFS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_D_UFS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_D_UFS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_D_UFS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_D_UFS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_UFS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_UFS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_UFS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_UFS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_UFS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_UFS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SIU_8X1_P0_NOCL1B_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SIU_8X1_P0_NOCL1B_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SIU_8X1_P0_NOCL1B_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SIU_8X1_P0_NOCL1B_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SIU_8X1_P0_NOCL1B_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SIU_8X1_P0_NOCL1B_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_ID_TT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_ID_TT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_ID_TT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_ID_TT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_ID_TT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_ID_TT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_ID_TT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_ID_TT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_ID_TT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_ID_TT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_ID_TT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_ID_TT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_RET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_RET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_RET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_RET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_RET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_RET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_RET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_RET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_RET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_RET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_RET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_RET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_BLK_NOCL1B_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_BLK_NOCL1B_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_BLK_NOCL1B_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_BLK_NOCL1B_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_BLK_NOCL1B_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_BLK_NOCL1B_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_NOCL1C_CMU_NOCL1C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_NOCL1C_CMU_NOCL1C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_NOCL1C_CMU_NOCL1C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_NOCL1C_CMU_NOCL1C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_NOCL1C_CMU_NOCL1C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_NOCL1C_CMU_NOCL1C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SYSREG_NOCL1C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SYSREG_NOCL1C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SYSREG_NOCL1C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SYSREG_NOCL1C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SYSREG_NOCL1C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SYSREG_NOCL1C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSTAT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSTAT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D_CSTAT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D_CSTAT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_NOCL1C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_NOCL1C),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_NOCL1C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_NOCL1C),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_NOCL1C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_NOCL1C),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_YUVP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_YUVP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AST_SI_G_NOCL1C_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AST_SI_G_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AST_SI_G_NOCL1C_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AST_SI_G_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AST_SI_G_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AST_SI_G_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_D_TZPC_NOCL1C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_D_TZPC_NOCL1C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_D_TZPC_NOCL1C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_D_TZPC_NOCL1C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_D_TZPC_NOCL1C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_D_TZPC_NOCL1C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_CLK_NOCL1C_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_CLK_NOCL1C_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_CLK_NOCL1C_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_CLK_NOCL1C_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_CLK_NOCL1C_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_CLK_NOCL1C_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSTAT_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSTAT_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSTAT_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_YUVP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_YUVP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D3_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D3_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D3_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D3_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D3_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D3_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D4_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D4_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D4_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D4_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D4_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D4_MCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_BRP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_BRP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_BRP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_BRP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_BRP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_BRP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_YUVP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_YUVP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D1_YUVP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D1_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D1_YUVP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D1_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D1_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D1_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_BRP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_BRP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_BRP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_BRP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_BRP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SIU_8X1_P0_NOCL1C_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SIU_8X1_P0_NOCL1C_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SIU_8X1_P0_NOCL1C_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SIU_8X1_P0_NOCL1C_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SIU_8X1_P0_NOCL1C_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SIU_8X1_P0_NOCL1C_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_BLK_NOCL1C_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_BLK_NOCL1C_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_BLK_NOCL1C_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_BLK_NOCL1C_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1C_UID_BLK_NOCL1C_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_BLK_NOCL1C_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_SR_CLK_S2D_CORE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_SR_CLK_S2D_CORE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_SR_CLK_S2D_CORE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_SR_CLK_S2D_CORE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_SR_CLK_S2D_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_SR_CLK_S2D_CORE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_SDMA_CMU_SDMA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_SDMA_CMU_SDMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_SDMA_CMU_SDMA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_SDMA_CMU_SDMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_SDMA_CMU_SDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_SDMA_CMU_SDMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_SLH_AXI_MI_LP_SDMA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_SLH_AXI_MI_LP_SDMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_SLH_AXI_MI_LP_SDMA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_SLH_AXI_MI_LP_SDMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_SLH_AXI_MI_LP_SDMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_SLH_AXI_MI_LP_SDMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_SYSREG_SDMA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_SYSREG_SDMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_SYSREG_SDMA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_SYSREG_SDMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_SYSREG_SDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_SYSREG_SDMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_D_TZPC_SDMA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_D_TZPC_SDMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_D_TZPC_SDMA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_D_TZPC_SDMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_D_TZPC_SDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_D_TZPC_SDMA_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AST_SI_LD_STRM_SDMADSP0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AST_SI_LD_STRM_SDMADSP0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AST_SI_LD_STRM_SDMADSP0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AST_SI_LD_STRM_SDMADSP0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AST_SI_LD_STRM_SDMADSP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AST_SI_LD_STRM_SDMADSP0_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_IP_SDMA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_IP_SDMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_IP_SDMA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_IP_SDMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_IP_SDMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_IP_SDMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_MI_LP_DNCSDMA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_MI_LP_DNCSDMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_MI_LP_DNCSDMA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_MI_LP_DNCSDMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_MI_LP_DNCSDMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_MI_LP_DNCSDMA_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_BLK_SDMA_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_BLK_SDMA_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_BLK_SDMA_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_BLK_SDMA_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SDMA_UID_BLK_SDMA_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SDMA_UID_BLK_SDMA_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_LH_AXI_MI_L_STRONG_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_LH_AXI_MI_L_STRONG_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_LH_AXI_MI_L_STRONG_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_LH_AXI_MI_L_STRONG_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_LH_AXI_MI_L_STRONG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_LH_AXI_MI_L_STRONG_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AXI_MI_P_SSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AXI_MI_P_SSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AXI_MI_P_SSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AXI_MI_P_SSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AXI_MI_P_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AXI_MI_P_SSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_ACEL_SI_D_SSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_ACEL_SI_D_SSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_ACEL_SI_D_SSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_ACEL_SI_D_SSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_ACEL_SI_D_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_ACEL_SI_D_SSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SYSREG_SSP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SYSREG_SSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SYSREG_SSP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SYSREG_SSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SYSREG_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SYSREG_SSP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_VGEN_LITE_SSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_VGEN_LITE_SSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_VGEN_LITE_SSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_VGEN_LITE_SSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_VGEN_LITE_SSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_VGEN_LITE_SSP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_AD_APB_SYSMMU_SSP_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_AD_APB_SYSMMU_SSP_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_AD_APB_SYSMMU_SSP_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_AD_APB_SYSMMU_SSP_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_AD_APB_SYSMMU_SSP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_AD_APB_SYSMMU_SSP_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SYSMMU_SSP_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SYSMMU_SSP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SYSMMU_SSP_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SYSMMU_SSP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SYSMMU_SSP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SYSMMU_SSP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AST_SI_G_PPMU_SSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AST_SI_G_PPMU_SSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AST_SI_G_PPMU_SSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AST_SI_G_PPMU_SSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AST_SI_G_PPMU_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AST_SI_G_PPMU_SSP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_OTP_DESERIAL_SSS_HIDE_SECKEY_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_OTP_DESERIAL_SSS_HIDE_SECKEY_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_OTP_DESERIAL_SSS_HIDE_SECKEY_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_OTP_DESERIAL_SSS_HIDE_SECKEY_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_OTP_DESERIAL_SSS_HIDE_SECKEY_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_OTP_DESERIAL_SSS_HIDE_SECKEY_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_BLK_SSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_BLK_SSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_BLK_SSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_BLK_SSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_BLK_SSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_BLK_SSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_STRONG_UID_STRONG_CMU_STRONG_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_STRONG_UID_STRONG_CMU_STRONG_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_STRONG_UID_STRONG_CMU_STRONG_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_STRONG_UID_STRONG_CMU_STRONG_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_STRONG_UID_STRONG_CMU_STRONG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_STRONG_UID_STRONG_CMU_STRONG_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_CMU_UFD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_CMU_UFD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_CMU_UFD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_CMU_UFD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_CMU_UFD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_CMU_UFD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_D_TZPC_UFD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_D_TZPC_UFD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_D_TZPC_UFD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_D_TZPC_UFD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_D_TZPC_UFD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_D_TZPC_UFD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_LP_CMGPUFD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_LP_CMGPUFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_LP_CMGPUFD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_LP_CMGPUFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_LP_CMGPUFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_LP_CMGPUFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_P_UFD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_P_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_P_UFD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_P_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_P_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_P_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_PDMA_UFD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_PDMA_UFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_PDMA_UFD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_PDMA_UFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_PDMA_UFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_PDMA_UFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_DP_UFD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_DP_UFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_DP_UFD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_DP_UFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_DP_UFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_DP_UFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_VGEN_LITE_D_UFD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_VGEN_LITE_D_UFD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_VGEN_LITE_D_UFD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_VGEN_LITE_D_UFD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_VGEN_LITE_D_UFD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_VGEN_LITE_D_UFD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_D_UFD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_D_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_D_UFD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_D_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_D_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_D_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_D_UFD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_D_UFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_D_UFD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_D_UFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_D_UFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_D_UFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LD_UFDDNC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LD_UFDDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LD_UFDDNC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LD_UFDDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LD_UFDDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LD_UFDDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SRAM_MIU_UFD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SRAM_MIU_UFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SRAM_MIU_UFD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SRAM_MIU_UFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SRAM_MIU_UFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SRAM_MIU_UFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_SCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_BAAW_D_UFDDNC_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_BAAW_D_UFDDNC_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_BAAW_D_UFDDNC_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_BAAW_D_UFDDNC_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_BAAW_D_UFDDNC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_BAAW_D_UFDDNC_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_SECURE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_SECURE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_SECURE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_SECURE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_SECURE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_SECURE_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_ID_COMP_UFD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_ID_COMP_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_ID_COMP_UFD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_ID_COMP_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_ID_COMP_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_ID_COMP_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LP_UFDCSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LP_UFDCSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LP_UFDCSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LP_UFDCSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LP_UFDCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LP_UFDCSIS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_MI_OTF_CSISUFD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_MI_OTF_CSISUFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_MI_OTF_CSISUFD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_MI_OTF_CSISUFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_MI_OTF_CSISUFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_MI_OTF_CSISUFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_SI_G_PPMU_UFD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_SI_G_PPMU_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_SI_G_PPMU_UFD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_SI_G_PPMU_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_SI_G_PPMU_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_SI_G_PPMU_UFD_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_LH_AST_SI_OTF_UFDDNC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_LH_AST_SI_OTF_UFDDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_LH_AST_SI_OTF_UFDDNC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_LH_AST_SI_OTF_UFDDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_LH_AST_SI_OTF_UFDDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_LH_AST_SI_OTF_UFDDNC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_BLK_UFD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_BLK_UFD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_BLK_UFD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_BLK_UFD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_BLK_UFD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_BLK_UFD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_US_32TO128_UFD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_US_32TO128_UFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_US_32TO128_UFD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_US_32TO128_UFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_US_32TO128_UFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_US_32TO128_UFD_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_DS_128TO32_UFD_IPCLKPORT_MAINCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_DS_128TO32_UFD_IPCLKPORT_MAINCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_DS_128TO32_UFD_IPCLKPORT_MAINCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_DS_128TO32_UFD_IPCLKPORT_MAINCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_DS_128TO32_UFD_IPCLKPORT_MAINCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_DS_128TO32_UFD_IPCLKPORT_MAINCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK),
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SFR_ACCESS(CLK_CON_GAT_CLKVTS_AUD_DMIC1_CG_VAL, 21, 1, CLK_CON_GAT_CLKVTS_AUD_DMIC1),
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SFR_ACCESS(CLK_CON_GAT_CLKVTS_AUD_DMIC1_MANUAL, 20, 1, CLK_CON_GAT_CLKVTS_AUD_DMIC1),
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SFR_ACCESS(CLK_CON_GAT_CLKVTS_AUD_DMIC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKVTS_AUD_DMIC1),
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SFR_ACCESS(CLK_CON_GAT_CLKVTS_AUD_DMIC0_CG_VAL, 21, 1, CLK_CON_GAT_CLKVTS_AUD_DMIC0),
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SFR_ACCESS(CLK_CON_GAT_CLKVTS_AUD_DMIC0_MANUAL, 20, 1, CLK_CON_GAT_CLKVTS_AUD_DMIC0),
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SFR_ACCESS(CLK_CON_GAT_CLKVTS_AUD_DMIC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKVTS_AUD_DMIC0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_CMU_YUVP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_CMU_YUVP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_CMU_YUVP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_CMU_YUVP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_CMU_YUVP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_CMU_YUVP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_AD_APB_YUVP_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_AD_APB_YUVP_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_AD_APB_YUVP_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_AD_APB_YUVP_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_AD_APB_YUVP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_AD_APB_YUVP_IPCLKPORT_PCLKM),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_MI_P_YUVP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_MI_P_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_MI_P_YUVP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_MI_P_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_MI_P_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_MI_P_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSREG_YUVP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSREG_YUVP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSREG_YUVP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSREG_YUVP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSREG_YUVP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSREG_YUVP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D0_YUVP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D0_YUVP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D0_YUVP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D0_YUVP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D0_YUVP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D0_YUVP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_MI_OTF_MCSCYUVP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_MI_OTF_MCSCYUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_MI_OTF_MCSCYUVP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_MI_OTF_MCSCYUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_MI_OTF_MCSCYUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_MI_OTF_MCSCYUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_D_TZPC_YUVP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_D_TZPC_YUVP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_D_TZPC_YUVP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_D_TZPC_YUVP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_D_TZPC_YUVP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_D_TZPC_YUVP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_DDD_YUVP_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_DDD_YUVP_IPCLKPORT_CK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_DDD_YUVP_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_DDD_YUVP_IPCLKPORT_CK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_DDD_YUVP_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_DDD_YUVP_IPCLKPORT_CK_IN),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D0_YUVP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D0_YUVP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D0_YUVP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D0_YUVP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D0_YUVP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D0_YUVP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_ATCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_ATCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_ATCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AST_SI_G_PPMU_YUVP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AST_SI_G_PPMU_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AST_SI_G_PPMU_YUVP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AST_SI_G_PPMU_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AST_SI_G_PPMU_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AST_SI_G_PPMU_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCD_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_PCLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AXI_SI_D0_YUVP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AXI_SI_D0_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AXI_SI_D0_YUVP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AXI_SI_D0_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AXI_SI_D0_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AXI_SI_D0_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_SI_D1_YUVP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_SI_D1_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_SI_D1_YUVP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_SI_D1_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_SI_D1_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_SI_D1_YUVP_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D1_YUVP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D1_YUVP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D1_YUVP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D1_YUVP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D1_YUVP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D1_YUVP_IPCLKPORT_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S2),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SIU_G_PPMU_YUVP_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SIU_G_PPMU_YUVP_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SIU_G_PPMU_YUVP_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SIU_G_PPMU_YUVP_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_SIU_G_PPMU_YUVP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_SIU_G_PPMU_YUVP_IPCLKPORT_I_ACLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D1_YUVP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D1_YUVP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D1_YUVP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D1_YUVP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D1_YUVP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D1_YUVP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF0),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF1),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCP_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_BLK_YUVP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_BLK_YUVP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_BLK_YUVP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_BLK_YUVP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_BLK_YUVP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_BLK_YUVP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_DDD_CTRL_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_DDD_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_DDD_CTRL_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_DDD_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_DDD_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_DDD_CTRL_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_FREE_OSCCLK_IPCLKPORT_CLK),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI1_PCIE),
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SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL0_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_CPUCL0_DDD_CTRL),
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SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL1_DDD_CTRL_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_CPUCL1_DDD_CTRL_0),
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SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL1_DDD_CTRL_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_CPUCL1_DDD_CTRL_1),
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SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL1_DDD_CTRL_2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_CPUCL1_DDD_CTRL_2),
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SFR_ACCESS(CLK_CON_DIV_CLK_CPUCL2_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_CPUCL2_DDD_CTRL),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DNC_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DNC_DDD_CTRL),
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SFR_ACCESS(CLK_CON_DIV_CLK_DSU_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_DSU_DDD_CTRL),
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SFR_ACCESS(CLK_CON_DIV_CLK_G3D_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_G3D_DDD_CTRL),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_NOCD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF_NOCD),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF_DDD_CTRL),
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SFR_ACCESS(CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_OTP),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIS_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIS_DDD_CTRL),
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SFR_ACCESS(CLK_CON_DIV_CLK_MIF_NOCD_S2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_MIF_NOCD_S2D),
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SFR_ACCESS(CLK_CON_DIV_DIV_CLK_YUVP_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_YUVP_DDD_CTRL),
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SFR_ACCESS(QCH_CON_ALIVE_CMU_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_ALIVE_CMU_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_ALIVE_CMU_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_ALIVE_CMU_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_ALIVE_CMU_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ALIVE_CMU_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_APBIF_GPIO_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_GPIO_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_GPIO_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_ENABLE, 0, 1, QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH),
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SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH),
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SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH),
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SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_ENABLE, 0, 1, QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH),
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SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH),
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SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH),
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SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_ENABLE, 0, 1, QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH),
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SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH),
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SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH),
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SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_APBIF_PMU_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_PMU_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_PMU_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_APM_DMA_QCH_APB_ENABLE, 0, 1, QCH_CON_APM_DMA_QCH_APB),
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SFR_ACCESS(QCH_CON_APM_DMA_QCH_APB_CLOCK_REQ, 1, 1, QCH_CON_APM_DMA_QCH_APB),
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SFR_ACCESS(QCH_CON_APM_DMA_QCH_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APM_DMA_QCH_APB),
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SFR_ACCESS(QCH_CON_CHUB_RTC_QCH_ENABLE, 0, 1, QCH_CON_CHUB_RTC_QCH),
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SFR_ACCESS(QCH_CON_CHUB_RTC_QCH_CLOCK_REQ, 1, 1, QCH_CON_CHUB_RTC_QCH),
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SFR_ACCESS(QCH_CON_CHUB_RTC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CHUB_RTC_QCH),
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SFR_ACCESS(QCH_CON_CLKMON_QCH_ENABLE, 0, 1, QCH_CON_CLKMON_QCH),
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SFR_ACCESS(QCH_CON_CLKMON_QCH_CLOCK_REQ, 1, 1, QCH_CON_CLKMON_QCH),
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SFR_ACCESS(QCH_CON_CLKMON_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLKMON_QCH),
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SFR_ACCESS(QCH_CON_DBGCORE_UART_QCH_ENABLE, 0, 1, QCH_CON_DBGCORE_UART_QCH),
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SFR_ACCESS(QCH_CON_DBGCORE_UART_QCH_CLOCK_REQ, 1, 1, QCH_CON_DBGCORE_UART_QCH),
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SFR_ACCESS(QCH_CON_DBGCORE_UART_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DBGCORE_UART_QCH),
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SFR_ACCESS(QCH_CON_DTZPC_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_DTZPC_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_DTZPC_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_DTZPC_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_DTZPC_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DTZPC_ALIVE_QCH),
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SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_ENABLE, 0, 1, QCH_CON_GREBEINTEGRATION_QCH_GREBE),
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SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_CLOCK_REQ, 1, 1, QCH_CON_GREBEINTEGRATION_QCH_GREBE),
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SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GREBEINTEGRATION_QCH_GREBE),
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SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_ENABLE, 0, 1, QCH_CON_GREBEINTEGRATION_QCH_DBG),
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SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_CLOCK_REQ, 1, 1, QCH_CON_GREBEINTEGRATION_QCH_DBG),
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SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GREBEINTEGRATION_QCH_DBG),
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SFR_ACCESS(QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_ENABLE, 0, 1, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH),
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SFR_ACCESS(QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_CLOCK_REQ, 1, 1, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH),
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SFR_ACCESS(QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH),
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SFR_ACCESS(QCH_CON_INTMEM_QCH_ENABLE, 0, 1, QCH_CON_INTMEM_QCH),
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SFR_ACCESS(QCH_CON_INTMEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_INTMEM_QCH),
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|
SFR_ACCESS(QCH_CON_INTMEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_INTMEM_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_APM_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_APM_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_APM_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_APM_QCH),
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|
SFR_ACCESS(QCH_CON_MAILBOX_APM_AP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_AP_QCH),
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|
SFR_ACCESS(QCH_CON_MAILBOX_APM_AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_AP_QCH),
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|
SFR_ACCESS(QCH_CON_MAILBOX_APM_AP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_AP_QCH),
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|
SFR_ACCESS(QCH_CON_MAILBOX_APM_AUD_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_AUD_QCH),
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|
SFR_ACCESS(QCH_CON_MAILBOX_APM_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_AUD_QCH),
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|
SFR_ACCESS(QCH_CON_MAILBOX_APM_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CHUB_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_CP_QCH),
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|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_CP_QCH),
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|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_CP_QCH),
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|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CP_1_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_CP_1_QCH),
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|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CP_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_CP_1_QCH),
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|
SFR_ACCESS(QCH_CON_MAILBOX_APM_CP_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_CP_1_QCH),
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|
SFR_ACCESS(QCH_CON_MAILBOX_APM_GNSS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_VTS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_APM_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CHUB_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_S_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_CP_S_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_S_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_CP_S_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_CP_S_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_CP_S_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_GNSS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_CHUB_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_CP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_CP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_CP_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_GNSS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_CP_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_CP_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CP_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_CP_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_GNSS_CHUB_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_GNSS_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_GNSS_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_GNSS_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_GNSS_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_GNSS_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_SHARED_SRAM_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_SHARED_SRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_SHARED_SRAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_SHARED_SRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_SHARED_SRAM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_SHARED_SRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_MCT_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_MCT_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_MCT_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCT_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_MCT_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCT_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_QCH_PMU_ENABLE, 0, 1, QCH_CON_PMU_QCH_PMU),
|
|
SFR_ACCESS(QCH_CON_PMU_QCH_PMU_CLOCK_REQ, 1, 1, QCH_CON_PMU_QCH_PMU),
|
|
SFR_ACCESS(QCH_CON_PMU_QCH_PMU_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PMU_QCH_PMU),
|
|
SFR_ACCESS(QCH_CON_PMU_QCH_PMLINK_ENABLE, 0, 1, QCH_CON_PMU_QCH_PMLINK),
|
|
SFR_ACCESS(QCH_CON_PMU_QCH_PMLINK_CLOCK_REQ, 1, 1, QCH_CON_PMU_QCH_PMLINK),
|
|
SFR_ACCESS(QCH_CON_PMU_QCH_PMLINK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PMU_QCH_PMLINK),
|
|
SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_ENABLE, 0, 1, QCH_CON_PMU_INTR_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_INTR_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PMU_INTR_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH),
|
|
SFR_ACCESS(QCH_CON_RTC_QCH_ENABLE, 0, 1, QCH_CON_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_RTC_QCH_CLOCK_REQ, 1, 1, QCH_CON_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_RTC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_ID_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_ID_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_ID_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_ID_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_ID_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_ID_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LD_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LD_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LD_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_GNSS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LD_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LD_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LD_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_MODEM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LP_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LP_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LP_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_APM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_IP_APM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_IP_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_IP_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_IP_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_IP_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_IP_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_ALIVEDNC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LP_ALIVEDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_ALIVEDNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LP_ALIVEDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_ALIVEDNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LP_ALIVEDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_CMGP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LP_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LP_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LP_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_PPU_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LP_PPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_PPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LP_PPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_PPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LP_PPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SPC_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_SPC_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_SPC_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPC_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_SPC_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPC_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_SPMI_MASTER_PMIC_QCH_P_ENABLE, 0, 1, QCH_CON_SPMI_MASTER_PMIC_QCH_P),
|
|
SFR_ACCESS(QCH_CON_SPMI_MASTER_PMIC_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_SPMI_MASTER_PMIC_QCH_P),
|
|
SFR_ACCESS(QCH_CON_SPMI_MASTER_PMIC_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPMI_MASTER_PMIC_QCH_P),
|
|
SFR_ACCESS(QCH_CON_SPMI_MASTER_PMIC_QCH_S_ENABLE, 0, 1, QCH_CON_SPMI_MASTER_PMIC_QCH_S),
|
|
SFR_ACCESS(QCH_CON_SPMI_MASTER_PMIC_QCH_S_CLOCK_REQ, 1, 1, QCH_CON_SPMI_MASTER_PMIC_QCH_S),
|
|
SFR_ACCESS(QCH_CON_SPMI_MASTER_PMIC_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPMI_MASTER_PMIC_QCH_S),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_P_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_SWEEPER_P_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_P_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SWEEPER_P_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_P_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SWEEPER_P_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_TOP_RTC_QCH_ENABLE, 0, 1, QCH_CON_TOP_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_TOP_RTC_QCH_CLOCK_REQ, 1, 1, QCH_CON_TOP_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_TOP_RTC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TOP_RTC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_WDT_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_ALIVE_QCH),
|
|
SFR_ACCESS(QCH_CON_ALLCSIS_CMU_ALLCSIS_QCH_ENABLE, 0, 1, QCH_CON_ALLCSIS_CMU_ALLCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_ALLCSIS_CMU_ALLCSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_ALLCSIS_CMU_ALLCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_ALLCSIS_CMU_ALLCSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ALLCSIS_CMU_ALLCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_VOTF0_ENABLE, 0, 1, QCH_CON_CSIS_PDP_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_VOTF0_CLOCK_REQ, 1, 1, QCH_CON_CSIS_PDP_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_VOTF0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSIS_PDP_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_DMA_ENABLE, 0, 1, QCH_CON_CSIS_PDP_QCH_DMA),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_DMA_CLOCK_REQ, 1, 1, QCH_CON_CSIS_PDP_QCH_DMA),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_DMA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSIS_PDP_QCH_DMA),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_MCB_ENABLE, 0, 1, QCH_CON_CSIS_PDP_QCH_MCB),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_MCB_CLOCK_REQ, 1, 1, QCH_CON_CSIS_PDP_QCH_MCB),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_MCB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSIS_PDP_QCH_MCB),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_VOTF1_ENABLE, 0, 1, QCH_CON_CSIS_PDP_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_VOTF1_CLOCK_REQ, 1, 1, QCH_CON_CSIS_PDP_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_VOTF1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSIS_PDP_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_PDP_ENABLE, 0, 1, QCH_CON_CSIS_PDP_QCH_PDP),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_PDP_CLOCK_REQ, 1, 1, QCH_CON_CSIS_PDP_QCH_PDP),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_PDP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSIS_PDP_QCH_PDP),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_PDP_VOTF_ENABLE, 0, 1, QCH_CON_CSIS_PDP_QCH_PDP_VOTF),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_PDP_VOTF_CLOCK_REQ, 1, 1, QCH_CON_CSIS_PDP_QCH_PDP_VOTF),
|
|
SFR_ACCESS(QCH_CON_CSIS_PDP_QCH_PDP_VOTF_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSIS_PDP_QCH_PDP_VOTF),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_BRPCSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF0_BRPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_BRPCSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF0_BRPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_BRPCSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF0_BRPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_BRPCSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF1_BRPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_BRPCSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF1_BRPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_BRPCSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF1_BRPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_CSISCSTAT_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF0_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_CSISCSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF0_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF0_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_CSISCSTAT_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF1_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_CSISCSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF1_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF1_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF2_CSISCSTAT_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF2_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF2_CSISCSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF2_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF2_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF2_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF3_CSISCSTAT_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF3_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF3_CSISCSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF3_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF3_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF3_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_CSISBRP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF_CSISBRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_CSISBRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF_CSISBRP_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_CSISBRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF_CSISBRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LP_INT_P0OIS_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LP_INT_P0OIS_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LP_INT_P0OIS_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LP_INT_P0OIS_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LP_INT_P0OIS_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LP_INT_P0OIS_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_CSIS_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_CSIS_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D2_CSIS_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LP_INT_P0OIS_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LP_INT_P0OIS_CSIS_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LP_INT_P0OIS_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LP_INT_P0OIS_CSIS_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LP_INT_P0OIS_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LP_INT_P0OIS_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LP_INT_P0P1_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LP_INT_P0P1_CSIS_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LP_INT_P0P1_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LP_INT_P0P1_CSIS_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LP_INT_P0P1_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LP_INT_P0P1_CSIS_QCH),
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|
SFR_ACCESS(QCH_CON_OIS_MCU_TOP_QCH_ENABLE, 0, 1, QCH_CON_OIS_MCU_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_OIS_MCU_TOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_OIS_MCU_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_OIS_MCU_TOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_OIS_MCU_TOP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D2_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_WDMA0_QCH_ENABLE, 0, 1, QCH_CON_QE_CSIS_WDMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_WDMA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_CSIS_WDMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_WDMA0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_CSIS_WDMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_WDMA1_QCH_ENABLE, 0, 1, QCH_CON_QE_CSIS_WDMA1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_WDMA1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_CSIS_WDMA1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_WDMA1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_CSIS_WDMA1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_WDMA2_QCH_ENABLE, 0, 1, QCH_CON_QE_CSIS_WDMA2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_WDMA2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_CSIS_WDMA2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_WDMA2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_CSIS_WDMA2_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_WDMA3_QCH_ENABLE, 0, 1, QCH_CON_QE_CSIS_WDMA3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_WDMA3_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_CSIS_WDMA3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_WDMA3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_CSIS_WDMA3_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_WDMA4_QCH_ENABLE, 0, 1, QCH_CON_QE_CSIS_WDMA4_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_WDMA4_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_CSIS_WDMA4_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_CSIS_WDMA4_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_CSIS_WDMA4_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_D0_QCH_ENABLE, 0, 1, QCH_CON_QE_PDP_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDP_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_PDP_D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDP_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCD_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCD_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCD_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCD_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCD_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCP_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCP_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_ALLCSIS_NOCP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_G_PPMU_CSIS_QCH_ENABLE, 0, 1, QCH_CON_SIU_G_PPMU_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_G_PPMU_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIU_G_PPMU_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_G_PPMU_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIU_G_PPMU_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_CSIS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CSIS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_CSISPERIC2_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LP_CSISPERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_CSISPERIC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LP_CSISPERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_CSISPERIC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LP_CSISPERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_CSIS_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_CSIS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_CSIS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D1_QCH),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_ENABLE, 0, 1, QCH_CON_ABOX_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK_DSIF_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK_DSIF),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK_DSIF_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK_DSIF),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK_DSIF_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK_DSIF),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK0_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK0_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK1_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK1_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK2_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK2_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK3_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK3),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK3_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK3),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK3_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK3),
|
|
SFR_ACCESS(DMYQCH_CON_ABOX_QCH_CPU_ENABLE, 0, 1, DMYQCH_CON_ABOX_QCH_CPU),
|
|
SFR_ACCESS(DMYQCH_CON_ABOX_QCH_CPU_CLOCK_REQ, 1, 1, DMYQCH_CON_ABOX_QCH_CPU),
|
|
SFR_ACCESS(DMYQCH_CON_ABOX_QCH_CPU_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ABOX_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK4_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK4),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK4_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK4),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK4_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK4),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CNT_ENABLE, 0, 1, QCH_CON_ABOX_QCH_CNT),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CNT_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_CNT),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CNT_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_CNT),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK5_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK5),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK5_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK5),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK5_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK5),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ASB_ENABLE, 0, 1, QCH_CON_ABOX_QCH_CCLK_ASB),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ASB_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_CCLK_ASB),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ASB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_CCLK_ASB),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK6_ENABLE, 0, 1, QCH_CON_ABOX_QCH_BCLK6),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK6_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_BCLK6),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_BCLK6_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_BCLK6),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK0_ENABLE, 0, 1, QCH_CON_ABOX_QCH_XCLK0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK0_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_XCLK0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_XCLK0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_PCMC_CLK_ENABLE, 0, 1, QCH_CON_ABOX_QCH_PCMC_CLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_PCMC_CLK_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_PCMC_CLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_PCMC_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_PCMC_CLK),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A0_ENABLE, 0, 1, QCH_CON_ABOX_QCH_C2A0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A0_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_C2A0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_C2A0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A1_ENABLE, 0, 1, QCH_CON_ABOX_QCH_C2A1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A1_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_C2A1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_C2A1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_C2A1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK1_ENABLE, 0, 1, QCH_CON_ABOX_QCH_XCLK1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK1_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_XCLK1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_XCLK1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK2_ENABLE, 0, 1, QCH_CON_ABOX_QCH_XCLK2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK2_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_XCLK2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_XCLK2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_XCLK2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CPU0_ENABLE, 0, 1, QCH_CON_ABOX_QCH_CPU0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CPU0_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_CPU0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CPU0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_CPU0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CPU1_ENABLE, 0, 1, QCH_CON_ABOX_QCH_CPU1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CPU1_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_CPU1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CPU1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_CPU1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CPU2_ENABLE, 0, 1, QCH_CON_ABOX_QCH_CPU2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CPU2_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_CPU2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CPU2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_CPU2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_NEON0_ENABLE, 0, 1, QCH_CON_ABOX_QCH_NEON0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_NEON0_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_NEON0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_NEON0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_NEON0),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_NEON1_ENABLE, 0, 1, QCH_CON_ABOX_QCH_NEON1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_NEON1_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_NEON1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_NEON1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_NEON1),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_NEON2_ENABLE, 0, 1, QCH_CON_ABOX_QCH_NEON2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_NEON2_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_NEON2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_NEON2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_NEON2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_L2_ENABLE, 0, 1, QCH_CON_ABOX_QCH_L2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_L2_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_L2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_L2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_L2),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ACP_ENABLE, 0, 1, QCH_CON_ABOX_QCH_CCLK_ACP),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ACP_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_CCLK_ACP),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_CCLK_ACP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_CCLK_ACP),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_ACP_ENABLE, 0, 1, QCH_CON_ABOX_QCH_ACLK_ACP),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_ACP_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_ACLK_ACP),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_ACP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_ACLK_ACP),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_ASB_ENABLE, 0, 1, QCH_CON_ABOX_QCH_ACLK_ASB),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_ASB_CLOCK_REQ, 1, 1, QCH_CON_ABOX_QCH_ACLK_ASB),
|
|
SFR_ACCESS(QCH_CON_ABOX_QCH_ACLK_ASB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ABOX_QCH_ACLK_ASB),
|
|
SFR_ACCESS(QCH_CON_AUD_CMU_AUD_QCH_ENABLE, 0, 1, QCH_CON_AUD_CMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_AUD_CMU_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_AUD_CMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_AUD_CMU_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_AUD_CMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_AUDCHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_BAAW_D_AUDCHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_AUDCHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_D_AUDCHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_AUDCHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_D_AUDCHUBVTS_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_AUD_QCH_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_AUD_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_AUD_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_AUD_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_AUD_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMAILBOX_AUD_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_AUD_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMAILBOX_AUD_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_AUD_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMAILBOX_AUD_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_AUD_QCH_ACLK_ENABLE, 0, 1, QCH_CON_DMAILBOX_AUD_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_AUD_QCH_ACLK_CLOCK_REQ, 1, 1, QCH_CON_DMAILBOX_AUD_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_AUD_QCH_ACLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMAILBOX_AUD_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_AUD_QCH_CCLK_ENABLE, 0, 1, QCH_CON_DMAILBOX_AUD_QCH_CCLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_AUD_QCH_CCLK_CLOCK_REQ, 1, 1, QCH_CON_DMAILBOX_AUD_QCH_CCLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_AUD_QCH_CCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMAILBOX_AUD_QCH_CCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD0_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_AUD0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD0_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_AUD0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD0_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_AUD0_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD0_QCH_DMIC_ENABLE, 0, 1, DMYQCH_CON_DMIC_AUD0_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD0_QCH_DMIC_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_AUD0_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD0_QCH_DMIC_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DMIC_AUD0_QCH_DMIC),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD1_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_AUD1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD1_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_AUD1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD1_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_AUD1_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD1_QCH_DMIC_ENABLE, 0, 1, DMYQCH_CON_DMIC_AUD1_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD1_QCH_DMIC_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_AUD1_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD1_QCH_DMIC_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DMIC_AUD1_QCH_DMIC),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD2_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_AUD2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD2_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_AUD2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_AUD2_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_AUD2_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD2_QCH_DMIC_ENABLE, 0, 1, DMYQCH_CON_DMIC_AUD2_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD2_QCH_DMIC_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_AUD2_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_AUD2_QCH_DMIC_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DMIC_AUD2_QCH_DMIC),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_AUD_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_PERI_ASB_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_PERI_ASB_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_PERI_ASB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_PERI_ASB_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_PERI_ASB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_PERI_ASB_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_PERI_ASB_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_PERI_ASB_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_PERI_ASB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_PERI_ASB_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_PERI_ASB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_PERI_ASB_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_QDI_SI_D_AUD_QCH_ENABLE, 0, 1, QCH_CON_LH_QDI_SI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_QDI_SI_D_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_QDI_SI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_QDI_SI_D_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_QDI_SI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD0_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AUD0_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AUD0_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AUD0_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD1_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AUD1_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AUD1_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AUD1_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD2_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AUD2_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD2_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AUD2_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AUD2_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD3_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AUD3_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD3_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AUD3_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AUD3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AUD3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_AUD_QCH_ENABLE, 0, 1, QCH_CON_PPMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_QCH_PCLK_ENABLE, 0, 1, QCH_CON_SERIAL_LIF_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_SERIAL_LIF_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SERIAL_LIF_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_QCH_BCLK_ENABLE, 0, 1, QCH_CON_SERIAL_LIF_QCH_BCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_QCH_BCLK_CLOCK_REQ, 1, 1, QCH_CON_SERIAL_LIF_QCH_BCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_QCH_BCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SERIAL_LIF_QCH_BCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_QCH_ACLK_ENABLE, 0, 1, QCH_CON_SERIAL_LIF_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_QCH_ACLK_CLOCK_REQ, 1, 1, QCH_CON_SERIAL_LIF_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_QCH_ACLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SERIAL_LIF_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_QCH_CCLK_ENABLE, 0, 1, QCH_CON_SERIAL_LIF_QCH_CCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_QCH_CCLK_CLOCK_REQ, 1, 1, QCH_CON_SERIAL_LIF_QCH_CCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_QCH_CCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SERIAL_LIF_QCH_CCLK),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_AUD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_HSI0AUD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LD_HSI0AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_HSI0AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LD_HSI0AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_HSI0AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LD_HSI0AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_AUD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LD_AUDHSI0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LD_AUDHSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LD_AUDHSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LD_AUDHSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LD_AUDHSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LD_AUDHSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_AUDCHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LP_AUDCHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_AUDCHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LP_AUDCHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_AUDCHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LP_AUDCHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SMMU_AUD_QCH_S1_ENABLE, 0, 1, QCH_CON_SMMU_AUD_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SMMU_AUD_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SMMU_AUD_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SMMU_AUD_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SMMU_AUD_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SMMU_AUD_QCH_S2_ENABLE, 0, 1, QCH_CON_SMMU_AUD_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SMMU_AUD_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SMMU_AUD_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SMMU_AUD_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SMMU_AUD_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_AUD_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_AUD_QCH_ENABLE, 0, 1, QCH_CON_TREX_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_AUD_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_AUD_QCH_ENABLE, 0, 1, QCH_CON_WDT_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_AUD_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_BRP_QCH_ENABLE, 0, 1, DMYQCH_CON_ADD_BRP_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_BRP_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADD_BRP_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_BRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADD_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_BRP_CMU_BRP_QCH_ENABLE, 0, 1, QCH_CON_BRP_CMU_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_BRP_CMU_BRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_BRP_CMU_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_BRP_CMU_BRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BRP_CMU_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_BRP_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_ADD_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_BRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_ADD_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_BRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_ADD_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_BYRP_QCH_ENABLE, 0, 1, QCH_CON_BYRP_QCH),
|
|
SFR_ACCESS(QCH_CON_BYRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_BYRP_QCH),
|
|
SFR_ACCESS(QCH_CON_BYRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BYRP_QCH),
|
|
SFR_ACCESS(QCH_CON_BYRP_QCH_C2S_ZSL_ENABLE, 0, 1, QCH_CON_BYRP_QCH_C2S_ZSL),
|
|
SFR_ACCESS(QCH_CON_BYRP_QCH_C2S_ZSL_CLOCK_REQ, 1, 1, QCH_CON_BYRP_QCH_C2S_ZSL),
|
|
SFR_ACCESS(QCH_CON_BYRP_QCH_C2S_ZSL_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BYRP_QCH_C2S_ZSL),
|
|
SFR_ACCESS(QCH_CON_BYRP_QCH_C2S_BYR_ENABLE, 0, 1, QCH_CON_BYRP_QCH_C2S_BYR),
|
|
SFR_ACCESS(QCH_CON_BYRP_QCH_C2S_BYR_CLOCK_REQ, 1, 1, QCH_CON_BYRP_QCH_C2S_BYR),
|
|
SFR_ACCESS(QCH_CON_BYRP_QCH_C2S_BYR_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BYRP_QCH_C2S_BYR),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_BRP_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_BRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_BRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_CSISBRP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF_CSISBRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_CSISBRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF_CSISBRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_CSISBRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF_CSISBRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_BRPCSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF0_BRPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_BRPCSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF0_BRPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_BRPCSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF0_BRPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_BRPCSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF1_BRPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_BRPCSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF1_BRPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_BRPCSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF1_BRPCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_BRPMCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF_BRPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_BRPMCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF_BRPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_BRPMCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF_BRPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_BRP_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_BRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_BRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_BRP_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_BRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_BRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_BRP_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D2_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_BRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D2_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_BRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D2_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_L_SIU_BRP_QCH_ENABLE, 0, 1, QCH_CON_L_SIU_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_L_SIU_BRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_L_SIU_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_L_SIU_BRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_L_SIU_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_BRP_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_BRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_BRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_BRP_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_BRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_BRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D2_BRP_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D2_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D2_BRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D2_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D2_BRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D2_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_RGBP_QCH_ENABLE, 0, 1, QCH_CON_RGBP_QCH),
|
|
SFR_ACCESS(QCH_CON_RGBP_QCH_CLOCK_REQ, 1, 1, QCH_CON_RGBP_QCH),
|
|
SFR_ACCESS(QCH_CON_RGBP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RGBP_QCH),
|
|
SFR_ACCESS(QCH_CON_RGBP_QCH_VOTF0_ENABLE, 0, 1, QCH_CON_RGBP_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_RGBP_QCH_VOTF0_CLOCK_REQ, 1, 1, QCH_CON_RGBP_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_RGBP_QCH_VOTF0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RGBP_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_RGBP_QCH_VOTF1_ENABLE, 0, 1, QCH_CON_RGBP_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_RGBP_QCH_VOTF1_CLOCK_REQ, 1, 1, QCH_CON_RGBP_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_RGBP_QCH_VOTF1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RGBP_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_BRP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_BRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_BRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_BRP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_BRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_BRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_BRP_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_BRP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_BRP_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_BRP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_BRP_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_BRP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_BRP_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_BRP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_BRP_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_BRP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_BRP_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_BRP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_BRP_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_BRP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_BRP_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_BRP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_BRP_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_BRP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_BRP_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_BRP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_BRP_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_BRP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_BRP_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_BRP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_BRP_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_BRP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_BRP_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_BRP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_BRP_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_BRP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_BRP_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_BRP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_BRP_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_BRP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D2_BRP_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_BRP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BRP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_BRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_BYRP_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_BYRP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_BYRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_BYRP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_BYRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_BYRP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_RGBP_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_RGBP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_RGBP_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_RGBP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_RGBP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_RGBP_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_ENABLE, 0, 1, QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_CHUB_QCH_ENABLE, 0, 1, QCH_CON_APBIF_GPIO_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_GPIO_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_GPIO_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_CHUB_CMU_CHUB_QCH_ENABLE, 0, 1, QCH_CON_CHUB_CMU_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_CHUB_CMU_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_CHUB_CMU_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_CHUB_CMU_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CHUB_CMU_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_CM4_CHUB_QCH_CPU_ENABLE, 0, 1, QCH_CON_CM4_CHUB_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_CM4_CHUB_QCH_CPU_CLOCK_REQ, 1, 1, QCH_CON_CM4_CHUB_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_CM4_CHUB_QCH_CPU_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CM4_CHUB_QCH_CPU),
|
|
SFR_ACCESS(QCH_CON_I2C_CHUB_QCH_ENABLE, 0, 1, QCH_CON_I2C_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_I3C_CHUB_QCH_S_ENABLE, 0, 1, QCH_CON_I3C_CHUB_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C_CHUB_QCH_S_CLOCK_REQ, 1, 1, QCH_CON_I3C_CHUB_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C_CHUB_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C_CHUB_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C_CHUB_QCH_P_ENABLE, 0, 1, QCH_CON_I3C_CHUB_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C_CHUB_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_I3C_CHUB_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C_CHUB_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C_CHUB_QCH_P),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_VC2CHUB_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_IP_VC2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_VC2CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_IP_VC2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_VC2CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_IP_VC2CHUB_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_CHUB2VC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_ID_CHUB2VC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_CHUB2VC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_ID_CHUB2VC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_CHUB2VC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_ID_CHUB2VC_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CHUB_ABOX_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_CHUB_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CHUB_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_CHUB_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CHUB_ABOX_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_CHUB_ABOX_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CHUB_DNC_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_CHUB_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CHUB_DNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_CHUB_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_CHUB_DNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_CHUB_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_CHUB_QCH_ENABLE, 0, 1, QCH_CON_PWM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_PWM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PWM_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_I2C_CHUB0_QCH_ENABLE, 0, 1, QCH_CON_SPI_I2C_CHUB0_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_I2C_CHUB0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPI_I2C_CHUB0_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_I2C_CHUB0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPI_I2C_CHUB0_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_I2C_CHUB1_QCH_ENABLE, 0, 1, QCH_CON_SPI_I2C_CHUB1_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_I2C_CHUB1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPI_I2C_CHUB1_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_I2C_CHUB1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPI_I2C_CHUB1_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_MULTI_SLV_Q_CTRL_CHUB_QCH_ENABLE, 0, 1, QCH_CON_SPI_MULTI_SLV_Q_CTRL_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_MULTI_SLV_Q_CTRL_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPI_MULTI_SLV_Q_CTRL_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_MULTI_SLV_Q_CTRL_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPI_MULTI_SLV_Q_CTRL_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CHUB_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_CHUB_QCH_ENABLE, 0, 1, QCH_CON_TIMER_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_TIMER_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TIMER_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB0_QCH_ENABLE, 0, 1, QCH_CON_USI_CHUB0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB0_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CHUB0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CHUB0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB1_QCH_ENABLE, 0, 1, QCH_CON_USI_CHUB1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB1_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CHUB1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CHUB1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB2_QCH_ENABLE, 0, 1, QCH_CON_USI_CHUB2_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB2_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CHUB2_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CHUB2_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB3_QCH_ENABLE, 0, 1, QCH_CON_USI_CHUB3_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB3_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CHUB3_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CHUB3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CHUB3_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CHUB_QCH_ENABLE, 0, 1, QCH_CON_WDT_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_UPMU_CHUB_QCH_ENABLE, 0, 1, QCH_CON_APBIF_UPMU_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_UPMU_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_UPMU_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_UPMU_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_UPMU_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_APB_SEMA_DMAILBOX_QCH_ENABLE, 0, 1, QCH_CON_APB_SEMA_DMAILBOX_QCH),
|
|
SFR_ACCESS(QCH_CON_APB_SEMA_DMAILBOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_APB_SEMA_DMAILBOX_QCH),
|
|
SFR_ACCESS(QCH_CON_APB_SEMA_DMAILBOX_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APB_SEMA_DMAILBOX_QCH),
|
|
SFR_ACCESS(QCH_CON_APB_SEMA_PDMA_QCH_ENABLE, 0, 1, QCH_CON_APB_SEMA_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_APB_SEMA_PDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_APB_SEMA_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_APB_SEMA_PDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APB_SEMA_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_CHUB_QCH_ENABLE, 0, 1, QCH_CON_BAAW_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_LD_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_BAAW_LD_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_LD_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_LD_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_LD_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_LD_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_CHUB_ALV_QCH_PMU_ENABLE, 0, 1, QCH_CON_CHUB_ALV_QCH_PMU),
|
|
SFR_ACCESS(QCH_CON_CHUB_ALV_QCH_PMU_CLOCK_REQ, 1, 1, QCH_CON_CHUB_ALV_QCH_PMU),
|
|
SFR_ACCESS(QCH_CON_CHUB_ALV_QCH_PMU_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CHUB_ALV_QCH_PMU),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_CHUBVTS_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMAILBOX_CHUBVTS_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_CHUBVTS_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMAILBOX_CHUBVTS_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_CHUBVTS_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMAILBOX_CHUBVTS_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_CHUBVTS_QCH_ACLK_ENABLE, 0, 1, QCH_CON_DMAILBOX_CHUBVTS_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_CHUBVTS_QCH_ACLK_CLOCK_REQ, 1, 1, QCH_CON_DMAILBOX_CHUBVTS_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_CHUBVTS_QCH_ACLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMAILBOX_CHUBVTS_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_CHUBVTS_QCH_CCLK_ENABLE, 0, 1, QCH_CON_DMAILBOX_CHUBVTS_QCH_CCLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_CHUBVTS_QCH_CCLK_CLOCK_REQ, 1, 1, QCH_CON_DMAILBOX_CHUBVTS_QCH_CCLK),
|
|
SFR_ACCESS(QCH_CON_DMAILBOX_CHUBVTS_QCH_CCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMAILBOX_CHUBVTS_QCH_CCLK),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_CHUB2VC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_ID_CHUB2VC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_CHUB2VC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_ID_CHUB2VC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_CHUB2VC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_ID_CHUB2VC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_VTS2VC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_ID_VTS2VC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_VTS2VC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_ID_VTS2VC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_VTS2VC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_ID_VTS2VC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_VC2CHUB_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_IP_VC2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_VC2CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_IP_VC2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_VC2CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_IP_VC2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_VC2VTS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_IP_VC2VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_VC2VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_IP_VC2VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_VC2VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_IP_VC2VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_VTS_CHUB_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_VTS_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_VTS_CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_VTS_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_VTS_CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_VTS_CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_PDMA_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_PDMA_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PDMA_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_AUDCHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LP_AUDCHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_AUDCHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LP_AUDCHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_AUDCHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LP_AUDCHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_DNCCHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LP_DNCCHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_DNCCHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LP_DNCCHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_DNCCHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LP_DNCCHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LD_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LD_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LD_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LD_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LD_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LD_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_LD_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_SWEEPER_LD_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_LD_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SWEEPER_LD_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SWEEPER_LD_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SWEEPER_LD_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_CHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_CHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_CHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_CMGP_QCH_ENABLE, 0, 1, QCH_CON_APBIF_GPIO_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_GPIO_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_GPIO_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_GPIO_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMGP_CMU_CMGP_QCH_ENABLE, 0, 1, QCH_CON_CMGP_CMU_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMGP_CMU_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMGP_CMU_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMGP_CMU_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMGP_CMU_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_CMGP_I2C_QCH_ENABLE, 0, 1, QCH_CON_CMGP_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_CMGP_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMGP_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_CMGP_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMGP_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CMGP_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP2_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP2_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP3_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP3_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP4_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP4_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP4_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP4_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP4_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP4_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP5_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP5_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP5_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP5_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP5_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP5_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP6_QCH_ENABLE, 0, 1, QCH_CON_I2C_CMGP6_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP6_QCH_CLOCK_REQ, 1, 1, QCH_CON_I2C_CMGP6_QCH),
|
|
SFR_ACCESS(QCH_CON_I2C_CMGP6_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I2C_CMGP6_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_CMGP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LP_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LP_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LP_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_CMGPUFD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LP_CMGPUFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_CMGPUFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LP_CMGPUFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_CMGPUFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LP_CMGPUFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_I2C_CMGP0_QCH_ENABLE, 0, 1, QCH_CON_SPI_I2C_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_I2C_CMGP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPI_I2C_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_I2C_CMGP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPI_I2C_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_I2C_CMGP1_QCH_ENABLE, 0, 1, QCH_CON_SPI_I2C_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_I2C_CMGP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPI_I2C_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_I2C_CMGP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPI_I2C_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_MULTI_SLV_Q_CTRL_CMGP_QCH_ENABLE, 0, 1, QCH_CON_SPI_MULTI_SLV_Q_CTRL_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_MULTI_SLV_Q_CTRL_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPI_MULTI_SLV_Q_CTRL_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_MULTI_SLV_Q_CTRL_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPI_MULTI_SLV_Q_CTRL_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2APM_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CHUB_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CHUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CHUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2CHUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2CP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2GNSS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_AP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CMGP2PMU_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CMGP2PMU_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CMGP2PMU_AP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CMGP2PMU_AP_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP0_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP1_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP2_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP2_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP2_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP3_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP3_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP3_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP4_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP4_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP4_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP4_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP4_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP4_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP5_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP5_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP5_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP5_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP5_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP5_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP6_QCH_ENABLE, 0, 1, QCH_CON_USI_CMGP6_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP6_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI_CMGP6_QCH),
|
|
SFR_ACCESS(QCH_CON_USI_CMGP6_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI_CMGP6_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_TOP_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_TOP_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_TOP_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_TOP_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_TOP_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_TOP_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_CPUCL0_0_QCH_ENABLE, 0, 1, DMYQCH_CON_ADD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_CPUCL0_0_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_ADD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_ADD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_ADD_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_0_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_STR_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_STR_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_STR_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_ENABLE, 0, 1, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_STR_CPUCL0_0_QCH_CORE),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_QCH_CORE0_ENABLE, 0, 1, QCH_CON_CPUCL0_QCH_CORE0),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_QCH_CORE0_CLOCK_REQ, 1, 1, QCH_CON_CPUCL0_QCH_CORE0),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_QCH_CORE0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL0_QCH_CORE0),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_QCH_CORE1_ENABLE, 0, 1, QCH_CON_CPUCL0_QCH_CORE1),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_QCH_CORE1_CLOCK_REQ, 1, 1, QCH_CON_CPUCL0_QCH_CORE1),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_QCH_CORE1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL0_QCH_CORE1),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_QCH_CORE2_ENABLE, 0, 1, QCH_CON_CPUCL0_QCH_CORE2),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_QCH_CORE2_CLOCK_REQ, 1, 1, QCH_CON_CPUCL0_QCH_CORE2),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_QCH_CORE2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL0_QCH_CORE2),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_QCH_CORE3_ENABLE, 0, 1, QCH_CON_CPUCL0_QCH_CORE3),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_QCH_CORE3_CLOCK_REQ, 1, 1, QCH_CON_CPUCL0_QCH_CORE3),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_QCH_CORE3_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL0_QCH_CORE3),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_QCH_COMPLEX0_ENABLE, 0, 1, QCH_CON_CPUCL0_QCH_COMPLEX0),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_QCH_COMPLEX0_CLOCK_REQ, 1, 1, QCH_CON_CPUCL0_QCH_COMPLEX0),
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SFR_ACCESS(QCH_CON_CPUCL0_QCH_COMPLEX0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL0_QCH_COMPLEX0),
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SFR_ACCESS(QCH_CON_CPUCL0_QCH_COMPLEX1_ENABLE, 0, 1, QCH_CON_CPUCL0_QCH_COMPLEX1),
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SFR_ACCESS(QCH_CON_CPUCL0_QCH_COMPLEX1_CLOCK_REQ, 1, 1, QCH_CON_CPUCL0_QCH_COMPLEX1),
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|
SFR_ACCESS(QCH_CON_CPUCL0_QCH_COMPLEX1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL0_QCH_COMPLEX1),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH),
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SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH),
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SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_HTU_CPUCL0_QCH_PCLK_ENABLE, 0, 1, QCH_CON_HTU_CPUCL0_QCH_PCLK),
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SFR_ACCESS(QCH_CON_HTU_CPUCL0_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_CPUCL0_QCH_PCLK),
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SFR_ACCESS(QCH_CON_HTU_CPUCL0_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_CPUCL0_QCH_PCLK),
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|
SFR_ACCESS(QCH_CON_HTU_CPUCL0_QCH_CLK_ENABLE, 0, 1, QCH_CON_HTU_CPUCL0_QCH_CLK),
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SFR_ACCESS(QCH_CON_HTU_CPUCL0_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_CPUCL0_QCH_CLK),
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SFR_ACCESS(QCH_CON_HTU_CPUCL0_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_CPUCL0_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_DDCLIT_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_IT_DDCLIT_QCH),
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SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_DDCLIT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_IT_DDCLIT_QCH),
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SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_DDCLIT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_IT_DDCLIT_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_POWERIP_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CPUCL0_POWERIP_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_POWERIP_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CPUCL0_POWERIP_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_POWERIP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CPUCL0_POWERIP_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_HTU_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_HTU_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_HTU_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_HTU_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_HTU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_HTU_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_QCH),
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|
SFR_ACCESS(DMYQCH_CON_STR_CPUCL0_0_QCH_ENABLE, 0, 1, DMYQCH_CON_STR_CPUCL0_0_QCH),
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SFR_ACCESS(DMYQCH_CON_STR_CPUCL0_0_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_STR_CPUCL0_0_QCH),
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|
SFR_ACCESS(DMYQCH_CON_STR_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_STR_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_U_DDD_CTRL_CORE__CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_U_DDD_CTRL_CORE__CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_U_DDD_CTRL_CORE__CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_BPS_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_BPS_CPUCL0_QCH),
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|
SFR_ACCESS(QCH_CON_BPS_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BPS_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_BPS_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BPS_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_DDC_CPUCL0_0_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_DDC_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_DDC_CPUCL0_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_DDC_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_DDC_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_DDC_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_DDC_CPUCL0_1_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_DDC_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_DDC_CPUCL0_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_DDC_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_DDC_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_DDC_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_CFM_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_CFM_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_CFM_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_CFM_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_CFM_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CFM_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_ENABLE, 0, 1, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH),
|
|
SFR_ACCESS(QCH_CON_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_IT_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_IT_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_IT_CLUSTER0_QCH),
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|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_DDCBIG_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_IT_DDCBIG_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_DDCBIG_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_IT_DDCBIG_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_DDCBIG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_IT_DDCBIG_QCH),
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|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_DDCDSU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_IT_DDCDSU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_DDCDSU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_IT_DDCDSU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_DDCDSU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_IT_DDCDSU_QCH),
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|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_DDCLIT_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_IT_DDCLIT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_DDCLIT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_IT_DDCLIT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_DDCLIT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_IT_DDCLIT_QCH),
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|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_DDCMID0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_IT_DDCMID0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_DDCMID0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_IT_DDCMID0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_DDCMID0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_IT_DDCMID0_QCH),
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|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_DDCMID1_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_IT_DDCMID1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_DDCMID1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_IT_DDCMID1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_DDCMID1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_IT_DDCMID1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_DDCMID2_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_IT_DDCMID2_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_DDCMID2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_IT_DDCMID2_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_IT_DDCMID2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_IT_DDCMID2_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_T_BDU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_T_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_T_BDU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_T_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_T_BDU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_T_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_T_DDCG3D_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_T_DDCG3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_T_DDCG3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_T_DDCG3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MI_T_DDCG3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_T_DDCG3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_G_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_G_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_PCSM_PM_QCH_ENABLE, 0, 1, QCH_CON_PMU_PCSM_PM_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_PCSM_PM_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_PCSM_PM_QCH),
|
|
SFR_ACCESS(QCH_CON_PMU_PCSM_PM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PMU_PCSM_PM_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SECJTAG_QCH_ENABLE, 0, 1, QCH_CON_SECJTAG_QCH),
|
|
SFR_ACCESS(QCH_CON_SECJTAG_QCH_CLOCK_REQ, 1, 1, QCH_CON_SECJTAG_QCH),
|
|
SFR_ACCESS(QCH_CON_SECJTAG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SECJTAG_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_IG_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_IG_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_IG_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_IG_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_IG_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_IG_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_IG_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_IG_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_IG_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_IG_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_IG_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_IG_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_IG_ETR_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_IG_ETR_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_IG_ETR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_IG_ETR_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_IG_ETR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_IG_ETR_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_IG_STM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_IG_STM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_IG_STM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_IG_STM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_IG_STM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_IG_STM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_IG_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_IG_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_IG_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_IG_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_IG_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_IG_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_IG_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_IG_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_IG_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_IG_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_IG_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_IG_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_IG_ETR_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_IG_ETR_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_IG_ETR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_IG_ETR_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_IG_ETR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_IG_ETR_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_IG_STM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_IG_STM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_IG_STM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_IG_STM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_IG_STM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_IG_STM_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_TREX_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_CPUCL0_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_CPUCL0_1_QCH_ENABLE, 0, 1, DMYQCH_CON_ADD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_CPUCL0_1_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_ADD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_ADD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_ADD_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_1_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_STR_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_STR_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_STR_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_ENABLE, 0, 1, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_STR_CPUCL0_1_QCH_CORE),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_QCH_CORE4_ENABLE, 0, 1, QCH_CON_CPUCL1_QCH_CORE4),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_QCH_CORE4_CLOCK_REQ, 1, 1, QCH_CON_CPUCL1_QCH_CORE4),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_QCH_CORE4_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL1_QCH_CORE4),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_QCH_CORE5_ENABLE, 0, 1, QCH_CON_CPUCL1_QCH_CORE5),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_QCH_CORE5_CLOCK_REQ, 1, 1, QCH_CON_CPUCL1_QCH_CORE5),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_QCH_CORE5_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL1_QCH_CORE5),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_QCH_CORE6_ENABLE, 0, 1, QCH_CON_CPUCL1_QCH_CORE6),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_QCH_CORE6_CLOCK_REQ, 1, 1, QCH_CON_CPUCL1_QCH_CORE6),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_QCH_CORE6_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL1_QCH_CORE6),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_0_QCH_PCLK_ENABLE, 0, 1, QCH_CON_HTU_CPUCL1_0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_0_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_CPUCL1_0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_0_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_CPUCL1_0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_0_QCH_CLK_ENABLE, 0, 1, QCH_CON_HTU_CPUCL1_0_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_0_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_CPUCL1_0_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_0_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_CPUCL1_0_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_1_QCH_PCLK_ENABLE, 0, 1, QCH_CON_HTU_CPUCL1_1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_1_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_CPUCL1_1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_1_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_CPUCL1_1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_1_QCH_CLK_ENABLE, 0, 1, QCH_CON_HTU_CPUCL1_1_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_1_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_CPUCL1_1_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_1_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_CPUCL1_1_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_2_QCH_CLK_ENABLE, 0, 1, QCH_CON_HTU_CPUCL1_2_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_2_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_CPUCL1_2_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_2_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_CPUCL1_2_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_2_QCH_PCLK_ENABLE, 0, 1, QCH_CON_HTU_CPUCL1_2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_2_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_CPUCL1_2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL1_2_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_CPUCL1_2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_DDCMID0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_IT_DDCMID0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_DDCMID0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_IT_DDCMID0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_DDCMID0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_IT_DDCMID0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_DDCMID1_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_IT_DDCMID1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_DDCMID1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_IT_DDCMID1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_DDCMID1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_IT_DDCMID1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_DDCMID2_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_IT_DDCMID2_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_DDCMID2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_IT_DDCMID2_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_DDCMID2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_IT_DDCMID2_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL1_POWERIP_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CPUCL1_POWERIP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL1_POWERIP_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CPUCL1_POWERIP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL1_POWERIP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CPUCL1_POWERIP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_HTU_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_HTU_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_HTU_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_HTU_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_HTU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_HTU_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_STR_CPUCL0_1_QCH_ENABLE, 0, 1, DMYQCH_CON_STR_CPUCL0_1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_STR_CPUCL0_1_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_STR_CPUCL0_1_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_STR_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_STR_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__CPUCL1_0_QCH_ENABLE, 0, 1, QCH_CON_U_DDD_CTRL_CORE__CPUCL1_0_QCH),
|
|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__CPUCL1_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_U_DDD_CTRL_CORE__CPUCL1_0_QCH),
|
|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__CPUCL1_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_U_DDD_CTRL_CORE__CPUCL1_0_QCH),
|
|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__CPUCL1_1_QCH_ENABLE, 0, 1, QCH_CON_U_DDD_CTRL_CORE__CPUCL1_1_QCH),
|
|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__CPUCL1_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_U_DDD_CTRL_CORE__CPUCL1_1_QCH),
|
|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__CPUCL1_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_U_DDD_CTRL_CORE__CPUCL1_1_QCH),
|
|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__CPUCL1_2_QCH_ENABLE, 0, 1, QCH_CON_U_DDD_CTRL_CORE__CPUCL1_2_QCH),
|
|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__CPUCL1_2_QCH_CLOCK_REQ, 1, 1, QCH_CON_U_DDD_CTRL_CORE__CPUCL1_2_QCH),
|
|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__CPUCL1_2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_U_DDD_CTRL_CORE__CPUCL1_2_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_CPUCL0_2_QCH_ENABLE, 0, 1, DMYQCH_CON_ADD_CPUCL0_2_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_CPUCL0_2_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADD_CPUCL0_2_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADD_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_ADD_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_ADD_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_ADD_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_ADD_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_2_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_STR_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_STR_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_STR_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_ENABLE, 0, 1, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_STR_CPUCL0_2_QCH_CORE),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL2_QCH_CORE7_ENABLE, 0, 1, QCH_CON_CPUCL2_QCH_CORE7),
|
|
SFR_ACCESS(QCH_CON_CPUCL2_QCH_CORE7_CLOCK_REQ, 1, 1, QCH_CON_CPUCL2_QCH_CORE7),
|
|
SFR_ACCESS(QCH_CON_CPUCL2_QCH_CORE7_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL2_QCH_CORE7),
|
|
SFR_ACCESS(QCH_CON_CPUCL2_CMU_CPUCL2_QCH_ENABLE, 0, 1, QCH_CON_CPUCL2_CMU_CPUCL2_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL2_CMU_CPUCL2_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL2_CMU_CPUCL2_QCH),
|
|
SFR_ACCESS(QCH_CON_CPUCL2_CMU_CPUCL2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL2_CMU_CPUCL2_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL2_QCH_PCLK_ENABLE, 0, 1, QCH_CON_HTU_CPUCL2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL2_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_CPUCL2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL2_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_CPUCL2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL2_QCH_CLK_ENABLE, 0, 1, QCH_CON_HTU_CPUCL2_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL2_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_CPUCL2_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_CPUCL2_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_CPUCL2_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_DDCBIG_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_IT_DDCBIG_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_DDCBIG_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_IT_DDCBIG_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_DDCBIG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_IT_DDCBIG_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL2_POWERIP_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CPUCL2_POWERIP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL2_POWERIP_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CPUCL2_POWERIP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CPUCL2_POWERIP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CPUCL2_POWERIP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_HTU_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_HTU_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_HTU_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_HTU_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_HTU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_HTU_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_STR_CPUCL0_2_QCH_ENABLE, 0, 1, DMYQCH_CON_STR_CPUCL0_2_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_STR_CPUCL0_2_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_STR_CPUCL0_2_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_STR_CPUCL0_2_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_STR_CPUCL0_2_QCH),
|
|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__CPUCL2_QCH_ENABLE, 0, 1, QCH_CON_U_DDD_CTRL_CORE__CPUCL2_QCH),
|
|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__CPUCL2_QCH_CLOCK_REQ, 1, 1, QCH_CON_U_DDD_CTRL_CORE__CPUCL2_QCH),
|
|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__CPUCL2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_U_DDD_CTRL_CORE__CPUCL2_QCH),
|
|
SFR_ACCESS(QCH_CON_CSIS_CMU_CSIS_QCH_ENABLE, 0, 1, QCH_CON_CSIS_CMU_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_CSIS_CMU_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_CSIS_CMU_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_CSIS_CMU_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSIS_CMU_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CSIS_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LP_INT_P0P1_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LP_INT_P0P1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LP_INT_P0P1_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LP_INT_P0P1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LP_INT_P0P1_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LP_INT_P0P1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_UFD_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_UFD),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_UFD_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_UFD),
|
|
SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_UFD_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_UFD),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_OTF_CSISUFD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_OTF_CSISUFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_OTF_CSISUFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_OTF_CSISUFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_OTF_CSISUFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_OTF_CSISUFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_UFDCSIS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LP_UFDCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_UFDCSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LP_UFDCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_UFDCSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LP_UFDCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CSIS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_CSTAT_CMU_CSTAT_QCH_ENABLE, 0, 1, QCH_CON_CSTAT_CMU_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_CSTAT_CMU_CSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_CSTAT_CMU_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_CSTAT_CMU_CSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSTAT_CMU_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CSTAT_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_CSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_CSISCSTAT_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF0_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_CSISCSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF0_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF0_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_CSISCSTAT_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF1_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_CSISCSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF1_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF1_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF2_CSISCSTAT_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF2_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF2_CSISCSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF2_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF2_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF2_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF3_CSISCSTAT_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF3_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF3_CSISCSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF3_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF3_CSISCSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF3_CSISCSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_CSTAT_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_CSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D_CSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CSTAT_QCH_ENABLE, 0, 1, QCH_CON_PPMU_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_SIPU_CSTAT_QCH_ENABLE, 0, 1, QCH_CON_SIPU_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_SIPU_CSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIPU_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_SIPU_CSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIPU_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_SIPU_CSTAT_QCH_C2RD_ENABLE, 0, 1, QCH_CON_SIPU_CSTAT_QCH_C2RD),
|
|
SFR_ACCESS(QCH_CON_SIPU_CSTAT_QCH_C2RD_CLOCK_REQ, 1, 1, QCH_CON_SIPU_CSTAT_QCH_C2RD),
|
|
SFR_ACCESS(QCH_CON_SIPU_CSTAT_QCH_C2RD_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIPU_CSTAT_QCH_C2RD),
|
|
SFR_ACCESS(QCH_CON_SIPU_CSTAT_QCH_C2DS_ENABLE, 0, 1, QCH_CON_SIPU_CSTAT_QCH_C2DS),
|
|
SFR_ACCESS(QCH_CON_SIPU_CSTAT_QCH_C2DS_CLOCK_REQ, 1, 1, QCH_CON_SIPU_CSTAT_QCH_C2DS),
|
|
SFR_ACCESS(QCH_CON_SIPU_CSTAT_QCH_C2DS_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIPU_CSTAT_QCH_C2DS),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_CSTAT_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_CSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_CSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CSTAT_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_CSTAT_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D_CSTAT_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_CSTAT_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_CSTAT_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_CSTAT_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_CSTAT_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_CSTAT_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D_CSTAT_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_CSTAT_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_CSTAT_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_CSTAT_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_CSTAT_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CSTAT_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_CSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_CSTAT0_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_CSTAT0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_CSTAT0_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_CSTAT0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_CSTAT0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_CSTAT0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_CSTAT1_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_CSTAT1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_CSTAT1_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_CSTAT1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_CSTAT1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_CSTAT1_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_S2D_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_APBIF_S2D_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_S2D_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_S2D_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_APBIF_S2D_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_S2D_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_ASYNCAHBMASTER_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_ASYNCAHBMASTER_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_ASYNCAHBMASTER_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_ASYNCAHBMASTER_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_ASYNCAHBMASTER_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASYNCAHBMASTER_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_DBGCORE_CMU_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_DBGCORE_CMU_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_DBGCORE_CMU_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_DBGCORE_CMU_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_DBGCORE_CMU_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DBGCORE_CMU_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_DBG_ENABLE, 0, 1, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_DBG_CLOCK_REQ, 1, 1, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_DBG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_DBG),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_GREBE_ENABLE, 0, 1, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_GREBE_CLOCK_REQ, 1, 1, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_GREBE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_GREBE),
|
|
SFR_ACCESS(QCH_CON_MDIS_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_MDIS_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_MDIS_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_MDIS_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_MDIS_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MDIS_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_MDIS_DBGCORE_QCH_OSC_ENABLE, 0, 1, QCH_CON_MDIS_DBGCORE_QCH_OSC),
|
|
SFR_ACCESS(QCH_CON_MDIS_DBGCORE_QCH_OSC_CLOCK_REQ, 1, 1, QCH_CON_MDIS_DBGCORE_QCH_OSC),
|
|
SFR_ACCESS(QCH_CON_MDIS_DBGCORE_QCH_OSC_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MDIS_DBGCORE_QCH_OSC),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_DBGCORE_GREBE_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_DBGCORE_GREBE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_DBGCORE_GREBE_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_DBGCORE_GREBE_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_DBGCORE_GREBE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_DBGCORE_GREBE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_IP_APM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_IP_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_IP_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_IP_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_IP_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_IP_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_ID_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_ID_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_ID_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_ID_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_ID_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_ID_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DBGCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DBGCORE_CORE_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DBGCORE_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DBGCORE_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DBGCORE_CORE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DBGCORE_CORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DBGCORE_CORE_QCH),
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SFR_ACCESS(QCH_CON_WDT_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_WDT_DBGCORE_QCH),
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SFR_ACCESS(QCH_CON_WDT_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_DBGCORE_QCH),
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SFR_ACCESS(QCH_CON_WDT_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_DBGCORE_QCH),
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|
SFR_ACCESS(DMYQCH_CON_ADD_DNC_QCH_ENABLE, 0, 1, DMYQCH_CON_ADD_DNC_QCH),
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|
SFR_ACCESS(DMYQCH_CON_ADD_DNC_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADD_DNC_QCH),
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SFR_ACCESS(DMYQCH_CON_ADD_DNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADD_DNC_QCH),
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SFR_ACCESS(DMYQCH_CON_ADM_DAP_DNC_QCH_ENABLE, 0, 1, DMYQCH_CON_ADM_DAP_DNC_QCH),
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SFR_ACCESS(DMYQCH_CON_ADM_DAP_DNC_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADM_DAP_DNC_QCH),
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SFR_ACCESS(DMYQCH_CON_ADM_DAP_DNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADM_DAP_DNC_QCH),
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|
SFR_ACCESS(QCH_CON_BAAW_DNCCHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_BAAW_DNCCHUBVTS_QCH),
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SFR_ACCESS(QCH_CON_BAAW_DNCCHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_DNCCHUBVTS_QCH),
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|
SFR_ACCESS(QCH_CON_BAAW_DNCCHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_DNCCHUBVTS_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_ADD_DNC_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_ADD_DNC_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_ADD_DNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_ADD_DNC_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_ADD_DNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_ADD_DNC_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_DDD_DNC_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_DDD_DNC_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_DDD_DNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_DDD_DNC_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_DDD_DNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_DDD_DNC_QCH),
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|
SFR_ACCESS(QCH_CON_DNC_CMU_DNC_QCH_ENABLE, 0, 1, QCH_CON_DNC_CMU_DNC_QCH),
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|
SFR_ACCESS(QCH_CON_DNC_CMU_DNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_DNC_CMU_DNC_QCH),
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SFR_ACCESS(QCH_CON_DNC_CMU_DNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DNC_CMU_DNC_QCH),
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SFR_ACCESS(QCH_CON_D_TZPC_DNC_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_DNC_QCH),
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|
SFR_ACCESS(QCH_CON_D_TZPC_DNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_DNC_QCH),
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SFR_ACCESS(QCH_CON_D_TZPC_DNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_DNC_QCH),
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|
SFR_ACCESS(QCH_CON_HTU_DNC_QCH_PCLK_ENABLE, 0, 1, QCH_CON_HTU_DNC_QCH_PCLK),
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|
SFR_ACCESS(QCH_CON_HTU_DNC_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_DNC_QCH_PCLK),
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|
SFR_ACCESS(QCH_CON_HTU_DNC_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_DNC_QCH_PCLK),
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|
SFR_ACCESS(QCH_CON_HTU_DNC_QCH_CLK_ENABLE, 0, 1, QCH_CON_HTU_DNC_QCH_CLK),
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|
SFR_ACCESS(QCH_CON_HTU_DNC_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_DNC_QCH_CLK),
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|
SFR_ACCESS(QCH_CON_HTU_DNC_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_DNC_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_IP_DNC_QCH_ENABLE, 0, 1, QCH_CON_IP_DNC_QCH),
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|
SFR_ACCESS(QCH_CON_IP_DNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_IP_DNC_QCH),
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|
SFR_ACCESS(QCH_CON_IP_DNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_UFDDNC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF_UFDDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_UFDDNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF_UFDDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_UFDDNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF_UFDDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_DSP0DNC_SFR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_DSP0DNC_SFR_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_DSP0DNC_SFR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_DSP0DNC_SFR_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_DSP0DNC_SFR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_DSP0DNC_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_DSP0DNC_SHMEM_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_DSP0DNC_SHMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_DSP0DNC_SHMEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_DSP0DNC_SHMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_DSP0DNC_SHMEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_DSP0DNC_SHMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_GNPU0DNC_SHMEM_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_GNPU0DNC_SHMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_GNPU0DNC_SHMEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_GNPU0DNC_SHMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_GNPU0DNC_SHMEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_GNPU0DNC_SHMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_GNPU1DNC_SHMEM_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_GNPU1DNC_SHMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_GNPU1DNC_SHMEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_GNPU1DNC_SHMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_GNPU1DNC_SHMEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_GNPU1DNC_SHMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_RQ_GNPU0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_RQ_GNPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_RQ_GNPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_RQ_GNPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_RQ_GNPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_RQ_GNPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_RQ_GNPU1_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_RQ_GNPU1_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_RQ_GNPU1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_RQ_GNPU1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_RQ_GNPU1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_RQ_GNPU1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA0_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA0_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA0_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA1_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA1_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA1_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA1_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA2_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA2_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA2_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA2_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA3_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA3_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA3_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA3_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA3_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA4_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA4_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA4_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA4_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA4_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA4_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA5_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA5_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA5_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA5_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA5_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA5_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA6_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA6_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA6_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA6_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA6_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA6_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA7_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA7_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA7_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA7_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA7_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_DATA7_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU1_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU2_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU2_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU2_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU2_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU3_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU3_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU3_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU3_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_SDMADNC_MMU3_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LP_IPDNC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LP_IPDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LP_IPDNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LP_IPDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LP_IPDNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LP_IPDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD0_GNPU0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD0_GNPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD0_GNPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD0_GNPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD0_GNPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD0_GNPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD0_GNPU1_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD0_GNPU1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD0_GNPU1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD0_GNPU1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD0_GNPU1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD0_GNPU1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD1_GNPU0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD1_GNPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD1_GNPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD1_GNPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD1_GNPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD1_GNPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD1_GNPU1_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD1_GNPU1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD1_GNPU1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD1_GNPU1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD1_GNPU1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD1_GNPU1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_CTRL_GNPU0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_CTRL_GNPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_CTRL_GNPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_CTRL_GNPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_CTRL_GNPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_CTRL_GNPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_CTRL_GNPU1_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_CTRL_GNPU1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_CTRL_GNPU1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_CTRL_GNPU1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_CTRL_GNPU1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_CTRL_GNPU1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_DNCDSP0_DMA_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_DNCDSP0_DMA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_DNCDSP0_DMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_DNCDSP0_DMA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_DNCDSP0_DMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_DNCDSP0_DMA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_DNCDSP0_SFR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_DNCDSP0_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_DNCDSP0_SFR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_DNCDSP0_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_DNCDSP0_SFR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_DNCDSP0_SFR_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LP_DNCSDMA_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LP_DNCSDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LP_DNCSDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LP_DNCSDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LP_DNCSDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LP_DNCSDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LP_IPDNC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LP_IPDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LP_IPDNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LP_IPDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LP_IPDNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LP_IPDNC_QCH),
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|
SFR_ACCESS(QCH_CON_PPMU_IPDNC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_IPDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_IPDNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_IPDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_IPDNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_IPDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_SDMA0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_SDMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_SDMA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_SDMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_SDMA0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_SDMA0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_SDMA1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_SDMA1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_SDMA1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_SDMA1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_SDMA1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_SDMA1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_SDMA2_QCH_ENABLE, 0, 1, QCH_CON_PPMU_SDMA2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_SDMA2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_SDMA2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_SDMA2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_SDMA2_QCH),
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|
SFR_ACCESS(QCH_CON_PPMU_SDMA3_QCH_ENABLE, 0, 1, QCH_CON_PPMU_SDMA3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_SDMA3_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_SDMA3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_SDMA3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_SDMA3_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_G_PPMU_DNC_QCH_ENABLE, 0, 1, QCH_CON_SIU_G_PPMU_DNC_QCH),
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|
SFR_ACCESS(QCH_CON_SIU_G_PPMU_DNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIU_G_PPMU_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_G_PPMU_DNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIU_G_PPMU_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_DNC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_DNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_DNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_DNC_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU0_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU0_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU1_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LD_CMDQ_GNPU1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_DSP0DNC_CACHE_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LD_DSP0DNC_CACHE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_DSP0DNC_CACHE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LD_DSP0DNC_CACHE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_DSP0DNC_CACHE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LD_DSP0DNC_CACHE_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_UFDDNC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LD_UFDDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_UFDDNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LD_UFDDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_UFDDNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LD_UFDDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_ALIVEDNC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LP_ALIVEDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_ALIVEDNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LP_ALIVEDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_ALIVEDNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LP_ALIVEDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DNC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_DNCCHUBVTS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LP_DNCCHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_DNCCHUBVTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LP_DNCCHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_DNCCHUBVTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LP_DNCCHUBVTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_DSP0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LP_DSP0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_DSP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LP_DSP0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_DSP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LP_DSP0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_GNPU0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LP_GNPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_GNPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LP_GNPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_GNPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LP_GNPU0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_GNPU1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LP_GNPU1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_GNPU1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LP_GNPU1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_GNPU1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LP_GNPU1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_SDMA_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LP_SDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_SDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LP_SDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_SDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LP_SDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_IPDNC_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_IPDNC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_IPDNC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_IPDNC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_IPDNC_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_IPDNC_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_IPDNC_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_IPDNC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_IPDNC_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_IPDNC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_IPDNC_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_IPDNC_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA0_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_SDMA0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA0_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_SDMA0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA0_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_SDMA0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA0_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_SDMA0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA0_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_SDMA0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA0_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_SDMA0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA1_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_SDMA1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA1_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_SDMA1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA1_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_SDMA1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA1_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_SDMA1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA1_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_SDMA1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA1_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_SDMA1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA2_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_SDMA2_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA2_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_SDMA2_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA2_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_SDMA2_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA2_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_SDMA2_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA2_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_SDMA2_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA2_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_SDMA2_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA3_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_SDMA3_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA3_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_SDMA3_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA3_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_SDMA3_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA3_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_SDMA3_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA3_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_SDMA3_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SDMA3_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_SDMA3_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DNC_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_DNC_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_DNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_DNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_DNC_QCH_ENABLE, 0, 1, QCH_CON_VGEN_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_DNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_DNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_DNC_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_DNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_DNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_DECON_ENABLE, 0, 1, QCH_CON_DPUB_QCH_DECON),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_DECON_CLOCK_REQ, 1, 1, QCH_CON_DPUB_QCH_DECON),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_DECON_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUB_QCH_DECON),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_ALV_DSIM0_ENABLE, 0, 1, QCH_CON_DPUB_QCH_ALV_DSIM0),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_ALV_DSIM0_CLOCK_REQ, 1, 1, QCH_CON_DPUB_QCH_ALV_DSIM0),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_ALV_DSIM0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUB_QCH_ALV_DSIM0),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_ALV_DSIM1_ENABLE, 0, 1, QCH_CON_DPUB_QCH_ALV_DSIM1),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_ALV_DSIM1_CLOCK_REQ, 1, 1, QCH_CON_DPUB_QCH_ALV_DSIM1),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_ALV_DSIM1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUB_QCH_ALV_DSIM1),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_ALV_DSIM2_ENABLE, 0, 1, QCH_CON_DPUB_QCH_ALV_DSIM2),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_ALV_DSIM2_CLOCK_REQ, 1, 1, QCH_CON_DPUB_QCH_ALV_DSIM2),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_ALV_DSIM2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUB_QCH_ALV_DSIM2),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_OSC_DSIM0_ENABLE, 0, 1, QCH_CON_DPUB_QCH_OSC_DSIM0),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_OSC_DSIM0_CLOCK_REQ, 1, 1, QCH_CON_DPUB_QCH_OSC_DSIM0),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_OSC_DSIM0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUB_QCH_OSC_DSIM0),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_OSC_DSIM1_ENABLE, 0, 1, QCH_CON_DPUB_QCH_OSC_DSIM1),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_OSC_DSIM1_CLOCK_REQ, 1, 1, QCH_CON_DPUB_QCH_OSC_DSIM1),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_OSC_DSIM1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUB_QCH_OSC_DSIM1),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_OSC_DSIM2_ENABLE, 0, 1, QCH_CON_DPUB_QCH_OSC_DSIM2),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_OSC_DSIM2_CLOCK_REQ, 1, 1, QCH_CON_DPUB_QCH_OSC_DSIM2),
|
|
SFR_ACCESS(QCH_CON_DPUB_QCH_OSC_DSIM2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUB_QCH_OSC_DSIM2),
|
|
SFR_ACCESS(QCH_CON_DPUB_CMU_DPUB_QCH_ENABLE, 0, 1, QCH_CON_DPUB_CMU_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUB_CMU_DPUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_DPUB_CMU_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUB_CMU_DPUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUB_CMU_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUB_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DPUB_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DPUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DPUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUB_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DPUB_QCH),
|
|
SFR_ACCESS(QCH_CON_UPI_M0_QCH_ENABLE, 0, 1, QCH_CON_UPI_M0_QCH),
|
|
SFR_ACCESS(QCH_CON_UPI_M0_QCH_CLOCK_REQ, 1, 1, QCH_CON_UPI_M0_QCH),
|
|
SFR_ACCESS(QCH_CON_UPI_M0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UPI_M0_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUF_QCH_DPUF0_ENABLE, 0, 1, QCH_CON_DPUF_QCH_DPUF0),
|
|
SFR_ACCESS(QCH_CON_DPUF_QCH_DPUF0_CLOCK_REQ, 1, 1, QCH_CON_DPUF_QCH_DPUF0),
|
|
SFR_ACCESS(QCH_CON_DPUF_QCH_DPUF0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUF_QCH_DPUF0),
|
|
SFR_ACCESS(QCH_CON_DPUF_QCH_VOTF0_ENABLE, 0, 1, QCH_CON_DPUF_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_DPUF_QCH_VOTF0_CLOCK_REQ, 1, 1, QCH_CON_DPUF_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_DPUF_QCH_VOTF0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUF_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_DPUF_QCH_DPUF1_ENABLE, 0, 1, QCH_CON_DPUF_QCH_DPUF1),
|
|
SFR_ACCESS(QCH_CON_DPUF_QCH_DPUF1_CLOCK_REQ, 1, 1, QCH_CON_DPUF_QCH_DPUF1),
|
|
SFR_ACCESS(QCH_CON_DPUF_QCH_DPUF1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUF_QCH_DPUF1),
|
|
SFR_ACCESS(QCH_CON_DPUF_QCH_VOTF1_ENABLE, 0, 1, QCH_CON_DPUF_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_DPUF_QCH_VOTF1_CLOCK_REQ, 1, 1, QCH_CON_DPUF_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_DPUF_QCH_VOTF1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUF_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_DPUF_QCH_SRAMC_ENABLE, 0, 1, QCH_CON_DPUF_QCH_SRAMC),
|
|
SFR_ACCESS(QCH_CON_DPUF_QCH_SRAMC_CLOCK_REQ, 1, 1, QCH_CON_DPUF_QCH_SRAMC),
|
|
SFR_ACCESS(QCH_CON_DPUF_QCH_SRAMC_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUF_QCH_SRAMC),
|
|
SFR_ACCESS(QCH_CON_DPUF_CMU_DPUF_QCH_ENABLE, 0, 1, QCH_CON_DPUF_CMU_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUF_CMU_DPUF_QCH_CLOCK_REQ, 1, 1, QCH_CON_DPUF_CMU_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUF_CMU_DPUF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUF_CMU_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUF_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUF_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUF1_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DPUF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_DPUF_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_DPUF_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_DPUF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_DPUF0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_DPUF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_DPUF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_DPUF1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_DPUF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_DPUF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_DPUF0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_DPUF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_DPUF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_DPUF1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_DPUF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_DPUF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_DPUF_QCH_ENABLE, 0, 1, QCH_CON_SIU_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_DPUF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIU_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_DPUF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIU_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_DPUF_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_DPUF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_DPUF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DPUF_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DPUF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DPUF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D0_DPUF_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_D0_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D0_DPUF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_D0_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D0_DPUF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_D0_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DPUF0_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_DPUF0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DPUF0_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_DPUF0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DPUF0_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_DPUF0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DPUF0_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_DPUF0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DPUF0_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_DPUF0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DPUF0_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_DPUF0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DPUF1_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_DPUF1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DPUF1_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_DPUF1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DPUF1_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_DPUF1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DPUF1_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_DPUF1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DPUF1_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_DPUF1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_DPUF1_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_DPUF1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DPUF0_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_DPUF0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DPUF0_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_DPUF0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DPUF0_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_DPUF0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DPUF0_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_DPUF0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DPUF0_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_DPUF0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DPUF0_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_DPUF0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DPUF1_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_DPUF1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DPUF1_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_DPUF1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DPUF1_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_DPUF1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DPUF1_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_DPUF1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DPUF1_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_DPUF1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_DPUF1_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_DPUF1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUF_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUF1_QCH_DPUF_ENABLE, 0, 1, QCH_CON_DPUF1_QCH_DPUF),
|
|
SFR_ACCESS(QCH_CON_DPUF1_QCH_DPUF_CLOCK_REQ, 1, 1, QCH_CON_DPUF1_QCH_DPUF),
|
|
SFR_ACCESS(QCH_CON_DPUF1_QCH_DPUF_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUF1_QCH_DPUF),
|
|
SFR_ACCESS(QCH_CON_DPUF1_QCH_VOTF_ENABLE, 0, 1, QCH_CON_DPUF1_QCH_VOTF),
|
|
SFR_ACCESS(QCH_CON_DPUF1_QCH_VOTF_CLOCK_REQ, 1, 1, QCH_CON_DPUF1_QCH_VOTF),
|
|
SFR_ACCESS(QCH_CON_DPUF1_QCH_VOTF_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUF1_QCH_VOTF),
|
|
SFR_ACCESS(QCH_CON_DPUF1_CMU_DPUF1_QCH_ENABLE, 0, 1, QCH_CON_DPUF1_CMU_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUF1_CMU_DPUF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_DPUF1_CMU_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_DPUF1_CMU_DPUF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUF1_CMU_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_DPUF1DPUF0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_DPUF1DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_DPUF1DPUF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_DPUF1DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_DPUF1DPUF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_DPUF1DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_DPUF1DPUF0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_DPUF1DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_DPUF1DPUF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_DPUF1DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_DPUF1DPUF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_DPUF1DPUF0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF1D0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_DPUF1D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF1D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_DPUF1D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF1D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_DPUF1D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF1D1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_DPUF1D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF1D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_DPUF1D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DPUF1D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_DPUF1D1_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_DPUF1_QCH_ENABLE, 0, 1, QCH_CON_SIU_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_DPUF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIU_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_DPUF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIU_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_ASTL_SI_G_PPMU_DPUF1_QCH_ENABLE, 0, 1, QCH_CON_SLH_ASTL_SI_G_PPMU_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_ASTL_SI_G_PPMU_DPUF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_ASTL_SI_G_PPMU_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_ASTL_SI_G_PPMU_DPUF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_ASTL_SI_G_PPMU_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DPUF1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DPUF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DPUF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D0_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUF1D0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D0_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUF1D0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D0_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUF1D0_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D0_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUF1D0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D0_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUF1D0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D0_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUF1D0_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D1_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUF1D1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D1_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUF1D1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D1_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUF1D1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D1_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUF1D1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D1_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUF1D1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_DPUF1D1_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUF1D1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUF1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_DPUF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DPUF1_QCH),
|
|
SFR_ACCESS(QCH_CON_DRCP_QCH_ENABLE, 0, 1, QCH_CON_DRCP_QCH),
|
|
SFR_ACCESS(QCH_CON_DRCP_QCH_CLOCK_REQ, 1, 1, QCH_CON_DRCP_QCH),
|
|
SFR_ACCESS(QCH_CON_DRCP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DRCP_QCH),
|
|
SFR_ACCESS(QCH_CON_DRCP_CMU_DRCP_QCH_ENABLE, 0, 1, QCH_CON_DRCP_CMU_DRCP_QCH),
|
|
SFR_ACCESS(QCH_CON_DRCP_CMU_DRCP_QCH_CLOCK_REQ, 1, 1, QCH_CON_DRCP_CMU_DRCP_QCH),
|
|
SFR_ACCESS(QCH_CON_DRCP_CMU_DRCP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DRCP_CMU_DRCP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DRCP_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_DRCP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DRCP_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_DRCP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_DRCP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_DRCP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_YUVPDRCP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF_YUVPDRCP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_YUVPDRCP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF_YUVPDRCP_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_YUVPDRCP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF_YUVPDRCP_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_DRCPMCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF_DRCPMCSC_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_DRCPMCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF_DRCPMCSC_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_DRCPMCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF_DRCPMCSC_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_D_DRCP_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_DRCP_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_D_DRCP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_DRCP_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_D_DRCP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_DRCP_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D_DRCP_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D_DRCP_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D_DRCP_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D_DRCP_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D_DRCP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D_DRCP_QCH),
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SFR_ACCESS(QCH_CON_SLH_ASTL_SI_G_PPMU_DRCP_QCH_ENABLE, 0, 1, QCH_CON_SLH_ASTL_SI_G_PPMU_DRCP_QCH),
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SFR_ACCESS(QCH_CON_SLH_ASTL_SI_G_PPMU_DRCP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_ASTL_SI_G_PPMU_DRCP_QCH),
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SFR_ACCESS(QCH_CON_SLH_ASTL_SI_G_PPMU_DRCP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_ASTL_SI_G_PPMU_DRCP_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DRCP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_DRCP_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DRCP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_DRCP_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DRCP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_DRCP_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_D_DRCP_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D_DRCP_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_D_DRCP_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_DRCP_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_D_DRCP_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_DRCP_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_D_DRCP_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D_DRCP_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_D_DRCP_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_DRCP_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_D_DRCP_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_DRCP_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSREG_DRCP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DRCP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_DRCP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DRCP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_DRCP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DRCP_QCH),
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SFR_ACCESS(QCH_CON_VGEN_LITE_D_DRCP_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D_DRCP_QCH),
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SFR_ACCESS(QCH_CON_VGEN_LITE_D_DRCP_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D_DRCP_QCH),
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SFR_ACCESS(QCH_CON_VGEN_LITE_D_DRCP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D_DRCP_QCH),
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SFR_ACCESS(QCH_CON_DSP_CMU_DSP_QCH_ENABLE, 0, 1, QCH_CON_DSP_CMU_DSP_QCH),
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SFR_ACCESS(QCH_CON_DSP_CMU_DSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_DSP_CMU_DSP_QCH),
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SFR_ACCESS(QCH_CON_DSP_CMU_DSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DSP_CMU_DSP_QCH),
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SFR_ACCESS(QCH_CON_D_TZPC_DSP_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_DSP_QCH),
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SFR_ACCESS(QCH_CON_D_TZPC_DSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_DSP_QCH),
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SFR_ACCESS(QCH_CON_D_TZPC_DSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_DSP_QCH),
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SFR_ACCESS(QCH_CON_IP_DSP_QCH_ENABLE, 0, 1, QCH_CON_IP_DSP_QCH),
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SFR_ACCESS(QCH_CON_IP_DSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_IP_DSP_QCH),
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SFR_ACCESS(QCH_CON_IP_DSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_DSP_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_LD_STRM_SDMADSP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_LD_STRM_SDMADSP_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_LD_STRM_SDMADSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_LD_STRM_SDMADSP_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_LD_STRM_SDMADSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_LD_STRM_SDMADSP_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_DNCDSP_DMA_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_DNCDSP_DMA_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_DNCDSP_DMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_DNCDSP_DMA_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_DNCDSP_DMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_DNCDSP_DMA_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_DNCDSP_SFR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_DNCDSP_SFR_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_DNCDSP_SFR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_DNCDSP_SFR_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_DNCDSP_SFR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_DNCDSP_SFR_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_DSPDNC_SFR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_DSPDNC_SFR_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_DSPDNC_SFR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_DSPDNC_SFR_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_DSPDNC_SFR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_DSPDNC_SFR_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_DSPDNC_SHMEM_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_DSPDNC_SHMEM_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_DSPDNC_SHMEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_DSPDNC_SHMEM_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_DSPDNC_SHMEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_DSPDNC_SHMEM_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_DSP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LP_DSP_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_DSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LP_DSP_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_DSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LP_DSP_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_LD_DSPDNC_CACHE_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LD_DSPDNC_CACHE_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_LD_DSPDNC_CACHE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LD_DSPDNC_CACHE_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_LD_DSPDNC_CACHE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LD_DSPDNC_CACHE_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_DSP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DSP_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_DSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DSP_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_DSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DSP_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_3_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_STR_CPUCL0_3_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_STR_CPUCL0_3_QCH),
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SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_STR_CPUCL0_3_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_ENABLE, 0, 1, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE),
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|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE),
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|
SFR_ACCESS(QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_STR_CPUCL0_3_QCH_CORE),
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SFR_ACCESS(QCH_CON_CLUSTER0_QCH_SCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_SCLK),
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|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_SCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_SCLK),
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|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_SCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_SCLK),
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|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_ATCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_ATCLK),
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|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_ATCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_ATCLK),
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|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_ATCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_ATCLK),
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|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PDBGCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_PDBGCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PDBGCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_PDBGCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PDBGCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_PDBGCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PERIPHCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_PERIPHCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PERIPHCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_PERIPHCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PERIPHCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_PERIPHCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PPUCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_PPUCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PPUCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_PPUCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PPUCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_PPUCLK),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_GIC_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_GIC),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_GIC_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_GIC),
|
|
SFR_ACCESS(QCH_CON_CLUSTER0_QCH_GIC_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_GIC),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_DSU_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_DSU_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_DSU_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_DSU_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_DSU_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_DSU_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_DSU_CMU_DSU_QCH_ENABLE, 0, 1, QCH_CON_DSU_CMU_DSU_QCH),
|
|
SFR_ACCESS(QCH_CON_DSU_CMU_DSU_QCH_CLOCK_REQ, 1, 1, QCH_CON_DSU_CMU_DSU_QCH),
|
|
SFR_ACCESS(QCH_CON_DSU_CMU_DSU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DSU_CMU_DSU_QCH),
|
|
SFR_ACCESS(QCH_CON_HTU_DSU_QCH_PCLK_ENABLE, 0, 1, QCH_CON_HTU_DSU_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_DSU_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_DSU_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_DSU_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_DSU_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_DSU_QCH_CLK_ENABLE, 0, 1, QCH_CON_HTU_DSU_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_DSU_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_DSU_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_DSU_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_DSU_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D0_ACP_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D0_ACP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D0_ACP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D0_ACP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D0_ACP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D0_ACP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D1_ACP_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D1_ACP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D1_ACP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D1_ACP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D1_ACP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D1_ACP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_IT_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_IT_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_IT_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_DDCDSU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_IT_DDCDSU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_DDCDSU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_IT_DDCDSU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_IT_DDCDSU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_IT_DDCDSU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_CHI_SI_D0_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_CHI_SI_D0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_CHI_SI_D0_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_CHI_SI_D0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_CHI_SI_D0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_CHI_SI_D0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_CHI_SI_D1_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_CHI_SI_D1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_CHI_SI_D1_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_CHI_SI_D1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_CHI_SI_D1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_CHI_SI_D1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_ENABLE, 0, 1, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_ENABLE, 0, 1, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_ENABLE, 0, 1, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH),
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SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH),
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SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH),
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SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_ENABLE, 0, 1, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH),
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|
SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_ACLK_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_ACLK_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_ACLK_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_ACLK_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_ACLK_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_ACLK_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_ATCLK_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_ATCLK_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_ATCLK_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_ATCLK_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_ATCLK_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_ATCLK_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_GICCLK_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_GICCLK_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_GICCLK_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_GICCLK_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_GICCLK_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_GICCLK_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_MPACTCLK_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_MPACTCLK_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_MPACTCLK_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_MPACTCLK_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_MPACTCLK_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_MPACTCLK_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_PCLK_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_PCLK_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_PCLK_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_PCLK_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_PCLK_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_PCLK_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_PPUCLK_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_PPUCLK_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_PPUCLK_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_PPUCLK_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_PPUCLK_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_PPUCLK_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_SCLK_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_SCLK_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_SCLK_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_SCLK_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_CLUSTER_SCLK_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_CLUSTER_SCLK_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_DSU_POWERIP_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_DSU_POWERIP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_DSU_POWERIP_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_DSU_POWERIP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_DSU_POWERIP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_DSU_POWERIP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_DSU_HTU_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_DSU_HTU_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_DSU_HTU_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_DSU_HTU_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_DSU_HTU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_DSU_HTU_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_DSU_POWERIP_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_DSU_POWERIP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_DSU_POWERIP_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_DSU_POWERIP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_DSU_POWERIP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_DSU_POWERIP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_IP_UTILITY_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_IP_UTILITY_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_IP_UTILITY_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_IP_UTILITY_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_IP_UTILITY_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_IP_UTILITY_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_PPU_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LP_PPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_PPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LP_PPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_PPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LP_PPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_IP_UTILITY_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_IP_UTILITY_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_IP_UTILITY_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_IP_UTILITY_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_IP_UTILITY_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_IP_UTILITY_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CLUSTER0_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_CLUSTER0_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CLUSTER0_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_CLUSTER0_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CLUSTER0_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_CLUSTER0_NOCL0_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_STR_CPUCL0_3_QCH_ENABLE, 0, 1, DMYQCH_CON_STR_CPUCL0_3_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_STR_CPUCL0_3_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_STR_CPUCL0_3_QCH),
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|
SFR_ACCESS(DMYQCH_CON_STR_CPUCL0_3_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_STR_CPUCL0_3_QCH),
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|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__DSU_QCH_ENABLE, 0, 1, QCH_CON_U_DDD_CTRL_CORE__DSU_QCH),
|
|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__DSU_QCH_CLOCK_REQ, 1, 1, QCH_CON_U_DDD_CTRL_CORE__DSU_QCH),
|
|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__DSU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_U_DDD_CTRL_CORE__DSU_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_BG3D_PWRCTL_QCH_ENABLE, 0, 1, DMYQCH_CON_BG3D_PWRCTL_QCH),
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|
SFR_ACCESS(DMYQCH_CON_BG3D_PWRCTL_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_BG3D_PWRCTL_QCH),
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|
SFR_ACCESS(DMYQCH_CON_BG3D_PWRCTL_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_BG3D_PWRCTL_QCH),
|
|
SFR_ACCESS(QCH_CON_CFM_G3D_QCH_ENABLE, 0, 1, QCH_CON_CFM_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_CFM_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_CFM_G3D_QCH),
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|
SFR_ACCESS(QCH_CON_CFM_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CFM_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_G3D_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_ENABLE, 0, 1, QCH_CON_G3D_CMU_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_G3D_CMU_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_G3D_CMU_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_G3D_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_INT_G3D_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_INT_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_INT_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_INT_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_INT_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_INT_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_ADD_APBIF_G3D_QCH_ENABLE, 0, 1, QCH_CON_ADD_APBIF_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_ADD_APBIF_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_ADD_APBIF_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_ADD_APBIF_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ADD_APBIF_G3D_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_G3D_QCH_ENABLE, 0, 1, DMYQCH_CON_ADD_G3D_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_G3D_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADD_G3D_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADD_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADD_G3D_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_DAP_G_G3D_QCH_ENABLE, 0, 1, DMYQCH_CON_ADM_DAP_G_G3D_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_DAP_G_G3D_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADM_DAP_G_G3D_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_ADM_DAP_G_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADM_DAP_G_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D0_G3D_ENABLE, 0, 1, QCH_CON_ASB_G3D_QCH_LH_D0_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D0_G3D_CLOCK_REQ, 1, 1, QCH_CON_ASB_G3D_QCH_LH_D0_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D0_G3D_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASB_G3D_QCH_LH_D0_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D1_G3D_ENABLE, 0, 1, QCH_CON_ASB_G3D_QCH_LH_D1_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D1_G3D_CLOCK_REQ, 1, 1, QCH_CON_ASB_G3D_QCH_LH_D1_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D1_G3D_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASB_G3D_QCH_LH_D1_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D2_G3D_ENABLE, 0, 1, QCH_CON_ASB_G3D_QCH_LH_D2_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D2_G3D_CLOCK_REQ, 1, 1, QCH_CON_ASB_G3D_QCH_LH_D2_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D2_G3D_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASB_G3D_QCH_LH_D2_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D3_G3D_ENABLE, 0, 1, QCH_CON_ASB_G3D_QCH_LH_D3_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D3_G3D_CLOCK_REQ, 1, 1, QCH_CON_ASB_G3D_QCH_LH_D3_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D3_G3D_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASB_G3D_QCH_LH_D3_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_S_LH_P_G3D_ENABLE, 0, 1, QCH_CON_ASB_G3D_QCH_S_LH_P_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_S_LH_P_G3D_CLOCK_REQ, 1, 1, QCH_CON_ASB_G3D_QCH_S_LH_P_G3D),
|
|
SFR_ACCESS(QCH_CON_ASB_G3D_QCH_S_LH_P_G3D_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASB_G3D_QCH_S_LH_P_G3D),
|
|
SFR_ACCESS(QCH_CON_BUSIF_DDC_G3D_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_DDC_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_DDC_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_DDC_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_DDC_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_DDC_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_G3DCORE_CMU_G3DCORE_QCH_ENABLE, 0, 1, QCH_CON_G3DCORE_CMU_G3DCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_G3DCORE_CMU_G3DCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_G3DCORE_CMU_G3DCORE_QCH),
|
|
SFR_ACCESS(QCH_CON_G3DCORE_CMU_G3DCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_G3DCORE_CMU_G3DCORE_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_GPU_QCH_CLK_ENABLE, 0, 1, DMYQCH_CON_GPU_QCH_CLK),
|
|
SFR_ACCESS(DMYQCH_CON_GPU_QCH_CLK_CLOCK_REQ, 1, 1, DMYQCH_CON_GPU_QCH_CLK),
|
|
SFR_ACCESS(DMYQCH_CON_GPU_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_GPU_QCH_CLK),
|
|
SFR_ACCESS(DMYQCH_CON_GPU_QCH_PCLK_ENABLE, 0, 1, DMYQCH_CON_GPU_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_GPU_QCH_PCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_GPU_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_GPU_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_GPU_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_PCLK_ENABLE, 0, 1, QCH_CON_HTU_G3D_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_G3D_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_G3D_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_CLK_ENABLE, 0, 1, QCH_CON_HTU_G3D_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_HTU_G3D_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_HTU_G3D_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HTU_G3D_QCH_CLK),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_T_DDCG3D_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_T_DDCG3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_T_DDCG3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_T_DDCG3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_T_DDCG3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_T_DDCG3D_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_G3DCORE_NOCP_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_G3DCORE_NOCP_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_G3DCORE_NOCP_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_G3DCORE_NOCP_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_G3DCORE_NOCP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_G3DCORE_NOCP_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_G3D_POWERIP_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_G3D_POWERIP_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_G3D_POWERIP_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_G3D_POWERIP_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_G3D_POWERIP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_G3D_POWERIP_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_NOCP_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_NOCP_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_NOCP_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_NOCP_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_NOCP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_G3DCORE_NOCP_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_G3D_POWERIP_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_G3D_POWERIP_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_G3D_POWERIP_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_G3D_POWERIP_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_G3D_POWERIP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_G3D_POWERIP_QCH),
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|
SFR_ACCESS(QCH_CON_STR_MUX_G3D_QCH_PCLK_ENABLE, 0, 1, QCH_CON_STR_MUX_G3D_QCH_PCLK),
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|
SFR_ACCESS(QCH_CON_STR_MUX_G3D_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_STR_MUX_G3D_QCH_PCLK),
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|
SFR_ACCESS(QCH_CON_STR_MUX_G3D_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_STR_MUX_G3D_QCH_PCLK),
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|
SFR_ACCESS(QCH_CON_STR_MUX_G3D_QCH_CORE_ENABLE, 0, 1, QCH_CON_STR_MUX_G3D_QCH_CORE),
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|
SFR_ACCESS(QCH_CON_STR_MUX_G3D_QCH_CORE_CLOCK_REQ, 1, 1, QCH_CON_STR_MUX_G3D_QCH_CORE),
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|
SFR_ACCESS(QCH_CON_STR_MUX_G3D_QCH_CORE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_STR_MUX_G3D_QCH_CORE),
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|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__G3D_QCH_ENABLE, 0, 1, QCH_CON_U_DDD_CTRL_CORE__G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_U_DDD_CTRL_CORE__G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_U_DDD_CTRL_CORE__G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_U_DDD_CTRL_CORE__G3D_QCH),
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|
SFR_ACCESS(QCH_CON_D_TZPC_GNPU_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_GNPU_QCH),
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|
SFR_ACCESS(QCH_CON_D_TZPC_GNPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_GNPU_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_GNPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_GNPU_QCH),
|
|
SFR_ACCESS(QCH_CON_GNPU_CMU_GNPU_QCH_ENABLE, 0, 1, QCH_CON_GNPU_CMU_GNPU_QCH),
|
|
SFR_ACCESS(QCH_CON_GNPU_CMU_GNPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_GNPU_CMU_GNPU_QCH),
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|
SFR_ACCESS(QCH_CON_GNPU_CMU_GNPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GNPU_CMU_GNPU_QCH),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_CORE_ENABLE, 0, 1, QCH_CON_IP_NPUCORE_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_CORE_CLOCK_REQ, 1, 1, QCH_CON_IP_NPUCORE_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_CORE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPUCORE_QCH_CORE),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_SRAM_ENABLE, 0, 1, QCH_CON_IP_NPUCORE_QCH_SRAM),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_SRAM_CLOCK_REQ, 1, 1, QCH_CON_IP_NPUCORE_QCH_SRAM),
|
|
SFR_ACCESS(QCH_CON_IP_NPUCORE_QCH_SRAM_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_NPUCORE_QCH_SRAM),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD0_GNPU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD0_GNPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD0_GNPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD0_GNPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD0_GNPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD0_GNPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD1_GNPU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD1_GNPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD1_GNPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD1_GNPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD1_GNPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD1_GNPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_CTRL_GNPU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_CTRL_GNPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_CTRL_GNPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_CTRL_GNPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_CTRL_GNPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_CTRL_GNPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_RQ_GNPU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_RQ_GNPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_RQ_GNPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_RQ_GNPU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_RQ_GNPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_RQ_GNPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_GNPU_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LP_GNPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_GNPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LP_GNPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_GNPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LP_GNPU_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LD_CMDQ_GNPU_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LD_CMDQ_GNPU_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LD_CMDQ_GNPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LD_CMDQ_GNPU_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LD_CMDQ_GNPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LD_CMDQ_GNPU_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_GNPU_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_GNPU_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_GNPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_GNPU_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_GNPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_GNPU_QCH),
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|
SFR_ACCESS(QCH_CON_GNSS_CMU_GNSS_QCH_ENABLE, 0, 1, QCH_CON_GNSS_CMU_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_GNSS_CMU_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_GNSS_CMU_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_GNSS_CMU_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GNSS_CMU_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_OSC_CLK_ENABLE, 0, 1, QCH_CON_DP_LINK_QCH_OSC_CLK),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_OSC_CLK_CLOCK_REQ, 1, 1, QCH_CON_DP_LINK_QCH_OSC_CLK),
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|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_OSC_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DP_LINK_QCH_OSC_CLK),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DP_LINK_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DP_LINK_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DP_LINK_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_GTC_CLK_ENABLE, 0, 1, QCH_CON_DP_LINK_QCH_GTC_CLK),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_GTC_CLK_CLOCK_REQ, 1, 1, QCH_CON_DP_LINK_QCH_GTC_CLK),
|
|
SFR_ACCESS(QCH_CON_DP_LINK_QCH_GTC_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DP_LINK_QCH_GTC_CLK),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_HSI0_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_HSI0_CMU_HSI0_QCH_ENABLE, 0, 1, QCH_CON_HSI0_CMU_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_HSI0_CMU_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_HSI0_CMU_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_HSI0_CMU_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HSI0_CMU_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_HSI0_BUS1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_HSI0_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_HSI0_BUS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_HSI0_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_HSI0_BUS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_HSI0_BUS1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_ACEL_SI_D_HSI0_QCH_ENABLE, 0, 1, QCH_CON_SLH_ACEL_SI_D_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_ACEL_SI_D_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_ACEL_SI_D_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_ACEL_SI_D_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_ACEL_SI_D_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_HSI0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_AUDHSI0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LD_AUDHSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_AUDHSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LD_AUDHSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LD_AUDHSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LD_AUDHSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LD_HSI0AUD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LD_HSI0AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LD_HSI0AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LD_HSI0AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LD_HSI0AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LD_HSI0AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SPC_HSI0_QCH_ENABLE, 0, 1, QCH_CON_SPC_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SPC_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPC_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SPC_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPC_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_HSI0_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_D_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_HSI0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_USB32DRD_QCH_S_SUBCTRL_ENABLE, 0, 1, QCH_CON_USB32DRD_QCH_S_SUBCTRL),
|
|
SFR_ACCESS(QCH_CON_USB32DRD_QCH_S_SUBCTRL_CLOCK_REQ, 1, 1, QCH_CON_USB32DRD_QCH_S_SUBCTRL),
|
|
SFR_ACCESS(QCH_CON_USB32DRD_QCH_S_SUBCTRL_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB32DRD_QCH_S_SUBCTRL),
|
|
SFR_ACCESS(QCH_CON_USB32DRD_QCH_S_LINK_ENABLE, 0, 1, QCH_CON_USB32DRD_QCH_S_LINK),
|
|
SFR_ACCESS(QCH_CON_USB32DRD_QCH_S_LINK_CLOCK_REQ, 1, 1, QCH_CON_USB32DRD_QCH_S_LINK),
|
|
SFR_ACCESS(QCH_CON_USB32DRD_QCH_S_LINK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB32DRD_QCH_S_LINK),
|
|
SFR_ACCESS(QCH_CON_USB32DRD_QCH_S_CTRL_ENABLE, 0, 1, QCH_CON_USB32DRD_QCH_S_CTRL),
|
|
SFR_ACCESS(QCH_CON_USB32DRD_QCH_S_CTRL_CLOCK_REQ, 1, 1, QCH_CON_USB32DRD_QCH_S_CTRL),
|
|
SFR_ACCESS(QCH_CON_USB32DRD_QCH_S_CTRL_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB32DRD_QCH_S_CTRL),
|
|
SFR_ACCESS(QCH_CON_USB32DRD_QCH_S_TCA_ENABLE, 0, 1, QCH_CON_USB32DRD_QCH_S_TCA),
|
|
SFR_ACCESS(QCH_CON_USB32DRD_QCH_S_TCA_CLOCK_REQ, 1, 1, QCH_CON_USB32DRD_QCH_S_TCA),
|
|
SFR_ACCESS(QCH_CON_USB32DRD_QCH_S_TCA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB32DRD_QCH_S_TCA),
|
|
SFR_ACCESS(QCH_CON_USB32DRD_QCH_S_EUSBCTL_ENABLE, 0, 1, QCH_CON_USB32DRD_QCH_S_EUSBCTL),
|
|
SFR_ACCESS(QCH_CON_USB32DRD_QCH_S_EUSBCTL_CLOCK_REQ, 1, 1, QCH_CON_USB32DRD_QCH_S_EUSBCTL),
|
|
SFR_ACCESS(QCH_CON_USB32DRD_QCH_S_EUSBCTL_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB32DRD_QCH_S_EUSBCTL),
|
|
SFR_ACCESS(QCH_CON_USB32DRD_QCH_S_EUSBPHY_ENABLE, 0, 1, QCH_CON_USB32DRD_QCH_S_EUSBPHY),
|
|
SFR_ACCESS(QCH_CON_USB32DRD_QCH_S_EUSBPHY_CLOCK_REQ, 1, 1, QCH_CON_USB32DRD_QCH_S_EUSBPHY),
|
|
SFR_ACCESS(QCH_CON_USB32DRD_QCH_S_EUSBPHY_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB32DRD_QCH_S_EUSBPHY),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_HSI0_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_HSI0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_HSI1_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_HSI1_QCH_ENABLE, 0, 1, QCH_CON_GPIO_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_HSI1_CMU_HSI1_QCH_ENABLE, 0, 1, QCH_CON_HSI1_CMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_HSI1_CMU_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_HSI1_CMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_HSI1_CMU_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HSI1_CMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_HSI1_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_SI_D_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_SI_D_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_SI_D_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_AXI_ENABLE, 0, 1, QCH_CON_PCIE_GEN2_QCH_AXI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_AXI_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN2_QCH_AXI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_AXI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN2_QCH_AXI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PCS_APB_ENABLE, 0, 1, QCH_CON_PCIE_GEN2_QCH_PCS_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PCS_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN2_QCH_PCS_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PCS_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN2_QCH_PCS_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_DBI_ENABLE, 0, 1, QCH_CON_PCIE_GEN2_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_DBI_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN2_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_DBI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN2_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_APB_ENABLE, 0, 1, QCH_CON_PCIE_GEN2_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN2_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN2_QCH_APB),
|
|
SFR_ACCESS(DMYQCH_CON_PCIE_GEN2_QCH_REF_ENABLE, 0, 1, DMYQCH_CON_PCIE_GEN2_QCH_REF),
|
|
SFR_ACCESS(DMYQCH_CON_PCIE_GEN2_QCH_REF_CLOCK_REQ, 1, 1, DMYQCH_CON_PCIE_GEN2_QCH_REF),
|
|
SFR_ACCESS(DMYQCH_CON_PCIE_GEN2_QCH_REF_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_PCIE_GEN2_QCH_REF),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PMA_APB_ENABLE, 0, 1, QCH_CON_PCIE_GEN2_QCH_PMA_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PMA_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN2_QCH_PMA_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_PMA_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN2_QCH_PMA_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_UDBG_APB_ENABLE, 0, 1, QCH_CON_PCIE_GEN2_QCH_UDBG_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_UDBG_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN2_QCH_UDBG_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN2_QCH_UDBG_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN2_QCH_UDBG_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_APB_ENABLE, 0, 1, QCH_CON_PCIE_GEN3_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN3_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN3_QCH_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_DBI_ENABLE, 0, 1, QCH_CON_PCIE_GEN3_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_DBI_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN3_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_DBI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN3_QCH_DBI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_AXI_ENABLE, 0, 1, QCH_CON_PCIE_GEN3_QCH_AXI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_AXI_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN3_QCH_AXI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_AXI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN3_QCH_AXI),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_PCS_APB_ENABLE, 0, 1, QCH_CON_PCIE_GEN3_QCH_PCS_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_PCS_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN3_QCH_PCS_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_PCS_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN3_QCH_PCS_APB),
|
|
SFR_ACCESS(DMYQCH_CON_PCIE_GEN3_QCH_REF_ENABLE, 0, 1, DMYQCH_CON_PCIE_GEN3_QCH_REF),
|
|
SFR_ACCESS(DMYQCH_CON_PCIE_GEN3_QCH_REF_CLOCK_REQ, 1, 1, DMYQCH_CON_PCIE_GEN3_QCH_REF),
|
|
SFR_ACCESS(DMYQCH_CON_PCIE_GEN3_QCH_REF_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_PCIE_GEN3_QCH_REF),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_UDBG_APB_ENABLE, 0, 1, QCH_CON_PCIE_GEN3_QCH_UDBG_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_UDBG_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN3_QCH_UDBG_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_UDBG_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN3_QCH_UDBG_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_PMA_APB_ENABLE, 0, 1, QCH_CON_PCIE_GEN3_QCH_PMA_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_PMA_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN3_QCH_PMA_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_GEN3_QCH_PMA_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN3_QCH_PMA_APB),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN2_QCH_ENABLE, 0, 1, QCH_CON_PCIE_IA_GEN2_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PCIE_IA_GEN2_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_IA_GEN2_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN3_QCH_ENABLE, 0, 1, QCH_CON_PCIE_IA_GEN3_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN3_QCH_CLOCK_REQ, 1, 1, QCH_CON_PCIE_IA_GEN3_QCH),
|
|
SFR_ACCESS(QCH_CON_PCIE_IA_GEN3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_IA_GEN3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_HSI1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_HSI1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_HSI1_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_HSI1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_HSI1_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_HSI1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_HSI1_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_HSI1_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_HSI1_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_HSI1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_HSI1_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_HSI1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_HSI1_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_HSI1_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_HSI1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_HSI1_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_LME_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_ENABLE, 0, 1, QCH_CON_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_C2_M_ENABLE, 0, 1, QCH_CON_GDC_QCH_C2_M),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_C2_M_CLOCK_REQ, 1, 1, QCH_CON_GDC_QCH_C2_M),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_C2_M_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GDC_QCH_C2_M),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_C2_S_ENABLE, 0, 1, QCH_CON_GDC_QCH_C2_S),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_C2_S_CLOCK_REQ, 1, 1, QCH_CON_GDC_QCH_C2_S),
|
|
SFR_ACCESS(QCH_CON_GDC_QCH_C2_S_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GDC_QCH_C2_S),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_LME_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_SI_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_SI_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_SI_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_LME_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_ID_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_ID_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_ID_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_LME_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_ID_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_ID_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_ID_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LME_QCH_0_ENABLE, 0, 1, QCH_CON_LME_QCH_0),
|
|
SFR_ACCESS(QCH_CON_LME_QCH_0_CLOCK_REQ, 1, 1, QCH_CON_LME_QCH_0),
|
|
SFR_ACCESS(QCH_CON_LME_QCH_0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LME_QCH_0),
|
|
SFR_ACCESS(QCH_CON_LME_CMU_LME_QCH_ENABLE, 0, 1, QCH_CON_LME_CMU_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LME_CMU_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_LME_CMU_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LME_CMU_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LME_CMU_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D_LME_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D1_LME_QCH_ENABLE, 0, 1, QCH_CON_QE_D1_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D1_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D1_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_D1_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D1_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_LME_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_LME_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_LME_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D_LME_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_LME_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_LME_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_LME_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_LME_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_LME_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D_LME_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_LME_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_LME_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_LME_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_LME_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_LME_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D_GDC_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D_GDC_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D_LME_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_M2M_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_FRC_MC_QCH_ENABLE, 0, 1, QCH_CON_FRC_MC_QCH),
|
|
SFR_ACCESS(QCH_CON_FRC_MC_QCH_CLOCK_REQ, 1, 1, QCH_CON_FRC_MC_QCH),
|
|
SFR_ACCESS(QCH_CON_FRC_MC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_FRC_MC_QCH),
|
|
SFR_ACCESS(QCH_CON_JPEG0_QCH_ENABLE, 0, 1, QCH_CON_JPEG0_QCH),
|
|
SFR_ACCESS(QCH_CON_JPEG0_QCH_CLOCK_REQ, 1, 1, QCH_CON_JPEG0_QCH),
|
|
SFR_ACCESS(QCH_CON_JPEG0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_JPEG0_QCH),
|
|
SFR_ACCESS(QCH_CON_JPEG1_QCH_ENABLE, 0, 1, QCH_CON_JPEG1_QCH),
|
|
SFR_ACCESS(QCH_CON_JPEG1_QCH_CLOCK_REQ, 1, 1, QCH_CON_JPEG1_QCH),
|
|
SFR_ACCESS(QCH_CON_JPEG1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_JPEG1_QCH),
|
|
SFR_ACCESS(QCH_CON_JSQZ_QCH_ENABLE, 0, 1, QCH_CON_JSQZ_QCH),
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SFR_ACCESS(QCH_CON_JSQZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_JSQZ_QCH),
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|
SFR_ACCESS(QCH_CON_JSQZ_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_JSQZ_QCH),
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|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_M2M_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_SI_D_M2M_QCH),
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|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_SI_D_M2M_QCH),
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|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_SI_D_M2M_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_FRC_MC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_FRC_MC_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_MI_FRC_MC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_FRC_MC_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_MI_FRC_MC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_FRC_MC_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_FRC_MC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_FRC_MC_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_FRC_MC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_FRC_MC_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_FRC_MC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_FRC_MC_QCH),
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|
SFR_ACCESS(QCH_CON_M2M_QCH_ENABLE, 0, 1, QCH_CON_M2M_QCH),
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SFR_ACCESS(QCH_CON_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_M2M_QCH),
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SFR_ACCESS(QCH_CON_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_M2M_QCH),
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|
SFR_ACCESS(QCH_CON_M2M_QCH_VOTF_ENABLE, 0, 1, QCH_CON_M2M_QCH_VOTF),
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SFR_ACCESS(QCH_CON_M2M_QCH_VOTF_CLOCK_REQ, 1, 1, QCH_CON_M2M_QCH_VOTF),
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SFR_ACCESS(QCH_CON_M2M_QCH_VOTF_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_M2M_QCH_VOTF),
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SFR_ACCESS(QCH_CON_M2M_CMU_M2M_QCH_ENABLE, 0, 1, QCH_CON_M2M_CMU_M2M_QCH),
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SFR_ACCESS(QCH_CON_M2M_CMU_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_M2M_CMU_M2M_QCH),
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SFR_ACCESS(QCH_CON_M2M_CMU_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_M2M_CMU_M2M_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D_M2M_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D_M2M_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D_M2M_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D_M2M_QCH),
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|
SFR_ACCESS(QCH_CON_QE_FRC_MC_QCH_ENABLE, 0, 1, QCH_CON_QE_FRC_MC_QCH),
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SFR_ACCESS(QCH_CON_QE_FRC_MC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_FRC_MC_QCH),
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SFR_ACCESS(QCH_CON_QE_FRC_MC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_FRC_MC_QCH),
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|
SFR_ACCESS(QCH_CON_QE_JPEG0_QCH_ENABLE, 0, 1, QCH_CON_QE_JPEG0_QCH),
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|
SFR_ACCESS(QCH_CON_QE_JPEG0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_JPEG0_QCH),
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|
SFR_ACCESS(QCH_CON_QE_JPEG0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_JPEG0_QCH),
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|
SFR_ACCESS(QCH_CON_QE_JPEG1_QCH_ENABLE, 0, 1, QCH_CON_QE_JPEG1_QCH),
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|
SFR_ACCESS(QCH_CON_QE_JPEG1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_JPEG1_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_JPEG1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_JPEG1_QCH),
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|
SFR_ACCESS(QCH_CON_QE_JSQZ_QCH_ENABLE, 0, 1, QCH_CON_QE_JSQZ_QCH),
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|
SFR_ACCESS(QCH_CON_QE_JSQZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_JSQZ_QCH),
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|
SFR_ACCESS(QCH_CON_QE_JSQZ_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_JSQZ_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_M2M_QCH_ENABLE, 0, 1, QCH_CON_QE_M2M_QCH),
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|
SFR_ACCESS(QCH_CON_QE_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_M2M_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_M2M_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_PM_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D_M2M_PM_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_PM_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_M2M_PM_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_PM_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_M2M_PM_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_PM_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D_M2M_PM_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_PM_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_M2M_PM_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_M2M_PM_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_M2M_PM_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSREG_M2M_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_M2M_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MCSC_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_YUVPMCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF0_YUVPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_YUVPMCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF0_YUVPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_YUVPMCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF0_YUVPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_YUVPMCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF1_YUVPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_YUVPMCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF1_YUVPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_YUVPMCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF1_YUVPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_BRPMCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF_BRPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_BRPMCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF_BRPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_BRPMCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF_BRPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_MCSCYUVP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF_MCSCYUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_MCSCYUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF_MCSCYUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_MCSCYUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF_MCSCYUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_ID_MCSC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_ID_MCSC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_ID_MCSC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC1_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_ID_MCSC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_ID_MCSC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_ID_MCSC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC2_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_ID_MCSC2_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_ID_MCSC2_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_ID_MCSC2_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC3_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_ID_MCSC3_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC3_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_ID_MCSC3_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_ID_MCSC3_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC4_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_ID_MCSC4_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC4_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_ID_MCSC4_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC4_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_ID_MCSC4_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC5_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_ID_MCSC5_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC5_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_ID_MCSC5_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC5_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_ID_MCSC5_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC6_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_ID_MCSC6_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC6_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_ID_MCSC6_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MCSC6_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_ID_MCSC6_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D2_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D2_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D2_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D3_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D3_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D3_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D3_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D3_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D3_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D4_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D4_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D4_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D4_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D4_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D4_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_ID_MCSC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_ID_MCSC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_ID_MCSC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC1_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_ID_MCSC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_ID_MCSC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_ID_MCSC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC2_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_ID_MCSC2_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_ID_MCSC2_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_ID_MCSC2_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC3_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_ID_MCSC3_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC3_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_ID_MCSC3_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_ID_MCSC3_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC4_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_ID_MCSC4_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC4_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_ID_MCSC4_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC4_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_ID_MCSC4_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC5_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_ID_MCSC5_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC5_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_ID_MCSC5_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC5_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_ID_MCSC5_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC6_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_ID_MCSC6_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC6_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_ID_MCSC6_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MCSC6_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_ID_MCSC6_QCH),
|
|
SFR_ACCESS(QCH_CON_MCFP_QCH_ENABLE, 0, 1, QCH_CON_MCFP_QCH),
|
|
SFR_ACCESS(QCH_CON_MCFP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCFP_QCH),
|
|
SFR_ACCESS(QCH_CON_MCFP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCFP_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_ENABLE, 0, 1, QCH_CON_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_C2R_ENABLE, 0, 1, QCH_CON_MCSC_QCH_C2R),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_C2R_CLOCK_REQ, 1, 1, QCH_CON_MCSC_QCH_C2R),
|
|
SFR_ACCESS(QCH_CON_MCSC_QCH_C2R_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCSC_QCH_C2R),
|
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SFR_ACCESS(QCH_CON_MCSC_QCH_C2W_ENABLE, 0, 1, QCH_CON_MCSC_QCH_C2W),
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SFR_ACCESS(QCH_CON_MCSC_QCH_C2W_CLOCK_REQ, 1, 1, QCH_CON_MCSC_QCH_C2W),
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SFR_ACCESS(QCH_CON_MCSC_QCH_C2W_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCSC_QCH_C2W),
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SFR_ACCESS(QCH_CON_MCSC_CMU_MCSC_QCH_ENABLE, 0, 1, QCH_CON_MCSC_CMU_MCSC_QCH),
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SFR_ACCESS(QCH_CON_MCSC_CMU_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCSC_CMU_MCSC_QCH),
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SFR_ACCESS(QCH_CON_MCSC_CMU_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCSC_CMU_MCSC_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D0_MCSC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_MCSC_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D0_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_MCSC_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D0_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_MCSC_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D1_MCSC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_MCSC_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D1_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_MCSC_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D1_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_MCSC_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D2_MCSC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D2_MCSC_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D2_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D2_MCSC_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D2_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D2_MCSC_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D3_MCSC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D3_MCSC_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D3_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D3_MCSC_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D3_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D3_MCSC_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D4_MCSC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D4_MCSC_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D4_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D4_MCSC_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D4_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D4_MCSC_QCH),
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SFR_ACCESS(QCH_CON_SIU_G_PPMU_MCSC_QCH_ENABLE, 0, 1, QCH_CON_SIU_G_PPMU_MCSC_QCH),
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SFR_ACCESS(QCH_CON_SIU_G_PPMU_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIU_G_PPMU_MCSC_QCH),
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SFR_ACCESS(QCH_CON_SIU_G_PPMU_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIU_G_PPMU_MCSC_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_MCSC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_MCSC_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_MCSC_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_MCSC_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MCSC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_MCSC_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_MCSC_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_MCSC_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_D0_MCSC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_D0_MCSC_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_D0_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_D0_MCSC_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_D0_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_D0_MCSC_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_MCSC_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_MCSC_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_MCSC_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_MCSC_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_MCSC_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_MCSC_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_D3_MCSC_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D3_MCSC_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_D3_MCSC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D3_MCSC_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_D3_MCSC_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D3_MCSC_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_D3_MCSC_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D3_MCSC_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_D3_MCSC_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D3_MCSC_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_D3_MCSC_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D3_MCSC_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_D4_MCSC_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D4_MCSC_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_D4_MCSC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D4_MCSC_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_D4_MCSC_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D4_MCSC_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_D4_MCSC_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D4_MCSC_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_D4_MCSC_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D4_MCSC_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_D4_MCSC_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D4_MCSC_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSREG_MCSC_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MCSC_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MCSC_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MCSC_QCH),
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SFR_ACCESS(QCH_CON_VGEN_LITE_D0_MCSC_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D0_MCSC_QCH),
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SFR_ACCESS(QCH_CON_VGEN_LITE_D0_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D0_MCSC_QCH),
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SFR_ACCESS(QCH_CON_VGEN_LITE_D0_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D0_MCSC_QCH),
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SFR_ACCESS(QCH_CON_VGEN_LITE_D1_MCSC_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D1_MCSC_QCH),
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SFR_ACCESS(QCH_CON_VGEN_LITE_D1_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D1_MCSC_QCH),
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SFR_ACCESS(QCH_CON_VGEN_LITE_D1_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D1_MCSC_QCH),
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SFR_ACCESS(QCH_CON_VGEN_LITE_D2_MCSC_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D2_MCSC_QCH),
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SFR_ACCESS(QCH_CON_VGEN_LITE_D2_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D2_MCSC_QCH),
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SFR_ACCESS(QCH_CON_VGEN_LITE_D2_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D2_MCSC_QCH),
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SFR_ACCESS(QCH_CON_D_TZPC_MFC0_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_MFC0_QCH),
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SFR_ACCESS(QCH_CON_D_TZPC_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_MFC0_QCH),
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SFR_ACCESS(QCH_CON_D_TZPC_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_MFC1MFC0_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF0_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_MFC1MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF0_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF0_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_MFC1MFC0_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF1_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_MFC1MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF1_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF1_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF2_MFC1MFC0_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF2_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF2_MFC1MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF2_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF2_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF2_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF3_MFC1MFC0_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF3_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF3_MFC1MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF3_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF3_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF3_MFC1MFC0_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_MFC0MFC1_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF0_MFC0MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_MFC0MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF0_MFC0MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF0_MFC0MFC1_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_MFC0MFC1_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF1_MFC0MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_MFC0MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF1_MFC0MFC1_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF1_MFC0MFC1_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF2_MFC0MFC1_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF2_MFC0MFC1_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF2_MFC0MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF2_MFC0MFC1_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF2_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF2_MFC0MFC1_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF3_MFC0MFC1_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF3_MFC0MFC1_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF3_MFC0MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF3_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF3_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF3_MFC0MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MFC0_QCH_MI_ENABLE, 0, 1, QCH_CON_LH_ATB_MFC0_QCH_MI),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MFC0_QCH_MI_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MFC0_QCH_MI),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MFC0_QCH_MI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MFC0_QCH_MI),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MFC0_QCH_SI_ENABLE, 0, 1, QCH_CON_LH_ATB_MFC0_QCH_SI),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MFC0_QCH_SI_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MFC0_QCH_SI),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_MFC0_QCH_SI_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MFC0_QCH_SI),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MFC0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_ID_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_ID_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_ID_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MFC0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MFC0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MFC0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_ID_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_ID_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_ID_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC0_QCH_ENABLE, 0, 1, QCH_CON_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC0_QCH_VOTF_ENABLE, 0, 1, QCH_CON_MFC0_QCH_VOTF),
|
|
SFR_ACCESS(QCH_CON_MFC0_QCH_VOTF_CLOCK_REQ, 1, 1, QCH_CON_MFC0_QCH_VOTF),
|
|
SFR_ACCESS(QCH_CON_MFC0_QCH_VOTF_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MFC0_QCH_VOTF),
|
|
SFR_ACCESS(QCH_CON_MFC0_CMU_MFC0_QCH_ENABLE, 0, 1, QCH_CON_MFC0_CMU_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC0_CMU_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFC0_CMU_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_MFC0_CMU_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MFC0_CMU_MFC0_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFC0D0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_MFC0D0_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFC0D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_MFC0D0_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFC0D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_MFC0D0_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFC0D1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_MFC0D1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFC0D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_MFC0D1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFC0D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_MFC0D1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_WFD_QCH_ENABLE, 0, 1, QCH_CON_PPMU_WFD_QCH),
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SFR_ACCESS(QCH_CON_PPMU_WFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_WFD_QCH),
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SFR_ACCESS(QCH_CON_PPMU_WFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_WFD_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_SIU_G_PPMU_MFC0_QCH_ENABLE, 0, 1, QCH_CON_SIU_G_PPMU_MFC0_QCH),
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SFR_ACCESS(QCH_CON_SIU_G_PPMU_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIU_G_PPMU_MFC0_QCH),
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SFR_ACCESS(QCH_CON_SIU_G_PPMU_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIU_G_PPMU_MFC0_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_MFC0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_MFC0_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_MFC0_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_MFC0_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MFC0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_MFC0_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_MFC0_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_MFC0_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC0D0_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_MFC0D0_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC0D0_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFC0D0_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC0D0_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFC0D0_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC0D0_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_MFC0D0_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC0D0_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFC0D0_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC0D0_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFC0D0_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC0D1_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_MFC0D1_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC0D1_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFC0D1_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC0D1_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFC0D1_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC0D1_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_MFC0D1_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC0D1_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFC0D1_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC0D1_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFC0D1_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSREG_MFC0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MFC0_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MFC0_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MFC0_QCH),
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SFR_ACCESS(QCH_CON_VGEN_LITE_MFC0_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_MFC0_QCH),
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SFR_ACCESS(QCH_CON_VGEN_LITE_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_MFC0_QCH),
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SFR_ACCESS(QCH_CON_VGEN_LITE_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_MFC0_QCH),
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SFR_ACCESS(QCH_CON_WFD_QCH_ENABLE, 0, 1, QCH_CON_WFD_QCH),
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SFR_ACCESS(QCH_CON_WFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_WFD_QCH),
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SFR_ACCESS(QCH_CON_WFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WFD_QCH),
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SFR_ACCESS(DMYQCH_CON_ADM_APB_MFC0MFC1_QCH_ENABLE, 0, 1, DMYQCH_CON_ADM_APB_MFC0MFC1_QCH),
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SFR_ACCESS(DMYQCH_CON_ADM_APB_MFC0MFC1_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADM_APB_MFC0MFC1_QCH),
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SFR_ACCESS(DMYQCH_CON_ADM_APB_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADM_APB_MFC0MFC1_QCH),
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SFR_ACCESS(QCH_CON_D_TZPC_MFC1_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_MFC1_QCH),
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SFR_ACCESS(QCH_CON_D_TZPC_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_MFC1_QCH),
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SFR_ACCESS(QCH_CON_D_TZPC_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_MFC0MFC1_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF0_MFC0MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_MFC0MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF0_MFC0MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF0_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF0_MFC0MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_MFC0MFC1_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF1_MFC0MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_MFC0MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF1_MFC0MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF1_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF1_MFC0MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF2_MFC0MFC1_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF2_MFC0MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF2_MFC0MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF2_MFC0MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF2_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF2_MFC0MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF3_MFC0MFC1_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF3_MFC0MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF3_MFC0MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF3_MFC0MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_OTF3_MFC0MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF3_MFC0MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_MFC1MFC0_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF0_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_MFC1MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF0_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF0_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_MFC1MFC0_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF1_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_MFC1MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF1_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF1_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_OTF2_MFC1MFC0_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF2_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_OTF2_MFC1MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF2_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_OTF2_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF2_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_OTF3_MFC1MFC0_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF3_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_OTF3_MFC1MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF3_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_OTF3_MFC1MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF3_MFC1MFC0_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MFC1_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MFC1_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_MFC1_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_MFC1_QCH),
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SFR_ACCESS(QCH_CON_MFC1_QCH_ENABLE, 0, 1, QCH_CON_MFC1_QCH),
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SFR_ACCESS(QCH_CON_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFC1_QCH),
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SFR_ACCESS(QCH_CON_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MFC1_QCH),
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SFR_ACCESS(QCH_CON_MFC1_CMU_MFC1_QCH_ENABLE, 0, 1, QCH_CON_MFC1_CMU_MFC1_QCH),
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SFR_ACCESS(QCH_CON_MFC1_CMU_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFC1_CMU_MFC1_QCH),
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SFR_ACCESS(QCH_CON_MFC1_CMU_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MFC1_CMU_MFC1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFC1D0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_MFC1D0_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFC1D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_MFC1D0_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFC1D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_MFC1D0_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFC1D1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_MFC1D1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFC1D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_MFC1D1_QCH),
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SFR_ACCESS(QCH_CON_PPMU_MFC1D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_MFC1D1_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH),
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|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH),
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SFR_ACCESS(QCH_CON_SIU_G_PPMU_MFC1_QCH_ENABLE, 0, 1, QCH_CON_SIU_G_PPMU_MFC1_QCH),
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SFR_ACCESS(QCH_CON_SIU_G_PPMU_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIU_G_PPMU_MFC1_QCH),
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SFR_ACCESS(QCH_CON_SIU_G_PPMU_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIU_G_PPMU_MFC1_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_MFC1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_MFC1_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_MFC1_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_MFC1_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MFC1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_MFC1_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_MFC1_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_MFC1_QCH),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC1D0_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_MFC1D0_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC1D0_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFC1D0_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC1D0_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFC1D0_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC1D0_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_MFC1D0_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC1D0_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFC1D0_QCH_S2),
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|
SFR_ACCESS(QCH_CON_SYSMMU_MFC1D0_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFC1D0_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC1D1_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_MFC1D1_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC1D1_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFC1D1_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC1D1_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFC1D1_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC1D1_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_MFC1D1_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_MFC1D1_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MFC1D1_QCH_S2),
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|
SFR_ACCESS(QCH_CON_SYSMMU_MFC1D1_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MFC1D1_QCH_S2),
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|
SFR_ACCESS(QCH_CON_SYSREG_MFC1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MFC1_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MFC1_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MFC1_QCH),
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|
SFR_ACCESS(QCH_CON_VGEN_MFC1_QCH_ENABLE, 0, 1, QCH_CON_VGEN_MFC1_QCH),
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|
SFR_ACCESS(QCH_CON_VGEN_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_MFC1_QCH),
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|
SFR_ACCESS(QCH_CON_VGEN_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_MFC1_QCH),
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|
SFR_ACCESS(QCH_CON_BUSIF_DDD_MIF_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_DDD_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_DDD_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_DDD_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_DDD_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_DDD_MIF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH),
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|
SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_DMC_QCH_ENABLE, 0, 1, QCH_CON_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_DMC_QCH_CLOCK_REQ, 1, 1, QCH_CON_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_DMC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MIF_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_ENABLE, 0, 1, QCH_CON_MIF_CMU_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_MIF_CMU_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIF_CMU_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_QCH_ADAPTER_DDRPHY_QCH_ENABLE, 0, 1, QCH_CON_QCH_ADAPTER_DDRPHY_QCH),
|
|
SFR_ACCESS(QCH_CON_QCH_ADAPTER_DDRPHY_QCH_CLOCK_REQ, 1, 1, QCH_CON_QCH_ADAPTER_DDRPHY_QCH),
|
|
SFR_ACCESS(QCH_CON_QCH_ADAPTER_DDRPHY_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QCH_ADAPTER_DDRPHY_QCH),
|
|
SFR_ACCESS(QCH_CON_QCH_ADAPTER_DMC_QCH_ENABLE, 0, 1, QCH_CON_QCH_ADAPTER_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_QCH_ADAPTER_DMC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QCH_ADAPTER_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_QCH_ADAPTER_DMC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QCH_ADAPTER_DMC_QCH),
|
|
SFR_ACCESS(QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_ENABLE, 0, 1, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH),
|
|
SFR_ACCESS(QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_CLOCK_REQ, 1, 1, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH),
|
|
SFR_ACCESS(QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_MIF_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_MIF_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MIF_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SPC_MIF_QCH_ENABLE, 0, 1, QCH_CON_SPC_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SPC_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPC_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SPC_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPC_MIF_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MIF_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MIF_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_PRIVATE_MIF_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PRIVATE_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PRIVATE_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PRIVATE_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PRIVATE_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_PRIVATE_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_CP_QCH_ENABLE, 0, 1, QCH_CON_BAAW_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_CP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_CP_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_GNSS_QCH_ENABLE, 0, 1, QCH_CON_BAAW_P_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_P_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_P_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_BDU_QCH_ENABLE, 0, 1, QCH_CON_BDU_QCH),
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|
SFR_ACCESS(QCH_CON_BDU_QCH_CLOCK_REQ, 1, 1, QCH_CON_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_BDU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_CACHEAID_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_CACHEAID_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_CACHEAID_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_CACHEAID_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_CACHEAID_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CACHEAID_NOCL0_QCH),
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|
SFR_ACCESS(DMYQCH_CON_CCI_QCH_ENABLE, 0, 1, DMYQCH_CON_CCI_QCH),
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|
SFR_ACCESS(DMYQCH_CON_CCI_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CCI_QCH),
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|
SFR_ACCESS(DMYQCH_CON_CCI_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CCI_QCH),
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|
SFR_ACCESS(QCH_CON_CCI_QCH_S_ENABLE, 0, 1, QCH_CON_CCI_QCH_S),
|
|
SFR_ACCESS(QCH_CON_CCI_QCH_S_CLOCK_REQ, 1, 1, QCH_CON_CCI_QCH_S),
|
|
SFR_ACCESS(QCH_CON_CCI_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CCI_QCH_S),
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|
SFR_ACCESS(DMYQCH_CON_CMU_NOCL0_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_NOCL0_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_NOCL0_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_NOCL0_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_NOCL0_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_NOCL0_CMUREF_QCH),
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|
SFR_ACCESS(QCH_CON_D_TZPC_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D0_G3D_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D0_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D0_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D0_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D0_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D0_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D1_G3D_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D1_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D1_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D1_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D1_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D1_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D2_G3D_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D2_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D2_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D2_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D2_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D2_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D3_G3D_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D3_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D3_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D3_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D3_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D3_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_D0_ACP_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_SI_D0_ACP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_D0_ACP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_SI_D0_ACP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_D0_ACP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_SI_D0_ACP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_D1_ACP_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_SI_D1_ACP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_D1_ACP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_SI_D1_ACP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_D1_ACP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_SI_D1_ACP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_NOCL1A_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_NOCL1A_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_NOCL1A_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1C_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1C_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_T_BDU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_T_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_T_BDU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_T_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ATB_SI_T_BDU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_T_BDU_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_APM_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_G_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_G_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_G_CSSYS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_CSSYS_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_IG_CSSYS_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_CSSYS_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_IG_CSSYS_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_CSSYS_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_IG_CSSYS_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_IG_CSSYS_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_IG_CSSYS_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_IG_CSSYS_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_IG_CSSYS_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_IG_CSSYS_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_IG_CSSYS_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_CHI_MI_D0_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_CHI_MI_D0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_CHI_MI_D0_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_CHI_MI_D0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_CHI_MI_D0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_CHI_MI_D0_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_CHI_MI_D1_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_CHI_MI_D1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_CHI_MI_D1_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_CHI_MI_D1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_CHI_MI_D1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_CHI_MI_D1_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_QDI_MI_D_AUD_QCH_ENABLE, 0, 1, QCH_CON_LH_QDI_MI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_QDI_MI_D_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_QDI_MI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_QDI_MI_D_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_QDI_MI_D_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_NOCIF_CMUTOPC_QCH_ENABLE, 0, 1, QCH_CON_NOCIF_CMUTOPC_QCH),
|
|
SFR_ACCESS(QCH_CON_NOCIF_CMUTOPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_NOCIF_CMUTOPC_QCH),
|
|
SFR_ACCESS(QCH_CON_NOCIF_CMUTOPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_NOCIF_CMUTOPC_QCH),
|
|
SFR_ACCESS(QCH_CON_NOCL0_CMU_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_NOCL0_CMU_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_NOCL0_CMU_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_NOCL0_CMU_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_NOCL0_CMU_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_NOCL0_CMU_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_PBHA_GEN_D0_MODEM_QCH_ENABLE, 0, 1, QCH_CON_PBHA_GEN_D0_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_PBHA_GEN_D0_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_PBHA_GEN_D0_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_PBHA_GEN_D0_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PBHA_GEN_D0_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_PBHA_GEN_D1_MODEM_QCH_ENABLE, 0, 1, QCH_CON_PBHA_GEN_D1_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_PBHA_GEN_D1_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_PBHA_GEN_D1_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_PBHA_GEN_D1_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PBHA_GEN_D1_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_SCI_QCH_ENABLE, 0, 1, QCH_CON_PPC_SCI_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_SCI_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_SCI_QCH),
|
|
SFR_ACCESS(QCH_CON_PPC_SCI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_SCI_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_APM_QCH_ENABLE, 0, 1, QCH_CON_PPMU_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_CPUCL0_0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_CPUCL0_1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_G3D0_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_G3D1_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D2_QCH_ENABLE, 0, 1, QCH_CON_PPMU_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_G3D2_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D3_QCH_ENABLE, 0, 1, QCH_CON_PPMU_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D3_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_G3D3_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_G3D3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_G3D3_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_PPMU_SYNC_GEN_QCH_ENABLE, 0, 1, DMYQCH_CON_PPMU_SYNC_GEN_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_PPMU_SYNC_GEN_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_PPMU_SYNC_GEN_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_PPMU_SYNC_GEN_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_PPMU_SYNC_GEN_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_NOCL0_NOCD_CCI_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_NOCL0_NOCD_CCI_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_NOCL0_NOCD_CCI_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_NOCL0_NOCD_CCI_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_NOCL0_NOCD_CCI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_NOCL0_NOCD_CCI_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_NOCL0_NOCP_CCI_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_NOCL0_NOCP_CCI_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_NOCL0_NOCP_CCI_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_NOCL0_NOCP_CCI_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_NOCL0_NOCP_CCI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_NOCL0_NOCP_CCI_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_G0_PPMU_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_SIU_G0_PPMU_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_G0_PPMU_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIU_G0_PPMU_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_G0_PPMU_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIU_G0_PPMU_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_G1_PPMU_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_SIU_G1_PPMU_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_G1_PPMU_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIU_G1_PPMU_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_G1_PPMU_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIU_G1_PPMU_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_G2_PPMU_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_SIU_G2_PPMU_NOCL0_QCH),
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SFR_ACCESS(QCH_CON_SIU_G2_PPMU_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIU_G2_PPMU_NOCL0_QCH),
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|
SFR_ACCESS(QCH_CON_SIU_G2_PPMU_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIU_G2_PPMU_NOCL0_QCH),
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|
SFR_ACCESS(QCH_CON_SIU_G3_PPMU_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_SIU_G3_PPMU_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_G3_PPMU_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIU_G3_PPMU_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_G3_PPMU_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIU_G3_PPMU_NOCL0_QCH),
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|
SFR_ACCESS(QCH_CON_SIU_G4_PPMU_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_SIU_G4_PPMU_NOCL0_QCH),
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|
SFR_ACCESS(QCH_CON_SIU_G4_PPMU_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIU_G4_PPMU_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_G4_PPMU_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIU_G4_PPMU_NOCL0_QCH),
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|
SFR_ACCESS(QCH_CON_SIU_G5_PPMU_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_SIU_G5_PPMU_NOCL0_QCH),
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|
SFR_ACCESS(QCH_CON_SIU_G5_PPMU_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIU_G5_PPMU_NOCL0_QCH),
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|
SFR_ACCESS(QCH_CON_SIU_G5_PPMU_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIU_G5_PPMU_NOCL0_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_ACEL_MI_D_SSP_QCH_ENABLE, 0, 1, QCH_CON_SLH_ACEL_MI_D_SSP_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_ACEL_MI_D_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_ACEL_MI_D_SSP_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_ACEL_MI_D_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_ACEL_MI_D_SSP_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_AUD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_AUD_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_AUD_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_GNSS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_GNSS_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_GNSS_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_GNSS_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MIF0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_MIF0_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MIF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_MIF0_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MIF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_MIF0_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MIF1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MIF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MIF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MIF2_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_MIF2_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MIF2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_MIF2_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MIF2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_MIF2_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MIF3_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_MIF3_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MIF3_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_MIF3_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MIF3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_MIF3_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MODEM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_NOCL1A_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_NOCL1A_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_NOCL1A_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_NOCL1C_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_NOCL1C_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_NOCL1C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_SSP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_UFD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_UFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_UFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_PPMU_P_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_IG_PPMU_P_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_PPMU_P_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_IG_PPMU_P_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_PPMU_P_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_IG_PPMU_P_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_PPMU_P_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_IG_PPMU_P_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_PPMU_P_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_IG_PPMU_P_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_PPMU_P_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_IG_PPMU_P_CLUSTER0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_D0_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_D0_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_D0_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_D1_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_D1_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_D1_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D2_MODEM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_D2_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D2_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_D2_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D2_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_D2_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_UFD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_D_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_UFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_D_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D_UFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_D_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CLUSTER0_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_CLUSTER0_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CLUSTER0_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_CLUSTER0_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CLUSTER0_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_CLUSTER0_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_APM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_APM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_AUD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_AUD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_AUD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_G3D_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_GNSS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_GNSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_GNSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MCW_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MCW_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MCW_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MCW_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MCW_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MCW_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MIF0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MIF0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MIF0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MIF1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF2_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MIF2_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MIF2_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MIF2_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF3_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MIF3_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF3_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MIF3_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MIF3_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MODEM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERISGIC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_PERISGIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERISGIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_PERISGIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERISGIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_PERISGIC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_SSP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_SSP_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_SSP_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_SSP_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_UFD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_UFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_UFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_UFD_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_MODEM_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_MODEM_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_MODEM_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MODEM_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_MODEM_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MODEM_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_MODEM_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_MODEM_QCH_S2),
|
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SFR_ACCESS(QCH_CON_SYSMMU_MODEM_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MODEM_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_MODEM_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MODEM_QCH_S2),
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|
SFR_ACCESS(QCH_CON_SYSMMU_S2_APM_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_S2_APM_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_S2_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_S2_APM_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_S2_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_S2_APM_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_S2_G3D_QCH_S0_ENABLE, 0, 1, QCH_CON_SYSMMU_S2_G3D_QCH_S0),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_S2_G3D_QCH_S0_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_S2_G3D_QCH_S0),
|
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SFR_ACCESS(QCH_CON_SYSMMU_S2_G3D_QCH_S0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_S2_G3D_QCH_S0),
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|
SFR_ACCESS(QCH_CON_SYSMMU_S2_G3D_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_S2_G3D_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_S2_G3D_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_S2_G3D_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_S2_G3D_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_S2_G3D_QCH_S1),
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SFR_ACCESS(QCH_CON_SYSMMU_S2_G3D_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_S2_G3D_QCH_S2),
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SFR_ACCESS(QCH_CON_SYSMMU_S2_G3D_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_S2_G3D_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_S2_G3D_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_S2_G3D_QCH_S2),
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|
SFR_ACCESS(QCH_CON_SYSMMU_S2_G3D_QCH_S3_ENABLE, 0, 1, QCH_CON_SYSMMU_S2_G3D_QCH_S3),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_S2_G3D_QCH_S3_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_S2_G3D_QCH_S3),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_S2_G3D_QCH_S3_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_S2_G3D_QCH_S3),
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|
SFR_ACCESS(QCH_CON_SYSMMU_S2_G3D_QCH_S4_ENABLE, 0, 1, QCH_CON_SYSMMU_S2_G3D_QCH_S4),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_S2_G3D_QCH_S4_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_S2_G3D_QCH_S4),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_S2_G3D_QCH_S4_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_S2_G3D_QCH_S4),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_NOCL0_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D0_ACP_QCH_ENABLE, 0, 1, QCH_CON_TREX_D0_ACP_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D0_ACP_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D0_ACP_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D0_ACP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D0_ACP_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D1_ACP_QCH_ENABLE, 0, 1, QCH_CON_TREX_D1_ACP_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D1_ACP_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D1_ACP_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D1_ACP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D1_ACP_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_TREX_P_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_P_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_D0_G3D_QCH_ENABLE, 0, 1, QCH_CON_VGEN_D0_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_D0_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_D0_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_D0_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_D0_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_D1_G3D_QCH_ENABLE, 0, 1, QCH_CON_VGEN_D1_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_D1_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_D1_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_D1_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_D1_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_D2_G3D_QCH_ENABLE, 0, 1, QCH_CON_VGEN_D2_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_D2_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_D2_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_D2_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_D2_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_D3_G3D_QCH_ENABLE, 0, 1, QCH_CON_VGEN_D3_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_D3_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_D3_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_D3_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_D3_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_MODEM_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_MODEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_MODEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_MODEM_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D0_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_WOW_DVFS_D0_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D0_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_WOW_DVFS_D0_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D0_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WOW_DVFS_D0_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D0_G3D_QCH_ENABLE, 0, 1, QCH_CON_WOW_DVFS_D0_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D0_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_WOW_DVFS_D0_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D0_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WOW_DVFS_D0_G3D_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D0_MIF_QCH_ENABLE, 0, 1, QCH_CON_WOW_DVFS_D0_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D0_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_WOW_DVFS_D0_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D0_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WOW_DVFS_D0_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D1_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_WOW_DVFS_D1_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D1_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_WOW_DVFS_D1_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D1_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WOW_DVFS_D1_CPUCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D1_MIF_QCH_ENABLE, 0, 1, QCH_CON_WOW_DVFS_D1_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D1_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_WOW_DVFS_D1_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D1_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WOW_DVFS_D1_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D2_MIF_QCH_ENABLE, 0, 1, QCH_CON_WOW_DVFS_D2_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D2_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_WOW_DVFS_D2_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D2_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WOW_DVFS_D2_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D3_MIF_QCH_ENABLE, 0, 1, QCH_CON_WOW_DVFS_D3_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D3_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_WOW_DVFS_D3_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_D3_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WOW_DVFS_D3_MIF_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_IRPS0_QCH_ENABLE, 0, 1, QCH_CON_WOW_DVFS_IRPS0_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_IRPS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_WOW_DVFS_IRPS0_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_IRPS0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WOW_DVFS_IRPS0_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_IRPS1_QCH_ENABLE, 0, 1, QCH_CON_WOW_DVFS_IRPS1_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_IRPS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_WOW_DVFS_IRPS1_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_IRPS1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WOW_DVFS_IRPS1_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_IRPS2_QCH_ENABLE, 0, 1, QCH_CON_WOW_DVFS_IRPS2_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_IRPS2_QCH_CLOCK_REQ, 1, 1, QCH_CON_WOW_DVFS_IRPS2_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_IRPS2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WOW_DVFS_IRPS2_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_IRPS3_QCH_ENABLE, 0, 1, QCH_CON_WOW_DVFS_IRPS3_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_IRPS3_QCH_CLOCK_REQ, 1, 1, QCH_CON_WOW_DVFS_IRPS3_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_IRPS3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WOW_DVFS_IRPS3_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_WOW_DVFS_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_WOW_DVFS_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_WOW_DVFS_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WOW_DVFS_NOCL0_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_DNC_QCH_ENABLE, 0, 1, QCH_CON_BAAW_P_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_DNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_P_DNC_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_P_DNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_P_DNC_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_NOCL1A_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_NOCL1A_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_NOCL1A_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_HSI1_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D_HSI1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_LME_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D_LME_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_M2M_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D_M2M_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_G_NOCL1A_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_G_NOCL1A_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_G_NOCL1A_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_MFC0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D0_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D0_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D0_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_MFC1_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D0_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D0_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D0_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_DPUF_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D1_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_DPUF_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D1_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_DPUF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D1_DPUF_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_MFC0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D1_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D1_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D1_MFC0_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_MFC1_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D1_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D1_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D1_MFC1_QCH),
|
|
SFR_ACCESS(QCH_CON_NOCL1A_CMU_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_NOCL1A_CMU_NOCL1A_QCH),
|
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SFR_ACCESS(QCH_CON_NOCL1A_CMU_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_NOCL1A_CMU_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_NOCL1A_CMU_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_NOCL1A_CMU_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SIU_2X1_P0_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_SIU_2X1_P0_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SIU_2X1_P0_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIU_2X1_P0_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SIU_2X1_P0_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIU_2X1_P0_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SIU_4X1_P0_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_SIU_4X1_P0_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SIU_4X1_P0_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIU_4X1_P0_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SIU_4X1_P0_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIU_4X1_P0_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SIU_8X1_P0_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_SIU_8X1_P0_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SIU_8X1_P0_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIU_8X1_P0_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SIU_8X1_P0_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIU_8X1_P0_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_DNC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_DNC_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_DNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_DNC_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_DNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_DNC_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_DPUF_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_DPUF_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_DPUF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_DPUF_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_DPUF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_DPUF_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_HSI1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_HSI1_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_HSI1_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_HSI1_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_LME_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_LME_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_LME_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_LME_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_M2M_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_M2M_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_M2M_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_M2M_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MFC0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_MFC0_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_MFC0_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_MFC0_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MFC1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_MFC1_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_MFC1_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_MFC1_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1A_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_D0_DPUF_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_D0_DPUF_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_D0_DPUF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_D0_DPUF_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_D0_DPUF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_D0_DPUF_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DNC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_DNC_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_DNC_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_DNC_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DPUB_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_DPUB_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DPUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_DPUB_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DPUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_DPUB_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DPUF_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_DPUF_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DPUF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_DPUF_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DPUF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_DPUF_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_HSI1_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_HSI1_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_HSI1_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_LME_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_LME_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_LME_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_LME_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_LME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_LME_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_M2M_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_M2M_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_M2M_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_M2M_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_M2M_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_M2M_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MFC0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MFC0_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MFC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MFC0_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MFC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MFC0_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MFC1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MFC1_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MFC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MFC1_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MFC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MFC1_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_PERIC0_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_PERIC0_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_PERIC0_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIC2_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_PERIC2_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_PERIC2_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_PERIC2_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_NOCL1A_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_NOCL1A_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_NOCL1A_QCH),
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|
SFR_ACCESS(QCH_CON_TREX_D_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_NOCL1A_QCH),
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|
SFR_ACCESS(QCH_CON_TREX_D_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_NOCL1A_QCH),
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|
SFR_ACCESS(QCH_CON_TREX_D_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_NOCL1A_QCH),
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|
SFR_ACCESS(QCH_CON_TREX_P_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_TREX_P_NOCL1A_QCH),
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|
SFR_ACCESS(QCH_CON_TREX_P_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P_NOCL1A_QCH),
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|
SFR_ACCESS(QCH_CON_TREX_P_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_P_NOCL1A_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH),
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|
SFR_ACCESS(DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_DIT_QCH_ENABLE, 0, 1, QCH_CON_DIT_QCH),
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|
SFR_ACCESS(QCH_CON_DIT_QCH_CLOCK_REQ, 1, 1, QCH_CON_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_DIT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_UFS_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_UFS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_UFS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_ID_DIT_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_ID_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_ID_DIT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_ID_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_MI_ID_DIT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_ID_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_ID_DIT_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_SI_ID_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_ID_DIT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_SI_ID_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_ID_DIT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_SI_ID_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_G_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_G_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_G_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_TT_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_ID_TT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_TT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_ID_TT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_TT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_ID_TT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_TT_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_ID_TT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_TT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_ID_TT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_TT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_ID_TT_QCH),
|
|
SFR_ACCESS(QCH_CON_NOCL1B_CMU_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_NOCL1B_CMU_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_NOCL1B_CMU_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_NOCL1B_CMU_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_NOCL1B_CMU_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_NOCL1B_CMU_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_QCH_ENABLE, 0, 1, QCH_CON_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DIT_QCH_ENABLE, 0, 1, QCH_CON_PPMU_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DIT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_DIT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D_TT_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D_TT_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D_TT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D_TT_QCH),
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SFR_ACCESS(QCH_CON_PPMU_D_TT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D_TT_QCH),
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SFR_ACCESS(QCH_CON_QE_PDMA_QCH_ENABLE, 0, 1, QCH_CON_QE_PDMA_QCH),
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SFR_ACCESS(QCH_CON_QE_PDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDMA_QCH),
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SFR_ACCESS(QCH_CON_QE_PDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDMA_QCH),
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SFR_ACCESS(QCH_CON_QE_SPDMA_QCH_ENABLE, 0, 1, QCH_CON_QE_SPDMA_QCH),
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SFR_ACCESS(QCH_CON_QE_SPDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_SPDMA_QCH),
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SFR_ACCESS(QCH_CON_QE_SPDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_SPDMA_QCH),
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SFR_ACCESS(QCH_CON_SIU_8X1_P0_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_SIU_8X1_P0_NOCL1B_QCH),
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SFR_ACCESS(QCH_CON_SIU_8X1_P0_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIU_8X1_P0_NOCL1B_QCH),
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SFR_ACCESS(QCH_CON_SIU_8X1_P0_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIU_8X1_P0_NOCL1B_QCH),
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SFR_ACCESS(QCH_CON_SLH_ACEL_MI_D_HSI0_QCH_ENABLE, 0, 1, QCH_CON_SLH_ACEL_MI_D_HSI0_QCH),
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SFR_ACCESS(QCH_CON_SLH_ACEL_MI_D_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_ACEL_MI_D_HSI0_QCH),
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SFR_ACCESS(QCH_CON_SLH_ACEL_MI_D_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_ACEL_MI_D_HSI0_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_HSI0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_HSI0_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_HSI0_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_HSI0_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_UFS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_UFS_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_UFS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_UFS_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_UFS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_UFS_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_PPMU_DIT_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_IG_PPMU_DIT_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_PPMU_DIT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_IG_PPMU_DIT_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_PPMU_DIT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_IG_PPMU_DIT_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_PPMU_TREXP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_IG_PPMU_TREXP_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_PPMU_TREXP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_IG_PPMU_TREXP_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_PPMU_TREXP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_IG_PPMU_TREXP_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_PPMU_XIU_D_TT_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_IG_PPMU_XIU_D_TT_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_PPMU_XIU_D_TT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_IG_PPMU_XIU_D_TT_QCH),
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SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_PPMU_XIU_D_TT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_IG_PPMU_XIU_D_TT_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_NOCL1B_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_PPMU_DIT_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_IG_PPMU_DIT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_PPMU_DIT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_IG_PPMU_DIT_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_PPMU_DIT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_IG_PPMU_DIT_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_PPMU_TREXP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_IG_PPMU_TREXP_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_PPMU_TREXP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_IG_PPMU_TREXP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_PPMU_TREXP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_IG_PPMU_TREXP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_PPMU_XIU_D_TT_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_IG_PPMU_XIU_D_TT_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_PPMU_XIU_D_TT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_IG_PPMU_XIU_D_TT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_PPMU_XIU_D_TT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_IG_PPMU_XIU_D_TT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_HSI0_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_HSI0_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_HSI0_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_UFS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_UFS_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_UFS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_UFS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_UFS_QCH),
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|
SFR_ACCESS(QCH_CON_SPDMA_QCH_ENABLE, 0, 1, QCH_CON_SPDMA_QCH),
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|
SFR_ACCESS(QCH_CON_SPDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPDMA_QCH),
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|
SFR_ACCESS(QCH_CON_SPDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPDMA_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_S2_DIT_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_S2_DIT_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_S2_DIT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_S2_DIT_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_S2_DIT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_S2_DIT_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_S2_TT_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_S2_TT_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_S2_TT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_S2_TT_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_S2_TT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_S2_TT_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_NOCL1B_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_TREX_P_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_P_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_NOCL1B_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_PDMA_QCH_ENABLE, 0, 1, QCH_CON_VGEN_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_PDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_PDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_PDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_SPDMA_QCH_ENABLE, 0, 1, QCH_CON_VGEN_SPDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_SPDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_SPDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_SPDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_SPDMA_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_NOCL1C_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_NOCL1C_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_NOCL1C_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_NOCL1C_CMUREF_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_CMU_NOCL1C_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_NOCL1C_CMUREF_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NOCL1C_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NOCL1C_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_NOCL1C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1C_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_G_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1C_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_G_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_G_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_BRP_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D0_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_BRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D0_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_BRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D0_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D0_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_YUVP_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D0_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_YUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D0_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_YUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D0_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_BRP_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D1_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_BRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D1_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_BRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D1_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D1_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D1_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_BRP_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D2_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_BRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D2_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_BRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D2_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D2_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D2_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D2_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D2_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D3_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D3_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D3_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D3_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D3_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D3_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D4_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D4_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D4_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D4_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D4_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D4_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_CSTAT_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_CSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_D_CSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_NOCL1C_CMU_NOCL1C_QCH_ENABLE, 0, 1, QCH_CON_NOCL1C_CMU_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_NOCL1C_CMU_NOCL1C_QCH_CLOCK_REQ, 1, 1, QCH_CON_NOCL1C_CMU_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_NOCL1C_CMU_NOCL1C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_NOCL1C_CMU_NOCL1C_QCH),
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|
SFR_ACCESS(QCH_CON_SIU_8X1_P0_NOCL1C_QCH_ENABLE, 0, 1, QCH_CON_SIU_8X1_P0_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_8X1_P0_NOCL1C_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIU_8X1_P0_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_8X1_P0_NOCL1C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIU_8X1_P0_NOCL1C_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_BRP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_BRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_BRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_BRP_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_CSIS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_CSIS_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_CSTAT_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_CSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_CSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_CSTAT_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MCSC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_MCSC_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_MCSC_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_YUVP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_G_PPMU_YUVP_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_YUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_G_PPMU_YUVP_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_G_PPMU_YUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_G_PPMU_YUVP_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1C_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1C_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1C_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1C_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_IG_PPMU_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_NOCL1C_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_NOCL1C_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_NOCL1C_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_NOCL1C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1C_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1C_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_IG_PPMU_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D0_MCSC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_D0_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D0_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_D0_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D0_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_D0_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D1_YUVP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_D1_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D1_YUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_D1_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_D1_YUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_D1_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_BRP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_BRP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_BRP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_BRP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CSIS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_CSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CSTAT_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_CSTAT_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MCSC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_YUVP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_YUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_YUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NOCL1C_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NOCL1C_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_NOCL1C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_NOCL1C_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_NOCL1C_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_D_NOCL1C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_NOCL1C_QCH_ENABLE, 0, 1, QCH_CON_TREX_P_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_NOCL1C_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_TREX_P_NOCL1C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_P_NOCL1C_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_GPIO_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_I3C00_QCH_S_ENABLE, 0, 1, QCH_CON_I3C00_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C00_QCH_S_CLOCK_REQ, 1, 1, QCH_CON_I3C00_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C00_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C00_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C00_QCH_P_ENABLE, 0, 1, QCH_CON_I3C00_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C00_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_I3C00_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C00_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C00_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C01_QCH_S_ENABLE, 0, 1, QCH_CON_I3C01_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C01_QCH_S_CLOCK_REQ, 1, 1, QCH_CON_I3C01_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C01_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C01_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C01_QCH_P_ENABLE, 0, 1, QCH_CON_I3C01_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C01_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_I3C01_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C01_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C01_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C02_QCH_S_ENABLE, 0, 1, QCH_CON_I3C02_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C02_QCH_S_CLOCK_REQ, 1, 1, QCH_CON_I3C02_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C02_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C02_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C02_QCH_P_ENABLE, 0, 1, QCH_CON_I3C02_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C02_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_I3C02_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C02_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C02_QCH_P),
|
|
SFR_ACCESS(QCH_CON_PERIC0_CMU_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_PERIC0_CMU_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC0_CMU_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_CMU_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC0_CMU_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_CMU_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_PERIC0_QCH),
|
|
SFR_ACCESS(QCH_CON_USI04_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI04_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI04_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI04_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI04_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI04_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI04_USI_QCH_ENABLE, 0, 1, QCH_CON_USI04_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI04_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI04_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI04_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI04_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_BT_UART_QCH_ENABLE, 0, 1, QCH_CON_BT_UART_QCH),
|
|
SFR_ACCESS(QCH_CON_BT_UART_QCH_CLOCK_REQ, 1, 1, QCH_CON_BT_UART_QCH),
|
|
SFR_ACCESS(QCH_CON_BT_UART_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BT_UART_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_GPIO_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC1_CMU_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_PERIC1_CMU_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC1_CMU_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PERIC1_CMU_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC1_CMU_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC1_CMU_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_PERIC1_QCH),
|
|
SFR_ACCESS(QCH_CON_USI07_SPI_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI07_SPI_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI07_SPI_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI07_SPI_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI07_SPI_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI07_SPI_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI07_USI_QCH_ENABLE, 0, 1, QCH_CON_USI07_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI07_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI07_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI07_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI07_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI08_SPI_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI08_SPI_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI08_SPI_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI08_SPI_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI08_SPI_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI08_SPI_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI08_USI_QCH_ENABLE, 0, 1, QCH_CON_USI08_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI08_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI08_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI08_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI08_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI09_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI09_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI09_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI09_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI09_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI09_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI09_USI_QCH_ENABLE, 0, 1, QCH_CON_USI09_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI09_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI09_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI09_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI09_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI10_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI10_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI10_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI10_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI10_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI10_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI10_USI_QCH_ENABLE, 0, 1, QCH_CON_USI10_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI10_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI10_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI10_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI10_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_DBG_UART_QCH_ENABLE, 0, 1, QCH_CON_DBG_UART_QCH),
|
|
SFR_ACCESS(QCH_CON_DBG_UART_QCH_CLOCK_REQ, 1, 1, QCH_CON_DBG_UART_QCH),
|
|
SFR_ACCESS(QCH_CON_DBG_UART_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DBG_UART_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC2_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC2_QCH_ENABLE, 0, 1, QCH_CON_GPIO_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_PERIC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_I3C03_OIS_QCH_S_ENABLE, 0, 1, QCH_CON_I3C03_OIS_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C03_OIS_QCH_S_CLOCK_REQ, 1, 1, QCH_CON_I3C03_OIS_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C03_OIS_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C03_OIS_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C03_OIS_QCH_P_ENABLE, 0, 1, QCH_CON_I3C03_OIS_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C03_OIS_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_I3C03_OIS_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C03_OIS_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C03_OIS_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C04_QCH_S_ENABLE, 0, 1, QCH_CON_I3C04_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C04_QCH_S_CLOCK_REQ, 1, 1, QCH_CON_I3C04_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C04_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C04_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C04_QCH_P_ENABLE, 0, 1, QCH_CON_I3C04_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C04_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_I3C04_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C04_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C04_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C05_QCH_S_ENABLE, 0, 1, QCH_CON_I3C05_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C05_QCH_S_CLOCK_REQ, 1, 1, QCH_CON_I3C05_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C05_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C05_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C05_QCH_P_ENABLE, 0, 1, QCH_CON_I3C05_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C05_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_I3C05_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C05_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C05_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C06_QCH_S_ENABLE, 0, 1, QCH_CON_I3C06_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C06_QCH_S_CLOCK_REQ, 1, 1, QCH_CON_I3C06_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C06_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C06_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C06_QCH_P_ENABLE, 0, 1, QCH_CON_I3C06_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C06_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_I3C06_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C06_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C06_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C07_QCH_S_ENABLE, 0, 1, QCH_CON_I3C07_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C07_QCH_S_CLOCK_REQ, 1, 1, QCH_CON_I3C07_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C07_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C07_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C07_QCH_P_ENABLE, 0, 1, QCH_CON_I3C07_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C07_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_I3C07_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C07_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C07_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C08_QCH_S_ENABLE, 0, 1, QCH_CON_I3C08_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C08_QCH_S_CLOCK_REQ, 1, 1, QCH_CON_I3C08_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C08_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C08_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C08_QCH_P_ENABLE, 0, 1, QCH_CON_I3C08_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C08_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_I3C08_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C08_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C08_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C09_QCH_S_ENABLE, 0, 1, QCH_CON_I3C09_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C09_QCH_S_CLOCK_REQ, 1, 1, QCH_CON_I3C09_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C09_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C09_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C09_QCH_P_ENABLE, 0, 1, QCH_CON_I3C09_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C09_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_I3C09_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C09_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C09_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C10_QCH_S_ENABLE, 0, 1, QCH_CON_I3C10_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C10_QCH_S_CLOCK_REQ, 1, 1, QCH_CON_I3C10_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C10_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C10_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C10_QCH_P_ENABLE, 0, 1, QCH_CON_I3C10_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C10_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_I3C10_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C10_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C10_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C11_QCH_S_ENABLE, 0, 1, QCH_CON_I3C11_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C11_QCH_S_CLOCK_REQ, 1, 1, QCH_CON_I3C11_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C11_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C11_QCH_S),
|
|
SFR_ACCESS(QCH_CON_I3C11_QCH_P_ENABLE, 0, 1, QCH_CON_I3C11_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C11_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_I3C11_QCH_P),
|
|
SFR_ACCESS(QCH_CON_I3C11_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C11_QCH_P),
|
|
SFR_ACCESS(QCH_CON_PERIC2_CMU_PERIC2_QCH_ENABLE, 0, 1, QCH_CON_PERIC2_CMU_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC2_CMU_PERIC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PERIC2_CMU_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_PERIC2_CMU_PERIC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC2_CMU_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_QCH_ENABLE, 0, 1, QCH_CON_PWM_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_QCH_CLOCK_REQ, 1, 1, QCH_CON_PWM_QCH),
|
|
SFR_ACCESS(QCH_CON_PWM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PWM_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_CSISPERIC2_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LP_CSISPERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_CSISPERIC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LP_CSISPERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_CSISPERIC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LP_CSISPERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIC2_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH_ENABLE, 0, 1, QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC2_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_PERIC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_PERIC2_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_SPI_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI00_SPI_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_SPI_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI00_SPI_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_SPI_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI00_SPI_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_USI_QCH_ENABLE, 0, 1, QCH_CON_USI00_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI00_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI00_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI00_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI01_SPI_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI01_SPI_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI01_SPI_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI01_SPI_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI01_SPI_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI01_SPI_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI01_USI_QCH_ENABLE, 0, 1, QCH_CON_USI01_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI01_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI01_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI01_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI01_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI02_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI02_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI02_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI02_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI02_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI02_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI02_USI_QCH_ENABLE, 0, 1, QCH_CON_USI02_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI02_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI02_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI02_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI02_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI03_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI03_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI03_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI03_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI03_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI03_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI03_USI_QCH_ENABLE, 0, 1, QCH_CON_USI03_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI03_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI03_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI03_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI03_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI05_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI05_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI05_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI05_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI05_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI05_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI05_USI_OIS_QCH_ENABLE, 0, 1, QCH_CON_USI05_USI_OIS_QCH),
|
|
SFR_ACCESS(QCH_CON_USI05_USI_OIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI05_USI_OIS_QCH),
|
|
SFR_ACCESS(QCH_CON_USI05_USI_OIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI05_USI_OIS_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI06_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI06_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI06_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_USI_OIS_QCH_ENABLE, 0, 1, QCH_CON_USI06_USI_OIS_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_USI_OIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI06_USI_OIS_QCH),
|
|
SFR_ACCESS(QCH_CON_USI06_USI_OIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI06_USI_OIS_QCH),
|
|
SFR_ACCESS(QCH_CON_USI11_I2C_QCH_ENABLE, 0, 1, QCH_CON_USI11_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI11_I2C_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI11_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI11_I2C_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI11_I2C_QCH),
|
|
SFR_ACCESS(QCH_CON_USI11_USI_QCH_ENABLE, 0, 1, QCH_CON_USI11_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI11_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI11_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_USI11_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI11_USI_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_DDD_PERIS_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_DDD_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_DDD_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_DDD_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_DDD_PERIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_DDD_PERIS_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_PERIS_QCH_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_PERIS_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_PERIS_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_PERIS_QCH),
|
|
SFR_ACCESS(DMYQCH_CON_DFTMUX_PERIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIS_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_PERIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_PERIS_QCH),
|
|
SFR_ACCESS(QCH_CON_GIC_QCH_ENABLE, 0, 1, QCH_CON_GIC_QCH),
|
|
SFR_ACCESS(QCH_CON_GIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_GIC_QCH),
|
|
SFR_ACCESS(QCH_CON_GIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GIC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_QCH),
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SFR_ACCESS(QCH_CON_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_QCH),
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SFR_ACCESS(QCH_CON_MCT_QCH_ENABLE, 0, 1, QCH_CON_MCT_QCH),
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SFR_ACCESS(QCH_CON_MCT_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCT_QCH),
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SFR_ACCESS(QCH_CON_MCT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCT_QCH),
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SFR_ACCESS(QCH_CON_OTP_CON_BIRA_QCH_ENABLE, 0, 1, QCH_CON_OTP_CON_BIRA_QCH),
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SFR_ACCESS(QCH_CON_OTP_CON_BIRA_QCH_CLOCK_REQ, 1, 1, QCH_CON_OTP_CON_BIRA_QCH),
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SFR_ACCESS(QCH_CON_OTP_CON_BIRA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_OTP_CON_BIRA_QCH),
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|
SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_ENABLE, 0, 1, QCH_CON_OTP_CON_TOP_QCH),
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SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_OTP_CON_TOP_QCH),
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SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_OTP_CON_TOP_QCH),
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SFR_ACCESS(QCH_CON_PERIS_CMU_PERIS_QCH_ENABLE, 0, 1, QCH_CON_PERIS_CMU_PERIS_QCH),
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SFR_ACCESS(QCH_CON_PERIS_CMU_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_PERIS_CMU_PERIS_QCH),
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SFR_ACCESS(QCH_CON_PERIS_CMU_PERIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIS_CMU_PERIS_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_PERIS_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_PERIS_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_PERIS_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERISGIC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_PERISGIC_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERISGIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_PERISGIC_QCH),
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SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERISGIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_PERISGIC_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_PERIS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PERIS_QCH),
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SFR_ACCESS(QCH_CON_SYSREG_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PERIS_QCH),
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|
SFR_ACCESS(QCH_CON_SYSREG_PERIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_PERIS_QCH),
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|
SFR_ACCESS(QCH_CON_TMU_SUB_QCH_ENABLE, 0, 1, QCH_CON_TMU_SUB_QCH),
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|
SFR_ACCESS(QCH_CON_TMU_SUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_TMU_SUB_QCH),
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SFR_ACCESS(QCH_CON_TMU_SUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TMU_SUB_QCH),
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|
SFR_ACCESS(QCH_CON_TMU_TOP_QCH_ENABLE, 0, 1, QCH_CON_TMU_TOP_QCH),
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|
SFR_ACCESS(QCH_CON_TMU_TOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_TMU_TOP_QCH),
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|
SFR_ACCESS(QCH_CON_TMU_TOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TMU_TOP_QCH),
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|
SFR_ACCESS(QCH_CON_WDT0_QCH_ENABLE, 0, 1, QCH_CON_WDT0_QCH),
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|
SFR_ACCESS(QCH_CON_WDT0_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT0_QCH),
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|
SFR_ACCESS(QCH_CON_WDT0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT0_QCH),
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|
SFR_ACCESS(QCH_CON_WDT1_QCH_ENABLE, 0, 1, QCH_CON_WDT1_QCH),
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|
SFR_ACCESS(QCH_CON_WDT1_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT1_QCH),
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|
SFR_ACCESS(QCH_CON_WDT1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT1_QCH),
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|
SFR_ACCESS(DMYQCH_CON_BIS_S2D_QCH_ENABLE, 0, 1, DMYQCH_CON_BIS_S2D_QCH),
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|
SFR_ACCESS(DMYQCH_CON_BIS_S2D_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_BIS_S2D_QCH),
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|
SFR_ACCESS(DMYQCH_CON_BIS_S2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_BIS_S2D_QCH),
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|
SFR_ACCESS(QCH_CON_S2D_CMU_S2D_QCH_ENABLE, 0, 1, QCH_CON_S2D_CMU_S2D_QCH),
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|
SFR_ACCESS(QCH_CON_S2D_CMU_S2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_S2D_CMU_S2D_QCH),
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|
SFR_ACCESS(QCH_CON_S2D_CMU_S2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_S2D_CMU_S2D_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH),
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|
SFR_ACCESS(QCH_CON_D_TZPC_SDMA_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_SDMA_QCH),
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|
SFR_ACCESS(QCH_CON_D_TZPC_SDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_SDMA_QCH),
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|
SFR_ACCESS(QCH_CON_D_TZPC_SDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_SDMA_QCH),
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|
SFR_ACCESS(QCH_CON_IP_SDMA_QCH_ENABLE, 0, 1, QCH_CON_IP_SDMA_QCH),
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|
SFR_ACCESS(QCH_CON_IP_SDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_IP_SDMA_QCH),
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|
SFR_ACCESS(QCH_CON_IP_SDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IP_SDMA_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AST_SI_LD_STRM_SDMADSP0_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_LD_STRM_SDMADSP0_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AST_SI_LD_STRM_SDMADSP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_LD_STRM_SDMADSP0_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AST_SI_LD_STRM_SDMADSP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_LD_STRM_SDMADSP0_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LP_DNCSDMA_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LP_DNCSDMA_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LP_DNCSDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LP_DNCSDMA_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_MI_LP_DNCSDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LP_DNCSDMA_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA0_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA0_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA0_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA1_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA1_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA1_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA1_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA2_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA2_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA2_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA2_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA3_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA3_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA3_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA3_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA3_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA4_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA4_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA4_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA4_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA4_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA4_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA5_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA5_QCH),
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SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA5_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA5_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA5_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA5_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA6_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA6_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA6_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA6_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA6_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA6_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA7_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA7_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA7_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA7_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA7_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_DATA7_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU0_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU0_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU0_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU1_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU1_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU1_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU1_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU2_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU2_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU2_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU2_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU3_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU3_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU3_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU3_QCH),
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|
SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_SDMADNC_MMU3_QCH),
|
|
SFR_ACCESS(QCH_CON_SDMA_CMU_SDMA_QCH_ENABLE, 0, 1, QCH_CON_SDMA_CMU_SDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SDMA_CMU_SDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SDMA_CMU_SDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SDMA_CMU_SDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SDMA_CMU_SDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_SDMA_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LP_SDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_SDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LP_SDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_SDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LP_SDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_SDMA_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_SDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_SDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_SDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_SDMA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_SDMA_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_SSS_QCH_ENABLE, 0, 1, QCH_CON_BAAW_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_SSP_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_HW_APBSEMA_MEC_QCH_ENABLE, 0, 1, QCH_CON_HW_APBSEMA_MEC_QCH),
|
|
SFR_ACCESS(QCH_CON_HW_APBSEMA_MEC_QCH_CLOCK_REQ, 1, 1, QCH_CON_HW_APBSEMA_MEC_QCH),
|
|
SFR_ACCESS(QCH_CON_HW_APBSEMA_MEC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HW_APBSEMA_MEC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_L_STRONG_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_L_STRONG_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_L_STRONG_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_L_STRONG_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_L_STRONG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_L_STRONG_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_SSP_QCH_ENABLE, 0, 1, QCH_CON_PPMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_SSS_QCH_ENABLE, 0, 1, QCH_CON_QE_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRONG_QCH_ENABLE, 0, 1, QCH_CON_QE_STRONG_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRONG_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_STRONG_QCH),
|
|
SFR_ACCESS(QCH_CON_QE_STRONG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_STRONG_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_ACEL_SI_D_SSP_QCH_ENABLE, 0, 1, QCH_CON_SLH_ACEL_SI_D_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_ACEL_SI_D_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_ACEL_SI_D_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_ACEL_SI_D_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_ACEL_SI_D_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_SSP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_SSP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SSP_CMU_SSP_QCH_ENABLE, 0, 1, QCH_CON_SSP_CMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SSP_CMU_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSP_CMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SSP_CMU_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSP_CMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SSS_QCH_ENABLE, 0, 1, QCH_CON_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SSP_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_SSP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_SSP_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_SSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_SSP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_SSP_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_QCH),
|
|
SFR_ACCESS(QCH_CON_STRONG_CMU_STRONG_QCH_ENABLE, 0, 1, QCH_CON_STRONG_CMU_STRONG_QCH),
|
|
SFR_ACCESS(QCH_CON_STRONG_CMU_STRONG_QCH_CLOCK_REQ, 1, 1, QCH_CON_STRONG_CMU_STRONG_QCH),
|
|
SFR_ACCESS(QCH_CON_STRONG_CMU_STRONG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_STRONG_CMU_STRONG_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_UFDDNC_QCH_ENABLE, 0, 1, QCH_CON_BAAW_D_UFDDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_UFDDNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_D_UFDDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_D_UFDDNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_D_UFDDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_UFD_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_UFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_UFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_I3C_UFD_QCH_PCLK_ENABLE, 0, 1, QCH_CON_I3C_UFD_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_I3C_UFD_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_I3C_UFD_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_I3C_UFD_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C_UFD_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_I3C_UFD_QCH_SCLK_ENABLE, 0, 1, QCH_CON_I3C_UFD_QCH_SCLK),
|
|
SFR_ACCESS(QCH_CON_I3C_UFD_QCH_SCLK_CLOCK_REQ, 1, 1, QCH_CON_I3C_UFD_QCH_SCLK),
|
|
SFR_ACCESS(QCH_CON_I3C_UFD_QCH_SCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C_UFD_QCH_SCLK),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_UFDDNC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF_UFDDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_UFDDNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF_UFDDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF_UFDDNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF_UFDDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_UFD_QCH_ENABLE, 0, 1, QCH_CON_PDMA_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_UFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_PDMA_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_PDMA_UFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PDMA_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D_UFD_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D_UFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D_UFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_OTF_CSISUFD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_MI_OTF_CSISUFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_OTF_CSISUFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_MI_OTF_CSISUFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_MI_OTF_CSISUFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_MI_OTF_CSISUFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_UFD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_UFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_UFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_CMGPUFD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LP_CMGPUFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_CMGPUFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LP_CMGPUFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP_CMGPUFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LP_CMGPUFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_UFD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_UFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_UFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_UFD_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_D_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_UFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_D_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D_UFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_D_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LD_UFDDNC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LD_UFDDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LD_UFDDNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LD_UFDDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LD_UFDDNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LD_UFDDNC_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_UFDCSIS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LP_UFDCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_UFDCSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LP_UFDCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP_UFDCSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LP_UFDCSIS_QCH),
|
|
SFR_ACCESS(QCH_CON_SRAM_MIU_UFD_QCH_ENABLE, 0, 1, QCH_CON_SRAM_MIU_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SRAM_MIU_UFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SRAM_MIU_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SRAM_MIU_UFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SRAM_MIU_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_UFD_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D_UFD_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_UFD_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_UFD_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_UFD_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_UFD_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_UFD_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D_UFD_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_UFD_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_UFD_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D_UFD_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_UFD_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_UFD_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_UFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_UFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_UFD_SECURE_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_UFD_SECURE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_UFD_SECURE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_UFD_SECURE_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_UFD_SECURE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_UFD_SECURE_QCH),
|
|
SFR_ACCESS(QCH_CON_UFD_CMU_UFD_QCH_ENABLE, 0, 1, QCH_CON_UFD_CMU_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFD_CMU_UFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_UFD_CMU_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFD_CMU_UFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UFD_CMU_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D_UFD_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D_UFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D_UFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFD_QCH_ENABLE, 0, 1, QCH_CON_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFD_QCH_CLOCK_REQ, 1, 1, QCH_CON_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UFD_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_UFS_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_UFS_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_UFS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_HSI1UFS_QCH_ENABLE, 0, 1, QCH_CON_GPIO_HSI1UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_HSI1UFS_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_HSI1UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_HSI1UFS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_HSI1UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_UFS_QCH_ENABLE, 0, 1, QCH_CON_GPIO_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_UFS_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_UFS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_UFS_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_SI_D_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_UFS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_SI_D_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_UFS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_SI_D_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_MMC_CARD_QCH_ENABLE, 0, 1, QCH_CON_MMC_CARD_QCH),
|
|
SFR_ACCESS(QCH_CON_MMC_CARD_QCH_CLOCK_REQ, 1, 1, QCH_CON_MMC_CARD_QCH),
|
|
SFR_ACCESS(QCH_CON_MMC_CARD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MMC_CARD_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_UFS_QCH_ENABLE, 0, 1, QCH_CON_PPMU_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_UFS_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_UFS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_UFS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_UFS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_UFS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_UFS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_UFS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_UFS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_SPC_UFS_QCH_ENABLE, 0, 1, QCH_CON_SPC_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_SPC_UFS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPC_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_SPC_UFS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPC_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_UFS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_UFS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_UFS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_UFS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_UFS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_UFS_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_UFS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_UFS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_UFS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_CMU_UFS_QCH_ENABLE, 0, 1, QCH_CON_UFS_CMU_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_CMU_UFS_QCH_CLOCK_REQ, 1, 1, QCH_CON_UFS_CMU_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_CMU_UFS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UFS_CMU_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_ENABLE, 0, 1, QCH_CON_UFS_EMBD_QCH_FMP),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ, 1, 1, QCH_CON_UFS_EMBD_QCH_FMP),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UFS_EMBD_QCH_FMP),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_ENABLE, 0, 1, QCH_CON_UFS_EMBD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_CLOCK_REQ, 1, 1, QCH_CON_UFS_EMBD_QCH),
|
|
SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UFS_EMBD_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_UFS_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_UFS_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_UFS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_UFS_QCH),
|
|
SFR_ACCESS(QCH_CON_ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT_ENABLE, 0, 1, QCH_CON_ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT),
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|
SFR_ACCESS(QCH_CON_ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT_CLOCK_REQ, 1, 1, QCH_CON_ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT),
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|
SFR_ACCESS(QCH_CON_ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT),
|
|
SFR_ACCESS(QCH_CON_BAAW_VTS_QCH_ENABLE, 0, 1, QCH_CON_BAAW_VTS_QCH),
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|
SFR_ACCESS(QCH_CON_BAAW_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_BAAW_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF0_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_IF0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF0_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_IF0_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF0_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_IF0_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF0_QCH_DMIC_ENABLE, 0, 1, DMYQCH_CON_DMIC_IF0_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF0_QCH_DMIC_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_IF0_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF0_QCH_DMIC_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DMIC_IF0_QCH_DMIC),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF1_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_IF1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF1_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_IF1_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF1_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_IF1_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF1_QCH_DMIC_ENABLE, 0, 1, DMYQCH_CON_DMIC_IF1_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF1_QCH_DMIC_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_IF1_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF1_QCH_DMIC_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DMIC_IF1_QCH_DMIC),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF2_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_IF2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF2_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_IF2_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_DMIC_IF2_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMIC_IF2_QCH_PCLK),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF2_QCH_DMIC_ENABLE, 0, 1, DMYQCH_CON_DMIC_IF2_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF2_QCH_DMIC_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_IF2_QCH_DMIC),
|
|
SFR_ACCESS(DMYQCH_CON_DMIC_IF2_QCH_DMIC_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DMIC_IF2_QCH_DMIC),
|
|
SFR_ACCESS(QCH_CON_GPIO_VTS_QCH_ENABLE, 0, 1, QCH_CON_GPIO_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_GPIO_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_CODE_QCH_ENABLE, 0, 1, QCH_CON_INTMEM_CODE_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_CODE_QCH_CLOCK_REQ, 1, 1, QCH_CON_INTMEM_CODE_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_CODE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_INTMEM_CODE_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_DATA0_QCH_ENABLE, 0, 1, QCH_CON_INTMEM_DATA0_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_DATA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_INTMEM_DATA0_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_DATA0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_INTMEM_DATA0_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_DATA1_QCH_ENABLE, 0, 1, QCH_CON_INTMEM_DATA1_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_DATA1_QCH_CLOCK_REQ, 1, 1, QCH_CON_INTMEM_DATA1_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_DATA1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_INTMEM_DATA1_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_PCM_QCH_ENABLE, 0, 1, QCH_CON_INTMEM_PCM_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_PCM_QCH_CLOCK_REQ, 1, 1, QCH_CON_INTMEM_PCM_QCH),
|
|
SFR_ACCESS(QCH_CON_INTMEM_PCM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_INTMEM_PCM_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_VC2VTS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_IP_VC2VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_VC2VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_IP_VC2VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_VC2VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_IP_VC2VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_VTS2VC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_ID_VTS2VC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_VTS2VC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_ID_VTS2VC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_VTS2VC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_ID_VTS2VC_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_ABOX_VTS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_ABOX_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_ABOX_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_ABOX_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_ABOX_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_ABOX_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_VTS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_AP_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_DNC_VTS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_DNC_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_DNC_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_DNC_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_MAILBOX_DNC_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_DNC_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_VT_QCH_PCLK_ENABLE, 0, 1, QCH_CON_SERIAL_LIF_VT_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_VT_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_SERIAL_LIF_VT_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_VT_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SERIAL_LIF_VT_QCH_PCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_VT_QCH_CCLK_ENABLE, 0, 1, QCH_CON_SERIAL_LIF_VT_QCH_CCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_VT_QCH_CCLK_CLOCK_REQ, 1, 1, QCH_CON_SERIAL_LIF_VT_QCH_CCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_VT_QCH_CCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SERIAL_LIF_VT_QCH_CCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_VT_QCH_ACLK_ENABLE, 0, 1, QCH_CON_SERIAL_LIF_VT_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_VT_QCH_ACLK_CLOCK_REQ, 1, 1, QCH_CON_SERIAL_LIF_VT_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_VT_QCH_ACLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SERIAL_LIF_VT_QCH_ACLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_VT_QCH_BCLK_ENABLE, 0, 1, QCH_CON_SERIAL_LIF_VT_QCH_BCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_VT_QCH_BCLK_CLOCK_REQ, 1, 1, QCH_CON_SERIAL_LIF_VT_QCH_BCLK),
|
|
SFR_ACCESS(QCH_CON_SERIAL_LIF_VT_QCH_BCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SERIAL_LIF_VT_QCH_BCLK),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_ENABLE, 0, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_CLOCK_REQ, 1, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_ENABLE, 0, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_CLOCK_REQ, 1, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2_ENABLE, 0, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2_CLOCK_REQ, 1, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD2),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK_ENABLE, 0, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK_CLOCK_REQ, 1, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK),
|
|
SFR_ACCESS(DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK),
|
|
SFR_ACCESS(QCH_CON_SYSREG_VTS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_QCH_ENABLE, 0, 1, QCH_CON_TIMER_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_QCH_CLOCK_REQ, 1, 1, QCH_CON_TIMER_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TIMER_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER1_QCH_ENABLE, 0, 1, QCH_CON_TIMER1_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER1_QCH_CLOCK_REQ, 1, 1, QCH_CON_TIMER1_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TIMER1_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER2_QCH_ENABLE, 0, 1, QCH_CON_TIMER2_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER2_QCH_CLOCK_REQ, 1, 1, QCH_CON_TIMER2_QCH),
|
|
SFR_ACCESS(QCH_CON_TIMER2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TIMER2_QCH),
|
|
SFR_ACCESS(QCH_CON_VTS_CMU_VTS_QCH_ENABLE, 0, 1, QCH_CON_VTS_CMU_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_VTS_CMU_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_VTS_CMU_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_VTS_CMU_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VTS_CMU_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_VTS_QCH_ENABLE, 0, 1, QCH_CON_WDT_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_WDT_VTS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_VTS_QCH),
|
|
SFR_ACCESS(QCH_CON_YAMIN_MCU_VTS_QCH_CLKIN_ENABLE, 0, 1, QCH_CON_YAMIN_MCU_VTS_QCH_CLKIN),
|
|
SFR_ACCESS(QCH_CON_YAMIN_MCU_VTS_QCH_CLKIN_CLOCK_REQ, 1, 1, QCH_CON_YAMIN_MCU_VTS_QCH_CLKIN),
|
|
SFR_ACCESS(QCH_CON_YAMIN_MCU_VTS_QCH_CLKIN_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_YAMIN_MCU_VTS_QCH_CLKIN),
|
|
SFR_ACCESS(QCH_CON_YAMIN_MCU_VTS_QCH_DBGCLK_ENABLE, 0, 1, QCH_CON_YAMIN_MCU_VTS_QCH_DBGCLK),
|
|
SFR_ACCESS(QCH_CON_YAMIN_MCU_VTS_QCH_DBGCLK_CLOCK_REQ, 1, 1, QCH_CON_YAMIN_MCU_VTS_QCH_DBGCLK),
|
|
SFR_ACCESS(QCH_CON_YAMIN_MCU_VTS_QCH_DBGCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_YAMIN_MCU_VTS_QCH_DBGCLK),
|
|
SFR_ACCESS(QCH_CON_BUSIF_DDD_YUVP_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_DDD_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_DDD_YUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_DDD_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_BUSIF_DDD_YUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_DDD_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_YUVP_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_YUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_D_TZPC_YUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_MCSCYUVP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_OTF_MCSCYUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_MCSCYUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_OTF_MCSCYUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_MI_OTF_MCSCYUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_OTF_MCSCYUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_YUVPMCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF0_YUVPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_YUVPMCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF0_YUVPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF0_YUVPMCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF0_YUVPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_YUVPMCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_OTF1_YUVPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_YUVPMCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_OTF1_YUVPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AST_SI_OTF1_YUVPMCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_OTF1_YUVPMCSC_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_YUVP_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_YUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_YUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_YUVP_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_YUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D0_YUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_YUVP_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_PPMU_D1_YUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_YUVP_QCH),
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|
SFR_ACCESS(QCH_CON_PPMU_D1_YUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_G_PPMU_YUVP_QCH_ENABLE, 0, 1, QCH_CON_SIU_G_PPMU_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_G_PPMU_YUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIU_G_PPMU_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_SIU_G_PPMU_YUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIU_G_PPMU_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_YUVP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AST_SI_G_PPMU_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_YUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AST_SI_G_PPMU_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AST_SI_G_PPMU_YUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AST_SI_G_PPMU_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_YUVP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_YUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_YUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_YUVP_QCH),
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|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D1_YUVP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_D1_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D1_YUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_D1_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_SLH_AXI_SI_D1_YUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_D1_YUVP_QCH),
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|
SFR_ACCESS(QCH_CON_SYSMMU_D0_YUVP_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_YUVP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_YUVP_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_YUVP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_YUVP_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_YUVP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_YUVP_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_YUVP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_YUVP_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_YUVP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D0_YUVP_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_YUVP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_YUVP_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_YUVP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_YUVP_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_YUVP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_YUVP_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_YUVP_QCH_S1),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_YUVP_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_YUVP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_YUVP_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_YUVP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSMMU_D1_YUVP_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_YUVP_QCH_S2),
|
|
SFR_ACCESS(QCH_CON_SYSREG_YUVP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_YUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_SYSREG_YUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_YUVP_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D0_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_YUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D0_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D0_YUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D0_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_YUVP_QCH_ENABLE, 0, 1, QCH_CON_VGEN_LITE_D1_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_YUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_VGEN_LITE_D1_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_VGEN_LITE_D1_YUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VGEN_LITE_D1_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_YUVP_QCH_ENABLE, 0, 1, QCH_CON_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_YUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_YUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_YUVP_QCH_VOTF0_ENABLE, 0, 1, QCH_CON_YUVP_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_YUVP_QCH_VOTF0_CLOCK_REQ, 1, 1, QCH_CON_YUVP_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_YUVP_QCH_VOTF0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_YUVP_QCH_VOTF0),
|
|
SFR_ACCESS(QCH_CON_YUVP_QCH_VOTF1_ENABLE, 0, 1, QCH_CON_YUVP_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_YUVP_QCH_VOTF1_CLOCK_REQ, 1, 1, QCH_CON_YUVP_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_YUVP_QCH_VOTF1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_YUVP_QCH_VOTF1),
|
|
SFR_ACCESS(QCH_CON_YUVP_CMU_YUVP_QCH_ENABLE, 0, 1, QCH_CON_YUVP_CMU_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_YUVP_CMU_YUVP_QCH_CLOCK_REQ, 1, 1, QCH_CON_YUVP_CMU_YUVP_QCH),
|
|
SFR_ACCESS(QCH_CON_YUVP_CMU_YUVP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_YUVP_CMU_YUVP_QCH),
|
|
SFR_ACCESS(ALIVE_CMU_ALIVE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, ALIVE_CMU_ALIVE_CONTROLLER_OPTION),
|
|
SFR_ACCESS(ALIVE_CMU_ALIVE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, ALIVE_CMU_ALIVE_CONTROLLER_OPTION),
|
|
SFR_ACCESS(ALLCSIS_CMU_ALLCSIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, ALLCSIS_CMU_ALLCSIS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(ALLCSIS_CMU_ALLCSIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, ALLCSIS_CMU_ALLCSIS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, AUD_CMU_AUD_CONTROLLER_OPTION),
|
|
SFR_ACCESS(AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, AUD_CMU_AUD_CONTROLLER_OPTION),
|
|
SFR_ACCESS(BRP_CMU_BRP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, BRP_CMU_BRP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(BRP_CMU_BRP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, BRP_CMU_BRP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CHUB_CMU_CHUB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CHUB_CMU_CHUB_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CHUB_CMU_CHUB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CHUB_CMU_CHUB_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CMGP_CMU_CMGP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CMGP_CMU_CMGP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CMU_CMU_TOP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CMU_CMU_TOP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CSIS_CMU_CSIS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CSIS_CMU_CSIS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CSTAT_CMU_CSTAT_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CSTAT_CMU_CSTAT_CONTROLLER_OPTION),
|
|
SFR_ACCESS(CSTAT_CMU_CSTAT_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CSTAT_CMU_CSTAT_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DBGCORE_CMU_DBGCORE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, DBGCORE_CMU_DBGCORE_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DBGCORE_CMU_DBGCORE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DBGCORE_CMU_DBGCORE_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DNC_CMU_DNC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, DNC_CMU_DNC_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DNC_CMU_DNC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DNC_CMU_DNC_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DPUB_CMU_DPUB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, DPUB_CMU_DPUB_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DPUB_CMU_DPUB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DPUB_CMU_DPUB_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DPUF_CMU_DPUF_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, DPUF_CMU_DPUF_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DPUF_CMU_DPUF_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DPUF_CMU_DPUF_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DPUF1_CMU_DPUF1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, DPUF1_CMU_DPUF1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DPUF1_CMU_DPUF1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DPUF1_CMU_DPUF1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DRCP_CMU_DRCP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, DRCP_CMU_DRCP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DRCP_CMU_DRCP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DRCP_CMU_DRCP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DSP_CMU_DSP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, DSP_CMU_DSP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DSP_CMU_DSP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DSP_CMU_DSP_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DSU_CMU_DSU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, DSU_CMU_DSU_CONTROLLER_OPTION),
|
|
SFR_ACCESS(DSU_CMU_DSU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DSU_CMU_DSU_CONTROLLER_OPTION),
|
|
SFR_ACCESS(G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, G3D_CMU_G3D_CONTROLLER_OPTION),
|
|
SFR_ACCESS(G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, G3D_CMU_G3D_CONTROLLER_OPTION),
|
|
SFR_ACCESS(G3DCORE_CMU_G3DCORE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, G3DCORE_CMU_G3DCORE_CONTROLLER_OPTION),
|
|
SFR_ACCESS(G3DCORE_CMU_G3DCORE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, G3DCORE_CMU_G3DCORE_CONTROLLER_OPTION),
|
|
SFR_ACCESS(GNPU_CMU_GNPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, GNPU_CMU_GNPU_CONTROLLER_OPTION),
|
|
SFR_ACCESS(GNPU_CMU_GNPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, GNPU_CMU_GNPU_CONTROLLER_OPTION),
|
|
SFR_ACCESS(GNSS_CMU_GNSS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, GNSS_CMU_GNSS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(GNSS_CMU_GNSS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, GNSS_CMU_GNSS_CONTROLLER_OPTION),
|
|
SFR_ACCESS(HSI0_CMU_HSI0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, HSI0_CMU_HSI0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(HSI0_CMU_HSI0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, HSI0_CMU_HSI0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(HSI1_CMU_HSI1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, HSI1_CMU_HSI1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(HSI1_CMU_HSI1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, HSI1_CMU_HSI1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(LME_CMU_LME_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, LME_CMU_LME_CONTROLLER_OPTION),
|
|
SFR_ACCESS(LME_CMU_LME_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, LME_CMU_LME_CONTROLLER_OPTION),
|
|
SFR_ACCESS(M2M_CMU_M2M_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, M2M_CMU_M2M_CONTROLLER_OPTION),
|
|
SFR_ACCESS(M2M_CMU_M2M_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, M2M_CMU_M2M_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MCSC_CMU_MCSC_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MCSC_CMU_MCSC_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MFC0_CMU_MFC0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MFC0_CMU_MFC0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MFC0_CMU_MFC0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MFC0_CMU_MFC0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MFC1_CMU_MFC1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MFC1_CMU_MFC1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MFC1_CMU_MFC1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MFC1_CMU_MFC1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MIF_CMU_MIF_CONTROLLER_OPTION),
|
|
SFR_ACCESS(MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MIF_CMU_MIF_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NOCL0_CMU_NOCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, NOCL0_CMU_NOCL0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NOCL0_CMU_NOCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, NOCL0_CMU_NOCL0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NOCL1C_CMU_NOCL1C_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, NOCL1C_CMU_NOCL1C_CONTROLLER_OPTION),
|
|
SFR_ACCESS(NOCL1C_CMU_NOCL1C_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, NOCL1C_CMU_NOCL1C_CONTROLLER_OPTION),
|
|
SFR_ACCESS(PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, PERIC0_CMU_PERIC0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PERIC0_CMU_PERIC0_CONTROLLER_OPTION),
|
|
SFR_ACCESS(PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, PERIC1_CMU_PERIC1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PERIC1_CMU_PERIC1_CONTROLLER_OPTION),
|
|
SFR_ACCESS(PERIC2_CMU_PERIC2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, PERIC2_CMU_PERIC2_CONTROLLER_OPTION),
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SFR_ACCESS(PERIC2_CMU_PERIC2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PERIC2_CMU_PERIC2_CONTROLLER_OPTION),
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SFR_ACCESS(PERIS_CMU_PERIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, PERIS_CMU_PERIS_CONTROLLER_OPTION),
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SFR_ACCESS(PERIS_CMU_PERIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PERIS_CMU_PERIS_CONTROLLER_OPTION),
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SFR_ACCESS(S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, S2D_CMU_S2D_CONTROLLER_OPTION),
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SFR_ACCESS(S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, S2D_CMU_S2D_CONTROLLER_OPTION),
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SFR_ACCESS(SDMA_CMU_SDMA_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, SDMA_CMU_SDMA_CONTROLLER_OPTION),
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SFR_ACCESS(SDMA_CMU_SDMA_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, SDMA_CMU_SDMA_CONTROLLER_OPTION),
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SFR_ACCESS(SSP_CMU_SSP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, SSP_CMU_SSP_CONTROLLER_OPTION),
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SFR_ACCESS(SSP_CMU_SSP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, SSP_CMU_SSP_CONTROLLER_OPTION),
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SFR_ACCESS(STRONG_CMU_STRONG_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, STRONG_CMU_STRONG_CONTROLLER_OPTION),
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SFR_ACCESS(STRONG_CMU_STRONG_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, STRONG_CMU_STRONG_CONTROLLER_OPTION),
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SFR_ACCESS(UFD_CMU_UFD_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, UFD_CMU_UFD_CONTROLLER_OPTION),
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SFR_ACCESS(UFD_CMU_UFD_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, UFD_CMU_UFD_CONTROLLER_OPTION),
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SFR_ACCESS(UFS_CMU_UFS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, UFS_CMU_UFS_CONTROLLER_OPTION),
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SFR_ACCESS(UFS_CMU_UFS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, UFS_CMU_UFS_CONTROLLER_OPTION),
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SFR_ACCESS(VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, VTS_CMU_VTS_CONTROLLER_OPTION),
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SFR_ACCESS(VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, VTS_CMU_VTS_CONTROLLER_OPTION),
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SFR_ACCESS(YUVP_CMU_YUVP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, YUVP_CMU_YUVP_CONTROLLER_OPTION),
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SFR_ACCESS(YUVP_CMU_YUVP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, YUVP_CMU_YUVP_CONTROLLER_OPTION),
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};
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