4993 lines
833 KiB
C
Executable file
4993 lines
833 KiB
C
Executable file
#include "../../cmucal.h"
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#include "cmucal-node.h"
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#include "cmucal-sfr.h"
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struct cmucal_pll_table pll_aud_rate_table[] = {
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PLL_RATE_MPSF(1550000000, 222, 11, 0, 0),
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PLL_RATE_MPSF(1200000000, 125, 8, 0, 0),
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PLL_RATE_MPSF(800000000, 125, 12, 0, 0),
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PLL_RATE_MPSF(400000000, 125, 12, 1, 0),
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};
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struct cmucal_pll_table pll_mmc_rate_table[] = {
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PLL_RATE_MPSF(808000000, 125, 12, 0, 0),
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PLL_RATE_MPSF(404000000, 125, 12, 1, 0),
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PLL_RATE_MPSF(101000000, 125, 12, 3, 0),
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};
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struct cmucal_pll_table pll_shared0_rate_table[] = {
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PLL_RATE_MPSF(1066000000, 111, 8, 0, 0),
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};
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struct cmucal_pll_table pll_shared1_rate_table[] = {
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PLL_RATE_MPSF(936000000, 73, 6, 0, 0),
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};
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struct cmucal_pll_table pll_shared2_rate_table[] = {
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PLL_RATE_MPSF(800000000, 125, 12, 0, 0),
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};
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struct cmucal_pll_table pll_shared3_rate_table[] = {
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PLL_RATE_MPSF(753000000, 87, 9, 0, 0),
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};
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struct cmucal_pll_table pll_shared4_rate_table[] = {
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PLL_RATE_MPSF(670000000, 95, 11, 0, 0),
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};
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struct cmucal_pll_table pll_shared_mif_rate_table[] = {
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PLL_RATE_MPSF(2028000000, 132, 5, 0, 0),
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PLL_RATE_MPSF(1690000000, 66, 3, 0, 0),
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PLL_RATE_MPSF(842000000, 263, 12, 1, 0),
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};
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struct cmucal_pll_table pll_cpucl0_rate_table[] = {
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PLL_RATE_MPSF(2100000000, 82, 3, 0, 0),
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PLL_RATE_MPSF(1900000000, 272, 11, 0, 0),
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PLL_RATE_MPSF(1700000000, 177, 8, 0, 0),
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PLL_RATE_MPSF(1200000000, 125, 8, 0, 0),
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PLL_RATE_MPSF(600000000, 125, 8, 1, 0),
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PLL_RATE_MPSF(200000000, 125, 12, 2, 0),
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};
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struct cmucal_pll_table pll_cpucl1_rate_table[] = {
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PLL_RATE_MPSF(2700000000, 457, 13, 0, 0),
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PLL_RATE_MPSF(2249999872, 205, 7, 0, 0),
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PLL_RATE_MPSF(1850000000, 289, 12, 0, 0),
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PLL_RATE_MPSF(1300000000, 203, 12, 0, 0),
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PLL_RATE_MPSF(650000000, 135, 8, 1, 0),
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PLL_RATE_MPSF(300000000, 125, 8, 2, 0),
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};
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struct cmucal_pll_table pll_cpucl2_rate_table[] = {
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PLL_RATE_MPSF(2950000128, 192, 5, 0, 0),
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PLL_RATE_MPSF(2500000000, 358, 11, 0, 0),
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PLL_RATE_MPSF(2000000000, 78, 3, 0, 0),
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PLL_RATE_MPSF(1400000000, 164, 9, 0, 0),
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PLL_RATE_MPSF(700000000, 82, 9, 0, 0),
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PLL_RATE_MPSF(300000000, 125, 8, 2, 0),
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};
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struct cmucal_pll_table pll_dsu_rate_table[] = {
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PLL_RATE_MPSF(2088999936, 136, 5, 0, 0),
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PLL_RATE_MPSF(1774000000, 254, 11, 0, 0),
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PLL_RATE_MPSF(1467000064, 191, 10, 0, 0),
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PLL_RATE_MPSF(982000000, 115, 9, 0, 0),
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PLL_RATE_MPSF(540000000, 225, 16, 1, 0),
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PLL_RATE_MPSF(200000000, 125, 12, 2, 0),
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};
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struct cmucal_pll_table pll_g3d_rate_table[] = {
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PLL_RATE_MPSF(1300000000, 203, 12, 0, 0),
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PLL_RATE_MPSF(1025000000, 80, 6, 0, 0),
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PLL_RATE_MPSF(750000000, 78, 8, 0, 0),
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PLL_RATE_MPSF(450000000, 82, 7, 1, 0),
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};
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struct cmucal_pll_table pll_g3d1_rate_table[] = {
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PLL_RATE_MPSF(1300000000, 203, 12, 0, 0),
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PLL_RATE_MPSF(1025000000, 80, 6, 0, 0),
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PLL_RATE_MPSF(750000000, 78, 8, 0, 0),
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PLL_RATE_MPSF(450000000, 82, 7, 1, 0),
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};
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struct cmucal_pll_table pll_mif_main_rate_table[] = {
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PLL_RATE_MPSF(4265999872, 361, 13, 0, 0),
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PLL_RATE_MPSF(3080000000, 401, 10, 1, 0),
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PLL_RATE_MPSF(1690000000, 154, 7, 1, 0),
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PLL_RATE_MPSF(842000000, 285, 13, 2, 0),
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};
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struct cmucal_pll_table pll_mif_sub_rate_table[] = {
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PLL_RATE_MPSF(4265999872, 361, 13, 0, 0),
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PLL_RATE_MPSF(3080000000, 401, 10, 1, 0),
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PLL_RATE_MPSF(1690000000, 154, 7, 1, 0),
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PLL_RATE_MPSF(842000000, 285, 13, 2, 0),
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};
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struct cmucal_pll_table pll_mif_s2d_rate_table[] = {
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PLL_RATE_MPSF(400000000, 125, 12, 2, 0),
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};
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unsigned int cmucal_pll_size = 17;
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struct cmucal_pll cmucal_pll_list[] = {
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CLK_RPLL(frd_4311_rpll, PLL_AUD, FREE_OSCCLK_AUD, PLL_LOCKTIME_PLL_AUD_PLL_LOCK_TIME, PLL_CON3_PLL_AUD_ENABLE, PLL_CON3_PLL_AUD_STABLE, PLL_CON3_PLL_AUD_DIV_P, PLL_CON3_PLL_AUD_DIV_M, PLL_CON3_PLL_AUD_DIV_S, PLL_CON8_PLL_AUD_F, pll_aud_rate_table, 0, 0),
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CLK_RPLL(frd_4311_rpll, PLL_MMC, FREE_OSCCLK_CMU, PLL_LOCKTIME_PLL_MMC_PLL_LOCK_TIME, PLL_CON3_PLL_MMC_ENABLE, PLL_CON3_PLL_MMC_STABLE, PLL_CON3_PLL_MMC_DIV_P, PLL_CON3_PLL_MMC_DIV_M, PLL_CON3_PLL_MMC_DIV_S, PLL_CON8_PLL_MMC_F, pll_mmc_rate_table, 0, 0),
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CLK_RPLL(frd_4311_rpll, PLL_SHARED0, FREE_OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED0_ENABLE, PLL_CON3_PLL_SHARED0_STABLE, PLL_CON3_PLL_SHARED0_DIV_P, PLL_CON3_PLL_SHARED0_DIV_M, PLL_CON3_PLL_SHARED0_DIV_S, PLL_CON8_PLL_SHARED0_F, pll_shared0_rate_table, 0, 0),
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CLK_RPLL(frd_4311_rpll, PLL_SHARED1, FREE_OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED1_ENABLE, PLL_CON3_PLL_SHARED1_STABLE, PLL_CON3_PLL_SHARED1_DIV_P, PLL_CON3_PLL_SHARED1_DIV_M, PLL_CON3_PLL_SHARED1_DIV_S, PLL_CON8_PLL_SHARED1_F, pll_shared1_rate_table, 0, 0),
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CLK_RPLL(frd_4311_rpll, PLL_SHARED2, FREE_OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED2_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED2_ENABLE, PLL_CON3_PLL_SHARED2_STABLE, PLL_CON3_PLL_SHARED2_DIV_P, PLL_CON3_PLL_SHARED2_DIV_M, PLL_CON3_PLL_SHARED2_DIV_S, PLL_CON8_PLL_SHARED2_F, pll_shared2_rate_table, 0, 0),
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CLK_RPLL(frd_4311_rpll, PLL_SHARED3, FREE_OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED3_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED3_ENABLE, PLL_CON3_PLL_SHARED3_STABLE, PLL_CON3_PLL_SHARED3_DIV_P, PLL_CON3_PLL_SHARED3_DIV_M, PLL_CON3_PLL_SHARED3_DIV_S, PLL_CON8_PLL_SHARED3_F, pll_shared3_rate_table, 0, 0),
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CLK_RPLL(frd_4311_rpll, PLL_SHARED4, FREE_OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED4_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED4_ENABLE, PLL_CON3_PLL_SHARED4_STABLE, PLL_CON3_PLL_SHARED4_DIV_P, PLL_CON3_PLL_SHARED4_DIV_M, PLL_CON3_PLL_SHARED4_DIV_S, PLL_CON8_PLL_SHARED4_F, pll_shared4_rate_table, 0, 0),
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CLK_RPLL(frd_4311_rpll, PLL_SHARED_MIF, FREE_OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED_MIF_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED_MIF_ENABLE, PLL_CON3_PLL_SHARED_MIF_STABLE, PLL_CON3_PLL_SHARED_MIF_DIV_P, PLL_CON3_PLL_SHARED_MIF_DIV_M, PLL_CON3_PLL_SHARED_MIF_DIV_S, PLL_CON8_PLL_SHARED_MIF_F, pll_shared_mif_rate_table, 0, 0),
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CLK_RPLL(frd_4311_rpll, PLL_CPUCL0, FREE_OSCCLK_CPUCL0, PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, PLL_CON3_PLL_CPUCL0_ENABLE, PLL_CON3_PLL_CPUCL0_STABLE, PLL_CON3_PLL_CPUCL0_DIV_P, PLL_CON3_PLL_CPUCL0_DIV_M, PLL_CON3_PLL_CPUCL0_DIV_S, PLL_CON8_PLL_CPUCL0_F, pll_cpucl0_rate_table, 0, 0),
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CLK_RPLL(frd_4311_rpll, PLL_CPUCL1, FREE_OSCCLK_CPUCL1, PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, PLL_CON3_PLL_CPUCL1_ENABLE, PLL_CON3_PLL_CPUCL1_STABLE, PLL_CON3_PLL_CPUCL1_DIV_P, PLL_CON3_PLL_CPUCL1_DIV_M, PLL_CON3_PLL_CPUCL1_DIV_S, PLL_CON8_PLL_CPUCL1_F, pll_cpucl1_rate_table, 0, 0),
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CLK_RPLL(frd_4311_rpll, PLL_CPUCL2, FREE_OSCCLK_CPUCL2, PLL_LOCKTIME_PLL_CPUCL2_PLL_LOCK_TIME, PLL_CON3_PLL_CPUCL2_ENABLE, PLL_CON3_PLL_CPUCL2_STABLE, PLL_CON3_PLL_CPUCL2_DIV_P, PLL_CON3_PLL_CPUCL2_DIV_M, PLL_CON3_PLL_CPUCL2_DIV_S, PLL_CON8_PLL_CPUCL2_F, pll_cpucl2_rate_table, 0, 0),
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CLK_RPLL(frd_4311_rpll, PLL_DSU, FREE_OSCCLK_DSU, PLL_LOCKTIME_PLL_DSU_PLL_LOCK_TIME, PLL_CON3_PLL_DSU_ENABLE, PLL_CON3_PLL_DSU_STABLE, PLL_CON3_PLL_DSU_DIV_P, PLL_CON3_PLL_DSU_DIV_M, PLL_CON3_PLL_DSU_DIV_S, PLL_CON8_PLL_DSU_F, pll_dsu_rate_table, 0, 0),
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CLK_RPLL(frd_4311_rpll, PLL_G3D, FREE_OSCCLK_G3DCORE, PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, PLL_CON3_PLL_G3D_ENABLE, PLL_CON3_PLL_G3D_STABLE, PLL_CON3_PLL_G3D_DIV_P, PLL_CON3_PLL_G3D_DIV_M, PLL_CON3_PLL_G3D_DIV_S, PLL_CON8_PLL_G3D_F, pll_g3d_rate_table, 0, 0),
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CLK_RPLL(frd_4311_rpll, PLL_G3D1, FREE_OSCCLK_G3DCORE, PLL_LOCKTIME_PLL_G3D1_PLL_LOCK_TIME, PLL_CON3_PLL_G3D1_ENABLE, PLL_CON3_PLL_G3D1_STABLE, PLL_CON3_PLL_G3D1_DIV_P, PLL_CON3_PLL_G3D1_DIV_M, PLL_CON3_PLL_G3D1_DIV_S, PLL_CON8_PLL_G3D1_F, pll_g3d1_rate_table, 0, 0),
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CLK_RPLL(frd_4601_ipll, PLL_MIF_MAIN, FREE_OSCCLK_MIF, PLL_LOCKTIME_PLL_MIF_MAIN_PLL_LOCK_TIME, PLL_CON3_PLL_MIF_MAIN_ENABLE, PLL_CON3_PLL_MIF_MAIN_STABLE, PLL_CON3_PLL_MIF_MAIN_DIV_P, PLL_CON3_PLL_MIF_MAIN_DIV_M, PLL_CON3_PLL_MIF_MAIN_DIV_S, 0, pll_mif_main_rate_table, 0, 0),
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CLK_RPLL(frd_4601_ipll, PLL_MIF_SUB, FREE_OSCCLK_MIF, PLL_LOCKTIME_PLL_MIF_SUB_PLL_LOCK_TIME, PLL_CON3_PLL_MIF_SUB_ENABLE, PLL_CON3_PLL_MIF_SUB_STABLE, PLL_CON3_PLL_MIF_SUB_DIV_P, PLL_CON3_PLL_MIF_SUB_DIV_M, PLL_CON3_PLL_MIF_SUB_DIV_S, 0, pll_mif_sub_rate_table, 0, 0),
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CLK_RPLL(frd_4601_ipll, PLL_MIF_S2D, OSCCLK_S2D, PLL_LOCKTIME_PLL_MIF_S2D_PLL_LOCK_TIME, PLL_CON3_PLL_MIF_S2D_ENABLE, PLL_CON3_PLL_MIF_S2D_STABLE, PLL_CON3_PLL_MIF_S2D_DIV_P, PLL_CON3_PLL_MIF_S2D_DIV_M, PLL_CON3_PLL_MIF_S2D_DIV_S, 0, pll_mif_s2d_rate_table, 0, 0),
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};
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enum clk_id cmucal_mux_clkalive_ufd_noc_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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RCO_400,
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MUX_CLKCMU_ALIVE_NOC_USER,
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OSCCLK_RCO_ALIVE,
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};
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enum clk_id cmucal_mux_clkalive_cmgp_noc_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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RCO_400,
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MUX_CLKCMU_ALIVE_NOC_USER,
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OSCCLK_RCO_ALIVE,
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};
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enum clk_id cmucal_mux_clk_alive_noc_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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RCO_400,
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MUX_CLKCMU_ALIVE_NOC_USER,
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OSCCLK_RCO_ALIVE,
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};
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enum clk_id cmucal_mux_clkalive_cmgp_peri_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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RCO_400,
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MUX_CLKCMU_ALIVE_NOC_USER,
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OSCCLK_RCO_ALIVE,
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};
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enum clk_id cmucal_mux_clkalive_chub_peri_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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RCO_400,
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MUX_CLKCMU_ALIVE_NOC_USER,
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OSCCLK_RCO_ALIVE,
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};
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enum clk_id cmucal_mux_clkalive_dbgcore_noc_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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RCO_400,
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MUX_CLKCMU_ALIVE_NOC_USER,
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OSCCLK_RCO_ALIVE,
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};
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enum clk_id cmucal_mux_clkalive_dnc_noc_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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RCO_400,
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MUX_CLKCMU_ALIVE_NOC_USER,
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OSCCLK_RCO_ALIVE,
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};
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enum clk_id cmucal_mux_clk_alive_timer_parents[] = {
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OSCCLK_RCO_ALIVE,
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FREE_OSCCLK_ALIVE,
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};
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enum clk_id cmucal_mux_clk_alive_spmi_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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RCO_400,
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MUX_CLKCMU_ALIVE_NOC_USER,
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MUX_CLKMUX_ALIVE_RCO_SPMI_USER,
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};
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enum clk_id cmucal_mux_clk_alive_dbgcore_uart_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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RCO_400,
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MUX_CLKCMU_ALIVE_NOC_USER,
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OSCCLK_RCO_ALIVE,
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};
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enum clk_id cmucal_mux_clkalive_gnpu_noc_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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RCO_400,
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MUX_CLKCMU_ALIVE_NOC_USER,
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OSCCLK_RCO_ALIVE,
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};
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enum clk_id cmucal_mux_clkalive_gnss_noc_parents[] = {
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RCO_400,
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MUX_CLKCMU_ALIVE_NOC_USER,
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};
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enum clk_id cmucal_mux_clkalive_sdma_noc_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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RCO_400,
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MUX_CLKCMU_ALIVE_NOC_USER,
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OSCCLK_RCO_ALIVE,
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};
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enum clk_id cmucal_mux_clk_alive_pmu_sub_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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RCO_400,
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MUX_CLKCMU_ALIVE_NOC_USER,
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OSCCLK_RCO_ALIVE,
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};
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enum clk_id cmucal_mux_clkalive_chubvts_noc_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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RCO_400,
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MUX_CLKCMU_ALIVE_NOC_USER,
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OSCCLK_RCO_ALIVE,
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};
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enum clk_id cmucal_mux_clkalive_csis_noc_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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RCO_400,
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MUX_CLKCMU_ALIVE_NOC_USER,
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OSCCLK_RCO_ALIVE,
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};
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enum clk_id cmucal_mux_clkalive_dsp_noc_parents[] = {
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MUX_CLK_RCO_ALIVE_USER,
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RCO_400,
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MUX_CLKCMU_ALIVE_NOC_USER,
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OSCCLK_RCO_ALIVE,
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};
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enum clk_id cmucal_mux_clk_aud_uaif3_parents[] = {
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FREE_OSCCLK_AUD,
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MUX_CLKCMU_AUD_AUDIF0_USER,
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PLL_AUD_D1,
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DIV_CLK_AUD_AUDIF,
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IOCLK_AUDIOCDCLK3,
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FREE_OSCCLK_AUD,
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FREE_OSCCLK_AUD,
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FREE_OSCCLK_AUD,
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};
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enum clk_id cmucal_mux_clk_aud_uaif2_parents[] = {
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FREE_OSCCLK_AUD,
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MUX_CLKCMU_AUD_AUDIF0_USER,
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MUX_CLKCMU_AUD_AUDIF1_USER,
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DIV_CLK_AUD_AUDIF,
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IOCLK_AUDIOCDCLK2,
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FREE_OSCCLK_AUD,
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FREE_OSCCLK_AUD,
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FREE_OSCCLK_AUD,
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};
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enum clk_id cmucal_mux_clk_aud_uaif1_parents[] = {
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FREE_OSCCLK_AUD,
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MUX_CLKCMU_AUD_AUDIF0_USER,
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MUX_CLKCMU_AUD_AUDIF1_USER,
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DIV_CLK_AUD_AUDIF,
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IOCLK_AUDIOCDCLK1,
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FREE_OSCCLK_AUD,
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FREE_OSCCLK_AUD,
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FREE_OSCCLK_AUD,
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};
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enum clk_id cmucal_mux_clk_aud_uaif0_parents[] = {
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FREE_OSCCLK_AUD,
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MUX_CLKCMU_AUD_AUDIF0_USER,
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MUX_CLKCMU_AUD_AUDIF1_USER,
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DIV_CLK_AUD_AUDIF,
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IOCLK_AUDIOCDCLK0,
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FREE_OSCCLK_AUD,
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FREE_OSCCLK_AUD,
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FREE_OSCCLK_AUD,
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};
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enum clk_id cmucal_mux_clk_aud_cpu_parents[] = {
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PLL_AUD_D1,
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MUX_CLKCMU_AUD_CPU_USER,
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MUX_CLK_AUD_RCO_USER,
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FREE_OSCCLK_AUD,
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};
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enum clk_id cmucal_mux_clk_aud_dsif_parents[] = {
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FREE_OSCCLK_AUD,
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MUX_CLKCMU_AUD_AUDIF0_USER,
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MUX_CLKCMU_AUD_AUDIF1_USER,
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DIV_CLK_AUD_AUDIF,
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CLKIO_AUD_DSIF,
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FREE_OSCCLK_AUD,
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FREE_OSCCLK_AUD,
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FREE_OSCCLK_AUD,
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};
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enum clk_id cmucal_mux_clk_aud_uaif4_parents[] = {
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FREE_OSCCLK_AUD,
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MUX_CLKCMU_AUD_AUDIF0_USER,
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MUX_CLKCMU_AUD_AUDIF1_USER,
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DIV_CLK_AUD_AUDIF,
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FREE_OSCCLK_AUD,
|
|
FREE_OSCCLK_AUD,
|
|
FREE_OSCCLK_AUD,
|
|
FREE_OSCCLK_AUD,
|
|
};
|
|
enum clk_id cmucal_mux_clk_aud_uaif5_parents[] = {
|
|
FREE_OSCCLK_AUD,
|
|
MUX_CLKCMU_AUD_AUDIF0_USER,
|
|
MUX_CLKCMU_AUD_AUDIF1_USER,
|
|
DIV_CLK_AUD_AUDIF,
|
|
FREE_OSCCLK_AUD,
|
|
FREE_OSCCLK_AUD,
|
|
FREE_OSCCLK_AUD,
|
|
FREE_OSCCLK_AUD,
|
|
};
|
|
enum clk_id cmucal_mux_clk_aud_uaif6_parents[] = {
|
|
FREE_OSCCLK_AUD,
|
|
MUX_CLKCMU_AUD_AUDIF0_USER,
|
|
MUX_CLKCMU_AUD_AUDIF1_USER,
|
|
DIV_CLK_AUD_AUDIF,
|
|
IOCLK_AUDIOCDCLK6,
|
|
FREE_OSCCLK_AUD,
|
|
FREE_OSCCLK_AUD,
|
|
FREE_OSCCLK_AUD,
|
|
};
|
|
enum clk_id cmucal_mux_clk_aud_noc_parents[] = {
|
|
PLL_AUD_D1,
|
|
MUX_CLKCMU_AUD_NOC_USER,
|
|
MUX_CLKCMU_AUD_CPU_USER,
|
|
MUX_CLK_AUD_RCO_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_aud_pcmc_parents[] = {
|
|
MUX_CP_PCMC_CLK_USER,
|
|
MUX_CLK_AUD_SCLK,
|
|
};
|
|
enum clk_id cmucal_mux_clk_aud_audif_parents[] = {
|
|
PLL_AUD_D1,
|
|
MUX_CLK_AUD_RCO_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_aud_sclk_parents[] = {
|
|
FREE_OSCCLK_AUD,
|
|
MUX_CLKCMU_AUD_AUDIF0_USER,
|
|
DIV_CLK_AUD_AUDIF,
|
|
MUX_CLK_AUD_RCO_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_aud_serial_lif_parents[] = {
|
|
MUX_CLK_AUD_RCO_USER,
|
|
MUX_CLKCMU_AUD_AUDIF0_USER,
|
|
MUX_CLKCMU_AUD_AUDIF1_USER,
|
|
FREE_OSCCLK_AUD,
|
|
};
|
|
enum clk_id cmucal_mux_clk_aud_serial_lif_core_parents[] = {
|
|
MUX_CLK_AUD_RCO_USER,
|
|
DIV_CLK_AUD_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_chub_timer_parents[] = {
|
|
FREE_OSCCLK_CHUB,
|
|
RTCCLK_CHUB,
|
|
};
|
|
enum clk_id cmucal_mux_clk_chub_usi0_parents[] = {
|
|
MUX_CLKALIVE_CHUB_RCO_USER,
|
|
MUX_CLKALIVE_CHUB_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_chub_usi1_parents[] = {
|
|
MUX_CLKALIVE_CHUB_RCO_USER,
|
|
MUX_CLKALIVE_CHUB_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_chub_usi3_parents[] = {
|
|
MUX_CLKALIVE_CHUB_RCO_USER,
|
|
MUX_CLKALIVE_CHUB_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_chub_i2c_parents[] = {
|
|
MUX_CLKALIVE_CHUB_RCO_USER,
|
|
MUX_CLKALIVE_CHUB_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_chub_usi2_parents[] = {
|
|
MUX_CLKALIVE_CHUB_RCO_USER,
|
|
MUX_CLKALIVE_CHUB_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_chub_spi_ms_ctrl_parents[] = {
|
|
MUX_CLKALIVE_CHUB_RCO_USER,
|
|
MUX_CLKALIVE_CHUB_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_chub_spi_i2c0_parents[] = {
|
|
MUX_CLKALIVE_CHUB_RCO_USER,
|
|
MUX_CLKALIVE_CHUB_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_chub_spi_i2c1_parents[] = {
|
|
MUX_CLKALIVE_CHUB_RCO_USER,
|
|
MUX_CLKALIVE_CHUB_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_chub_noc_parents[] = {
|
|
MUX_CLKALIVE_CHUB_NOC_USER,
|
|
MUX_CLKALIVE_CHUB_RCO_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_chubvts_dmailbox_cclk_parents[] = {
|
|
MUX_CLKALIVE_CHUBVTS_NOC_USER,
|
|
MUX_CLKALIVE_CHUBVTS_RCO_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_chubvts_noc_parents[] = {
|
|
MUX_CLKALIVE_CHUBVTS_NOC_USER,
|
|
MUX_CLKALIVE_CHUBVTS_RCO_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_usi4_parents[] = {
|
|
OSCCLK_CMGP,
|
|
MUX_CLKALIVE_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_usi0_parents[] = {
|
|
OSCCLK_CMGP,
|
|
MUX_CLKALIVE_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_usi1_parents[] = {
|
|
OSCCLK_CMGP,
|
|
MUX_CLKALIVE_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_usi2_parents[] = {
|
|
OSCCLK_CMGP,
|
|
MUX_CLKALIVE_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_usi3_parents[] = {
|
|
OSCCLK_CMGP,
|
|
MUX_CLKALIVE_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_usi5_parents[] = {
|
|
OSCCLK_CMGP,
|
|
MUX_CLKALIVE_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_usi6_parents[] = {
|
|
OSCCLK_CMGP,
|
|
MUX_CLKALIVE_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_i2c_parents[] = {
|
|
OSCCLK_CMGP,
|
|
MUX_CLKALIVE_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_spi_ms_ctrl_parents[] = {
|
|
OSCCLK_CMGP,
|
|
MUX_CLKALIVE_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_spi_i2c0_parents[] = {
|
|
OSCCLK_CMGP,
|
|
MUX_CLKALIVE_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cmgp_spi_i2c1_parents[] = {
|
|
OSCCLK_CMGP,
|
|
MUX_CLKALIVE_CMGP_PERI_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi0_dposc_parents[] = {
|
|
FREE_OSCCLK_CMU,
|
|
PLL_SHARED2_D1,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mfc0_mfc0_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dsp_noc_parents[] = {
|
|
PLL_SHARED0_D1,
|
|
PLL_SHARED1_D1,
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl0_switch_parents[] = {
|
|
PLL_SHARED0_D1,
|
|
PLL_SHARED1_D1,
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
FREE_OSCCLK_CMU,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_nocl0_noc_parents[] = {
|
|
PLL_SHARED0_D1,
|
|
PLL_SHARED1_D1,
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
MUX_CP_MPLL_CLK_D2_USER,
|
|
PLL_SHARED_MIF_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mif_switch_parents[] = {
|
|
PLL_SHARED0_D1,
|
|
PLL_SHARED1_D1,
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
MUX_CP_MPLL_CLK_USER,
|
|
PLL_SHARED_MIF_D1,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_brp_noc_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_yuvp_noc_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_aud_cpu_parents[] = {
|
|
PLL_SHARED0_D1,
|
|
PLL_SHARED1_D1,
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
MUX_CP_MPLL_CLK_D2_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl0_dbg_noc_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cis_clk0_parents[] = {
|
|
FREE_OSCCLK_CMU,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cis_clk1_parents[] = {
|
|
FREE_OSCCLK_CMU,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cis_clk2_parents[] = {
|
|
FREE_OSCCLK_CMU,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cis_clk3_parents[] = {
|
|
FREE_OSCCLK_CMU,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_cmu_cmuref_parents[] = {
|
|
OSCCLK_CMU,
|
|
CLKCMU_CMU_BOOST,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric0_noc_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric1_noc_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peris_noc_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi1_pcie_parents[] = {
|
|
FREE_OSCCLK_CMU,
|
|
PLL_SHARED2_D1,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_gnpu_noc_parents[] = {
|
|
PLL_SHARED0_D1,
|
|
PLL_SHARED1_D1,
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_alive_noc_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi1_noc_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mfc0_wfd_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
PLL_SHARED4_D2,
|
|
FREE_OSCCLK_CMU,
|
|
FREE_OSCCLK_CMU,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mif_nocp_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric0_ip0_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric1_ip0_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_clkcmu_dpuf_noc_parents[] = {
|
|
DIV_CLKCMU_DPUF,
|
|
DIV_CLKCMU_DPUF_ALT,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpuf_alt_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
FREE_OSCCLK_CMU,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl1_switch_parents[] = {
|
|
PLL_SHARED0_D1,
|
|
PLL_SHARED1_D1,
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
FREE_OSCCLK_CMU,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi0_noc_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cmu_boost_mif_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cis_clk4_parents[] = {
|
|
FREE_OSCCLK_CMU,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpuf_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
FREE_OSCCLK_CMU,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cmu_boost_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_csis_noc_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mcsc_noc_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_csis_ois_mcu_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cis_clk5_parents[] = {
|
|
FREE_OSCCLK_CMU,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cmu_boost_cpu_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_m2m_noc_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpub_alt_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
FREE_OSCCLK_CMU,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_clkcmu_dpub_noc_parents[] = {
|
|
DIV_CLKCMU_DPUB,
|
|
DIV_CLKCMU_DPUB_ALT,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpub_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
FREE_OSCCLK_CMU,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mfc1_mfc1_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_lme_noc_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi0_usb32drd_parents[] = {
|
|
FREE_OSCCLK_CMU,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi0_dpgtc_parents[] = {
|
|
FREE_OSCCLK_CMU,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_aud_noc_parents[] = {
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
MUX_CP_MPLL_CLK_D2_USER,
|
|
FREE_OSCCLK_CMU,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_csis_dcphy_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_cp_hispeedy_clk_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric0_ip1_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric1_ip1_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_ssp_noc_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_g3d_switch_parents[] = {
|
|
PLL_SHARED0_D1,
|
|
PLL_SHARED1_D1,
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric2_ip0_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric2_noc_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric2_ip1_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl0_nocp_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dsu_switch_parents[] = {
|
|
PLL_SHARED0_D1,
|
|
PLL_SHARED1_D1,
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
FREE_OSCCLK_CMU,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_g3d_nocp_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cstat_noc_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpub_dsim_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dnc_noc_parents[] = {
|
|
PLL_SHARED0_D1,
|
|
PLL_SHARED1_D1,
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl2_switch_parents[] = {
|
|
PLL_SHARED0_D1,
|
|
PLL_SHARED1_D1,
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
FREE_OSCCLK_CMU,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_sdma_noc_parents[] = {
|
|
PLL_SHARED0_D1,
|
|
PLL_SHARED1_D1,
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cis_clk6_parents[] = {
|
|
FREE_OSCCLK_CMU,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_nocl1c_noc_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_cp_shared0_clk_parents[] = {
|
|
PLL_SHARED0_D1,
|
|
PLL_SHARED1_D1,
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
};
|
|
enum clk_id cmucal_mux_cp_shared1_clk_parents[] = {
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_cp_shared2_clk_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED1_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cmu_boost_cam_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_vts_dmic_parents[] = {
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_aud_audif0_parents[] = {
|
|
PLL_SHARED0_D1,
|
|
PLL_SHARED1_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
MUX_CP_MPLL_CLK_D2_USER,
|
|
FREE_OSCCLK_CMU,
|
|
FREE_OSCCLK_CMU,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_aud_audif1_parents[] = {
|
|
PLL_SHARED0_D1,
|
|
PLL_SHARED1_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
MUX_CP_MPLL_CLK_D2_USER,
|
|
FREE_OSCCLK_CMU,
|
|
FREE_OSCCLK_CMU,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peris_gic_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cis_clk7_parents[] = {
|
|
FREE_OSCCLK_CMU,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_nocl1b_noc0_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_nocl1a_noc_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_nocl1b_noc1_parents[] = {
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_lme_lme_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_m2m_frc_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mcsc_mcsc_parents[] = {
|
|
PLL_SHARED2_D1,
|
|
PLL_SHARED3_D1,
|
|
PLL_SHARED4_D1,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED3_D2,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_ufs_ufs_embd_parents[] = {
|
|
FREE_OSCCLK_CMU,
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_ufs_noc_parents[] = {
|
|
PLL_SHARED0_D2,
|
|
PLL_SHARED1_D2,
|
|
PLL_SHARED2_D2,
|
|
PLL_SHARED4_D2,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_ufs_mmc_card_parents[] = {
|
|
FREE_OSCCLK_CMU,
|
|
PLL_SHARED2_D1,
|
|
PLL_MMC_D1,
|
|
PLL_SHARED0_D2,
|
|
};
|
|
enum clk_id cmucal_clkcmu_aud_cpu_parents[] = {
|
|
DIV_CLKCMU_AUD_CPU_SM,
|
|
DIV_CLKCMU_AUD_CPU,
|
|
};
|
|
enum clk_id cmucal_clkcmu_aud_audif0_parents[] = {
|
|
DIV_CLKCMU_AUD_AUDIF0_SM,
|
|
DIV_CLKCMU_AUD_AUDIF0,
|
|
};
|
|
enum clk_id cmucal_clkcmu_aud_audif1_parents[] = {
|
|
DIV_CLKCMU_AUD_AUDIF1_SM,
|
|
DIV_CLKCMU_AUD_AUDIF1,
|
|
};
|
|
enum clk_id cmucal_clkcmu_cpucl0_switch_parents[] = {
|
|
DIV_CLKCMU_CPUCL0_SWITCH_SM,
|
|
DIV_CLKCMU_CPUCL0_SWITCH,
|
|
};
|
|
enum clk_id cmucal_clkcmu_cpucl1_switch_parents[] = {
|
|
DIV_CLKCMU_CPUCL1_SWITCH_SM,
|
|
DIV_CLKCMU_CPUCL1_SWITCH,
|
|
};
|
|
enum clk_id cmucal_clkcmu_cpucl2_switch_parents[] = {
|
|
DIV_CLKCMU_CPUCL2_SWITCH_SM,
|
|
DIV_CLKCMU_CPUCL2_SWITCH,
|
|
};
|
|
enum clk_id cmucal_clkcmu_dsu_switch_parents[] = {
|
|
DIV_CLKCMU_DSU_SWITCH_SM,
|
|
DIV_CLKCMU_DSU_SWITCH,
|
|
};
|
|
enum clk_id cmucal_clkcmu_cpucl0_dbg_noc_parents[] = {
|
|
DIV_CLKCMU_CPUCL0_DBG_NOC_SM,
|
|
DIV_CLKCMU_CPUCL0_DBG_NOC,
|
|
};
|
|
enum clk_id cmucal_clkcmu_dnc_noc_parents[] = {
|
|
DIV_CLKCMU_DNC_NOC_SM,
|
|
DIV_CLKCMU_DNC_NOC,
|
|
};
|
|
enum clk_id cmucal_clkcmu_sdma_noc_parents[] = {
|
|
DIV_CLKCMU_SDMA_NOC_SM,
|
|
DIV_CLKCMU_SDMA_NOC,
|
|
};
|
|
enum clk_id cmucal_clkcmu_dsp_noc_parents[] = {
|
|
DIV_CLKCMU_DSP_NOC_SM,
|
|
DIV_CLKCMU_DSP_NOC,
|
|
PLL_SHARED_MIF_D1,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_clkcmu_g3d_switch_parents[] = {
|
|
DIV_CLKCMU_G3D_SWITCH_SM,
|
|
DIV_CLKCMU_G3D_SWITCH,
|
|
};
|
|
enum clk_id cmucal_clkcmu_gnpu_noc_parents[] = {
|
|
DIV_CLKCMU_GNPU_NOC_SM,
|
|
DIV_CLKCMU_GNPU_NOC,
|
|
PLL_SHARED_MIF_D1,
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_clkcmu_m2m_noc_parents[] = {
|
|
DIV_CLKCMU_M2M_NOC_SM,
|
|
DIV_CLKCMU_M2M_NOC,
|
|
};
|
|
enum clk_id cmucal_clkcmu_m2m_frc_parents[] = {
|
|
DIV_CLKCMU_M2M_FRC_SM,
|
|
DIV_CLKCMU_M2M_FRC,
|
|
};
|
|
enum clk_id cmucal_clkcmu_mcsc_noc_parents[] = {
|
|
DIV_CLKCMU_MCSC_NOC_SM,
|
|
DIV_CLKCMU_MCSC_NOC,
|
|
};
|
|
enum clk_id cmucal_clkcmu_mcsc_mcsc_parents[] = {
|
|
DIV_CLKCMU_MCSC_MCSC_SM,
|
|
DIV_CLKCMU_MCSC_MCSC,
|
|
};
|
|
enum clk_id cmucal_clkcmu_nocl0_noc_parents[] = {
|
|
DIV_CLKCMU_NOCL0_NOC_SM,
|
|
DIV_CLKCMU_NOCL0_NOC,
|
|
};
|
|
enum clk_id cmucal_clkcmu_nocl1a_noc_parents[] = {
|
|
DIV_CLKCMU_NOCL1A_NOC_SM,
|
|
DIV_CLKCMU_NOCL1A_NOC,
|
|
};
|
|
enum clk_id cmucal_clkcmu_nocl1b_noc0_parents[] = {
|
|
DIV_CLKCMU_NOCL1B_NOC0_SM,
|
|
DIV_CLKCMU_NOCL1B_NOC0,
|
|
};
|
|
enum clk_id cmucal_clkcmu_nocl1c_noc_parents[] = {
|
|
DIV_CLKCMU_NOCL1C_NOC_SM,
|
|
DIV_CLKCMU_NOCL1C_NOC,
|
|
};
|
|
enum clk_id cmucal_cp_shared0_clk_parents[] = {
|
|
DIV_CP_SHARED0_CLK_SM,
|
|
DIV_CP_SHARED0_CLK,
|
|
};
|
|
enum clk_id cmucal_cp_shared2_clk_parents[] = {
|
|
DIV_CP_SHARED2_CLK_SM,
|
|
DIV_CP_SHARED2_CLK,
|
|
};
|
|
enum clk_id cmucal_cp_hispeedy_clk_parents[] = {
|
|
DIV_CP_HISPEEDY_CLK_SM,
|
|
DIV_CP_HISPEEDY_CLK,
|
|
};
|
|
enum clk_id cmucal_clkcmu_ufs_mmc_card_parents[] = {
|
|
DIV_CLKCMU_UFS_MMC_CARD_SM,
|
|
DIV_CLKCMU_UFS_MMC_CARD,
|
|
};
|
|
enum clk_id cmucal_mux_cpucl0_cmuref_parents[] = {
|
|
OSCCLK_CPUCL0,
|
|
CLKCMU_CMU_BOOST_CPU,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl0_idleclkdown_parents[] = {
|
|
MUX_CLK_CPUCL0_STRMUX,
|
|
MUX_CLKCMU_CPUCL0_SWITCH_USER,
|
|
FREE_OSCCLK_CPUCL0,
|
|
PLL_DSU_D1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl0_delaymux_parents[] = {
|
|
CPUCL0_CPM,
|
|
MUX_CLK_CPUCL0_DELAYCHAIN,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl0_delaychain_parents[] = {
|
|
CPUCL0_CPM,
|
|
CPUCL0_CPM,
|
|
CPUCL0_CPM,
|
|
CPUCL0_CPM,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl0_powerip_parents[] = {
|
|
PLL_CPUCL0_D1,
|
|
MUX_CLKCMU_CPUCL0_SWITCH_USER,
|
|
FREE_OSCCLK_CPUCL0,
|
|
PLL_DSU_D1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl0_ddd_parents[] = {
|
|
MUX_CLK_CPUCL0_IDLECLKDOWN,
|
|
CPUCL0_CPM,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl0_htu_parents[] = {
|
|
PLL_CPUCL0_D4,
|
|
MUX_CLKCMU_CPUCL0_SWITCH_USER,
|
|
FREE_OSCCLK_CPUCL0,
|
|
PLL_DSU_D4,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_idleclkdown_0_parents[] = {
|
|
MUX_CLK_CPUCL1_STRMUX_0,
|
|
MUX_CLKCMU_CPUCL1_SWITCH_USER,
|
|
FREE_OSCCLK_CPUCL1,
|
|
FREE_OSCCLK_CPUCL1,
|
|
};
|
|
enum clk_id cmucal_mux_cpucl1_cmuref_parents[] = {
|
|
OSCCLK_CPUCL1,
|
|
CLKCMU_CMU_BOOST_CPU,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_delaychain_0_parents[] = {
|
|
CPUCL1_CPM0,
|
|
CPUCL1_CPM0,
|
|
CPUCL1_CPM0,
|
|
CPUCL1_CPM0,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_delaymux_0_parents[] = {
|
|
CPUCL1_CPM0,
|
|
MUX_CLK_CPUCL1_DELAYCHAIN_0,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_powerip_parents[] = {
|
|
PLL_CPUCL1_D1,
|
|
MUX_CLKCMU_CPUCL1_SWITCH_USER,
|
|
FREE_OSCCLK_CPUCL1,
|
|
FREE_OSCCLK_CPUCL1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_ddd_0_parents[] = {
|
|
MUX_CLK_CPUCL1_IDLECLKDOWN_0,
|
|
CPUCL1_CPM0,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_idleclkdown_1_parents[] = {
|
|
MUX_CLK_CPUCL1_STRMUX_1,
|
|
MUX_CLKCMU_CPUCL1_SWITCH_USER,
|
|
FREE_OSCCLK_CPUCL1,
|
|
FREE_OSCCLK_CPUCL1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_delaymux_1_parents[] = {
|
|
CPUCL1_CPM1,
|
|
MUX_CLK_CPUCL1_DELAYCHAIN_1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_ddd_1_parents[] = {
|
|
MUX_CLK_CPUCL1_IDLECLKDOWN_1,
|
|
CPUCL1_CPM1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_delaychain_1_parents[] = {
|
|
CPUCL1_CPM1,
|
|
CPUCL1_CPM1,
|
|
CPUCL1_CPM1,
|
|
CPUCL1_CPM1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_idleclkdown_2_parents[] = {
|
|
MUX_CLK_CPUCL1_STRMUX_2,
|
|
MUX_CLKCMU_CPUCL1_SWITCH_USER,
|
|
FREE_OSCCLK_CPUCL1,
|
|
FREE_OSCCLK_CPUCL1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_delaymux_2_parents[] = {
|
|
CPUCL1_CPM2,
|
|
MUX_CLK_CPUCL1_DELAYCHAIN_2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_ddd_2_parents[] = {
|
|
MUX_CLK_CPUCL1_IDLECLKDOWN_2,
|
|
CPUCL1_CPM2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_delaychain_2_parents[] = {
|
|
CPUCL1_CPM2,
|
|
CPUCL1_CPM2,
|
|
CPUCL1_CPM2,
|
|
CPUCL1_CPM2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_htu_parents[] = {
|
|
PLL_CPUCL1_D4,
|
|
MUX_CLKCMU_CPUCL1_SWITCH_USER,
|
|
FREE_OSCCLK_CPUCL1,
|
|
FREE_OSCCLK_CPUCL1,
|
|
};
|
|
enum clk_id cmucal_mux_cpucl2_cmuref_parents[] = {
|
|
OSCCLK_CPUCL2,
|
|
CLKCMU_CMU_BOOST_CPU,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl2_idleclkdown_parents[] = {
|
|
MUX_CLK_CPUCL2_STRMUX,
|
|
MUX_CLKCMU_CPUCL2_SWITCH_USER,
|
|
FREE_OSCCLK_CPUCL2,
|
|
FREE_OSCCLK_CPUCL2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl2_delaychain_parents[] = {
|
|
CPUCL2_CPM,
|
|
CPUCL2_CPM,
|
|
CPUCL2_CPM,
|
|
CPUCL2_CPM,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl2_delaymux_parents[] = {
|
|
CPUCL2_CPM,
|
|
MUX_CLK_CPUCL2_DELAYCHAIN,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl2_powerip_parents[] = {
|
|
PLL_CPUCL2_D1,
|
|
MUX_CLKCMU_CPUCL2_SWITCH_USER,
|
|
FREE_OSCCLK_CPUCL2,
|
|
FREE_OSCCLK_CPUCL2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl2_ddd_parents[] = {
|
|
MUX_CLK_CPUCL2_IDLECLKDOWN,
|
|
CPUCL2_CPM,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl2_htu_parents[] = {
|
|
PLL_CPUCL2_D4,
|
|
MUX_CLKCMU_CPUCL2_SWITCH_USER,
|
|
FREE_OSCCLK_CPUCL2,
|
|
FREE_OSCCLK_CPUCL2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_csis_noc_parents[] = {
|
|
MUX_CLKCMU_CSIS_NOC_USER,
|
|
MUX_CLKALIVE_CSIS_NOC_USER,
|
|
MUX_CLKALIVE_CSIS_RCO_USER,
|
|
FREE_OSCCLK_CSIS,
|
|
};
|
|
enum clk_id cmucal_mux_clk_csis_dcphy_parents[] = {
|
|
MUX_CLKCMU_CSIS_DCPHY_USER,
|
|
MUX_CLKALIVE_CSIS_NOC_USER,
|
|
MUX_CLKALIVE_CSIS_RCO_USER,
|
|
FREE_OSCCLK_CSIS,
|
|
};
|
|
enum clk_id cmucal_mux_clk_dnc_noc_parents[] = {
|
|
MUX_CLKCMU_DNC_NOC_USER,
|
|
MUX_CLKALIVE_DNC_NOC_USER,
|
|
MUX_CLKALIVE_DNC_RCO_USER,
|
|
FREE_OSCCLK_DNC,
|
|
};
|
|
enum clk_id cmucal_mux_clk_dsp_noc_parents[] = {
|
|
MUX_CLKCMU_DSP_NOC_USER,
|
|
MUX_CLKALIVE_SDMA_NOC_USER_CPY,
|
|
MUX_CLKALIVE_SDMA_RCO_USER_CPY,
|
|
FREE_OSCCLK_DSP,
|
|
};
|
|
enum clk_id cmucal_mux_clk_dsu_idleclkdown_parents[] = {
|
|
MUX_CLK_DSU_STRMUX,
|
|
MUX_CLKCMU_DSU_SWITCH_USER,
|
|
FREE_OSCCLK_DSU,
|
|
FREE_OSCCLK_DSU,
|
|
};
|
|
enum clk_id cmucal_mux_dsu_cmuref_parents[] = {
|
|
OSCCLK_DSU,
|
|
CLKCMU_CMU_BOOST_CPU,
|
|
};
|
|
enum clk_id cmucal_mux_clk_dsu_delaychain_parents[] = {
|
|
DSU_CPM,
|
|
DSU_CPM,
|
|
DSU_CPM,
|
|
DSU_CPM,
|
|
};
|
|
enum clk_id cmucal_mux_clk_dsu_delaymux_parents[] = {
|
|
DSU_CPM,
|
|
MUX_CLK_DSU_DELAYCHAIN,
|
|
};
|
|
enum clk_id cmucal_mux_clk_dsu_powerip_parents[] = {
|
|
PLL_DSU_D1,
|
|
MUX_CLKCMU_DSU_SWITCH_USER,
|
|
FREE_OSCCLK_DSU,
|
|
FREE_OSCCLK_DSU,
|
|
};
|
|
enum clk_id cmucal_mux_clk_dsu_ddd_parents[] = {
|
|
MUX_CLK_DSU_IDLECLKDOWN,
|
|
DSU_CPM,
|
|
};
|
|
enum clk_id cmucal_mux_clk_dsu_htu_parents[] = {
|
|
PLL_DSU_D4,
|
|
MUX_CLKCMU_DSU_SWITCH_USER,
|
|
FREE_OSCCLK_DSU,
|
|
FREE_OSCCLK_DSU,
|
|
};
|
|
enum clk_id cmucal_mux_clk_g3d_core_parents[] = {
|
|
MUX_CLK_G3D_STRMUX,
|
|
MUX_CLKCMU_G3D_SWITCH_USER,
|
|
FREE_OSCCLK_G3DCORE,
|
|
FREE_OSCCLK_G3DCORE,
|
|
};
|
|
enum clk_id cmucal_mux_clk_g3d_ddd_parents[] = {
|
|
MUX_CLK_G3D_CORE,
|
|
G3DCORE_CPM,
|
|
};
|
|
enum clk_id cmucal_mux_clk_g3d_delaychain_parents[] = {
|
|
G3DCORE_CPM,
|
|
G3DCORE_CPM,
|
|
G3DCORE_CPM,
|
|
G3DCORE_CPM,
|
|
};
|
|
enum clk_id cmucal_mux_clk_g3d_delaymux_parents[] = {
|
|
G3DCORE_CPM,
|
|
MUX_CLK_G3D_DELAYCHAIN,
|
|
};
|
|
enum clk_id cmucal_mux_clk_g3d_pll_parents[] = {
|
|
PLL_G3D_D1,
|
|
PLL_G3D1_D1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_gnpu_noc_parents[] = {
|
|
MUX_CLKCMU_GNPU_NOC_USER,
|
|
MUX_CLKALIVE_GNPU_NOC_USER,
|
|
MUX_CLKALIVE_GNPU_RCO_USER,
|
|
FREE_OSCCLK_GNPU,
|
|
};
|
|
enum clk_id cmucal_mux_clk_hsi0_usb32drd_parents[] = {
|
|
OSCCLK_19_2,
|
|
MUX_CLKCMU_HSI0_USB32DRD_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_hsi0_noc_parents[] = {
|
|
MUX_CLKCMU_HSI0_NOC_USER,
|
|
MUX_CLKAUD_HSI0_NOC_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_hsi0_rtcclk_parents[] = {
|
|
RTCCLK_HSI0,
|
|
OSCCLK_HSI0,
|
|
};
|
|
enum clk_id cmucal_mux_mif_cmuref_parents[] = {
|
|
OSCCLK_MIF,
|
|
CLKCMU_CMU_BOOST_MIF,
|
|
};
|
|
enum clk_id cmucal_mux_nocl0_cmuref_parents[] = {
|
|
OSCCLK_NOCL0,
|
|
CLKCMU_CMU_BOOST,
|
|
};
|
|
enum clk_id cmucal_mux_nocl1a_cmuref_parents[] = {
|
|
OSCCLK_NOCL1A,
|
|
CLKCMU_CMU_BOOST,
|
|
};
|
|
enum clk_id cmucal_mux_nocl1b_cmuref_parents[] = {
|
|
OSCCLK_NOCL1B,
|
|
CLKCMU_CMU_BOOST,
|
|
};
|
|
enum clk_id cmucal_mux_nocl1c_cmuref_parents[] = {
|
|
OSCCLK_NOCL1C,
|
|
CLKCMU_CMU_BOOST_CAM,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric0_usi04_parents[] = {
|
|
FREE_OSCCLK_PERIC0,
|
|
MUX_CLKCMU_PERIC0_IP0_USER,
|
|
MUX_CLKCMU_PERIC0_IP1_USER,
|
|
FREE_OSCCLK_PERIC0,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric0_i2c_parents[] = {
|
|
FREE_OSCCLK_PERIC0,
|
|
MUX_CLKCMU_PERIC0_IP0_USER,
|
|
MUX_CLKCMU_PERIC0_IP1_USER,
|
|
FREE_OSCCLK_PERIC0,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric1_uart_bt_parents[] = {
|
|
FREE_OSCCLK_PERIC1,
|
|
MUX_CLKCMU_PERIC1_IP0_USER,
|
|
MUX_CLKCMU_PERIC1_IP1_USER,
|
|
FREE_OSCCLK_PERIC1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric1_i2c_parents[] = {
|
|
FREE_OSCCLK_PERIC1,
|
|
MUX_CLKCMU_PERIC1_IP0_USER,
|
|
MUX_CLKCMU_PERIC1_IP1_USER,
|
|
FREE_OSCCLK_PERIC1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric1_usi07_parents[] = {
|
|
FREE_OSCCLK_PERIC1,
|
|
MUX_CLKCMU_PERIC1_IP0_USER,
|
|
MUX_CLKCMU_PERIC1_IP1_USER,
|
|
FREE_OSCCLK_PERIC1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric1_usi08_parents[] = {
|
|
FREE_OSCCLK_PERIC1,
|
|
MUX_CLKCMU_PERIC1_IP0_USER,
|
|
MUX_CLKCMU_PERIC1_IP1_USER,
|
|
FREE_OSCCLK_PERIC1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric1_usi09_parents[] = {
|
|
FREE_OSCCLK_PERIC1,
|
|
MUX_CLKCMU_PERIC1_IP0_USER,
|
|
MUX_CLKCMU_PERIC1_IP1_USER,
|
|
FREE_OSCCLK_PERIC1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric1_usi10_parents[] = {
|
|
FREE_OSCCLK_PERIC1,
|
|
MUX_CLKCMU_PERIC1_IP0_USER,
|
|
MUX_CLKCMU_PERIC1_IP1_USER,
|
|
FREE_OSCCLK_PERIC1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric1_spi_ms_ctrl_parents[] = {
|
|
FREE_OSCCLK_PERIC1,
|
|
MUX_CLKCMU_PERIC1_IP0_USER,
|
|
MUX_CLKCMU_PERIC1_IP1_USER,
|
|
FREE_OSCCLK_PERIC1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric1_usi07_spi_i2c_parents[] = {
|
|
FREE_OSCCLK_PERIC1,
|
|
MUX_CLKCMU_PERIC1_IP0_USER,
|
|
MUX_CLKCMU_PERIC1_IP1_USER,
|
|
FREE_OSCCLK_PERIC1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric1_usi08_spi_i2c_parents[] = {
|
|
FREE_OSCCLK_PERIC1,
|
|
MUX_CLKCMU_PERIC1_IP0_USER,
|
|
MUX_CLKCMU_PERIC1_IP1_USER,
|
|
FREE_OSCCLK_PERIC1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric2_i2c_parents[] = {
|
|
FREE_OSCCLK_PERIC2,
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
|
FREE_OSCCLK_PERIC2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric2_usi00_parents[] = {
|
|
FREE_OSCCLK_PERIC2,
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
|
FREE_OSCCLK_PERIC2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric2_usi01_parents[] = {
|
|
FREE_OSCCLK_PERIC2,
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
|
FREE_OSCCLK_PERIC2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric2_usi02_parents[] = {
|
|
FREE_OSCCLK_PERIC2,
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
|
FREE_OSCCLK_PERIC2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric2_usi03_parents[] = {
|
|
FREE_OSCCLK_PERIC2,
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
|
FREE_OSCCLK_PERIC2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric2_usi05_parents[] = {
|
|
FREE_OSCCLK_PERIC2,
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
|
FREE_OSCCLK_PERIC2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric2_usi06_parents[] = {
|
|
FREE_OSCCLK_PERIC2,
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
|
FREE_OSCCLK_PERIC2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric2_spi_ms_ctrl_parents[] = {
|
|
FREE_OSCCLK_PERIC2,
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
|
FREE_OSCCLK_PERIC2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric2_usi11_parents[] = {
|
|
FREE_OSCCLK_PERIC2,
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
|
FREE_OSCCLK_PERIC2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric2_uart_dbg_parents[] = {
|
|
FREE_OSCCLK_PERIC2,
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
|
FREE_OSCCLK_PERIC2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric2_usi00_spi_i2c_parents[] = {
|
|
FREE_OSCCLK_PERIC2,
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
|
FREE_OSCCLK_PERIC2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peric2_usi01_spi_i2c_parents[] = {
|
|
FREE_OSCCLK_PERIC2,
|
|
MUX_CLKCMU_PERIC2_IP0_USER,
|
|
MUX_CLKCMU_PERIC2_IP1_USER,
|
|
FREE_OSCCLK_PERIC2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_s2d_core_parents[] = {
|
|
OSCCLK_S2D,
|
|
CLK_MIF_NOCD_S2D,
|
|
};
|
|
enum clk_id cmucal_mux_clk_sdma_noc_parents[] = {
|
|
MUX_CLKCMU_SDMA_NOC_USER,
|
|
MUX_CLKALIVE_SDMA_NOC_USER,
|
|
MUX_CLKALIVE_SDMA_RCO_USER,
|
|
FREE_OSCCLK_SDMA,
|
|
};
|
|
enum clk_id cmucal_mux_clk_ufd_noc_parents[] = {
|
|
MUX_CLKALIVE_UFD_NOC_USER,
|
|
MUX_CLKALIVE_UFD_RCO_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clk_vts_dmic_pad_parents[] = {
|
|
MUX_CLKALIVE_VTS_RCO_USER,
|
|
MUX_CLKCMU_VTS_DMIC_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clkvts_aud_dmic1_parents[] = {
|
|
DIV_CLKVTS_AUD_DMIC1,
|
|
DIV_CLK_VTS_DMIC_IF_DIV2,
|
|
DMIC_CLK0_IN,
|
|
DMCI_CLK1_IN,
|
|
DMIC_CLK2_IN,
|
|
FREE_OSCCLK_VTS,
|
|
FREE_OSCCLK_VTS,
|
|
FREE_OSCCLK_VTS,
|
|
};
|
|
enum clk_id cmucal_mux_clk_vts_noc_parents[] = {
|
|
MUX_CLKALIVE_VTS_NOC_USER,
|
|
MUX_CLKALIVE_VTS_RCO_USER,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_alive_noc_user_parents[] = {
|
|
FREE_OSCCLK_ALIVE,
|
|
CLKCMU_ALIVE_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clk_rco_alive_user_parents[] = {
|
|
FREE_OSCCLK_ALIVE,
|
|
CLK_RCO_ALIVE,
|
|
};
|
|
enum clk_id cmucal_mux_clkmux_alive_rco_spmi_user_parents[] = {
|
|
FREE_OSCCLK_ALIVE,
|
|
CLK_RCO_I3C_PMIC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_aud_cpu_user_parents[] = {
|
|
FREE_OSCCLK_AUD,
|
|
CLKCMU_AUD_CPU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_aud_noc_user_parents[] = {
|
|
FREE_OSCCLK_AUD,
|
|
CLKCMU_AUD_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_cp_pcmc_clk_user_parents[] = {
|
|
FREE_OSCCLK_AUD,
|
|
};
|
|
enum clk_id cmucal_mux_clk_aud_rco_user_parents[] = {
|
|
FREE_OSCCLK_AUD,
|
|
CLK_RCO_AUD,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_aud_audif0_user_parents[] = {
|
|
FREE_OSCCLK_AUD,
|
|
CLKCMU_AUD_AUDIF0,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_aud_audif1_user_parents[] = {
|
|
FREE_OSCCLK_AUD,
|
|
CLKCMU_AUD_AUDIF1,
|
|
};
|
|
enum clk_id cmucal_mux_clkvts_aud_dmic0_user_parents[] = {
|
|
FREE_OSCCLK_AUD,
|
|
CLKVTS_AUD_DMIC0,
|
|
};
|
|
enum clk_id cmucal_mux_clkvts_aud_dmic1_user_parents[] = {
|
|
FREE_OSCCLK_AUD,
|
|
CLKVTS_AUD_DMIC1,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_brp_noc_user_parents[] = {
|
|
FREE_OSCCLK_BRP,
|
|
CLKCMU_BRP_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_chub_noc_user_parents[] = {
|
|
FREE_OSCCLK_CHUB,
|
|
CLKALIVE_CHUBVTS_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_chub_peri_user_parents[] = {
|
|
FREE_OSCCLK_CHUB,
|
|
CLKALIVE_CHUB_PERI,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_chub_rco_user_parents[] = {
|
|
FREE_OSCCLK_CHUB,
|
|
CLKALIVE_CHUBVTS_RCO,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_chubvts_noc_user_parents[] = {
|
|
FREE_OSCCLK_CHUBVTS,
|
|
CLKALIVE_CHUBVTS_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_chubvts_rco_user_parents[] = {
|
|
FREE_OSCCLK_CHUBVTS,
|
|
CLKALIVE_CHUBVTS_RCO,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_cmgp_noc_user_parents[] = {
|
|
FREE_OSCCLK_CMGP,
|
|
CLKALIVE_CMGP_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_cmgp_peri_user_parents[] = {
|
|
FREE_OSCCLK_CMGP,
|
|
CLKALIVE_CMGP_PERI,
|
|
};
|
|
enum clk_id cmucal_mux_cp_mpll_clk_user_parents[] = {
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_cp_mpll_clk_d2_user_parents[] = {
|
|
FREE_OSCCLK_CMU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl0_switch_user_parents[] = {
|
|
FREE_OSCCLK_CPUCL0,
|
|
CLKCMU_CPUCL0_SWITCH,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl0_dbg_noc_user_parents[] = {
|
|
FREE_OSCCLK_CPUCL0_GLB,
|
|
CLKCMU_CPUCL0_DBG_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl0_glb_nocp_user_parents[] = {
|
|
FREE_OSCCLK_CPUCL0_GLB,
|
|
CLKCMU_CPUCL0_NOCP,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl1_switch_user_parents[] = {
|
|
FREE_OSCCLK_CPUCL1,
|
|
CLKCMU_CPUCL1_SWITCH,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cpucl2_switch_user_parents[] = {
|
|
FREE_OSCCLK_CPUCL2,
|
|
CLKCMU_CPUCL2_SWITCH,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_csis_dcphy_user_parents[] = {
|
|
FREE_OSCCLK_CSIS,
|
|
CLKCMU_CSIS_DCPHY,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_csis_rco_user_parents[] = {
|
|
FREE_OSCCLK_CSIS,
|
|
CLKALIVE_CSIS_RCO,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_csis_noc_user_parents[] = {
|
|
FREE_OSCCLK_CSIS,
|
|
CLKCMU_CSIS_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_csis_noc_user_parents[] = {
|
|
FREE_OSCCLK_CSIS,
|
|
CLKALIVE_CSIS_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_csis_ois_mcu_user_parents[] = {
|
|
FREE_OSCCLK_CSIS,
|
|
CLKCMU_CSIS_OIS_MCU,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_cstat_noc_user_parents[] = {
|
|
FREE_OSCCLK_CSTAT,
|
|
CLKCMU_CSTAT_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_dbgcore_noc_user_parents[] = {
|
|
FREE_OSCCLK_DBGCORE,
|
|
CLKALIVE_DBGCORE_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dnc_noc_user_parents[] = {
|
|
FREE_OSCCLK_DNC,
|
|
CLKCMU_DNC_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_dnc_rco_user_parents[] = {
|
|
FREE_OSCCLK_DNC,
|
|
CLKALIVE_DNC_RCO,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_dnc_noc_user_parents[] = {
|
|
FREE_OSCCLK_DNC,
|
|
CLKALIVE_DNC_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpub_noc_user_parents[] = {
|
|
FREE_OSCCLK_DPUB,
|
|
CLKCMU_DPUB_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpub_dsim_user_parents[] = {
|
|
FREE_OSCCLK_DPUB,
|
|
CLKCMU_DPUB_DSIM,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpuf_noc_user_parents[] = {
|
|
FREE_OSCCLK_DPUF,
|
|
CLKCMU_DPUF_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dpuf1_noc_user_parents[] = {
|
|
FREE_OSCCLK_DPUF1,
|
|
OSCCLK_DPUF1,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_drcp_noc_user_parents[] = {
|
|
FREE_OSCCLK_DRCP,
|
|
FREE_OSCCLK_DRCP,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dsp_noc_user_parents[] = {
|
|
FREE_OSCCLK_DSP,
|
|
CLKCMU_DSP_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_sdma_rco_user_cpy_parents[] = {
|
|
FREE_OSCCLK_DSP,
|
|
CLKALIVE_DSP_RCO,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_sdma_noc_user_cpy_parents[] = {
|
|
FREE_OSCCLK_DSP,
|
|
CLKALIVE_DSP_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_dsu_switch_user_parents[] = {
|
|
FREE_OSCCLK_DSU,
|
|
CLKCMU_DSU_SWITCH,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_g3d_nocp_user_parents[] = {
|
|
FREE_OSCCLK_G3D,
|
|
CLKCMU_G3D_NOCP,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_g3d_switch_user_parents[] = {
|
|
FREE_OSCCLK_G3DCORE,
|
|
CLKCMU_G3D_SWITCH,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_gnpu_noc_user_parents[] = {
|
|
FREE_OSCCLK_GNPU,
|
|
CLKCMU_GNPU_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_gnpu_noc_user_parents[] = {
|
|
FREE_OSCCLK_GNPU,
|
|
CLKALIVE_GNPU_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_gnpu_rco_user_parents[] = {
|
|
FREE_OSCCLK_GNPU,
|
|
CLKALIVE_GNPU_RCO,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi0_dposc_user_parents[] = {
|
|
FREE_OSCCLK_HSI0,
|
|
CLKCMU_HSI0_DPOSC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi0_noc_user_parents[] = {
|
|
FREE_OSCCLK_HSI0,
|
|
CLKCMU_HSI0_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi0_usb32drd_user_parents[] = {
|
|
FREE_OSCCLK_HSI0,
|
|
CLKCMU_HSI0_USB32DRD,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi0_dpgtc_user_parents[] = {
|
|
FREE_OSCCLK_HSI0,
|
|
CLKCMU_HSI0_DPGTC,
|
|
};
|
|
enum clk_id cmucal_mux_clkaud_hsi0_noc_user_parents[] = {
|
|
FREE_OSCCLK_HSI0,
|
|
CLKAUD_HSI0_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi1_noc_user_parents[] = {
|
|
FREE_OSCCLK_HSI1,
|
|
CLKCMU_HSI1_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_hsi1_pcie_user_parents[] = {
|
|
FREE_OSCCLK_HSI1,
|
|
CLKCMU_HSI1_PCIE,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_lme_noc_user_parents[] = {
|
|
FREE_OSCCLK_LME,
|
|
CLKCMU_LME_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_lme_lme_user_parents[] = {
|
|
FREE_OSCCLK_LME,
|
|
CLKCMU_LME_LME,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_m2m_noc_user_parents[] = {
|
|
FREE_OSCCLK_M2M,
|
|
CLKCMU_M2M_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_m2m_frc_user_parents[] = {
|
|
FREE_OSCCLK_M2M,
|
|
CLKCMU_M2M_FRC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mcsc_noc_user_parents[] = {
|
|
FREE_OSCCLK_MCSC,
|
|
CLKCMU_MCSC_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mcsc_mcsc_user_parents[] = {
|
|
FREE_OSCCLK_MCSC,
|
|
CLKCMU_MCSC_MCSC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mfc0_mfc0_user_parents[] = {
|
|
FREE_OSCCLK_MFC0,
|
|
CLKCMU_MFC0_MFC0,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mfc0_wfd_user_parents[] = {
|
|
FREE_OSCCLK_MFC0,
|
|
CLKCMU_MFC0_WFD,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mfc1_mfc1_user_parents[] = {
|
|
FREE_OSCCLK_MFC1,
|
|
CLKCMU_MFC1_MFC1,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_mif_nocp_user_parents[] = {
|
|
FREE_OSCCLK_MIF,
|
|
CLKCMU_MIF_NOCP,
|
|
};
|
|
enum clk_id cmucal_clkmux_mif_ddrphy2x_parents[] = {
|
|
FREE_OSCCLK_MIF,
|
|
CLKCMU_MIF01_SWITCH,
|
|
PLL_MIF_MAIN_D1,
|
|
PLL_MIF_SUB_D1,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_nocl0_noc_user_parents[] = {
|
|
FREE_OSCCLK_NOCL0,
|
|
CLKCMU_NOCL0_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_nocl1a_noc_user_parents[] = {
|
|
FREE_OSCCLK_NOCL1A,
|
|
CLKCMU_NOCL1A_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_nocl1b_noc0_user_parents[] = {
|
|
FREE_OSCCLK_NOCL1B,
|
|
CLKCMU_NOCL1B_NOC0,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_nocl1b_noc1_user_parents[] = {
|
|
FREE_OSCCLK_NOCL1B,
|
|
CLKCMU_NOCL1B_NOC1,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_nocl1c_noc_user_parents[] = {
|
|
FREE_OSCCLK_NOCL1C,
|
|
CLKCMU_NOCL1C_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric0_noc_user_parents[] = {
|
|
FREE_OSCCLK_PERIC0,
|
|
CLKCMU_PERIC0_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric0_ip0_user_parents[] = {
|
|
FREE_OSCCLK_PERIC0,
|
|
CLKCMU_PERIC0_IP0,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric0_ip1_user_parents[] = {
|
|
FREE_OSCCLK_PERIC0,
|
|
CLKCMU_PERIC0_IP1,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric1_noc_user_parents[] = {
|
|
FREE_OSCCLK_PERIC1,
|
|
CLKCMU_PERIC1_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric1_ip0_user_parents[] = {
|
|
FREE_OSCCLK_PERIC1,
|
|
CLKCMU_PERIC1_IP0,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric1_ip1_user_parents[] = {
|
|
FREE_OSCCLK_PERIC1,
|
|
CLKCMU_PERIC1_IP1,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric2_ip0_user_parents[] = {
|
|
FREE_OSCCLK_PERIC2,
|
|
CLKCMU_PERIC2_IP0,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric2_ip1_user_parents[] = {
|
|
FREE_OSCCLK_PERIC2,
|
|
CLKCMU_PERIC2_IP1,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peric2_noc_user_parents[] = {
|
|
FREE_OSCCLK_PERIC2,
|
|
CLKCMU_PERIC2_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peris_noc_user_parents[] = {
|
|
FREE_OSCCLK_PERIS,
|
|
CLKCMU_PERIS_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_peris_gic_user_parents[] = {
|
|
FREE_OSCCLK_PERIS,
|
|
CLKCMU_PERIS_GIC,
|
|
};
|
|
enum clk_id cmucal_clkcmu_mif_ddrphy2x_s2d_parents[] = {
|
|
FREE_OSCCLK_S2D,
|
|
PLL_MIF_S2D_D1,
|
|
PLL_MIF_S2D_D1,
|
|
PLL_MIF_S2D_D1,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_sdma_noc_user_parents[] = {
|
|
FREE_OSCCLK_SDMA,
|
|
CLKCMU_SDMA_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_sdma_rco_user_parents[] = {
|
|
FREE_OSCCLK_SDMA,
|
|
CLKALIVE_SDMA_RCO,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_sdma_noc_user_parents[] = {
|
|
FREE_OSCCLK_SDMA,
|
|
CLKALIVE_SDMA_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_ssp_noc_user_parents[] = {
|
|
FREE_OSCCLK_SSP,
|
|
CLKCMU_SSP_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_ufd_noc_user_parents[] = {
|
|
FREE_OSCCLK_UFD,
|
|
CLKALIVE_UFD_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_ufd_rco_user_parents[] = {
|
|
FREE_OSCCLK_UFD,
|
|
CLKALIVE_UFD_RCO,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_ufs_ufs_embd_user_parents[] = {
|
|
FREE_OSCCLK_UFS,
|
|
CLKCMU_UFS_UFS_EMBD,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_ufs_noc_user_parents[] = {
|
|
FREE_OSCCLK_UFS,
|
|
CLKCMU_UFS_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_ufs_mmc_card_user_parents[] = {
|
|
FREE_OSCCLK_UFS,
|
|
CLKCMU_UFS_MMC_CARD,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_vts_noc_user_parents[] = {
|
|
FREE_OSCCLK_VTS,
|
|
CLKALIVE_CHUBVTS_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_vts_dmic_user_parents[] = {
|
|
FREE_OSCCLK_VTS,
|
|
CLKCMU_VTS_DMIC,
|
|
};
|
|
enum clk_id cmucal_mux_clkalive_vts_rco_user_parents[] = {
|
|
FREE_OSCCLK_VTS,
|
|
CLKALIVE_CHUBVTS_RCO,
|
|
};
|
|
enum clk_id cmucal_mux_clkcmu_yuvp_noc_user_parents[] = {
|
|
FREE_OSCCLK_YUVP,
|
|
CLKCMU_YUVP_NOC,
|
|
};
|
|
enum clk_id cmucal_mux_hchgen_clk_aud_cpu_parents[] = {
|
|
MUX_CLK_AUD_CPU,
|
|
FREE_OSCCLK_AUD,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl0_strmux_parents[] = {
|
|
MUX_CLK_CPUCL0_DELAYMUX,
|
|
STRETCHER_CLK_CPUCL0,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_strmux_0_parents[] = {
|
|
MUX_CLK_CPUCL1_DELAYMUX_0,
|
|
STRETCHER_CLK_CPUCL1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_strmux_1_parents[] = {
|
|
MUX_CLK_CPUCL1_DELAYMUX_1,
|
|
STRETCHER_CLK_CPUCL1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl1_strmux_2_parents[] = {
|
|
MUX_CLK_CPUCL1_DELAYMUX_2,
|
|
STRETCHER_CLK_CPUCL1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_cpucl2_strmux_parents[] = {
|
|
MUX_CLK_CPUCL2_DELAYMUX,
|
|
STRETCHER_CLK_CPUCL2,
|
|
};
|
|
enum clk_id cmucal_mux_clk_dbgcore_noc_parents[] = {
|
|
MUX_CLKALIVE_DBGCORE_NOC_USER,
|
|
TCXO_IN,
|
|
};
|
|
enum clk_id cmucal_mux_oscclk_dbgcore_parents[] = {
|
|
OSCCLK_DBGCORE,
|
|
TCXO_IN,
|
|
};
|
|
enum clk_id cmucal_mux_free_oscclk_dbgcore_parents[] = {
|
|
FREE_OSCCLK_DBGCORE,
|
|
TCXO_IN,
|
|
};
|
|
enum clk_id cmucal_mux_clk_dsu_strmux_parents[] = {
|
|
MUX_CLK_DSU_DELAYMUX,
|
|
STRETCHER_CLK_DSU,
|
|
};
|
|
enum clk_id cmucal_mux_clk_g3d_strmux_parents[] = {
|
|
MUX_CLK_G3D_DELAYMUX,
|
|
PLL_G3D1_D1,
|
|
};
|
|
enum clk_id cmucal_mux_clk_peris_gic_parents[] = {
|
|
MUX_CLKCMU_PERIS_GIC_USER,
|
|
FREE_OSCCLK_PERIS,
|
|
};
|
|
unsigned int cmucal_mux_size = 406;
|
|
struct cmucal_mux cmucal_mux_list[] = {
|
|
CLK_MUX(MUX_CLKALIVE_UFD_NOC, cmucal_mux_clkalive_ufd_noc_parents, CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC_SELECT, CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC_BUSY, CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_CMGP_NOC, cmucal_mux_clkalive_cmgp_noc_parents, CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC_SELECT, CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC_BUSY, CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_ALIVE_NOC, cmucal_mux_clk_alive_noc_parents, CLK_CON_MUX_MUX_CLK_ALIVE_NOC_SELECT, CLK_CON_MUX_MUX_CLK_ALIVE_NOC_BUSY, CLK_CON_MUX_MUX_CLK_ALIVE_NOC_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_CMGP_PERI, cmucal_mux_clkalive_cmgp_peri_parents, CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI_SELECT, CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI_BUSY, CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_CHUB_PERI, cmucal_mux_clkalive_chub_peri_parents, CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI_SELECT, CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI_BUSY, CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_DBGCORE_NOC, cmucal_mux_clkalive_dbgcore_noc_parents, CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC_SELECT, CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC_BUSY, CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_DNC_NOC, cmucal_mux_clkalive_dnc_noc_parents, CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC_SELECT, CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC_BUSY, CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_ALIVE_TIMER, cmucal_mux_clk_alive_timer_parents, CLK_CON_MUX_MUX_CLK_ALIVE_TIMER_SELECT, CLK_CON_MUX_MUX_CLK_ALIVE_TIMER_BUSY, CLK_CON_MUX_MUX_CLK_ALIVE_TIMER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_ALIVE_SPMI, cmucal_mux_clk_alive_spmi_parents, CLK_CON_MUX_MUX_CLK_ALIVE_SPMI_SELECT, CLK_CON_MUX_MUX_CLK_ALIVE_SPMI_BUSY, CLK_CON_MUX_MUX_CLK_ALIVE_SPMI_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_ALIVE_DBGCORE_UART, cmucal_mux_clk_alive_dbgcore_uart_parents, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_SELECT, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_BUSY, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_GNPU_NOC, cmucal_mux_clkalive_gnpu_noc_parents, CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC_SELECT, CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC_BUSY, CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_GNSS_NOC, cmucal_mux_clkalive_gnss_noc_parents, CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC_SELECT, CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC_BUSY, CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_SDMA_NOC, cmucal_mux_clkalive_sdma_noc_parents, CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC_SELECT, CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC_BUSY, CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_ALIVE_PMU_SUB, cmucal_mux_clk_alive_pmu_sub_parents, CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB_SELECT, CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB_BUSY, CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_CHUBVTS_NOC, cmucal_mux_clkalive_chubvts_noc_parents, CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC_SELECT, CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC_BUSY, CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_CSIS_NOC, cmucal_mux_clkalive_csis_noc_parents, CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC_SELECT, CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC_BUSY, CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_DSP_NOC, cmucal_mux_clkalive_dsp_noc_parents, CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC_SELECT, CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC_BUSY, CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_UAIF3, cmucal_mux_clk_aud_uaif3_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF3_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF3_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_UAIF2, cmucal_mux_clk_aud_uaif2_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_UAIF1, cmucal_mux_clk_aud_uaif1_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_UAIF0, cmucal_mux_clk_aud_uaif0_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_CPU, cmucal_mux_clk_aud_cpu_parents, CLK_CON_MUX_MUX_CLK_AUD_CPU_SELECT, CLK_CON_MUX_MUX_CLK_AUD_CPU_BUSY, CLK_CON_MUX_MUX_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_DSIF, cmucal_mux_clk_aud_dsif_parents, CLK_CON_MUX_MUX_CLK_AUD_DSIF_SELECT, CLK_CON_MUX_MUX_CLK_AUD_DSIF_BUSY, CLK_CON_MUX_MUX_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_UAIF4, cmucal_mux_clk_aud_uaif4_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF4_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF4_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF4_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_UAIF5, cmucal_mux_clk_aud_uaif5_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF5_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF5_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF5_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_UAIF6, cmucal_mux_clk_aud_uaif6_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF6_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF6_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF6_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_NOC, cmucal_mux_clk_aud_noc_parents, CLK_CON_MUX_MUX_CLK_AUD_NOC_SELECT, CLK_CON_MUX_MUX_CLK_AUD_NOC_BUSY, CLK_CON_MUX_MUX_CLK_AUD_NOC_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_PCMC, cmucal_mux_clk_aud_pcmc_parents, CLK_CON_MUX_MUX_CLK_AUD_PCMC_SELECT, CLK_CON_MUX_MUX_CLK_AUD_PCMC_BUSY, CLK_CON_MUX_MUX_CLK_AUD_PCMC_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_AUDIF, cmucal_mux_clk_aud_audif_parents, CLK_CON_MUX_MUX_CLK_AUD_AUDIF_SELECT, CLK_CON_MUX_MUX_CLK_AUD_AUDIF_BUSY, CLK_CON_MUX_MUX_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_SCLK, cmucal_mux_clk_aud_sclk_parents, CLK_CON_MUX_MUX_CLK_AUD_SCLK_SELECT, CLK_CON_MUX_MUX_CLK_AUD_SCLK_BUSY, CLK_CON_MUX_MUX_CLK_AUD_SCLK_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_SERIAL_LIF, cmucal_mux_clk_aud_serial_lif_parents, CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_SELECT, CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_BUSY, CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_SERIAL_LIF_CORE, cmucal_mux_clk_aud_serial_lif_core_parents, CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_CORE_SELECT, CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_CORE_BUSY, CLK_CON_MUX_MUX_CLK_AUD_SERIAL_LIF_CORE_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CHUB_TIMER, cmucal_mux_chub_timer_parents, CLK_CON_MUX_MUX_CHUB_TIMER_SELECT, CLK_CON_MUX_MUX_CHUB_TIMER_BUSY, CLK_CON_MUX_MUX_CHUB_TIMER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CHUB_USI0, cmucal_mux_clk_chub_usi0_parents, CLK_CON_MUX_MUX_CLK_CHUB_USI0_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_USI0_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_USI0_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CHUB_USI1, cmucal_mux_clk_chub_usi1_parents, CLK_CON_MUX_MUX_CLK_CHUB_USI1_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_USI1_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_USI1_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CHUB_USI3, cmucal_mux_clk_chub_usi3_parents, CLK_CON_MUX_MUX_CLK_CHUB_USI3_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_USI3_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_USI3_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CHUB_I2C, cmucal_mux_clk_chub_i2c_parents, CLK_CON_MUX_MUX_CLK_CHUB_I2C_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_I2C_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CHUB_USI2, cmucal_mux_clk_chub_usi2_parents, CLK_CON_MUX_MUX_CLK_CHUB_USI2_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_USI2_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_USI2_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CHUB_SPI_MS_CTRL, cmucal_mux_clk_chub_spi_ms_ctrl_parents, CLK_CON_MUX_MUX_CLK_CHUB_SPI_MS_CTRL_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_SPI_MS_CTRL_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CHUB_SPI_I2C0, cmucal_mux_clk_chub_spi_i2c0_parents, CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C0_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C0_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C0_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CHUB_SPI_I2C1, cmucal_mux_clk_chub_spi_i2c1_parents, CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C1_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C1_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_SPI_I2C1_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CHUB_NOC, cmucal_mux_clk_chub_noc_parents, CLK_CON_MUX_MUX_CLK_CHUB_NOC_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_NOC_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_NOC_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CHUBVTS_DMAILBOX_CCLK, cmucal_mux_clk_chubvts_dmailbox_cclk_parents, CLK_CON_MUX_MUX_CLK_CHUBVTS_DMAILBOX_CCLK_SELECT, CLK_CON_MUX_MUX_CLK_CHUBVTS_DMAILBOX_CCLK_BUSY, CLK_CON_MUX_MUX_CLK_CHUBVTS_DMAILBOX_CCLK_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CHUBVTS_NOC, cmucal_mux_clk_chubvts_noc_parents, CLK_CON_MUX_MUX_CLK_CHUBVTS_NOC_SELECT, CLK_CON_MUX_MUX_CLK_CHUBVTS_NOC_BUSY, CLK_CON_MUX_MUX_CLK_CHUBVTS_NOC_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CMGP_USI4, cmucal_mux_clk_cmgp_usi4_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI4_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI4_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI4_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CMGP_USI0, cmucal_mux_clk_cmgp_usi0_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI0_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI0_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CMGP_USI1, cmucal_mux_clk_cmgp_usi1_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI1_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI1_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI1_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CMGP_USI2, cmucal_mux_clk_cmgp_usi2_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI2_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI2_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI2_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CMGP_USI3, cmucal_mux_clk_cmgp_usi3_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI3_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI3_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI3_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CMGP_USI5, cmucal_mux_clk_cmgp_usi5_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI5_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI5_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI5_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CMGP_USI6, cmucal_mux_clk_cmgp_usi6_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI6_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI6_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI6_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CMGP_I2C, cmucal_mux_clk_cmgp_i2c_parents, CLK_CON_MUX_MUX_CLK_CMGP_I2C_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_I2C_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CMGP_SPI_MS_CTRL, cmucal_mux_clk_cmgp_spi_ms_ctrl_parents, CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CMGP_SPI_I2C0, cmucal_mux_clk_cmgp_spi_i2c0_parents, CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_CMGP_SPI_I2C1, cmucal_mux_clk_cmgp_spi_i2c1_parents, CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_HSI0_DPOSC, cmucal_mux_clkcmu_hsi0_dposc_parents, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MFC0_MFC0, cmucal_mux_clkcmu_mfc0_mfc0_parents, CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0_SELECT, CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DSP_NOC, cmucal_mux_clkcmu_dsp_noc_parents, CLK_CON_MUX_MUX_CLKCMU_DSP_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_DSP_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL0_SWITCH, cmucal_mux_clkcmu_cpucl0_switch_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_NOCL0_NOC, cmucal_mux_clkcmu_nocl0_noc_parents, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MIF_SWITCH, cmucal_mux_clkcmu_mif_switch_parents, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_BRP_NOC, cmucal_mux_clkcmu_brp_noc_parents, CLK_CON_MUX_MUX_CLKCMU_BRP_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_BRP_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_BRP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_YUVP_NOC, cmucal_mux_clkcmu_yuvp_noc_parents, CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_AUD_CPU, cmucal_mux_clkcmu_aud_cpu_parents, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_SELECT, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_BUSY, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL0_DBG_NOC, cmucal_mux_clkcmu_cpucl0_dbg_noc_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CIS_CLK0, cmucal_mux_clkcmu_cis_clk0_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CIS_CLK1, cmucal_mux_clkcmu_cis_clk1_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CIS_CLK2, cmucal_mux_clkcmu_cis_clk2_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CIS_CLK3, cmucal_mux_clkcmu_cis_clk3_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CMU_CMUREF, cmucal_mux_cmu_cmuref_parents, CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC0_NOC, cmucal_mux_clkcmu_peric0_noc_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC1_NOC, cmucal_mux_clkcmu_peric1_noc_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIS_NOC, cmucal_mux_clkcmu_peris_noc_parents, CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI1_PCIE, cmucal_mux_clkcmu_hsi1_pcie_parents, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_GNPU_NOC, cmucal_mux_clkcmu_gnpu_noc_parents, CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_ALIVE_NOC, cmucal_mux_clkcmu_alive_noc_parents, CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI1_NOC, cmucal_mux_clkcmu_hsi1_noc_parents, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MFC0_WFD, cmucal_mux_clkcmu_mfc0_wfd_parents, CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD_SELECT, CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MIF_NOCP, cmucal_mux_clkcmu_mif_nocp_parents, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC0_IP0, cmucal_mux_clkcmu_peric0_ip0_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC1_IP0, cmucal_mux_clkcmu_peric1_ip0_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_DPUF_NOC, cmucal_clkcmu_dpuf_noc_parents, CLK_CON_MUX_CLKCMU_DPUF_NOC_SELECT, CLK_CON_MUX_CLKCMU_DPUF_NOC_BUSY, CLK_CON_MUX_CLKCMU_DPUF_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DPUF_ALT, cmucal_mux_clkcmu_dpuf_alt_parents, CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT_SELECT, CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT_BUSY, CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL1_SWITCH, cmucal_mux_clkcmu_cpucl1_switch_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI0_NOC, cmucal_mux_clkcmu_hsi0_noc_parents, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CMU_BOOST_MIF, cmucal_mux_clkcmu_cmu_boost_mif_parents, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF_SELECT, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF_BUSY, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CIS_CLK4, cmucal_mux_clkcmu_cis_clk4_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DPUF, cmucal_mux_clkcmu_dpuf_parents, CLK_CON_MUX_MUX_CLKCMU_DPUF_SELECT, CLK_CON_MUX_MUX_CLKCMU_DPUF_BUSY, CLK_CON_MUX_MUX_CLKCMU_DPUF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CMU_BOOST, cmucal_mux_clkcmu_cmu_boost_parents, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_SELECT, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_BUSY, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CSIS_NOC, cmucal_mux_clkcmu_csis_noc_parents, CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MCSC_NOC, cmucal_mux_clkcmu_mcsc_noc_parents, CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CSIS_OIS_MCU, cmucal_mux_clkcmu_csis_ois_mcu_parents, CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU_SELECT, CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU_BUSY, CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CIS_CLK5, cmucal_mux_clkcmu_cis_clk5_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CMU_BOOST_CPU, cmucal_mux_clkcmu_cmu_boost_cpu_parents, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU_SELECT, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU_BUSY, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_M2M_NOC, cmucal_mux_clkcmu_m2m_noc_parents, CLK_CON_MUX_MUX_CLKCMU_M2M_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_M2M_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_M2M_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DPUB_ALT, cmucal_mux_clkcmu_dpub_alt_parents, CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT_SELECT, CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT_BUSY, CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_DPUB_NOC, cmucal_clkcmu_dpub_noc_parents, CLK_CON_MUX_CLKCMU_DPUB_NOC_SELECT, CLK_CON_MUX_CLKCMU_DPUB_NOC_BUSY, CLK_CON_MUX_CLKCMU_DPUB_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DPUB, cmucal_mux_clkcmu_dpub_parents, CLK_CON_MUX_MUX_CLKCMU_DPUB_SELECT, CLK_CON_MUX_MUX_CLKCMU_DPUB_BUSY, CLK_CON_MUX_MUX_CLKCMU_DPUB_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MFC1_MFC1, cmucal_mux_clkcmu_mfc1_mfc1_parents, CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1_SELECT, CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_LME_NOC, cmucal_mux_clkcmu_lme_noc_parents, CLK_CON_MUX_MUX_CLKCMU_LME_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_LME_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_LME_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI0_USB32DRD, cmucal_mux_clkcmu_hsi0_usb32drd_parents, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI0_DPGTC, cmucal_mux_clkcmu_hsi0_dpgtc_parents, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_AUD_NOC, cmucal_mux_clkcmu_aud_noc_parents, CLK_CON_MUX_MUX_CLKCMU_AUD_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_AUD_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_AUD_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CSIS_DCPHY, cmucal_mux_clkcmu_csis_dcphy_parents, CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY_SELECT, CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY_BUSY, CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CP_HISPEEDY_CLK, cmucal_mux_cp_hispeedy_clk_parents, CLK_CON_MUX_MUX_CP_HISPEEDY_CLK_SELECT, CLK_CON_MUX_MUX_CP_HISPEEDY_CLK_BUSY, CLK_CON_MUX_MUX_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC0_IP1, cmucal_mux_clkcmu_peric0_ip1_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC1_IP1, cmucal_mux_clkcmu_peric1_ip1_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_SSP_NOC, cmucal_mux_clkcmu_ssp_noc_parents, CLK_CON_MUX_MUX_CLKCMU_SSP_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_SSP_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_SSP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_G3D_SWITCH, cmucal_mux_clkcmu_g3d_switch_parents, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC2_IP0, cmucal_mux_clkcmu_peric2_ip0_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC2_NOC, cmucal_mux_clkcmu_peric2_noc_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC2_IP1, cmucal_mux_clkcmu_peric2_ip1_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL0_NOCP, cmucal_mux_clkcmu_cpucl0_nocp_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DSU_SWITCH, cmucal_mux_clkcmu_dsu_switch_parents, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_G3D_NOCP, cmucal_mux_clkcmu_g3d_nocp_parents, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP_SELECT, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP_BUSY, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CSTAT_NOC, cmucal_mux_clkcmu_cstat_noc_parents, CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DPUB_DSIM, cmucal_mux_clkcmu_dpub_dsim_parents, CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM_SELECT, CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM_BUSY, CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_DNC_NOC, cmucal_mux_clkcmu_dnc_noc_parents, CLK_CON_MUX_MUX_CLKCMU_DNC_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_DNC_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CPUCL2_SWITCH, cmucal_mux_clkcmu_cpucl2_switch_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_SDMA_NOC, cmucal_mux_clkcmu_sdma_noc_parents, CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CIS_CLK6, cmucal_mux_clkcmu_cis_clk6_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_NOCL1C_NOC, cmucal_mux_clkcmu_nocl1c_noc_parents, CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CP_SHARED0_CLK, cmucal_mux_cp_shared0_clk_parents, CLK_CON_MUX_MUX_CP_SHARED0_CLK_SELECT, CLK_CON_MUX_MUX_CP_SHARED0_CLK_BUSY, CLK_CON_MUX_MUX_CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CP_SHARED1_CLK, cmucal_mux_cp_shared1_clk_parents, CLK_CON_MUX_MUX_CP_SHARED1_CLK_SELECT, CLK_CON_MUX_MUX_CP_SHARED1_CLK_BUSY, CLK_CON_MUX_MUX_CP_SHARED1_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CP_SHARED2_CLK, cmucal_mux_cp_shared2_clk_parents, CLK_CON_MUX_MUX_CP_SHARED2_CLK_SELECT, CLK_CON_MUX_MUX_CP_SHARED2_CLK_BUSY, CLK_CON_MUX_MUX_CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CMU_BOOST_CAM, cmucal_mux_clkcmu_cmu_boost_cam_parents, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM_SELECT, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM_BUSY, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_VTS_DMIC, cmucal_mux_clkcmu_vts_dmic_parents, CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC_SELECT, CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC_BUSY, CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_AUD_AUDIF0, cmucal_mux_clkcmu_aud_audif0_parents, CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0_SELECT, CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0_BUSY, CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_AUD_AUDIF1, cmucal_mux_clkcmu_aud_audif1_parents, CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1_SELECT, CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1_BUSY, CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIS_GIC, cmucal_mux_clkcmu_peris_gic_parents, CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_CIS_CLK7, cmucal_mux_clkcmu_cis_clk7_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_NOCL1B_NOC0, cmucal_mux_clkcmu_nocl1b_noc0_parents, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0_SELECT, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0_BUSY, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_NOCL1A_NOC, cmucal_mux_clkcmu_nocl1a_noc_parents, CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_NOCL1B_NOC1, cmucal_mux_clkcmu_nocl1b_noc1_parents, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1_SELECT, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1_BUSY, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_LME_LME, cmucal_mux_clkcmu_lme_lme_parents, CLK_CON_MUX_MUX_CLKCMU_LME_LME_SELECT, CLK_CON_MUX_MUX_CLKCMU_LME_LME_BUSY, CLK_CON_MUX_MUX_CLKCMU_LME_LME_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_M2M_FRC, cmucal_mux_clkcmu_m2m_frc_parents, CLK_CON_MUX_MUX_CLKCMU_M2M_FRC_SELECT, CLK_CON_MUX_MUX_CLKCMU_M2M_FRC_BUSY, CLK_CON_MUX_MUX_CLKCMU_M2M_FRC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MCSC_MCSC, cmucal_mux_clkcmu_mcsc_mcsc_parents, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_SELECT, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_BUSY, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_UFS_UFS_EMBD, cmucal_mux_clkcmu_ufs_ufs_embd_parents, CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD_SELECT, CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD_BUSY, CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_UFS_NOC, cmucal_mux_clkcmu_ufs_noc_parents, CLK_CON_MUX_MUX_CLKCMU_UFS_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_UFS_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_UFS_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_UFS_MMC_CARD, cmucal_mux_clkcmu_ufs_mmc_card_parents, CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD_SELECT, CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD_BUSY, CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_AUD_CPU, cmucal_clkcmu_aud_cpu_parents, CLK_CON_MUX_CLKCMU_AUD_CPU_SELECT, CLK_CON_MUX_CLKCMU_AUD_CPU_BUSY, CLK_CON_MUX_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_AUD_AUDIF0, cmucal_clkcmu_aud_audif0_parents, CLK_CON_MUX_CLKCMU_AUD_AUDIF0_SELECT, CLK_CON_MUX_CLKCMU_AUD_AUDIF0_BUSY, CLK_CON_MUX_CLKCMU_AUD_AUDIF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_AUD_AUDIF1, cmucal_clkcmu_aud_audif1_parents, CLK_CON_MUX_CLKCMU_AUD_AUDIF1_SELECT, CLK_CON_MUX_CLKCMU_AUD_AUDIF1_BUSY, CLK_CON_MUX_CLKCMU_AUD_AUDIF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_CPUCL0_SWITCH, cmucal_clkcmu_cpucl0_switch_parents, CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_CPUCL1_SWITCH, cmucal_clkcmu_cpucl1_switch_parents, CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_CPUCL2_SWITCH, cmucal_clkcmu_cpucl2_switch_parents, CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH_SELECT, CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH_BUSY, CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_DSU_SWITCH, cmucal_clkcmu_dsu_switch_parents, CLK_CON_MUX_CLKCMU_DSU_SWITCH_SELECT, CLK_CON_MUX_CLKCMU_DSU_SWITCH_BUSY, CLK_CON_MUX_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_CPUCL0_DBG_NOC, cmucal_clkcmu_cpucl0_dbg_noc_parents, CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC_SELECT, CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC_BUSY, CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_DNC_NOC, cmucal_clkcmu_dnc_noc_parents, CLK_CON_MUX_CLKCMU_DNC_NOC_SELECT, CLK_CON_MUX_CLKCMU_DNC_NOC_BUSY, CLK_CON_MUX_CLKCMU_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_SDMA_NOC, cmucal_clkcmu_sdma_noc_parents, CLK_CON_MUX_CLKCMU_SDMA_NOC_SELECT, CLK_CON_MUX_CLKCMU_SDMA_NOC_BUSY, CLK_CON_MUX_CLKCMU_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_DSP_NOC, cmucal_clkcmu_dsp_noc_parents, CLK_CON_MUX_CLKCMU_DSP_NOC_SELECT, CLK_CON_MUX_CLKCMU_DSP_NOC_BUSY, CLK_CON_MUX_CLKCMU_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_G3D_SWITCH, cmucal_clkcmu_g3d_switch_parents, CLK_CON_MUX_CLKCMU_G3D_SWITCH_SELECT, CLK_CON_MUX_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_MUX_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_GNPU_NOC, cmucal_clkcmu_gnpu_noc_parents, CLK_CON_MUX_CLKCMU_GNPU_NOC_SELECT, CLK_CON_MUX_CLKCMU_GNPU_NOC_BUSY, CLK_CON_MUX_CLKCMU_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_M2M_NOC, cmucal_clkcmu_m2m_noc_parents, CLK_CON_MUX_CLKCMU_M2M_NOC_SELECT, CLK_CON_MUX_CLKCMU_M2M_NOC_BUSY, CLK_CON_MUX_CLKCMU_M2M_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_M2M_FRC, cmucal_clkcmu_m2m_frc_parents, CLK_CON_MUX_CLKCMU_M2M_FRC_SELECT, CLK_CON_MUX_CLKCMU_M2M_FRC_BUSY, CLK_CON_MUX_CLKCMU_M2M_FRC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_MCSC_NOC, cmucal_clkcmu_mcsc_noc_parents, CLK_CON_MUX_CLKCMU_MCSC_NOC_SELECT, CLK_CON_MUX_CLKCMU_MCSC_NOC_BUSY, CLK_CON_MUX_CLKCMU_MCSC_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_MCSC_MCSC, cmucal_clkcmu_mcsc_mcsc_parents, CLK_CON_MUX_CLKCMU_MCSC_MCSC_SELECT, CLK_CON_MUX_CLKCMU_MCSC_MCSC_BUSY, CLK_CON_MUX_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_NOCL0_NOC, cmucal_clkcmu_nocl0_noc_parents, CLK_CON_MUX_CLKCMU_NOCL0_NOC_SELECT, CLK_CON_MUX_CLKCMU_NOCL0_NOC_BUSY, CLK_CON_MUX_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_NOCL1A_NOC, cmucal_clkcmu_nocl1a_noc_parents, CLK_CON_MUX_CLKCMU_NOCL1A_NOC_SELECT, CLK_CON_MUX_CLKCMU_NOCL1A_NOC_BUSY, CLK_CON_MUX_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_NOCL1B_NOC0, cmucal_clkcmu_nocl1b_noc0_parents, CLK_CON_MUX_CLKCMU_NOCL1B_NOC0_SELECT, CLK_CON_MUX_CLKCMU_NOCL1B_NOC0_BUSY, CLK_CON_MUX_CLKCMU_NOCL1B_NOC0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_NOCL1C_NOC, cmucal_clkcmu_nocl1c_noc_parents, CLK_CON_MUX_CLKCMU_NOCL1C_NOC_SELECT, CLK_CON_MUX_CLKCMU_NOCL1C_NOC_BUSY, CLK_CON_MUX_CLKCMU_NOCL1C_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CP_SHARED0_CLK, cmucal_cp_shared0_clk_parents, CLK_CON_MUX_CP_SHARED0_CLK_SELECT, CLK_CON_MUX_CP_SHARED0_CLK_BUSY, CLK_CON_MUX_CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CP_SHARED2_CLK, cmucal_cp_shared2_clk_parents, CLK_CON_MUX_CP_SHARED2_CLK_SELECT, CLK_CON_MUX_CP_SHARED2_CLK_BUSY, CLK_CON_MUX_CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CP_HISPEEDY_CLK, cmucal_cp_hispeedy_clk_parents, CLK_CON_MUX_CP_HISPEEDY_CLK_SELECT, CLK_CON_MUX_CP_HISPEEDY_CLK_BUSY, CLK_CON_MUX_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_UFS_MMC_CARD, cmucal_clkcmu_ufs_mmc_card_parents, CLK_CON_MUX_CLKCMU_UFS_MMC_CARD_SELECT, CLK_CON_MUX_CLKCMU_UFS_MMC_CARD_BUSY, CLK_CON_MUX_CLKCMU_UFS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CPUCL0_CMUREF, cmucal_mux_cpucl0_cmuref_parents, CLK_CON_MUX_MUX_CPUCL0_CMUREF_SELECT, CLK_CON_MUX_MUX_CPUCL0_CMUREF_BUSY, CLK_CON_MUX_MUX_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL0_IDLECLKDOWN, cmucal_mux_clk_cpucl0_idleclkdown_parents, CLK_CON_MUX_MUX_CLK_CPUCL0_IDLECLKDOWN_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL0_IDLECLKDOWN_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_IDLECLKDOWN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL0_DELAYMUX, cmucal_mux_clk_cpucl0_delaymux_parents, CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYMUX_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYMUX_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYMUX_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL0_DELAYCHAIN, cmucal_mux_clk_cpucl0_delaychain_parents, CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYCHAIN_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYCHAIN_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_DELAYCHAIN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL0_POWERIP, cmucal_mux_clk_cpucl0_powerip_parents, CLK_CON_MUX_MUX_CLK_CPUCL0_POWERIP_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL0_POWERIP_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_POWERIP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL0_DDD, cmucal_mux_clk_cpucl0_ddd_parents, CLK_CON_MUX_MUX_CLK_CPUCL0_DDD_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL0_DDD_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_DDD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL0_HTU, cmucal_mux_clk_cpucl0_htu_parents, CLK_CON_MUX_MUX_CLK_CPUCL0_HTU_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL0_HTU_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_HTU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_IDLECLKDOWN_0, cmucal_mux_clk_cpucl1_idleclkdown_0_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_0_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_0_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CPUCL1_CMUREF, cmucal_mux_cpucl1_cmuref_parents, CLK_CON_MUX_MUX_CPUCL1_CMUREF_SELECT, CLK_CON_MUX_MUX_CPUCL1_CMUREF_BUSY, CLK_CON_MUX_MUX_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_DELAYCHAIN_0, cmucal_mux_clk_cpucl1_delaychain_0_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_0_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_0_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_DELAYMUX_0, cmucal_mux_clk_cpucl1_delaymux_0_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_0_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_0_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_POWERIP, cmucal_mux_clk_cpucl1_powerip_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_POWERIP_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_POWERIP_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_POWERIP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_DDD_0, cmucal_mux_clk_cpucl1_ddd_0_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_0_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_0_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_IDLECLKDOWN_1, cmucal_mux_clk_cpucl1_idleclkdown_1_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_1_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_1_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_DELAYMUX_1, cmucal_mux_clk_cpucl1_delaymux_1_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_1_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_1_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_DDD_1, cmucal_mux_clk_cpucl1_ddd_1_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_1_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_1_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_DELAYCHAIN_1, cmucal_mux_clk_cpucl1_delaychain_1_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_1_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_1_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_IDLECLKDOWN_2, cmucal_mux_clk_cpucl1_idleclkdown_2_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_2_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_2_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_IDLECLKDOWN_2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_DELAYMUX_2, cmucal_mux_clk_cpucl1_delaymux_2_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_2_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_2_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYMUX_2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_DDD_2, cmucal_mux_clk_cpucl1_ddd_2_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_2_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_2_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_DDD_2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_DELAYCHAIN_2, cmucal_mux_clk_cpucl1_delaychain_2_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_2_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_2_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_DELAYCHAIN_2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_HTU, cmucal_mux_clk_cpucl1_htu_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_HTU_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_HTU_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_HTU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CPUCL2_CMUREF, cmucal_mux_cpucl2_cmuref_parents, CLK_CON_MUX_MUX_CPUCL2_CMUREF_SELECT, CLK_CON_MUX_MUX_CPUCL2_CMUREF_BUSY, CLK_CON_MUX_MUX_CPUCL2_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL2_IDLECLKDOWN, cmucal_mux_clk_cpucl2_idleclkdown_parents, CLK_CON_MUX_MUX_CLK_CPUCL2_IDLECLKDOWN_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL2_IDLECLKDOWN_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL2_IDLECLKDOWN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL2_DELAYCHAIN, cmucal_mux_clk_cpucl2_delaychain_parents, CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYCHAIN_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYCHAIN_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYCHAIN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL2_DELAYMUX, cmucal_mux_clk_cpucl2_delaymux_parents, CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYMUX_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYMUX_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL2_DELAYMUX_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL2_POWERIP, cmucal_mux_clk_cpucl2_powerip_parents, CLK_CON_MUX_MUX_CLK_CPUCL2_POWERIP_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL2_POWERIP_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL2_POWERIP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL2_DDD, cmucal_mux_clk_cpucl2_ddd_parents, CLK_CON_MUX_MUX_CLK_CPUCL2_DDD_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL2_DDD_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL2_DDD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL2_HTU, cmucal_mux_clk_cpucl2_htu_parents, CLK_CON_MUX_MUX_CLK_CPUCL2_HTU_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL2_HTU_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL2_HTU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CSIS_NOC, cmucal_mux_clk_csis_noc_parents, CLK_CON_MUX_MUX_CLK_CSIS_NOC_SELECT, CLK_CON_MUX_MUX_CLK_CSIS_NOC_BUSY, CLK_CON_MUX_MUX_CLK_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CSIS_DCPHY, cmucal_mux_clk_csis_dcphy_parents, CLK_CON_MUX_MUX_CLK_CSIS_DCPHY_SELECT, CLK_CON_MUX_MUX_CLK_CSIS_DCPHY_BUSY, CLK_CON_MUX_MUX_CLK_CSIS_DCPHY_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_DNC_NOC, cmucal_mux_clk_dnc_noc_parents, CLK_CON_MUX_MUX_CLK_DNC_NOC_SELECT, CLK_CON_MUX_MUX_CLK_DNC_NOC_BUSY, CLK_CON_MUX_MUX_CLK_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_DSP_NOC, cmucal_mux_clk_dsp_noc_parents, CLK_CON_MUX_MUX_CLK_DSP_NOC_SELECT, CLK_CON_MUX_MUX_CLK_DSP_NOC_BUSY, CLK_CON_MUX_MUX_CLK_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_DSU_IDLECLKDOWN, cmucal_mux_clk_dsu_idleclkdown_parents, CLK_CON_MUX_MUX_CLK_DSU_IDLECLKDOWN_SELECT, CLK_CON_MUX_MUX_CLK_DSU_IDLECLKDOWN_BUSY, CLK_CON_MUX_MUX_CLK_DSU_IDLECLKDOWN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_DSU_CMUREF, cmucal_mux_dsu_cmuref_parents, CLK_CON_MUX_MUX_DSU_CMUREF_SELECT, CLK_CON_MUX_MUX_DSU_CMUREF_BUSY, CLK_CON_MUX_MUX_DSU_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_DSU_DELAYCHAIN, cmucal_mux_clk_dsu_delaychain_parents, CLK_CON_MUX_MUX_CLK_DSU_DELAYCHAIN_SELECT, CLK_CON_MUX_MUX_CLK_DSU_DELAYCHAIN_BUSY, CLK_CON_MUX_MUX_CLK_DSU_DELAYCHAIN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_DSU_DELAYMUX, cmucal_mux_clk_dsu_delaymux_parents, CLK_CON_MUX_MUX_CLK_DSU_DELAYMUX_SELECT, CLK_CON_MUX_MUX_CLK_DSU_DELAYMUX_BUSY, CLK_CON_MUX_MUX_CLK_DSU_DELAYMUX_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_DSU_POWERIP, cmucal_mux_clk_dsu_powerip_parents, CLK_CON_MUX_MUX_CLK_DSU_POWERIP_SELECT, CLK_CON_MUX_MUX_CLK_DSU_POWERIP_BUSY, CLK_CON_MUX_MUX_CLK_DSU_POWERIP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_DSU_DDD, cmucal_mux_clk_dsu_ddd_parents, CLK_CON_MUX_MUX_CLK_DSU_DDD_SELECT, CLK_CON_MUX_MUX_CLK_DSU_DDD_BUSY, CLK_CON_MUX_MUX_CLK_DSU_DDD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_DSU_HTU, cmucal_mux_clk_dsu_htu_parents, CLK_CON_MUX_MUX_CLK_DSU_HTU_SELECT, CLK_CON_MUX_MUX_CLK_DSU_HTU_BUSY, CLK_CON_MUX_MUX_CLK_DSU_HTU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_G3D_CORE, cmucal_mux_clk_g3d_core_parents, CLK_CON_MUX_MUX_CLK_G3D_CORE_SELECT, CLK_CON_MUX_MUX_CLK_G3D_CORE_BUSY, CLK_CON_MUX_MUX_CLK_G3D_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_G3D_DDD, cmucal_mux_clk_g3d_ddd_parents, CLK_CON_MUX_MUX_CLK_G3D_DDD_SELECT, CLK_CON_MUX_MUX_CLK_G3D_DDD_BUSY, CLK_CON_MUX_MUX_CLK_G3D_DDD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_G3D_DELAYCHAIN, cmucal_mux_clk_g3d_delaychain_parents, CLK_CON_MUX_MUX_CLK_G3D_DELAYCHAIN_SELECT, CLK_CON_MUX_MUX_CLK_G3D_DELAYCHAIN_BUSY, CLK_CON_MUX_MUX_CLK_G3D_DELAYCHAIN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_G3D_DELAYMUX, cmucal_mux_clk_g3d_delaymux_parents, CLK_CON_MUX_MUX_CLK_G3D_DELAYMUX_SELECT, CLK_CON_MUX_MUX_CLK_G3D_DELAYMUX_BUSY, CLK_CON_MUX_MUX_CLK_G3D_DELAYMUX_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_G3D_PLL, cmucal_mux_clk_g3d_pll_parents, CLK_CON_MUX_MUX_CLK_G3D_PLL_SELECT, CLK_CON_MUX_MUX_CLK_G3D_PLL_BUSY, CLK_CON_MUX_MUX_CLK_G3D_PLL_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_GNPU_NOC, cmucal_mux_clk_gnpu_noc_parents, CLK_CON_MUX_MUX_CLK_GNPU_NOC_SELECT, CLK_CON_MUX_MUX_CLK_GNPU_NOC_BUSY, CLK_CON_MUX_MUX_CLK_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_HSI0_USB32DRD, cmucal_mux_clk_hsi0_usb32drd_parents, CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD_SELECT, CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD_BUSY, CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_HSI0_NOC, cmucal_mux_clk_hsi0_noc_parents, CLK_CON_MUX_MUX_CLK_HSI0_NOC_SELECT, CLK_CON_MUX_MUX_CLK_HSI0_NOC_BUSY, CLK_CON_MUX_MUX_CLK_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_HSI0_RTCCLK, cmucal_mux_clk_hsi0_rtcclk_parents, CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK_SELECT, CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK_BUSY, CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_MIF_CMUREF, cmucal_mux_mif_cmuref_parents, CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_NOCL0_CMUREF, cmucal_mux_nocl0_cmuref_parents, CLK_CON_MUX_MUX_NOCL0_CMUREF_SELECT, CLK_CON_MUX_MUX_NOCL0_CMUREF_BUSY, CLK_CON_MUX_MUX_NOCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_NOCL1A_CMUREF, cmucal_mux_nocl1a_cmuref_parents, CLK_CON_MUX_MUX_NOCL1A_CMUREF_SELECT, CLK_CON_MUX_MUX_NOCL1A_CMUREF_BUSY, CLK_CON_MUX_MUX_NOCL1A_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_NOCL1B_CMUREF, cmucal_mux_nocl1b_cmuref_parents, CLK_CON_MUX_MUX_NOCL1B_CMUREF_SELECT, CLK_CON_MUX_MUX_NOCL1B_CMUREF_BUSY, CLK_CON_MUX_MUX_NOCL1B_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_NOCL1C_CMUREF, cmucal_mux_nocl1c_cmuref_parents, CLK_CON_MUX_MUX_NOCL1C_CMUREF_SELECT, CLK_CON_MUX_MUX_NOCL1C_CMUREF_BUSY, CLK_CON_MUX_MUX_NOCL1C_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC0_USI04, cmucal_mux_clk_peric0_usi04_parents, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_SELECT, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_BUSY, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC0_I2C, cmucal_mux_clk_peric0_i2c_parents, CLK_CON_MUX_MUX_CLK_PERIC0_I2C_SELECT, CLK_CON_MUX_MUX_CLK_PERIC0_I2C_BUSY, CLK_CON_MUX_MUX_CLK_PERIC0_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC1_UART_BT, cmucal_mux_clk_peric1_uart_bt_parents, CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT_SELECT, CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT_BUSY, CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC1_I2C, cmucal_mux_clk_peric1_i2c_parents, CLK_CON_MUX_MUX_CLK_PERIC1_I2C_SELECT, CLK_CON_MUX_MUX_CLK_PERIC1_I2C_BUSY, CLK_CON_MUX_MUX_CLK_PERIC1_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC1_USI07, cmucal_mux_clk_peric1_usi07_parents, CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SELECT, CLK_CON_MUX_MUX_CLK_PERIC1_USI07_BUSY, CLK_CON_MUX_MUX_CLK_PERIC1_USI07_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC1_USI08, cmucal_mux_clk_peric1_usi08_parents, CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SELECT, CLK_CON_MUX_MUX_CLK_PERIC1_USI08_BUSY, CLK_CON_MUX_MUX_CLK_PERIC1_USI08_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC1_USI09, cmucal_mux_clk_peric1_usi09_parents, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_SELECT, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_BUSY, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC1_USI10, cmucal_mux_clk_peric1_usi10_parents, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_SELECT, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_BUSY, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC1_SPI_MS_CTRL, cmucal_mux_clk_peric1_spi_ms_ctrl_parents, CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL_SELECT, CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL_BUSY, CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC1_USI07_SPI_I2C, cmucal_mux_clk_peric1_usi07_spi_i2c_parents, CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C_SELECT, CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C_BUSY, CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC1_USI08_SPI_I2C, cmucal_mux_clk_peric1_usi08_spi_i2c_parents, CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C_SELECT, CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C_BUSY, CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC2_I2C, cmucal_mux_clk_peric2_i2c_parents, CLK_CON_MUX_MUX_CLK_PERIC2_I2C_SELECT, CLK_CON_MUX_MUX_CLK_PERIC2_I2C_BUSY, CLK_CON_MUX_MUX_CLK_PERIC2_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC2_USI00, cmucal_mux_clk_peric2_usi00_parents, CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SELECT, CLK_CON_MUX_MUX_CLK_PERIC2_USI00_BUSY, CLK_CON_MUX_MUX_CLK_PERIC2_USI00_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC2_USI01, cmucal_mux_clk_peric2_usi01_parents, CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SELECT, CLK_CON_MUX_MUX_CLK_PERIC2_USI01_BUSY, CLK_CON_MUX_MUX_CLK_PERIC2_USI01_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC2_USI02, cmucal_mux_clk_peric2_usi02_parents, CLK_CON_MUX_MUX_CLK_PERIC2_USI02_SELECT, CLK_CON_MUX_MUX_CLK_PERIC2_USI02_BUSY, CLK_CON_MUX_MUX_CLK_PERIC2_USI02_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC2_USI03, cmucal_mux_clk_peric2_usi03_parents, CLK_CON_MUX_MUX_CLK_PERIC2_USI03_SELECT, CLK_CON_MUX_MUX_CLK_PERIC2_USI03_BUSY, CLK_CON_MUX_MUX_CLK_PERIC2_USI03_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC2_USI05, cmucal_mux_clk_peric2_usi05_parents, CLK_CON_MUX_MUX_CLK_PERIC2_USI05_SELECT, CLK_CON_MUX_MUX_CLK_PERIC2_USI05_BUSY, CLK_CON_MUX_MUX_CLK_PERIC2_USI05_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC2_USI06, cmucal_mux_clk_peric2_usi06_parents, CLK_CON_MUX_MUX_CLK_PERIC2_USI06_SELECT, CLK_CON_MUX_MUX_CLK_PERIC2_USI06_BUSY, CLK_CON_MUX_MUX_CLK_PERIC2_USI06_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC2_SPI_MS_CTRL, cmucal_mux_clk_peric2_spi_ms_ctrl_parents, CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL_SELECT, CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL_BUSY, CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC2_USI11, cmucal_mux_clk_peric2_usi11_parents, CLK_CON_MUX_MUX_CLK_PERIC2_USI11_SELECT, CLK_CON_MUX_MUX_CLK_PERIC2_USI11_BUSY, CLK_CON_MUX_MUX_CLK_PERIC2_USI11_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC2_UART_DBG, cmucal_mux_clk_peric2_uart_dbg_parents, CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG_SELECT, CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG_BUSY, CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC2_USI00_SPI_I2C, cmucal_mux_clk_peric2_usi00_spi_i2c_parents, CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C_SELECT, CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C_BUSY, CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIC2_USI01_SPI_I2C, cmucal_mux_clk_peric2_usi01_spi_i2c_parents, CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C_SELECT, CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C_BUSY, CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_S2D_CORE, cmucal_mux_clk_s2d_core_parents, CLK_CON_MUX_MUX_CLK_S2D_CORE_SELECT, CLK_CON_MUX_MUX_CLK_S2D_CORE_BUSY, CLK_CON_MUX_MUX_CLK_S2D_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_SDMA_NOC, cmucal_mux_clk_sdma_noc_parents, CLK_CON_MUX_MUX_CLK_SDMA_NOC_SELECT, CLK_CON_MUX_MUX_CLK_SDMA_NOC_BUSY, CLK_CON_MUX_MUX_CLK_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_UFD_NOC, cmucal_mux_clk_ufd_noc_parents, CLK_CON_MUX_MUX_CLK_UFD_NOC_SELECT, CLK_CON_MUX_MUX_CLK_UFD_NOC_BUSY, CLK_CON_MUX_MUX_CLK_UFD_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_VTS_DMIC_PAD, cmucal_mux_clk_vts_dmic_pad_parents, CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD_SELECT, CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD_BUSY, CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKVTS_AUD_DMIC1, cmucal_mux_clkvts_aud_dmic1_parents, CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1_SELECT, CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1_BUSY, CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_VTS_NOC, cmucal_mux_clk_vts_noc_parents, CLK_CON_MUX_MUX_CLK_VTS_NOC_SELECT, CLK_CON_MUX_MUX_CLK_VTS_NOC_BUSY, CLK_CON_MUX_MUX_CLK_VTS_NOC_ENABLE_AUTOMATIC_CLKGATING),
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|
CLK_MUX(ALIVE_CMU_ALIVE_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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|
CLK_MUX(ALLCSIS_CMU_ALLCSIS_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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|
CLK_MUX(AUD_CMU_AUD_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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|
CLK_MUX(BRP_CMU_BRP_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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|
CLK_MUX(CHUB_CMU_CHUB_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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|
CLK_MUX(CHUBVTS_CMU_CHUBVTS_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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|
CLK_MUX(CMGP_CMU_CMGP_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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|
CLK_MUX(CMU_CMU_TOP_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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|
CLK_MUX(CPUCL0_CMU_CPUCL0_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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|
CLK_MUX(CPUCL0_GLB_CMU_CPUCL0_GLB_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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|
CLK_MUX(CPUCL1_CMU_CPUCL1_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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|
CLK_MUX(CPUCL2_CMU_CPUCL2_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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|
CLK_MUX(CSIS_CMU_CSIS_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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|
CLK_MUX(CSTAT_CMU_CSTAT_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
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|
CLK_MUX(DBGCORE_CMU_DBGCORE_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(DNC_CMU_DNC_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(DPUB_CMU_DPUB_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(DPUF_CMU_DPUF_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(DPUF1_CMU_DPUF1_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(DRCP_CMU_DRCP_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(DSP_CMU_DSP_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(DSU_CMU_DSU_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(G3D_CMU_G3D_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(G3DCORE_CMU_G3DCORE_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(GNPU_CMU_GNPU_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(HSI0_CMU_HSI0_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(HSI1_CMU_HSI1_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(LME_CMU_LME_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(M2M_CMU_M2M_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(MCSC_CMU_MCSC_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(MFC0_CMU_MFC0_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(MFC1_CMU_MFC1_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(MIF_CMU_MIF_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(NOCL0_CMU_NOCL0_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(NOCL1A_CMU_NOCL1A_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(NOCL1B_CMU_NOCL1B_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(NOCL1C_CMU_NOCL1C_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(PERIC0_CMU_PERIC0_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(PERIC1_CMU_PERIC1_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(PERIC2_CMU_PERIC2_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(PERIS_CMU_PERIS_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(SDMA_CMU_SDMA_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(SSP_CMU_SSP_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(STRONG_CMU_STRONG_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(UFD_CMU_UFD_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(UFS_CMU_UFS_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(VTS_CMU_VTS_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(YUVP_CMU_YUVP_CLKOUT, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
|
|
CLK_MUX(MUX_CLKCMU_ALIVE_NOC_USER, cmucal_mux_clkcmu_alive_noc_user_parents, PLL_CON0_MUX_CLKCMU_ALIVE_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ALIVE_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_ALIVE_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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|
CLK_MUX(MUX_CLK_RCO_ALIVE_USER, cmucal_mux_clk_rco_alive_user_parents, PLL_CON0_MUX_CLK_RCO_ALIVE_USER_MUX_SEL, PLL_CON0_MUX_CLK_RCO_ALIVE_USER_BUSY, PLL_CON1_MUX_CLK_RCO_ALIVE_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKMUX_ALIVE_RCO_SPMI_USER, cmucal_mux_clkmux_alive_rco_spmi_user_parents, PLL_CON0_MUX_CLKMUX_ALIVE_RCO_SPMI_USER_MUX_SEL, PLL_CON0_MUX_CLKMUX_ALIVE_RCO_SPMI_USER_BUSY, PLL_CON1_MUX_CLKMUX_ALIVE_RCO_SPMI_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_AUD_CPU_USER, cmucal_mux_clkcmu_aud_cpu_user_parents, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_BUSY, PLL_CON1_MUX_CLKCMU_AUD_CPU_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_AUD_NOC_USER, cmucal_mux_clkcmu_aud_noc_user_parents, PLL_CON0_MUX_CLKCMU_AUD_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_AUD_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_AUD_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CP_PCMC_CLK_USER, cmucal_mux_cp_pcmc_clk_user_parents, PLL_CON0_MUX_CP_PCMC_CLK_USER_MUX_SEL, PLL_CON0_MUX_CP_PCMC_CLK_USER_BUSY, PLL_CON1_MUX_CP_PCMC_CLK_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLK_AUD_RCO_USER, cmucal_mux_clk_aud_rco_user_parents, PLL_CON0_MUX_CLK_AUD_RCO_USER_MUX_SEL, PLL_CON0_MUX_CLK_AUD_RCO_USER_BUSY, PLL_CON1_MUX_CLK_AUD_RCO_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_AUD_AUDIF0_USER, cmucal_mux_clkcmu_aud_audif0_user_parents, PLL_CON0_MUX_CLKCMU_AUD_AUDIF0_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_AUD_AUDIF0_USER_BUSY, PLL_CON1_MUX_CLKCMU_AUD_AUDIF0_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_AUD_AUDIF1_USER, cmucal_mux_clkcmu_aud_audif1_user_parents, PLL_CON0_MUX_CLKCMU_AUD_AUDIF1_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_AUD_AUDIF1_USER_BUSY, PLL_CON1_MUX_CLKCMU_AUD_AUDIF1_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKVTS_AUD_DMIC0_USER, cmucal_mux_clkvts_aud_dmic0_user_parents, PLL_CON0_MUX_CLKVTS_AUD_DMIC0_USER_MUX_SEL, PLL_CON0_MUX_CLKVTS_AUD_DMIC0_USER_BUSY, PLL_CON1_MUX_CLKVTS_AUD_DMIC0_USER_ENABLE_AUTOMATIC_CLKGATING),
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|
CLK_MUX(MUX_CLKVTS_AUD_DMIC1_USER, cmucal_mux_clkvts_aud_dmic1_user_parents, PLL_CON0_MUX_CLKVTS_AUD_DMIC1_USER_MUX_SEL, PLL_CON0_MUX_CLKVTS_AUD_DMIC1_USER_BUSY, PLL_CON1_MUX_CLKVTS_AUD_DMIC1_USER_ENABLE_AUTOMATIC_CLKGATING),
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|
CLK_MUX(MUX_CLKCMU_BRP_NOC_USER, cmucal_mux_clkcmu_brp_noc_user_parents, PLL_CON0_MUX_CLKCMU_BRP_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_BRP_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_BRP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_CHUB_NOC_USER, cmucal_mux_clkalive_chub_noc_user_parents, PLL_CON0_MUX_CLKALIVE_CHUB_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_CHUB_NOC_USER_BUSY, PLL_CON1_MUX_CLKALIVE_CHUB_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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|
CLK_MUX(MUX_CLKALIVE_CHUB_PERI_USER, cmucal_mux_clkalive_chub_peri_user_parents, PLL_CON0_MUX_CLKALIVE_CHUB_PERI_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_CHUB_PERI_USER_BUSY, PLL_CON1_MUX_CLKALIVE_CHUB_PERI_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_CHUB_RCO_USER, cmucal_mux_clkalive_chub_rco_user_parents, PLL_CON0_MUX_CLKALIVE_CHUB_RCO_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_CHUB_RCO_USER_BUSY, PLL_CON1_MUX_CLKALIVE_CHUB_RCO_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_CHUBVTS_NOC_USER, cmucal_mux_clkalive_chubvts_noc_user_parents, PLL_CON0_MUX_CLKALIVE_CHUBVTS_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_CHUBVTS_NOC_USER_BUSY, PLL_CON1_MUX_CLKALIVE_CHUBVTS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_CHUBVTS_RCO_USER, cmucal_mux_clkalive_chubvts_rco_user_parents, PLL_CON0_MUX_CLKALIVE_CHUBVTS_RCO_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_CHUBVTS_RCO_USER_BUSY, PLL_CON1_MUX_CLKALIVE_CHUBVTS_RCO_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_CMGP_NOC_USER, cmucal_mux_clkalive_cmgp_noc_user_parents, PLL_CON0_MUX_CLKALIVE_CMGP_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_CMGP_NOC_USER_BUSY, PLL_CON1_MUX_CLKALIVE_CMGP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_CMGP_PERI_USER, cmucal_mux_clkalive_cmgp_peri_user_parents, PLL_CON0_MUX_CLKALIVE_CMGP_PERI_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_CMGP_PERI_USER_BUSY, PLL_CON1_MUX_CLKALIVE_CMGP_PERI_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CP_MPLL_CLK_USER, cmucal_mux_cp_mpll_clk_user_parents, PLL_CON0_MUX_CP_MPLL_CLK_USER_MUX_SEL, PLL_CON0_MUX_CP_MPLL_CLK_USER_BUSY, PLL_CON1_MUX_CP_MPLL_CLK_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CP_MPLL_CLK_D2_USER, cmucal_mux_cp_mpll_clk_d2_user_parents, PLL_CON0_MUX_CP_MPLL_CLK_D2_USER_MUX_SEL, PLL_CON0_MUX_CP_MPLL_CLK_D2_USER_BUSY, PLL_CON1_MUX_CP_MPLL_CLK_D2_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_CPUCL0_SWITCH_USER, cmucal_mux_clkcmu_cpucl0_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_CPUCL0_DBG_NOC_USER, cmucal_mux_clkcmu_cpucl0_dbg_noc_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, cmucal_mux_clkcmu_cpucl0_glb_nocp_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_GLB_NOCP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_GLB_NOCP_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL0_GLB_NOCP_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_CPUCL1_SWITCH_USER, cmucal_mux_clkcmu_cpucl1_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_CPUCL2_SWITCH_USER, cmucal_mux_clkcmu_cpucl2_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_CSIS_DCPHY_USER, cmucal_mux_clkcmu_csis_dcphy_user_parents, PLL_CON0_MUX_CLKCMU_CSIS_DCPHY_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CSIS_DCPHY_USER_BUSY, PLL_CON1_MUX_CLKCMU_CSIS_DCPHY_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_CSIS_RCO_USER, cmucal_mux_clkalive_csis_rco_user_parents, PLL_CON0_MUX_CLKALIVE_CSIS_RCO_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_CSIS_RCO_USER_BUSY, PLL_CON1_MUX_CLKALIVE_CSIS_RCO_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_CSIS_NOC_USER, cmucal_mux_clkcmu_csis_noc_user_parents, PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_CSIS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_CSIS_NOC_USER, cmucal_mux_clkalive_csis_noc_user_parents, PLL_CON0_MUX_CLKALIVE_CSIS_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_CSIS_NOC_USER_BUSY, PLL_CON1_MUX_CLKALIVE_CSIS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_CSIS_OIS_MCU_USER, cmucal_mux_clkcmu_csis_ois_mcu_user_parents, PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CSIS_OIS_MCU_USER_BUSY, PLL_CON1_MUX_CLKCMU_CSIS_OIS_MCU_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_CSTAT_NOC_USER, cmucal_mux_clkcmu_cstat_noc_user_parents, PLL_CON0_MUX_CLKCMU_CSTAT_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CSTAT_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_CSTAT_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_DBGCORE_NOC_USER, cmucal_mux_clkalive_dbgcore_noc_user_parents, PLL_CON0_MUX_CLKALIVE_DBGCORE_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_DBGCORE_NOC_USER_BUSY, PLL_CON1_MUX_CLKALIVE_DBGCORE_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_DNC_NOC_USER, cmucal_mux_clkcmu_dnc_noc_user_parents, PLL_CON0_MUX_CLKCMU_DNC_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DNC_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_DNC_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_DNC_RCO_USER, cmucal_mux_clkalive_dnc_rco_user_parents, PLL_CON0_MUX_CLKALIVE_DNC_RCO_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_DNC_RCO_USER_BUSY, PLL_CON1_MUX_CLKALIVE_DNC_RCO_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_DNC_NOC_USER, cmucal_mux_clkalive_dnc_noc_user_parents, PLL_CON0_MUX_CLKALIVE_DNC_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_DNC_NOC_USER_BUSY, PLL_CON1_MUX_CLKALIVE_DNC_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_DPUB_NOC_USER, cmucal_mux_clkcmu_dpub_noc_user_parents, PLL_CON0_MUX_CLKCMU_DPUB_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DPUB_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_DPUB_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_DPUB_DSIM_USER, cmucal_mux_clkcmu_dpub_dsim_user_parents, PLL_CON0_MUX_CLKCMU_DPUB_DSIM_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DPUB_DSIM_USER_BUSY, PLL_CON1_MUX_CLKCMU_DPUB_DSIM_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_DPUF_NOC_USER, cmucal_mux_clkcmu_dpuf_noc_user_parents, PLL_CON0_MUX_CLKCMU_DPUF_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DPUF_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_DPUF_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_DPUF1_NOC_USER, cmucal_mux_clkcmu_dpuf1_noc_user_parents, PLL_CON0_MUX_CLKCMU_DPUF1_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DPUF1_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_DPUF1_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_DRCP_NOC_USER, cmucal_mux_clkcmu_drcp_noc_user_parents, PLL_CON0_MUX_CLKCMU_DRCP_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DRCP_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_DRCP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_DSP_NOC_USER, cmucal_mux_clkcmu_dsp_noc_user_parents, PLL_CON0_MUX_CLKCMU_DSP_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DSP_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_DSP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_SDMA_RCO_USER_CPY, cmucal_mux_clkalive_sdma_rco_user_cpy_parents, PLL_CON0_MUX_CLKALIVE_DSP_RCO_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_DSP_RCO_USER_BUSY, PLL_CON1_MUX_CLKALIVE_DSP_RCO_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_SDMA_NOC_USER_CPY, cmucal_mux_clkalive_sdma_noc_user_cpy_parents, PLL_CON0_MUX_CLKALIVE_DSP_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_DSP_NOC_USER_BUSY, PLL_CON1_MUX_CLKALIVE_DSP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_DSU_SWITCH_USER, cmucal_mux_clkcmu_dsu_switch_user_parents, PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_G3D_NOCP_USER, cmucal_mux_clkcmu_g3d_nocp_user_parents, PLL_CON0_MUX_CLKCMU_G3D_NOCP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G3D_NOCP_USER_BUSY, PLL_CON1_MUX_CLKCMU_G3D_NOCP_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_G3D_SWITCH_USER, cmucal_mux_clkcmu_g3d_switch_user_parents, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_G3D_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKCMU_GNPU_NOC_USER, cmucal_mux_clkcmu_gnpu_noc_user_parents, PLL_CON0_MUX_CLKCMU_GNPU_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_GNPU_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_GNPU_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
|
|
CLK_MUX(MUX_CLKALIVE_GNPU_NOC_USER, cmucal_mux_clkalive_gnpu_noc_user_parents, PLL_CON0_MUX_CLKALIVE_GNPU_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_GNPU_NOC_USER_BUSY, PLL_CON1_MUX_CLKALIVE_GNPU_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKALIVE_GNPU_RCO_USER, cmucal_mux_clkalive_gnpu_rco_user_parents, PLL_CON0_MUX_CLKALIVE_GNPU_RCO_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_GNPU_RCO_USER_BUSY, PLL_CON1_MUX_CLKALIVE_GNPU_RCO_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI0_DPOSC_USER, cmucal_mux_clkcmu_hsi0_dposc_user_parents, PLL_CON0_MUX_CLKCMU_HSI0_DPOSC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI0_DPOSC_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI0_DPOSC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI0_NOC_USER, cmucal_mux_clkcmu_hsi0_noc_user_parents, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI0_USB32DRD_USER, cmucal_mux_clkcmu_hsi0_usb32drd_user_parents, PLL_CON0_MUX_CLKCMU_HSI0_USB32DRD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI0_USB32DRD_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI0_USB32DRD_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI0_DPGTC_USER, cmucal_mux_clkcmu_hsi0_dpgtc_user_parents, PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKAUD_HSI0_NOC_USER, cmucal_mux_clkaud_hsi0_noc_user_parents, PLL_CON0_MUX_CLKAUD_HSI0_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKAUD_HSI0_NOC_USER_BUSY, PLL_CON1_MUX_CLKAUD_HSI0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI1_NOC_USER, cmucal_mux_clkcmu_hsi1_noc_user_parents, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI1_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_HSI1_PCIE_USER, cmucal_mux_clkcmu_hsi1_pcie_user_parents, PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_LME_NOC_USER, cmucal_mux_clkcmu_lme_noc_user_parents, PLL_CON0_MUX_CLKCMU_LME_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_LME_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_LME_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_LME_LME_USER, cmucal_mux_clkcmu_lme_lme_user_parents, PLL_CON0_MUX_CLKCMU_LME_LME_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_LME_LME_USER_BUSY, PLL_CON1_MUX_CLKCMU_LME_LME_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_M2M_NOC_USER, cmucal_mux_clkcmu_m2m_noc_user_parents, PLL_CON0_MUX_CLKCMU_M2M_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_M2M_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_M2M_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_M2M_FRC_USER, cmucal_mux_clkcmu_m2m_frc_user_parents, PLL_CON0_MUX_CLKCMU_M2M_FRC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_M2M_FRC_USER_BUSY, PLL_CON1_MUX_CLKCMU_M2M_FRC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MCSC_NOC_USER, cmucal_mux_clkcmu_mcsc_noc_user_parents, PLL_CON0_MUX_CLKCMU_MCSC_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MCSC_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_MCSC_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MCSC_MCSC_USER, cmucal_mux_clkcmu_mcsc_mcsc_user_parents, PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER_BUSY, PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MFC0_MFC0_USER, cmucal_mux_clkcmu_mfc0_mfc0_user_parents, PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFC0_MFC0_USER_BUSY, PLL_CON1_MUX_CLKCMU_MFC0_MFC0_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MFC0_WFD_USER, cmucal_mux_clkcmu_mfc0_wfd_user_parents, PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFC0_WFD_USER_BUSY, PLL_CON1_MUX_CLKCMU_MFC0_WFD_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MFC1_MFC1_USER, cmucal_mux_clkcmu_mfc1_mfc1_user_parents, PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFC1_MFC1_USER_BUSY, PLL_CON1_MUX_CLKCMU_MFC1_MFC1_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_MIF_NOCP_USER, cmucal_mux_clkcmu_mif_nocp_user_parents, PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER_BUSY, PLL_CON1_MUX_CLKCMU_MIF_NOCP_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKMUX_MIF_DDRPHY2X, cmucal_clkmux_mif_ddrphy2x_parents, PLL_CON0_CLKMUX_MIF_DDRPHY2X_MUX_SEL, PLL_CON0_CLKMUX_MIF_DDRPHY2X_BUSY, PLL_CON1_CLKMUX_MIF_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_NOCL0_NOC_USER, cmucal_mux_clkcmu_nocl0_noc_user_parents, PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_NOCL0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_NOCL1A_NOC_USER, cmucal_mux_clkcmu_nocl1a_noc_user_parents, PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_NOCL1A_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_NOCL1B_NOC0_USER, cmucal_mux_clkcmu_nocl1b_noc0_user_parents, PLL_CON0_MUX_CLKCMU_NOCL1B_NOC0_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_NOCL1B_NOC0_USER_BUSY, PLL_CON1_MUX_CLKCMU_NOCL1B_NOC0_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_NOCL1B_NOC1_USER, cmucal_mux_clkcmu_nocl1b_noc1_user_parents, PLL_CON0_MUX_CLKCMU_NOCL1B_NOC1_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_NOCL1B_NOC1_USER_BUSY, PLL_CON1_MUX_CLKCMU_NOCL1B_NOC1_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_NOCL1C_NOC_USER, cmucal_mux_clkcmu_nocl1c_noc_user_parents, PLL_CON0_MUX_CLKCMU_NOCL1C_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_NOCL1C_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_NOCL1C_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC0_NOC_USER, cmucal_mux_clkcmu_peric0_noc_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC0_IP0_USER, cmucal_mux_clkcmu_peric0_ip0_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC0_IP0_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC0_IP1_USER, cmucal_mux_clkcmu_peric0_ip1_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC0_IP1_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC1_NOC_USER, cmucal_mux_clkcmu_peric1_noc_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC1_IP0_USER, cmucal_mux_clkcmu_peric1_ip0_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC1_IP0_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC1_IP1_USER, cmucal_mux_clkcmu_peric1_ip1_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC1_IP1_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC2_IP0_USER, cmucal_mux_clkcmu_peric2_ip0_user_parents, PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC2_IP0_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC2_IP1_USER, cmucal_mux_clkcmu_peric2_ip1_user_parents, PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC2_IP1_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIC2_NOC_USER, cmucal_mux_clkcmu_peric2_noc_user_parents, PLL_CON0_MUX_CLKCMU_PERIC2_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC2_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC2_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIS_NOC_USER, cmucal_mux_clkcmu_peris_noc_user_parents, PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_PERIS_GIC_USER, cmucal_mux_clkcmu_peris_gic_user_parents, PLL_CON0_MUX_CLKCMU_PERIS_GIC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIS_GIC_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIS_GIC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(CLKCMU_MIF_DDRPHY2X_S2D, cmucal_clkcmu_mif_ddrphy2x_s2d_parents, PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_MUX_SEL, PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_BUSY, PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_SDMA_NOC_USER, cmucal_mux_clkcmu_sdma_noc_user_parents, PLL_CON0_MUX_CLKCMU_SDMA_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_SDMA_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_SDMA_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKALIVE_SDMA_RCO_USER, cmucal_mux_clkalive_sdma_rco_user_parents, PLL_CON0_MUX_CLKALIVE_SDMA_RCO_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_SDMA_RCO_USER_BUSY, PLL_CON1_MUX_CLKALIVE_SDMA_RCO_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKALIVE_SDMA_NOC_USER, cmucal_mux_clkalive_sdma_noc_user_parents, PLL_CON0_MUX_CLKALIVE_SDMA_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_SDMA_NOC_USER_BUSY, PLL_CON1_MUX_CLKALIVE_SDMA_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_SSP_NOC_USER, cmucal_mux_clkcmu_ssp_noc_user_parents, PLL_CON0_MUX_CLKCMU_SSP_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_SSP_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_SSP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKALIVE_UFD_NOC_USER, cmucal_mux_clkalive_ufd_noc_user_parents, PLL_CON0_MUX_CLKALIVE_UFD_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_UFD_NOC_USER_BUSY, PLL_CON1_MUX_CLKALIVE_UFD_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKALIVE_UFD_RCO_USER, cmucal_mux_clkalive_ufd_rco_user_parents, PLL_CON0_MUX_CLKALIVE_UFD_RCO_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_UFD_RCO_USER_BUSY, PLL_CON1_MUX_CLKALIVE_UFD_RCO_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_UFS_UFS_EMBD_USER, cmucal_mux_clkcmu_ufs_ufs_embd_user_parents, PLL_CON0_MUX_CLKCMU_UFS_UFS_EMBD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_UFS_UFS_EMBD_USER_BUSY, PLL_CON1_MUX_CLKCMU_UFS_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_UFS_NOC_USER, cmucal_mux_clkcmu_ufs_noc_user_parents, PLL_CON0_MUX_CLKCMU_UFS_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_UFS_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_UFS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_UFS_MMC_CARD_USER, cmucal_mux_clkcmu_ufs_mmc_card_user_parents, PLL_CON0_MUX_CLKCMU_UFS_MMC_CARD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_UFS_MMC_CARD_USER_BUSY, PLL_CON1_MUX_CLKCMU_UFS_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKALIVE_VTS_NOC_USER, cmucal_mux_clkalive_vts_noc_user_parents, PLL_CON0_MUX_CLKALIVE_VTS_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_VTS_NOC_USER_BUSY, PLL_CON1_MUX_CLKALIVE_VTS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_VTS_DMIC_USER, cmucal_mux_clkcmu_vts_dmic_user_parents, PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER_BUSY, PLL_CON1_MUX_CLKCMU_VTS_DMIC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKALIVE_VTS_RCO_USER, cmucal_mux_clkalive_vts_rco_user_parents, PLL_CON0_MUX_CLKALIVE_VTS_RCO_USER_MUX_SEL, PLL_CON0_MUX_CLKALIVE_VTS_RCO_USER_BUSY, PLL_CON1_MUX_CLKALIVE_VTS_RCO_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLKCMU_YUVP_NOC_USER, cmucal_mux_clkcmu_yuvp_noc_user_parents, PLL_CON0_MUX_CLKCMU_YUVP_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_YUVP_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_YUVP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_HCHGEN_CLK_AUD_CPU, cmucal_mux_hchgen_clk_aud_cpu_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_BUSY, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL0_STRMUX, cmucal_mux_clk_cpucl0_strmux_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_CLK_CPUCL0_STRMUX_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_STRMUX_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_STRMUX_0, cmucal_mux_clk_cpucl1_strmux_0_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_0_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_STRMUX_1, cmucal_mux_clk_cpucl1_strmux_1_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_1_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL1_STRMUX_2, cmucal_mux_clk_cpucl1_strmux_2_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_2_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_STRMUX_2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_CPUCL2_STRMUX, cmucal_mux_clk_cpucl2_strmux_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_CLK_CPUCL2_STRMUX_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL2_STRMUX_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_DBGCORE_NOC, cmucal_mux_clk_dbgcore_noc_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_CLK_DBGCORE_NOC_BUSY, CLK_CON_MUX_MUX_CLK_DBGCORE_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_OSCCLK_DBGCORE, cmucal_mux_oscclk_dbgcore_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_OSCCLK_DBGCORE_BUSY, CLK_CON_MUX_MUX_OSCCLK_DBGCORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_FREE_OSCCLK_DBGCORE, cmucal_mux_free_oscclk_dbgcore_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_FREE_OSCCLK_DBGCORE_BUSY, CLK_CON_MUX_MUX_FREE_OSCCLK_DBGCORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_DSU_STRMUX, cmucal_mux_clk_dsu_strmux_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_CLK_DSU_STRMUX_BUSY, CLK_CON_MUX_MUX_CLK_DSU_STRMUX_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_G3D_STRMUX, cmucal_mux_clk_g3d_strmux_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_CLK_G3D_STRMUX_BUSY, CLK_CON_MUX_MUX_CLK_G3D_STRMUX_ENABLE_AUTOMATIC_CLKGATING),
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CLK_MUX(MUX_CLK_PERIS_GIC, cmucal_mux_clk_peris_gic_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_CLK_PERIS_GIC_BUSY, CLK_CON_MUX_MUX_CLK_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING),
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};
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unsigned int cmucal_div_size = 254;
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struct cmucal_div cmucal_div_list[] = {
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CLK_DIV(CLKALIVE_UFD_NOC, GATE_CLKALIVE_UFD_NOC, CLK_CON_DIV_CLKALIVE_UFD_NOC_DIVRATIO, CLK_CON_DIV_CLKALIVE_UFD_NOC_BUSY, CLK_CON_DIV_CLKALIVE_UFD_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_ALIVE_NOC, MUX_CLK_ALIVE_NOC, CLK_CON_DIV_DIV_CLK_ALIVE_NOC_DIVRATIO, CLK_CON_DIV_DIV_CLK_ALIVE_NOC_BUSY, CLK_CON_DIV_DIV_CLK_ALIVE_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKALIVE_CMGP_NOC, GATE_CLKALIVE_CMGP_NOC, CLK_CON_DIV_CLKALIVE_CMGP_NOC_DIVRATIO, CLK_CON_DIV_CLKALIVE_CMGP_NOC_BUSY, CLK_CON_DIV_CLKALIVE_CMGP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_ALIVE_SPMI, MUX_CLK_ALIVE_SPMI, CLK_CON_DIV_DIV_CLK_ALIVE_SPMI_DIVRATIO, CLK_CON_DIV_DIV_CLK_ALIVE_SPMI_BUSY, CLK_CON_DIV_DIV_CLK_ALIVE_SPMI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKALIVE_CMGP_PERI, GATE_CLKALIVE_CMGP_PERI, CLK_CON_DIV_CLKALIVE_CMGP_PERI_DIVRATIO, CLK_CON_DIV_CLKALIVE_CMGP_PERI_BUSY, CLK_CON_DIV_CLKALIVE_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_ALIVE_DBGCORE_UART, MUX_CLK_ALIVE_DBGCORE_UART, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_DIVRATIO, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_BUSY, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKALIVE_CHUB_PERI, GATE_CLKALIVE_CHUB_PERI, CLK_CON_DIV_CLKALIVE_CHUB_PERI_DIVRATIO, CLK_CON_DIV_CLKALIVE_CHUB_PERI_BUSY, CLK_CON_DIV_CLKALIVE_CHUB_PERI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKALIVE_DBGCORE_NOC, GATE_CLKALIVE_DBGCORE_NOC, CLK_CON_DIV_CLKALIVE_DBGCORE_NOC_DIVRATIO, CLK_CON_DIV_CLKALIVE_DBGCORE_NOC_BUSY, CLK_CON_DIV_CLKALIVE_DBGCORE_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKALIVE_DNC_NOC, GATE_CLKALIVE_DNC_NOC, CLK_CON_DIV_CLKALIVE_DNC_NOC_DIVRATIO, CLK_CON_DIV_CLKALIVE_DNC_NOC_BUSY, CLK_CON_DIV_CLKALIVE_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKALIVE_GNPU_NOC, GATE_CLKALIVE_GNPU_NOC, CLK_CON_DIV_CLKALIVE_GNPU_NOC_DIVRATIO, CLK_CON_DIV_CLKALIVE_GNPU_NOC_BUSY, CLK_CON_DIV_CLKALIVE_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKALIVE_SDMA_NOC, GATE_CLKALIVE_SDMA_NOC, CLK_CON_DIV_CLKALIVE_SDMA_NOC_DIVRATIO, CLK_CON_DIV_CLKALIVE_SDMA_NOC_BUSY, CLK_CON_DIV_CLKALIVE_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_ALIVE_PMU_SUB, MUX_CLK_ALIVE_PMU_SUB, CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB_DIVRATIO, CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB_BUSY, CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKALIVE_CHUBVTS_NOC, GATE_CLKALIVE_CHUBVTS_NOC, CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC_DIVRATIO, CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC_BUSY, CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKALIVE_CSIS_NOC, GATE_CLKALIVE_CSIS_NOC, CLK_CON_DIV_CLKALIVE_CSIS_NOC_DIVRATIO, CLK_CON_DIV_CLKALIVE_CSIS_NOC_BUSY, CLK_CON_DIV_CLKALIVE_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKALIVE_DSP_NOC, GATE_CLKALIVE_DSP_NOC, CLK_CON_DIV_CLKALIVE_DSP_NOC_DIVRATIO, CLK_CON_DIV_CLKALIVE_DSP_NOC_BUSY, CLK_CON_DIV_CLKALIVE_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_CPU_PCLKDBG, MUX_HCHGEN_CLK_AUD_CPU, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_DSIF, MUX_CLK_AUD_DSIF, CLK_CON_DIV_DIV_CLK_AUD_DSIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_DSIF_BUSY, CLK_CON_DIV_DIV_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_UAIF0, MUX_CLK_AUD_UAIF0, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_UAIF1, MUX_CLK_AUD_UAIF1, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_UAIF2, MUX_CLK_AUD_UAIF2, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_UAIF3, MUX_CLK_AUD_UAIF3, CLK_CON_DIV_DIV_CLK_AUD_UAIF3_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF3_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_CPU_ACLK, MUX_HCHGEN_CLK_AUD_CPU, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_NOC, MUX_CLK_AUD_NOC, CLK_CON_DIV_DIV_CLK_AUD_NOC_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_NOC_BUSY, CLK_CON_DIV_DIV_CLK_AUD_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_NOCP, DIV_CLK_AUD_NOC, CLK_CON_DIV_DIV_CLK_AUD_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_AUD_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_CNT, MUX_CLK_AUD_SCLK, CLK_CON_DIV_DIV_CLK_AUD_CNT_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CNT_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CNT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_UAIF4, MUX_CLK_AUD_UAIF4, CLK_CON_DIV_DIV_CLK_AUD_UAIF4_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF4_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_UAIF5, MUX_CLK_AUD_UAIF5, CLK_CON_DIV_DIV_CLK_AUD_UAIF5_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF5_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_UAIF6, MUX_CLK_AUD_UAIF6, CLK_CON_DIV_DIV_CLK_AUD_UAIF6_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF6_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF6_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKAUD_HSI0_NOC, GATE_CLKAUD_HSI0_NOC, CLK_CON_DIV_CLKAUD_HSI0_NOC_DIVRATIO, CLK_CON_DIV_CLKAUD_HSI0_NOC_BUSY, CLK_CON_DIV_CLKAUD_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_PCMC, MUX_CLK_AUD_PCMC, CLK_CON_DIV_DIV_CLK_AUD_PCMC_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_PCMC_BUSY, CLK_CON_DIV_DIV_CLK_AUD_PCMC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_AUDIF, MUX_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_BUSY, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_SERIAL_LIF, MUX_CLK_AUD_SERIAL_LIF, CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_BUSY, CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_SERIAL_LIF_CORE, MUX_CLK_AUD_SERIAL_LIF_CORE, CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_CORE_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_CORE_BUSY, CLK_CON_DIV_DIV_CLK_AUD_SERIAL_LIF_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLK_AUD_MCLK, MUX_CLK_AUD_SCLK, CLK_CON_DIV_CLK_AUD_MCLK_DIVRATIO, CLK_CON_DIV_CLK_AUD_MCLK_BUSY, CLK_CON_DIV_CLK_AUD_MCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_AUD_CPU_ACP, MUX_HCHGEN_CLK_AUD_CPU, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_BRP_NOCP, DIV_CLK_BRP_NOC, CLK_CON_DIV_DIV_CLK_BRP_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_BRP_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_BRP_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLK_BRP_ADD_CH_CLK, FREE_OSCCLK_BRP, CLK_CON_DIV_CLK_BRP_ADD_CH_CLK_DIVRATIO, CLK_CON_DIV_CLK_BRP_ADD_CH_CLK_BUSY, CLK_CON_DIV_CLK_BRP_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CHUB_NOC, MUX_CLK_CHUB_NOC, CLK_CON_DIV_DIV_CLK_CHUB_NOC_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_NOC_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CHUB_USI0, MUX_CLK_CHUB_USI0, CLK_CON_DIV_DIV_CLK_CHUB_USI0_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_USI0_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_USI0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CHUB_USI1, MUX_CLK_CHUB_USI1, CLK_CON_DIV_DIV_CLK_CHUB_USI1_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_USI1_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_USI1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CHUB_USI3, MUX_CLK_CHUB_USI3, CLK_CON_DIV_DIV_CLK_CHUB_USI3_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_USI3_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_USI3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CHUB_I2C, MUX_CLK_CHUB_I2C, CLK_CON_DIV_DIV_CLK_CHUB_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_I2C_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CHUB_USI2, MUX_CLK_CHUB_USI2, CLK_CON_DIV_DIV_CLK_CHUB_USI2_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_USI2_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_USI2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CHUB_SPI_MS_CTRL, MUX_CLK_CHUB_SPI_MS_CTRL, CLK_CON_DIV_DIV_CLK_CHUB_SPI_MS_CTRL_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_SPI_MS_CTRL_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CHUB_SPI_I2C0, MUX_CLK_CHUB_SPI_I2C0, CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C0_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C0_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CHUB_SPI_I2C1, MUX_CLK_CHUB_SPI_I2C1, CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C1_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C1_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_SPI_I2C1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CHUBVTS_NOC, MUX_CLK_CHUBVTS_NOC, CLK_CON_DIV_DIV_CLK_CHUBVTS_NOC_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUBVTS_NOC_BUSY, CLK_CON_DIV_DIV_CLK_CHUBVTS_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CHUBVTS_DMAILBOX_CCLK, MUX_CLK_CHUBVTS_DMAILBOX_CCLK, CLK_CON_DIV_DIV_CLK_CHUBVTS_DMAILBOX_CCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUBVTS_DMAILBOX_CCLK_BUSY, CLK_CON_DIV_DIV_CLK_CHUBVTS_DMAILBOX_CCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_USI4, MUX_CLK_CMGP_USI4, CLK_CON_DIV_DIV_CLK_CMGP_USI4_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI4_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_USI1, MUX_CLK_CMGP_USI1, CLK_CON_DIV_DIV_CLK_CMGP_USI1_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI1_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_USI0, MUX_CLK_CMGP_USI0, CLK_CON_DIV_DIV_CLK_CMGP_USI0_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI0_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_USI2, MUX_CLK_CMGP_USI2, CLK_CON_DIV_DIV_CLK_CMGP_USI2_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI2_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_USI3, MUX_CLK_CMGP_USI3, CLK_CON_DIV_DIV_CLK_CMGP_USI3_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI3_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_USI5, MUX_CLK_CMGP_USI5, CLK_CON_DIV_DIV_CLK_CMGP_USI5_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI5_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_USI6, MUX_CLK_CMGP_USI6, CLK_CON_DIV_DIV_CLK_CMGP_USI6_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI6_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI6_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_I2C, MUX_CLK_CMGP_I2C, CLK_CON_DIV_DIV_CLK_CMGP_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_I2C_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_SPI_MS_CTRL, MUX_CLK_CMGP_SPI_MS_CTRL, CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_SPI_I2C0, MUX_CLK_CMGP_SPI_I2C0, CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CMGP_SPI_I2C1, MUX_CLK_CMGP_SPI_I2C1, CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_ALIVE_NOC, GATE_CLKCMU_ALIVE_NOC, CLK_CON_DIV_CLKCMU_ALIVE_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_ALIVE_NOC_BUSY, CLK_CON_DIV_CLKCMU_ALIVE_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_HSI0_DPOSC, GATE_CLKCMU_HSI0_DPOSC, CLK_CON_DIV_CLKCMU_HSI0_DPOSC_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI0_DPOSC_BUSY, CLK_CON_DIV_CLKCMU_HSI0_DPOSC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC0_NOC, GATE_CLKCMU_PERIC0_NOC, CLK_CON_DIV_CLKCMU_PERIC0_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_NOC_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIS_NOC, GATE_CLKCMU_PERIS_NOC, CLK_CON_DIV_CLKCMU_PERIS_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIS_NOC_BUSY, CLK_CON_DIV_CLKCMU_PERIS_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_DPUF_ALT, GATE_CLKCMU_DPUF_ALT, CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT_BUSY, CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_MFC0_MFC0, GATE_CLKCMU_MFC0_MFC0, CLK_CON_DIV_CLKCMU_MFC0_MFC0_DIVRATIO, CLK_CON_DIV_CLKCMU_MFC0_MFC0_BUSY, CLK_CON_DIV_CLKCMU_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_DSP_NOC_SM, GATE_CLKCMU_DSP_NOC_SM, CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC1_NOC, GATE_CLKCMU_PERIC1_NOC, CLK_CON_DIV_CLKCMU_PERIC1_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_NOC_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_CPUCL0_SWITCH_SM, GATE_CLKCMU_CPUCL0_SWITCH_SM, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_NOCL0_NOC_SM, GATE_CLKCMU_NOCL0_NOC_SM, CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_BRP_NOC, GATE_CLKCMU_BRP_NOC, CLK_CON_DIV_CLKCMU_BRP_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_BRP_NOC_BUSY, CLK_CON_DIV_CLKCMU_BRP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_YUVP_NOC, GATE_CLKCMU_YUVP_NOC, CLK_CON_DIV_CLKCMU_YUVP_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_YUVP_NOC_BUSY, CLK_CON_DIV_CLKCMU_YUVP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_AUD_CPU_SM, GATE_CLKCMU_AUD_CPU_SM, CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_CPUCL0_DBG_NOC_SM, GATE_CLKCMU_CPUCL0_DBG_NOC_SM, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_CIS_CLK0, GATE_CLKCMU_CIS_CLK0, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0_BUSY, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_CIS_CLK1, GATE_CLKCMU_CIS_CLK1, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1_BUSY, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_CIS_CLK2, GATE_CLKCMU_CIS_CLK2, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2_BUSY, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_CIS_CLK3, GATE_CLKCMU_CIS_CLK3, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3_BUSY, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CMU_BOOST_MIF, GATE_CLKCMU_CMU_BOOST_CPU_MIF, CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF_DIVRATIO, CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF_BUSY, CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_GNPU_NOC_SM, GATE_CLKCMU_GNPU_NOC_SM, CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_MFC0_WFD, GATE_CLKCMU_MFC0_WFD, CLK_CON_DIV_CLKCMU_MFC0_WFD_DIVRATIO, CLK_CON_DIV_CLKCMU_MFC0_WFD_BUSY, CLK_CON_DIV_CLKCMU_MFC0_WFD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_MIF_NOCP, GATE_CLKCMU_MIF_NOCP, CLK_CON_DIV_CLKCMU_MIF_NOCP_DIVRATIO, CLK_CON_DIV_CLKCMU_MIF_NOCP_BUSY, CLK_CON_DIV_CLKCMU_MIF_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC0_IP0, GATE_CLKCMU_PERIC0_IP0, CLK_CON_DIV_CLKCMU_PERIC0_IP0_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_IP0_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_IP0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC1_IP0, GATE_CLKCMU_PERIC1_IP0, CLK_CON_DIV_CLKCMU_PERIC1_IP0_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_IP0_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_IP0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_DPUF, GATE_CLKCMU_DPUF, CLK_CON_DIV_DIV_CLKCMU_DPUF_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_DPUF_BUSY, CLK_CON_DIV_DIV_CLKCMU_DPUF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_CPUCL1_SWITCH_SM, GATE_CLKCMU_CPUCL1_SWITCH_SM, CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_HSI0_NOC, GATE_CLKCMU_HSI0_NOC, CLK_CON_DIV_CLKCMU_HSI0_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI0_NOC_BUSY, CLK_CON_DIV_CLKCMU_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_CIS_CLK4, GATE_CLKCMU_CIS_CLK4, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4_BUSY, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CMU_BOOST, GATE_CLKCMU_CMU_BOOST, CLK_CON_DIV_CLKCMU_CMU_BOOST_DIVRATIO, CLK_CON_DIV_CLKCMU_CMU_BOOST_BUSY, CLK_CON_DIV_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CSIS_NOC, GATE_CLKCMU_CSIS_NOC, CLK_CON_DIV_CLKCMU_CSIS_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_CSIS_NOC_BUSY, CLK_CON_DIV_CLKCMU_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_MCSC_NOC_SM, GATE_CLKCMU_MCSC_NOC_SM, CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_HSI1_NOC, GATE_CLKCMU_HSI1_NOC, CLK_CON_DIV_CLKCMU_HSI1_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI1_NOC_BUSY, CLK_CON_DIV_CLKCMU_HSI1_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CSIS_OIS_MCU, GATE_CLKCMU_CSIS_OIS_MCU, CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU_DIVRATIO, CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU_BUSY, CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_CIS_CLK5, GATE_CLKCMU_CIS_CLK5, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5_BUSY, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CMU_BOOST_CPU, GATE_CLKCMU_CMU_BOOST_CPU, CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU_DIVRATIO, CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU_BUSY, CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_M2M_NOC_SM, GATE_CLKCMU_M2M_NOC_SM, CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_DPUB_ALT, GATE_CLKCMU_DPUB_ALT, CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT_BUSY, CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_DPUB, GATE_CLKCMU_DPUB, CLK_CON_DIV_DIV_CLKCMU_DPUB_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_DPUB_BUSY, CLK_CON_DIV_DIV_CLKCMU_DPUB_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_MFC1_MFC1, GATE_CLKCMU_MFC1_MFC1, CLK_CON_DIV_CLKCMU_MFC1_MFC1_DIVRATIO, CLK_CON_DIV_CLKCMU_MFC1_MFC1_BUSY, CLK_CON_DIV_CLKCMU_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_LME_NOC, GATE_CLKCMU_LME_NOC, CLK_CON_DIV_CLKCMU_LME_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_LME_NOC_BUSY, CLK_CON_DIV_CLKCMU_LME_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_NOCL1A_NOC_SM, GATE_CLKCMU_NOCL1A_NOC_SM, CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_HSI0_USB32DRD, GATE_CLKCMU_HSI0_USB32DRD, CLK_CON_DIV_CLKCMU_HSI0_USB32DRD_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI0_USB32DRD_BUSY, CLK_CON_DIV_CLKCMU_HSI0_USB32DRD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_HSI0_DPGTC, GATE_CLKCMU_HSI0_DPGTC, CLK_CON_DIV_CLKCMU_HSI0_DPGTC_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI0_DPGTC_BUSY, CLK_CON_DIV_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_AUD_NOC, GATE_CLKCMU_AUD_NOC, CLK_CON_DIV_CLKCMU_AUD_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_AUD_NOC_BUSY, CLK_CON_DIV_CLKCMU_AUD_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CSIS_DCPHY, GATE_CLKCMU_CSIS_DCPHY, CLK_CON_DIV_CLKCMU_CSIS_DCPHY_DIVRATIO, CLK_CON_DIV_CLKCMU_CSIS_DCPHY_BUSY, CLK_CON_DIV_CLKCMU_CSIS_DCPHY_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CP_SHARED0_CLK_SM, GATE_CP_SHARED0_CLK_SM, CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM_DIVRATIO, CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM_BUSY, CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CP_SHARED1_CLK, GATE_CP_SHARED1_CLK, CLK_CON_DIV_CP_SHARED1_CLK_DIVRATIO, CLK_CON_DIV_CP_SHARED1_CLK_BUSY, CLK_CON_DIV_CP_SHARED1_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CP_HISPEEDY_CLK_SM, GATE_CP_HISPEEDY_CLK_SM, CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM_DIVRATIO, CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM_BUSY, CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC0_IP1, GATE_CLKCMU_PERIC0_IP1, CLK_CON_DIV_CLKCMU_PERIC0_IP1_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_IP1_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_IP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC1_IP1, GATE_CLKCMU_PERIC1_IP1, CLK_CON_DIV_CLKCMU_PERIC1_IP1_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_IP1_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_IP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_SSP_NOC, GATE_CLKCMU_SSP_NOC, CLK_CON_DIV_CLKCMU_SSP_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_SSP_NOC_BUSY, CLK_CON_DIV_CLKCMU_SSP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_G3D_SWITCH_SM, GATE_CLKCMU_G3D_SWITCH_SM, CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC2_NOC, GATE_CLKCMU_PERIC2_NOC, CLK_CON_DIV_CLKCMU_PERIC2_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC2_NOC_BUSY, CLK_CON_DIV_CLKCMU_PERIC2_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC2_IP0, GATE_CLKCMU_PERIC2_IP0, CLK_CON_DIV_CLKCMU_PERIC2_IP0_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC2_IP0_BUSY, CLK_CON_DIV_CLKCMU_PERIC2_IP0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIC2_IP1, GATE_CLKCMU_PERIC2_IP1, CLK_CON_DIV_CLKCMU_PERIC2_IP1_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC2_IP1_BUSY, CLK_CON_DIV_CLKCMU_PERIC2_IP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CPUCL0_NOCP, GATE_CLKCMU_CPUCL0_NOCP, CLK_CON_DIV_CLKCMU_CPUCL0_NOCP_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_NOCP_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_DSU_SWITCH_SM, GATE_CLKCMU_DSU_SWITCH_SM, CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_G3D_NOCP, GATE_CLKCMU_G3D_NOCP, CLK_CON_DIV_CLKCMU_G3D_NOCP_DIVRATIO, CLK_CON_DIV_CLKCMU_G3D_NOCP_BUSY, CLK_CON_DIV_CLKCMU_G3D_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CSTAT_NOC, GATE_CLKCMU_CSTAT_NOC, CLK_CON_DIV_CLKCMU_CSTAT_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_CSTAT_NOC_BUSY, CLK_CON_DIV_CLKCMU_CSTAT_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_DPUB_DSIM, GATE_CLKCMU_DPUB_DSIM, CLK_CON_DIV_CLKCMU_DPUB_DSIM_DIVRATIO, CLK_CON_DIV_CLKCMU_DPUB_DSIM_BUSY, CLK_CON_DIV_CLKCMU_DPUB_DSIM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_DNC_NOC_SM, GATE_CLKCMU_DNC_NOC_SM, CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_CPUCL2_SWITCH_SM, GATE_CLKCMU_CPUCL2_SWITCH_SM, CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_SDMA_NOC_SM, GATE_CLKCMU_SDMA_NOC_SM, CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CP_SHARED2_CLK_SM, GATE_CP_SHARED2_CLK_SM, CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM_DIVRATIO, CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM_BUSY, CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_CIS_CLK6, GATE_CLKCMU_CIS_CLK6, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6_BUSY, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_NOCL1C_NOC_SM, GATE_CLKCMU_NOCL1C_NOC_SM, CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_NOCL1B_NOC0_SM, GATE_CLKCMU_NOCL1B_NOC0_SM, CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_CMU_BOOST_CAM, GATE_CLKCMU_CMU_BOOST_CAM, CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM_DIVRATIO, CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM_BUSY, CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_VTS_DMIC, GATE_CLKCMU_VTS_DMIC, CLK_CON_DIV_CLKCMU_VTS_DMIC_DIVRATIO, CLK_CON_DIV_CLKCMU_VTS_DMIC_BUSY, CLK_CON_DIV_CLKCMU_VTS_DMIC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_AUD_AUDIF0_SM, GATE_CLKCMU_AUD_AUDIF0_SM, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_AUD_AUDIF1_SM, GATE_CLKCMU_AUD_AUDIF1_SM, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_PERIS_GIC, GATE_CLKCMU_PERIS_GIC, CLK_CON_DIV_CLKCMU_PERIS_GIC_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIS_GIC_BUSY, CLK_CON_DIV_CLKCMU_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_CIS_CLK7, GATE_CLKCMU_CIS_CLK7, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7_BUSY, CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_NOCL1B_NOC1, GATE_CLKCMU_NOCL1B_NOC1, CLK_CON_DIV_CLKCMU_NOCL1B_NOC1_DIVRATIO, CLK_CON_DIV_CLKCMU_NOCL1B_NOC1_BUSY, CLK_CON_DIV_CLKCMU_NOCL1B_NOC1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_LME_LME, GATE_CLKCMU_LME_LME, CLK_CON_DIV_CLKCMU_LME_LME_DIVRATIO, CLK_CON_DIV_CLKCMU_LME_LME_BUSY, CLK_CON_DIV_CLKCMU_LME_LME_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_M2M_FRC_SM, GATE_CLKCMU_M2M_FRC_SM, CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_MCSC_MCSC_SM, GATE_CLKCMU_MCSC_MCSC_SM, CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_UFS_UFS_EMBD, GATE_CLKCMU_UFS_UFS_EMBD, CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD_DIVRATIO, CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD_BUSY, CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_UFS_MMC_CARD_SM, GATE_CLKCMU_UFS_MMC_CARD_SM, CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM_BUSY, CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLKCMU_UFS_NOC, GATE_CLKCMU_UFS_NOC, CLK_CON_DIV_CLKCMU_UFS_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_UFS_NOC_BUSY, CLK_CON_DIV_CLKCMU_UFS_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_AUD_CPU, GATE_CLKCMU_AUD_CPU, CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_BUSY, CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_AUD_AUDIF0, GATE_CLKCMU_AUD_AUDIF0, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_BUSY, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_AUD_AUDIF1, GATE_CLKCMU_AUD_AUDIF1, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_BUSY, CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_CPUCL0_SWITCH, GATE_CLKCMU_CPUCL0_SWITCH, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_CPUCL1_SWITCH, GATE_CLKCMU_CPUCL1_SWITCH, CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_CPUCL2_SWITCH, GATE_CLKCMU_CPUCL2_SWITCH, CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_BUSY, CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_DSU_SWITCH, GATE_CLKCMU_DSU_SWITCH, CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_BUSY, CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_CPUCL0_DBG_NOC, GATE_CLKCMU_CPUCL0_DBG_NOC, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_BUSY, CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_DNC_NOC, GATE_CLKCMU_DNC_NOC, CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_BUSY, CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_SDMA_NOC, GATE_CLKCMU_SDMA_NOC, CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_BUSY, CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_DSP_NOC, GATE_CLKCMU_DSP_NOC, CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_BUSY, CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_G3D_SWITCH, GATE_CLKCMU_G3D_SWITCH, CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_GNPU_NOC, GATE_CLKCMU_GNPU_NOC, CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_BUSY, CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_M2M_NOC, GATE_CLKCMU_M2M_NOC, CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_BUSY, CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_M2M_FRC, GATE_CLKCMU_M2M_FRC, CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_BUSY, CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_MCSC_NOC, GATE_CLKCMU_MCSC_NOC, CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_BUSY, CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_MCSC_MCSC, GATE_CLKCMU_MCSC_MCSC, CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_BUSY, CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_NOCL0_NOC, GATE_CLKCMU_NOCL0_NOC, CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_BUSY, CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_NOCL1A_NOC, GATE_CLKCMU_NOCL1A_NOC, CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_BUSY, CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_NOCL1B_NOC0, GATE_CLKCMU_NOCL1B_NOC0, CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_BUSY, CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_NOCL1C_NOC, GATE_CLKCMU_NOCL1C_NOC, CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_BUSY, CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CP_HISPEEDY_CLK, GATE_CP_HISPEEDY_CLK, CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_DIVRATIO, CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_BUSY, CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CP_SHARED2_CLK, GATE_CP_SHARED2_CLK, CLK_CON_DIV_DIV_CP_SHARED2_CLK_DIVRATIO, CLK_CON_DIV_DIV_CP_SHARED2_CLK_BUSY, CLK_CON_DIV_DIV_CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CP_SHARED0_CLK, GATE_CP_SHARED0_CLK, CLK_CON_DIV_DIV_CP_SHARED0_CLK_DIVRATIO, CLK_CON_DIV_DIV_CP_SHARED0_CLK_BUSY, CLK_CON_DIV_DIV_CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKCMU_UFS_MMC_CARD, GATE_CLKCMU_UFS_MMC_CARD, CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_BUSY, CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLK_CPUCL0_ADD_CH_CLK, FREE_OSCCLK_CPUCL0, CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK_DIVRATIO, CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK_BUSY, CLK_CON_DIV_CLK_CPUCL0_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLK_CPUCL0_DDD, MUX_CLK_CPUCL0_DDD, CLK_CON_DIV_CLK_CPUCL0_DDD_DIVRATIO, CLK_CON_DIV_CLK_CPUCL0_DDD_BUSY, CLK_CON_DIV_CLK_CPUCL0_DDD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL0_DBG_NOC, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL0_DBG_PCLKDBG, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLK_CPUCL1_ADD_CH_CLK, FREE_OSCCLK_CPUCL1, CLK_CON_DIV_CLK_CPUCL1_ADD_CH_CLK_DIVRATIO, CLK_CON_DIV_CLK_CPUCL1_ADD_CH_CLK_BUSY, CLK_CON_DIV_CLK_CPUCL1_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLK_CPUCL1_DDD_0, MUX_CLK_CPUCL1_DDD_0, CLK_CON_DIV_CLK_CPUCL1_DDD_0_DIVRATIO, CLK_CON_DIV_CLK_CPUCL1_DDD_0_BUSY, CLK_CON_DIV_CLK_CPUCL1_DDD_0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL1_CORE_1, MUX_CLK_CPUCL1_IDLECLKDOWN_1, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_1_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_1_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLK_CPUCL1_DDD_1, MUX_CLK_CPUCL1_DDD_1, CLK_CON_DIV_CLK_CPUCL1_DDD_1_DIVRATIO, CLK_CON_DIV_CLK_CPUCL1_DDD_1_BUSY, CLK_CON_DIV_CLK_CPUCL1_DDD_1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL1_CORE_2, MUX_CLK_CPUCL1_IDLECLKDOWN_2, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_2_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_2_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLK_CPUCL1_DDD_2, MUX_CLK_CPUCL1_DDD_2, CLK_CON_DIV_CLK_CPUCL1_DDD_2_DIVRATIO, CLK_CON_DIV_CLK_CPUCL1_DDD_2_BUSY, CLK_CON_DIV_CLK_CPUCL1_DDD_2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLK_CPUCL2_ADD_CH_CLK, FREE_OSCCLK_CPUCL2, CLK_CON_DIV_CLK_CPUCL2_ADD_CH_CLK_DIVRATIO, CLK_CON_DIV_CLK_CPUCL2_ADD_CH_CLK_BUSY, CLK_CON_DIV_CLK_CPUCL2_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLK_CPUCL2_DDD, MUX_CLK_CPUCL2_DDD, CLK_CON_DIV_CLK_CPUCL2_DDD_DIVRATIO, CLK_CON_DIV_CLK_CPUCL2_DDD_BUSY, CLK_CON_DIV_CLK_CPUCL2_DDD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CSIS_NOCP, MUX_CLK_CSIS_NOC, CLK_CON_DIV_DIV_CLK_CSIS_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CSIS_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_CSIS_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CSIS_DCPHY, MUX_CLK_CSIS_DCPHY, CLK_CON_DIV_DIV_CLK_CSIS_DCPHY_DIVRATIO, CLK_CON_DIV_DIV_CLK_CSIS_DCPHY_BUSY, CLK_CON_DIV_DIV_CLK_CSIS_DCPHY_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CSTAT_NOCP, MUX_CLKCMU_CSTAT_NOC_USER, CLK_CON_DIV_DIV_CLK_CSTAT_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CSTAT_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_CSTAT_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DNC_NOCP, DIV_CLK_DNC_NOC, CLK_CON_DIV_DIV_CLK_DNC_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DNC_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_DNC_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLK_DNC_ADD_CH_CLK, FREE_OSCCLK_DNC, CLK_CON_DIV_CLK_DNC_ADD_CH_CLK_DIVRATIO, CLK_CON_DIV_CLK_DNC_ADD_CH_CLK_BUSY, CLK_CON_DIV_CLK_DNC_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DPUB_NOCP, MUX_CLKCMU_DPUB_NOC_USER, CLK_CON_DIV_DIV_CLK_DPUB_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DPUB_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_DPUB_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DPUF_NOCP, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_DIV_DIV_CLK_DPUF_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DPUF_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_DPUF_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DPUF1_NOCP, MUX_CLKCMU_DPUF1_NOC_USER, CLK_CON_DIV_DIV_CLK_DPUF1_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DPUF1_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_DPUF1_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DRCP_NOCP, DIV_CLK_DRCP_NOC, CLK_CON_DIV_DIV_CLK_DRCP_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DRCP_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_DRCP_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DSP_NOCP, DIV_CLK_DSP_NOC, CLK_CON_DIV_DIV_CLK_DSP_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DSP_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_DSP_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CLUSTER_ACLK, DIV_CLK_DSU_CLUSTER, CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CLUSTER_ATCLK, DIV_CLK_DSU_CLUSTER, CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLK_DSU_DDD, MUX_CLK_DSU_DDD, CLK_CON_DIV_CLK_DSU_DDD_DIVRATIO, CLK_CON_DIV_CLK_DSU_DDD_BUSY, CLK_CON_DIV_CLK_DSU_DDD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLK_DSU_STR_DEM_CLK, FREE_OSCCLK_DSU, CLK_CON_DIV_CLK_DSU_STR_DEM_CLK_DIVRATIO, CLK_CON_DIV_CLK_DSU_STR_DEM_CLK_BUSY, CLK_CON_DIV_CLK_DSU_STR_DEM_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CLUSTER_ACPCLK, DIV_CLK_DSU_CLUSTER, CLK_CON_DIV_DIV_CLK_CLUSTER_ACPCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER_ACPCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER_ACPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CLUSTER_MPCLK, DIV_CLK_DSU_CLUSTER, CLK_CON_DIV_DIV_CLK_CLUSTER_MPCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER_MPCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER_MPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CLUSTER_MPACTCLK, DIV_CLK_CLUSTER_ACLK, CLK_CON_DIV_DIV_CLK_CLUSTER_MPACTCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER_MPACTCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER_MPACTCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLK_G3D_ADD_CH_CLK, FREE_OSCCLK_G3DCORE, CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_DIVRATIO, CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_BUSY, CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(CLK_G3D_DDD, MUX_CLK_G3D_DDD, CLK_CON_DIV_CLK_G3D_DDD_DIVRATIO, CLK_CON_DIV_CLK_G3D_DDD_BUSY, CLK_CON_DIV_CLK_G3D_DDD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_GNPU_NOCP, DIV_CLK_GNPU_NOC, CLK_CON_DIV_DIV_CLK_GNPU_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_GNPU_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_GNPU_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_HSI0_EUSB, MUX_CLK_HSI0_NOC, CLK_CON_DIV_DIV_CLK_HSI0_EUSB_DIVRATIO, CLK_CON_DIV_DIV_CLK_HSI0_EUSB_BUSY, CLK_CON_DIV_DIV_CLK_HSI0_EUSB_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_LME_NOCP, MUX_CLKCMU_LME_NOC_USER, CLK_CON_DIV_DIV_CLK_LME_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_LME_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_LME_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_M2M_NOCP, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_DIV_DIV_CLK_M2M_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_M2M_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_M2M_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_MCSC_NOCP, DIV_CLK_MCSC_NOC, CLK_CON_DIV_DIV_CLK_MCSC_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MCSC_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_MCSC_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_MFC0_NOCP, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_DIV_DIV_CLK_MFC0_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MFC0_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_MFC0_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_MFC1_NOCP, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_DIV_DIV_CLK_MFC1_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MFC1_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_MFC1_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_NOCL0_NOCP, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_NOCL1A_NOCP, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_NOCL1B_NOCP, MUX_CLKCMU_NOCL1B_NOC0_USER, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_NOCL1C_NOCP, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_DIV_DIV_CLK_NOCL1C_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_NOCL1C_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_NOCL1C_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_USI04, MUX_CLK_PERIC0_USI04, CLK_CON_DIV_DIV_CLK_PERIC0_USI04_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI04_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI04_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC0_I2C, MUX_CLK_PERIC0_I2C, CLK_CON_DIV_DIV_CLK_PERIC0_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_UART_BT, MUX_CLK_PERIC1_UART_BT, CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_I2C, MUX_CLK_PERIC1_I2C, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_USI07, MUX_CLK_PERIC1_USI07, CLK_CON_DIV_DIV_CLK_PERIC1_USI07_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI07_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI07_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_USI08, MUX_CLK_PERIC1_USI08, CLK_CON_DIV_DIV_CLK_PERIC1_USI08_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI08_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI08_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_USI09, MUX_CLK_PERIC1_USI09, CLK_CON_DIV_DIV_CLK_PERIC1_USI09_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI09_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI09_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_USI10, MUX_CLK_PERIC1_USI10, CLK_CON_DIV_DIV_CLK_PERIC1_USI10_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI10_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI10_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_SPI_MS_CTRL, MUX_CLK_PERIC1_SPI_MS_CTRL, CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_USI07_SPI_I2C, MUX_CLK_PERIC1_USI07_SPI_I2C, CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC1_USI08_SPI_I2C, MUX_CLK_PERIC1_USI08_SPI_I2C, CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC2_I2C, MUX_CLK_PERIC2_I2C, CLK_CON_DIV_DIV_CLK_PERIC2_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC2_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERIC2_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC2_USI00, MUX_CLK_PERIC2_USI00, CLK_CON_DIV_DIV_CLK_PERIC2_USI00_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC2_USI00_BUSY, CLK_CON_DIV_DIV_CLK_PERIC2_USI00_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC2_USI01, MUX_CLK_PERIC2_USI01, CLK_CON_DIV_DIV_CLK_PERIC2_USI01_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC2_USI01_BUSY, CLK_CON_DIV_DIV_CLK_PERIC2_USI01_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC2_USI02, MUX_CLK_PERIC2_USI02, CLK_CON_DIV_DIV_CLK_PERIC2_USI02_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC2_USI02_BUSY, CLK_CON_DIV_DIV_CLK_PERIC2_USI02_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC2_USI03, MUX_CLK_PERIC2_USI03, CLK_CON_DIV_DIV_CLK_PERIC2_USI03_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC2_USI03_BUSY, CLK_CON_DIV_DIV_CLK_PERIC2_USI03_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC2_USI05, MUX_CLK_PERIC2_USI05, CLK_CON_DIV_DIV_CLK_PERIC2_USI05_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC2_USI05_BUSY, CLK_CON_DIV_DIV_CLK_PERIC2_USI05_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC2_USI06, MUX_CLK_PERIC2_USI06, CLK_CON_DIV_DIV_CLK_PERIC2_USI06_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC2_USI06_BUSY, CLK_CON_DIV_DIV_CLK_PERIC2_USI06_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC2_SPI_MS_CTRL, MUX_CLK_PERIC2_SPI_MS_CTRL, CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL_BUSY, CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC2_USI11, MUX_CLK_PERIC2_USI11, CLK_CON_DIV_DIV_CLK_PERIC2_USI11_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC2_USI11_BUSY, CLK_CON_DIV_DIV_CLK_PERIC2_USI11_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC2_UART_DBG, MUX_CLK_PERIC2_UART_DBG, CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG_BUSY, CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC2_USI00_SPI_I2C, MUX_CLK_PERIC2_USI00_SPI_I2C, CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_PERIC2_USI01_SPI_I2C, MUX_CLK_PERIC2_USI01_SPI_I2C, CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_SDMA_NOCP, DIV_CLK_SDMA_NOC, CLK_CON_DIV_DIV_CLK_SDMA_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_SDMA_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_SDMA_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_SSP_NOCP, MUX_CLKCMU_SSP_NOC_USER, CLK_CON_DIV_DIV_CLK_SSP_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_SSP_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_SSP_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VTS_DMIC_IF, DIV_CLKVTS_AUD_DMIC0, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VTS_DMIC_IF_DIV2, DIV_CLK_VTS_DMIC_IF, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VTS_NOC, DIV_CLK_VTS_CPU, CLK_CON_DIV_DIV_CLK_VTS_NOC_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_NOC_BUSY, CLK_CON_DIV_DIV_CLK_VTS_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VTS_SERIAL_LIF, MUX_CLKALIVE_VTS_RCO_USER, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_BUSY, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VTS_SERIAL_LIF_CORE, MUX_CLKALIVE_VTS_RCO_USER, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE_BUSY, CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_VTS_CPU, MUX_CLK_VTS_NOC, CLK_CON_DIV_DIV_CLK_VTS_CPU_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_CPU_BUSY, CLK_CON_DIV_DIV_CLK_VTS_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKVTS_AUD_DMIC0, MUX_CLK_VTS_DMIC_PAD, CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0_DIVRATIO, CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0_BUSY, CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLKVTS_AUD_DMIC1, DIV_CLKVTS_AUD_DMIC0, CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1_DIVRATIO, CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1_BUSY, CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_YUVP_NOCP, DIV_CLK_YUVP_NOC, CLK_CON_DIV_DIV_CLK_YUVP_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_YUVP_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_YUVP_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_BRP_NOC, MUX_CLKCMU_BRP_NOC_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_BRP_NOC_BUSY, CLK_CON_DIV_DIV_CLK_BRP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL0_CORE, MUX_CLK_CPUCL0_IDLECLKDOWN, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_CPUCL0_CORE_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL1_CORE_0, MUX_CLK_CPUCL1_IDLECLKDOWN_0, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_0_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CORE_0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_CPUCL2_CORE, MUX_CLK_CPUCL2_IDLECLKDOWN, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_CPUCL2_CORE_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL2_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DNC_NOC, MUX_CLK_DNC_NOC, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_DNC_NOC_BUSY, CLK_CON_DIV_DIV_CLK_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DRCP_NOC, MUX_CLKCMU_DRCP_NOC_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_DRCP_NOC_BUSY, CLK_CON_DIV_DIV_CLK_DRCP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DSP_NOC, MUX_CLK_DSP_NOC, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_DSP_NOC_BUSY, CLK_CON_DIV_DIV_CLK_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_DSU_CLUSTER, MUX_CLK_DSU_IDLECLKDOWN, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_BUSY, CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_G3D_CORE, MUX_CLK_G3D_CORE, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_G3D_CORE_BUSY, CLK_CON_DIV_DIV_CLK_G3D_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_GNPU_NOC, MUX_CLK_GNPU_NOC, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_GNPU_NOC_BUSY, CLK_CON_DIV_DIV_CLK_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_MCSC_NOC, MUX_CLKCMU_MCSC_NOC_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_MCSC_NOC_BUSY, CLK_CON_DIV_DIV_CLK_MCSC_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_MCSC_MCSC, MUX_CLKCMU_MCSC_MCSC_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_MCSC_MCSC_BUSY, CLK_CON_DIV_DIV_CLK_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_SDMA_NOC, MUX_CLK_SDMA_NOC, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_SDMA_NOC_BUSY, CLK_CON_DIV_DIV_CLK_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_DIV(DIV_CLK_YUVP_NOC, MUX_CLKCMU_YUVP_NOC_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_YUVP_NOC_BUSY, CLK_CON_DIV_DIV_CLK_YUVP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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};
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unsigned int cmucal_gate_size = 2117;
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struct cmucal_gate cmucal_gate_list[] = {
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CLK_GATE(GATE_CLKALIVE_UFD_NOC, MUX_CLKALIVE_UFD_NOC, CLK_CON_GAT_GATE_CLKALIVE_UFD_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKALIVE_UFD_NOC_MANUAL, CLK_CON_GAT_GATE_CLKALIVE_UFD_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK, OSCCLK_RCO_ALIVE, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKALIVE_CMGP_NOC, MUX_CLKALIVE_CMGP_NOC, CLK_CON_GAT_GATE_CLKALIVE_CMGP_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKALIVE_CMGP_NOC_MANUAL, CLK_CON_GAT_GATE_CLKALIVE_CMGP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKALIVE_CMGP_PERI, MUX_CLKALIVE_CMGP_PERI, CLK_CON_GAT_GATE_CLKALIVE_CMGP_PERI_CG_VAL, CLK_CON_GAT_GATE_CLKALIVE_CMGP_PERI_MANUAL, CLK_CON_GAT_GATE_CLKALIVE_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK, DIV_CLK_ALIVE_DBGCORE_UART, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK, DIV_CLK_ALIVE_DBGCORE_UART, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK, DIV_CLK_ALIVE_SPMI, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKALIVE_CHUB_PERI, MUX_CLKALIVE_CHUB_PERI, CLK_CON_GAT_GATE_CLKALIVE_CHUB_PERI_CG_VAL, CLK_CON_GAT_GATE_CLKALIVE_CHUB_PERI_MANUAL, CLK_CON_GAT_GATE_CLKALIVE_CHUB_PERI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKALIVE_DBGCORE_NOC, MUX_CLKALIVE_DBGCORE_NOC, CLK_CON_GAT_GATE_CLKALIVE_DBGCORE_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKALIVE_DBGCORE_NOC_MANUAL, CLK_CON_GAT_GATE_CLKALIVE_DBGCORE_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKALIVE_DNC_NOC, MUX_CLKALIVE_DNC_NOC, CLK_CON_GAT_GATE_CLKALIVE_DNC_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKALIVE_DNC_NOC_MANUAL, CLK_CON_GAT_GATE_CLKALIVE_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK, MUX_CLK_ALIVE_TIMER, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKALIVE_GNPU_NOC, MUX_CLKALIVE_GNPU_NOC, CLK_CON_GAT_GATE_CLKALIVE_GNPU_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKALIVE_GNPU_NOC_MANUAL, CLK_CON_GAT_GATE_CLKALIVE_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKALIVE_GNSS_NOC, MUX_CLKALIVE_GNSS_NOC, CLK_CON_GAT_CLKALIVE_GNSS_NOC_CG_VAL, CLK_CON_GAT_CLKALIVE_GNSS_NOC_MANUAL, CLK_CON_GAT_CLKALIVE_GNSS_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKALIVE_UFD_RCO, MUX_CLK_RCO_ALIVE_USER, CLK_CON_GAT_CLKALIVE_UFD_RCO_CG_VAL, CLK_CON_GAT_CLKALIVE_UFD_RCO_MANUAL, CLK_CON_GAT_CLKALIVE_UFD_RCO_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKALIVE_DNC_RCO, MUX_CLK_RCO_ALIVE_USER, CLK_CON_GAT_CLKALIVE_DNC_RCO_CG_VAL, CLK_CON_GAT_CLKALIVE_DNC_RCO_MANUAL, CLK_CON_GAT_CLKALIVE_DNC_RCO_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKALIVE_GNPU_RCO, MUX_CLK_RCO_ALIVE_USER, CLK_CON_GAT_CLKALIVE_GNPU_RCO_CG_VAL, CLK_CON_GAT_CLKALIVE_GNPU_RCO_MANUAL, CLK_CON_GAT_CLKALIVE_GNPU_RCO_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKALIVE_SDMA_NOC, MUX_CLKALIVE_SDMA_NOC, CLK_CON_GAT_GATE_CLKALIVE_SDMA_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKALIVE_SDMA_NOC_MANUAL, CLK_CON_GAT_GATE_CLKALIVE_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKALIVE_SDMA_RCO, MUX_CLK_RCO_ALIVE_USER, CLK_CON_GAT_CLKALIVE_SDMA_RCO_CG_VAL, CLK_CON_GAT_CLKALIVE_SDMA_RCO_MANUAL, CLK_CON_GAT_CLKALIVE_SDMA_RCO_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB, DIV_CLK_ALIVE_PMU_SUB, CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK, OSCCLK_RCO_ALIVE, CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK, OSCCLK_RCO_ALIVE, CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK, DIV_CLK_ALIVE_SPMI, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_ALIVE, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKALIVE_CHUBVTS_RCO, MUX_CLK_RCO_ALIVE_USER, CLK_CON_GAT_CLKALIVE_CHUBVTS_RCO_CG_VAL, CLK_CON_GAT_CLKALIVE_CHUBVTS_RCO_MANUAL, CLK_CON_GAT_CLKALIVE_CHUBVTS_RCO_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKALIVE_CHUBVTS_NOC, MUX_CLKALIVE_CHUBVTS_NOC, CLK_CON_GAT_GATE_CLKALIVE_CHUBVTS_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKALIVE_CHUBVTS_NOC_MANUAL, CLK_CON_GAT_GATE_CLKALIVE_CHUBVTS_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKALIVE_CSIS_NOC, MUX_CLKALIVE_CSIS_NOC, CLK_CON_GAT_GATE_CLKALIVE_CSIS_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKALIVE_CSIS_NOC_MANUAL, CLK_CON_GAT_GATE_CLKALIVE_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKALIVE_CSIS_RCO, MUX_CLK_RCO_ALIVE_USER, CLK_CON_GAT_CLKALIVE_CSIS_RCO_CG_VAL, CLK_CON_GAT_CLKALIVE_CSIS_RCO_MANUAL, CLK_CON_GAT_CLKALIVE_CSIS_RCO_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKALIVE_DSP_NOC, MUX_CLKALIVE_DSP_NOC, CLK_CON_GAT_GATE_CLKALIVE_DSP_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKALIVE_DSP_NOC_MANUAL, CLK_CON_GAT_GATE_CLKALIVE_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKALIVE_DSP_RCO, MUX_CLK_RCO_ALIVE_USER, CLK_CON_GAT_CLKALIVE_DSP_RCO_CG_VAL, CLK_CON_GAT_CLKALIVE_DSP_RCO_MANUAL, CLK_CON_GAT_CLKALIVE_DSP_RCO_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_ALIVE, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK, DIV_CLK_ALIVE_NOC, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK, DIV_CLK_ALIVE_SPMI, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_ALIVE, CLK_CON_GAT_CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK, FREE_OSCCLK_ALIVE, CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_ALIVE, CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK, OSCCLK_RCO_ALIVE, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_AD_APB_CSIS_WDMA_IPCLKPORT_PCLKM, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_AD_APB_CSIS_WDMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_AD_APB_CSIS_WDMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_AD_APB_CSIS_WDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_EBUF_BNS, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_EBUF_BNS_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_EBUF_BNS_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_EBUF_BNS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF_CSISBRP_IPCLKPORT_I_CLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF_CSISBRP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF_CSISBRP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF_CSISBRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF0_BRPCSIS_IPCLKPORT_I_CLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF0_BRPCSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF0_BRPCSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF0_BRPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF1_BRPCSIS_IPCLKPORT_I_CLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF1_BRPCSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF1_BRPCSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_MI_OTF1_BRPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AST_SI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK, CLKCSIS_ALLCSIS_OIC_MCU, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_OIS_MCU_TOP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_ACLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_PCLK, CLKCSIS_ALLCSIS_NOCP, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_ACLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_PCLK, CLKCSIS_ALLCSIS_NOCP, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_ACLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_PCLK, CLKCSIS_ALLCSIS_NOCP, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_PPMU_D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_ACLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_PCLK, CLKCSIS_ALLCSIS_NOCP, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_ACLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_PCLK, CLKCSIS_ALLCSIS_NOCP, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_ACLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_PCLK, CLKCSIS_ALLCSIS_NOCP, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_ACLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_PCLK, CLKCSIS_ALLCSIS_NOCP, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_ACLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_PCLK, CLKCSIS_ALLCSIS_NOCP, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_CSIS_WDMA4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_ACLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_PCLK, CLKCSIS_ALLCSIS_NOCP, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_QE_PDP_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_SIU_G_PPMU_CSIS_IPCLKPORT_I_ACLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SIU_G_PPMU_CSIS_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SIU_G_PPMU_CSIS_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SIU_G_PPMU_CSIS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_SLH_AST_SI_G_PPMU_CSIS_IPCLKPORT_I_CLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AST_SI_G_PPMU_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AST_SI_G_PPMU_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AST_SI_G_PPMU_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_XIU_P0_CSIS_IPCLKPORT_ACLK, CLKCSIS_ALLCSIS_NOCP, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_P0_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_P0_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_P0_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_SLH_AXI_SI_LP_CSISPERIC2_IPCLKPORT_I_CLK, CLKCSIS_ALLCSIS_OIC_MCU, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_SI_LP_CSISPERIC2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_SI_LP_CSISPERIC2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_SI_LP_CSISPERIC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_VGEN_LITE_D1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK, CLKCSIS_ALLCSIS_NOCP, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK, CLKCSIS_ALLCSIS_NOCD, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK, CLKCSIS_ALLCSIS_OIC_MCU, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK, CLKCSIS_ALLCSIS_OIC_MCU, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK, CLKCSIS_ALLCSIS_OIC_MCU, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK, CLKCSIS_ALLCSIS_NOCP, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_RSTNSYNC_SR_CLK_ALLCSIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK, CLKCSIS_ALLCSIS_NOCP, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK, CLKCSIS_ALLCSIS_NOCP, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK, CLKCSIS_ALLCSIS_NOCP, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_SI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_LH_AXI_MI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK, CLKCSIS_ALLCSIS_OIC_MCU, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_MI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_MI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_LH_AXI_MI_LP_INT_P0OIS_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_ALLCSIS_CMU_ALLCSIS_IPCLKPORT_PCLK, CLKCSIS_ALLCSIS_NOCP, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_ALLCSIS_CMU_ALLCSIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_ALLCSIS_CMU_ALLCSIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_ALLCSIS_CMU_ALLCSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_ALLCSIS_UID_BLK_CSIS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_ALLCSIS, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_BLK_CSIS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_BLK_CSIS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALLCSIS_UID_BLK_CSIS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT, DIV_CLK_AUD_CNT, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF, DIV_CLK_AUD_DSIF, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0, DIV_CLK_AUD_UAIF0, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1, DIV_CLK_AUD_UAIF1, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2, DIV_CLK_AUD_UAIF2, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3, DIV_CLK_AUD_UAIF3, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4, DIV_CLK_AUD_UAIF4, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5, DIV_CLK_AUD_UAIF5, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6, DIV_CLK_AUD_UAIF6, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB, DIV_CLK_AUD_CPU_ACLK, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32, MUX_HCHGEN_CLK_AUD_CPU, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP, DIV_CLK_AUD_CPU_PCLKDBG, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK, DIV_CLK_AUD_PCMC, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK0, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK0_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK0_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_NS1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_BAAW_D_AUDCHUBVTS_IPCLKPORT_I_PCLK, DIV_CLK_AUD_NOCP, CLK_CON_GAT_CLK_BLK_AUD_UID_BAAW_D_AUDCHUBVTS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_BAAW_D_AUDCHUBVTS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_BAAW_D_AUDCHUBVTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK, DIV_CLK_AUD_NOCP, CLK_CON_GAT_CLK_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_SLH_AXI_MI_LD_HSI0AUD_IPCLKPORT_I_CLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_LD_HSI0AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_LD_HSI0AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_LD_HSI0AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK, DIV_CLK_AUD_NOCP, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_LH_QDI_SI_D_AUD_IPCLKPORT_I_CLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_LH_QDI_SI_D_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_LH_QDI_SI_D_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_LH_QDI_SI_D_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_SLH_AXI_SI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_MAILBOX_AUD3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCD_IPCLKPORT_CLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCP_IPCLKPORT_CLK, DIV_CLK_AUD_NOCP, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK, DIV_CLK_AUD_CNT, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK, MUX_HCHGEN_CLK_AUD_CPU, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK, MUX_HCHGEN_CLK_AUD_CPU, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK, DIV_CLK_AUD_CPU_ACLK, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK, MUX_HCHGEN_CLK_AUD_CPU, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_CLKIN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_AUD_CPU_PCLKDBG, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK, DIV_CLK_AUD_DSIF, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK, DIV_CLK_AUD_PCMC, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF0, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF2, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF3, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF4, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF5, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF5_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF6, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF6_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK, DIV_CLK_AUD_NOCP, CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_TREX_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK1, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK1_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK1_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK2, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK2_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK2_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_SLH_AXI_SI_LD_AUDHSI0_IPCLKPORT_I_CLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LD_AUDHSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LD_AUDHSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AXI_SI_LD_AUDHSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_IPCLKPORT_CLK, MUX_HCHGEN_CLK_AUD_CPU, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKAUD_HSI0_NOC, PLL_AUD, CLK_CON_GAT_GATE_CLKAUD_HSI0_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKAUD_HSI0_NOC_MANUAL, CLK_CON_GAT_GATE_CLKAUD_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_AD_APB_VGEN_LITE_IPCLKPORT_PCLKM, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_VGEN_LITE_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_VGEN_LITE_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_AD_APB_VGEN_LITE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_CCLK, DIV_CLK_AUD_SERIAL_LIF_CORE, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_CCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_CCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK, DIV_CLK_AUD_SERIAL_LIF_CORE, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK, DIV_CLK_AUD_SERIAL_LIF, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK, CLK_AUD_MCLK, CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_BCLK, DIV_CLK_AUD_SERIAL_LIF, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_BCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_BCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_BCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_ACLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_SLH_AST_SI_G_PPMU_AUD_IPCLKPORT_I_CLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AST_SI_G_PPMU_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AST_SI_G_PPMU_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SLH_AST_SI_G_PPMU_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK, MUX_CLKVTS_AUD_DMIC0_USER, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK, MUX_CLKVTS_AUD_DMIC1_USER, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK, MUX_CLKVTS_AUD_DMIC0_USER, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK, MUX_CLKVTS_AUD_DMIC1_USER, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK, MUX_CLKVTS_AUD_DMIC0_USER, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK, MUX_CLKVTS_AUD_DMIC1_USER, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC0_IPCLKPORT_CLK, MUX_CLKVTS_AUD_DMIC0_USER, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC1_IPCLKPORT_CLK, MUX_CLKVTS_AUD_DMIC1_USER, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DMIC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_PCLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_SERIAL_LIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_PCLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_PCLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_PCLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMIC_AUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCD_IPCLKPORT_CLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK, DIV_CLK_AUD_DSIF, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF0, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF1, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF2, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF3, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF4, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF5, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF6, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCP_IPCLKPORT_CLK, DIV_CLK_AUD_NOCP, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK, DIV_CLK_AUD_SERIAL_LIF, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK, DIV_CLK_AUD_SERIAL_LIF_CORE, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_SERIAL_LIF_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC0_IPCLKPORT_CLK, MUX_CLKVTS_AUD_DMIC0_USER, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC1_IPCLKPORT_CLK, MUX_CLKVTS_AUD_DMIC1_USER, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DMIC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK, DIV_CLK_AUD_CNT, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_AUD, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_AUD, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_ACLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP, DIV_CLK_AUD_CPU_ACP, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK, DIV_CLK_AUD_CPU_ACP, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_BLK_AUD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_AUD, CLK_CON_GAT_CLK_BLK_AUD_UID_BLK_AUD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_BLK_AUD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_BLK_AUD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_LH_AXI_SI_PERI_ASB_IPCLKPORT_I_CLK, DIV_CLK_AUD_NOCP, CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_SI_PERI_ASB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_SI_PERI_ASB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_SI_PERI_ASB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_LH_AXI_MI_PERI_ASB_IPCLKPORT_I_CLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_MI_PERI_ASB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_MI_PERI_ASB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_LH_AXI_MI_PERI_ASB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_PCLK, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK, DIV_CLK_AUD_CPU_ACLK, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACP_IPCLKPORT_CLK, DIV_CLK_AUD_CPU_ACP, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ACP, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ACP_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ACP_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ACP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ASB, DIV_CLK_AUD_NOC, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ASB_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ASB_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ASB_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_CCLK, FREE_OSCCLK_AUD, CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_CCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_CCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_DMAILBOX_AUD_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_BRP_CMU_BRP_IPCLKPORT_PCLK, DIV_CLK_BRP_NOCP, CLK_CON_GAT_CLK_BLK_BRP_UID_BRP_CMU_BRP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_BRP_CMU_BRP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_BRP_CMU_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_AD_APB_BYRP_IPCLKPORT_PCLKM, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_BYRP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_BYRP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_BYRP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_D_TZPC_BRP_IPCLKPORT_PCLK, DIV_CLK_BRP_NOCP, CLK_CON_GAT_CLK_BLK_BRP_UID_D_TZPC_BRP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_D_TZPC_BRP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_D_TZPC_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_LH_AXI_SI_D0_BRP_IPCLKPORT_I_CLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D0_BRP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D0_BRP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D0_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_ACLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_PCLK, DIV_CLK_BRP_NOCP, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D0_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCP_IPCLKPORT_CLK, DIV_CLK_BRP_NOCP, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S1, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_SYSREG_BRP_IPCLKPORT_PCLK, DIV_CLK_BRP_NOCP, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSREG_BRP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSREG_BRP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSREG_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_XIU_D0_BRP_IPCLKPORT_ACLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D0_BRP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D0_BRP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D0_BRP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_SLH_AXI_MI_P_BRP_IPCLKPORT_I_CLK, DIV_CLK_BRP_NOCP, CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AXI_MI_P_BRP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AXI_MI_P_BRP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AXI_MI_P_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCD_IPCLKPORT_CLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_ZSL, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_ZSL_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_ZSL_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_ZSL_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_BYR, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_BYR_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_BYR_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_BYRP_IPCLKPORT_CLK_C2S_BYR_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S2, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D0_BRP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_VGEN_LITE_BYRP_IPCLKPORT_CLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_BYRP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_BYRP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_BYRP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_SLH_AST_SI_G_PPMU_BRP_IPCLKPORT_I_CLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AST_SI_G_PPMU_BRP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AST_SI_G_PPMU_BRP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_SLH_AST_SI_G_PPMU_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCD_IPCLKPORT_CLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_AD_APB_RGBP_IPCLKPORT_PCLKM, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_RGBP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_RGBP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_AD_APB_RGBP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_LH_AXI_SI_D1_BRP_IPCLKPORT_I_CLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D1_BRP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D1_BRP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D1_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_LH_AXI_SI_D2_BRP_IPCLKPORT_I_CLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D2_BRP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D2_BRP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AXI_SI_D2_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S1, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S2, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D2_BRP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S1, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S2, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_SYSMMU_D1_BRP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_ACLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_PCLK, DIV_CLK_BRP_NOCP, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D1_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_ACLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_PCLK, DIV_CLK_BRP_NOCP, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_PPMU_D2_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF0, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF0_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF0_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF1, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF1_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF1_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RGBP_IPCLKPORT_CLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_XIU_D1_BRP_IPCLKPORT_ACLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D1_BRP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D1_BRP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D1_BRP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_XIU_D2_BRP_IPCLKPORT_ACLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D2_BRP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D2_BRP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_XIU_D2_BRP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_VGEN_LITE_RGBP_IPCLKPORT_CLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_RGBP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_RGBP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_VGEN_LITE_RGBP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_LH_AST_SI_OTF0_BRPCSIS_IPCLKPORT_I_CLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF0_BRPCSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF0_BRPCSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF0_BRPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_LH_AST_MI_OTF_CSISBRP_IPCLKPORT_I_CLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_MI_OTF_CSISBRP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_MI_OTF_CSISBRP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_MI_OTF_CSISBRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_LH_AST_SI_OTF1_BRPCSIS_IPCLKPORT_I_CLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF1_BRPCSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF1_BRPCSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF1_BRPCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_LH_AST_SI_OTF_BRPMCSC_IPCLKPORT_I_CLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF_BRPMCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF_BRPMCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_LH_AST_SI_OTF_BRPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_L_SIU_BRP_IPCLKPORT_I_ACLK, DIV_CLK_BRP_NOC, CLK_CON_GAT_CLK_BLK_BRP_UID_L_SIU_BRP_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_L_SIU_BRP_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_L_SIU_BRP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCP_IPCLKPORT_CLK, DIV_CLK_BRP_NOCP, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_BLK_BRP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_BRP, CLK_CON_GAT_CLK_BLK_BRP_UID_BLK_BRP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_BLK_BRP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_BLK_BRP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_POWERIP_IPCLKPORT_CLK, MUX_CLKCMU_BRP_NOC_USER, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_POWERIP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_POWERIP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CH_CLK, CLK_BRP_ADD_CH_CLK, CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CH_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CH_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CLK, MUX_CLKCMU_BRP_NOC_USER, CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_ADD_BRP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_CLK_CORE, MUX_CLKCMU_BRP_NOC_USER, CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_PCLK, DIV_CLK_BRP_NOCP, CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_BUSIF_ADD_BRP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_POWERIP_IPCLKPORT_CLK, MUX_CLKCMU_BRP_NOC_USER, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_POWERIP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_POWERIP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_CLK_BRP_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_BRP, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BRP_UID_RSTNSYNC_SR_CLK_BRP_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK, RTCCLK_CHUB, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_TIMER_IPCLKPORT_CLK, MUX_CHUB_TIMER, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_TIMER_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_TIMER_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_TIMER_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_LH_AXI_MI_IP_VC2CHUB_IPCLKPORT_I_CLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_MI_IP_VC2CHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_MI_IP_VC2CHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_MI_IP_VC2CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_LH_AXI_SI_ID_CHUB2VC_IPCLKPORT_I_CLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_SI_ID_CHUB2VC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_SI_ID_CHUB2VC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_LH_AXI_SI_ID_CHUB2VC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_NOC_IPCLKPORT_CLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK, DIV_CLK_CHUB_I2C, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI0_IPCLKPORT_CLK, DIV_CLK_CHUB_USI0, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI1_IPCLKPORT_CLK, DIV_CLK_CHUB_USI1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI2_IPCLKPORT_CLK, DIV_CLK_CHUB_USI2, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI3_IPCLKPORT_CLK, DIV_CLK_CHUB_USI3, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_USI3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_PCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_PCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_IPCLK, DIV_CLK_CHUB_I2C, CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_I2C_CHUB_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_SCLK, DIV_CLK_CHUB_I2C, CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_I3C_CHUB_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK, DIV_CLK_CHUB_USI0, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK, DIV_CLK_CHUB_USI1, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK, DIV_CLK_CHUB_USI2, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK, DIV_CLK_CHUB_USI3, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_ASYNCINTERRUPT_IPCLKPORT_CLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_ASYNCINTERRUPT_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_ASYNCINTERRUPT_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_ASYNCINTERRUPT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_MAILBOX_CHUB_DNC_IPCLKPORT_PCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_DNC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_DNC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_PCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_PCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_SPI_MULTI_SLV_Q_CTRL_CHUB_IPCLKPORT_CLK, DIV_CLK_CHUB_SPI_MS_CTRL, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_MULTI_SLV_Q_CTRL_CHUB_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_MULTI_SLV_Q_CTRL_CHUB_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_MULTI_SLV_Q_CTRL_CHUB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_MS_CTRL_IPCLKPORT_CLK, DIV_CLK_CHUB_SPI_MS_CTRL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_MS_CTRL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_MS_CTRL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_MS_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_CHUB, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_IPCLK, DIV_CLK_CHUB_SPI_I2C0, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_IPCLK, DIV_CLK_CHUB_SPI_I2C1, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_SPI_I2C_CHUB1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C0_IPCLKPORT_CLK, DIV_CLK_CHUB_SPI_I2C0, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C1_IPCLKPORT_CLK, DIV_CLK_CHUB_SPI_I2C1, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_SPI_I2C1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_AXI2AHB_CHUB_IPCLKPORT_CLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_AXI2AHB_CHUB_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_AXI2AHB_CHUB_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_AXI2AHB_CHUB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_MAILBOX_CHUB_ABOX_IPCLKPORT_PCLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_MAILBOX_CHUB_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_NOC_IPCLKPORT_CLK, DIV_CLK_CHUB_NOC, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_I2C_IPCLKPORT_CLK, DIV_CLK_CHUB_I2C, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_CHUB, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_RSTNSYNC_SR_CLK_CHUB_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2VTS_IPCLKPORT_I_CLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2CHUB_IPCLKPORT_I_CLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2CHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2CHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_SI_IP_VC2CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_SWEEPER_LD_CHUBVTS_IPCLKPORT_ACLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SWEEPER_LD_CHUBVTS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SWEEPER_LD_CHUBVTS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SWEEPER_LD_CHUBVTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_BPS_LP_ALIVECHUBVTS_IPCLKPORT_I_CLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_ALIVECHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_ALIVECHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_ALIVECHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_CCLK, DIV_CLK_CHUBVTS_DMAILBOX_CCLK, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_CCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_CCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_PCLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_ACLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_DMAILBOX_CHUBVTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_VTS2VC_IPCLKPORT_I_CLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_VTS2VC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_VTS2VC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_VTS2VC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_PDMA_CHUBVTS_IPCLKPORT_ACLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_PDMA_CHUBVTS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_PDMA_CHUBVTS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_PDMA_CHUBVTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_CHUB2VC_IPCLKPORT_I_CLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_CHUB2VC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_CHUB2VC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_LH_AXI_MI_ID_CHUB2VC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_APBIF_UPMU_CHUB_IPCLKPORT_PCLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APBIF_UPMU_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APBIF_UPMU_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APBIF_UPMU_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_UPMU_CHUB_ACLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_UPMU_CHUB_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_UPMU_CHUB_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_UPMU_CHUB_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_RSTNSYNCH_CLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_RSTNSYNCH_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_RSTNSYNCH_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUB_ALV_IPCLKPORT_RSTNSYNCH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_SLH_AXI_SI_LD_CHUBVTS_IPCLKPORT_I_CLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_SI_LD_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_SI_LD_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_SI_LD_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_BPS_LP_DNCCHUBVTS_IPCLKPORT_I_CLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BPS_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_AUDCHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_NOC_IPCLKPORT_CLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_APB_SEMA_PDMA_IPCLKPORT_PCLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_PDMA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_PDMA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_PDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_APB_SEMA_DMAILBOX_IPCLKPORT_PCLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_DMAILBOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_DMAILBOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_APB_SEMA_DMAILBOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_NOC_IPCLKPORT_CLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_CHUBVTS, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_BLK_CHUBVTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_CHUBVTS, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BLK_CHUBVTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BLK_CHUBVTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BLK_CHUBVTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_DMAILBOX_CCLK_IPCLKPORT_CLK, DIV_CLK_CHUBVTS_DMAILBOX_CCLK, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_DMAILBOX_CCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_DMAILBOX_CCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_RSTNSYNC_SR_CLK_CHUBVTS_DMAILBOX_CCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_BAAW_LD_CHUBVTS_IPCLKPORT_I_PCLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_LD_CHUBVTS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_LD_CHUBVTS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_LD_CHUBVTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK, DIV_CLK_CHUBVTS_NOC, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK, DIV_CLK_CMGP_USI4, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK, DIV_CLK_CMGP_USI5, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK, DIV_CLK_CMGP_USI6, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK, DIV_CLK_CMGP_USI0, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK, DIV_CLK_CMGP_USI1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK, DIV_CLK_CMGP_USI2, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK, DIV_CLK_CMGP_USI3, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI0, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI1, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI2, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI3, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI4, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI5, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI6, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK, DIV_CLK_CMGP_SPI_MS_CTRL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK, DIV_CLK_CMGP_SPI_MS_CTRL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_CMGP, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK, DIV_CLK_CMGP_SPI_I2C0, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK, DIV_CLK_CMGP_SPI_I2C1, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK, DIV_CLK_CMGP_SPI_I2C0, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK, DIV_CLK_CMGP_SPI_I2C1, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK, MUX_CLKALIVE_CMGP_NOC_USER, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_ALIVE_NOC, MUX_CLKCMU_ALIVE_NOC, CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_HSI0_DPOSC, MUX_CLKCMU_HSI0_DPOSC, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKCMU_MIF01_SWITCH, MUX_CLKCMU_MIF_SWITCH, CLK_CON_GAT_CLKCMU_MIF01_SWITCH_CG_VAL, CLK_CON_GAT_CLKCMU_MIF01_SWITCH_MANUAL, CLK_CON_GAT_CLKCMU_MIF01_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MFC0_MFC0, MUX_CLKCMU_MFC0_MFC0, CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_HSI1_NOC, MUX_CLKCMU_HSI1_NOC, CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DPUF_ALT, MUX_CLKCMU_DPUF_ALT, CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIS_NOC, MUX_CLKCMU_PERIS_NOC, CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC0_NOC, MUX_CLKCMU_PERIC0_NOC, CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC1_NOC, MUX_CLKCMU_PERIC1_NOC, CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_BRP_NOC, MUX_CLKCMU_BRP_NOC, CLK_CON_GAT_GATE_CLKCMU_BRP_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_BRP_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_BRP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_YUVP_NOC, MUX_CLKCMU_YUVP_NOC, CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_AUD_CPU_SM, MUX_CLKCMU_AUD_CPU, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_HSI1_PCIE, MUX_CLKCMU_HSI1_PCIE, CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CIS_CLK0, MUX_CLKCMU_CIS_CLK0, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CIS_CLK1, MUX_CLKCMU_CIS_CLK1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CIS_CLK3, MUX_CLKCMU_CIS_CLK3, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CIS_CLK2, MUX_CLKCMU_CIS_CLK2, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MFC0_WFD, MUX_CLKCMU_MFC0_WFD, CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MIF_NOCP, MUX_CLKCMU_MIF_NOCP, CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC0_IP0, MUX_CLKCMU_PERIC0_IP0, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC1_IP0, MUX_CLKCMU_PERIC1_IP0, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DPUF, MUX_CLKCMU_DPUF, CLK_CON_GAT_GATE_CLKCMU_DPUF_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DPUF_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DPUF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_HSI0_NOC, MUX_CLKCMU_HSI0_NOC, CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CIS_CLK4, MUX_CLKCMU_CIS_CLK4, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CSIS_NOC, MUX_CLKCMU_CSIS_NOC, CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MCSC_NOC_SM, MUX_CLKCMU_MCSC_NOC, CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CSIS_OIS_MCU, MUX_CLKCMU_CSIS_OIS_MCU, CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CIS_CLK5, MUX_CLKCMU_CIS_CLK5, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_M2M_NOC_SM, MUX_CLKCMU_M2M_NOC, CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DPUB_ALT, MUX_CLKCMU_DPUB_ALT, CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DPUB, MUX_CLKCMU_DPUB, CLK_CON_GAT_GATE_CLKCMU_DPUB_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DPUB_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DPUB_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MFC1_MFC1, MUX_CLKCMU_MFC1_MFC1, CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_LME_NOC, MUX_CLKCMU_LME_NOC, CLK_CON_GAT_GATE_CLKCMU_LME_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_LME_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_LME_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_HSI0_USB32DRD, MUX_CLKCMU_HSI0_USB32DRD, CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_HSI0_DPGTC, MUX_CLKCMU_HSI0_DPGTC, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_AUD_NOC, MUX_CLKCMU_AUD_NOC, CLK_CON_GAT_GATE_CLKCMU_AUD_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_AUD_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_AUD_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CSIS_DCPHY, MUX_CLKCMU_CSIS_DCPHY, CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CP_SHARED1_CLK, MUX_CP_SHARED1_CLK, CLK_CON_GAT_GATE_CP_SHARED1_CLK_CG_VAL, CLK_CON_GAT_GATE_CP_SHARED1_CLK_MANUAL, CLK_CON_GAT_GATE_CP_SHARED1_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC0_IP1, MUX_CLKCMU_PERIC0_IP1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC1_IP1, MUX_CLKCMU_PERIC1_IP1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_SSP_NOC, MUX_CLKCMU_SSP_NOC, CLK_CON_GAT_GATE_CLKCMU_SSP_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_SSP_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_SSP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC2_IP0, MUX_CLKCMU_PERIC2_IP0, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC2_NOC, MUX_CLKCMU_PERIC2_NOC, CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIC2_IP1, MUX_CLKCMU_PERIC2_IP1, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKCMU_MIF23_SWITCH, MUX_CLKCMU_MIF_SWITCH, CLK_CON_GAT_CLKCMU_MIF23_SWITCH_CG_VAL, CLK_CON_GAT_CLKCMU_MIF23_SWITCH_MANUAL, CLK_CON_GAT_CLKCMU_MIF23_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CPUCL0_NOCP, MUX_CLKCMU_CPUCL0_NOCP, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_G3D_NOCP, MUX_CLKCMU_G3D_NOCP, CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CSTAT_NOC, MUX_CLKCMU_CSTAT_NOC, CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DPUB_DSIM, MUX_CLKCMU_DPUB_DSIM, CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CIS_CLK6, MUX_CLKCMU_CIS_CLK6, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_NOCL1A_NOC_SM, MUX_CLKCMU_NOCL1A_NOC, CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_NOCL0_NOC_SM, MUX_CLKCMU_NOCL0_NOC, CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CPUCL0_SWITCH_SM, MUX_CLKCMU_CPUCL0_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CPUCL1_SWITCH_SM, MUX_CLKCMU_CPUCL1_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CPUCL2_SWITCH_SM, MUX_CLKCMU_CPUCL2_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DSU_SWITCH_SM, MUX_CLKCMU_DSU_SWITCH, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CPUCL0_DBG_NOC_SM, MUX_CLKCMU_CPUCL0_DBG_NOC, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DNC_NOC_SM, MUX_CLKCMU_DNC_NOC, CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_SDMA_NOC_SM, MUX_CLKCMU_SDMA_NOC, CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_GNPU_NOC_SM, MUX_CLKCMU_GNPU_NOC, CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DSP_NOC_SM, MUX_CLKCMU_DSP_NOC, CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CP_SHARED0_CLK_SM, MUX_CP_SHARED0_CLK, CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM_CG_VAL, CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM_MANUAL, CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CP_HISPEEDY_CLK_SM, MUX_CP_HISPEEDY_CLK, CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM_CG_VAL, CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM_MANUAL, CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_G3D_SWITCH_SM, MUX_CLKCMU_G3D_SWITCH, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CP_SHARED2_CLK_SM, MUX_CP_SHARED2_CLK, CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM_CG_VAL, CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM_MANUAL, CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_NOCL1C_NOC_SM, MUX_CLKCMU_NOCL1C_NOC, CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_NOCL1B_NOC0_SM, MUX_CLKCMU_NOCL1B_NOC0, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CMU_BOOST, MUX_CLKCMU_CMU_BOOST, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CMU_BOOST_CPU, MUX_CLKCMU_CMU_BOOST_CPU, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CMU_BOOST_CPU_MIF, MUX_CLKCMU_CMU_BOOST_MIF, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CMU_BOOST_CAM, MUX_CLKCMU_CMU_BOOST_CAM, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_VTS_DMIC, MUX_CLKCMU_VTS_DMIC, CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_AUD_AUDIF0_SM, MUX_CLKCMU_AUD_AUDIF0, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_AUD_AUDIF1_SM, MUX_CLKCMU_AUD_AUDIF1, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_PERIS_GIC, MUX_CLKCMU_PERIS_GIC, CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CIS_CLK7, MUX_CLKCMU_CIS_CLK7, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_NOCL1B_NOC1, MUX_CLKCMU_NOCL1B_NOC1, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_LME_LME, MUX_CLKCMU_LME_LME, CLK_CON_GAT_GATE_CLKCMU_LME_LME_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_LME_LME_MANUAL, CLK_CON_GAT_GATE_CLKCMU_LME_LME_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_M2M_FRC_SM, MUX_CLKCMU_M2M_FRC, CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MCSC_MCSC_SM, MUX_CLKCMU_MCSC_MCSC, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_UFS_MMC_CARD_SM, MUX_CLKCMU_UFS_MMC_CARD, CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_UFS_UFS_EMBD, MUX_CLKCMU_UFS_UFS_EMBD, CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_UFS_NOC, MUX_CLKCMU_UFS_NOC, CLK_CON_GAT_GATE_CLKCMU_UFS_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_UFS_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_UFS_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_AUD_CPU, MUX_CLKCMU_AUD_CPU, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_MANUAL, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_AUD_AUDIF0, MUX_CLKCMU_AUD_AUDIF0, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_AUD_AUDIF1, MUX_CLKCMU_AUD_AUDIF1, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CPUCL0_SWITCH, MUX_CLKCMU_CPUCL0_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CPUCL1_SWITCH, MUX_CLKCMU_CPUCL1_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CPUCL2_SWITCH, MUX_CLKCMU_CPUCL2_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DSU_SWITCH, MUX_CLKCMU_DSU_SWITCH, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_CPUCL0_DBG_NOC, MUX_CLKCMU_CPUCL0_DBG_NOC, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DNC_NOC, MUX_CLKCMU_DNC_NOC, CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_SDMA_NOC, MUX_CLKCMU_SDMA_NOC, CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_DSP_NOC, MUX_CLKCMU_DSP_NOC, CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_G3D_SWITCH, MUX_CLKCMU_G3D_SWITCH, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_GNPU_NOC, MUX_CLKCMU_GNPU_NOC, CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_M2M_NOC, MUX_CLKCMU_M2M_NOC, CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_M2M_FRC, MUX_CLKCMU_M2M_FRC, CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MCSC_NOC, MUX_CLKCMU_MCSC_NOC, CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_MCSC_MCSC, MUX_CLKCMU_MCSC_MCSC, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_NOCL0_NOC, MUX_CLKCMU_NOCL0_NOC, CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_NOCL1A_NOC, MUX_CLKCMU_NOCL1A_NOC, CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_NOCL1B_NOC0, MUX_CLKCMU_NOCL1B_NOC0, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_NOCL1C_NOC, MUX_CLKCMU_NOCL1C_NOC, CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CP_HISPEEDY_CLK, MUX_CP_HISPEEDY_CLK, CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_CG_VAL, CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_MANUAL, CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CP_SHARED2_CLK, MUX_CP_SHARED2_CLK, CLK_CON_GAT_GATE_CP_SHARED2_CLK_CG_VAL, CLK_CON_GAT_GATE_CP_SHARED2_CLK_MANUAL, CLK_CON_GAT_GATE_CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CP_SHARED0_CLK, MUX_CP_SHARED0_CLK, CLK_CON_GAT_GATE_CP_SHARED0_CLK_CG_VAL, CLK_CON_GAT_GATE_CP_SHARED0_CLK_MANUAL, CLK_CON_GAT_GATE_CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(GATE_CLKCMU_UFS_MMC_CARD, MUX_CLKCMU_UFS_MMC_CARD, CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK, MUX_CLK_CPUCL0_POWERIP, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE, MUX_CLK_CPUCL0_POWERIP, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE, MUX_CLK_CPUCL0_POWERIP, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK, MUX_CLK_CPUCL0_POWERIP, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_ADD_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_BUSIF_STR_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK, CLK_CPUCL0_ADD_CH_CLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_ADD_CPUCL0_0_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CPUCL0_CPM, PLL_CPUCL0, CLK_CON_GAT_CPUCL0_CPM_CG_VAL, CLK_CON_GAT_CPUCL0_CPM_MANUAL, CLK_CON_GAT_CPUCL0_CPM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX0CLK, DIV_CLK_CPUCL0_CORE, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX0CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX0CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX0CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX1CLK, DIV_CLK_CPUCL0_CORE, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX1CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX1CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_COMPLEX1CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_STR_CPUCL0_0_IPCLKPORT_DEM_CLK, CLK_CPUCL0_ADD_CH_CLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_STR_CPUCL0_0_IPCLKPORT_DEM_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_STR_CPUCL0_0_IPCLKPORT_DEM_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_STR_CPUCL0_0_IPCLKPORT_DEM_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_HTU_IPCLKPORT_CLK, MUX_CLK_CPUCL0_HTU, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK, MUX_CLK_CPUCL0_HTU, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK, MUX_CLK_CPUCL0_POWERIP, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_SR_CLK_CPUCL0_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_IPCLKPORT_PCLKM, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_ETR_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_ETR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_ETR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_STM_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_STM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_STM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_IG_STM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_LH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_ETR_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_ETR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_ETR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_TREX_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_STM_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_STM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_STM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_IG_STM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_PMU_PCSM_PM_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_PMU_PCSM_PM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_PMU_PCSM_PM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_PMU_PCSM_PM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_0_IPCLKPORT_PCLK_S0, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_0_IPCLKPORT_PCLK_S0_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_0_IPCLKPORT_PCLK_S0_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_0_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_1_IPCLKPORT_PCLK_S0, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_1_IPCLKPORT_PCLK_S0_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_1_IPCLKPORT_PCLK_S0_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BUSIF_DDC_CPUCL0_1_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCDSU_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCDSU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCDSU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCDSU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_DDCG3D_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_DDCG3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_DDCG3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_T_DDCG3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCLIT_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCLIT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCLIT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCLIT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID1_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID2_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCMID2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCBIG_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCBIG_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCBIG_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_LH_ATB_MI_IT_DDCBIG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_CFM_CPUCL0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CFM_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CFM_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CFM_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_CPUCL0_GLB, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_OTP_DESERIAL_SECJTAG_IPCLKPORT_I_CLK, FREE_OSCCLK_CPUCL0_GLB, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_OTP_DESERIAL_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_OTP_DESERIAL_SECJTAG_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_OTP_DESERIAL_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_BLK_CPUCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_CPUCL0_GLB, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BLK_CPUCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BLK_CPUCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_BLK_CPUCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_GLB_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_CPUCL0_GLB, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_RSTNSYNC_SR_CLK_CPUCL0_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK, MUX_CLK_CPUCL1_POWERIP, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE, MUX_CLK_CPUCL1_POWERIP, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE, MUX_CLK_CPUCL1_POWERIP, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_CLK, MUX_CLK_CPUCL1_HTU, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK, MUX_CLK_CPUCL1_POWERIP, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_HTU_IPCLKPORT_CLK, MUX_CLK_CPUCL1_HTU, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_ADD_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_BUSIF_STR_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK, CLK_CPUCL1_ADD_CH_CLK, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_ADD_CPUCL0_1_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CPUCL1_CPM0, PLL_CPUCL1, CLK_CON_GAT_CPUCL1_CPM0_CG_VAL, CLK_CON_GAT_CPUCL1_CPM0_MANUAL, CLK_CON_GAT_CPUCL1_CPM0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CPUCL1_CPM1, PLL_CPUCL1, CLK_CON_GAT_CPUCL1_CPM1_CG_VAL, CLK_CON_GAT_CPUCL1_CPM1_MANUAL, CLK_CON_GAT_CPUCL1_CPM1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CPUCL1_CPM2, PLL_CPUCL1, CLK_CON_GAT_CPUCL1_CPM2_CG_VAL, CLK_CON_GAT_CPUCL1_CPM2_MANUAL, CLK_CON_GAT_CPUCL1_CPM2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_CLK, MUX_CLK_CPUCL1_HTU, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_CLK, MUX_CLK_CPUCL1_HTU, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HTU_CPUCL1_2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_STR_CPUCL0_1_IPCLKPORT_DEM_CLK, CLK_CPUCL1_ADD_CH_CLK, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_STR_CPUCL0_1_IPCLKPORT_DEM_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_STR_CPUCL0_1_IPCLKPORT_DEM_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_STR_CPUCL0_1_IPCLKPORT_DEM_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK, MUX_CLK_CPUCL1_POWERIP, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_RSTNSYNC_SR_CLK_CPUCL1_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK, MUX_CLK_CPUCL2_POWERIP, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE, MUX_CLK_CPUCL2_POWERIP, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE, MUX_CLK_CPUCL2_POWERIP, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK, MUX_CLK_CPUCL2_HTU, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK, MUX_CLK_CPUCL2_POWERIP, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_HTU_IPCLKPORT_CLK, MUX_CLK_CPUCL2_HTU, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_ADD_CPUCL0_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_BUSIF_STR_CPUCL0_2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_HTU_CPUCL2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK, CLK_CPUCL2_ADD_CH_CLK, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_ADD_CPUCL0_2_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CPUCL2_CPM, PLL_CPUCL2, CLK_CON_GAT_CPUCL2_CPM_CG_VAL, CLK_CON_GAT_CPUCL2_CPM_MANUAL, CLK_CON_GAT_CPUCL2_CPM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_STR_CPUCL0_2_IPCLKPORT_DEM_CLK, CLK_CPUCL2_ADD_CH_CLK, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_STR_CPUCL0_2_IPCLKPORT_DEM_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_STR_CPUCL0_2_IPCLKPORT_DEM_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_STR_CPUCL0_2_IPCLKPORT_DEM_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK, MUX_CLK_CPUCL2_POWERIP, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_RSTNSYNC_SR_CLK_CPUCL2_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKCSIS_ALLCSIS_NOCD, MUX_CLK_CSIS_NOC, CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCD_CG_VAL, CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCD_MANUAL, CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKCSIS_ALLCSIS_NOCP, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCP_CG_VAL, CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCP_MANUAL, CLK_CON_GAT_CLKCSIS_ALLCSIS_NOCP_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKCSIS_ALLCSIS_OIC_MCU, MUX_CLKCMU_CSIS_OIS_MCU_USER, CLK_CON_GAT_CLKCSIS_ALLCSIS_OIC_MCU_CG_VAL, CLK_CON_GAT_CLKCSIS_ALLCSIS_OIC_MCU_MANUAL, CLK_CON_GAT_CLKCSIS_ALLCSIS_OIC_MCU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_CLK_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0, MUX_CLK_CSIS_NOC, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1, MUX_CLK_CSIS_NOC, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2, MUX_CLK_CSIS_NOC, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3, MUX_CLK_CSIS_NOC, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4, MUX_CLK_CSIS_NOC, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5, MUX_CLK_CSIS_NOC, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS6, MUX_CLK_CSIS_NOC, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS6_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS6_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS6_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_I_FD_ACLK, MUX_CLK_CSIS_NOC, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_I_FD_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_I_FD_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_I_FD_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS0, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS0_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS0_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS1, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS1_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS1_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS2, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS2_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS2_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS4, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS4_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS4_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS4_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS3, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS3_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS3_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS5, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS5_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS5_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS5_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS6, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS6_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS6_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_PCLK_CSIS6_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_XIU_P1_CSIS_IPCLKPORT_ACLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_CLK_BLK_CSIS_UID_XIU_P1_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_XIU_P1_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_XIU_P1_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_AD_APB_MIPI_PHY_IPCLKPORT_PCLKM, DIV_CLK_CSIS_DCPHY, CLK_CON_GAT_CLK_BLK_CSIS_UID_AD_APB_MIPI_PHY_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_AD_APB_MIPI_PHY_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_AD_APB_MIPI_PHY_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_SLH_AXI_MI_LP_UFDCSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AXI_MI_LP_UFDCSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AXI_MI_LP_UFDCSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AXI_MI_LP_UFDCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_CLK_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_SLH_AST_SI_OTF_CSISUFD_IPCLKPORT_I_CLK, MUX_CLK_CSIS_NOC, CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AST_SI_OTF_CSISUFD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AST_SI_OTF_CSISUFD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_SLH_AST_SI_OTF_CSISUFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_LH_AXI_MI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_CLK_BLK_CSIS_UID_LH_AXI_MI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_LH_AXI_MI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_LH_AXI_MI_LP_INT_P0P1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_DCPHY_IPCLKPORT_CLK, DIV_CLK_CSIS_DCPHY, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_DCPHY_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_DCPHY_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_DCPHY_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK, MUX_CLK_CSIS_NOC, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCD_IPCLKPORT_CLK, MUX_CLK_CSIS_NOC, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCP_IPCLKPORT_CLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_CSTAT_CMU_CSTAT_IPCLKPORT_PCLK, DIV_CLK_CSTAT_NOCP, CLK_CON_GAT_CLK_BLK_CSTAT_UID_CSTAT_CMU_CSTAT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_CSTAT_CMU_CSTAT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_CSTAT_CMU_CSTAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_D_TZPC_CSTAT_IPCLKPORT_PCLK, DIV_CLK_CSTAT_NOCP, CLK_CON_GAT_CLK_BLK_CSTAT_UID_D_TZPC_CSTAT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_D_TZPC_CSTAT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_D_TZPC_CSTAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_AD_APB_CSTAT0_IPCLKPORT_PCLKM, MUX_CLKCMU_CSTAT_NOC_USER, CLK_CON_GAT_CLK_BLK_CSTAT_UID_AD_APB_CSTAT0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_AD_APB_CSTAT0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_AD_APB_CSTAT0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_SLH_AXI_MI_P_CSTAT_IPCLKPORT_I_CLK, DIV_CLK_CSTAT_NOCP, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AXI_MI_P_CSTAT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AXI_MI_P_CSTAT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AXI_MI_P_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_ACLK, MUX_CLKCMU_CSTAT_NOC_USER, CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_PCLK, DIV_CLK_CSTAT_NOCP, CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_PPMU_CSTAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S1, MUX_CLKCMU_CSTAT_NOC_USER, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_LH_AXI_SI_D_CSTAT_IPCLKPORT_I_CLK, MUX_CLKCMU_CSTAT_NOC_USER, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AXI_SI_D_CSTAT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AXI_SI_D_CSTAT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AXI_SI_D_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_SYSREG_CSTAT_IPCLKPORT_PCLK, DIV_CLK_CSTAT_NOCP, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSREG_CSTAT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSREG_CSTAT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSREG_CSTAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_XIU_D_CSTAT_IPCLKPORT_ACLK, MUX_CLKCMU_CSTAT_NOC_USER, CLK_CON_GAT_CLK_BLK_CSTAT_UID_XIU_D_CSTAT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_XIU_D_CSTAT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_XIU_D_CSTAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_CSTAT_NOC_USER, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCP_IPCLKPORT_CLK, DIV_CLK_CSTAT_NOCP, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_CLK_CSTAT_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_LH_AST_MI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK, MUX_CLKCMU_CSTAT_NOC_USER, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF0_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_LH_AST_MI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK, MUX_CLKCMU_CSTAT_NOC_USER, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF1_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_LH_AST_MI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK, MUX_CLKCMU_CSTAT_NOC_USER, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF2_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_LH_AST_MI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK, MUX_CLKCMU_CSTAT_NOC_USER, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_LH_AST_MI_OTF3_CSISCSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK, MUX_CLKCMU_CSTAT_NOC_USER, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2RD, MUX_CLKCMU_CSTAT_NOC_USER, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2RD_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2RD_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2RD_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2DS, MUX_CLKCMU_CSTAT_NOC_USER, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2DS_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2DS_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SIPU_CSTAT_IPCLKPORT_I_CLK_C2DS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S2, MUX_CLKCMU_CSTAT_NOC_USER, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SYSMMU_D_CSTAT_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT0_IPCLKPORT_CLK, MUX_CLKCMU_CSTAT_NOC_USER, CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT1_IPCLKPORT_CLK, MUX_CLKCMU_CSTAT_NOC_USER, CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_VGEN_LITE_CSTAT1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_SLH_AST_SI_G_PPMU_CSTAT_IPCLKPORT_I_CLK, MUX_CLKCMU_CSTAT_NOC_USER, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AST_SI_G_PPMU_CSTAT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AST_SI_G_PPMU_CSTAT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_SLH_AST_SI_G_PPMU_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_CSTAT_NOC_USER, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCP_IPCLKPORT_CLK, DIV_CLK_CSTAT_NOCP, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_RSTNSYNC_SR_CLK_CSTAT_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_CSTAT_UID_BLK_CSTAT_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_CSTAT, CLK_CON_GAT_CLK_BLK_CSTAT_UID_BLK_CSTAT_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_BLK_CSTAT_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSTAT_UID_BLK_CSTAT_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_AHB_BUSMATRIX_DBGCORE_IPCLKPORT_HCLK, MUX_CLK_DBGCORE_NOC, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_AHB_BUSMATRIX_DBGCORE_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_AHB_BUSMATRIX_DBGCORE_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_AHB_BUSMATRIX_DBGCORE_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_GREBEINTEGRATION_DBGCORE_IPCLKPORT_HCLK, MUX_CLK_DBGCORE_NOC, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_GREBEINTEGRATION_DBGCORE_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_GREBEINTEGRATION_DBGCORE_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_GREBEINTEGRATION_DBGCORE_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_NOC_IPCLKPORT_CLK, MUX_CLK_DBGCORE_NOC, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_SLH_AXI_MI_IP_APM_IPCLKPORT_I_CLK, MUX_CLK_DBGCORE_NOC, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_MI_IP_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_MI_IP_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_MI_IP_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK, MUX_CLK_DBGCORE_NOC, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK, MUX_CLK_DBGCORE_NOC, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_SLH_AXI_SI_ID_DBGCORE_IPCLKPORT_I_CLK, MUX_CLK_DBGCORE_NOC, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_ID_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_ID_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SLH_AXI_SI_ID_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_IPCLKPORT_PCLK, MUX_CLK_DBGCORE_NOC, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_WDT_DBGCORE_IPCLKPORT_PCLK, MUX_CLK_DBGCORE_NOC, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_WDT_DBGCORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_WDT_DBGCORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_WDT_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_XHB_DBGCORE_IPCLKPORT_CLK, MUX_CLK_DBGCORE_NOC, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_XHB_DBGCORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_XHB_DBGCORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_XHB_DBGCORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_DBGCORE_CMU_DBGCORE_IPCLKPORT_PCLK, MUX_CLK_DBGCORE_NOC, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_DBGCORE_CMU_DBGCORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_DBGCORE_CMU_DBGCORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_DBGCORE_CMU_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_GREBE_IPCLKPORT_CLK, MUX_CLK_DBGCORE_NOC, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_GREBE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_GREBE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_GREBE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_PCLK, MUX_CLK_DBGCORE_NOC, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_CORE_IPCLKPORT_PCLK, MUX_CLK_DBGCORE_NOC, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SYSREG_DBGCORE_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_D_TZPC_DBGCORE_IPCLKPORT_PCLK, MUX_CLK_DBGCORE_NOC, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_D_TZPC_DBGCORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_D_TZPC_DBGCORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_D_TZPC_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_APBIF_S2D_DBGCORE_IPCLKPORT_I_PCLK, MUX_CLK_DBGCORE_NOC, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_APBIF_S2D_DBGCORE_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_APBIF_S2D_DBGCORE_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_APBIF_S2D_DBGCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_ASYNCAHBMASTER_DBGCORE_IPCLKPORT_HCLKM, MUX_FREE_OSCCLK_DBGCORE, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_ASYNCAHBMASTER_DBGCORE_IPCLKPORT_HCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_ASYNCAHBMASTER_DBGCORE_IPCLKPORT_HCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_ASYNCAHBMASTER_DBGCORE_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_OSCCLK, MUX_FREE_OSCCLK_DBGCORE, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_OSCCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_OSCCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_MDIS_DBGCORE_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_FREE_OSCCLK_IPCLKPORT_CLK, MUX_FREE_OSCCLK_DBGCORE, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_CLK_DBGCORE_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_RSTNSYNC_SR_CLK_DBGCORE_NOC_IPCLKPORT_CLK, MUX_CLK_DBGCORE_NOC, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_SR_CLK_DBGCORE_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_SR_CLK_DBGCORE_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_RSTNSYNC_SR_CLK_DBGCORE_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DBGCORE_UID_SS_DBGCORE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_DBGCORE, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SS_DBGCORE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SS_DBGCORE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DBGCORE_UID_SS_DBGCORE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SHMEM_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SHMEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SHMEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SHMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU0DNC_SHMEM_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU0DNC_SHMEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU0DNC_SHMEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU0DNC_SHMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU1DNC_SHMEM_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU1DNC_SHMEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU1DNC_SHMEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_GNPU1DNC_SHMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_DNC_CMU_DNC_IPCLKPORT_PCLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_DNC_CMU_DNC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_DNC_CMU_DNC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_DNC_CMU_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU0_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SFR_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_DSP0DNC_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU1_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_CMDQ_GNPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SLH_AXI_MI_P_DNC_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_P_DNC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_P_DNC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_P_DNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU0_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_MI_LP_IPDNC_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LP_IPDNC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LP_IPDNC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LP_IPDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU1_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD1_GNPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_SI_LP_IPDNC_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_IPDNC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_IPDNC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_IPDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_ADM_DAP_DNC_IPCLKPORT_DAPCLKM, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_ADM_DAP_DNC_IPCLKPORT_DAPCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_ADM_DAP_DNC_IPCLKPORT_DAPCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_ADM_DAP_DNC_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU0_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU1_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_RQ_GNPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SLH_AXI_MI_LD_DSP0DNC_CACHE_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_DSP0DNC_CACHE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_DSP0DNC_CACHE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_DSP0DNC_CACHE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU0_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU1_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD0_GNPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_DMA_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_DMA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_DMA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_DMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SYSREG_DNC_IPCLKPORT_PCLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSREG_DNC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSREG_DNC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSREG_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_SFR_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_SFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_SFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_DNCDSP0_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_D_TZPC_DNC_IPCLKPORT_PCLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_D_TZPC_DNC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_D_TZPC_DNC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_D_TZPC_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU1_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU0_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LD_CTRL_GNPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_MI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCD_IPCLKPORT_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCP_IPCLKPORT_CLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_ACLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_PCLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_IPDNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_ACLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_PCLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_ACLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_PCLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_ACLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_PCLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_ACLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_PCLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_PPMU_SDMA3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S1, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S1, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S2, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S2, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_IPDNC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S1, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S2, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S1, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S2, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA2_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S1, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S2, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SYSMMU_SDMA3_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_ACLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_PCLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_TREX_D_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_APBAS_S1_NS_SDMA0_IPCLKPORT_PCLKM, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_APBAS_S1_NS_SDMA0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_APBAS_S1_NS_SDMA0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_APBAS_S1_NS_SDMA0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_CLK, MUX_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_PCLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_HTU_DNC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_PCLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_PCLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_CLK_CORE, MUX_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_ADD_DNC_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CH_CLK, CLK_DNC_ADD_CH_CLK, CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CH_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CH_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DNCCHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_BAAW_DNCCHUBVTS_IPCLKPORT_I_PCLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_BAAW_DNCCHUBVTS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_BAAW_DNCCHUBVTS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_BAAW_DNCCHUBVTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_POWERIP_IPCLKPORT_CLK, MUX_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_POWERIP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_POWERIP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_ATCLK, DIV_CLK_DNC_DDD_CTRL, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_ATCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_ATCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_BUSIF_DDD_DNC_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CLK, MUX_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_ADD_DNC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_DDD_DNC_IPCLKPORT_CK_IN, MUX_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_DDD_DNC_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_DDD_DNC_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_DDD_DNC_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AXI_SI_LP_DNCSDMA_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_DNCSDMA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_DNCSDMA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AXI_SI_LP_DNCSDMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SIU_G_PPMU_DNC_IPCLKPORT_I_ACLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_SIU_G_PPMU_DNC_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SIU_G_PPMU_DNC_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SIU_G_PPMU_DNC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SLH_AST_SI_G_PPMU_DNC_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AST_SI_G_PPMU_DNC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AST_SI_G_PPMU_DNC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AST_SI_G_PPMU_DNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU0_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU1_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_GNPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SLH_AXI_MI_LP_ALIVEDNC_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LP_ALIVEDNC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LP_ALIVEDNC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LP_ALIVEDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_VGEN_DNC_IPCLKPORT_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_DNC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_DNC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_DNC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_VGEN_LITE_DNC_IPCLKPORT_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_LITE_DNC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_LITE_DNC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_VGEN_LITE_DNC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCD_IPCLKPORT_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SLH_AXI_MI_LD_UFDDNC_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_UFDDNC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_UFDDNC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_MI_LD_UFDDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_DNC, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_XIU_P_DNC_IPCLKPORT_ACLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_XIU_P_DNC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_XIU_P_DNC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_XIU_P_DNC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AST_MI_OTF_UFDDNC_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_MI_OTF_UFDDNC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_MI_OTF_UFDDNC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_MI_OTF_UFDDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_LH_AST_GLUE_OTF_UFDDNC_IPCLKPORT_CLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_GLUE_OTF_UFDDNC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_GLUE_OTF_UFDDNC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_LH_AST_GLUE_OTF_UFDDNC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCP_IPCLKPORT_CLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DSP0_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DSP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DSP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_DSP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_SLH_AXI_SI_LP_SDMA_IPCLKPORT_I_CLK, DIV_CLK_DNC_NOCP, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_SDMA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_SDMA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_SLH_AXI_SI_LP_SDMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_BLK_DNC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_DNC, CLK_CON_GAT_CLK_BLK_DNC_UID_BLK_DNC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_BLK_DNC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_BLK_DNC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_POWERIP_IPCLKPORT_CLK, MUX_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_POWERIP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_POWERIP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_DNC, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_DDD_CTRL_IPCLKPORT_CLK, DIV_CLK_DNC_DDD_CTRL, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_DDD_CTRL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_DDD_CTRL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_RSTNSYNC_SR_CLK_DNC_DDD_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_DAPCLK, DIV_CLK_DNC_NOC, CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_DAPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_DAPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNC_UID_IP_DNC_IPCLKPORT_DAPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK, DIV_CLK_DPUB_NOCP, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_CMU_DPUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM, MUX_CLKCMU_DPUB_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON, MUX_CLKCMU_DPUB_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON_MANUAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ACLK_DECON_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK, DIV_CLK_DPUB_NOCP, CLK_CON_GAT_CLK_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_D_TZPC_DPUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUB_UID_SLH_AXI_MI_P_DPUB_IPCLKPORT_I_CLK, DIV_CLK_DPUB_NOCP, CLK_CON_GAT_CLK_BLK_DPUB_UID_SLH_AXI_MI_P_DPUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_SLH_AXI_MI_P_DPUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_SLH_AXI_MI_P_DPUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_DPUB_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCP_IPCLKPORT_CLK, DIV_CLK_DPUB_NOCP, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_CLK_DPUB_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK, DIV_CLK_DPUB_NOCP, CLK_CON_GAT_CLK_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_SYSREG_DPUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM1, MUX_CLKCMU_DPUB_DSIM_USER, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM1_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM1_MANUAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM2, MUX_CLKCMU_DPUB_DSIM_USER, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM2_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM2_MANUAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM0, MUX_CLKCMU_DPUB_DSIM_USER, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM0_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM0_MANUAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_ALVCLK_DSIM0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUB_UID_UPI_M0_IPCLKPORT_PCLK, DIV_CLK_DPUB_NOCP, CLK_CON_GAT_CLK_BLK_DPUB_UID_UPI_M0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_UPI_M0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_UPI_M0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_DPUB_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCP_IPCLKPORT_CLK, DIV_CLK_DPUB_NOCP, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_RSTNSYNC_SR_CLK_DPUB_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM0, FREE_OSCCLK_DPUB, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM0_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM0_MANUAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM1, FREE_OSCCLK_DPUB, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM1_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM1_MANUAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM2, FREE_OSCCLK_DPUB, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM2_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM2_MANUAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_DPUB_IPCLKPORT_OSCCLK_DSIM2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUB_UID_BLK_DPUB_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_DPUB, CLK_CON_GAT_CLK_BLK_DPUB_UID_BLK_DPUB_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_BLK_DPUB_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUB_UID_BLK_DPUB_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_DPUF_CMU_DPUF_IPCLKPORT_PCLK, DIV_CLK_DPUF_NOCP, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_CMU_DPUF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_CMU_DPUF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_CMU_DPUF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF0_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF0, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF0_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF0_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_D_TZPC_DPUF_IPCLKPORT_PCLK, DIV_CLK_DPUF_NOCP, CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_SLH_AXI_MI_P_DPUF_IPCLKPORT_I_CLK, DIV_CLK_DPUF_NOCP, CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_MI_P_DPUF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_MI_P_DPUF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_MI_P_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_LH_AXI_SI_D1_DPUF_IPCLKPORT_I_CLK, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_LH_AXI_SI_D1_DPUF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_LH_AXI_SI_D1_DPUF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_LH_AXI_SI_D1_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_ACLK, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_PCLK, DIV_CLK_DPUF_NOCP, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_ACLK, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_PCLK, DIV_CLK_DPUF_NOCP, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCP_IPCLKPORT_CLK, DIV_CLK_DPUF_NOCP, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_CLK_DPUF_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S2, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S1, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_SYSREG_DPUF_IPCLKPORT_PCLK, DIV_CLK_DPUF_NOCP, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSREG_DPUF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSREG_DPUF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSREG_DPUF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S1, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S2, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF0, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF0_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF0_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_XIU_D0_DPUF_IPCLKPORT_ACLK, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D0_DPUF_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D0_DPUF_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D0_DPUF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_XIU_D1_DPUF_IPCLKPORT_ACLK, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D1_DPUF_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D1_DPUF_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_XIU_D1_DPUF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_SIU_DPUF_IPCLKPORT_I_ACLK, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_SIU_DPUF_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SIU_DPUF_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SIU_DPUF_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_SLH_AST_SI_G_PPMU_DPUF_IPCLKPORT_I_CLK, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AST_SI_G_PPMU_DPUF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AST_SI_G_PPMU_DPUF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AST_SI_G_PPMU_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_SLH_AXI_SI_D0_DPUF_IPCLKPORT_I_CLK, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_SI_D0_DPUF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_SI_D0_DPUF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SLH_AXI_SI_D0_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_AD_APB_DPUF1_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF1, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF1_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF1_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_DPUF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF1, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF1_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF1_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_SRAMC, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_SRAMC_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_SRAMC_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_DPUF_IPCLKPORT_ACLK_SRAMC_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_ACLK, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_PCLK, DIV_CLK_DPUF_NOCP, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D1_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_ACLK, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_PCLK, DIV_CLK_DPUF_NOCP, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_PPMU_D0_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S1, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S2, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D0_DPUF1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S1, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S2, MUX_CLKCMU_DPUF_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_SYSMMU_D1_DPUF1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK, DIV_CLK_DPUF_NOCP, CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_D_TZPC_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCP_IPCLKPORT_CLK, DIV_CLK_DPUF_NOCP, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_RSTNSYNC_SR_CLK_DPUF_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF_UID_BLK_DPUF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_DPUF, CLK_CON_GAT_CLK_BLK_DPUF_UID_BLK_DPUF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_BLK_DPUF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF_UID_BLK_DPUF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK, DIV_CLK_DPUF1_NOCP, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_CMU_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPUF, MUX_CLKCMU_DPUF1_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPUF_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPUF_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_DPUF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_VOTF, MUX_CLKCMU_DPUF1_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_VOTF_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_VOTF_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_DPUF1_IPCLKPORT_ACLK_VOTF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_SLH_AXI_MI_P_DPUF1_IPCLKPORT_I_CLK, DIV_CLK_DPUF1_NOCP, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_AXI_MI_P_DPUF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_AXI_MI_P_DPUF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_AXI_MI_P_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK, MUX_CLKCMU_DPUF1_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK, DIV_CLK_DPUF1_NOCP, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK, MUX_CLKCMU_DPUF1_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK, DIV_CLK_DPUF1_NOCP, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_PPMU_DPUF1D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_DPUF1_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCP_IPCLKPORT_CLK, DIV_CLK_DPUF1_NOCP, CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_CLK_DPUF1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1, MUX_CLKCMU_DPUF1_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1, MUX_CLKCMU_DPUF1_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK, DIV_CLK_DPUF1_NOCP, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSREG_DPUF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2, MUX_CLKCMU_DPUF1_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2, MUX_CLKCMU_DPUF1_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SYSMMU_DPUF1D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_SIU_DPUF1_IPCLKPORT_I_ACLK, MUX_CLKCMU_DPUF1_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SIU_DPUF1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SIU_DPUF1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SIU_DPUF1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_LH_AXI_SI_D0_DPUF1DPUF0_IPCLKPORT_I_CLK, MUX_CLKCMU_DPUF1_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D0_DPUF1DPUF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D0_DPUF1DPUF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D0_DPUF1DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_LH_AXI_SI_D1_DPUF1DPUF0_IPCLKPORT_I_CLK, MUX_CLKCMU_DPUF1_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D1_DPUF1DPUF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D1_DPUF1DPUF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_LH_AXI_SI_D1_DPUF1DPUF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_SLH_ASTL_SI_G_PPMU_DPUF1_IPCLKPORT_I_CLK, MUX_CLKCMU_DPUF1_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_ASTL_SI_G_PPMU_DPUF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_ASTL_SI_G_PPMU_DPUF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_SLH_ASTL_SI_G_PPMU_DPUF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DPUF1_UID_RSTNSYNC_SR_CLK_DPUF1_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_DPUF1_NOC_USER, CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_SR_CLK_DPUF1_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_SR_CLK_DPUF1_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPUF1_UID_RSTNSYNC_SR_CLK_DPUF1_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DRCP_UID_DRCP_CMU_DRCP_IPCLKPORT_PCLK, DIV_CLK_DRCP_NOCP, CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_CMU_DRCP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_CMU_DRCP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_CMU_DRCP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DRCP_UID_AD_APB_DRCP_IPCLKPORT_PCLKM, DIV_CLK_DRCP_NOC, CLK_CON_GAT_CLK_BLK_DRCP_UID_AD_APB_DRCP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_AD_APB_DRCP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_AD_APB_DRCP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DRCP_UID_DRCP_IPCLKPORT_CLK, DIV_CLK_DRCP_NOC, CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_DRCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_PCLK, DIV_CLK_DRCP_NOCP, CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_ACLK, DIV_CLK_DRCP_NOC, CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_PPMU_D_DRCP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S2, DIV_CLK_DRCP_NOC, CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S1, DIV_CLK_DRCP_NOC, CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSMMU_D_DRCP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DRCP_UID_D_TZPC_DRCP_IPCLKPORT_PCLK, DIV_CLK_DRCP_NOCP, CLK_CON_GAT_CLK_BLK_DRCP_UID_D_TZPC_DRCP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_D_TZPC_DRCP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_D_TZPC_DRCP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DRCP_UID_XIU_D_DRCP_IPCLKPORT_ACLK, DIV_CLK_DRCP_NOC, CLK_CON_GAT_CLK_BLK_DRCP_UID_XIU_D_DRCP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_XIU_D_DRCP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_XIU_D_DRCP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCD_IPCLKPORT_CLK, DIV_CLK_DRCP_NOC, CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCP_IPCLKPORT_CLK, DIV_CLK_DRCP_NOCP, CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_CLK_DRCP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DRCP_UID_SYSREG_DRCP_IPCLKPORT_PCLK, DIV_CLK_DRCP_NOCP, CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSREG_DRCP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSREG_DRCP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_SYSREG_DRCP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DRCP_UID_SLH_AXI_MI_P_DRCP_IPCLKPORT_I_CLK, DIV_CLK_DRCP_NOCP, CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_AXI_MI_P_DRCP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_AXI_MI_P_DRCP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_AXI_MI_P_DRCP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DRCP_UID_LH_AST_MI_OTF_YUVPDRCP_IPCLKPORT_I_CLK, DIV_CLK_DRCP_NOC, CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_MI_OTF_YUVPDRCP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_MI_OTF_YUVPDRCP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_MI_OTF_YUVPDRCP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DRCP_UID_LH_AST_SI_OTF_DRCPMCSC_IPCLKPORT_I_CLK, DIV_CLK_DRCP_NOC, CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_SI_OTF_DRCPMCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_SI_OTF_DRCPMCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AST_SI_OTF_DRCPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DRCP_UID_LH_AXI_SI_D_DRCP_IPCLKPORT_I_CLK, DIV_CLK_DRCP_NOC, CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AXI_SI_D_DRCP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AXI_SI_D_DRCP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_LH_AXI_SI_D_DRCP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DRCP_UID_VGEN_LITE_D_DRCP_IPCLKPORT_CLK, DIV_CLK_DRCP_NOC, CLK_CON_GAT_CLK_BLK_DRCP_UID_VGEN_LITE_D_DRCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_VGEN_LITE_D_DRCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_VGEN_LITE_D_DRCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DRCP_UID_SLH_ASTL_SI_G_PPMU_DRCP_IPCLKPORT_I_CLK, DIV_CLK_DRCP_NOC, CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_ASTL_SI_G_PPMU_DRCP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_ASTL_SI_G_PPMU_DRCP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_SLH_ASTL_SI_G_PPMU_DRCP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DRCP_UID_RSTNSYNC_SR_CLK_DRCP_NOCD_IPCLKPORT_CLK, DIV_CLK_DRCP_NOC, CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_SR_CLK_DRCP_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_SR_CLK_DRCP_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DRCP_UID_RSTNSYNC_SR_CLK_DRCP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SHMEM_IPCLKPORT_I_CLK, DIV_CLK_DSP_NOC, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SHMEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SHMEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SHMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK, DIV_CLK_DSP_NOCP, CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCD_IPCLKPORT_CLK, DIV_CLK_DSP_NOC, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCP_IPCLKPORT_CLK, DIV_CLK_DSP_NOCP, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_CLK_DSP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK, DIV_CLK_DSP_NOCP, CLK_CON_GAT_CLK_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSP_UID_D_TZPC_DSP_IPCLKPORT_PCLK, DIV_CLK_DSP_NOCP, CLK_CON_GAT_CLK_BLK_DSP_UID_D_TZPC_DSP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSP_UID_D_TZPC_DSP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSP_UID_D_TZPC_DSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSP_UID_SLH_AXI_MI_LP_DSP_IPCLKPORT_I_CLK, DIV_CLK_DSP_NOCP, CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_MI_LP_DSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_MI_LP_DSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_MI_LP_DSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_DMA_IPCLKPORT_I_CLK, DIV_CLK_DSP_NOC, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_DMA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_DMA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_DMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_SFR_IPCLKPORT_I_CLK, DIV_CLK_DSP_NOC, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_SFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_SFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_MI_LD_DNCDSP_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSP_UID_SLH_AXI_SI_LD_DSPDNC_CACHE_IPCLKPORT_I_CLK, DIV_CLK_DSP_NOC, CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_SI_LD_DSPDNC_CACHE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_SI_LD_DSPDNC_CACHE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSP_UID_SLH_AXI_SI_LD_DSPDNC_CACHE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SFR_IPCLKPORT_I_CLK, DIV_CLK_DSP_NOC, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SFR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SFR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AXI_SI_LD_DSPDNC_SFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSP_UID_IP_DSP_IPCLKPORT_CLK, DIV_CLK_DSP_NOC, CLK_CON_GAT_CLK_BLK_DSP_UID_IP_DSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSP_UID_IP_DSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSP_UID_IP_DSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSP_UID_LH_AST_MI_LD_STRM_SDMADSP_IPCLKPORT_I_CLK, DIV_CLK_DSP_NOC, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AST_MI_LD_STRM_SDMADSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AST_MI_LD_STRM_SDMADSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSP_UID_LH_AST_MI_LD_STRM_SDMADSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCD_IPCLKPORT_CLK, DIV_CLK_DSP_NOC, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCP_IPCLKPORT_CLK, DIV_CLK_DSP_NOCP, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSP_UID_RSTNSYNC_SR_CLK_DSP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSP_UID_BLK_DSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_DSP, CLK_CON_GAT_CLK_BLK_DSP_UID_BLK_DSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSP_UID_BLK_DSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSP_UID_BLK_DSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE, MUX_CLK_DSU_POWERIP, CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_LH_ATB_SI_IT_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ATB_SI_IT_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ATB_SI_IT_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ATB_SI_IT_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK, DIV_CLK_DSU_CLUSTER, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_CLK_DSU_POWERIP_IPCLKPORT_CLK, MUX_CLK_DSU_POWERIP, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_DSU_POWERIP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_DSU_POWERIP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_DSU_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_BUSIF_STR_CPUCL0_3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_GLB_NOCP_USER, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_LH_CHI_SI_D0_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_ACLK, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_LH_CHI_SI_D1_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_ACLK, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_CHI_SI_D1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_GRAY2BIN_CNTVALUEB_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_GRAY2BIN_CNTVALUEB_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_GRAY2BIN_CNTVALUEB_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_GRAY2BIN_CNTVALUEB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_SCLK, DIV_CLK_DSU_CLUSTER, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(DSU_CPM, PLL_DSU, CLK_CON_GAT_DSU_CPM_CG_VAL, CLK_CON_GAT_DSU_CPM_MANUAL, CLK_CON_GAT_DSU_CPM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ACLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_STR_CPUCL0_3_IPCLKPORT_DEM_CLK, CLK_DSU_STR_DEM_CLK, CLK_CON_GAT_CLK_BLK_DSU_UID_STR_CPUCL0_3_IPCLKPORT_DEM_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_STR_CPUCL0_3_IPCLKPORT_DEM_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_STR_CPUCL0_3_IPCLKPORT_DEM_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_HTU_IPCLKPORT_CLK, MUX_CLK_DSU_HTU, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK, MUX_CLK_DSU_HTU, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_SLH_AXI_MI_LP_PPU_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_LP_PPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_LP_PPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_LP_PPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_U_SYNC_PPUWAKEUP_CLUSTER0_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_PPUWAKEUP_CLUSTER0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_PPUWAKEUP_CLUSTER0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_PPUWAKEUP_CLUSTER0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_XIU_DP_UTILITY_IPCLKPORT_ACLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_UTILITY_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_UTILITY_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_UTILITY_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_SLH_AXI_MI_IP_UTILITY_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_IP_UTILITY_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_IP_UTILITY_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_MI_IP_UTILITY_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PPUCLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PPUCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PPUCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PPUCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACLK, DIV_CLK_CLUSTER_ACLK, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ACLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_GICCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_PPUCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_SCLK_IPCLKPORT_CLK, DIV_CLK_DSU_CLUSTER, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ACPCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_MPCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ACPCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_ACPCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_XIU_DP_PERIPHERAL_IPCLKPORT_ACLK, DIV_CLK_CLUSTER_MPCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_PERIPHERAL_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_PERIPHERAL_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_DP_PERIPHERAL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_SLH_AXI_SI_IP_UTILITY_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_MPCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_IP_UTILITY_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_IP_UTILITY_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_IP_UTILITY_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_LH_ACEL_MI_D0_ACP_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_ACPCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D0_ACP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D0_ACP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D0_ACP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_LH_ACEL_MI_D1_ACP_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_ACPCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D1_ACP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D1_ACP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_ACEL_MI_D1_ACP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_XIU_D_CPUCL0_ACP_IPCLKPORT_ACLK, DIV_CLK_CLUSTER_ACPCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_D_CPUCL0_ACP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_D_CPUCL0_ACP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_XIU_D_CPUCL0_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_MPCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACPCLK, DIV_CLK_CLUSTER_ACPCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ACPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_MPCLK, DIV_CLK_CLUSTER_MPCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_MPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_MPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_MPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_U_SYNC_ACPWAKEUP_CLUSTER0_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ACPCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_ACPWAKEUP_CLUSTER0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_ACPWAKEUP_CLUSTER0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_ACPWAKEUP_CLUSTER0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_ACLK, DIV_CLK_CLUSTER_ACLK, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_DIVCLK, DIV_CLK_CLUSTER_MPACTCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_DIVCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_DIVCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M0_IPCLKPORT_DIVCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_ACLK, DIV_CLK_CLUSTER_ACLK, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_DIVCLK, DIV_CLK_CLUSTER_MPACTCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_DIVCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_DIVCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_MPACT_M1_IPCLKPORT_DIVCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_MPACTCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D1_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_MPACTCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D2_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_MPACTCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D3_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER_MPACTCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_LH_PACE_ASYNC_MPACT_D3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_MPACTCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_POWERIP_IPCLKPORT_CLK, MUX_CLK_DSU_POWERIP, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_POWERIP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_POWERIP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_DSU_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_MPACTCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_MPACTCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_U_SYNC_IRITWAKEUP_CLUSTER0_IPCLKPORT_CLK, DIV_CLK_CLUSTER_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_IRITWAKEUP_CLUSTER0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_IRITWAKEUP_CLUSTER0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_U_SYNC_IRITWAKEUP_CLUSTER0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER_MPCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_SR_CLK_CLUSTER_MPCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, MUX_CLKCMU_G3D_NOCP_USER, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_SLH_AXI_SI_P_INT_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_G3D_NOCP_USER, CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_SI_P_INT_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_SI_P_INT_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_SI_P_INT_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, MUX_CLKCMU_G3D_NOCP_USER, CLK_CON_GAT_CLK_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK, MUX_CLKCMU_G3D_NOCP_USER, CLK_CON_GAT_CLK_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_G3D_NOCP_USER, CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_G3D_NOCP_USER, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_CFM_G3D_IPCLKPORT_PCLK, MUX_CLKCMU_G3D_NOCP_USER, CLK_CON_GAT_CLK_BLK_G3D_UID_CFM_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_CFM_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_CFM_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_BG3D_PWRCTL_IPCLKPORT_CLK, MUX_CLKCMU_G3D_NOCP_USER, CLK_CON_GAT_CLK_BLK_G3D_UID_BG3D_PWRCTL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_BG3D_PWRCTL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_BG3D_PWRCTL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_G3D, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_G3D, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_G3D_NOCP_USER, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CLK, MUX_CLK_G3D_PLL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CH_CLK, CLK_G3D_ADD_CH_CLK, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CH_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CH_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_G3D_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE, MUX_CLK_G3D_PLL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3D_POWERIP_IPCLKPORT_CLK, MUX_CLK_G3D_PLL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3D_POWERIP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3D_POWERIP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3D_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK, MUX_CLKCMU_G3D_NOCP_USER, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_PCLK, MUX_CLKCMU_G3D_NOCP_USER, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3DCORE_UID_G3DCORE_CMU_G3DCORE_IPCLKPORT_PCLK, MUX_CLKCMU_G3D_NOCP_USER, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_G3DCORE_CMU_G3DCORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_G3DCORE_CMU_G3DCORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_G3DCORE_CMU_G3DCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3DCORE_UID_GPU_IPCLKPORT_PCLK, MUX_CLKCMU_G3D_NOCP_USER, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_GPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_GPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_GPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3DCORE_UID_ADM_DAP_G_G3D_IPCLKPORT_DAPCLKM, MUX_CLKCMU_G3D_NOCP_USER, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADM_DAP_G_G3D_IPCLKPORT_DAPCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADM_DAP_G_G3D_IPCLKPORT_DAPCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_ADM_DAP_G_G3D_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_CLK, MUX_CLK_G3D_PLL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_HTU_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_G3D_NOCP_USER, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3DCORE_UID_BUSIF_DDC_G3D_IPCLKPORT_PCLK_S0, MUX_CLKCMU_G3D_NOCP_USER, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_BUSIF_DDC_G3D_IPCLKPORT_PCLK_S0_CG_VAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_BUSIF_DDC_G3D_IPCLKPORT_PCLK_S0_MANUAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_BUSIF_DDC_G3D_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(G3DCORE_CPM, MUX_CLK_G3D_PLL, CLK_CON_GAT_G3DCORE_CPM_CG_VAL, CLK_CON_GAT_G3DCORE_CPM_MANUAL, CLK_CON_GAT_G3DCORE_CPM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_G3DCORE, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_G3DCORE, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_G3D_NOCP_USER, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3DCORE_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3D_POWERIP_IPCLKPORT_CLK, MUX_CLK_G3D_PLL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3D_POWERIP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3D_POWERIP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_RSTNSYNC_SR_CLK_G3D_POWERIP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_PCLK, MUX_CLKCMU_G3D_NOCP_USER, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_CLK_CORE, MUX_CLK_G3D_PLL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_CLK_BLK_G3DCORE_UID_STR_MUX_G3D_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNPU_UID_GNPU_CMU_GNPU_IPCLKPORT_PCLK, DIV_CLK_GNPU_NOCP, CLK_CON_GAT_CLK_BLK_GNPU_UID_GNPU_CMU_GNPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_GNPU_CMU_GNPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_GNPU_CMU_GNPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_CORE, DIV_CLK_GNPU_NOC, CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_CORE_CG_VAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_CORE_MANUAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_CORE_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_SRAM, DIV_CLK_GNPU_NOC, CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_SRAM_CG_VAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_SRAM_MANUAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_IP_NPUCORE_IPCLKPORT_CLK_SRAM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNPU_UID_LH_AXI_MI_LD_CTRL_GNPU_IPCLKPORT_I_CLK, DIV_CLK_GNPU_NOC, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD_CTRL_GNPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD_CTRL_GNPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD_CTRL_GNPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNPU_UID_LH_AXI_SI_LD_RQ_GNPU_IPCLKPORT_I_CLK, DIV_CLK_GNPU_NOC, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_RQ_GNPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_RQ_GNPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_RQ_GNPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNPU_UID_LH_AXI_MI_LD1_GNPU_IPCLKPORT_I_CLK, DIV_CLK_GNPU_NOC, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD1_GNPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD1_GNPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD1_GNPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNPU_UID_D_TZPC_GNPU_IPCLKPORT_PCLK, DIV_CLK_GNPU_NOCP, CLK_CON_GAT_CLK_BLK_GNPU_UID_D_TZPC_GNPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_D_TZPC_GNPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_D_TZPC_GNPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNPU_UID_SLH_AXI_MI_LP_GNPU_IPCLKPORT_I_CLK, DIV_CLK_GNPU_NOCP, CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_MI_LP_GNPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_MI_LP_GNPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_MI_LP_GNPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNPU_UID_SLH_AXI_SI_LD_CMDQ_GNPU_IPCLKPORT_I_CLK, DIV_CLK_GNPU_NOC, CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_SI_LD_CMDQ_GNPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_SI_LD_CMDQ_GNPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_SLH_AXI_SI_LD_CMDQ_GNPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNPU_UID_SYSREG_GNPU_IPCLKPORT_PCLK, DIV_CLK_GNPU_NOCP, CLK_CON_GAT_CLK_BLK_GNPU_UID_SYSREG_GNPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_SYSREG_GNPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_SYSREG_GNPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNPU_UID_LH_AXI_MI_LD0_GNPU_IPCLKPORT_I_CLK, DIV_CLK_GNPU_NOC, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD0_GNPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD0_GNPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_MI_LD0_GNPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNPU_UID_LH_AXI_SI_LD_GNPUDNC_SHMEM_IPCLKPORT_I_CLK, DIV_CLK_GNPU_NOC, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_GNPUDNC_SHMEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_GNPUDNC_SHMEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_LH_AXI_SI_LD_GNPUDNC_SHMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNPU_UID_XIU_D_GNPU_0_IPCLKPORT_ACLK, DIV_CLK_GNPU_NOC, CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNPU_UID_XIU_D_GNPU_1_IPCLKPORT_ACLK, DIV_CLK_GNPU_NOC, CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_XIU_D_GNPU_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCD_IPCLKPORT_CLK, DIV_CLK_GNPU_NOC, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCP_IPCLKPORT_CLK, DIV_CLK_GNPU_NOCP, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_CLK_GNPU_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCD_IPCLKPORT_CLK, DIV_CLK_GNPU_NOC, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCP_IPCLKPORT_CLK, DIV_CLK_GNPU_NOCP, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_RSTNSYNC_SR_CLK_GNPU_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNPU_UID_BLK_GNPU_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_GNPU, CLK_CON_GAT_CLK_BLK_GNPU_UID_BLK_GNPU_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_BLK_GNPU_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNPU_UID_BLK_GNPU_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK, CLKALIVE_GNSS_NOC, CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK, MUX_CLKCMU_HSI0_DPOSC_USER, CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK, MUX_CLKCMU_HSI0_DPGTC_USER, CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40, MUX_CLK_HSI0_USB32DRD, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK, DIV_CLK_HSI0_EUSB, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM, DIV_CLK_HSI0_EUSB, CLK_CON_GAT_CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK, DIV_CLK_HSI0_EUSB, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK, FREE_OSCCLK_HSI0, CLK_CON_GAT_CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_HSI0, CLK_CON_GAT_CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_HSI0, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_A_G2X1_PHY_REFCLK_IN, MUX_CLKCMU_HSI1_PCIE_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_A_G2X1_PHY_REFCLK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_A_G2X1_PHY_REFCLK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_A_G2X1_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PIPE_PAL_GEN2_X1_PCIE_INST_0_I_APB_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PIPE_PAL_GEN2_X1_PCIE_INST_0_I_APB_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PIPE_PAL_GEN2_X1_PCIE_INST_0_I_APB_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PIPE_PAL_GEN2_X1_PCIE_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PAMIR_G3X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PHY_UDBG_I_APB_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PHY_UDBG_I_APB_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PHY_UDBG_I_APB_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_VGEN_LITE_HSI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PAMIR_G2X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SUB_CTRL_A_G3X2_PHY_REFCLK_IN, MUX_CLKCMU_HSI1_PCIE_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SUB_CTRL_A_G3X2_PHY_REFCLK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SUB_CTRL_A_G3X2_PHY_REFCLK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SUB_CTRL_A_G3X2_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_SF_PCIEPHY_X1_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_SF_PCIEPHY_X1_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_SF_PCIEPHY_X1_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_SF_PCIEPHY_X1_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_SLH_AST_SI_G_PPMU_HSI1_IPCLKPORT_I_CLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AST_SI_G_PPMU_HSI1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AST_SI_G_PPMU_HSI1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AST_SI_G_PPMU_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_NOC_IPCLKPORT_CLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SOC_CTRL_GEN3A_IPCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SOC_CTRL_GEN3A_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SOC_CTRL_GEN3A_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_SOC_CTRL_GEN3A_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_SF_PCIEPHY_X2_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_SF_PCIEPHY_X2_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_SF_PCIEPHY_X2_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN3_IPCLKPORT_PCIE_PHY_TOP_INST_0_SF_PCIEPHY_X2_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PHY_UDBG_I_APB_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PHY_UDBG_I_APB_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PHY_UDBG_I_APB_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_PHY_TOP_GEN2_X1_INST_0_PHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_HSI1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_HSI1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_SR_CLK_HSI1_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SOC_CTRL_GEN2_IPCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SOC_CTRL_GEN2_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SOC_CTRL_GEN2_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SOC_CTRL_GEN2_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_HSI1_UID_BLK_HSI1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_HSI1, CLK_CON_GAT_CLK_BLK_HSI1_UID_BLK_HSI1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_BLK_HSI1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_BLK_HSI1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK, DIV_CLK_LME_NOCP, CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_LME_CMU_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_LH_ACEL_SI_D_LME_IPCLKPORT_I_CLK, MUX_CLKCMU_LME_NOC_USER, CLK_CON_GAT_CLK_BLK_LME_UID_LH_ACEL_SI_D_LME_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_LH_ACEL_SI_D_LME_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_LH_ACEL_SI_D_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_PCLK, DIV_CLK_LME_NOCP, CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_ACLK, MUX_CLKCMU_LME_NOC_USER, CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_PPMU_D_LME_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_SLH_AXI_MI_P_LME_IPCLKPORT_I_CLK, DIV_CLK_LME_NOCP, CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AXI_MI_P_LME_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AXI_MI_P_LME_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AXI_MI_P_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK, DIV_CLK_LME_NOCP, CLK_CON_GAT_CLK_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_SYSREG_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK, DIV_CLK_LME_NOCP, CLK_CON_GAT_CLK_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_D_TZPC_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1, MUX_CLKCMU_LME_NOC_USER, CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK, MUX_CLKCMU_LME_NOC_USER, CLK_CON_GAT_CLK_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_XIU_D_LME_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_LME_NOC_USER, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCP_IPCLKPORT_CLK, DIV_CLK_LME_NOCP, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_ACLK, MUX_CLKCMU_LME_NOC_USER, CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_PCLK, DIV_CLK_LME_NOCP, CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_QE_D1_LME_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2, MUX_CLKCMU_LME_NOC_USER, CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_SYSMMU_D_LME_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_SLH_AST_SI_G_PPMU_LME_IPCLKPORT_I_CLK, MUX_CLKCMU_LME_NOC_USER, CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AST_SI_G_PPMU_LME_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AST_SI_G_PPMU_LME_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_SLH_AST_SI_G_PPMU_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_LME_IPCLKPORT_CLK, MUX_CLKCMU_LME_LME_USER, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_LME_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_LME_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_CLK_LME_LME_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_LME_NOC_USER, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM, MUX_CLKCMU_LME_LME_USER, CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_LME_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_AD_APB_GDC_IPCLKPORT_PCLKM, MUX_CLKCMU_LME_NOC_USER, CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_GDC_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_GDC_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_AD_APB_GDC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_LME_IPCLKPORT_CLK, MUX_CLKCMU_LME_LME_USER, CLK_CON_GAT_CLK_BLK_LME_UID_LME_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_LME_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_LME_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_M, MUX_CLKCMU_LME_NOC_USER, CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_M_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_M_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_M_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_S, MUX_CLKCMU_LME_NOC_USER, CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_S_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_S_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_C2CLK_S_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_GDC_IPCLKPORT_CLK, MUX_CLKCMU_LME_NOC_USER, CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_LH_AXI_MI_ID_LME_IPCLKPORT_I_CLK, MUX_CLKCMU_LME_NOC_USER, CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_MI_ID_LME_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_MI_ID_LME_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_MI_ID_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_LH_AXI_SI_ID_LME_IPCLKPORT_I_CLK, MUX_CLKCMU_LME_LME_USER, CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_SI_ID_LME_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_SI_ID_LME_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_LH_AXI_SI_ID_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_LME_IPCLKPORT_CLK, MUX_CLKCMU_LME_LME_USER, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_LME_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_LME_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_LME_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCP_IPCLKPORT_CLK, DIV_CLK_LME_NOCP, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_RSTNSYNC_SR_CLK_LME_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_VGEN_LITE_D_GDC_IPCLKPORT_CLK, MUX_CLKCMU_LME_NOC_USER, CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_GDC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_GDC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_VGEN_LITE_D_LME_IPCLKPORT_CLK, MUX_CLKCMU_LME_LME_USER, CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_LME_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_LME_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_VGEN_LITE_D_LME_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_LME_UID_BLK_LME_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_LME, CLK_CON_GAT_CLK_BLK_LME_UID_BLK_LME_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_LME_UID_BLK_LME_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_LME_UID_BLK_LME_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK, DIV_CLK_M2M_NOCP, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_M2M_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK, DIV_CLK_M2M_NOCP, CLK_CON_GAT_CLK_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK, DIV_CLK_M2M_NOCP, CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_LH_ACEL_SI_D_M2M_IPCLKPORT_I_CLK, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_LH_ACEL_SI_D_M2M_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_LH_ACEL_SI_D_M2M_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_LH_ACEL_SI_D_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK, DIV_CLK_M2M_NOCP, CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK, DIV_CLK_M2M_NOCP, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK, DIV_CLK_M2M_NOCP, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK, DIV_CLK_M2M_NOCP, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCP_IPCLKPORT_CLK, DIV_CLK_M2M_NOCP, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S1, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S2, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_SYSMMU_D_M2M_PM_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK, DIV_CLK_M2M_NOCP, CLK_CON_GAT_CLK_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK, DIV_CLK_M2M_NOCP, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_JPEG1_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_JSQZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JPEG1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_JSQZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_SLH_AST_SI_G_PPMU_M2M_IPCLKPORT_I_CLK, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AST_SI_G_PPMU_M2M_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AST_SI_G_PPMU_M2M_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_SLH_AST_SI_G_PPMU_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_FRC_MC_IPCLKPORT_I_CLK, MUX_CLKCMU_M2M_FRC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_FRC_MC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_FRC_MC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_FRC_MC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_PCLK, DIV_CLK_M2M_NOCP, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_QE_FRC_MC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_FRC_IPCLKPORT_CLK, MUX_CLKCMU_M2M_FRC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_FRC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_FRC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_FRC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_FRC_IPCLKPORT_CLK, MUX_CLKCMU_M2M_FRC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_FRC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_FRC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_CLK_M2M_FRC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_AS_APB_FRC_MC_IPCLKPORT_PCLKM, MUX_CLKCMU_M2M_FRC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_FRC_MC_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_FRC_MC_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_AS_APB_FRC_MC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_BLK_M2M_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_M2M, CLK_CON_GAT_CLK_BLK_M2M_UID_BLK_M2M_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_BLK_M2M_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_BLK_M2M_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCP_IPCLKPORT_CLK, DIV_CLK_M2M_NOCP, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_LH_AXI_MI_FRC_MC_IPCLKPORT_I_CLK, MUX_CLKCMU_M2M_NOC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_MI_FRC_MC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_MI_FRC_MC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_MI_FRC_MC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_M2M_UID_LH_AXI_SI_FRC_MC_IPCLKPORT_I_CLK, MUX_CLKCMU_M2M_FRC_USER, CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_SI_FRC_MC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_SI_FRC_MC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_LH_AXI_SI_FRC_MC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_CLK_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D2_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCD_IPCLKPORT_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK, DIV_CLK_MCSC_MCSC, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D2_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D1_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_SLH_AST_SI_G_PPMU_MCSC_IPCLKPORT_I_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AST_SI_G_PPMU_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AST_SI_G_PPMU_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AST_SI_G_PPMU_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_SIU_G_PPMU_MCSC_IPCLKPORT_I_ACLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_SIU_G_PPMU_MCSC_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SIU_G_PPMU_MCSC_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SIU_G_PPMU_MCSC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCD_IPCLKPORT_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_MCSC_IPCLKPORT_CLK, DIV_CLK_MCSC_MCSC, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_MCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_MCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_AD_APB_MCFP_IPCLKPORT_PCLKM, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCFP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCFP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCFP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM, DIV_CLK_MCSC_MCSC, CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_ACLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D3_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_ACLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_PPMU_D4_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S1, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S2, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D3_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S1, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S2, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SYSMMU_D4_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_SLH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_SLH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AXI_SI_D3_MCSC_IPCLKPORT_I_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D3_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D3_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D3_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AXI_SI_D4_MCSC_IPCLKPORT_I_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D4_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D4_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_D4_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_XIU_D3_MCSC_IPCLKPORT_ACLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D3_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D3_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D3_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_XIU_D4_MCSC_IPCLKPORT_ACLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D4_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D4_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_XIU_D4_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D0_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_VGEN_LITE_D2_MCSC_IPCLKPORT_CLK, DIV_CLK_MCSC_MCSC, CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D2_MCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D2_MCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_VGEN_LITE_D2_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK, DIV_CLK_MCSC_MCSC, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2R_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK, DIV_CLK_MCSC_MCSC, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_C2W_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK, DIV_CLK_MCSC_MCSC, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_MCFP_IPCLKPORT_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCFP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCFP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCFP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AST_SI_OTF_MCSCYUVP_IPCLKPORT_I_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_SI_OTF_MCSCYUVP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_SI_OTF_MCSCYUVP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_SI_OTF_MCSCYUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AST_MI_OTF_BRPMCSC_IPCLKPORT_I_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF_BRPMCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF_BRPMCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF_BRPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCP_IPCLKPORT_CLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC6_IPCLKPORT_I_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC6_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC6_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC6_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC0_IPCLKPORT_I_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC1_IPCLKPORT_I_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC2_IPCLKPORT_I_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC3_IPCLKPORT_I_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC4_IPCLKPORT_I_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC4_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC4_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC4_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC5_IPCLKPORT_I_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC5_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC5_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_MI_ID_MCSC5_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC0_IPCLKPORT_I_CLK, DIV_CLK_MCSC_MCSC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC1_IPCLKPORT_I_CLK, DIV_CLK_MCSC_MCSC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC2_IPCLKPORT_I_CLK, DIV_CLK_MCSC_MCSC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC3_IPCLKPORT_I_CLK, DIV_CLK_MCSC_MCSC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC4_IPCLKPORT_I_CLK, DIV_CLK_MCSC_MCSC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC4_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC4_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC4_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC5_IPCLKPORT_I_CLK, DIV_CLK_MCSC_MCSC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC5_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC5_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC5_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC6_IPCLKPORT_I_CLK, DIV_CLK_MCSC_MCSC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC6_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC6_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AXI_SI_ID_MCSC6_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_BLK_MCSC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_MCSC, CLK_CON_GAT_CLK_BLK_MCSC_UID_BLK_MCSC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_BLK_MCSC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_BLK_MCSC_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AST_MI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK, DIV_CLK_MCSC_MCSC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MCSC_UID_LH_AST_MI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK, DIV_CLK_MCSC_NOC, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_LH_AST_MI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK, DIV_CLK_MFC0_NOCP, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_CMU_MFC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_XIU_D_MFC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK, MUX_CLKCMU_MFC0_WFD_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_WFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCP_IPCLKPORT_CLK, DIV_CLK_MFC0_NOCP, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_WFD_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_WFD_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_WFD_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK, DIV_CLK_MFC0_NOCP, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK, DIV_CLK_MFC0_NOCP, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK, DIV_CLK_MFC0_NOCP, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_MFC0D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_MFC0_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_SI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI, MUX_CLKCMU_MFC0_WFD_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_ATB_MFC0_IPCLKPORT_I_CLK_MI_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_LH_AXI_SI_D1_MFC0_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D1_MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D1_MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D1_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_LH_AXI_SI_D0_MFC0_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D0_MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D0_MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_D0_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_LH_AST_SI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_LH_AST_SI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_LH_AST_SI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_SLH_AXI_MI_P_MFC0_IPCLKPORT_I_CLK, DIV_CLK_MFC0_NOCP, CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AXI_MI_P_MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AXI_MI_P_MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AXI_MI_P_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_LH_AST_MI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_LH_AST_MI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_LH_AST_MI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_LH_AST_MI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_MI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK, DIV_CLK_MFC0_NOCP, CLK_CON_GAT_CLK_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_D_TZPC_MFC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_ADS_APB_MFC0MFC1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_MFC0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM, MUX_CLKCMU_MFC0_WFD_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK, DIV_CLK_MFC0_NOCP, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSREG_MFC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_LH_AST_SI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AST_SI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_SYSMMU_MFC0D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_SLH_AST_SI_G_PPMU_MFC0_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AST_SI_G_PPMU_MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AST_SI_G_PPMU_MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_SLH_AST_SI_G_PPMU_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_SIU_G_PPMU_MFC0_IPCLKPORT_I_ACLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_SIU_G_PPMU_MFC0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_SIU_G_PPMU_MFC0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_SIU_G_PPMU_MFC0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_VGEN_LITE_MFC0_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_VGEN_LITE_MFC0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_VGEN_LITE_MFC0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_VGEN_LITE_MFC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_PPMU_WFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_CLK_MFC0_NOCD_MFC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCP_IPCLKPORT_CLK, DIV_CLK_MFC0_NOCP, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_LH_AXI_SI_ID_MFC0_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC0_WFD_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_ID_MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_ID_MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_SI_ID_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_LH_AXI_MI_ID_MFC0_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_MI_ID_MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_MI_ID_MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_LH_AXI_MI_ID_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_BLK_MFC0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_MFC0, CLK_CON_GAT_CLK_BLK_MFC0_UID_BLK_MFC0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_BLK_MFC0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_BLK_MFC0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_MFC0_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK, MUX_CLKCMU_MFC0_WFD_USER, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC0_UID_RSTNSYNC_SR_CLK_MFC0_NOCD_WFD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK, DIV_CLK_MFC1_NOCP, CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_CMU_MFC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK, DIV_CLK_MFC1_NOCP, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSREG_MFC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCP_IPCLKPORT_CLK, DIV_CLK_MFC1_NOCP, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_LH_AST_MI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF0_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK, DIV_CLK_MFC1_NOCP, CLK_CON_GAT_CLK_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_D_TZPC_MFC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_AS_APB_MFC1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_ADM_APB_MFC0MFC1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_LH_AST_MI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF1_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_LH_AST_MI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF2_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_LH_AST_MI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_MI_OTF3_MFC0MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_SLH_AXI_MI_P_MFC1_IPCLKPORT_I_CLK, DIV_CLK_MFC1_NOCP, CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AXI_MI_P_MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AXI_MI_P_MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AXI_MI_P_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_LH_AST_SI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF0_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_LH_AST_SI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF1_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_LH_AST_SI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF2_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_LH_AST_SI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AST_SI_OTF3_MFC1MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_LH_AXI_SI_D0_MFC1_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D0_MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D0_MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D0_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_LH_AXI_SI_D1_MFC1_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D1_MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D1_MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_LH_AXI_SI_D1_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_MFC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK, DIV_CLK_MFC1_NOCP, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK, DIV_CLK_MFC1_NOCP, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_PPMU_MFC1D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_SYSMMU_MFC1D1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_VGEN_MFC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_SLH_AST_SI_G_PPMU_MFC1_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AST_SI_G_PPMU_MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AST_SI_G_PPMU_MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_SLH_AST_SI_G_PPMU_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_SIU_G_PPMU_MFC1_IPCLKPORT_I_ACLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_SIU_G_PPMU_MFC1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_SIU_G_PPMU_MFC1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_SIU_G_PPMU_MFC1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCP_IPCLKPORT_CLK, DIV_CLK_MFC1_NOCP, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_BLK_MFC1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_MFC1, CLK_CON_GAT_CLK_BLK_MFC1_UID_BLK_MFC1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_BLK_MFC1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_BLK_MFC1_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC1_MFC1_USER, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC1_UID_RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK, DIV_CLK_MIF_NOCD, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_QCH_ADAPTER_DDRPHY_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DDRPHY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DDRPHY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_QCH_ADAPTER_DMC_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DMC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DMC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_CLK_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_SPC_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_CLK_BLK_MIF_UID_SPC_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_SPC_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_SPC_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_SYSREG_PRIVATE_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_PRIVATE_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_PRIVATE_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_SYSREG_PRIVATE_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_SLH_AST_SI_G_PPMU_MIF_IPCLKPORT_I_CLK, I_CLK_MIF_NOCD_DBG, CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AST_SI_G_PPMU_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AST_SI_G_PPMU_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AST_SI_G_PPMU_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_MIF, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_ATCLK, DIV_CLK_MIF_DDD_CTRL, CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_ATCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_ATCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_BUSIF_DDD_MIF_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_DDD_MIF_IPCLKPORT_CK_IN, DIV_CLK_MIF_NOCD, CLK_CON_GAT_CLK_BLK_MIF_UID_DDD_MIF_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_DDD_MIF_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_DDD_MIF_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK, I_CLK_MIF_NOCD_DBG, CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_DEBUG_IPCLKPORT_CLK, I_CLK_MIF_NOCD_DBG, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_DEBUG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_DEBUG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_DEBUG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_DDD_CTRL_IPCLKPORT_CLK, DIV_CLK_MIF_DDD_CTRL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_DDD_CTRL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_DDD_CTRL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_DDD_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_MIF, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_BLK_MIF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_MIF, CLK_CON_GAT_CLK_BLK_MIF_UID_BLK_MIF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_BLK_MIF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_BLK_MIF_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_IPCLKPORT_CLK, DIV_CLK_MIF_NOCD, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_SR_CLK_MIF_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SIU_G0_PPMU_NOCL0_IPCLKPORT_I_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G0_PPMU_NOCL0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G0_PPMU_NOCL0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G0_PPMU_NOCL0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SIU_G1_PPMU_NOCL0_IPCLKPORT_I_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G1_PPMU_NOCL0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G1_PPMU_NOCL0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G1_PPMU_NOCL0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_APB_ASYNC_SYSMMU_S2_G3D_IPCLKPORT_PCLKM, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_SYSMMU_S2_G3D_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_SYSMMU_S2_G3D_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_SYSMMU_S2_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_BAAW_CP_IPCLKPORT_I_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_CP_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_CP_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_CP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_MI_D2_MODEM_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D2_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D2_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D2_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_LH_CHI_MI_D0_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_LH_CHI_MI_D1_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_CHI_MI_D1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_LH_QDI_MI_D_AUD_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_QDI_MI_D_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_QDI_MI_D_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_QDI_MI_D_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERISGIC_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERISGIC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERISGIC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERISGIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_MPACE2AXI_0_IPCLKPORT_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_MPACE2AXI_1_IPCLKPORT_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE2AXI_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_G3D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D0, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D0_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D0_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_LITE_MODEM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_NOCL0, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_NOCL0_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_NOCL0_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_NOCL0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SYSMMU_S2_APM_IPCLKPORT_CLK_S2, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_APM_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_APM_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_APM_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_MI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_P_CLUSTER0_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D1, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D1_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D1_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D2, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D2_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D2_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D3, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D3_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D3_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_S2_D3_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CACHEAID_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_NOCL0, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_NOCL0_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_NOCL0_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_NOCL0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S1, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_MODEM_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_UFD_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_UFD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_UFD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_SSP_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_SSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_SSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1C_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1C_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1C_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_IRPS3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D0_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_MPTW, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_MPTW_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_MPTW_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SYSMMU_S2_G3D_IPCLKPORT_CLK_MPTW_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_AUD_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MODEM_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SIU_G2_PPMU_NOCL0_IPCLKPORT_I_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G2_PPMU_NOCL0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G2_PPMU_NOCL0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G2_PPMU_NOCL0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SIU_G3_PPMU_NOCL0_IPCLKPORT_I_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G3_PPMU_NOCL0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G3_PPMU_NOCL0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G3_PPMU_NOCL0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SIU_G4_PPMU_NOCL0_IPCLKPORT_I_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G4_PPMU_NOCL0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G4_PPMU_NOCL0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G4_PPMU_NOCL0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SIU_G5_PPMU_NOCL0_IPCLKPORT_I_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G5_PPMU_NOCL0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G5_PPMU_NOCL0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SIU_G5_PPMU_NOCL0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_APB_ASYNC_ETR_IPCLKPORT_PCLKM, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_ETR_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_ETR_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_ETR_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_ETR_64_NOCL0_IPCLKPORT_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_ETR_64_NOCL0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_ETR_64_NOCL0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_ETR_64_NOCL0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF0_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF1_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF2_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF3_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_SYNC_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PBHA_GEN_D0_MODEM_IPCLKPORT_I_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D0_MODEM_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D0_MODEM_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D0_MODEM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PBHA_GEN_D1_MODEM_IPCLKPORT_I_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D1_MODEM_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D1_MODEM_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PBHA_GEN_D1_MODEM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D1_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D2_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_WOW_DVFS_D3_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_VGEN_D0_G3D_IPCLKPORT_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D0_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D0_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D0_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_VGEN_D1_G3D_IPCLKPORT_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D1_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D1_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D1_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_VGEN_D2_G3D_IPCLKPORT_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D2_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D2_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D2_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_VGEN_D3_G3D_IPCLKPORT_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D3_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D3_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_VGEN_D3_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_PPMU_P_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D0_G3D_IPCLKPORT_PCLKM, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D0_G3D_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D0_G3D_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D0_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D1_G3D_IPCLKPORT_PCLKM, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D1_G3D_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D1_G3D_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D1_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D2_G3D_IPCLKPORT_PCLKM, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D2_G3D_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D2_G3D_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D2_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D3_G3D_IPCLKPORT_PCLKM, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D3_G3D_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D3_G3D_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_APB_ASYNC_VGEN_D3_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_SCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPMU_MIF3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_NOCL0, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_NOCL0, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_GNSS_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_NOCIF_CMUTOPC_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCIF_CMUTOPC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCIF_CMUTOPC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCIF_CMUTOPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIS_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_SSP_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_SSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_SSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_UFD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_UFD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_UFD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_ACEL_MI_D_SSP_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_ACEL_MI_D_SSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_ACEL_MI_D_SSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_ACEL_MI_D_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_MI_D_UFD_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D_UFD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D_UFD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_MI_D_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_SI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_MI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_IG_CSSYS_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_LH_ACEL_SI_D0_ACP_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D0_ACP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D0_ACP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D0_ACP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D0_ACP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_TREX_D1_ACP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_LH_ACEL_SI_D1_ACP_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D1_ACP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D1_ACP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ACEL_SI_D1_ACP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_XIU_D0_ACP_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D0_ACP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D0_ACP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D0_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_XIU_D1_ACP_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D1_ACP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D1_ACP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D1_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_XIU_D2_ACP_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D2_ACP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D2_ACP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D2_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_XIU_D3_ACP_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D3_ACP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D3_ACP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_XIU_D3_ACP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_CCI_IPCLKPORT_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_CCI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_CCI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK, MUX_CLKCMU_NOCL0_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL0_UID_BLK_NOCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_NOCL0, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BLK_NOCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BLK_NOCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_BLK_NOCL0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC1_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC1_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC0_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC0_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_LME_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_LME_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_LME_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_NOCL1A, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_NOCL1A_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_NOCL1A_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_NOCL1A_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC1_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_LME_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_LME_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_LME_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC0_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_HSI1_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_HSI1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_HSI1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_LME_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_LME_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_LME_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_LME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC0_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC1_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_MFC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AST_SI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_G_PPMU_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SIU_2X1_P0_NOCL1A_IPCLKPORT_I_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_2X1_P0_NOCL1A_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_2X1_P0_NOCL1A_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_2X1_P0_NOCL1A_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SIU_4X1_P0_NOCL1A_IPCLKPORT_I_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_4X1_P0_NOCL1A_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_4X1_P0_NOCL1A_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_4X1_P0_NOCL1A_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SIU_8X1_P0_NOCL1A_IPCLKPORT_I_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_8X1_P0_NOCL1A_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_8X1_P0_NOCL1A_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SIU_8X1_P0_NOCL1A_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC2_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_PERIC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_PPMU_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_DPUF_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_DPUF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_DPUF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DNC_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DNC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DNC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DPUF_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DPUF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DPUF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AXI_MI_D0_DPUF_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_MI_D0_DPUF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_MI_D0_DPUF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_MI_D0_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DNC_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DNC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DNC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUB_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUF_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_DPUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_BAAW_P_DNC_IPCLKPORT_I_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BAAW_P_DNC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BAAW_P_DNC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BAAW_P_DNC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_M2M_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_M2M_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_M2M_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_ACEL_MI_D_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_M2M_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_M2M_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_M2M_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AST_MI_G_PPMU_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_RET_IPCLKPORT_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_RET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_RET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_RET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_RET_IPCLKPORT_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_RET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_RET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_RET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1A_UID_BLK_NOCL1A_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_NOCL1A, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BLK_NOCL1A_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BLK_NOCL1A_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_BLK_NOCL1A_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_SLH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1B_NOC0_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1B_NOC0_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_PCLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_PCLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1B_NOC0_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_NOCL1B, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_NOCL1B_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_NOCL1B_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_NOCL1B_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_UFS_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_UFS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_UFS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_UFS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_PCLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_PCLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_HSI0_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1B_NOC0_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_HSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_HSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_SLH_AST_SI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1B_NOC0_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_G_PPMU_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_AD_APB_DIT_IPCLKPORT_PCLKM, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_DIT_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_DIT_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_AD_APB_PDMA_IPCLKPORT_PCLKM, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_TT_IPCLKPORT_PCLKM, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_TT_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_TT_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_SYSMMU_TT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_PDMA_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PDMA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PDMA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_SPDMA_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SPDMA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SPDMA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SPDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_PDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_QE_SPDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_DIT_IPCLKPORT_ICLKL2A, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_DIT_IPCLKPORT_ICLKL2A_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_DIT_IPCLKPORT_ICLKL2A_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_DIT_IPCLKPORT_ICLKL2A_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_XIU_D_TT_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_XIU_D_TT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_XIU_D_TT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_XIU_D_TT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_SYSMMU_S2_TT_IPCLKPORT_CLK_S2, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_TT_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_TT_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_TT_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SYSMMU_S2_DIT_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_VGEN_LITE_NOCL1B_IPCLKPORT_CLK, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_LITE_NOCL1B_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_LITE_NOCL1B_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_LITE_NOCL1B_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_VGEN_SPDMA_IPCLKPORT_CLK, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_SPDMA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_SPDMA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_SPDMA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_VGEN_PDMA_IPCLKPORT_CLK, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_PDMA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_PDMA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_VGEN_PDMA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_DIT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_PPMU_D_TT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_LH_ACEL_MI_ID_DIT_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1B_NOC0_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_ID_DIT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_ID_DIT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_ID_DIT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_LH_ACEL_SI_ID_DIT_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_SI_ID_DIT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_SI_ID_DIT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_SI_ID_DIT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_AD_APB_VGEN_LITE_NOCL1B_IPCLKPORT_PCLKM, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_LITE_NOCL1B_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_LITE_NOCL1B_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_LITE_NOCL1B_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_PDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_AD_APB_VGEN_SPDMA_IPCLKPORT_PCLKM, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_SPDMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_SPDMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_AD_APB_VGEN_SPDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_IPCLKPORT_CLK, MUX_CLKCMU_NOCL1B_NOC0_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_RET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_TREXP_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_TREXP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_TREXP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_TREXP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_DIT_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_DIT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_DIT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_PPMU_DIT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_TREXP_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1B_NOC0_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_TREXP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_TREXP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_TREXP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1B_NOC0_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_XIU_D_TT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_DIT_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1B_NOC0_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_DIT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_DIT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_PPMU_DIT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1B_NOC0_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_LH_ACEL_MI_D_UFS_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1B_NOC0_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_D_UFS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_D_UFS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_ACEL_MI_D_UFS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_UFS_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1B_NOC0_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_UFS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_UFS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AST_MI_G_PPMU_UFS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_SIU_8X1_P0_NOCL1B_IPCLKPORT_I_ACLK, MUX_CLKCMU_NOCL1B_NOC0_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SIU_8X1_P0_NOCL1B_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SIU_8X1_P0_NOCL1B_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SIU_8X1_P0_NOCL1B_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_LH_AXI_MI_ID_TT_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1B_NOC0_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_ID_TT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_ID_TT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_ID_TT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_LH_AXI_SI_ID_TT_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_ID_TT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_ID_TT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_ID_TT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK, MUX_CLKCMU_NOCL1B_NOC1_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_RET_IPCLKPORT_CLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_RET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_RET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_RET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_RET_IPCLKPORT_CLK, MUX_CLKCMU_NOCL1B_NOC0_USER, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_RET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_RET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD0_RET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1B_UID_BLK_NOCL1B_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_NOCL1B, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_BLK_NOCL1B_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_BLK_NOCL1B_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_BLK_NOCL1B_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_NOCL1C_CMU_NOCL1C_IPCLKPORT_PCLK, DIV_CLK_NOCL1C_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_NOCL1C_CMU_NOCL1C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_NOCL1C_CMU_NOCL1C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_NOCL1C_CMU_NOCL1C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_SYSREG_NOCL1C_IPCLKPORT_PCLK, DIV_CLK_NOCL1C_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SYSREG_NOCL1C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SYSREG_NOCL1C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SYSREG_NOCL1C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_PCLK, DIV_CLK_NOCL1C_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_D_NOCL1C_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSTAT_IPCLKPORT_I_CLK, DIV_CLK_NOCL1C_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSTAT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSTAT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_LH_AXI_MI_D_CSTAT_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D_CSTAT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D_CSTAT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK, DIV_CLK_NOCL1C_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK, DIV_CLK_NOCL1C_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_NOCL1C, DIV_CLK_NOCL1C_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_NOCL1C_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_NOCL1C_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_TREX_P_NOCL1C_IPCLKPORT_PCLK_NOCL1C_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_YUVP_IPCLKPORT_I_CLK, DIV_CLK_NOCL1C_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_YUVP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_YUVP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_LH_AST_SI_G_NOCL1C_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AST_SI_G_NOCL1C_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AST_SI_G_NOCL1C_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AST_SI_G_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK, DIV_CLK_NOCL1C_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_D_TZPC_NOCL1C_IPCLKPORT_PCLK, DIV_CLK_NOCL1C_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_D_TZPC_NOCL1C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_D_TZPC_NOCL1C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_D_TZPC_NOCL1C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_RSTNSYNC_CLK_NOCL1C_NOCP_IPCLKPORT_CLK, DIV_CLK_NOCL1C_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_CLK_NOCL1C_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_CLK_NOCL1C_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_CLK_NOCL1C_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSTAT_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSTAT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSTAT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_CSTAT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_YUVP_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_YUVP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_YUVP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_SLH_AST_SI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_G_PPMU_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK, DIV_CLK_NOCL1C_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_PPMU_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK, DIV_CLK_NOCL1C_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_LH_AXI_MI_D3_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D3_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D3_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D3_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_LH_AXI_MI_D4_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D4_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D4_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D4_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_BRP_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_BRP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_BRP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_BRP_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_BRP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_BRP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D1_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_BRP_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_BRP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_BRP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D2_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_YUVP_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_YUVP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_YUVP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_LH_AXI_MI_D0_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D1_YUVP_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D1_YUVP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D1_YUVP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_MI_D1_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_BRP_IPCLKPORT_I_CLK, DIV_CLK_NOCL1C_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_BRP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_BRP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AXI_SI_P_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_BRP_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_BRP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_BRP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SLH_AST_MI_G_PPMU_BRP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_SIU_8X1_P0_NOCL1C_IPCLKPORT_I_ACLK, MUX_CLKCMU_NOCL1C_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SIU_8X1_P0_NOCL1C_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SIU_8X1_P0_NOCL1C_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_SIU_8X1_P0_NOCL1C_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCP_IPCLKPORT_CLK, DIV_CLK_NOCL1C_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_RSTNSYNC_SR_CLK_NOCL1C_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_NOCL1C_UID_BLK_NOCL1C_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_NOCL1C, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_BLK_NOCL1C_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_BLK_NOCL1C_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1C_UID_BLK_NOCL1C_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC0_I2C, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI04, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_I2C, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI04, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_PERIC0, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK, DIV_CLK_PERIC0_I2C, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK, DIV_CLK_PERIC0_I2C, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK, DIV_CLK_PERIC0_I2C, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC0_I2C, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK, DIV_CLK_PERIC1_UART_BT, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI07, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI08, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI09, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI10, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_UART_BT, CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI07, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI08, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_I2C, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_I2C, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI09, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI10, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK, DIV_CLK_PERIC1_SPI_MS_CTRL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK, DIV_CLK_PERIC1_SPI_MS_CTRL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_PERIC1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI07_SPI_I2C, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI08_SPI_I2C, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI07_SPI_I2C, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI08_SPI_I2C, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC1_I2C, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC2_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK, DIV_CLK_PERIC2_USI00, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK, DIV_CLK_PERIC2_USI01, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK, DIV_CLK_PERIC2_USI02, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK, DIV_CLK_PERIC2_USI03, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK, DIV_CLK_PERIC2_USI05, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK, DIV_CLK_PERIC2_USI06, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC2_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC2_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC2_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC2_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC2_USI00, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC2_USI02, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC2_USI03, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK, DIV_CLK_PERIC2_USI06, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC2_USI01, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK, DIV_CLK_PERIC2_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK, DIV_CLK_PERIC2_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK, DIV_CLK_PERIC2_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK, DIV_CLK_PERIC2_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK, DIV_CLK_PERIC2_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK, DIV_CLK_PERIC2_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK, DIV_CLK_PERIC2_SPI_MS_CTRL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK, DIV_CLK_PERIC2_USI05, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK, DIV_CLK_PERIC2_USI11, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC2_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC2_USI11, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK, DIV_CLK_PERIC2_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK, DIV_CLK_PERIC2_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK, DIV_CLK_PERIC2_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK, DIV_CLK_PERIC2_UART_DBG, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK, DIV_CLK_PERIC2_UART_DBG, CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK, DIV_CLK_PERIC2_SPI_MS_CTRL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_PERIC2, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC2_USI00_SPI_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERIC2_USI01_SPI_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC2_USI00_SPI_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC2_USI01_SPI_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK, DIV_CLK_PERIC2_I2C, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_PERIC2_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK, MUX_CLK_PERIS_GIC, CLK_CON_GAT_CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLK_PERIS_GIC, CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK, MUX_CLKCMU_PERIS_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK, MUX_CLK_PERIS_GIC, CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLK_PERIS_GIC, CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_PERIS_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK, MUX_CLK_PERIS_GIC, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, FREE_OSCCLK_PERIS, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, FREE_OSCCLK_PERIS, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_PERIS, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK, MUX_CLKCMU_PERIS_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK, DIV_CLK_PERIS_DDD_CTRL, CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN, MUX_CLK_PERIS_GIC, CLK_CON_GAT_CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_PERIS_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK, MUX_CLK_PERIS_GIC, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_PERIS, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK, DIV_CLK_PERIS_DDD_CTRL, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK, MUX_CLK_S2D_CORE, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK, I_SCLK_S2D, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK, I_SCLK_S2D, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK, MUX_CLK_S2D_CORE, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK, MUX_CLK_S2D_CORE, CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK, MUX_CLK_S2D_CORE, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_S2D_UID_RSTNSYNC_SR_CLK_S2D_CORE_IPCLKPORT_CLK, MUX_CLK_S2D_CORE, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_SR_CLK_S2D_CORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_SR_CLK_S2D_CORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_SR_CLK_S2D_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_SDMA_CMU_SDMA_IPCLKPORT_PCLK, DIV_CLK_SDMA_NOCP, CLK_CON_GAT_CLK_BLK_SDMA_UID_SDMA_CMU_SDMA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_SDMA_CMU_SDMA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_SDMA_CMU_SDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK, DIV_CLK_SDMA_NOC, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK, DIV_CLK_SDMA_NOC, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK, DIV_CLK_SDMA_NOC, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK, DIV_CLK_SDMA_NOC, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK, DIV_CLK_SDMA_NOC, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_SLH_AXI_MI_LP_SDMA_IPCLKPORT_I_CLK, DIV_CLK_SDMA_NOCP, CLK_CON_GAT_CLK_BLK_SDMA_UID_SLH_AXI_MI_LP_SDMA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_SLH_AXI_MI_LP_SDMA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_SLH_AXI_MI_LP_SDMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_SYSREG_SDMA_IPCLKPORT_PCLK, DIV_CLK_SDMA_NOCP, CLK_CON_GAT_CLK_BLK_SDMA_UID_SYSREG_SDMA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_SYSREG_SDMA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_SYSREG_SDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK, DIV_CLK_SDMA_NOC, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_D_TZPC_SDMA_IPCLKPORT_PCLK, DIV_CLK_SDMA_NOCP, CLK_CON_GAT_CLK_BLK_SDMA_UID_D_TZPC_SDMA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_D_TZPC_SDMA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_D_TZPC_SDMA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCD_IPCLKPORT_CLK, DIV_CLK_SDMA_NOC, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCP_IPCLKPORT_CLK, DIV_CLK_SDMA_NOCP, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_CLK_SDMA_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_LH_AST_SI_LD_STRM_SDMADSP0_IPCLKPORT_I_CLK, DIV_CLK_SDMA_NOC, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AST_SI_LD_STRM_SDMADSP0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AST_SI_LD_STRM_SDMADSP0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AST_SI_LD_STRM_SDMADSP0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_IP_SDMA_IPCLKPORT_I_CLK, DIV_CLK_SDMA_NOC, CLK_CON_GAT_CLK_BLK_SDMA_UID_IP_SDMA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_IP_SDMA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_IP_SDMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_LH_AXI_MI_LP_DNCSDMA_IPCLKPORT_I_CLK, DIV_CLK_SDMA_NOC, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_MI_LP_DNCSDMA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_MI_LP_DNCSDMA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_MI_LP_DNCSDMA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCD_IPCLKPORT_CLK, DIV_CLK_SDMA_NOC, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK, DIV_CLK_SDMA_NOC, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA4_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK, DIV_CLK_SDMA_NOC, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA5_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK, DIV_CLK_SDMA_NOC, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA6_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK, DIV_CLK_SDMA_NOC, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_DATA7_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK, DIV_CLK_SDMA_NOC, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK, DIV_CLK_SDMA_NOC, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_LH_AXI_SI_LD_SDMADNC_MMU3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCP_IPCLKPORT_CLK, DIV_CLK_SDMA_NOCP, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_RSTNSYNC_SR_CLK_SDMA_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SDMA_UID_BLK_SDMA_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_SDMA, CLK_CON_GAT_CLK_BLK_SDMA_UID_BLK_SDMA_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_BLK_SDMA_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SDMA_UID_BLK_SDMA_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK, DIV_CLK_SSP_NOCP, CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_SSP_CMU_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK, DIV_CLK_SSP_NOCP, CLK_CON_GAT_CLK_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_BAAW_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK, DIV_CLK_SSP_NOCP, CLK_CON_GAT_CLK_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_D_TZPC_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_LH_AXI_MI_L_STRONG_IPCLKPORT_I_CLK, MUX_CLKCMU_SSP_NOC_USER, CLK_CON_GAT_CLK_BLK_SSP_UID_LH_AXI_MI_L_STRONG_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_LH_AXI_MI_L_STRONG_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_LH_AXI_MI_L_STRONG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_SLH_AXI_MI_P_SSP_IPCLKPORT_I_CLK, DIV_CLK_SSP_NOCP, CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AXI_MI_P_SSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AXI_MI_P_SSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AXI_MI_P_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_SLH_ACEL_SI_D_SSP_IPCLKPORT_I_CLK, MUX_CLKCMU_SSP_NOC_USER, CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_ACEL_SI_D_SSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_ACEL_SI_D_SSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_ACEL_SI_D_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK, MUX_CLKCMU_SSP_NOC_USER, CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK, DIV_CLK_SSP_NOCP, CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_PPMU_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_ACLK, MUX_CLKCMU_SSP_NOC_USER, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_PCLK, DIV_CLK_SSP_NOCP, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_STRONG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK, MUX_CLKCMU_SSP_NOC_USER, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK, DIV_CLK_SSP_NOCP, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_QE_SSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_SSP_NOC_USER, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCP_IPCLKPORT_CLK, DIV_CLK_SSP_NOCP, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK, MUX_CLKCMU_SSP_NOC_USER, CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_SYSREG_SSP_IPCLKPORT_PCLK, DIV_CLK_SSP_NOCP, CLK_CON_GAT_CLK_BLK_SSP_UID_SYSREG_SSP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_SYSREG_SSP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_SYSREG_SSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_VGEN_LITE_SSP_IPCLKPORT_CLK, DIV_CLK_SSP_NOCP, CLK_CON_GAT_CLK_BLK_SSP_UID_VGEN_LITE_SSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_VGEN_LITE_SSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_VGEN_LITE_SSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK, MUX_CLKCMU_SSP_NOC_USER, CLK_CON_GAT_CLK_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_XIU_D_SSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK, DIV_CLK_SSP_NOCP, CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_AD_APB_SYSMMU_SSP_IPCLKPORT_PCLKM, MUX_CLKCMU_SSP_NOC_USER, CLK_CON_GAT_CLK_BLK_SSP_UID_AD_APB_SYSMMU_SSP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_AD_APB_SYSMMU_SSP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_AD_APB_SYSMMU_SSP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_SYSMMU_SSP_IPCLKPORT_CLK_S2, MUX_CLKCMU_SSP_NOC_USER, CLK_CON_GAT_CLK_BLK_SSP_UID_SYSMMU_SSP_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_SYSMMU_SSP_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_SYSMMU_SSP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_SLH_AST_SI_G_PPMU_SSP_IPCLKPORT_I_CLK, MUX_CLKCMU_SSP_NOC_USER, CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AST_SI_G_PPMU_SSP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AST_SI_G_PPMU_SSP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_SLH_AST_SI_G_PPMU_SSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_SSP_NOC_USER, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_SSP, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_OTP_DESERIAL_SSS_HIDE_SECKEY_IPCLKPORT_I_CLK, FREE_OSCCLK_SSP, CLK_CON_GAT_CLK_BLK_SSP_UID_OTP_DESERIAL_SSS_HIDE_SECKEY_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_OTP_DESERIAL_SSS_HIDE_SECKEY_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_OTP_DESERIAL_SSS_HIDE_SECKEY_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK, DIV_CLK_SSP_NOCP, CLK_CON_GAT_CLK_BLK_SSP_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCP_IPCLKPORT_CLK, DIV_CLK_SSP_NOCP, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_BLK_SSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_SSP, CLK_CON_GAT_CLK_BLK_SSP_UID_BLK_SSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_BLK_SSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_BLK_SSP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_SSP, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_SSP_UID_RSTNSYNC_SR_CLK_SSP_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_STRONG_UID_STRONG_CMU_STRONG_IPCLKPORT_PCLK, DIV_CLK_SSP_NOCP, CLK_CON_GAT_CLK_BLK_STRONG_UID_STRONG_CMU_STRONG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_STRONG_UID_STRONG_CMU_STRONG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_STRONG_UID_STRONG_CMU_STRONG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_STRONG, CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_IPCLKPORT_CLK, FREE_OSCCLK_STRONG, CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_STRONG_UID_RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_UFD_CMU_UFD_IPCLKPORT_PCLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_CMU_UFD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_CMU_UFD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_CMU_UFD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_D_TZPC_UFD_IPCLKPORT_PCLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_D_TZPC_UFD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_D_TZPC_UFD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_D_TZPC_UFD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_IPCLKPORT_CLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_SLH_AXI_MI_LP_CMGPUFD_IPCLKPORT_I_CLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_LP_CMGPUFD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_LP_CMGPUFD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_LP_CMGPUFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_SLH_AXI_MI_P_UFD_IPCLKPORT_I_CLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_P_UFD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_P_UFD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_MI_P_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_PDMA_UFD_IPCLKPORT_ACLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_PDMA_UFD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_PDMA_UFD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_PDMA_UFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_SYSREG_UFD_IPCLKPORT_PCLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_UFD_IPCLKPORT_CLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_UFD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_XIU_DP_UFD_IPCLKPORT_ACLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_DP_UFD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_DP_UFD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_DP_UFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_PCLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_ACLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_PPMU_D_UFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_VGEN_LITE_D_UFD_IPCLKPORT_CLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_VGEN_LITE_D_UFD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_VGEN_LITE_D_UFD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_VGEN_LITE_D_UFD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_SLH_AXI_SI_D_UFD_IPCLKPORT_I_CLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_D_UFD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_D_UFD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_D_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_XIU_D_UFD_IPCLKPORT_ACLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_D_UFD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_D_UFD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_XIU_D_UFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_SLH_AXI_SI_LD_UFDDNC_IPCLKPORT_I_CLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LD_UFDDNC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LD_UFDDNC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LD_UFDDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_SRAM_MIU_UFD_IPCLKPORT_ACLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_SRAM_MIU_UFD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SRAM_MIU_UFD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SRAM_MIU_UFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_PCLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_SCLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_I3C_UFD_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_BAAW_D_UFDDNC_IPCLKPORT_I_PCLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_BAAW_D_UFDDNC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_BAAW_D_UFDDNC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_BAAW_D_UFDDNC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_SYSREG_UFD_SECURE_IPCLKPORT_PCLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_SECURE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_SECURE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSREG_UFD_SECURE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_IPCLKPORT_CLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_ID_COMP_UFD_IPCLKPORT_I_CLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_ID_COMP_UFD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_ID_COMP_UFD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_ID_COMP_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_SLH_AXI_SI_LP_UFDCSIS_IPCLKPORT_I_CLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LP_UFDCSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LP_UFDCSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AXI_SI_LP_UFDCSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_SLH_AST_MI_OTF_CSISUFD_IPCLKPORT_I_CLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_MI_OTF_CSISUFD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_MI_OTF_CSISUFD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_MI_OTF_CSISUFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S1, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S2, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SYSMMU_D_UFD_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_SLH_AST_SI_G_PPMU_UFD_IPCLKPORT_I_CLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_SI_G_PPMU_UFD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_SI_G_PPMU_UFD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_SLH_AST_SI_G_PPMU_UFD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_LH_AST_SI_OTF_UFDDNC_IPCLKPORT_I_CLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_LH_AST_SI_OTF_UFDDNC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_LH_AST_SI_OTF_UFDDNC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_LH_AST_SI_OTF_UFDDNC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_BLK_UFD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_UFD, CLK_CON_GAT_CLK_BLK_UFD_UID_BLK_UFD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_BLK_UFD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_BLK_UFD_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_IPCLKPORT_CLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_IPCLKPORT_CLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_IPCLKPORT_CLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_AXI_US_32TO128_UFD_IPCLKPORT_ACLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_US_32TO128_UFD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_US_32TO128_UFD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_US_32TO128_UFD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFD_UID_AXI_DS_128TO32_UFD_IPCLKPORT_MAINCLK, MUX_CLK_UFD_NOC, CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_DS_128TO32_UFD_IPCLKPORT_MAINCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_DS_128TO32_UFD_IPCLKPORT_MAINCLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFD_UID_AXI_DS_128TO32_UFD_IPCLKPORT_MAINCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN, MUX_CLKCMU_UFS_MMC_CARD_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, MUX_CLKCMU_UFS_UFS_EMBD_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK, MUX_CLKCMU_UFS_MMC_CARD_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK, MUX_CLKCMU_UFS_UFS_EMBD_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_UFS, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_UFS, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK, FREE_OSCCLK_UFS, CLK_CON_GAT_CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK, MUX_CLKCMU_UFS_NOC_USER, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_UFS, CLK_CON_GAT_CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK, DIV_CLK_VTS_DMIC_IF, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK, DIV_CLK_VTS_DMIC_IF, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK, DIV_CLK_VTS_SERIAL_LIF, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK, DIV_CLK_VTS_SERIAL_LIF_CORE, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK, DIV_CLK_VTS_DMIC_IF, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK, DIV_CLK_VTS_CPU, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN, DIV_CLK_VTS_CPU, CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK, DIV_CLK_VTS_CPU, CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK, DIV_CLK_VTS_CPU, CLK_CON_GAT_CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK, DIV_CLK_VTS_CPU, CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKVTS_AUD_DMIC1, MUX_CLKVTS_AUD_DMIC1, CLK_CON_GAT_CLKVTS_AUD_DMIC1_CG_VAL, CLK_CON_GAT_CLKVTS_AUD_DMIC1_MANUAL, CLK_CON_GAT_CLKVTS_AUD_DMIC1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLKVTS_AUD_DMIC0, DIV_CLKVTS_AUD_DMIC0, CLK_CON_GAT_CLKVTS_AUD_DMIC0_CG_VAL, CLK_CON_GAT_CLKVTS_AUD_DMIC0_MANUAL, CLK_CON_GAT_CLKVTS_AUD_DMIC0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK, DIV_CLKVTS_AUD_DMIC1, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU, DIV_CLK_VTS_CPU, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_VTS, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK, DIV_CLK_VTS_NOC, CLK_CON_GAT_CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK, DIV_CLK_VTS_SERIAL_LIF, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK, DIV_CLK_VTS_SERIAL_LIF_CORE, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK, DIV_CLK_VTS_DMIC_IF, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK, DIV_CLK_VTS_CPU, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_VTS, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_YUVP_CMU_YUVP_IPCLKPORT_PCLK, DIV_CLK_YUVP_NOCP, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_CMU_YUVP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_CMU_YUVP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_CMU_YUVP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_AD_APB_YUVP_IPCLKPORT_PCLKM, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_AD_APB_YUVP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_AD_APB_YUVP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_AD_APB_YUVP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_SLH_AXI_MI_P_YUVP_IPCLKPORT_I_CLK, DIV_CLK_YUVP_NOCP, CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_MI_P_YUVP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_MI_P_YUVP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_MI_P_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCD_IPCLKPORT_CLK, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCP_IPCLKPORT_CLK, DIV_CLK_YUVP_NOCP, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_CLK_YUVP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_SYSREG_YUVP_IPCLKPORT_PCLK, DIV_CLK_YUVP_NOCP, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSREG_YUVP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSREG_YUVP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSREG_YUVP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_ACLK, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_PCLK, DIV_CLK_YUVP_NOCP, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D0_YUVP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S1, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_XIU_D0_YUVP_IPCLKPORT_ACLK, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D0_YUVP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D0_YUVP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D0_YUVP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_LH_AST_MI_OTF_MCSCYUVP_IPCLKPORT_I_CLK, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_MI_OTF_MCSCYUVP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_MI_OTF_MCSCYUVP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_MI_OTF_MCSCYUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_D_TZPC_YUVP_IPCLKPORT_PCLK, DIV_CLK_YUVP_NOCP, CLK_CON_GAT_CLK_BLK_YUVP_UID_D_TZPC_YUVP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_D_TZPC_YUVP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_D_TZPC_YUVP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S2, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D0_YUVP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_LH_AST_SI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF0_YUVPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_PCLK, DIV_CLK_YUVP_NOCP, CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_DDD_YUVP_IPCLKPORT_CK_IN, MUX_CLKCMU_YUVP_NOC_USER, CLK_CON_GAT_CLK_BLK_YUVP_UID_DDD_YUVP_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_DDD_YUVP_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_DDD_YUVP_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_VGEN_LITE_D0_YUVP_IPCLKPORT_CLK, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D0_YUVP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D0_YUVP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D0_YUVP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_ATCLK, DIV_CLK_YUVP_DDD_CTRL, CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_ATCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_ATCLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_BUSIF_DDD_YUVP_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_SLH_AST_SI_G_PPMU_YUVP_IPCLKPORT_I_CLK, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AST_SI_G_PPMU_YUVP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AST_SI_G_PPMU_YUVP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AST_SI_G_PPMU_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCD_IPCLKPORT_CLK, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_ACLK, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_PCLK, DIV_CLK_YUVP_NOCP, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_PPMU_D1_YUVP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_LH_AXI_SI_D0_YUVP_IPCLKPORT_I_CLK, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AXI_SI_D0_YUVP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AXI_SI_D0_YUVP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AXI_SI_D0_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_SLH_AXI_SI_D1_YUVP_IPCLKPORT_I_CLK, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_SI_D1_YUVP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_SI_D1_YUVP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_SLH_AXI_SI_D1_YUVP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_XIU_D1_YUVP_IPCLKPORT_ACLK, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D1_YUVP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D1_YUVP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_XIU_D1_YUVP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S1, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S2, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_SYSMMU_D1_YUVP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_SIU_G_PPMU_YUVP_IPCLKPORT_I_ACLK, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_SIU_G_PPMU_YUVP_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_SIU_G_PPMU_YUVP_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_SIU_G_PPMU_YUVP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_VGEN_LITE_D1_YUVP_IPCLKPORT_CLK, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D1_YUVP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D1_YUVP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_VGEN_LITE_D1_YUVP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF0, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF0_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF0_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF1, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF1_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF1_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_YUVP_IPCLKPORT_CLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCP_IPCLKPORT_CLK, DIV_CLK_YUVP_NOCP, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_BLK_YUVP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, FREE_OSCCLK_YUVP, CLK_CON_GAT_CLK_BLK_YUVP_UID_BLK_YUVP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_BLK_YUVP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_BLK_YUVP_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_LH_AST_SI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK, DIV_CLK_YUVP_NOC, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_LH_AST_SI_OTF1_YUVPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
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CLK_GATE(CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_DDD_CTRL_IPCLKPORT_CLK, DIV_CLK_YUVP_DDD_CTRL, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_DDD_CTRL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_DDD_CTRL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_DDD_CTRL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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|
CLK_GATE(CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_FREE_OSCCLK_IPCLKPORT_CLK, FREE_OSCCLK_YUVP, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_FREE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_FREE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_YUVP_UID_RSTNSYNC_SR_CLK_YUVP_FREE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
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};
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|
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unsigned int cmucal_fixed_rate_size = 99;
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struct cmucal_clk_fixed_rate cmucal_fixed_rate_list[] = {
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FIXEDRATE(OSCCLK_RCO_ALIVE, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(CLK_RCO_ALIVE, 49152000, EMPTY_CAL_ID),
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FIXEDRATE(CLK_RCO_I3C_PMIC, 49152000, EMPTY_CAL_ID),
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FIXEDRATE(RCO_400, 393216000, EMPTY_CAL_ID),
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FIXEDRATE(RTCCLK_ALIVE, 32768, EMPTY_CAL_ID),
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FIXEDRATE(FREE_OSCCLK_ALIVE, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(FREE_OSCCLK_ALLCSIS, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(IOCLK_AUDIOCDCLK0, 100000000, EMPTY_CAL_ID),
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FIXEDRATE(IOCLK_AUDIOCDCLK1, 100000000, EMPTY_CAL_ID),
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FIXEDRATE(IOCLK_AUDIOCDCLK2, 100000000, EMPTY_CAL_ID),
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FIXEDRATE(CLKIO_AUD_DSIF, 100000000, EMPTY_CAL_ID),
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FIXEDRATE(CLK_RCO_AUD, 49152000, EMPTY_CAL_ID),
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FIXEDRATE(IOCLK_AUDIOCDCLK3, 100000000, EMPTY_CAL_ID),
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FIXEDRATE(IOCLK_AUDIOCDCLK6, 100000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_PLL_AUD, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(FREE_OSCCLK_AUD, 76800000, EMPTY_CAL_ID),
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|
FIXEDRATE(FREE_OSCCLK_BRP, 76800000, EMPTY_CAL_ID),
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|
FIXEDRATE(RTCCLK_CHUB, 32768, EMPTY_CAL_ID),
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|
FIXEDRATE(FREE_OSCCLK_CHUB, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(FREE_OSCCLK_CHUBVTS, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_CMGP, 76800000, EMPTY_CAL_ID),
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|
FIXEDRATE(FREE_OSCCLK_CMGP, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_CMU, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(FREE_OSCCLK_CMU, 76800000, EMPTY_CAL_ID),
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|
FIXEDRATE(OSCCLK_PLL_CMU, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_CPUCL0, 76800000, EMPTY_CAL_ID),
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|
FIXEDRATE(STRETCHER_CLK_CPUCL0, 1700000000, EMPTY_CAL_ID),
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|
FIXEDRATE(OSCCLK_PLL_CPUCL0, 76800000, EMPTY_CAL_ID),
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|
FIXEDRATE(FREE_OSCCLK_CPUCL0, 76800000, EMPTY_CAL_ID),
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|
FIXEDRATE(FREE_OSCCLK_CPUCL0_GLB, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_CPUCL1, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(STRETCHER_CLK_CPUCL1, 1850000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_PLL_CPUCL1, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(FREE_OSCCLK_CPUCL1, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_CPUCL2, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(STRETCHER_CLK_CPUCL2, 2000000000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_PLL_CPUCL2, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(FREE_OSCCLK_CPUCL2, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(FREE_OSCCLK_CSIS, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(FREE_OSCCLK_CSTAT, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_DBGCORE, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(TCXO_IN, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(FREE_OSCCLK_DBGCORE, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(FREE_OSCCLK_DNC, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(FREE_OSCCLK_DPUB, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(FREE_OSCCLK_DPUF, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(OSCCLK_DPUF1, 76800000, EMPTY_CAL_ID),
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FIXEDRATE(FREE_OSCCLK_DPUF1, 76800000, EMPTY_CAL_ID),
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|
FIXEDRATE(FREE_OSCCLK_DRCP, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_DSP, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_DSU, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(STRETCHER_CLK_DSU, 1467000064, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_PLL_DSU, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_DSU, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_G3D, 25600000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_PLL_G3DCORE, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_G3DCORE, 25600000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_GNPU, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_19_2, 19200000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_HSI0, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(RTCCLK_HSI0, 32768, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_HSI0, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_HSI1, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_LME, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_M2M, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_MCSC, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_MFC0, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_MFC1, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_MIF, 25600000, EMPTY_CAL_ID),
|
|
FIXEDRATE(I_CLK_MIF_NOCD_DBG, 533000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_MIF, 25600000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_PLL_MIF, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_NOCL0, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_NOCL0, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_NOCL1A, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_NOCL1A, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_NOCL1B, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_NOCL1B, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_NOCL1C, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_NOCL1C, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_PERIC0, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_PERIC1, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_PERIC2, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_PERIS, 25600000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_PERIS, 25600000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_S2D, 25600000, EMPTY_CAL_ID),
|
|
FIXEDRATE(I_SCLK_S2D, 6500000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_S2D, 25600000, EMPTY_CAL_ID),
|
|
FIXEDRATE(OSCCLK_PLL_S2D, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_SDMA, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_SSP, 25600000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_STRONG, 25600000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_UFD, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_UFS, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(DMIC_CLK0_IN, 100000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(DMCI_CLK1_IN, 100000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(DMIC_CLK2_IN, 100000000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_VTS, 76800000, EMPTY_CAL_ID),
|
|
FIXEDRATE(FREE_OSCCLK_YUVP, 76800000, EMPTY_CAL_ID),
|
|
};
|
|
|
|
unsigned int cmucal_fixed_factor_size = 15;
|
|
struct cmucal_clk_fixed_factor cmucal_fixed_factor_list[] = {
|
|
FIXEDFACTOR(CLKCMU_HSI1_PCIE, GATE_CLKCMU_HSI1_PCIE, 7, CLK_CON_DIV_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(CLK_CPUCL0_DDD_CTRL, CLK_CPUCL0_DDD, 3, CLK_CON_DIV_CLK_CPUCL0_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(CLK_CPUCL1_DDD_CTRL_0, CLK_CPUCL1_DDD_0, 3, CLK_CON_DIV_CLK_CPUCL1_DDD_CTRL_0_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(CLK_CPUCL1_DDD_CTRL_1, CLK_CPUCL1_DDD_1, 3, CLK_CON_DIV_CLK_CPUCL1_DDD_CTRL_1_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(CLK_CPUCL1_DDD_CTRL_2, CLK_CPUCL1_DDD_2, 3, CLK_CON_DIV_CLK_CPUCL1_DDD_CTRL_2_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(CLK_CPUCL2_DDD_CTRL, CLK_CPUCL2_DDD, 3, CLK_CON_DIV_CLK_CPUCL2_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(DIV_CLK_DNC_DDD_CTRL, MUX_CLK_DNC_NOC, 3, CLK_CON_DIV_DIV_CLK_DNC_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(CLK_DSU_DDD_CTRL, CLK_DSU_DDD, 3, CLK_CON_DIV_CLK_DSU_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(CLK_G3D_DDD_CTRL, CLK_G3D_DDD, 3, CLK_CON_DIV_CLK_G3D_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(DIV_CLK_MIF_NOCD, CLKMUX_MIF_DDRPHY2X, 3, CLK_CON_DIV_DIV_CLK_MIF_NOCD_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(DIV_CLK_MIF_DDD_CTRL, DIV_CLK_MIF_NOCD, 3, CLK_CON_DIV_DIV_CLK_MIF_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(CLKCMU_OTP, OSCCLK_PERIS, 7, CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(DIV_CLK_PERIS_DDD_CTRL, MUX_CLK_PERIS_GIC, 3, CLK_CON_DIV_DIV_CLK_PERIS_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(CLK_MIF_NOCD_S2D, CLKCMU_MIF_DDRPHY2X_S2D, 3, CLK_CON_DIV_CLK_MIF_NOCD_S2D_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(DIV_CLK_YUVP_DDD_CTRL, MUX_CLKCMU_YUVP_NOC_USER, 3, CLK_CON_DIV_DIV_CLK_YUVP_DDD_CTRL_ENABLE_AUTOMATIC_CLKGATING),
|
|
FIXEDFACTOR(PLL_AUD_D1, PLL_AUD, 0, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_AUD_D2, PLL_AUD, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_AUD_D4, PLL_AUD, 3, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_MMC_D1, PLL_MMC, 0, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_MMC_D2, PLL_MMC, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_MMC_D4, PLL_MMC, 3, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED0_D1, PLL_SHARED0, 0, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED0_D2, PLL_SHARED0, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED0_D4, PLL_SHARED0, 3, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED1_D1, PLL_SHARED1, 0, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED1_D2, PLL_SHARED1, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED1_D4, PLL_SHARED1, 3, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED2_D1, PLL_SHARED2, 0, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED2_D2, PLL_SHARED2, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED2_D4, PLL_SHARED2, 3, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED3_D1, PLL_SHARED3, 0, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED3_D2, PLL_SHARED3, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED3_D4, PLL_SHARED3, 3, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED4_D1, PLL_SHARED4, 0, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED4_D2, PLL_SHARED4, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED4_D4, PLL_SHARED4, 3, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED_MIF_D1, PLL_SHARED_MIF, 0, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED_MIF_D2, PLL_SHARED_MIF, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_SHARED_MIF_D4, PLL_SHARED_MIF, 3, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_CPUCL0_D1, PLL_CPUCL0, 0, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_CPUCL0_D2, PLL_CPUCL0, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_CPUCL0_D4, PLL_CPUCL0, 3, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_CPUCL1_D1, PLL_CPUCL1, 0, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_CPUCL1_D2, PLL_CPUCL1, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_CPUCL1_D4, PLL_CPUCL1, 3, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_CPUCL2_D1, PLL_CPUCL2, 0, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_CPUCL2_D2, PLL_CPUCL2, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_CPUCL2_D4, PLL_CPUCL2, 3, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_DSU_D1, PLL_DSU, 0, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_DSU_D2, PLL_DSU, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_DSU_D4, PLL_DSU, 3, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_G3D_D1, PLL_G3D, 0, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_G3D_D2, PLL_G3D, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_G3D_D4, PLL_G3D, 3, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_G3D1_D1, PLL_G3D1, 0, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_G3D1_D2, PLL_G3D1, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_G3D1_D4, PLL_G3D1, 3, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_MIF_MAIN_D1, PLL_MIF_MAIN, 0, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_MIF_MAIN_D2, PLL_MIF_MAIN, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_MIF_MAIN_D4, PLL_MIF_MAIN, 3, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_MIF_SUB_D1, PLL_MIF_SUB, 0, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_MIF_SUB_D2, PLL_MIF_SUB, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_MIF_SUB_D4, PLL_MIF_SUB, 3, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_MIF_S2D_D1, PLL_MIF_S2D, 0, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_MIF_S2D_D2, PLL_MIF_S2D, 1, EMPTY_CAL_ID),
|
|
FIXEDFACTOR(PLL_MIF_S2D_D4, PLL_MIF_S2D, 3, EMPTY_CAL_ID),
|
|
};
|
|
|