160 lines
3.5 KiB
C
Executable file
160 lines
3.5 KiB
C
Executable file
/* include/soc/samsung/exynos-migov-shared.h
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*
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* Copyright (C) 2020 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS - Header file for Exynos Multi IP Governor support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __EXYNOS_MIGOV_SHARED_H
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#define __EXYNOS_MIGOV_SHARED_H
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#include <dt-bindings/soc/samsung/exynos-migov.h>
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struct profile_sharing_data {
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s32 monitor;
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s64 profile_time_ms;
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s64 frame_done_time_us;
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s64 frame_vsync_time_us;
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u64 profile_frame_cnt;
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u64 profile_frame_vsync_cnt;
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u64 profile_fence_cnt;
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s64 profile_fence_time_us;
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s32 user_target_fps;
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s32 frame_cnt_by_swap;
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u64 delta_ms_by_swap;
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/* Domain common data */
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s32 max_freq[NUM_OF_DOMAIN];
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s32 min_freq[NUM_OF_DOMAIN];
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s32 freq[NUM_OF_DOMAIN];
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u64 dyn_power[NUM_OF_DOMAIN];
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u64 st_power[NUM_OF_DOMAIN];
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s32 temp[NUM_OF_DOMAIN];
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s32 active_pct[NUM_OF_DOMAIN];
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/* CPU domain private data */
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s32 cpu_active_pct[NUM_OF_CPU_DOMAIN][MAXNUM_OF_CPU];
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/* GPU domain private data */
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u64 q0_empty_pct;
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u64 q1_empty_pct;
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u64 input_nr_avg_cnt;
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u64 rtimes[NUM_OF_TIMEINFO];
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/* MIF domain private data */
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u64 stats0_sum;
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u64 stats0_avg;
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u64 stats1_sum;
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u64 stats_ratio;
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u64 llc_status;
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s32 mif_pm_qos_cur_freq;
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};
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struct tunable_sharing_data {
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s32 monitor;
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s32 profile_only;
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s32 window_period;
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s32 window_number;
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s32 active_pct_thr;
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s32 valid_freq_delta_pct;
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s32 min_sensitivity;
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s32 cpu_bottleneck_thr;
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s32 mif_bottleneck_thr;
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s32 gpu_bottleneck_thr;
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s32 gpu_ar_bottleneck_thr;
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s32 frame_src;
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s32 max_fps;
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s32 dt_ctrl_en;
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s32 dt_over_thr;
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s32 dt_under_thr;
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s32 dt_up_step;
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s32 dt_down_step;
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s32 dpat_upper_thr;
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s32 dpat_lower_thr;
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s32 dpat_lower_cnt_thr;
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s32 dpat_up_step;
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s32 dpat_down_step;
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s32 inc_perf_temp_thr;
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s32 inc_perf_power_thr;
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s32 dyn_mo_control;
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s32 inc_perf_thr;
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s32 dec_perf_thr;
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/* Domain common data */
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bool enabled[NUM_OF_DOMAIN];
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s32 freq_table[NUM_OF_DOMAIN][MAXNUM_OF_DVFS];
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s32 freq_table_cnt[NUM_OF_DOMAIN];
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s32 max_margin[NUM_OF_DOMAIN];
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s32 min_margin[NUM_OF_DOMAIN];
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s32 margin_up_step[NUM_OF_DOMAIN];
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s32 margin_down_step[NUM_OF_DOMAIN];
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s32 margin_default_step[NUM_OF_DOMAIN];
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s32 minlock_low_limit[NUM_OF_DOMAIN];
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s32 maxlock_high_limit[NUM_OF_DOMAIN];
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/* CPU domain private data */
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s32 first_cpu[NUM_OF_CPU_DOMAIN];
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s32 num_of_cpu[NUM_OF_CPU_DOMAIN];
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s32 asv_ids[NUM_OF_CPU_DOMAIN];
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s32 hp_minlock_low_limit[NUM_OF_CPU_DOMAIN];
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s32 lp_minlock_low_limit[NUM_OF_CPU_DOMAIN];
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/* GPU domain private data */
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u64 gpu_hw_status;
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u64 reserved_gpu1;
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u64 reserved_gpu2;
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/* MIF domain private data */
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s32 stats0_mode_min_freq;
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u64 stats0_sum_thr;
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u64 stats0_updown_delta_pct_thr;
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s32 mif_hp_minlock_low_limit;
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/* minlock mode data */
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s32 hp_minlock_fps_delta_pct_thr;
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s32 hp_minlock_power_upper_thr;
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s32 hp_minlock_power_lower_thr;
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s32 runtime_thr[6];
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};
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struct delta_sharing_data {
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s32 id;
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s32 freq_delta_pct;
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u32 freq;
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u64 dyn_power;
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u64 st_power;
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};
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/*
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* 1st argument is migov-id & op-code in set_margin_store
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* | | OPCODE | IP-ID |
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* 31 11 3 0
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*/
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#define IP_ID_MASK 0xF
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#define OP_CODE_MASK 0xFF
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#define OP_CODE_SHIFT 0x4
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enum control_op_code {
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OP_INVALID = 0,
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OP_PM_QOS_MAX = 1,
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OP_PM_QOS_MIN = 2,
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OP_MARGIN = 3,
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OP_MO = 4,
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OP_LLC = 5,
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OP_RTP_TARGETFRAMETIME = 6,
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OP_RTP_TARGETTIMEMARGIN = 7,
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OP_RTP_UTIL_MARGIN = 8,
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OP_RTP_DECON_TIME = 9,
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OP_RTP_COMBCTRL = 10,
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};
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#endif /* EXYNOS_MIGOV_SHARED_H */
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