469 lines
16 KiB
C
Executable file
469 lines
16 KiB
C
Executable file
/*
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* Copyright (c) 2019 Samsung Electronics Co., Ltd.
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*
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* Author: Hajun Sung <hajun.sung@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Device Tree binding constants for S5E8825 interrupt controller.
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*/
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#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_S5E8825_H
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#define _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_S5E8825_H
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define I3C_APM_PMIC_O_INTERRUPT 0
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#define INTREQ__ALIVE_CP_ACTIVE 1
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#define INTREQ__ALIVE_EINT0 2
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#define INTREQ__ALIVE_EINT1 3
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#define INTREQ__ALIVE_EINT2 4
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#define INTREQ__ALIVE_EINT3 5
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#define INTREQ__ALIVE_EINT4 6
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#define INTREQ__ALIVE_EINT5 7
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#define INTREQ__ALIVE_EINT6 8
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#define INTREQ__ALIVE_EINT7 9
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#define INTREQ__ALIVE_EINT8 10
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#define INTREQ__ALIVE_EINT9 11
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#define INTREQ__ALIVE_EINT10 12
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#define INTREQ__ALIVE_EINT11 13
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#define INTREQ__ALIVE_EXT_INTC0 14
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#define INTREQ__ALIVE_EXT_INTC1 15
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#define INTREQ__ALIVE_EXT_INTC2 16
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#define INTREQ__ALIVE_EXT_INTC3 17
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#define INTREQ__ALIVE_EXT_INTC4 18
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#define INTREQ__ALIVE_EXT_INTC5 19
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#define INTREQ__ALIVE_EXT_INTC6 20
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#define INTREQ__ALIVE_EXT_INTC7 21
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#define INTREQ__ALIVE_GNSS_ACTIVE 22
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#define INTREQ__ALIVE_WLBT_ACTIVE 23
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#define INTREQ__COMB_NONSECURE_SYSREG_VGPIO2AP 24
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#define INTREQ__COMB_SFI_CE_NONSECURE_SYSREG_APM 25
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#define INTREQ__COMB_SFI_UCE_NONSECURE_SYSREG_APM 26
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#define INTREQ__DBGCORE_UART 27
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#define INTREQ__I2C_ALIVE0 28
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#define INTREQ__MAILBOX_APM2AP 29
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#define INTREQ__MAILBOX_CHUB2AP 30
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#define INTREQ__MAILBOX_CP2AP_0 31
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#define INTREQ__MAILBOX_CP2AP_1 32
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#define INTREQ__MAILBOX_CP2AP_2 33
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#define INTREQ__MAILBOX_CP2AP_3 34
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#define INTREQ__MAILBOX_CP2AP_4 35
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#define INTREQ__MAILBOX_DBGCORE2AP 36
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#define INTREQ__MAILBOX_GNSS2AP 37
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#define INTREQ__MAILBOX_WLBT2ABOX 38
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#define INTREQ__MAILBOX_WLBT_BT2AP 39
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#define INTREQ__MAILBOX_WLBT_WL2AP 40
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#define INTREQ__NOTIFY 41
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#define INTREQ__RTC_ALARM_INT 42
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#define INTREQ__RTC_TIC_INT_0 43
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#define INTREQ__S_MAILBOX_CP2AP 44
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#define INTREQ__TOP_RTC_ALARM_INT 45
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#define INTREQ__TOP_RTC_TIC_INT_0 46
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#define INTREQ__USI_ALIVE0 47
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#define INTREQ__AUD_ABOX_GIC400_MCPU 48
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#define INTREQ__AUD_WDT 49
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#define INTREQ__SYSMMU_ABOX_S1_NS 50
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#define INTREQ__SYSMMU_ABOX_S1_S 51
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#define INTREQ__SYSMMU_ABOX_S2_NS 52
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#define INTREQ__SYSMMU_ABOX_S2_S 53
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#define INTREQ__PDMA0 54
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#define INTREQ__SPDMA0 55
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#define INTREQ__SYSMMU_AXI_D_BUSC_O_INTERRUPT_S2_NS 56
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#define INTREQ__SYSMMU_AXI_D_BUSC_O_INTERRUPT_S2_S 57
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#define INTREQ__TREX_D_BUSC_DEBUGINTERRUPT1 58
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#define INTREQ__TREX_D_BUSC_PPCINTERRUPT_CORE0 59
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#define INTREQ__EXT_INTE0 60
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#define INTREQ__EXT_INTE1 61
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#define INTREQ__EXT_INTH0_0 62
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#define INTREQ__EXT_INTH0_1 63
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#define INTREQ__EXT_INTH0_2 64
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#define INTREQ__EXT_INTH0_3 65
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#define INTREQ__EXT_INTH0_4 66
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#define INTREQ__EXT_INTH0_5 67
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#define INTREQ__EXT_INTH0_6 68
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#define INTREQ__EXT_INTH0_7 69
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#define INTREQ__EXT_INTH1_0 70
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#define INTREQ__EXT_INTH1_1 71
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#define INTREQ__EXT_INTH1_2 72
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#define INTREQ__EXT_INTH1_3 73
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#define INTREQ__I2C_CHUB1 74
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#define INTREQ__I2C_CHUB3 75
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#define INTREQ__MAILBOX_AP_VTS 76
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#define INTREQ__TIMER_CHUB 77
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#define INTREQ__USI_CHUB0 78
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#define INTREQ__USI_CHUB1 79
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#define INTREQ__USI_CHUB2 80
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#define INTREQ__USI_CHUB3 81
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#define INTREQ__WDT_CHUB 82
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#define INTREQ__WDT_VTS 83
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#define INTRQ_PWM_CHUB_0 84
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#define INTRQ_PWM_CHUB_1 85
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#define INTRQ_PWM_CHUB_2 86
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#define INTRQ_PWM_CHUB_3 87
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#define INTREQ__EXT_INTM00 88
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#define INTREQ__EXT_INTM01 89
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#define INTREQ__EXT_INTM02 90
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#define INTREQ__EXT_INTM03 91
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#define INTREQ__EXT_INTM04 92
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#define INTREQ__EXT_INTM05 93
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#define INTREQ__EXT_INTM06 94
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#define INTREQ__EXT_INTM07 95
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#define INTREQ__EXT_INTM08 96
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#define INTREQ__EXT_INTM09 97
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#define INTREQ__EXT_INTM10 98
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#define INTREQ__EXT_INTM11 99
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#define INTREQ__EXT_INTM12 100
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#define INTREQ__EXT_INTM13 101
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#define INTREQ__EXT_INTM14 102
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#define INTREQ__EXT_INTM15 103
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#define INTREQ__EXT_INTM16 104
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#define INTREQ__EXT_INTM17 105
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#define INTREQ__EXT_INTM18 106
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#define INTREQ__EXT_INTM19 107
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#define INTREQ__EXT_INTM20 108
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#define INTREQ__CPUCL0_CTIIRQ_0 109
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#define INTREQ__CPUCL0_CTIIRQ_1 110
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#define INTREQ__CPUCL0_CTIIRQ_2 111
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#define INTREQ__CPUCL0_CTIIRQ_3 112
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#define INTREQ__CPUCL0_CTIIRQ_4 113
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#define INTREQ__CPUCL0_CTIIRQ_5 114
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#define INTREQ__CPUCL0_CTIIRQ_6 115
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#define INTREQ__CPUCL0_CTIIRQ_7 116
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#define INTREQ__CPUCL0_PMBIRQ_6 117
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#define INTREQ__CPUCL0_PMBIRQ_7 118
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#define INTREQ__I2C_CMGP0 119
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#define INTREQ__I2C_CMGP1 120
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#define INTREQ__I2C_CMGP2 121
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#define INTREQ__I2C_CMGP3 122
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#define INTREQ__I2C_CMGP4 123
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#define INTREQ__I3C_CMGP 124
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#define INTREQ__USI_CMGP0 125
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#define INTREQ__USI_CMGP1 126
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#define INTREQ__USI_CMGP2 127
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#define INTREQ__USI_CMGP3 128
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#define INTREQ__USI_CMGP4 129
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#define INTREQ__CPUCL0_CLUSTERPMUIRQ 130
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#define INTREQ__CPUCL0_COMMIRQ_0 131
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#define INTREQ__CPUCL0_COMMIRQ_1 132
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#define INTREQ__CPUCL0_COMMIRQ_2 133
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#define INTREQ__CPUCL0_COMMIRQ_3 134
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#define INTREQ__CPUCL0_COMMIRQ_4 135
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#define INTREQ__CPUCL0_COMMIRQ_5 136
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#define INTREQ__CPUCL0_COMMIRQ_6 137
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#define INTREQ__CPUCL0_COMMIRQ_7 138
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#define INTREQ__CPUCL0_ERRIRQ_0 139
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#define INTREQ__CPUCL0_ERRIRQ_1 140
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#define INTREQ__CPUCL0_ERRIRQ_2 141
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#define INTREQ__CPUCL0_ERRIRQ_3 142
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#define INTREQ__CPUCL0_ERRIRQ_4 143
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#define INTREQ__CPUCL0_ERRIRQ_5 144
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#define INTREQ__CPUCL0_ERRIRQ_6 145
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#define INTREQ__CPUCL0_ERRIRQ_7 146
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#define INTREQ__CPUCL0_ERRIRQ_8 147
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#define INTREQ__CPUCL0_FAULTIRQ_0 148
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#define INTREQ__CPUCL0_FAULTIRQ_1 149
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#define INTREQ__CPUCL0_FAULTIRQ_2 150
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#define INTREQ__CPUCL0_FAULTIRQ_3 151
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#define INTREQ__CPUCL0_FAULTIRQ_4 152
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#define INTREQ__CPUCL0_FAULTIRQ_5 153
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#define INTREQ__CPUCL0_FAULTIRQ_6 154
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#define INTREQ__CPUCL0_FAULTIRQ_7 155
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#define INTREQ__CPUCL0_FAULTIRQ_8 156
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#define INTREQ__CPUCL0_PMUIRQ_0 157
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#define INTREQ__CPUCL0_PMUIRQ_1 158
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#define INTREQ__CPUCL0_PMUIRQ_2 159
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#define INTREQ__CPUCL0_PMUIRQ_3 160
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#define INTREQ__CPUCL0_PMUIRQ_4 161
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#define INTREQ__CPUCL0_PMUIRQ_5 162
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#define INTREQ__CPUCL0_PMUIRQ_6 163
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#define INTREQ__CPUCL0_PMUIRQ_7 164
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#define INTREQ__OCP_REATOR_CPUCL0_0 165
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#define INTREQ__OCP_REATOR_CPUCL0_1 166
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#define INTREQ__OCP_REATOR_DSU 167
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#define INTREQ__PPC_INSTRRET_LOWER_CPUCL0_0 168
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#define INTREQ__PPC_INSTRRET_LOWER_CPUCL0_1 169
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#define INTREQ__PPC_INSTRRET_UPPER_CPUCL0_0 170
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#define INTREQ__PPC_INSTRRET_UPPER_CPUCL0_1 171
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#define INTREQ__PPC_INSTRRUN_LOWER_CPUCL0_0 172
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#define INTREQ__PPC_INSTRRUN_LOWER_CPUCL0_1 173
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#define INTREQ__PPC_INSTRRUN_UPPER_CPUCL0_0 174
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#define INTREQ__PPC_INSTRRUN_UPPER_CPUCL0_1 175
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#define INTREQ__PPMU_LOWER_CPUCL0 176
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#define INTREQ__PPMU_LOWER_CPUCL1 177
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#define INTREQ__CSIS0 178
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#define INTREQ__CSIS1 179
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#define INTREQ__CSIS2 180
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#define INTREQ__CSIS3 181
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#define INTREQ__CSIS4 182
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#define INTREQ__CSIS5 183
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#define INTREQ__CSIS_DMA0 184
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#define INTREQ__CSIS_DMA1 185
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#define INTREQ__CSIS_DMA2 186
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#define INTREQ__CSIS_DMA3 187
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#define INTREQ__OVERFLOW 188
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#define INTREQ__PDP_TOP0 189
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#define INTREQ__PDP_TOP1 190
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#define INTREQ__PDP_TOP2 191
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#define INTREQ__PDP_TOP3 192
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#define INTREQ__PDP_TOP4 193
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#define INTREQ__PDP_TOP5 194
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#define INTREQ__PDP_TOP6 195
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#define INTREQ__PDP_TOP7 196
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#define INTREQ__STRP_DMA0 197
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#define INTREQ__STRP_DMA1 198
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#define INTREQ__STRP_DMA2 199
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#define INTREQ__SYSMMU_D0_CSIS_S1_NS 200
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#define INTREQ__SYSMMU_D0_CSIS_S1_S 201
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#define INTREQ__SYSMMU_D0_CSIS_S2_NS 202
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#define INTREQ__SYSMMU_D0_CSIS_S2_S 203
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#define INTREQ__SYSMMU_D1_CSIS_S1_NS 204
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#define INTREQ__SYSMMU_D1_CSIS_S1_S 205
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#define INTREQ__SYSMMU_D1_CSIS_S2_NS 206
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#define INTREQ__SYSMMU_D1_CSIS_S2_S 207
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#define INTREQ__SYSMMU_D2_CSIS_S1_NS 208
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#define INTREQ__SYSMMU_D2_CSIS_S1_S 209
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#define INTREQ__SYSMMU_D2_CSIS_S2_NS 210
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#define INTREQ__SYSMMU_D2_CSIS_S2_S 211
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#define INTREQ__SYSMMU_D3_CSIS_S1_NS 212
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#define INTREQ__SYSMMU_D3_CSIS_S1_S 213
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#define INTREQ__SYSMMU_D3_CSIS_S2_NS 214
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#define INTREQ__SYSMMU_D3_CSIS_S2_S 215
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#define INTREQ__ZSL_DMA0 216
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#define INTREQ__ZSL_DMA1 217
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#define INTREQ__ZSL_DMA2 218
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#define INTREQ__DPU_DECON0_DQE_DIMMING_END 219
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#define INTREQ__DPU_DECON0_DQE_DIMMING_START 220
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#define INTREQ__DPU_DECON0_EXTRA 221
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#define INTREQ__HDCP 222
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#define INTREQ__TBASE 223
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#define INTREQ__SECURE_LOG 224
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#define INTREQ__RPMB 225
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#define INTREQ__DPU_DECON0_FRAME_DONE 226
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#define INTREQ__DPU_DECON0_FRAME_START 227
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#define INTREQ__DPU_DECON1_DQE_DIMMING_END 228
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#define INTREQ__DPU_DECON1_DQE_DIMMING_START 229
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#define INTREQ__DPU_DECON1_EXTRA 230
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#define INTREQ__DPU_DECON1_FRAME_DONE 231
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#define INTREQ__DPU_DECON1_FRAME_START 232
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#define INTREQ__DPU_DMA_DSIMFC0 233
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#define INTREQ__DPU_DMA_L0 234
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#define INTREQ__DPU_DMA_L1 235
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#define INTREQ__DPU_DMA_L2 236
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#define INTREQ__DPU_DMA_L3 237
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#define INTREQ__DPU_DMA_L4 238
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#define INTREQ__DPU_DMA_L5 239
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#define INTREQ__DPU_DMA_L6 240
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#define INTREQ__DPU_DMA_L7 241
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#define INTREQ__DPU_DMA_RCD0 242
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#define INTREQ__DPU_DMA_WB 243
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#define INTREQ__DPU_DPP_L0 244
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#define INTREQ__DPU_DPP_L1 245
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#define INTREQ__DPU_DPP_L2 246
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#define INTREQ__DPU_DPP_L3 247
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#define INTREQ__DPU_DPP_L4 248
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#define INTREQ__DPU_DPP_L5 249
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#define INTREQ__DPU_DPP_L6 250
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#define INTREQ__DPU_DPP_L7 251
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#define INTREQ__DPU_DSIM0 252
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#define INTREQ__SYSMMU_D0_DPU_S1_NS 253
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#define INTREQ__SYSMMU_D0_DPU_S1_S 254
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#define INTREQ__SYSMMU_D0_DPU_S2_NS 255
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#define INTREQ__SYSMMU_D0_DPU_S2_S 256
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#define INTREQ__SYSMMU_D1_DPU_S1_NS 257
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#define INTREQ__SYSMMU_D1_DPU_S1_S 258
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#define INTREQ__SYSMMU_D1_DPU_S2_NS 259
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#define INTREQ__SYSMMU_D1_DPU_S2_S 260
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#define INTREQ__G3D_IRQEVENT 261
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#define INTREQ__G3D_IRQGPU 262
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#define INTREQ__G3D_IRQJOB 263
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#define INTREQ__G3D_IRQMMU 264
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#define INTREQ__G3D_O_OCP_THROTT 265
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#define INTREQ__SYSMMU_D_G3D_S2_NS 266
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#define INTREQ__SYSMMU_D_G3D_S2_S 267
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#define INTREQ__GNSS_SW_INT 268
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#define INTREQ__GNSS_WAKEUP_INT 269
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#define INTREQ__GNSS_WDOG_RESET 270
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#define INTREQ__GPIO_HSI 271
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#define INTREQ__GPIO_HSI_UFS 272
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#define INTREQ__S2MPU_D_HSI_NS 273
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#define INTREQ__S2MPU_D_HSI_S 274
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#define INTREQ__UFS_EMBD 275
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#define INTREQ__ISP_0 276
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#define INTREQ__ISP_1 277
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#define INTREQ__SYSMMU_ISP_S1_NS 278
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#define INTREQ__SYSMMU_ISP_S1_S 279
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#define INTREQ__SYSMMU_ISP_S2_NS 280
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#define INTREQ__DERATE_INTR_MIF1 281
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#define INTREQ__DMC_INTR_MIF1 282
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#define INTREQ__DMC_PEREV_INTR_MIF1 283
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#define INTREQ__HIGHTEMP_INTR_MIF1 284
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#define INTREQ__NORMTEMP_INTR_MIF1 285
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#define INTREQ__PPMU_UPPER_OR_NORMAL_MIF1 286
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#define INTREQ__TEMPERR_INTR_MIF1 287
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#define INTREQ__SYSMMU_ISP_S2_S 288
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#define INTREQ__JPEG0 289
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#define INTREQ__MSCL 290
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#define INTREQ__SYSMMU_D_M2M_S1_NS 291
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#define INTREQ__SYSMMU_D_M2M_S1_S 292
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#define INTREQ__SYSMMU_D_M2M_S2_NS 293
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#define INTREQ__SYSMMU_D_M2M_S2_S 294
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#define INTREQ__GDC_IRQ 295
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#define INTREQ__MCSC_IRQ 296
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#define INTREQ__ORBMCH_O_INT 297
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#define INTREQ__SYSMMU_D0_MCSC_S1_NS 298
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#define INTREQ__SYSMMU_D0_MCSC_S1_S 299
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#define INTREQ__SYSMMU_D0_MCSC_S2_NS 300
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#define INTREQ__SYSMMU_D0_MCSC_S2_S 301
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#define INTREQ__SYSMMU_D1_MCSC_S1_NS 302
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#define INTREQ__SYSMMU_D1_MCSC_S1_S 303
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#define INTREQ__SYSMMU_D1_MCSC_S2_NS 304
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#define INTREQ__SYSMMU_D1_MCSC_S2_S 305
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#define INTREQ__TREX_D_CAM_DEBUGINTERRUPT 306
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#define INTREQ__MFC 307
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#define INTREQ__SYSMMU_MFC_INTERRUPT_S1_NS 308
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#define INTREQ__SYSMMU_MFC_INTERRUPT_S1_S 309
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#define INTREQ__SYSMMU_MFC_INTERRUPT_S2_NS 310
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#define INTREQ__SYSMMU_MFC_INTERRUPT_S2_S 311
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#define INTREQ__DERATE_INTR_MIF0 312
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#define INTREQ__DMC_ASP_INTR_MIF0 313
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#define INTREQ__DMC_INTR_MIF0 314
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#define INTREQ__DMC_PEREV_INTR_MIF0 315
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#define INTREQ__DMC_PPMPU_INTR_MIF0 316
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#define INTREQ__HIGHTEMP_INTR_MIF0 317
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#define INTREQ__NORMTEMP_INTR_MIF0 318
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#define INTREQ__PPMU_UPPER_OR_NORMAL_MIF0 319
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#define INTREQ__TEMPERR_INTR_MIF0 320
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#define INTREQ__DMC_ASP_INTR_MIF1 321
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#define INTREQ__DMC_PPMPU_INTR_MIF1 322
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#define INTREQ__RESET_REQ 323
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#define SFR_BUS_RDY 324
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#define INTREQ__OCP_THROTT_INTR_NPUS 325
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#define INTREQ__SYSMMU_D0_NPUS_INTERRUPT_S1_NS 326
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#define INTREQ__SYSMMU_D0_NPUS_INTERRUPT_S1_S 327
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#define INTREQ__SYSMMU_D0_NPUS_INTERRUPT_S2_NS 328
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#define INTREQ__SYSMMU_D0_NPUS_INTERRUPT_S2_S 329
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#define INTREQ__SYSMMU_D1_NPUS_INTERRUPT_S1_NS 330
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#define INTREQ__SYSMMU_D1_NPUS_INTERRUPT_S1_S 331
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#define INTREQ__SYSMMU_D1_NPUS_INTERRUPT_S2_NS 332
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#define INTREQ__SYSMMU_D1_NPUS_INTERRUPT_S2_S 333
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#define O_INTREQ_NS_NPUS_HOST_0 334
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#define O_INTREQ_NS_NPUS_HOST_1 335
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#define O_INTREQ_NS_NPUS_HOST_2 336
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#define O_INTREQ_NS_NPUS_HOST_3 337
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#define O_INTREQ_NS_NPUS_HOST_4 338
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#define O_INTREQ_NS_NPUS_HOST_5 339
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#define O_INTREQ_NS_NPUS_HOST_6 340
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#define O_INTREQ_NS_NPUS_HOST_7 341
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#define O_INTREQ_S_NPUS_HOST_0 342
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#define O_INTREQ_S_NPUS_HOST_1 343
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#define O_INTREQ_S_NPUS_HOST_2 344
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#define O_INTREQ_S_NPUS_HOST_3 345
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#define O_INTREQ_S_NPUS_HOST_4 346
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#define O_INTREQ_S_NPUS_HOST_5 347
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#define O_INTREQ_S_NPUS_HOST_6 348
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#define O_INTREQ_S_NPUS_HOST_7 349
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#define INTREQ__GPIO_PERI 350
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#define INTREQ__GPIO_PERIMMC 351
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#define INTREQ__MCT_G0 352
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#define INTREQ__MCT_G1 353
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#define INTREQ__MCT_G2 354
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#define INTREQ__MCT_G3 355
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#define INTREQ__MCT_L0 356
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#define INTREQ__MCT_L1 357
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#define INTREQ__MCT_L2 358
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#define INTREQ__MCT_L3 359
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#define INTREQ__MCT_L4 360
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#define INTREQ__MCT_L5 361
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#define INTREQ__MCT_L6 362
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#define INTREQ__MCT_L7 363
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#define INTREQ__MMC_CARD 364
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#define INTREQ__OTP_CON_TOP 365
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#define INTREQ__PWM0 366
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#define INTREQ__PWM1 367
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#define INTREQ__PWM2 368
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#define INTREQ__PWM3 369
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#define INTREQ__PWM4 370
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#define INTREQ__S2MPU_D_PERI_S2_NS 371
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#define INTREQ__S2MPU_D_PERI_S2_S 372
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#define INTREQ__TMU 373
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#define INTREQ__UART_DBG 374
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#define INTREQ__USI00_I2C 375
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#define INTREQ__USI00_USI 376
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#define INTREQ__USI01_I2C 377
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#define INTREQ__USI01_USI 378
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#define INTREQ__USI02_I2C 379
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#define INTREQ__USI02_USI 380
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#define INTREQ__USI03_I2C 381
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#define INTREQ__USI03_USI 382
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#define INTREQ__USI04_I2C 383
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#define INTREQ__USI04_USI 384
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#define INTREQ__USI05_I2C 385
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#define INTREQ__USI05_USI 386
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#define INTREQ__USI06_I2C 387
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#define INTREQ__USI06_USI 388
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#define INTREQ__USI07_I2C 389
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#define INTREQ__WDT0 390
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#define INTREQ__WDT1 391
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#define INTREQ__SYSMMU_TAA_S1_NS 392
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#define INTREQ__SYSMMU_TAA_S1_S 393
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#define INTREQ__SYSMMU_TAA_S2_NS 394
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#define INTREQ__SYSMMU_TAA_S2_S 395
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#define INTREQ__TAA_CH0_0 396
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#define INTREQ__TAA_CH0_1 397
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#define INTREQ__TAA_CH1_0 398
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#define INTREQ__TAA_CH1_1 399
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#define INTREQ__TAA_CH2_0 400
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#define INTREQ__TAA_CH2_1 401
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#define INTREQ__SYSMMU_D0_TNR_S1_NS 402
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#define INTREQ__SYSMMU_D0_TNR_S1_S 403
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#define INTREQ__SYSMMU_D0_TNR_S2_NS 404
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#define INTREQ__SYSMMU_D0_TNR_S2_S 405
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#define INTREQ__SYSMMU_D1_TNR_S1_NS 406
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#define INTREQ__SYSMMU_D1_TNR_S1_S 407
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#define INTREQ__SYSMMU_D1_TNR_S2_NS 408
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#define INTREQ__SYSMMU_D1_TNR_S2_S 409
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#define INTREQ__TNR_0 410
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#define INTREQ__TNR_1 411
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#define INTREQ__S2MPU_D_USB_NS 412
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#define INTREQ__S2MPU_D_USB_S 413
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#define INTREQ__USB2_REMOTE_CONNECT_GIC 414
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#define INTREQ__USB2_REMOTE_TIMER_GIC 415
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#define INTREQ__USB2_REMOTE_WAKEUP_GIC 416
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#define INTREQ__USB2_REWA_WAKEUP_REQ 417
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#define INTREQ__USB20DRD_GIC0 418
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#define INTREQ__USB20DRD_GIC1 419
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#define INTREQ__USB20_PHY_FSVMINUS_GIC 420
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#define INTREQ__USB20_PHY_FSVPLUS_GIC 421
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#define WB2AP_CFG_REQ 422
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#define WB2AP_WDOG_RESET_REQ_IRQ 423
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#define INTREQ__TEEGRIS_EVENT 428
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#define INTREQ__TEEGRIS_PANIC 429
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#define INTREQ__S2_LV3_TABLE_ALLOC 430
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#define INTREQ_SYSMMU_ACEL_D2_MODEM_S 458
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#define INTREQ_SYSMMU_ACEL_D2_MODEM_NS 459
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#define INTREQ_SYSMMU_ACEL_D_DIT_S 460
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#define INTREQ_SYSMMU_ACEL_D_DIT_NS 461
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#define INTREQ__TREX_D_CORE_MODEM1 462
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#define INTREQ__TREX_D_CORE_CORE1 463
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#define INTREQ__PUF_UNCORRECT_INT 464
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#define INTREQ__PUF_SEC_INT 465
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#define INTREQ__CORE_CON_ALIVE_INTERRUPT 466
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#define INTREQ__HWSEMA_ACK_INT 467
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#define INTREQ__HWSEMA_TIMEOUT 468
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#define INTREQ__HWSEMA_INT 469
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#define INTREQ__HWSEMA_DMA 470
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#define INTREQ__HWSEMA_KM 471
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#define INTREQ__TREX_D_NRT_DEBUG_INT 472
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#define INTREQ__TREX_P_CORE_DEBUG_INT 473
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#define INTREQ__TREX_D_CORE_DEBUG_INT 474
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#define INTREQ__DIT_RX2_END 475
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#define INTREQ__DIT_RX1_END 476
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#define INTREQ__DIT_RX0_END 477
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#define INTREQ__DIT_TX_END 478
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#define INTREQ__DIT_BUS_ERR 479
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#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_S5E8825_H */
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