1307 lines
111 KiB
C
Executable file
1307 lines
111 KiB
C
Executable file
/*
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* Copyright (c) 2018 Samsung Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Common Clock Framework support for Exynos2100 SoC.
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <soc/samsung/cal-if.h>
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#include <dt-bindings/clock/s5e9925_evt0.h>
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#include "../../soc/samsung/cal-if/s5e9925_evt0/cmucal/cmucal-vclk.h"
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#include "../../soc/samsung/cal-if/s5e9925_evt0/cmucal/cmucal-node.h"
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#include "../../soc/samsung/cal-if/s5e9925_evt0/cmucal/cmucal-qch.h"
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#include "../../soc/samsung/cal-if/s5e9925_evt0/cmucal/clkout_s5e9925.h"
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#include "composite.h"
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static struct samsung_clk_provider *s5e9925_clk_provider;
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bool clk_exynos_skip_hw;
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/*
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* list of controller registers to be saved and restored during a
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* suspend/resume cycle.
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*/
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/* fixed rate clocks generated outside the soc */
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struct samsung_fixed_rate s5e9925_fixed_rate_ext_clks[] = {
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FRATE(OSCCLK1, "fin_pll1", NULL, 0, 76800000),
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FRATE(OSCCLK2, "fin_pll2", NULL, 0, 25600000),
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};
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/* HWACG VCLK */
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struct init_vclk s5e9925_alive_hwacg_vclks[] = {
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HWACG_VCLK(UMUX_CLK_RCO_ALIVE, MUX_CLK_RCO_ALIVE_USER, "UMUX_CLK_RCO_ALIVE", NULL, 0, 0, NULL),
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HWACG_VCLK(UMUX_CLKMUX_ALIVE_RCO_SPMI, MUX_CLKMUX_ALIVE_RCO_SPMI_USER, "UMUX_CLKMUX_ALIVE_RCO_SPMI", NULL, 0, 0, NULL),
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HWACG_VCLK(GATE_ALIVE_CMU_ALIVE_QCH, ALIVE_CMU_ALIVE_QCH, "GATE_ALIVE_CMU_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APBIF_GPIO_ALIVE_QCH, APBIF_GPIO_ALIVE_QCH, "GATE_APBIF_GPIO_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APBIF_INTCOMB_VGPIO2AP_QCH, APBIF_INTCOMB_VGPIO2AP_QCH, "GATE_APBIF_INTCOMB_VGPIO2AP_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APBIF_INTCOMB_VGPIO2APM_QCH, APBIF_INTCOMB_VGPIO2APM_QCH, "GATE_APBIF_INTCOMB_VGPIO2APM_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APBIF_INTCOMB_VGPIO2PMU_QCH, APBIF_INTCOMB_VGPIO2PMU_QCH, "GATE_APBIF_INTCOMB_VGPIO2PMU_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APBIF_PMU_ALIVE_QCH, APBIF_PMU_ALIVE_QCH, "GATE_APBIF_PMU_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APM_DMA_QCH_APB, APM_DMA_QCH_APB, "GATE_APM_DMA_QCH_APB", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_CHUB_RTC_QCH, CHUB_RTC_QCH, "GATE_CHUB_RTC_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_CLKMON_QCH, CLKMON_QCH, "GATE_CLKMON_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_DBGCORE_UART_QCH, DBGCORE_UART_QCH, "GATE_DBGCORE_UART_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_DTZPC_ALIVE_QCH, DTZPC_ALIVE_QCH, "GATE_DTZPC_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_GREBEINTEGRATION_QCH_GREBE, GREBEINTEGRATION_QCH_GREBE, "GATE_GREBEINTEGRATION_QCH_GREBE", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_GREBEINTEGRATION_QCH_DBG, GREBEINTEGRATION_QCH_DBG, "GATE_GREBEINTEGRATION_QCH_DBG", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_HW_SCANDUMP_CLKSTOP_CTRL_QCH, HW_SCANDUMP_CLKSTOP_CTRL_QCH, "GATE_HW_SCANDUMP_CLKSTOP_CTRL_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_INTMEM_QCH, INTMEM_QCH, "GATE_INTMEM_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_LH_AXI_SI_D_APM_QCH, LH_AXI_SI_D_APM_QCH, "GATE_LH_AXI_SI_D_APM_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_APM_AP_QCH, MAILBOX_APM_AP_QCH, "GATE_MAILBOX_APM_AP_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_APM_CHUB_QCH, MAILBOX_APM_CHUB_QCH, "GATE_MAILBOX_APM_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_APM_CP_QCH, MAILBOX_APM_CP_QCH, "GATE_MAILBOX_APM_CP_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_APM_GNSS_QCH, MAILBOX_APM_GNSS_QCH, "GATE_MAILBOX_APM_GNSS_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_APM_VTS_QCH, MAILBOX_APM_VTS_QCH, "GATE_MAILBOX_APM_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AP_CHUB_QCH, MAILBOX_AP_CHUB_QCH, "GATE_MAILBOX_AP_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AP_CP_QCH, MAILBOX_AP_CP_QCH, "GATE_MAILBOX_AP_CP_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AP_CP_S_QCH, MAILBOX_AP_CP_S_QCH, "GATE_MAILBOX_AP_CP_S_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AP_DBGCORE_QCH, MAILBOX_AP_DBGCORE_QCH, "GATE_MAILBOX_AP_DBGCORE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AP_GNSS_QCH, MAILBOX_AP_GNSS_QCH, "GATE_MAILBOX_AP_GNSS_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_CP_CHUB_QCH, MAILBOX_CP_CHUB_QCH, "GATE_MAILBOX_CP_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_CP_GNSS_QCH, MAILBOX_CP_GNSS_QCH, "GATE_MAILBOX_CP_GNSS_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_GNSS_CHUB_QCH, MAILBOX_GNSS_CHUB_QCH, "GATE_MAILBOX_GNSS_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_SHARED_SRAM_QCH, MAILBOX_SHARED_SRAM_QCH, "GATE_MAILBOX_SHARED_SRAM_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_VTS_CHUB_QCH, MAILBOX_VTS_CHUB_QCH, "GATE_MAILBOX_VTS_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MCT_ALIVE_QCH, MCT_ALIVE_QCH, "GATE_MCT_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_PMU_QCH_PMU, PMU_QCH_PMU, "GATE_PMU_QCH_PMU", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_PMU_QCH_PMLINK, PMU_QCH_PMLINK, "GATE_PMU_QCH_PMLINK", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_PMU_INTR_GEN_QCH, PMU_INTR_GEN_QCH, "GATE_PMU_INTR_GEN_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ROM_CRC32_HOST_QCH, ROM_CRC32_HOST_QCH, "GATE_ROM_CRC32_HOST_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_RSTNSYNC_CLK_ALIVE_GREBE_QCH, RSTNSYNC_CLK_ALIVE_GREBE_QCH, "GATE_RSTNSYNC_CLK_ALIVE_GREBE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_RTC_QCH, RTC_QCH, "GATE_RTC_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_MI_C_CHUB_QCH, SLH_AXI_MI_C_CHUB_QCH, "GATE_SLH_AXI_MI_C_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_MI_C_GNSS_QCH, SLH_AXI_MI_C_GNSS_QCH, "GATE_SLH_AXI_MI_C_GNSS_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_MI_C_MODEM_QCH, SLH_AXI_MI_C_MODEM_QCH, "GATE_SLH_AXI_MI_C_MODEM_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_MI_C_VTS_QCH, SLH_AXI_MI_C_VTS_QCH, "GATE_SLH_AXI_MI_C_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_MI_ID_DBGCORE_QCH, SLH_AXI_MI_ID_DBGCORE_QCH, "GATE_SLH_AXI_MI_ID_DBGCORE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_MI_P_APM_QCH, SLH_AXI_MI_P_APM_QCH, "GATE_SLH_AXI_MI_P_APM_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_SI_C_CMGP_QCH, SLH_AXI_SI_C_CMGP_QCH, "GATE_SLH_AXI_SI_C_CMGP_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_SI_IP_APM_QCH, SLH_AXI_SI_IP_APM_QCH, "GATE_SLH_AXI_SI_IP_APM_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_SI_LP_CHUB_QCH, SLH_AXI_SI_LP_CHUB_QCH, "GATE_SLH_AXI_SI_LP_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_SI_LP_VTS_QCH, SLH_AXI_SI_LP_VTS_QCH, "GATE_SLH_AXI_SI_LP_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_SI_PPU_ALIVE_CPUCL0_QCH, SLH_AXI_SI_PPU_ALIVE_CPUCL0_QCH, "GATE_SLH_AXI_SI_PPU_ALIVE_CPUCL0_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_SI_P_ALIVEDNC_QCH, SLH_AXI_SI_P_ALIVEDNC_QCH, "GATE_SLH_AXI_SI_P_ALIVEDNC_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SPC_ALIVE_QCH, SPC_ALIVE_QCH, "GATE_SPC_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SPMI_MASTER_PMIC_QCH_P, SPMI_MASTER_PMIC_QCH_P, "GATE_SPMI_MASTER_PMIC_QCH_P", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SPMI_MASTER_PMIC_QCH_S, SPMI_MASTER_PMIC_QCH_S, "GATE_SPMI_MASTER_PMIC_QCH_S", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SWEEPER_P_ALIVE_QCH, SWEEPER_P_ALIVE_QCH, "GATE_SWEEPER_P_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SYSREG_ALIVE_QCH, SYSREG_ALIVE_QCH, "GATE_SYSREG_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_TOP_RTC_QCH, TOP_RTC_QCH, "GATE_TOP_RTC_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_VGEN_LITE_ALIVE_QCH, VGEN_LITE_ALIVE_QCH, "GATE_VGEN_LITE_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_WDT_ALIVE_QCH, WDT_ALIVE_QCH, "GATE_WDT_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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};
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struct init_vclk s5e9925_aud_hwacg_vclks[] = {
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HWACG_VCLK(UMUX_CLKCMU_AUD_CPU, MUX_CLKCMU_AUD_CPU_USER, "UMUX_CLKCMU_AUD_CPU", NULL, 0, 0, NULL),
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HWACG_VCLK(UMUX_CLKCMU_AUD_NOC, MUX_CLKCMU_AUD_NOC_USER, "UMUX_CLKCMU_AUD_NOC", NULL, 0, 0, NULL),
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HWACG_VCLK(UMUX_CLK_AUD_RCO, MUX_CLK_AUD_RCO_USER, "UMUX_CLK_AUD_RCO", NULL, 0, 0, NULL),
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HWACG_VCLK(UMUX_CLKCMU_AUD_AUDIF0, MUX_CLKCMU_AUD_AUDIF0_USER, "UMUX_CLKCMU_AUD_AUDIF0", NULL, 0, 0, NULL),
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HWACG_VCLK(UMUX_CLKCMU_AUD_AUDIF1, MUX_CLKCMU_AUD_AUDIF1_USER, "UMUX_CLKCMU_AUD_AUDIF1", NULL, 0, 0, NULL),
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HWACG_VCLK(UMUX_CLKVTS_AUD_DMIC0, MUX_CLKVTS_AUD_DMIC0_USER, "UMUX_CLKVTS_AUD_DMIC0", NULL, 0, 0, NULL),
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HWACG_VCLK(UMUX_CLKVTS_AUD_DMIC1, MUX_CLKVTS_AUD_DMIC1_USER, "UMUX_CLKVTS_AUD_DMIC1", NULL, 0, 0, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_ACLK, ABOX_QCH_ACLK, "GATE_ABOX_QCH_ACLK", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK_DSIF, ABOX_QCH_BCLK_DSIF, "GATE_ABOX_QCH_BCLK_DSIF", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK0, ABOX_QCH_BCLK0, "GATE_ABOX_QCH_BCLK0", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK1, ABOX_QCH_BCLK1, "GATE_ABOX_QCH_BCLK1", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK2, ABOX_QCH_BCLK2, "GATE_ABOX_QCH_BCLK2", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK3, ABOX_QCH_BCLK3, "GATE_ABOX_QCH_BCLK3", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_CPU, ABOX_QCH_CPU, "GATE_ABOX_QCH_CPU", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK4, ABOX_QCH_BCLK4, "GATE_ABOX_QCH_BCLK4", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_CNT, ABOX_QCH_CNT, "GATE_ABOX_QCH_CNT", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK5, ABOX_QCH_BCLK5, "GATE_ABOX_QCH_BCLK5", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_CCLK_ASB, ABOX_QCH_CCLK_ASB, "GATE_ABOX_QCH_CCLK_ASB", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK6, ABOX_QCH_BCLK6, "GATE_ABOX_QCH_BCLK6", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_XCLK0, ABOX_QCH_XCLK0, "GATE_ABOX_QCH_XCLK0", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_PCMC_CLK, ABOX_QCH_PCMC_CLK, "GATE_ABOX_QCH_PCMC_CLK", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_C2A0, ABOX_QCH_C2A0, "GATE_ABOX_QCH_C2A0", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_C2A1, ABOX_QCH_C2A1, "GATE_ABOX_QCH_C2A1", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_XCLK1, ABOX_QCH_XCLK1, "GATE_ABOX_QCH_XCLK1", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_XCLK2, ABOX_QCH_XCLK2, "GATE_ABOX_QCH_XCLK2", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_CPU0, ABOX_QCH_CPU0, "GATE_ABOX_QCH_CPU0", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_CPU1, ABOX_QCH_CPU1, "GATE_ABOX_QCH_CPU1", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_CPU2, ABOX_QCH_CPU2, "GATE_ABOX_QCH_CPU2", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_NEON0, ABOX_QCH_NEON0, "GATE_ABOX_QCH_NEON0", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_NEON1, ABOX_QCH_NEON1, "GATE_ABOX_QCH_NEON1", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_NEON2, ABOX_QCH_NEON2, "GATE_ABOX_QCH_NEON2", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_L2, ABOX_QCH_L2, "GATE_ABOX_QCH_L2", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_AUD_CMU_AUD_QCH, AUD_CMU_AUD_QCH, "GATE_AUD_CMU_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_BAAW_D_AUDVTS_QCH, BAAW_D_AUDVTS_QCH, "GATE_BAAW_D_AUDVTS_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_DFTMUX_AUD_QCH, DFTMUX_AUD_QCH, "GATE_DFTMUX_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_DMIC_AUD0_QCH_PCLK, DMIC_AUD0_QCH_PCLK, "GATE_DMIC_AUD0_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_DMIC_AUD0_QCH_DMIC, DMIC_AUD0_QCH_DMIC, "GATE_DMIC_AUD0_QCH_DMIC", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_DMIC_AUD1_QCH_PCLK, DMIC_AUD1_QCH_PCLK, "GATE_DMIC_AUD1_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_DMIC_AUD1_QCH_DMIC, DMIC_AUD1_QCH_DMIC, "GATE_DMIC_AUD1_QCH_DMIC", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_DMIC_AUD2_QCH_PCLK, DMIC_AUD2_QCH_PCLK, "GATE_DMIC_AUD2_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_DMIC_AUD2_QCH_DMIC, DMIC_AUD2_QCH_DMIC, "GATE_DMIC_AUD2_QCH_DMIC", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_D_TZPC_AUD_QCH, D_TZPC_AUD_QCH, "GATE_D_TZPC_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_LH_QDI_SI_D_AUD_QCH, LH_QDI_SI_D_AUD_QCH, "GATE_LH_QDI_SI_D_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AUD0_QCH, MAILBOX_AUD0_QCH, "GATE_MAILBOX_AUD0_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AUD1_QCH, MAILBOX_AUD1_QCH, "GATE_MAILBOX_AUD1_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AUD2_QCH, MAILBOX_AUD2_QCH, "GATE_MAILBOX_AUD2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MAILBOX_AUD3_QCH, MAILBOX_AUD3_QCH, "GATE_MAILBOX_AUD3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_AUD_QCH, PPMU_AUD_QCH, "GATE_PPMU_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH, RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH, RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH, RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH, RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH, "GATE_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SERIAL_LIF_QCH_PCLK, SERIAL_LIF_QCH_PCLK, "GATE_SERIAL_LIF_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SERIAL_LIF_QCH_LIF, SERIAL_LIF_QCH_LIF, "GATE_SERIAL_LIF_QCH_LIF", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SERIAL_LIF_QCH_ACLK, SERIAL_LIF_QCH_ACLK, "GATE_SERIAL_LIF_QCH_ACLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_ASTL_SI_G_PPMU_AUD_QCH, SLH_ASTL_SI_G_PPMU_AUD_QCH, "GATE_SLH_ASTL_SI_G_PPMU_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_LD_HSI0AUD_QCH, SLH_AXI_MI_LD_HSI0AUD_QCH, "GATE_SLH_AXI_MI_LD_HSI0AUD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_AUD_QCH, SLH_AXI_MI_P_AUD_QCH, "GATE_SLH_AXI_MI_P_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_LD_AUDHSI0_QCH, SLH_AXI_SI_LD_AUDHSI0_QCH, "GATE_SLH_AXI_SI_LD_AUDHSI0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_LD_AUDVTS_QCH, SLH_AXI_SI_LD_AUDVTS_QCH, "GATE_SLH_AXI_SI_LD_AUDVTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SMMU_AUD_QCH_S1, SMMU_AUD_QCH_S1, "GATE_SMMU_AUD_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SMMU_AUD_QCH_S2, SMMU_AUD_QCH_S2, "GATE_SMMU_AUD_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_AUD_QCH, SYSREG_AUD_QCH, "GATE_SYSREG_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TREX_AUD_QCH, TREX_AUD_QCH, "GATE_TREX_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_AUD_QCH, VGEN_LITE_AUD_QCH, "GATE_VGEN_LITE_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_WDT_AUD_QCH, WDT_AUD_QCH, "GATE_WDT_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
struct init_vclk s5e9925_nocl1a_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_NOCL1A_NOC, MUX_CLKCMU_NOCL1A_NOC_USER, "UMUX_CLKCMU_NOCL1A_NOC", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_SYSREG_NOCL1A_QCH, SYSREG_NOCL1A_QCH, "GATE_SYSREG_NOCL1A_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TREX_D_NOCL1A_QCH, TREX_D_NOCL1A_QCH, "GATE_TREX_D_NOCL1A_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TREX_P_NOCL1A_QCH, TREX_P_NOCL1A_QCH, "GATE_TREX_P_NOCL1A_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_nocl1b_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_NOCL1B_NOC0, MUX_CLKCMU_NOCL1B_NOC0_USER, "UMUX_CLKCMU_NOCL1B_NOC0", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_SYSREG_NOCL1B_QCH, SYSREG_NOCL1B_QCH, "GATE_SYSREG_NOCL1B_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TREX_D_NOCL1B_QCH, TREX_D_NOCL1B_QCH, "GATE_TREX_D_NOCL1B_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TREX_P_NOCL1B_QCH, TREX_P_NOCL1B_QCH, "GATE_TREX_P_NOCL1B_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TREX_RB_NOCL1B_QCH, TREX_RB_NOCL1B_QCH, "GATE_TREX_RB_NOCL1B_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_NOCL1B_QCH, VGEN_LITE_NOCL1B_QCH, "GATE_VGEN_LITE_NOCL1B_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
};
|
|
|
|
struct init_vclk s5e9925_nocl1c_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_NOCL1B_NOC1, MUX_CLKCMU_NOCL1B_NOC1_USER, "UMUX_CLKCMU_NOCL1B_NOC1", NULL, 0, 0, NULL),
|
|
|
|
};
|
|
|
|
struct init_vclk s5e9925_cmgp_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(GATE_APBIF_GPIO_CMGP_QCH, APBIF_GPIO_CMGP_QCH, "GATE_APBIF_GPIO_CMGP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CMGP_CMU_CMGP_QCH, CMGP_CMU_CMGP_QCH, "GATE_CMGP_CMU_CMGP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CMGP_I2C_QCH, CMGP_I2C_QCH, "GATE_CMGP_I2C_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_CMGP_QCH, D_TZPC_CMGP_QCH, "GATE_D_TZPC_CMGP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I2C_CMGP2_QCH, I2C_CMGP2_QCH, "GATE_I2C_CMGP2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I2C_CMGP3_QCH, I2C_CMGP3_QCH, "GATE_I2C_CMGP3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I2C_CMGP4_QCH, I2C_CMGP4_QCH, "GATE_I2C_CMGP4_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I2C_CMGP5_QCH, I2C_CMGP5_QCH, "GATE_I2C_CMGP5_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I2C_CMGP6_QCH, I2C_CMGP6_QCH, "GATE_I2C_CMGP6_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I3C_CMGP_QCH_P, I3C_CMGP_QCH_P, "GATE_I3C_CMGP_QCH_P", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I3C_CMGP_QCH_S, I3C_CMGP_QCH_S, "GATE_I3C_CMGP_QCH_S", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_C_CMGP_QCH, SLH_AXI_MI_C_CMGP_QCH, "GATE_SLH_AXI_MI_C_CMGP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_LP_CMGPUFD_QCH, SLH_AXI_SI_LP_CMGPUFD_QCH, "GATE_SLH_AXI_SI_LP_CMGPUFD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SPI_I2C_CMGP0_QCH, SPI_I2C_CMGP0_QCH, "GATE_SPI_I2C_CMGP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SPI_I2C_CMGP1_QCH, SPI_I2C_CMGP1_QCH, "GATE_SPI_I2C_CMGP1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SPI_MULTI_SLV_Q_CTRL_CMGP_QCH, SPI_MULTI_SLV_Q_CTRL_CMGP_QCH, "GATE_SPI_MULTI_SLV_Q_CTRL_CMGP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CMGP_QCH, SYSREG_CMGP_QCH, "GATE_SYSREG_CMGP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CMGP2APM_QCH, SYSREG_CMGP2APM_QCH, "GATE_SYSREG_CMGP2APM_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CMGP2CHUB_QCH, SYSREG_CMGP2CHUB_QCH, "GATE_SYSREG_CMGP2CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CMGP2CP_QCH, SYSREG_CMGP2CP_QCH, "GATE_SYSREG_CMGP2CP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CMGP2GNSS_QCH, SYSREG_CMGP2GNSS_QCH, "GATE_SYSREG_CMGP2GNSS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CMGP2PMU_AP_QCH, SYSREG_CMGP2PMU_AP_QCH, "GATE_SYSREG_CMGP2PMU_AP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CMGP0_QCH, USI_CMGP0_QCH, "GATE_USI_CMGP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CMGP1_QCH, USI_CMGP1_QCH, "GATE_USI_CMGP1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CMGP2_QCH, USI_CMGP2_QCH, "GATE_USI_CMGP2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CMGP3_QCH, USI_CMGP3_QCH, "GATE_USI_CMGP3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CMGP4_QCH, USI_CMGP4_QCH, "GATE_USI_CMGP4_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CMGP5_QCH, USI_CMGP5_QCH, "GATE_USI_CMGP5_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CMGP6_QCH, USI_CMGP6_QCH, "GATE_USI_CMGP6_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
struct init_vclk s5e9925_top_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(GATE_CMU_TOP_CMUREF_QCH, CMU_TOP_CMUREF_QCH, "GATE_CMU_TOP_CMUREF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_CMU_QCH_CIS_CLK0, DFTMUX_CMU_QCH_CIS_CLK0, "GATE_DFTMUX_CMU_QCH_CIS_CLK0", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_CMU_QCH_CIS_CLK1, DFTMUX_CMU_QCH_CIS_CLK1, "GATE_DFTMUX_CMU_QCH_CIS_CLK1", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_CMU_QCH_CIS_CLK2, DFTMUX_CMU_QCH_CIS_CLK2, "GATE_DFTMUX_CMU_QCH_CIS_CLK2", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_CMU_QCH_CIS_CLK3, DFTMUX_CMU_QCH_CIS_CLK3, "GATE_DFTMUX_CMU_QCH_CIS_CLK3", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_CMU_QCH_CIS_CLK4, DFTMUX_CMU_QCH_CIS_CLK4, "GATE_DFTMUX_CMU_QCH_CIS_CLK4", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_CMU_QCH_CIS_CLK5, DFTMUX_CMU_QCH_CIS_CLK5, "GATE_DFTMUX_CMU_QCH_CIS_CLK5", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_CMU_QCH_CIS_CLK6, DFTMUX_CMU_QCH_CIS_CLK6, "GATE_DFTMUX_CMU_QCH_CIS_CLK6", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_CMU_QCH_CIS_CLK7, DFTMUX_CMU_QCH_CIS_CLK7, "GATE_DFTMUX_CMU_QCH_CIS_CLK7", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_nocl0_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_NOCL0_NOC, MUX_CLKCMU_NOCL0_NOC_USER, "UMUX_CLKCMU_NOCL0_NOC", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_CACHEAID_NOCL0_QCH, CACHEAID_NOCL0_QCH, "GATE_CACHEAID_NOCL0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CCI_QCH, CCI_QCH, "GATE_CCI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CCI_QCH_S, CCI_QCH_S, "GATE_CCI_QCH_S", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CMU_NOCL0_CMUREF_QCH, CMU_NOCL0_CMUREF_QCH, "GATE_CMU_NOCL0_CMUREF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_NOCL0_QCH, D_TZPC_NOCL0_QCH, "GATE_D_TZPC_NOCL0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_csis_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_CSIS_NOC, MUX_CLKCMU_CSIS_NOC_USER, "UMUX_CLKCMU_CSIS_NOC", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_CSIS_OIS_MCU, MUX_CLKCMU_CSIS_OIS_MCU_USER, "UMUX_CLKCMU_CSIS_OIS_MCU", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_CSIS_DCPHY, MUX_CLKCMU_CSIS_DCPHY_USER, "UMUX_CLKCMU_CSIS_DCPHY", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_CSIS_CMU_CSIS_QCH, CSIS_CMU_CSIS_QCH, "GATE_CSIS_CMU_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CSIS_PDP_QCH_VOTF0, CSIS_PDP_QCH_VOTF0, "GATE_CSIS_PDP_QCH_VOTF0", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CSIS_PDP_QCH_DMA, CSIS_PDP_QCH_DMA, "GATE_CSIS_PDP_QCH_DMA", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CSIS_PDP_QCH_MCB, CSIS_PDP_QCH_MCB, "GATE_CSIS_PDP_QCH_MCB", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CSIS_PDP_QCH_VOTF1, CSIS_PDP_QCH_VOTF1, "GATE_CSIS_PDP_QCH_VOTF1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CSIS_PDP_QCH_PDP, CSIS_PDP_QCH_PDP, "GATE_CSIS_PDP_QCH_PDP", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CSIS_PDP_QCH_PDP_VOTF, CSIS_PDP_QCH_PDP_VOTF, "GATE_CSIS_PDP_QCH_PDP_VOTF", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_CSIS_QCH, D_TZPC_CSIS_QCH, "GATE_D_TZPC_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_OTF0_CSISCSTAT_QCH, LH_AST_SI_OTF0_CSISCSTAT_QCH, "GATE_LH_AST_SI_OTF0_CSISCSTAT_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_OTF1_CSISCSTAT_QCH, LH_AST_SI_OTF1_CSISCSTAT_QCH, "GATE_LH_AST_SI_OTF1_CSISCSTAT_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_OTF2_CSISCSTAT_QCH, LH_AST_SI_OTF2_CSISCSTAT_QCH, "GATE_LH_AST_SI_OTF2_CSISCSTAT_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_OTF3_CSISCSTAT_QCH, LH_AST_SI_OTF3_CSISCSTAT_QCH, "GATE_LH_AST_SI_OTF3_CSISCSTAT_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D0_CSIS_QCH, LH_AXI_SI_D0_CSIS_QCH, "GATE_LH_AXI_SI_D0_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D1_CSIS_QCH, LH_AXI_SI_D1_CSIS_QCH, "GATE_LH_AXI_SI_D1_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D2_CSIS_QCH, LH_AXI_SI_D2_CSIS_QCH, "GATE_LH_AXI_SI_D2_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D3_CSIS_QCH, LH_AXI_SI_D3_CSIS_QCH, "GATE_LH_AXI_SI_D3_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D4_CSIS_QCH, LH_AXI_SI_D4_CSIS_QCH, "GATE_LH_AXI_SI_D4_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS0, MIPI_PHY_LINK_WRAP_QCH_CSIS0, "GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS0", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS1, MIPI_PHY_LINK_WRAP_QCH_CSIS1, "GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS2, MIPI_PHY_LINK_WRAP_QCH_CSIS2, "GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS3, MIPI_PHY_LINK_WRAP_QCH_CSIS3, "GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS3", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS4, MIPI_PHY_LINK_WRAP_QCH_CSIS4, "GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS4", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS5, MIPI_PHY_LINK_WRAP_QCH_CSIS5, "GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS5", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS6, MIPI_PHY_LINK_WRAP_QCH_CSIS6, "GATE_MIPI_PHY_LINK_WRAP_QCH_CSIS6", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_OIS_MCU_TOP_QCH, OIS_MCU_TOP_QCH, "GATE_OIS_MCU_TOP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
};
|
|
|
|
struct init_vclk s5e9925_dnc_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_DNC_NOC, MUX_CLKCMU_DNC_NOC_USER, "UMUX_CLKCMU_DNC_NOC", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_ADD_DNC_QCH, ADD_DNC_QCH, "GATE_ADD_DNC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ADM_DAP_DNC_QCH, ADM_DAP_DNC_QCH, "GATE_ADM_DAP_DNC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BAAW_DNCCHUB_QCH, BAAW_DNCCHUB_QCH, "GATE_BAAW_DNCCHUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BAAW_DNCVTS_QCH, BAAW_DNCVTS_QCH, "GATE_BAAW_DNCVTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_ADD_DNC_QCH, BUSIF_ADD_DNC_QCH, "GATE_BUSIF_ADD_DNC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_DDD_DNC_QCH, BUSIF_DDD_DNC_QCH, "GATE_BUSIF_DDD_DNC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_HPM_DNC_QCH, BUSIF_HPM_DNC_QCH, "GATE_BUSIF_HPM_DNC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DNC_CMU_DNC_QCH, DNC_CMU_DNC_QCH, "GATE_DNC_CMU_DNC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_DNC_QCH, D_TZPC_DNC_QCH, "GATE_D_TZPC_DNC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_DNC_QCH_PCLK, HTU_DNC_QCH_PCLK, "GATE_HTU_DNC_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_DNC_QCH_CLK, HTU_DNC_QCH_CLK, "GATE_HTU_DNC_QCH_CLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_DNC_QCH, IP_DNC_QCH, "GATE_IP_DNC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_DNC_QCH, SYSREG_DNC_QCH, "GATE_SYSREG_DNC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TREX_D_DNC_QCH, TREX_D_DNC_QCH, "GATE_TREX_D_DNC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_DNC_QCH, VGEN_DNC_QCH, "GATE_VGEN_DNC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_DNC_QCH, VGEN_LITE_DNC_QCH, "GATE_VGEN_LITE_DNC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
};
|
|
|
|
struct init_vclk s5e9925_dpub_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_DPUB_NOC, MUX_CLKCMU_DPUB_NOC_USER, "UMUX_CLKCMU_DPUB_NOC", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_DPUB_DSIM, MUX_CLKCMU_DPUB_DSIM_USER, "UMUX_CLKCMU_DPUB_DSIM", NULL, 0, 0, NULL),
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|
|
|
HWACG_VCLK(GATE_DPUB_QCH_DECON, DPUB_QCH_DECON, "GATE_DPUB_QCH_DECON", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPUB_QCH_DSIM0, DPUB_QCH_DSIM0, "GATE_DPUB_QCH_DSIM0", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPUB_QCH_DSIM1, DPUB_QCH_DSIM1, "GATE_DPUB_QCH_DSIM1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPUB_QCH_DSIM2, DPUB_QCH_DSIM2, "GATE_DPUB_QCH_DSIM2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPUB_CMU_DPUB_QCH, DPUB_CMU_DPUB_QCH, "GATE_DPUB_CMU_DPUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_DPUB_QCH, D_TZPC_DPUB_QCH, "GATE_D_TZPC_DPUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_DPUB_QCH, SYSREG_DPUB_QCH, "GATE_SYSREG_DPUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
};
|
|
|
|
struct init_vclk s5e9925_dpuf0_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_DPUF0_NOC, MUX_CLKCMU_DPUF0_NOC_USER, "UMUX_CLKCMU_DPUF0_NOC", NULL, 0, 0, NULL),
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|
|
|
HWACG_VCLK(GATE_DPUF0_QCH_DPUF, DPUF0_QCH_DPUF, "GATE_DPUF0_QCH_DPUF", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPUF0_QCH_VOTF, DPUF0_QCH_VOTF, "GATE_DPUF0_QCH_VOTF", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPUF0_CMU_DPUF0_QCH, DPUF0_CMU_DPUF0_QCH, "GATE_DPUF0_CMU_DPUF0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_DPUF0_QCH, D_TZPC_DPUF0_QCH, "GATE_D_TZPC_DPUF0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_DPUF0D0_QCH_S1, SYSMMU_DPUF0D0_QCH_S1, "GATE_SYSMMU_DPUF0D0_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_DPUF0D0_QCH_S2, SYSMMU_DPUF0D0_QCH_S2, "GATE_SYSMMU_DPUF0D0_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_DPUF0D1_QCH_S1, SYSMMU_DPUF0D1_QCH_S1, "GATE_SYSMMU_DPUF0D1_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_DPUF0D1_QCH_S2, SYSMMU_DPUF0D1_QCH_S2, "GATE_SYSMMU_DPUF0D1_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_DPUF0_QCH, SYSREG_DPUF0_QCH, "GATE_SYSREG_DPUF0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_dpuf1_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_DPUF1_NOC, MUX_CLKCMU_DPUF1_NOC_USER, "UMUX_CLKCMU_DPUF1_NOC", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_DPUF1_QCH_DPUF, DPUF1_QCH_DPUF, "GATE_DPUF1_QCH_DPUF", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPUF1_QCH_VOTF, DPUF1_QCH_VOTF, "GATE_DPUF1_QCH_VOTF", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPUF1_CMU_DPUF1_QCH, DPUF1_CMU_DPUF1_QCH, "GATE_DPUF1_CMU_DPUF1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_DPUF1_QCH, D_TZPC_DPUF1_QCH, "GATE_D_TZPC_DPUF1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D0_DPUF1DPUF0_QCH, LH_AXI_SI_D0_DPUF1DPUF0_QCH, "GATE_LH_AXI_SI_D0_DPUF1DPUF0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D1_DPUF1DPUF0_QCH, LH_AXI_SI_D1_DPUF1DPUF0_QCH, "GATE_LH_AXI_SI_D1_DPUF1DPUF0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_DPUF1D0_QCH, PPMU_DPUF1D0_QCH, "GATE_PPMU_DPUF1D0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_DPUF1D1_QCH, PPMU_DPUF1D1_QCH, "GATE_PPMU_DPUF1D1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SIU_DPUF1_QCH, SIU_DPUF1_QCH, "GATE_SIU_DPUF1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_ASTL_SI_G_PPMU_DPUF1_QCH, SLH_ASTL_SI_G_PPMU_DPUF1_QCH, "GATE_SLH_ASTL_SI_G_PPMU_DPUF1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_DPUF1_QCH, SLH_AXI_MI_P_DPUF1_QCH, "GATE_SLH_AXI_MI_P_DPUF1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_DPUF1D0_QCH_S1, SYSMMU_DPUF1D0_QCH_S1, "GATE_SYSMMU_DPUF1D0_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_DPUF1D0_QCH_S2, SYSMMU_DPUF1D0_QCH_S2, "GATE_SYSMMU_DPUF1D0_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_DPUF1D1_QCH_S1, SYSMMU_DPUF1D1_QCH_S1, "GATE_SYSMMU_DPUF1D1_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_DPUF1D1_QCH_S2, SYSMMU_DPUF1D1_QCH_S2, "GATE_SYSMMU_DPUF1D1_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_DPUF1_QCH, SYSREG_DPUF1_QCH, "GATE_SYSREG_DPUF1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
};
|
|
|
|
struct init_vclk s5e9925_dsu_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_DSU_SWITCH, MUX_CLKCMU_DSU_SWITCH_USER, "UMUX_CLKCMU_DSU_SWITCH", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_CMU_DSU_CMUREF_QCH, CMU_DSU_CMUREF_QCH, "GATE_CMU_DSU_CMUREF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DSU_CMU_DSU_QCH, DSU_CMU_DSU_QCH, "GATE_DSU_CMU_DSU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_DSU_QCH_PCLK, HTU_DSU_QCH_PCLK, "GATE_HTU_DSU_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
};
|
|
|
|
struct init_vclk s5e9925_g3d_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_G3D_NOCP, MUX_CLKCMU_G3D_NOCP_USER, "UMUX_CLKCMU_G3D_NOCP", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_G3D_SWITCH, MUX_CLKCMU_G3D_SWITCH_USER, "UMUX_CLKCMU_G3D_SWITCH", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_BG3D_PWRCTL_QCH, BG3D_PWRCTL_QCH, "GATE_BG3D_PWRCTL_QCH", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_HPMG3D_QCH, BUSIF_HPMG3D_QCH, "GATE_BUSIF_HPMG3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CFM_G3D_QCH, CFM_G3D_QCH, "GATE_CFM_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_G3D_QCH, D_TZPC_G3D_QCH, "GATE_D_TZPC_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_G3D_CMU_G3D_QCH, G3D_CMU_G3D_QCH, "GATE_G3D_CMU_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_G3D_QCH, SLH_AXI_MI_P_G3D_QCH, "GATE_SLH_AXI_MI_P_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_P_INT_G3D_QCH, SLH_AXI_SI_P_INT_G3D_QCH, "GATE_SLH_AXI_SI_P_INT_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_G3D_QCH, SYSREG_G3D_QCH, "GATE_SYSREG_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ADD_APBIF_G3D_QCH, ADD_APBIF_G3D_QCH, "GATE_ADD_APBIF_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ADD_G3D_QCH, ADD_G3D_QCH, "GATE_ADD_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ADM_DAP_G_G3D_QCH, ADM_DAP_G_G3D_QCH, "GATE_ADM_DAP_G_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ASB_G3D_QCH_LH_D0_G3D, ASB_G3D_QCH_LH_D0_G3D, "GATE_ASB_G3D_QCH_LH_D0_G3D", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ASB_G3D_QCH_LH_D1_G3D, ASB_G3D_QCH_LH_D1_G3D, "GATE_ASB_G3D_QCH_LH_D1_G3D", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ASB_G3D_QCH_LH_D2_G3D, ASB_G3D_QCH_LH_D2_G3D, "GATE_ASB_G3D_QCH_LH_D2_G3D", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ASB_G3D_QCH_LH_D3_G3D, ASB_G3D_QCH_LH_D3_G3D, "GATE_ASB_G3D_QCH_LH_D3_G3D", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ASB_G3D_QCH_S_LH_P_G3D, ASB_G3D_QCH_S_LH_P_G3D, "GATE_ASB_G3D_QCH_S_LH_P_G3D", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_DDC_G3D_QCH, BUSIF_DDC_G3D_QCH, "GATE_BUSIF_DDC_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_STR_G3D_QCH, BUSIF_STR_G3D_QCH, "GATE_BUSIF_STR_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_STR_G3D_QCH_CORE, BUSIF_STR_G3D_QCH_CORE, "GATE_BUSIF_STR_G3D_QCH_CORE", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_G3DCORE_CMU_G3DCORE_QCH, G3DCORE_CMU_G3DCORE_QCH, "GATE_G3DCORE_CMU_G3DCORE_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPU_QCH, GPU_QCH, "GATE_GPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_G3D_QCH_PCLK, HTU_G3D_QCH_PCLK, "GATE_HTU_G3D_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_G3D_QCH_CLK, HTU_G3D_QCH_CLK, "GATE_HTU_G3D_QCH_CLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_ATB_SI_T_DDCG3D_QCH, LH_ATB_SI_T_DDCG3D_QCH, "GATE_LH_ATB_SI_T_DDCG3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_G3DCORE_NOCP_QCH, RSTNSYNC_CLK_G3DCORE_NOCP_QCH, "GATE_RSTNSYNC_CLK_G3DCORE_NOCP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_STR_G3D_QCH, STR_G3D_QCH, "GATE_STR_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_U_DDD_CTRL_CORE__G3D_QCH, U_DDD_CTRL_CORE__G3D_QCH, "GATE_U_DDD_CTRL_CORE__G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_hsi0_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_HSI0_DPOSC, MUX_CLKCMU_HSI0_DPOSC_USER, "UMUX_CLKCMU_HSI0_DPOSC", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_HSI0_NOC, MUX_CLKCMU_HSI0_NOC_USER, "UMUX_CLKCMU_HSI0_NOC", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_HSI0_USB32DRD, MUX_CLKCMU_HSI0_USB32DRD_USER, "UMUX_CLKCMU_HSI0_USB32DRD", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_HSI0_DPGTC, MUX_CLKCMU_HSI0_DPGTC_USER, "UMUX_CLKCMU_HSI0_DPGTC", NULL, 0, 0, NULL),
|
|
// HWACG_VCLK(UMUX_CLKAUD_HSI0_NOC, MUX_CLKAUD_HSI0_NOC_USER, "UMUX_CLKAUD_HSI0_NOC", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(MOUT_CLK_HSI0_USB32DRD, MUX_CLK_HSI0_USB32DRD, "MOUT_CLK_HSI0_USB32DRD", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_HSI0_QCH, D_TZPC_HSI0_QCH, "GATE_D_TZPC_HSI0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HSI0_CMU_HSI0_QCH, HSI0_CMU_HSI0_QCH, "GATE_HSI0_CMU_HSI0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_HSI0_BUS1_QCH, PPMU_HSI0_BUS1_QCH, "GATE_PPMU_HSI0_BUS1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_ACEL_SI_D_HSI0_QCH, SLH_ACEL_SI_D_HSI0_QCH, "GATE_SLH_ACEL_SI_D_HSI0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_ASTL_SI_G_PPMU_HSI0_QCH, SLH_ASTL_SI_G_PPMU_HSI0_QCH, "GATE_SLH_ASTL_SI_G_PPMU_HSI0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_LD_AUDHSI0_QCH, SLH_AXI_MI_LD_AUDHSI0_QCH, "GATE_SLH_AXI_MI_LD_AUDHSI0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_HSI0_QCH, SLH_AXI_MI_P_HSI0_QCH, "GATE_SLH_AXI_MI_P_HSI0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_LD_HSI0AUD_QCH, SLH_AXI_SI_LD_HSI0AUD_QCH, "GATE_SLH_AXI_SI_LD_HSI0AUD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SPC_HSI0_QCH, SPC_HSI0_QCH, "GATE_SPC_HSI0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_HSI0_QCH, SYSMMU_D_HSI0_QCH, "GATE_SYSMMU_D_HSI0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_HSI0_QCH, SYSREG_HSI0_QCH, "GATE_SYSREG_HSI0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USB32DRD_QCH_S_SUBCTRL, USB32DRD_QCH_S_SUBCTRL, "GATE_USB32DRD_QCH_S_SUBCTRL", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USB32DRD_QCH_S_LINK, USB32DRD_QCH_S_LINK, "GATE_USB32DRD_QCH_S_LINK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USB32DRD_QCH_S_CTRL, USB32DRD_QCH_S_CTRL, "GATE_USB32DRD_QCH_S_CTRL", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USB32DRD_QCH_S_TCA, USB32DRD_QCH_S_TCA, "GATE_USB32DRD_QCH_S_TCA", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USB32DRD_QCH_S_EUSBCTL, USB32DRD_QCH_S_EUSBCTL, "GATE_USB32DRD_QCH_S_EUSBCTL", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USB32DRD_QCH_S_EUSBPHY, USB32DRD_QCH_S_EUSBPHY, "GATE_USB32DRD_QCH_S_EUSBPHY", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_HSI0_QCH, VGEN_LITE_HSI0_QCH, "GATE_VGEN_LITE_HSI0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
};
|
|
|
|
struct init_vclk s5e9925_hsi1_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_HSI1_NOC, MUX_CLKCMU_HSI1_NOC_USER, "UMUX_CLKCMU_HSI1_NOC", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_HSI1_PCIE, MUX_CLKCMU_HSI1_PCIE_USER, "UMUX_CLKCMU_HSI1_PCIE", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_HSI1_MMC_CARD, MUX_CLKCMU_HSI1_MMC_CARD_USER, "UMUX_CLKCMU_HSI1_MMC_CARD", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_HSI1_UFS_EMBD, MUX_CLKCMU_HSI1_UFS_EMBD_USER, "UMUX_CLKCMU_HSI1_UFS_EMBD", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_HSI1_QCH, D_TZPC_HSI1_QCH, "GATE_D_TZPC_HSI1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPIO_HSI1_QCH, GPIO_HSI1_QCH, "GATE_GPIO_HSI1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPIO_HSI1UFS_QCH, GPIO_HSI1UFS_QCH, "GATE_GPIO_HSI1UFS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HSI1_CMU_HSI1_QCH, HSI1_CMU_HSI1_QCH, "GATE_HSI1_CMU_HSI1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_ACEL_SI_D_HSI1_QCH, LH_ACEL_SI_D_HSI1_QCH, "GATE_LH_ACEL_SI_D_HSI1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_HSI1_QCH, PPMU_HSI1_QCH, "GATE_PPMU_HSI1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_ASTL_SI_G_PPMU_HSI1_QCH, SLH_ASTL_SI_G_PPMU_HSI1_QCH, "GATE_SLH_ASTL_SI_G_PPMU_HSI1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_HSI1_QCH, SLH_AXI_MI_P_HSI1_QCH, "GATE_SLH_AXI_MI_P_HSI1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SPC_HSI1_QCH, SPC_HSI1_QCH, "GATE_SPC_HSI1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_HSI1_QCH_S1, SYSMMU_HSI1_QCH_S1, "GATE_SYSMMU_HSI1_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_HSI1_QCH_S2, SYSMMU_HSI1_QCH_S2, "GATE_SYSMMU_HSI1_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_HSI1_QCH, SYSREG_HSI1_QCH, "GATE_SYSREG_HSI1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_UFS_EMBD_QCH, UFS_EMBD_QCH, "GATE_UFS_EMBD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_UFS_EMBD_QCH_FMP, UFS_EMBD_QCH_FMP, "GATE_UFS_EMBD_QCH_FMP", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_HSI1_QCH, VGEN_LITE_HSI1_QCH, "GATE_VGEN_LITE_HSI1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PCIE_GEN2_QCH_REF, PCIE_GEN2_QCH_REF, "GATE_PCIE_GEN2_QCH_REF", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
HWACG_VCLK(GATE_PCIE_GEN3_QCH_REF, PCIE_GEN3_QCH_REF, "GATE_PCIE_GEN3_QCH_REF", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
};
|
|
|
|
|
|
struct init_vclk s5e9925_lme_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_LME_NOC, MUX_CLKCMU_LME_NOC_USER, "UMUX_CLKCMU_LME_NOC", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_LME_FRC, MUX_CLKCMU_LME_FRC_USER, "UMUX_CLKCMU_LME_FRC", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_LME_QCH, D_TZPC_LME_QCH, "GATE_D_TZPC_LME_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_FRC_MC_QCH, FRC_MC_QCH, "GATE_FRC_MC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D_LME_QCH, LH_AXI_SI_D_LME_QCH, "GATE_LH_AXI_SI_D_LME_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LME_QCH_0, LME_QCH_0, "GATE_LME_QCH_0", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LME_QCH_1, LME_QCH_1, "GATE_LME_QCH_1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LME_CMU_LME_QCH, LME_CMU_LME_QCH, "GATE_LME_CMU_LME_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D_LME_QCH, PPMU_D_LME_QCH, "GATE_PPMU_D_LME_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D0_LME_QCH, QE_D0_LME_QCH, "GATE_QE_D0_LME_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_D1_LME_QCH, QE_D1_LME_QCH, "GATE_QE_D1_LME_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_ASTL_SI_G_PPMU_LME_QCH, SLH_ASTL_SI_G_PPMU_LME_QCH, "GATE_SLH_ASTL_SI_G_PPMU_LME_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_LME_QCH, SLH_AXI_MI_P_LME_QCH, "GATE_SLH_AXI_MI_P_LME_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_LME_QCH_S1, SYSMMU_D_LME_QCH_S1, "GATE_SYSMMU_D_LME_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_LME_QCH_S2, SYSMMU_D_LME_QCH_S2, "GATE_SYSMMU_D_LME_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_LME_QCH, SYSREG_LME_QCH, "GATE_SYSREG_LME_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_D_LME_QCH, VGEN_LITE_D_LME_QCH, "GATE_VGEN_LITE_D_LME_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_m2m_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_M2M_NOC, MUX_CLKCMU_M2M_NOC_USER, "UMUX_CLKCMU_M2M_NOC", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_M2M_QCH, D_TZPC_M2M_QCH, "GATE_D_TZPC_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_ACEL_SI_D_M2M_QCH, LH_ACEL_SI_D_M2M_QCH, "GATE_LH_ACEL_SI_D_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_M2M_QCH, M2M_QCH, "GATE_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_M2M_QCH_VOTF, M2M_QCH_VOTF, "GATE_M2M_QCH_VOTF", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_M2M_CMU_M2M_QCH, M2M_CMU_M2M_QCH, "GATE_M2M_CMU_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D_M2M_QCH, PPMU_D_M2M_QCH, "GATE_PPMU_D_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_ASTC_QCH, QE_ASTC_QCH, "GATE_QE_ASTC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_JPEG0_QCH, QE_JPEG0_QCH, "GATE_QE_JPEG0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_JPEG1_QCH, QE_JPEG1_QCH, "GATE_QE_JPEG1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_JSQZ_QCH, QE_JSQZ_QCH, "GATE_QE_JSQZ_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_M2M_QCH, QE_M2M_QCH, "GATE_QE_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_ASTL_SI_G_PPMU_M2M_QCH, SLH_ASTL_SI_G_PPMU_M2M_QCH, "GATE_SLH_ASTL_SI_G_PPMU_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_M2M_QCH, SLH_AXI_MI_P_M2M_QCH, "GATE_SLH_AXI_MI_P_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_M2M_PM_QCH_S2, SYSMMU_D_M2M_PM_QCH_S2, "GATE_SYSMMU_D_M2M_PM_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_M2M_PM_QCH_S1, SYSMMU_D_M2M_PM_QCH_S1, "GATE_SYSMMU_D_M2M_PM_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_M2M_QCH, SYSREG_M2M_QCH, "GATE_SYSREG_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_M2M_QCH, VGEN_LITE_M2M_QCH, "GATE_VGEN_LITE_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_mcfp_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_MCFP_NOC, MUX_CLKCMU_MCFP_NOC_USER, "UMUX_CLKCMU_MCFP_NOC", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_MCFP_QCH, D_TZPC_MCFP_QCH, "GATE_D_TZPC_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_OTF_RGBPMCFP_QCH, LH_AST_MI_OTF_RGBPMCFP_QCH, "GATE_LH_AST_MI_OTF_RGBPMCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_OTF_YUVPMCFP_QCH, LH_AST_MI_OTF_YUVPMCFP_QCH, "GATE_LH_AST_MI_OTF_YUVPMCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_OTF0_MCFPYUVP_QCH, LH_AST_SI_OTF0_MCFPYUVP_QCH, "GATE_LH_AST_SI_OTF0_MCFPYUVP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D0_MCFP_QCH, LH_AXI_SI_D0_MCFP_QCH, "GATE_LH_AXI_SI_D0_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D1_MCFP_QCH, LH_AXI_SI_D1_MCFP_QCH, "GATE_LH_AXI_SI_D1_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D2_MCFP_QCH, LH_AXI_SI_D2_MCFP_QCH, "GATE_LH_AXI_SI_D2_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MCFP_QCH, MCFP_QCH, "GATE_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MCFP_CMU_MCFP_QCH, MCFP_CMU_MCFP_QCH, "GATE_MCFP_CMU_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D0_MCFP_QCH, PPMU_D0_MCFP_QCH, "GATE_PPMU_D0_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D1_MCFP_QCH, PPMU_D1_MCFP_QCH, "GATE_PPMU_D1_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D2_MCFP_QCH, PPMU_D2_MCFP_QCH, "GATE_PPMU_D2_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D3_MCFP_QCH, PPMU_D3_MCFP_QCH, "GATE_PPMU_D3_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D4_MCFP_QCH, PPMU_D4_MCFP_QCH, "GATE_PPMU_D4_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D5_MCFP_QCH, PPMU_D5_MCFP_QCH, "GATE_PPMU_D5_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MCFP_NOCD_MCFP_SW_RESET_QCH, RSTNSYNC_CLK_MCFP_NOCD_MCFP_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MCFP_NOCD_MCFP_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SIU_G_PPMU_MCFP_QCH, SIU_G_PPMU_MCFP_QCH, "GATE_SIU_G_PPMU_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_ASTL_SI_G_PPMU_MCFP_QCH, SLH_ASTL_SI_G_PPMU_MCFP_QCH, "GATE_SLH_ASTL_SI_G_PPMU_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_MCFP_QCH, SLH_AXI_MI_P_MCFP_QCH, "GATE_SLH_AXI_MI_P_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_D3_MCFP_QCH, SLH_AXI_SI_D3_MCFP_QCH, "GATE_SLH_AXI_SI_D3_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_D4_MCFP_QCH, SLH_AXI_SI_D4_MCFP_QCH, "GATE_SLH_AXI_SI_D4_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_D5_MCFP_QCH, SLH_AXI_SI_D5_MCFP_QCH, "GATE_SLH_AXI_SI_D5_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_MCFP_QCH_S1, SYSMMU_D0_MCFP_QCH_S1, "GATE_SYSMMU_D0_MCFP_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_MCFP_QCH_S2, SYSMMU_D0_MCFP_QCH_S2, "GATE_SYSMMU_D0_MCFP_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_MCFP_QCH_S1, SYSMMU_D1_MCFP_QCH_S1, "GATE_SYSMMU_D1_MCFP_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_MCFP_QCH_S2, SYSMMU_D1_MCFP_QCH_S2, "GATE_SYSMMU_D1_MCFP_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D2_MCFP_QCH_S1, SYSMMU_D2_MCFP_QCH_S1, "GATE_SYSMMU_D2_MCFP_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D2_MCFP_QCH_S2, SYSMMU_D2_MCFP_QCH_S2, "GATE_SYSMMU_D2_MCFP_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D3_MCFP_QCH_S1, SYSMMU_D3_MCFP_QCH_S1, "GATE_SYSMMU_D3_MCFP_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D3_MCFP_QCH_S2, SYSMMU_D3_MCFP_QCH_S2, "GATE_SYSMMU_D3_MCFP_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D4_MCFP_QCH_S1, SYSMMU_D4_MCFP_QCH_S1, "GATE_SYSMMU_D4_MCFP_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D4_MCFP_QCH_S2, SYSMMU_D4_MCFP_QCH_S2, "GATE_SYSMMU_D4_MCFP_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D5_MCFP_QCH_S1, SYSMMU_D5_MCFP_QCH_S1, "GATE_SYSMMU_D5_MCFP_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D5_MCFP_QCH_S2, SYSMMU_D5_MCFP_QCH_S2, "GATE_SYSMMU_D5_MCFP_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_MCFP_QCH, SYSREG_MCFP_QCH, "GATE_SYSREG_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_D0_MCFP_QCH, VGEN_LITE_D0_MCFP_QCH, "GATE_VGEN_LITE_D0_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_D1_MCFP_QCH, VGEN_LITE_D1_MCFP_QCH, "GATE_VGEN_LITE_D1_MCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
};
|
|
|
|
struct init_vclk s5e9925_mcsc_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_MCSC_NOC, MUX_CLKCMU_MCSC_NOC_USER, "UMUX_CLKCMU_MCSC_NOC", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_MCSC_GDC, MUX_CLKCMU_MCSC_GDC_USER, "UMUX_CLKCMU_MCSC_GDC", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_MCSC_QCH, D_TZPC_MCSC_QCH, "GATE_D_TZPC_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_ACEL_SI_D0_MCSC_QCH, LH_ACEL_SI_D0_MCSC_QCH, "GATE_LH_ACEL_SI_D0_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_LH_AST_MI_OTF_DRCPMCSC_QCH, LH_AST_MI_OTF_DRCPMCSC_QCH, "GATE_LH_AST_MI_OTF_DRCPMCSC_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_LH_AXI_SI_D1_MCSC_QCH, LH_AXI_SI_D1_MCSC_QCH, "GATE_LH_AXI_SI_D1_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_LH_AXI_SI_D2_MCSC_QCH, LH_AXI_SI_D2_MCSC_QCH, "GATE_LH_AXI_SI_D2_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_MCSC_QCH, MCSC_QCH, "GATE_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MCSC_QCH_C2R, MCSC_QCH_C2R, "GATE_MCSC_QCH_C2R", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MCSC_QCH_C2W, MCSC_QCH_C2W, "GATE_MCSC_QCH_C2W", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MCSC_CMU_MCSC_QCH, MCSC_CMU_MCSC_QCH, "GATE_MCSC_CMU_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D0_MCSC_QCH, PPMU_D0_MCSC_QCH, "GATE_PPMU_D0_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D1_MCSC_QCH, PPMU_D1_MCSC_QCH, "GATE_PPMU_D1_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D2_MCSC_QCH, PPMU_D2_MCSC_QCH, "GATE_PPMU_D2_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SIU_G_PPMU_MCSC_QCH, SIU_G_PPMU_MCSC_QCH, "GATE_SIU_G_PPMU_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_ASTL_MI_IG_PPMU_D0_MCSC_QCH, SLH_ASTL_MI_IG_PPMU_D0_MCSC_QCH, "GATE_SLH_ASTL_MI_IG_PPMU_D0_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_ASTL_SI_G_PPMU_MCSC_QCH, SLH_ASTL_SI_G_PPMU_MCSC_QCH, "GATE_SLH_ASTL_SI_G_PPMU_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_ASTL_SI_IG_PPMU_D0_MCSC_QCH, SLH_ASTL_SI_IG_PPMU_D0_MCSC_QCH, "GATE_SLH_ASTL_SI_IG_PPMU_D0_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_MI_P_MCSC_QCH, SLH_AXI_MI_P_MCSC_QCH, "GATE_SLH_AXI_MI_P_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SYSMMU_D0_MCSC_QCH_S1, SYSMMU_D0_MCSC_QCH_S1, "GATE_SYSMMU_D0_MCSC_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_MCSC_QCH_S2, SYSMMU_D0_MCSC_QCH_S2, "GATE_SYSMMU_D0_MCSC_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_MCSC_QCH_S1, SYSMMU_D1_MCSC_QCH_S1, "GATE_SYSMMU_D1_MCSC_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_MCSC_QCH_S2, SYSMMU_D1_MCSC_QCH_S2, "GATE_SYSMMU_D1_MCSC_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D2_MCSC_QCH_S1, SYSMMU_D2_MCSC_QCH_S1, "GATE_SYSMMU_D2_MCSC_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D2_MCSC_QCH_S2, SYSMMU_D2_MCSC_QCH_S2, "GATE_SYSMMU_D2_MCSC_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_MCSC_QCH, SYSREG_MCSC_QCH, "GATE_SYSREG_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_D0_MCSC_QCH, VGEN_LITE_D0_MCSC_QCH, "GATE_VGEN_LITE_D0_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_D1_MCSC_QCH, VGEN_LITE_D1_MCSC_QCH, "GATE_VGEN_LITE_D1_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_mfc0_hwacg_vclks[] = {
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|
|
|
HWACG_VCLK(UMUX_CLKCMU_MFC0_MFC0, MUX_CLKCMU_MFC0_MFC0_USER, "UMUX_CLKCMU_MFC0_MFC0", NULL, 0, 0, NULL),
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|
HWACG_VCLK(UMUX_CLKCMU_MFC0_WFD, MUX_CLKCMU_MFC0_WFD_USER, "UMUX_CLKCMU_MFC0_WFD", NULL, 0, 0, NULL),
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|
|
|
HWACG_VCLK(GATE_D_TZPC_MFC0_QCH, D_TZPC_MFC0_QCH, "GATE_D_TZPC_MFC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MFC0_QCH, MFC0_QCH, "GATE_MFC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MFC0_QCH_VOTF, MFC0_QCH_VOTF, "GATE_MFC0_QCH_VOTF", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MFC0_CMU_MFC0_QCH, MFC0_CMU_MFC0_QCH, "GATE_MFC0_CMU_MFC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_MFC0D0_QCH, PPMU_MFC0D0_QCH, "GATE_PPMU_MFC0D0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_MFC0D1_QCH, PPMU_MFC0D1_QCH, "GATE_PPMU_MFC0D1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_WFD_QCH, PPMU_WFD_QCH, "GATE_PPMU_WFD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SIU_G_PPMU_MFC0_QCH, SIU_G_PPMU_MFC0_QCH, "GATE_SIU_G_PPMU_MFC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_ASTL_SI_G_PPMU_MFC0_QCH, SLH_ASTL_SI_G_PPMU_MFC0_QCH, "GATE_SLH_ASTL_SI_G_PPMU_MFC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_MFC0_QCH, SLH_AXI_MI_P_MFC0_QCH, "GATE_SLH_AXI_MI_P_MFC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_MFC0D0_QCH_S1, SYSMMU_MFC0D0_QCH_S1, "GATE_SYSMMU_MFC0D0_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_MFC0D0_QCH_S2, SYSMMU_MFC0D0_QCH_S2, "GATE_SYSMMU_MFC0D0_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_MFC0D1_QCH_S1, SYSMMU_MFC0D1_QCH_S1, "GATE_SYSMMU_MFC0D1_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_MFC0D1_QCH_S2, SYSMMU_MFC0D1_QCH_S2, "GATE_SYSMMU_MFC0D1_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_MFC0_QCH, SYSREG_MFC0_QCH, "GATE_SYSREG_MFC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_MFC0_QCH, VGEN_LITE_MFC0_QCH, "GATE_VGEN_LITE_MFC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_mfc1_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_MFC1_MFC1, MUX_CLKCMU_MFC1_MFC1_USER, "UMUX_CLKCMU_MFC1_MFC1", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_ADM_APB_MFC0MFC1_QCH, ADM_APB_MFC0MFC1_QCH, "GATE_ADM_APB_MFC0MFC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_MFC1_QCH, D_TZPC_MFC1_QCH, "GATE_D_TZPC_MFC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MFC1_QCH, MFC1_QCH, "GATE_MFC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MFC1_CMU_MFC1_QCH, MFC1_CMU_MFC1_QCH, "GATE_MFC1_CMU_MFC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_MFC1D0_QCH, PPMU_MFC1D0_QCH, "GATE_PPMU_MFC1D0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_MFC1D1_QCH, PPMU_MFC1D1_QCH, "GATE_PPMU_MFC1D1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH, RSTNSYNC_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH, RSTNSYNC_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH, RSTNSYNC_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH, RSTNSYNC_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH, RSTNSYNC_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH, RSTNSYNC_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH, RSTNSYNC_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH, RSTNSYNC_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH, RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SIU_G_PPMU_MFC1_QCH, SIU_G_PPMU_MFC1_QCH, "GATE_SIU_G_PPMU_MFC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_ASTL_SI_G_PPMU_MFC1_QCH, SLH_ASTL_SI_G_PPMU_MFC1_QCH, "GATE_SLH_ASTL_SI_G_PPMU_MFC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_MFC1_QCH, SLH_AXI_MI_P_MFC1_QCH, "GATE_SLH_AXI_MI_P_MFC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_MFC1D0_QCH_S1, SYSMMU_MFC1D0_QCH_S1, "GATE_SYSMMU_MFC1D0_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_MFC1D0_QCH_S2, SYSMMU_MFC1D0_QCH_S2, "GATE_SYSMMU_MFC1D0_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_MFC1D1_QCH_S1, SYSMMU_MFC1D1_QCH_S1, "GATE_SYSMMU_MFC1D1_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_MFC1D1_QCH_S2, SYSMMU_MFC1D1_QCH_S2, "GATE_SYSMMU_MFC1D1_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_MFC1_QCH, SYSREG_MFC1_QCH, "GATE_SYSREG_MFC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_MFC1_QCH, VGEN_MFC1_QCH, "GATE_VGEN_MFC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_mif_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_MIF_NOCP, MUX_CLKCMU_MIF_NOCP_USER, "UMUX_CLKCMU_MIF_NOCP", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_BUSIF_DDD_MIF_QCH, BUSIF_DDD_MIF_QCH, "GATE_BUSIF_DDD_MIF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CMU_MIF_CMUREF_QCH, CMU_MIF_CMUREF_QCH, "GATE_CMU_MIF_CMUREF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMC_QCH, DMC_QCH, "GATE_DMC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_MIF_QCH, D_TZPC_MIF_QCH, "GATE_D_TZPC_MIF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_G_DMC_QCH, LH_AST_SI_G_DMC_QCH, "GATE_LH_AST_SI_G_DMC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIF_CMU_MIF_QCH, MIF_CMU_MIF_QCH, "GATE_MIF_CMU_MIF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QCH_ADAPTER_PPC_DEBUG_QCH, QCH_ADAPTER_PPC_DEBUG_QCH, "GATE_QCH_ADAPTER_PPC_DEBUG_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_ASTL_SI_G_PPMU_MIF_QCH, SLH_ASTL_SI_G_PPMU_MIF_QCH, "GATE_SLH_ASTL_SI_G_PPMU_MIF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_MIF_QCH, SLH_AXI_MI_P_MIF_QCH, "GATE_SLH_AXI_MI_P_MIF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SPC_MIF_QCH, SPC_MIF_QCH, "GATE_SPC_MIF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_MIF_QCH, SYSREG_MIF_QCH, "GATE_SYSREG_MIF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_PRIVATE_MIF_QCH, SYSREG_PRIVATE_MIF_QCH, "GATE_SYSREG_PRIVATE_MIF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(MUX_MIF_DDRPHY2X, CLKMUX_MIF_DDRPHY2X, "MUX_MIF_DDRPHY2X", NULL, 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_gnpu_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLKCMU_GNPU_NOC, MUX_CLKCMU_GNPU_NOC_USER, "UMUX_CLKCMU_GNPU_NOC", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_GNPUP_NOC, MUX_CLKCMU_GNPUP_NOC_USER, "UMUX_CLKCMU_GNPUP_NOC", NULL, 0, 0, NULL),
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|
|
|
HWACG_VCLK(GATE_D_TZPC_GNPU_QCH, D_TZPC_GNPU_QCH, "GATE_D_TZPC_GNPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GNPU_CMU_GNPU_QCH, GNPU_CMU_GNPU_QCH, "GATE_GNPU_CMU_GNPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPUCORE_QCH_CORE, IP_NPUCORE_QCH_CORE, "GATE_IP_NPUCORE_QCH_CORE", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPUCORE_QCH_SRAM, IP_NPUCORE_QCH_SRAM, "GATE_IP_NPUCORE_QCH_SRAM", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPUP_BU0_QCH, LH_AST_MI_LD_GNPUP_BU0_QCH, "GATE_LH_AST_MI_LD_GNPUP_BU0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPUP_BU1_QCH, LH_AST_MI_LD_GNPUP_BU1_QCH, "GATE_LH_AST_MI_LD_GNPUP_BU1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPUP_BU2_QCH, LH_AST_MI_LD_GNPUP_BU2_QCH, "GATE_LH_AST_MI_LD_GNPUP_BU2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPUP_BU3_QCH, LH_AST_MI_LD_GNPUP_BU3_QCH, "GATE_LH_AST_MI_LD_GNPUP_BU3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPUP_CU_WCH_QCH, LH_AST_MI_LD_GNPUP_CU_WCH_QCH, "GATE_LH_AST_MI_LD_GNPUP_CU_WCH_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPUP_NPUC_DONE_QCH, LH_AST_MI_LD_GNPUP_NPUC_DONE_QCH, "GATE_LH_AST_MI_LD_GNPUP_NPUC_DONE_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPUP_RDREQ_QCH, LH_AST_MI_LD_GNPUP_RDREQ_QCH, "GATE_LH_AST_MI_LD_GNPUP_RDREQ_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU0_QCH, LH_AST_SI_LD_GNPU_AU0_QCH, "GATE_LH_AST_SI_LD_GNPU_AU0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU1_QCH, LH_AST_SI_LD_GNPU_AU1_QCH, "GATE_LH_AST_SI_LD_GNPU_AU1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU10_QCH, LH_AST_SI_LD_GNPU_AU10_QCH, "GATE_LH_AST_SI_LD_GNPU_AU10_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU11_QCH, LH_AST_SI_LD_GNPU_AU11_QCH, "GATE_LH_AST_SI_LD_GNPU_AU11_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU12_QCH, LH_AST_SI_LD_GNPU_AU12_QCH, "GATE_LH_AST_SI_LD_GNPU_AU12_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU13_QCH, LH_AST_SI_LD_GNPU_AU13_QCH, "GATE_LH_AST_SI_LD_GNPU_AU13_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU14_QCH, LH_AST_SI_LD_GNPU_AU14_QCH, "GATE_LH_AST_SI_LD_GNPU_AU14_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU15_QCH, LH_AST_SI_LD_GNPU_AU15_QCH, "GATE_LH_AST_SI_LD_GNPU_AU15_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU16_QCH, LH_AST_SI_LD_GNPU_AU16_QCH, "GATE_LH_AST_SI_LD_GNPU_AU16_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU17_QCH, LH_AST_SI_LD_GNPU_AU17_QCH, "GATE_LH_AST_SI_LD_GNPU_AU17_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU18_QCH, LH_AST_SI_LD_GNPU_AU18_QCH, "GATE_LH_AST_SI_LD_GNPU_AU18_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU19_QCH, LH_AST_SI_LD_GNPU_AU19_QCH, "GATE_LH_AST_SI_LD_GNPU_AU19_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU2_QCH, LH_AST_SI_LD_GNPU_AU2_QCH, "GATE_LH_AST_SI_LD_GNPU_AU2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU20_QCH, LH_AST_SI_LD_GNPU_AU20_QCH, "GATE_LH_AST_SI_LD_GNPU_AU20_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU21_QCH, LH_AST_SI_LD_GNPU_AU21_QCH, "GATE_LH_AST_SI_LD_GNPU_AU21_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU22_QCH, LH_AST_SI_LD_GNPU_AU22_QCH, "GATE_LH_AST_SI_LD_GNPU_AU22_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU23_QCH, LH_AST_SI_LD_GNPU_AU23_QCH, "GATE_LH_AST_SI_LD_GNPU_AU23_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU24_QCH, LH_AST_SI_LD_GNPU_AU24_QCH, "GATE_LH_AST_SI_LD_GNPU_AU24_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU25_QCH, LH_AST_SI_LD_GNPU_AU25_QCH, "GATE_LH_AST_SI_LD_GNPU_AU25_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU26_QCH, LH_AST_SI_LD_GNPU_AU26_QCH, "GATE_LH_AST_SI_LD_GNPU_AU26_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU27_QCH, LH_AST_SI_LD_GNPU_AU27_QCH, "GATE_LH_AST_SI_LD_GNPU_AU27_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU28_QCH, LH_AST_SI_LD_GNPU_AU28_QCH, "GATE_LH_AST_SI_LD_GNPU_AU28_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU29_QCH, LH_AST_SI_LD_GNPU_AU29_QCH, "GATE_LH_AST_SI_LD_GNPU_AU29_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU3_QCH, LH_AST_SI_LD_GNPU_AU3_QCH, "GATE_LH_AST_SI_LD_GNPU_AU3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU30_QCH, LH_AST_SI_LD_GNPU_AU30_QCH, "GATE_LH_AST_SI_LD_GNPU_AU30_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU31_QCH, LH_AST_SI_LD_GNPU_AU31_QCH, "GATE_LH_AST_SI_LD_GNPU_AU31_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU4_QCH, LH_AST_SI_LD_GNPU_AU4_QCH, "GATE_LH_AST_SI_LD_GNPU_AU4_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU5_QCH, LH_AST_SI_LD_GNPU_AU5_QCH, "GATE_LH_AST_SI_LD_GNPU_AU5_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU6_QCH, LH_AST_SI_LD_GNPU_AU6_QCH, "GATE_LH_AST_SI_LD_GNPU_AU6_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU7_QCH, LH_AST_SI_LD_GNPU_AU7_QCH, "GATE_LH_AST_SI_LD_GNPU_AU7_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU8_QCH, LH_AST_SI_LD_GNPU_AU8_QCH, "GATE_LH_AST_SI_LD_GNPU_AU8_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AU9_QCH, LH_AST_SI_LD_GNPU_AU9_QCH, "GATE_LH_AST_SI_LD_GNPU_AU9_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_AULOADER_QCH, LH_AST_SI_LD_GNPU_AULOADER_QCH, "GATE_LH_AST_SI_LD_GNPU_AULOADER_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_CU_RDATA_QCH, LH_AST_SI_LD_GNPU_CU_RDATA_QCH, "GATE_LH_AST_SI_LD_GNPU_CU_RDATA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_NPUC_SETREG_QCH, LH_AST_SI_LD_GNPU_NPUC_SETREG_QCH, "GATE_LH_AST_SI_LD_GNPU_NPUC_SETREG_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPU_SRAM_WRRESP_QCH, LH_AST_SI_LD_GNPU_SRAM_WRRESP_QCH, "GATE_LH_AST_SI_LD_GNPU_SRAM_WRRESP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D0_GNPU_QCH, LH_AXI_MI_D0_GNPU_QCH, "GATE_LH_AXI_MI_D0_GNPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D1_GNPU_QCH, LH_AXI_MI_D1_GNPU_QCH, "GATE_LH_AXI_MI_D1_GNPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D_CTRL_GNPU_QCH, LH_AXI_MI_D_CTRL_GNPU_QCH, "GATE_LH_AXI_MI_D_CTRL_GNPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D_RQ_GNPU_QCH, LH_AXI_SI_D_RQ_GNPU_QCH, "GATE_LH_AXI_SI_D_RQ_GNPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH, LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH, "GATE_LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_GNPU_QCH, SLH_AXI_MI_P_GNPU_QCH, "GATE_SLH_AXI_MI_P_GNPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_D_CMDQ_GNPU_QCH, SLH_AXI_SI_D_CMDQ_GNPU_QCH, "GATE_SLH_AXI_SI_D_CMDQ_GNPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_GNPU_QCH, SYSREG_GNPU_QCH, "GATE_SYSREG_GNPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_GNPUP_QCH, D_TZPC_GNPUP_QCH, "GATE_D_TZPC_GNPUP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GNPUP_CMU_GNPUP_QCH, GNPUP_CMU_GNPUP_QCH, "GATE_GNPUP_CMU_GNPUP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPUPOST_QCH_CORE, IP_NPUPOST_QCH_CORE, "GATE_IP_NPUPOST_QCH_CORE", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU0_QCH, LH_AST_MI_LD_GNPU_AU0_QCH, "GATE_LH_AST_MI_LD_GNPU_AU0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU1_QCH, LH_AST_MI_LD_GNPU_AU1_QCH, "GATE_LH_AST_MI_LD_GNPU_AU1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU10_QCH, LH_AST_MI_LD_GNPU_AU10_QCH, "GATE_LH_AST_MI_LD_GNPU_AU10_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU11_QCH, LH_AST_MI_LD_GNPU_AU11_QCH, "GATE_LH_AST_MI_LD_GNPU_AU11_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU12_QCH, LH_AST_MI_LD_GNPU_AU12_QCH, "GATE_LH_AST_MI_LD_GNPU_AU12_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU13_QCH, LH_AST_MI_LD_GNPU_AU13_QCH, "GATE_LH_AST_MI_LD_GNPU_AU13_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU14_QCH, LH_AST_MI_LD_GNPU_AU14_QCH, "GATE_LH_AST_MI_LD_GNPU_AU14_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU15_QCH, LH_AST_MI_LD_GNPU_AU15_QCH, "GATE_LH_AST_MI_LD_GNPU_AU15_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU16_QCH, LH_AST_MI_LD_GNPU_AU16_QCH, "GATE_LH_AST_MI_LD_GNPU_AU16_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU17_QCH, LH_AST_MI_LD_GNPU_AU17_QCH, "GATE_LH_AST_MI_LD_GNPU_AU17_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU18_QCH, LH_AST_MI_LD_GNPU_AU18_QCH, "GATE_LH_AST_MI_LD_GNPU_AU18_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU19_QCH, LH_AST_MI_LD_GNPU_AU19_QCH, "GATE_LH_AST_MI_LD_GNPU_AU19_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU2_QCH, LH_AST_MI_LD_GNPU_AU2_QCH, "GATE_LH_AST_MI_LD_GNPU_AU2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU20_QCH, LH_AST_MI_LD_GNPU_AU20_QCH, "GATE_LH_AST_MI_LD_GNPU_AU20_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU21_QCH, LH_AST_MI_LD_GNPU_AU21_QCH, "GATE_LH_AST_MI_LD_GNPU_AU21_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU22_QCH, LH_AST_MI_LD_GNPU_AU22_QCH, "GATE_LH_AST_MI_LD_GNPU_AU22_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU23_QCH, LH_AST_MI_LD_GNPU_AU23_QCH, "GATE_LH_AST_MI_LD_GNPU_AU23_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU24_QCH, LH_AST_MI_LD_GNPU_AU24_QCH, "GATE_LH_AST_MI_LD_GNPU_AU24_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU25_QCH, LH_AST_MI_LD_GNPU_AU25_QCH, "GATE_LH_AST_MI_LD_GNPU_AU25_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU26_QCH, LH_AST_MI_LD_GNPU_AU26_QCH, "GATE_LH_AST_MI_LD_GNPU_AU26_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU27_QCH, LH_AST_MI_LD_GNPU_AU27_QCH, "GATE_LH_AST_MI_LD_GNPU_AU27_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU28_QCH, LH_AST_MI_LD_GNPU_AU28_QCH, "GATE_LH_AST_MI_LD_GNPU_AU28_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU29_QCH, LH_AST_MI_LD_GNPU_AU29_QCH, "GATE_LH_AST_MI_LD_GNPU_AU29_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU3_QCH, LH_AST_MI_LD_GNPU_AU3_QCH, "GATE_LH_AST_MI_LD_GNPU_AU3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU30_QCH, LH_AST_MI_LD_GNPU_AU30_QCH, "GATE_LH_AST_MI_LD_GNPU_AU30_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU31_QCH, LH_AST_MI_LD_GNPU_AU31_QCH, "GATE_LH_AST_MI_LD_GNPU_AU31_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU4_QCH, LH_AST_MI_LD_GNPU_AU4_QCH, "GATE_LH_AST_MI_LD_GNPU_AU4_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU5_QCH, LH_AST_MI_LD_GNPU_AU5_QCH, "GATE_LH_AST_MI_LD_GNPU_AU5_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU6_QCH, LH_AST_MI_LD_GNPU_AU6_QCH, "GATE_LH_AST_MI_LD_GNPU_AU6_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU7_QCH, LH_AST_MI_LD_GNPU_AU7_QCH, "GATE_LH_AST_MI_LD_GNPU_AU7_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU8_QCH, LH_AST_MI_LD_GNPU_AU8_QCH, "GATE_LH_AST_MI_LD_GNPU_AU8_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AU9_QCH, LH_AST_MI_LD_GNPU_AU9_QCH, "GATE_LH_AST_MI_LD_GNPU_AU9_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_AULOADER_QCH, LH_AST_MI_LD_GNPU_AULOADER_QCH, "GATE_LH_AST_MI_LD_GNPU_AULOADER_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_CU_RDATA_QCH, LH_AST_MI_LD_GNPU_CU_RDATA_QCH, "GATE_LH_AST_MI_LD_GNPU_CU_RDATA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_NPUC_SETREG_QCH, LH_AST_MI_LD_GNPU_NPUC_SETREG_QCH, "GATE_LH_AST_MI_LD_GNPU_NPUC_SETREG_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_GNPU_SRAM_WRRESP_QCH, LH_AST_MI_LD_GNPU_SRAM_WRRESP_QCH, "GATE_LH_AST_MI_LD_GNPU_SRAM_WRRESP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPUP_BU0_QCH, LH_AST_SI_LD_GNPUP_BU0_QCH, "GATE_LH_AST_SI_LD_GNPUP_BU0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPUP_BU1_QCH, LH_AST_SI_LD_GNPUP_BU1_QCH, "GATE_LH_AST_SI_LD_GNPUP_BU1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPUP_BU2_QCH, LH_AST_SI_LD_GNPUP_BU2_QCH, "GATE_LH_AST_SI_LD_GNPUP_BU2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPUP_BU3_QCH, LH_AST_SI_LD_GNPUP_BU3_QCH, "GATE_LH_AST_SI_LD_GNPUP_BU3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPUP_CU_WCH_QCH, LH_AST_SI_LD_GNPUP_CU_WCH_QCH, "GATE_LH_AST_SI_LD_GNPUP_CU_WCH_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPUP_NPUC_DONE_QCH, LH_AST_SI_LD_GNPUP_NPUC_DONE_QCH, "GATE_LH_AST_SI_LD_GNPUP_NPUC_DONE_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_GNPUP_RDREQ_QCH, LH_AST_SI_LD_GNPUP_RDREQ_QCH, "GATE_LH_AST_SI_LD_GNPUP_RDREQ_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_GNPUP_QCH, SLH_AXI_MI_P_GNPUP_QCH, "GATE_SLH_AXI_MI_P_GNPUP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_GNPUP_QCH, SYSREG_GNPUP_QCH, "GATE_SYSREG_GNPUP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_peric0_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_PERIC0_NOC, MUX_CLKCMU_PERIC0_NOC_USER, "UMUX_CLKCMU_PERIC0_NOC", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_PERIC0_IP0, MUX_CLKCMU_PERIC0_IP0_USER, "UMUX_CLKCMU_PERIC0_IP0", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_PERIC0_IP1, MUX_CLKCMU_PERIC0_IP1_USER, "UMUX_CLKCMU_PERIC0_IP1", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_PERIC0_QCH, D_TZPC_PERIC0_QCH, "GATE_D_TZPC_PERIC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPIO_PERIC0_QCH, GPIO_PERIC0_QCH, "GATE_GPIO_PERIC0_QCH", "UMUX_CLKCMU_PERIC0_NOC", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC0_CMU_PERIC0_QCH, PERIC0_CMU_PERIC0_QCH, "GATE_PERIC0_CMU_PERIC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_PERIC0_QCH, SLH_AXI_MI_P_PERIC0_QCH, "GATE_SLH_AXI_MI_P_PERIC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_PERIC0_QCH, SYSREG_PERIC0_QCH, "GATE_SYSREG_PERIC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
HWACG_VCLK(GATE_USI04_USI_QCH, USI04_USI_QCH, "GATE_USI04_USI_QCH", "UMUX_CLKCMU_PERIC0_IP0", 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_peric1_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_PERIC1_NOC, MUX_CLKCMU_PERIC1_NOC_USER, "UMUX_CLKCMU_PERIC1_NOC", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_PERIC1_IP0, MUX_CLKCMU_PERIC1_IP0_USER, "UMUX_CLKCMU_PERIC1_IP0", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_PERIC1_IP1, MUX_CLKCMU_PERIC1_IP1_USER, "UMUX_CLKCMU_PERIC1_IP1", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_PERIC1_QCH, D_TZPC_PERIC1_QCH, "GATE_D_TZPC_PERIC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPIO_PERIC1_QCH, GPIO_PERIC1_QCH, "GATE_GPIO_PERIC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC1_CMU_PERIC1_QCH, PERIC1_CMU_PERIC1_QCH, "GATE_PERIC1_CMU_PERIC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_CSISPERIC1_QCH, SLH_AXI_MI_P_CSISPERIC1_QCH, "GATE_SLH_AXI_MI_P_CSISPERIC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_PERIC1_QCH, SLH_AXI_MI_P_PERIC1_QCH, "GATE_SLH_AXI_MI_P_PERIC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH, SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH, "GATE_SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_PERIC1_QCH, SYSREG_PERIC1_QCH, "GATE_SYSREG_PERIC1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_peric2_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_PERIC2_IP0, MUX_CLKCMU_PERIC2_IP0_USER, "UMUX_CLKCMU_PERIC2_IP0", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_PERIC2_IP1, MUX_CLKCMU_PERIC2_IP1_USER, "UMUX_CLKCMU_PERIC2_IP1", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_PERIC2_NOC, MUX_CLKCMU_PERIC2_NOC_USER, "UMUX_CLKCMU_PERIC2_NOC", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_PERIC2_QCH, D_TZPC_PERIC2_QCH, "GATE_D_TZPC_PERIC2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPIO_PERIC2_QCH, GPIO_PERIC2_QCH, "GATE_GPIO_PERIC2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIC2_CMU_PERIC2_QCH, PERIC2_CMU_PERIC2_QCH, "GATE_PERIC2_CMU_PERIC2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PWM_QCH, PWM_QCH, "GATE_PWM_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_PERIC2_QCH, SLH_AXI_MI_P_PERIC2_QCH, "GATE_SLH_AXI_MI_P_PERIC2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH, SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH, "GATE_SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_PERIC2_QCH, SYSREG_PERIC2_QCH, "GATE_SYSREG_PERIC2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_peris_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_PERIS_NOC, MUX_CLKCMU_PERIS_NOC_USER, "UMUX_CLKCMU_PERIS_NOC", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_PERIS_GIC, MUX_CLKCMU_PERIS_GIC_USER, "UMUX_CLKCMU_PERIS_GIC", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_BUSIF_DDD_PERIS_QCH, BUSIF_DDD_PERIS_QCH, "GATE_BUSIF_DDD_PERIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_PERIS_QCH, DFTMUX_PERIS_QCH, "GATE_DFTMUX_PERIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_PERIS_QCH, D_TZPC_PERIS_QCH, "GATE_D_TZPC_PERIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERIS_CMU_PERIS_QCH, PERIS_CMU_PERIS_QCH, "GATE_PERIS_CMU_PERIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_PERIS_QCH, SLH_AXI_MI_P_PERIS_QCH, "GATE_SLH_AXI_MI_P_PERIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_PERISGIC_QCH, SLH_AXI_MI_P_PERISGIC_QCH, "GATE_SLH_AXI_MI_P_PERISGIC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_PERIS_QCH, SYSREG_PERIS_QCH, "GATE_SYSREG_PERIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
HWACG_VCLK(GATE_MCT_QCH, MCT_QCH, "GATE_MCT_QCH", "UMUX_CLKCMU_PERIS_NOC", 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_WDT0_QCH, WDT0_QCH, "GATE_WDT0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_WDT1_QCH, WDT1_QCH, "GATE_WDT1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_s2d_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(GATE_BIS_S2D_QCH, BIS_S2D_QCH, "GATE_BIS_S2D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_S2D_CMU_S2D_QCH, S2D_CMU_S2D_QCH, "GATE_S2D_CMU_S2D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_ssp_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_SSP_NOC_USER, MUX_CLKCMU_SSP_NOC_USER, "UMUX_CLKCMU_SSP_NOC_USER", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_SSP_QCH, D_TZPC_SSP_QCH, "GATE_D_TZPC_SSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_L_STRONG_QCH, LH_AXI_MI_L_STRONG_QCH, "GATE_LH_AXI_MI_L_STRONG_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_SSP_QCH, PPMU_SSP_QCH, "GATE_PPMU_SSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_SSP_CM35P_QCH, RSTNSYNC_CLK_SSP_CM35P_QCH, "GATE_RSTNSYNC_CLK_SSP_CM35P_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RTIC_QCH, RTIC_QCH, "GATE_RTIC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_ACEL_SI_D_SSP_QCH, SLH_ACEL_SI_D_SSP_QCH, "GATE_SLH_ACEL_SI_D_SSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_ASTL_SI_G_PPMU_SSP_QCH, SLH_ASTL_SI_G_PPMU_SSP_QCH, "GATE_SLH_ASTL_SI_G_PPMU_SSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_SSP_QCH, SLH_AXI_MI_P_SSP_QCH, "GATE_SLH_AXI_MI_P_SSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SSP_CMU_SSP_QCH, SSP_CMU_SSP_QCH, "GATE_SSP_CMU_SSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SSS_QCH, SSS_QCH, "GATE_SSS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SWEEPER_D_SSP_QCH, SWEEPER_D_SSP_QCH, "GATE_SWEEPER_D_SSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_SSP_QCH, SYSMMU_SSP_QCH, "GATE_SYSMMU_SSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_SSP_QCH, SYSREG_SSP_QCH, "GATE_SYSREG_SSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_SSP_QCH, VGEN_LITE_SSP_QCH, "GATE_VGEN_LITE_SSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ADM_DAP_G_SSS_QCH, ADM_DAP_G_SSS_QCH, "GATE_ADM_DAP_G_SSS_QCH", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
|
|
};
|
|
|
|
|
|
struct init_vclk s5e9925_vts_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_VTS_DMIC_USER, MUX_CLKCMU_VTS_DMIC_USER, "UMUX_CLKCMU_VTS_DMIC_USER", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_VTS_QCH, D_TZPC_VTS_QCH, "GATE_D_TZPC_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPIO_VTS_QCH, GPIO_VTS_QCH, "GATE_GPIO_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT, ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT, "GATE_ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BAAW_C_VTS_QCH, BAAW_C_VTS_QCH, "GATE_BAAW_C_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MAILBOX_ABOX_VTS_QCH, MAILBOX_ABOX_VTS_QCH, "GATE_MAILBOX_ABOX_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MAILBOX_AP_VTS_QCH, MAILBOX_AP_VTS_QCH, "GATE_MAILBOX_AP_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MAILBOX_DNC_VTS_QCH, MAILBOX_DNC_VTS_QCH, "GATE_MAILBOX_DNC_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PDMA_VTS_QCH, PDMA_VTS_QCH, "GATE_PDMA_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_LD_AUDVTS_QCH, SLH_AXI_MI_LD_AUDVTS_QCH, "GATE_SLH_AXI_MI_LD_AUDVTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_LD_DNCVTS_QCH, SLH_AXI_MI_LD_DNCVTS_QCH, "GATE_SLH_AXI_MI_LD_DNCVTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_LP_VTS_QCH, SLH_AXI_MI_LP_VTS_QCH, "GATE_SLH_AXI_MI_LP_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_VTS_QCH, SLH_AXI_MI_P_VTS_QCH, "GATE_SLH_AXI_MI_P_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_C_VTS_QCH, SLH_AXI_SI_C_VTS_QCH, "GATE_SLH_AXI_SI_C_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD0, SS_VTS_GLUE_QCH_DMIC_IF_PAD0, "GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD0", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD1, SS_VTS_GLUE_QCH_DMIC_IF_PAD1, "GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD2, SS_VTS_GLUE_QCH_DMIC_IF_PAD2, "GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK, SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK, "GATE_SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SWEEPER_C_VTS_QCH, SWEEPER_C_VTS_QCH, "GATE_SWEEPER_C_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_VTS_QCH, SYSREG_VTS_QCH, "GATE_SYSREG_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VTS_CMU_VTS_QCH, VTS_CMU_VTS_QCH, "GATE_VTS_CMU_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_WDT_VTS_QCH, WDT_VTS_QCH, "GATE_WDT_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_YAMIN_MCU_VTS_QCH_CLKIN, YAMIN_MCU_VTS_QCH_CLKIN, "GATE_YAMIN_MCU_VTS_QCH_CLKIN", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_YAMIN_MCU_VTS_QCH_DBGCLK, YAMIN_MCU_VTS_QCH_DBGCLK, "GATE_YAMIN_MCU_VTS_QCH_DBGCLK", NULL, 0, VCLK_GATE, NULL),
|
|
|
|
HWACG_VCLK(MOUT_CLK_VTS_DMIC_PAD, MUX_CLK_VTS_DMIC_PAD, "MOUT_CLK_VTS_DMIC_PAD", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(MOUT_CLK_VTS_SERIAL_LIF, MUX_CLK_VTS_SERIAL_LIF, "MOUT_CLK_VTS_SERIAL_LIF", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(MOUT_CLKALIVE_VTS_NOC_USER, MUX_CLKALIVE_VTS_NOC_USER, "MOUT_CLKALIVE_VTS_NOC_USER", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(MOUT_CLKALIVE_VTS_RCO_USER, MUX_CLKALIVE_VTS_RCO_USER, "MOUT_CLKALIVE_VTS_RCO_USER", NULL, 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_yuvp_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_YUVP_NOC, MUX_CLKCMU_YUVP_NOC_USER, "UMUX_CLKCMU_YUVP_NOC", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_ADD_YUVP_QCH, ADD_YUVP_QCH, "GATE_ADD_YUVP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_ADD_YUVP_QCH, BUSIF_ADD_YUVP_QCH, "GATE_BUSIF_ADD_YUVP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_DDD_YUVP_QCH, BUSIF_DDD_YUVP_QCH, "GATE_BUSIF_DDD_YUVP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BUSIF_HPM_YUVP_QCH, BUSIF_HPM_YUVP_QCH, "GATE_BUSIF_HPM_YUVP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_YUVP_QCH, D_TZPC_YUVP_QCH, "GATE_D_TZPC_YUVP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_OTF0_MCFPYUVP_QCH, LH_AST_MI_OTF0_MCFPYUVP_QCH, "GATE_LH_AST_MI_OTF0_MCFPYUVP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_OTF_YUVPDRCP_QCH, LH_AST_SI_OTF_YUVPDRCP_QCH, "GATE_LH_AST_SI_OTF_YUVPDRCP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_OTF_YUVPMCFP_QCH, LH_AST_SI_OTF_YUVPMCFP_QCH, "GATE_LH_AST_SI_OTF_YUVPMCFP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_YUVP_QCH, PPMU_YUVP_QCH, "GATE_PPMU_YUVP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_ASTL_SI_G_PPMU_YUVP_QCH, SLH_ASTL_SI_G_PPMU_YUVP_QCH, "GATE_SLH_ASTL_SI_G_PPMU_YUVP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_YUVP_QCH, SLH_AXI_MI_P_YUVP_QCH, "GATE_SLH_AXI_MI_P_YUVP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_D_YUVP_QCH, SLH_AXI_SI_D_YUVP_QCH, "GATE_SLH_AXI_SI_D_YUVP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_YUVP_QCH_S1, SYSMMU_D_YUVP_QCH_S1, "GATE_SYSMMU_D_YUVP_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_YUVP_QCH_S2, SYSMMU_D_YUVP_QCH_S2, "GATE_SYSMMU_D_YUVP_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_YUVP_QCH, SYSREG_YUVP_QCH, "GATE_SYSREG_YUVP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_YUVP_QCH, VGEN_LITE_YUVP_QCH, "GATE_VGEN_LITE_YUVP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_YUVP_QCH, YUVP_QCH, "GATE_YUVP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_YUVP_CMU_YUVP_QCH, YUVP_CMU_YUVP_QCH, "GATE_YUVP_CMU_YUVP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_cstat_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_CSTAT_NOC, MUX_CLKCMU_CSTAT_NOC_USER, "UMUX_CLKCMU_CSTAT_NOC", NULL, 0, 0, NULL),
|
|
|
|
};
|
|
struct init_vclk s5e9925_dsp_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_DSP_NOC, MUX_CLKCMU_DSP_NOC_USER, "UMUX_CLKCMU_DSP_NOC", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_DSP_CMU_DSP_QCH, DSP_CMU_DSP_QCH, "GATE_DSP_CMU_DSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_DSP_QCH, D_TZPC_DSP_QCH, "GATE_D_TZPC_DSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_DSP_QCH, IP_DSP_QCH, "GATE_IP_DSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_LD_STRM_SDMADSP_QCH, LH_AST_MI_LD_STRM_SDMADSP_QCH, "GATE_LH_AST_MI_LD_STRM_SDMADSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_LD_DNCDSP_DMA_QCH, LH_AXI_MI_LD_DNCDSP_DMA_QCH, "GATE_LH_AXI_MI_LD_DNCDSP_DMA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_LD_DNCDSP_SFR_QCH, LH_AXI_MI_LD_DNCDSP_SFR_QCH, "GATE_LH_AXI_MI_LD_DNCDSP_SFR_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_LD_DSPDNC_SFR_QCH, LH_AXI_SI_LD_DSPDNC_SFR_QCH, "GATE_LH_AXI_SI_LD_DSPDNC_SFR_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_LD_DSPDNC_SHMEM_QCH, LH_AXI_SI_LD_DSPDNC_SHMEM_QCH, "GATE_LH_AXI_SI_LD_DSPDNC_SHMEM_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_DSP_QCH, SLH_AXI_MI_P_DSP_QCH, "GATE_SLH_AXI_MI_P_DSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_LD_DSPDNC_CACHE_QCH, SLH_AXI_SI_LD_DSPDNC_CACHE_QCH, "GATE_SLH_AXI_SI_LD_DSPDNC_CACHE_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_DSP_QCH, SYSREG_DSP_QCH, "GATE_SYSREG_DSP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
struct init_vclk s5e9925_sdma_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(UMUX_CLKCMU_SDMA_NOC, MUX_CLKCMU_SDMA_NOC_USER, "UMUX_CLKCMU_SDMA_NOC", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_D_TZPC_SDMA_QCH, D_TZPC_SDMA_QCH, "GATE_D_TZPC_SDMA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_SDMA_QCH, IP_SDMA_QCH, "GATE_IP_SDMA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_STRM_SDMADSP0_QCH, LH_AST_SI_LD_STRM_SDMADSP0_QCH, "GATE_LH_AST_SI_LD_STRM_SDMADSP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_LD_STRM_SDMADSP1_QCH, LH_AST_SI_LD_STRM_SDMADSP1_QCH, "GATE_LH_AST_SI_LD_STRM_SDMADSP1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_LP_DNCSDMA_QCH, LH_AXI_MI_LP_DNCSDMA_QCH, "GATE_LH_AXI_MI_LP_DNCSDMA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_LD_SDMADNC_DATA0_QCH, LH_AXI_SI_LD_SDMADNC_DATA0_QCH, "GATE_LH_AXI_SI_LD_SDMADNC_DATA0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_LD_SDMADNC_DATA1_QCH, LH_AXI_SI_LD_SDMADNC_DATA1_QCH, "GATE_LH_AXI_SI_LD_SDMADNC_DATA1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_LD_SDMADNC_DATA2_QCH, LH_AXI_SI_LD_SDMADNC_DATA2_QCH, "GATE_LH_AXI_SI_LD_SDMADNC_DATA2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_LD_SDMADNC_DATA3_QCH, LH_AXI_SI_LD_SDMADNC_DATA3_QCH, "GATE_LH_AXI_SI_LD_SDMADNC_DATA3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_LD_SDMADNC_DATA4_QCH, LH_AXI_SI_LD_SDMADNC_DATA4_QCH, "GATE_LH_AXI_SI_LD_SDMADNC_DATA4_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_LD_SDMADNC_DATA5_QCH, LH_AXI_SI_LD_SDMADNC_DATA5_QCH, "GATE_LH_AXI_SI_LD_SDMADNC_DATA5_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_LD_SDMADNC_DATA6_QCH, LH_AXI_SI_LD_SDMADNC_DATA6_QCH, "GATE_LH_AXI_SI_LD_SDMADNC_DATA6_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_LD_SDMADNC_DATA7_QCH, LH_AXI_SI_LD_SDMADNC_DATA7_QCH, "GATE_LH_AXI_SI_LD_SDMADNC_DATA7_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_LD_SDMADNC_MMU0_QCH, LH_AXI_SI_LD_SDMADNC_MMU0_QCH, "GATE_LH_AXI_SI_LD_SDMADNC_MMU0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_LD_SDMADNC_MMU1_QCH, LH_AXI_SI_LD_SDMADNC_MMU1_QCH, "GATE_LH_AXI_SI_LD_SDMADNC_MMU1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_LD_SDMADNC_MMU2_QCH, LH_AXI_SI_LD_SDMADNC_MMU2_QCH, "GATE_LH_AXI_SI_LD_SDMADNC_MMU2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_LD_SDMADNC_MMU3_QCH, LH_AXI_SI_LD_SDMADNC_MMU3_QCH, "GATE_LH_AXI_SI_LD_SDMADNC_MMU3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SDMA_CMU_SDMA_QCH, SDMA_CMU_SDMA_QCH, "GATE_SDMA_CMU_SDMA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_SDMA_QCH, SLH_AXI_MI_P_SDMA_QCH, "GATE_SLH_AXI_MI_P_SDMA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_SDMA_QCH, SYSREG_SDMA_QCH, "GATE_SYSREG_SDMA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
struct init_vclk s5e9925_ufd_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(GATE_BAAW_D_UFDDNC_QCH, BAAW_D_UFDDNC_QCH, "GATE_BAAW_D_UFDDNC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_UFD_QCH, D_TZPC_UFD_QCH, "GATE_D_TZPC_UFD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I3C_UFD_QCH_PCLK, I3C_UFD_QCH_PCLK, "GATE_I3C_UFD_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I3C_UFD_QCH_SCLK, I3C_UFD_QCH_SCLK, "GATE_I3C_UFD_QCH_SCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PDMA_UFD_QCH, PDMA_UFD_QCH, "GATE_PDMA_UFD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AST_MI_OTF_CSISUFD_QCH, SLH_AST_MI_OTF_CSISUFD_QCH, "GATE_SLH_AST_MI_OTF_CSISUFD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_LP_CMGPUFD_QCH, SLH_AXI_MI_LP_CMGPUFD_QCH, "GATE_SLH_AXI_MI_LP_CMGPUFD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_UFD_QCH, SLH_AXI_MI_P_UFD_QCH, "GATE_SLH_AXI_MI_P_UFD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_D_UFD_QCH, SLH_AXI_SI_D_UFD_QCH, "GATE_SLH_AXI_SI_D_UFD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_LD_UFDDNC_QCH, SLH_AXI_SI_LD_UFDDNC_QCH, "GATE_SLH_AXI_SI_LD_UFDDNC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_LP_UFDCSIS_QCH, SLH_AXI_SI_LP_UFDCSIS_QCH, "GATE_SLH_AXI_SI_LP_UFDCSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SPI_UFD_QCH, SPI_UFD_QCH, "GATE_SPI_UFD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SRAM_MIU_UFD_QCH, SRAM_MIU_UFD_QCH, "GATE_SRAM_MIU_UFD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_UFD_QCH, SYSREG_UFD_QCH, "GATE_SYSREG_UFD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_UFD_SECURE_QCH, SYSREG_UFD_SECURE_QCH, "GATE_SYSREG_UFD_SECURE_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_UFD_CMU_UFD_QCH, UFD_CMU_UFD_QCH, "GATE_UFD_CMU_UFD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_D_UFD_QCH, VGEN_LITE_D_UFD_QCH, "GATE_VGEN_LITE_D_UFD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_UFD_QCH, UFD_QCH, "GATE_UFD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
/* Special VCLK */
|
|
struct init_vclk s5e9925_alive_vclks[] = {
|
|
|
|
VCLK(DOUT_CLKALIVE_UFD_NOC, CLKALIVE_UFD_NOC, "DOUT_CLKALIVE_UFD_NOC", 0, 0, NULL),
|
|
VCLK(DOUT_CLKALIVE_VTS_NOC, CLKALIVE_VTS_NOC, "DOUT_CLKALIVE_VTS_NOC", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_ALIVE_NOC, DIV_CLK_ALIVE_NOC, "DOUT_DIV_CLK_ALIVE_NOC", 0, 0, NULL),
|
|
VCLK(DOUT_CLKALIVE_CMGP_NOC, CLKALIVE_CMGP_NOC, "DOUT_CLKALIVE_CMGP_NOC", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_ALIVE_SPMI, DIV_CLK_ALIVE_SPMI, "DOUT_DIV_CLK_ALIVE_SPMI", 0, 0, NULL),
|
|
VCLK(DOUT_CLKALIVE_CMGP_PERI, CLKALIVE_CMGP_PERI, "DOUT_CLKALIVE_CMGP_PERI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_ALIVE_DBGCORE_UART, DIV_CLK_ALIVE_DBGCORE_UART, "DOUT_DIV_CLK_ALIVE_DBGCORE_UART", 0, 0, NULL),
|
|
VCLK(DOUT_CLKALIVE_CHUB_NOC, CLKALIVE_CHUB_NOC, "DOUT_CLKALIVE_CHUB_NOC", 0, 0, NULL),
|
|
VCLK(DOUT_CLKALIVE_CHUB_PERI, CLKALIVE_CHUB_PERI, "DOUT_CLKALIVE_CHUB_PERI", 0, 0, NULL),
|
|
VCLK(DOUT_CLKALIVE_DBGCORE_NOC, CLKALIVE_DBGCORE_NOC, "DOUT_CLKALIVE_DBGCORE_NOC", 0, 0, NULL),
|
|
VCLK(DOUT_CLKALIVE_DNC_NOC, CLKALIVE_DNC_NOC, "DOUT_CLKALIVE_DNC_NOC", 0, 0, NULL),
|
|
VCLK(DOUT_CLKALIVE_GNPU_NOC, CLKALIVE_GNPU_NOC, "DOUT_CLKALIVE_GNPU_NOC", 0, 0, NULL),
|
|
VCLK(DOUT_CLKALIVE_SDMA_NOC, CLKALIVE_SDMA_NOC, "DOUT_CLKALIVE_SDMA_NOC", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_ALIVE_PMU_SUB, DIV_CLK_ALIVE_PMU_SUB, "DOUT_DIV_CLK_ALIVE_PMU_SUB", 0, 0, NULL),
|
|
VCLK(DOUT_CLKALIVE_GNPUP_NOC, CLKALIVE_GNPUP_NOC, "DOUT_CLKALIVE_GNPUP_NOC", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_ALIVE_NOC, CLKCMU_ALIVE_NOC, "DOUT_CLKCMU_ALIVE_NOC", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_aud_vclks[] = {
|
|
VCLK(MOUT_MUX_CLK_AUD_PCMC, MUX_CLK_AUD_PCMC, "MOUT_MUX_CLK_AUD_PCMC", 0, 0, NULL),
|
|
VCLK(MOUT_MUX_CLK_AUD_SCLK, MUX_CLK_AUD_SCLK, "MOUT_MUX_CLK_AUD_SCLK", 0, 0, NULL),
|
|
VCLK(MOUT_CLK_AUD_UAIF6, MUX_CLK_AUD_UAIF6, "MOUT_CLK_AUD_UAIF6", 0, 0, NULL),
|
|
VCLK(MOUT_CLK_AUD_UAIF0, MUX_CLK_AUD_UAIF0, "MOUT_CLK_AUD_UAIF0", 0, 0, NULL),
|
|
VCLK(MOUT_CLK_AUD_UAIF1, MUX_CLK_AUD_UAIF1, "MOUT_CLK_AUD_UAIF1", 0, 0, NULL),
|
|
VCLK(MOUT_CLK_AUD_UAIF2, MUX_CLK_AUD_UAIF2, "MOUT_CLK_AUD_UAIF2", 0, 0, NULL),
|
|
VCLK(MOUT_CLK_AUD_UAIF3, MUX_CLK_AUD_UAIF3, "MOUT_CLK_AUD_UAIF3", 0, 0, NULL),
|
|
VCLK(MOUT_CLK_AUD_UAIF4, MUX_CLK_AUD_UAIF4, "MOUT_CLK_AUD_UAIF4", 0, 0, NULL),
|
|
VCLK(MOUT_CLK_AUD_UAIF5, MUX_CLK_AUD_UAIF5, "MOUT_CLK_AUD_UAIF5", 0, 0, NULL),
|
|
VCLK(UMUX_CP_PCMC_CLK, MUX_CP_PCMC_CLK_USER, "UMUX_CP_PCMC_CLK", 0, 0, NULL),
|
|
VCLK(MOUT_CLK_AUD_SERIAL_LIF, MUX_CLK_AUD_SERIAL_LIF, "MOUT_CLK_AUD_SERIAL_LIF", 0, 0, NULL),
|
|
|
|
VCLK(DOUT_DIV_CLK_AUD_CPU_PCLKDBG, DIV_CLK_AUD_CPU_PCLKDBG, "DOUT_DIV_CLK_AUD_CPU_PCLKDBG", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_DSIF, DIV_CLK_AUD_DSIF, "DOUT_DIV_CLK_AUD_DSIF", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF0, DIV_CLK_AUD_UAIF0, "DOUT_DIV_CLK_AUD_UAIF0", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF1, DIV_CLK_AUD_UAIF1, "DOUT_DIV_CLK_AUD_UAIF1", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF2, DIV_CLK_AUD_UAIF2, "DOUT_DIV_CLK_AUD_UAIF2", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF3, DIV_CLK_AUD_UAIF3, "DOUT_DIV_CLK_AUD_UAIF3", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_CPU_ACLK, DIV_CLK_AUD_CPU_ACLK, "DOUT_DIV_CLK_AUD_CPU_ACLK", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_NOC, DIV_CLK_AUD_NOC, "DOUT_DIV_CLK_AUD_NOC", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_NOCP, DIV_CLK_AUD_NOCP, "DOUT_DIV_CLK_AUD_NOCP", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_CNT, DIV_CLK_AUD_CNT, "DOUT_DIV_CLK_AUD_CNT", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF4, DIV_CLK_AUD_UAIF4, "DOUT_DIV_CLK_AUD_UAIF4", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF5, DIV_CLK_AUD_UAIF5, "DOUT_DIV_CLK_AUD_UAIF5", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF6, DIV_CLK_AUD_UAIF6, "DOUT_DIV_CLK_AUD_UAIF6", 0, 0, NULL),
|
|
VCLK(DOUT_CLKAUD_HSI0_NOC, CLKAUD_HSI0_NOC, "DOUT_CLKAUD_HSI0_NOC", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_PCMC, DIV_CLK_AUD_PCMC, "DOUT_DIV_CLK_AUD_PCMC", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_AUDIF, DIV_CLK_AUD_AUDIF, "DOUT_DIV_CLK_AUD_AUDIF", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_SERIAL_LIF, DIV_CLK_AUD_SERIAL_LIF, "DOUT_DIV_CLK_AUD_SERIAL_LIF", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_SERIAL_LIF_CORE, DIV_CLK_AUD_SERIAL_LIF_CORE, "DOUT_DIV_CLK_AUD_SERIAL_LIF_CORE", 0, 0, NULL),
|
|
VCLK(DOUT_CLK_AUD_MCLK, CLK_AUD_MCLK, "DOUT_CLK_AUD_MCLK", 0, 0, NULL),
|
|
VCLK(MOUT_CLK_AUD_SERIAL_LIF, MUX_CLK_AUD_SERIAL_LIF, "MOUT_CLK_AUD_SERIAL_LIF", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_cmgp_vclks[] = {
|
|
|
|
VCLK(DOUT_DIV_CLK_CMGP_USI4, DIV_CLK_CMGP_USI4, "DOUT_DIV_CLK_CMGP_USI4", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_USI1, DIV_CLK_CMGP_USI1, "DOUT_DIV_CLK_CMGP_USI1", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_USI0, DIV_CLK_CMGP_USI0, "DOUT_DIV_CLK_CMGP_USI0", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_USI2, DIV_CLK_CMGP_USI2, "DOUT_DIV_CLK_CMGP_USI2", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_USI3, DIV_CLK_CMGP_USI3, "DOUT_DIV_CLK_CMGP_USI3", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_USI5, DIV_CLK_CMGP_USI5, "DOUT_DIV_CLK_CMGP_USI5", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_USI6, DIV_CLK_CMGP_USI6, "DOUT_DIV_CLK_CMGP_USI6", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_I3C, DIV_CLK_CMGP_I3C, "DOUT_DIV_CLK_CMGP_I3C", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_I2C, DIV_CLK_CMGP_I2C, "DOUT_DIV_CLK_CMGP_I2C", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_SPI_MS_CTRL, DIV_CLK_CMGP_SPI_MS_CTRL, "DOUT_DIV_CLK_CMGP_SPI_MS_CTRL", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_SPI_I2C0, DIV_CLK_CMGP_SPI_I2C0, "DOUT_DIV_CLK_CMGP_SPI_I2C0", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_SPI_I2C1, DIV_CLK_CMGP_SPI_I2C1, "DOUT_DIV_CLK_CMGP_SPI_I2C1", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_top_vclks[] = {
|
|
VCLK(DOUT_DIV_CLKCMU_AUD_AUDIF0, DIV_CLKCMU_AUD_AUDIF0, "DOUT_DIV_CLKCMU_AUD_AUDIF0", 0, 0, NULL),
|
|
VCLK(MOUT_MUX_CLKCMU_AUD_AUDIF0, MUX_CLKCMU_AUD_AUDIF0, "MOUT_MUX_CLKCMU_AUD_AUDIF0", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLKCMU_AUD_AUDIF1, DIV_CLKCMU_AUD_AUDIF1, "DOUT_DIV_CLKCMU_AUD_AUDIF1", 0, 0, NULL),
|
|
VCLK(MOUT_MUX_CLKCMU_AUD_AUDIF1, MUX_CLKCMU_AUD_AUDIF1, "MOUT_MUX_CLKCMU_AUD_AUDIF1", 0, 0, NULL),
|
|
|
|
VCLK(DOUT_DIV_CLKCMU_CIS_CLK0, DIV_CLKCMU_CIS_CLK0, "DOUT_DIV_CLKCMU_CIS_CLK0", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLKCMU_CIS_CLK1, DIV_CLKCMU_CIS_CLK1, "DOUT_DIV_CLKCMU_CIS_CLK1", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLKCMU_CIS_CLK2, DIV_CLKCMU_CIS_CLK2, "DOUT_DIV_CLKCMU_CIS_CLK2", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLKCMU_CIS_CLK3, DIV_CLKCMU_CIS_CLK3, "DOUT_DIV_CLKCMU_CIS_CLK3", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLKCMU_CIS_CLK4, DIV_CLKCMU_CIS_CLK4, "DOUT_DIV_CLKCMU_CIS_CLK4", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLKCMU_CIS_CLK5, DIV_CLKCMU_CIS_CLK5, "DOUT_DIV_CLKCMU_CIS_CLK5", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLKCMU_CIS_CLK6, DIV_CLKCMU_CIS_CLK6, "DOUT_DIV_CLKCMU_CIS_CLK6", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLKCMU_CIS_CLK7, DIV_CLKCMU_CIS_CLK7, "DOUT_DIV_CLKCMU_CIS_CLK7", 0, 0, NULL),
|
|
VCLK(POUT_SHARED3_D1, PLL_SHARED3_D1, "POUT_SHARED3_D1", 0, 0, NULL),
|
|
VCLK(POUT_SHARED4_D1, PLL_SHARED4_D1, "POUT_SHARED4_D1", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_hsi0_vclks[] = {
|
|
|
|
VCLK(DOUT_CLKCMU_HSI0_USB32DRD, CLKCMU_HSI0_USB32DRD, "DOUT_CLKCMU_HSI0_USB32DRD", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_HSI0_DPGTC, CLKCMU_HSI0_DPGTC, "DOUT_CLKCMU_HSI0_DPGTC", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_hsi1_vclks[] = {
|
|
|
|
VCLK(DOUT_DIV_CLKCMU_HSI1_MMC_CARD_SM, DIV_CLKCMU_HSI1_MMC_CARD_SM, "DOUT_DIV_CLKCMU_HSI1_MMC_CARD_SM", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_HSI1_UFS_EMBD, CLKCMU_HSI1_UFS_EMBD, "DOUT_CLKCMU_HSI1_UFS_EMBD", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_lme_vclks[] = {
|
|
|
|
VCLK(DOUT_DIV_CLK_LME_NOCP, DIV_CLK_LME_NOCP, "DOUT_DIV_CLK_LME_NOCP", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_m2m_vclks[] = {
|
|
|
|
VCLK(DOUT_DIV_CLK_M2M_NOCP, DIV_CLK_M2M_NOCP, "DOUT_DIV_CLK_M2M_NOCP", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_gnpu_vclks[] = {
|
|
|
|
VCLK(DOUT_DIV_CLK_GNPU_NOC, DIV_CLK_GNPU_NOC, "DOUT_DIV_CLK_GNPU_NOC", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_GNPUP_NOC, DIV_CLK_GNPUP_NOC, "DOUT_DIV_CLK_GNPUP_NOC", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_peric0_vclks[] = {
|
|
|
|
VCLK(DOUT_DIV_CLK_PERIC0_USI04, DIV_CLK_PERIC0_USI04, "DOUT_DIV_CLK_PERIC0_USI04", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC0_I2C, DIV_CLK_PERIC0_I2C, "DOUT_DIV_CLK_PERIC0_I2C", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_peric1_vclks[] = {
|
|
|
|
VCLK(DOUT_DIV_CLK_PERIC1_UART_BT, DIV_CLK_PERIC1_UART_BT, "DOUT_DIV_CLK_PERIC1_UART_BT", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC1_I2C, DIV_CLK_PERIC1_I2C, "DOUT_DIV_CLK_PERIC1_I2C", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC1_USI07, DIV_CLK_PERIC1_USI07, "DOUT_DIV_CLK_PERIC1_USI07", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC1_USI08, DIV_CLK_PERIC1_USI08, "DOUT_DIV_CLK_PERIC1_USI08", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC1_USI09, DIV_CLK_PERIC1_USI09, "DOUT_DIV_CLK_PERIC1_USI09", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC1_USI10, DIV_CLK_PERIC1_USI10, "DOUT_DIV_CLK_PERIC1_USI10", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC1_SPI_MS_CTRL, DIV_CLK_PERIC1_SPI_MS_CTRL, "DOUT_DIV_CLK_PERIC1_SPI_MS_CTRL", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC1_USI07_SPI_I2C, DIV_CLK_PERIC1_USI07_SPI_I2C, "DOUT_DIV_CLK_PERIC1_USI07_SPI_I2C", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC1_USI08_SPI_I2C, DIV_CLK_PERIC1_USI08_SPI_I2C, "DOUT_DIV_CLK_PERIC1_USI08_SPI_I2C", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_peric2_vclks[] = {
|
|
|
|
VCLK(DOUT_DIV_CLK_PERIC2_I2C, DIV_CLK_PERIC2_I2C, "DOUT_DIV_CLK_PERIC2_I2C", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC2_USI00, DIV_CLK_PERIC2_USI00, "DOUT_DIV_CLK_PERIC2_USI00", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC2_USI01, DIV_CLK_PERIC2_USI01, "DOUT_DIV_CLK_PERIC2_USI01", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC2_USI02, DIV_CLK_PERIC2_USI02, "DOUT_DIV_CLK_PERIC2_USI02", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC2_USI03, DIV_CLK_PERIC2_USI03, "DOUT_DIV_CLK_PERIC2_USI03", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC2_USI05, DIV_CLK_PERIC2_USI05, "DOUT_DIV_CLK_PERIC2_USI05", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC2_USI06, DIV_CLK_PERIC2_USI06, "DOUT_DIV_CLK_PERIC2_USI06", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC2_SPI_MS_CTRL, DIV_CLK_PERIC2_SPI_MS_CTRL, "DOUT_DIV_CLK_PERIC2_SPI_MS_CTRL", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC2_USI11, DIV_CLK_PERIC2_USI11, "DOUT_DIV_CLK_PERIC2_USI11", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC2_UART_DBG, DIV_CLK_PERIC2_UART_DBG, "DOUT_DIV_CLK_PERIC2_UART_DBG", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC2_USI00_SPI_I2C, DIV_CLK_PERIC2_USI00_SPI_I2C, "DOUT_DIV_CLK_PERIC2_USI00_SPI_I2C", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERIC2_USI01_SPI_I2C, DIV_CLK_PERIC2_USI01_SPI_I2C, "DOUT_DIV_CLK_PERIC2_USI01_SPI_I2C", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_vts_vclks[] = {
|
|
|
|
VCLK(DOUT_DIV_CLK_VTS_DMIC_IF, DIV_CLK_VTS_DMIC_IF, "DOUT_DIV_CLK_VTS_DMIC_IF", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_VTS_DMIC_IF_DIV2, DIV_CLK_VTS_DMIC_IF_DIV2, "DOUT_DIV_CLK_VTS_DMIC_IF_DIV2", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_VTS_NOC, DIV_CLK_VTS_NOC, "DOUT_DIV_CLK_VTS_NOC", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_VTS_SERIAL_LIF, DIV_CLK_VTS_SERIAL_LIF, "DOUT_DIV_CLK_VTS_SERIAL_LIF", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_VTS_DMIC_AHB, DIV_CLK_VTS_DMIC_AHB, "DOUT_DIV_CLK_VTS_DMIC_AHB", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_VTS_SERIAL_LIF_CORE, DIV_CLK_VTS_SERIAL_LIF_CORE, "DOUT_DIV_CLK_VTS_SERIAL_LIF_CORE", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_VTS_CPU, DIV_CLK_VTS_CPU, "DOUT_DIV_CLK_VTS_CPU", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLKVTS_AUD_DMIC0, DIV_CLKVTS_AUD_DMIC0, "DOUT_DIV_CLKVTS_AUD_DMIC0", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLKVTS_AUD_DMIC1, DIV_CLKVTS_AUD_DMIC1, "DOUT_DIV_CLKVTS_AUD_DMIC1", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_VTS_DMAILBOX_CCLK, DIV_CLK_VTS_DMAILBOX_CCLK, "DOUT_DIV_CLK_VTS_DMAILBOX_CCLK", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e9925_yuvp_vclks[] = {
|
|
|
|
VCLK(DOUT_DIV_CLK_YUVP_NOCP, DIV_CLK_YUVP_NOCP, "DOUT_DIV_CLK_YUVP_NOCP", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_YUVP_NOC, DIV_CLK_YUVP_NOC, "DOUT_DIV_CLK_YUVP_NOC", 0, 0, NULL),
|
|
};
|
|
|
|
static struct init_vclk s5e9925_clkout_vclks[] = {
|
|
VCLK(OSC_AUD, VCLK_CLKOUT0, "OSC_AUD", 0, 0, NULL),
|
|
};
|
|
|
|
static struct of_device_id ext_clk_match[] = {
|
|
{.compatible = "samsung,s5e9925-oscclk", .data = (void *)0},
|
|
{},
|
|
};
|
|
|
|
void s5e9925_vclk_init(void)
|
|
{
|
|
/* Common clock init */
|
|
}
|
|
|
|
/* register s5e9925 clocks */
|
|
static int s5e9925_clock_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
void __iomem *reg_base;
|
|
|
|
if (np) {
|
|
reg_base = of_iomap(np, 0);
|
|
if (!reg_base)
|
|
panic("%s: failed to map registers\n", __func__);
|
|
} else {
|
|
panic("%s: unable to determine soc\n", __func__);
|
|
}
|
|
|
|
s5e9925_clk_provider = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
|
|
if (!s5e9925_clk_provider)
|
|
panic("%s: unable to allocate context.\n", __func__);
|
|
|
|
samsung_register_of_fixed_ext(s5e9925_clk_provider, s5e9925_fixed_rate_ext_clks,
|
|
ARRAY_SIZE(s5e9925_fixed_rate_ext_clks),
|
|
ext_clk_match);
|
|
|
|
/* register HWACG vclk */
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_alive_hwacg_vclks, ARRAY_SIZE(s5e9925_alive_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_nocl1c_hwacg_vclks, ARRAY_SIZE(s5e9925_nocl1c_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_cmgp_hwacg_vclks, ARRAY_SIZE(s5e9925_cmgp_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_top_hwacg_vclks, ARRAY_SIZE(s5e9925_top_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_nocl0_hwacg_vclks, ARRAY_SIZE(s5e9925_nocl0_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_dpub_hwacg_vclks, ARRAY_SIZE(s5e9925_dpub_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_dpuf0_hwacg_vclks, ARRAY_SIZE(s5e9925_dpuf0_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_dpuf1_hwacg_vclks, ARRAY_SIZE(s5e9925_dpuf1_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_hsi0_hwacg_vclks, ARRAY_SIZE(s5e9925_hsi0_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_hsi1_hwacg_vclks, ARRAY_SIZE(s5e9925_hsi1_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_mif_hwacg_vclks, ARRAY_SIZE(s5e9925_mif_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_peric0_hwacg_vclks, ARRAY_SIZE(s5e9925_peric0_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_peric1_hwacg_vclks, ARRAY_SIZE(s5e9925_peric1_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_peric2_hwacg_vclks, ARRAY_SIZE(s5e9925_peric2_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_peris_hwacg_vclks, ARRAY_SIZE(s5e9925_peris_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_ssp_hwacg_vclks, ARRAY_SIZE(s5e9925_ssp_hwacg_vclks));
|
|
|
|
/* register special vclk */
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_alive_vclks, ARRAY_SIZE(s5e9925_alive_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_cmgp_vclks, ARRAY_SIZE(s5e9925_cmgp_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_top_vclks, ARRAY_SIZE(s5e9925_top_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_hsi0_vclks, ARRAY_SIZE(s5e9925_hsi0_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_hsi1_vclks, ARRAY_SIZE(s5e9925_hsi1_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_peric0_vclks, ARRAY_SIZE(s5e9925_peric0_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_peric1_vclks, ARRAY_SIZE(s5e9925_peric1_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_peric2_vclks, ARRAY_SIZE(s5e9925_peric2_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_clkout_vclks, ARRAY_SIZE(s5e9925_clkout_vclks));
|
|
|
|
clk_exynos_skip_hw = true;
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_g3d_hwacg_vclks, ARRAY_SIZE(s5e9925_g3d_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_aud_hwacg_vclks, ARRAY_SIZE(s5e9925_aud_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_nocl1a_hwacg_vclks, ARRAY_SIZE(s5e9925_nocl1a_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_nocl1b_hwacg_vclks, ARRAY_SIZE(s5e9925_nocl1b_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_csis_hwacg_vclks, ARRAY_SIZE(s5e9925_csis_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_dnc_hwacg_vclks, ARRAY_SIZE(s5e9925_dnc_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_dsu_hwacg_vclks, ARRAY_SIZE(s5e9925_dsu_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_lme_hwacg_vclks, ARRAY_SIZE(s5e9925_lme_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_m2m_hwacg_vclks, ARRAY_SIZE(s5e9925_m2m_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_mcfp_hwacg_vclks, ARRAY_SIZE(s5e9925_mcfp_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_mcsc_hwacg_vclks, ARRAY_SIZE(s5e9925_mcsc_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_mfc0_hwacg_vclks, ARRAY_SIZE(s5e9925_mfc0_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_mfc1_hwacg_vclks, ARRAY_SIZE(s5e9925_mfc1_hwacg_vclks));
|
|
samsung_register_vclk(s5e9925_clk_provider, s5e9925_gnpu_hwacg_vclks, ARRAY_SIZE(s5e9925_gnpu_hwacg_vclks));
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samsung_register_vclk(s5e9925_clk_provider, s5e9925_s2d_hwacg_vclks, ARRAY_SIZE(s5e9925_s2d_hwacg_vclks));
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samsung_register_vclk(s5e9925_clk_provider, s5e9925_vts_hwacg_vclks, ARRAY_SIZE(s5e9925_vts_hwacg_vclks));
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samsung_register_vclk(s5e9925_clk_provider, s5e9925_vts_vclks, ARRAY_SIZE(s5e9925_vts_vclks));
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samsung_register_vclk(s5e9925_clk_provider, s5e9925_yuvp_hwacg_vclks, ARRAY_SIZE(s5e9925_yuvp_hwacg_vclks));
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samsung_register_vclk(s5e9925_clk_provider, s5e9925_cstat_hwacg_vclks, ARRAY_SIZE(s5e9925_cstat_hwacg_vclks));
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samsung_register_vclk(s5e9925_clk_provider, s5e9925_dsp_hwacg_vclks, ARRAY_SIZE(s5e9925_dsp_hwacg_vclks));
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samsung_register_vclk(s5e9925_clk_provider, s5e9925_sdma_hwacg_vclks, ARRAY_SIZE(s5e9925_sdma_hwacg_vclks));
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samsung_register_vclk(s5e9925_clk_provider, s5e9925_ufd_hwacg_vclks, ARRAY_SIZE(s5e9925_ufd_hwacg_vclks));
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samsung_register_vclk(s5e9925_clk_provider, s5e9925_aud_vclks, ARRAY_SIZE(s5e9925_aud_vclks));
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samsung_register_vclk(s5e9925_clk_provider, s5e9925_lme_vclks, ARRAY_SIZE(s5e9925_lme_vclks));
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samsung_register_vclk(s5e9925_clk_provider, s5e9925_m2m_vclks, ARRAY_SIZE(s5e9925_m2m_vclks));
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samsung_register_vclk(s5e9925_clk_provider, s5e9925_gnpu_vclks, ARRAY_SIZE(s5e9925_gnpu_vclks));
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clk_exynos_skip_hw = false;
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|
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clk_register_fixed_factor(NULL, "pwm-clock", "fin_pll", CLK_SET_RATE_PARENT, 1, 1);
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|
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samsung_clk_of_add_provider(np, s5e9925_clk_provider);
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|
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s5e9925_vclk_init();
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|
|
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pr_info("S5E9925: Clock setup completed\n");
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return 0;
|
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}
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|
|
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static const struct of_device_id of_exynos_clock_match[] = {
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{ .compatible = "samsung,s5e9925-clock", },
|
|
{ },
|
|
};
|
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MODULE_DEVICE_TABLE(of, of_exynos_clock_match);
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|
|
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static const struct platform_device_id exynos_clock_ids[] = {
|
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{ "s5e9925-clock", },
|
|
{ }
|
|
};
|
|
|
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static struct platform_driver s5e9925_clock_driver = {
|
|
.driver = {
|
|
.name = "s5e9925_clock",
|
|
.of_match_table = of_exynos_clock_match,
|
|
},
|
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.probe = s5e9925_clock_probe,
|
|
.id_table = exynos_clock_ids,
|
|
};
|
|
|
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static int s5e9925_clock_init(void)
|
|
{
|
|
return platform_driver_register(&s5e9925_clock_driver);
|
|
}
|
|
arch_initcall(s5e9925_clock_init);
|
|
|
|
static void s5e9925_clock_exit(void)
|
|
{
|
|
return platform_driver_unregister(&s5e9925_clock_driver);
|
|
}
|
|
module_exit(s5e9925_clock_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|