1108 lines
94 KiB
C
Executable file
1108 lines
94 KiB
C
Executable file
/*
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* Copyright (c) 2018 Samsung Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Common Clock Framework support for s5e8825 SoC.
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <soc/samsung/cal-if.h>
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#include <dt-bindings/clock/s5e8825.h>
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#include "../../soc/samsung/cal-if/s5e8825/cmucal/cmucal-vclk.h"
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#include "../../soc/samsung/cal-if/s5e8825/cmucal/cmucal-node.h"
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#include "../../soc/samsung/cal-if/s5e8825/cmucal/cmucal-qch.h"
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#include "../../soc/samsung/cal-if/s5e8825/cmucal/clkout_s5e8825.h"
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#include "composite.h"
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bool clk_exynos_skip_hw;
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static struct samsung_clk_provider *s5e8825_clk_provider;
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/*
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* list of controller registers to be saved and restored during a
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* suspend/resume cycle.
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*/
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/* fixed rate clocks generated outside the soc */
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struct samsung_fixed_rate s5e8825_fixed_rate_ext_clks[] = {
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FRATE(OSCCLK, "fin_pll", NULL, 0, 26000000),
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};
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/* HWACG VCLK */
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//ALIVE
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struct init_vclk s5e8825_alive_hwacg_vclks[] = {
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HWACG_VCLK(GATE_ALIVE_CMU_ALIVE_QCH, ALIVE_CMU_ALIVE_QCH, "GATE_ALIVE_CMU_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APBIF_CHUB_RTC_QCH, APBIF_CHUB_RTC_QCH, "GATE_APBIF_CHUB_RTC_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APBIF_GPIO_ALIVE_QCH, APBIF_GPIO_ALIVE_QCH, "GATE_APBIF_GPIO_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APBIF_PMU_ALIVE_QCH, APBIF_PMU_ALIVE_QCH, "GATE_APBIF_PMU_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APBIF_RTC_QCH, APBIF_RTC_QCH, "GATE_APBIF_RTC_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APBIF_SYSREG_VGPIO2AP_QCH, APBIF_SYSREG_VGPIO2AP_QCH, "GATE_APBIF_SYSREG_VGPIO2AP_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APBIF_SYSREG_VGPIO2APM_QCH, APBIF_SYSREG_VGPIO2APM_QCH, "GATE_APBIF_SYSREG_VGPIO2APM_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APBIF_SYSREG_VGPIO2PMU_QCH, APBIF_SYSREG_VGPIO2PMU_QCH, "GATE_APBIF_SYSREG_VGPIO2PMU_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_APBIF_TOP_RTC_QCH, APBIF_TOP_RTC_QCH, "GATE_APBIF_TOP_RTC_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_DBGCORE_UART_QCH, DBGCORE_UART_QCH, "GATE_DBGCORE_UART_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_D_TZPC_ALIVE_QCH, D_TZPC_ALIVE_QCH, "GATE_D_TZPC_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_GREBEINTEGRATION_QCH_GREBE, GREBEINTEGRATION_QCH_GREBE, "GATE_GREBEINTEGRATION_QCH_GREBE", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_GREBEINTEGRATION_QCH_DBG, GREBEINTEGRATION_QCH_DBG, "GATE_GREBEINTEGRATION_QCH_DBG", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_HW_SCANDUMP_CLKSTOP_CTRL_QCH, HW_SCANDUMP_CLKSTOP_CTRL_QCH, "GATE_HW_SCANDUMP_CLKSTOP_CTRL_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_I2C_ALIVE0_QCH, I2C_ALIVE0_QCH, "GATE_I2C_ALIVE0_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_I3C_APM_PMIC_QCH_P, I3C_APM_PMIC_QCH_P, "GATE_I3C_APM_PMIC_QCH_P", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_I3C_APM_PMIC_QCH_S, I3C_APM_PMIC_QCH_S, "GATE_I3C_APM_PMIC_QCH_S", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_INTMEM_QCH, INTMEM_QCH, "GATE_INTMEM_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_APM_AP_QCH, MAILBOX_APM_AP_QCH, "GATE_MAILBOX_APM_AP_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_APM_CHUB_QCH, MAILBOX_APM_CHUB_QCH, "GATE_MAILBOX_APM_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_APM_CP_QCH, MAILBOX_APM_CP_QCH, "GATE_MAILBOX_APM_CP_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_APM_GNSS_QCH, MAILBOX_APM_GNSS_QCH, "GATE_MAILBOX_APM_GNSS_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_APM_VTS_QCH, MAILBOX_APM_VTS_QCH, "GATE_MAILBOX_APM_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_APM_WLBT_QCH, MAILBOX_APM_WLBT_QCH, "GATE_MAILBOX_APM_WLBT_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AP_CHUB_QCH, MAILBOX_AP_CHUB_QCH, "GATE_MAILBOX_AP_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AP_CP_QCH, MAILBOX_AP_CP_QCH, "GATE_MAILBOX_AP_CP_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AP_CP_S_QCH, MAILBOX_AP_CP_S_QCH, "GATE_MAILBOX_AP_CP_S_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AP_DBGCORE_QCH, MAILBOX_AP_DBGCORE_QCH, "GATE_MAILBOX_AP_DBGCORE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AP_GNSS_QCH, MAILBOX_AP_GNSS_QCH, "GATE_MAILBOX_AP_GNSS_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AP_WLBT_BT_QCH, MAILBOX_AP_WLBT_BT_QCH, "GATE_MAILBOX_AP_WLBT_BT_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AP_WLBT_WL_QCH, MAILBOX_AP_WLBT_WL_QCH, "GATE_MAILBOX_AP_WLBT_WL_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_CP_CHUB_QCH, MAILBOX_CP_CHUB_QCH, "GATE_MAILBOX_CP_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_CP_GNSS_QCH, MAILBOX_CP_GNSS_QCH, "GATE_MAILBOX_CP_GNSS_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_CP_WLBT_BT_QCH, MAILBOX_CP_WLBT_BT_QCH, "GATE_MAILBOX_CP_WLBT_BT_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_CP_WLBT_WL_QCH, MAILBOX_CP_WLBT_WL_QCH, "GATE_MAILBOX_CP_WLBT_WL_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_GNSS_CHUB_QCH, MAILBOX_GNSS_CHUB_QCH, "GATE_MAILBOX_GNSS_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_GNSS_WLBT_QCH, MAILBOX_GNSS_WLBT_QCH, "GATE_MAILBOX_GNSS_WLBT_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_SHARED_SRAM_QCH, MAILBOX_SHARED_SRAM_QCH, "GATE_MAILBOX_SHARED_SRAM_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_VTS_CHUB_QCH, MAILBOX_VTS_CHUB_QCH, "GATE_MAILBOX_VTS_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_WLBT_ABOX_QCH, MAILBOX_WLBT_ABOX_QCH, "GATE_MAILBOX_WLBT_ABOX_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_WLBT_CHUB_QCH, MAILBOX_WLBT_CHUB_QCH, "GATE_MAILBOX_WLBT_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_PMU_INTR_GEN_QCH, PMU_INTR_GEN_QCH, "GATE_PMU_INTR_GEN_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ROM_CRC32_HOST_QCH, ROM_CRC32_HOST_QCH, "GATE_ROM_CRC32_HOST_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_RSTNSYNC_CLK_ALIVE_GREBE_QCH, RSTNSYNC_CLK_ALIVE_GREBE_QCH, "GATE_RSTNSYNC_CLK_ALIVE_GREBE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH, RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH, "GATE_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_MI_C_CHUBVTS_QCH, SLH_AXI_MI_C_CHUBVTS_QCH, "GATE_SLH_AXI_MI_C_CHUBVTS_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_MI_C_GNSS_QCH, SLH_AXI_MI_C_GNSS_QCH, "GATE_SLH_AXI_MI_C_GNSS_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_MI_C_MODEM_QCH, SLH_AXI_MI_C_MODEM_QCH, "GATE_SLH_AXI_MI_C_MODEM_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_MI_C_WLBT_QCH, SLH_AXI_MI_C_WLBT_QCH, "GATE_SLH_AXI_MI_C_WLBT_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_MI_P_APM_QCH, SLH_AXI_MI_P_APM_QCH, "GATE_SLH_AXI_MI_P_APM_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_SI_C_CMGP_QCH, SLH_AXI_SI_C_CMGP_QCH, "GATE_SLH_AXI_SI_C_CMGP_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_SI_D_APM_QCH, SLH_AXI_SI_D_APM_QCH, "GATE_SLH_AXI_SI_D_APM_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_SI_G_DBGCORE_QCH, SLH_AXI_SI_G_DBGCORE_QCH, "GATE_SLH_AXI_SI_G_DBGCORE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_SI_G_SCAN2DRAM_QCH, SLH_AXI_SI_G_SCAN2DRAM_QCH, "GATE_SLH_AXI_SI_G_SCAN2DRAM_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_SI_LP_CHUBVTS_QCH, SLH_AXI_SI_LP_CHUBVTS_QCH, "GATE_SLH_AXI_SI_LP_CHUBVTS_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SS_DBGCORE_QCH_GREBE, SS_DBGCORE_QCH_GREBE, "GATE_SS_DBGCORE_QCH_GREBE", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SS_DBGCORE_QCH_DBG, SS_DBGCORE_QCH_DBG, "GATE_SS_DBGCORE_QCH_DBG", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SYSREG_ALIVE_QCH, SYSREG_ALIVE_QCH, "GATE_SYSREG_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_USI_ALIVE0_QCH, USI_ALIVE0_QCH, "GATE_USI_ALIVE0_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_VGEN_LITE_ALIVE_QCH, VGEN_LITE_ALIVE_QCH, "GATE_VGEN_LITE_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_WDT_ALIVE_QCH, WDT_ALIVE_QCH, "GATE_WDT_ALIVE_QCH", NULL, 0, VCLK_GATE, NULL),
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};
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//AUD
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struct init_vclk s5e8825_aud_hwacg_vclks[] = {
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HWACG_VCLK(UMUX_CLK_AUD_CPU_PLL, MUX_CLK_AUD_CPU_PLL, "UMUX_CLK_AUD_CPU_PLL", NULL, 0, 0, NULL),
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HWACG_VCLK(UMUX_CLKCMU_AUD_CPU_USER, MUX_CLKCMU_AUD_CPU_USER, "UMUX_CLKCMU_AUD_CPU_USER", NULL, 0, 0, NULL),
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HWACG_VCLK(UMUX_CLKCMU_AUD_BUS_USER, MUX_CLKCMU_AUD_BUS_USER, "UMUX_CLKCMU_AUD_BUS_USER", NULL, 0, 0, NULL),
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HWACG_VCLK(UMUX_CP_PCMC_CLK_USER, MUX_CP_PCMC_CLK_USER, "UMUX_CP_PCMC_CLK_USER", NULL, 0, 0, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_ACLK, ABOX_QCH_ACLK, "GATE_ABOX_QCH_ACLK", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK_DSIF, ABOX_QCH_BCLK_DSIF, "GATE_ABOX_QCH_BCLK_DSIF", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK0, ABOX_QCH_BCLK0, "GATE_ABOX_QCH_BCLK0", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK1, ABOX_QCH_BCLK1, "GATE_ABOX_QCH_BCLK1", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK2, ABOX_QCH_BCLK2, "GATE_ABOX_QCH_BCLK2", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK3, ABOX_QCH_BCLK3, "GATE_ABOX_QCH_BCLK3", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK4, ABOX_QCH_BCLK4, "GATE_ABOX_QCH_BCLK4", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_CNT, ABOX_QCH_CNT, "GATE_ABOX_QCH_CNT", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_CCLK_ASB, ABOX_QCH_CCLK_ASB, "GATE_ABOX_QCH_CCLK_ASB", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK5, ABOX_QCH_BCLK5, "GATE_ABOX_QCH_BCLK5", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_BCLK6, ABOX_QCH_BCLK6, "GATE_ABOX_QCH_BCLK6", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_CPU, ABOX_QCH_CPU, "GATE_ABOX_QCH_CPU", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_PCMC_CLK, ABOX_QCH_PCMC_CLK, "GATE_ABOX_QCH_PCMC_CLK", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_C2A0, ABOX_QCH_C2A0, "GATE_ABOX_QCH_C2A0", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_C2A1, ABOX_QCH_C2A1, "GATE_ABOX_QCH_C2A1", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_XCLK0, ABOX_QCH_XCLK0, "GATE_ABOX_QCH_XCLK0", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_XCLK1, ABOX_QCH_XCLK1, "GATE_ABOX_QCH_XCLK1", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_XCLK2, ABOX_QCH_XCLK2, "GATE_ABOX_QCH_XCLK2", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_CPU0, ABOX_QCH_CPU0, "GATE_ABOX_QCH_CPU0", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_CPU1, ABOX_QCH_CPU1, "GATE_ABOX_QCH_CPU1", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_NEON0, ABOX_QCH_NEON0, "GATE_ABOX_QCH_NEON0", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_NEON1, ABOX_QCH_NEON1, "GATE_ABOX_QCH_NEON1", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_L2, ABOX_QCH_L2, "GATE_ABOX_QCH_L2", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_ABOX_QCH_CCLK_ACP, ABOX_QCH_CCLK_ACP, "GATE_ABOX_QCH_CCLK_ACP", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_AUD_CMU_AUD_QCH, AUD_CMU_AUD_QCH, "GATE_AUD_CMU_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_DFTMUX_AUD_QCH, DFTMUX_AUD_QCH, "GATE_DFTMUX_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_D_TZPC_AUD_QCH, D_TZPC_AUD_QCH, "GATE_D_TZPC_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_LH_AXI_SI_D_AUD_QCH, LH_AXI_SI_D_AUD_QCH, "GATE_LH_AXI_SI_D_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AUD0_QCH, MAILBOX_AUD0_QCH, "GATE_MAILBOX_AUD0_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_MAILBOX_AUD1_QCH, MAILBOX_AUD1_QCH, "GATE_MAILBOX_AUD1_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_PPMU_AUD_QCH, PPMU_AUD_QCH, "GATE_PPMU_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH, RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH, RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH, RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH, "GATE_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_MI_D_USBAUD_QCH, SLH_AXI_MI_D_USBAUD_QCH, "GATE_SLH_AXI_MI_D_USBAUD_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_MI_P_AUD_QCH, SLH_AXI_MI_P_AUD_QCH, "GATE_SLH_AXI_MI_P_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SYSMMU_AUD_QCH_S1, SYSMMU_AUD_QCH_S1, "GATE_SYSMMU_AUD_QCH_S1", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SYSMMU_AUD_QCH_S2, SYSMMU_AUD_QCH_S2, "GATE_SYSMMU_AUD_QCH_S2", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SYSREG_AUD_QCH, SYSREG_AUD_QCH, "GATE_SYSREG_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_AUD_QCH, VGEN_LITE_AUD_QCH, "GATE_VGEN_LITE_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_WDT_AUD_QCH, WDT_AUD_QCH, "GATE_WDT_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
//BUSC
|
|
struct init_vclk s5e8825_busc_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_BUSC_CMU_BUSC_QCH, BUSC_CMU_BUSC_QCH, "GATE_BUSC_CMU_BUSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CMU_BUSC_CMUREF_QCH, CMU_BUSC_CMUREF_QCH, "GATE_CMU_BUSC_CMUREF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_BUSC_QCH, D_TZPC_BUSC_QCH, "GATE_D_TZPC_BUSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D_CHUBVTS_QCH, LH_AXI_MI_D_CHUBVTS_QCH, "GATE_LH_AXI_MI_D_CHUBVTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D_MFC_QCH, LH_AXI_MI_D_MFC_QCH, "GATE_LH_AXI_MI_D_MFC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PDMA_BUSC_QCH, PDMA_BUSC_QCH, "GATE_PDMA_BUSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_D_APM_QCH, SLH_AXI_MI_D_APM_QCH, "GATE_SLH_AXI_MI_D_APM_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_D_PERI_QCH, SLH_AXI_MI_D_PERI_QCH, "GATE_SLH_AXI_MI_D_PERI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_D_USB_QCH, SLH_AXI_MI_D_USB_QCH, "GATE_SLH_AXI_MI_D_USB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_BUSC_QCH, SLH_AXI_MI_P_BUSC_QCH, "GATE_SLH_AXI_MI_P_BUSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SPDMA_BUSC_QCH, SPDMA_BUSC_QCH, "GATE_SPDMA_BUSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_AXI_D_BUSC_QCH, SYSMMU_AXI_D_BUSC_QCH, "GATE_SYSMMU_AXI_D_BUSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_BUSC_QCH, SYSREG_BUSC_QCH, "GATE_SYSREG_BUSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TREX_D_BUSC_QCH, TREX_D_BUSC_QCH, "GATE_TREX_D_BUSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_PDMA_QCH, VGEN_PDMA_QCH, "GATE_VGEN_PDMA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_SPDMA_QCH, VGEN_SPDMA_QCH, "GATE_VGEN_SPDMA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
//CHUB
|
|
struct init_vclk s5e8825_chub_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH, APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH, "GATE_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_APBIF_GPIO_CHUB_QCH, APBIF_GPIO_CHUB_QCH, "GATE_APBIF_GPIO_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_APBIF_GPIO_CHUBEINT_QCH, APBIF_GPIO_CHUBEINT_QCH, "GATE_APBIF_GPIO_CHUBEINT_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CHUB_CMU_CHUB_QCH, CHUB_CMU_CHUB_QCH, "GATE_CHUB_CMU_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CM4_CHUB_QCH_CPU, CM4_CHUB_QCH_CPU, "GATE_CM4_CHUB_QCH_CPU", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I2C_CHUB1_QCH, I2C_CHUB1_QCH, "GATE_I2C_CHUB1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I2C_CHUB3_QCH, I2C_CHUB3_QCH, "GATE_I2C_CHUB3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PWM_CHUB_QCH, PWM_CHUB_QCH, "GATE_PWM_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_S_CHUB_QCH, SLH_AXI_MI_S_CHUB_QCH, "GATE_SLH_AXI_MI_S_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_M_CHUB_QCH, SLH_AXI_SI_M_CHUB_QCH, "GATE_SLH_AXI_SI_M_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CHUB_QCH, SYSREG_CHUB_QCH, "GATE_SYSREG_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_COMBINE_CHUB2AP_QCH, SYSREG_COMBINE_CHUB2AP_QCH, "GATE_SYSREG_COMBINE_CHUB2AP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_COMBINE_CHUB2APM_QCH, SYSREG_COMBINE_CHUB2APM_QCH, "GATE_SYSREG_COMBINE_CHUB2APM_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_COMBINE_CHUB2WLBT_QCH, SYSREG_COMBINE_CHUB2WLBT_QCH, "GATE_SYSREG_COMBINE_CHUB2WLBT_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TIMER_CHUB_QCH, TIMER_CHUB_QCH, "GATE_TIMER_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CHUB0_QCH, USI_CHUB0_QCH, "GATE_USI_CHUB0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CHUB1_QCH, USI_CHUB1_QCH, "GATE_USI_CHUB1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CHUB2_QCH, USI_CHUB2_QCH, "GATE_USI_CHUB2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CHUB3_QCH, USI_CHUB3_QCH, "GATE_USI_CHUB3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_WDT_CHUB_QCH, WDT_CHUB_QCH, "GATE_WDT_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BAAW_CHUB_QCH, BAAW_CHUB_QCH, "GATE_BAAW_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BAAW_VTS_QCH, BAAW_VTS_QCH, "GATE_BAAW_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CHUBVTS_CMU_CHUBVTS_QCH, CHUBVTS_CMU_CHUBVTS_QCH, "GATE_CHUBVTS_CMU_CHUBVTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_CHUBVTS_QCH, D_TZPC_CHUBVTS_QCH, "GATE_D_TZPC_CHUBVTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D_CHUBVTS_QCH, LH_AXI_SI_D_CHUBVTS_QCH, "GATE_LH_AXI_SI_D_CHUBVTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_LP_CHUBVTS_QCH, SLH_AXI_MI_LP_CHUBVTS_QCH, "GATE_SLH_AXI_MI_LP_CHUBVTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_M_CHUB_QCH, SLH_AXI_MI_M_CHUB_QCH, "GATE_SLH_AXI_MI_M_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_M_VTS_QCH, SLH_AXI_MI_M_VTS_QCH, "GATE_SLH_AXI_MI_M_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_C_CHUBVTS_QCH, SLH_AXI_SI_C_CHUBVTS_QCH, "GATE_SLH_AXI_SI_C_CHUBVTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_S_CHUB_QCH, SLH_AXI_SI_S_CHUB_QCH, "GATE_SLH_AXI_SI_S_CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_S_VTS_QCH, SLH_AXI_SI_S_VTS_QCH, "GATE_SLH_AXI_SI_S_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SWEEPER_C_CHUBVTS_QCH, SWEEPER_C_CHUBVTS_QCH, "GATE_SWEEPER_C_CHUBVTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CHUBVTS_QCH, SYSREG_CHUBVTS_QCH, "GATE_SYSREG_CHUBVTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_CHUBVTS_QCH, VGEN_LITE_CHUBVTS_QCH, "GATE_VGEN_LITE_CHUBVTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
//CMGP
|
|
struct init_vclk s5e8825_cmgp_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_CMGP_CMU_CMGP_QCH, CMGP_CMU_CMGP_QCH, "GATE_CMGP_CMU_CMGP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_CMGP_QCH, D_TZPC_CMGP_QCH, "GATE_D_TZPC_CMGP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPIO_CMGP_QCH, GPIO_CMGP_QCH, "GATE_GPIO_CMGP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I2C_CMGP0_QCH, I2C_CMGP0_QCH, "GATE_I2C_CMGP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I2C_CMGP1_QCH, I2C_CMGP1_QCH, "GATE_I2C_CMGP1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I2C_CMGP2_QCH, I2C_CMGP2_QCH, "GATE_I2C_CMGP2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I2C_CMGP3_QCH, I2C_CMGP3_QCH, "GATE_I2C_CMGP3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I2C_CMGP4_QCH, I2C_CMGP4_QCH, "GATE_I2C_CMGP4_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I3C_CMGP_QCH_P, I3C_CMGP_QCH_P, "GATE_I3C_CMGP_QCH_P", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_I3C_CMGP_QCH_S, I3C_CMGP_QCH_S, "GATE_I3C_CMGP_QCH_S", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_C_CMGP_QCH, SLH_AXI_MI_C_CMGP_QCH, "GATE_SLH_AXI_MI_C_CMGP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CMGP_QCH, SYSREG_CMGP_QCH, "GATE_SYSREG_CMGP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CMGP2APM_QCH, SYSREG_CMGP2APM_QCH, "GATE_SYSREG_CMGP2APM_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CMGP2CHUB_QCH, SYSREG_CMGP2CHUB_QCH, "GATE_SYSREG_CMGP2CHUB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CMGP2CP_QCH, SYSREG_CMGP2CP_QCH, "GATE_SYSREG_CMGP2CP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CMGP2GNSS_QCH, SYSREG_CMGP2GNSS_QCH, "GATE_SYSREG_CMGP2GNSS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CMGP2PMU_AP_QCH, SYSREG_CMGP2PMU_AP_QCH, "GATE_SYSREG_CMGP2PMU_AP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CMGP2WLBT_QCH, SYSREG_CMGP2WLBT_QCH, "GATE_SYSREG_CMGP2WLBT_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CMGP0_QCH, USI_CMGP0_QCH, "GATE_USI_CMGP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CMGP1_QCH, USI_CMGP1_QCH, "GATE_USI_CMGP1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CMGP2_QCH, USI_CMGP2_QCH, "GATE_USI_CMGP2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CMGP3_QCH, USI_CMGP3_QCH, "GATE_USI_CMGP3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI_CMGP4_QCH, USI_CMGP4_QCH, "GATE_USI_CMGP4_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
//TOP
|
|
struct init_vclk s5e8825_top_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_CMU_CMU_CMUREF_QCH, CMU_CMU_CMUREF_QCH, "GATE_CMU_CMU_CMUREF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_TOP_QCH_CIS_CLK0, DFTMUX_TOP_QCH_CIS_CLK0, "GATE_DFTMUX_TOP_QCH_CIS_CLK0", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_TOP_QCH_CIS_CLK1, DFTMUX_TOP_QCH_CIS_CLK1, "GATE_DFTMUX_TOP_QCH_CIS_CLK1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_TOP_QCH_CIS_CLK2, DFTMUX_TOP_QCH_CIS_CLK2, "GATE_DFTMUX_TOP_QCH_CIS_CLK2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_TOP_QCH_CIS_CLK3, DFTMUX_TOP_QCH_CIS_CLK3, "GATE_DFTMUX_TOP_QCH_CIS_CLK3", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_TOP_QCH_CIS_CLK4, DFTMUX_TOP_QCH_CIS_CLK4, "GATE_DFTMUX_TOP_QCH_CIS_CLK4", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DFTMUX_TOP_QCH_CIS_CLK5, DFTMUX_TOP_QCH_CIS_CLK5, "GATE_DFTMUX_TOP_QCH_CIS_CLK5", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_OTP_QCH, OTP_QCH, "GATE_OTP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
// CORE
|
|
struct init_vclk s5e8825_core_hwacg_vclks[] = {
|
|
|
|
HWACG_VCLK(GATE_ADM_APB_G_BDU_QCH, ADM_APB_G_BDU_QCH, "GATE_ADM_APB_G_BDU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BAAW_D_SSS_QCH, BAAW_D_SSS_QCH, "GATE_BAAW_D_SSS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BAAW_P_GNSS_QCH, BAAW_P_GNSS_QCH, "GATE_BAAW_P_GNSS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BAAW_P_MODEM_QCH, BAAW_P_MODEM_QCH, "GATE_BAAW_P_MODEM_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BAAW_P_WLBT_QCH, BAAW_P_WLBT_QCH, "GATE_BAAW_P_WLBT_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_BDU_QCH, BDU_QCH, "GATE_BDU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CMU_CORE_CMUREF_QCH, CMU_CORE_CMUREF_QCH, "GATE_CMU_CORE_CMUREF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CORE_CMU_CORE_QCH, CORE_CMU_CORE_QCH, "GATE_CORE_CMU_CORE_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DIT_QCH, DIT_QCH, "GATE_DIT_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_CORE_QCH, D_TZPC_CORE_QCH, "GATE_D_TZPC_CORE_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GIC_QCH, GIC_QCH, "GATE_GIC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HW_APBSEMA_MEC_QCH, HW_APBSEMA_MEC_QCH, "GATE_HW_APBSEMA_MEC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_G_CPU_QCH, LH_AST_MI_G_CPU_QCH, "GATE_LH_AST_MI_G_CPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D0_DPU_QCH, LH_AXI_MI_D0_DPU_QCH, "GATE_LH_AXI_MI_D0_DPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D0_NPUS_QCH, LH_AXI_MI_D0_NPUS_QCH, "GATE_LH_AXI_MI_D0_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D1_DPU_QCH, LH_AXI_MI_D1_DPU_QCH, "GATE_LH_AXI_MI_D1_DPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D1_NPUS_QCH, LH_AXI_MI_D1_NPUS_QCH, "GATE_LH_AXI_MI_D1_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D_AUD_QCH, LH_AXI_MI_D_AUD_QCH, "GATE_LH_AXI_MI_D_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D_G3D_QCH, LH_AXI_MI_D_G3D_QCH, "GATE_LH_AXI_MI_D_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D_M2M_QCH, LH_AXI_MI_D_M2M_QCH, "GATE_LH_AXI_MI_D_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D_SSS_QCH, LH_AXI_MI_D_SSS_QCH, "GATE_LH_AXI_MI_D_SSS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D0_MIF_CP_QCH, LH_AXI_SI_D0_MIF_CP_QCH, "GATE_LH_AXI_SI_D0_MIF_CP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D0_MIF_NRT_QCH, LH_AXI_SI_D0_MIF_NRT_QCH, "GATE_LH_AXI_SI_D0_MIF_NRT_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D0_MIF_RT_QCH, LH_AXI_SI_D0_MIF_RT_QCH, "GATE_LH_AXI_SI_D0_MIF_RT_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D1_MIF_CP_QCH, LH_AXI_SI_D1_MIF_CP_QCH, "GATE_LH_AXI_SI_D1_MIF_CP_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_LH_AXI_SI_D1_MIF_NRT_QCH, LH_AXI_SI_D1_MIF_NRT_QCH, "GATE_LH_AXI_SI_D1_MIF_NRT_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_LH_AXI_SI_D1_MIF_RT_QCH, LH_AXI_SI_D1_MIF_RT_QCH, "GATE_LH_AXI_SI_D1_MIF_RT_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_LH_AXI_SI_D_SSS_QCH, LH_AXI_SI_D_SSS_QCH, "GATE_LH_AXI_SI_D_SSS_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_PUF_QCH, PUF_QCH, "GATE_PUF_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_RSTNSYNC_I_ARESETN_SSS_QCH, RSTNSYNC_I_ARESETN_SSS_QCH, "GATE_RSTNSYNC_I_ARESETN_SSS_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SFR_APBIF_CMU_TOPC_QCH, SFR_APBIF_CMU_TOPC_QCH, "GATE_SFR_APBIF_CMU_TOPC_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SIREX_QCH, SIREX_QCH, "GATE_SIREX_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_MI_D0_MODEM_QCH, SLH_AXI_MI_D0_MODEM_QCH, "GATE_SLH_AXI_MI_D0_MODEM_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_MI_D1_MODEM_QCH, SLH_AXI_MI_D1_MODEM_QCH, "GATE_SLH_AXI_MI_D1_MODEM_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_MI_D_GNSS_QCH, SLH_AXI_MI_D_GNSS_QCH, "GATE_SLH_AXI_MI_D_GNSS_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_MI_D_HSI_QCH, SLH_AXI_MI_D_HSI_QCH, "GATE_SLH_AXI_MI_D_HSI_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_MI_D_WLBT_QCH, SLH_AXI_MI_D_WLBT_QCH, "GATE_SLH_AXI_MI_D_WLBT_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_MI_G_CSSYS_QCH, SLH_AXI_MI_G_CSSYS_QCH, "GATE_SLH_AXI_MI_G_CSSYS_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_MI_P_CLUSTER0_QCH, SLH_AXI_MI_P_CLUSTER0_QCH, "GATE_SLH_AXI_MI_P_CLUSTER0_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_SI_P_APM_QCH, SLH_AXI_SI_P_APM_QCH, "GATE_SLH_AXI_SI_P_APM_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_AUD_QCH, SLH_AXI_SI_P_AUD_QCH, "GATE_SLH_AXI_SI_P_AUD_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_SI_P_BUSC_QCH, SLH_AXI_SI_P_BUSC_QCH, "GATE_SLH_AXI_SI_P_BUSC_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_SLH_AXI_SI_P_CPUCL0_QCH, SLH_AXI_SI_P_CPUCL0_QCH, "GATE_SLH_AXI_SI_P_CPUCL0_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_CSIS_QCH, SLH_AXI_SI_P_CSIS_QCH, "GATE_SLH_AXI_SI_P_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_DPU_QCH, SLH_AXI_SI_P_DPU_QCH, "GATE_SLH_AXI_SI_P_DPU_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_G3D_QCH, SLH_AXI_SI_P_G3D_QCH, "GATE_SLH_AXI_SI_P_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_GNSS_QCH, SLH_AXI_SI_P_GNSS_QCH, "GATE_SLH_AXI_SI_P_GNSS_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_HSI_QCH, SLH_AXI_SI_P_HSI_QCH, "GATE_SLH_AXI_SI_P_HSI_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_ISP_QCH, SLH_AXI_SI_P_ISP_QCH, "GATE_SLH_AXI_SI_P_ISP_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_M2M_QCH, SLH_AXI_SI_P_M2M_QCH, "GATE_SLH_AXI_SI_P_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_MCSC_QCH, SLH_AXI_SI_P_MCSC_QCH, "GATE_SLH_AXI_SI_P_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_MCW_QCH, SLH_AXI_SI_P_MCW_QCH, "GATE_SLH_AXI_SI_P_MCW_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_MFC_QCH, SLH_AXI_SI_P_MFC_QCH, "GATE_SLH_AXI_SI_P_MFC_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_MIF0_QCH, SLH_AXI_SI_P_MIF0_QCH, "GATE_SLH_AXI_SI_P_MIF0_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_MIF1_QCH, SLH_AXI_SI_P_MIF1_QCH, "GATE_SLH_AXI_SI_P_MIF1_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_MODEM_QCH, SLH_AXI_SI_P_MODEM_QCH, "GATE_SLH_AXI_SI_P_MODEM_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_NPU0_QCH, SLH_AXI_SI_P_NPU0_QCH, "GATE_SLH_AXI_SI_P_NPU0_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_NPUS_QCH, SLH_AXI_SI_P_NPUS_QCH, "GATE_SLH_AXI_SI_P_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_PERI_QCH, SLH_AXI_SI_P_PERI_QCH, "GATE_SLH_AXI_SI_P_PERI_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_TAA_QCH, SLH_AXI_SI_P_TAA_QCH, "GATE_SLH_AXI_SI_P_TAA_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_TNR_QCH, SLH_AXI_SI_P_TNR_QCH, "GATE_SLH_AXI_SI_P_TNR_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_USB_QCH, SLH_AXI_SI_P_USB_QCH, "GATE_SLH_AXI_SI_P_USB_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SLH_AXI_SI_P_WLBT_QCH, SLH_AXI_SI_P_WLBT_QCH, "GATE_SLH_AXI_SI_P_WLBT_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SSS_QCH, SSS_QCH, "GATE_SSS_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SYSMMU_ACEL_D2_MODEM_QCH, SYSMMU_ACEL_D2_MODEM_QCH, "GATE_SYSMMU_ACEL_D2_MODEM_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SYSMMU_ACEL_D_DIT_QCH, SYSMMU_ACEL_D_DIT_QCH, "GATE_SYSMMU_ACEL_D_DIT_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SYSREG_CORE_QCH, SYSREG_CORE_QCH, "GATE_SYSREG_CORE_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_TREX_D_CORE_QCH, TREX_D_CORE_QCH, "GATE_TREX_D_CORE_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TREX_D_NRT_QCH, TREX_D_NRT_QCH, "GATE_TREX_D_NRT_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_TREX_P_CORE_QCH, TREX_P_CORE_QCH, "GATE_TREX_P_CORE_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_VGEN_LITE_CORE_QCH, VGEN_LITE_CORE_QCH, "GATE_VGEN_LITE_CORE_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_CMU_CPUCL0_CMUREF_QCH, CMU_CPUCL0_CMUREF_QCH, "GATE_CMU_CPUCL0_CMUREF_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_CMU_CPUCL0_SHORTSTOP_QCH, CMU_CPUCL0_SHORTSTOP_QCH, "GATE_CMU_CPUCL0_SHORTSTOP_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_CPUCL0_QCH, CPUCL0_QCH, "GATE_CPUCL0_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_CPUCL0_CMU_CPUCL0_QCH, CPUCL0_CMU_CPUCL0_QCH, "GATE_CPUCL0_CMU_CPUCL0_QCH", NULL, 0, VCLK_GATE, NULL),
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HWACG_VCLK(GATE_HTU_CPUCL0_QCH_PCLK, HTU_CPUCL0_QCH_PCLK, "GATE_HTU_CPUCL0_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_HTU_CPUCL0_QCH_CLK, HTU_CPUCL0_QCH_CLK, "GATE_HTU_CPUCL0_QCH_CLK", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_BPS_CPUCL0_QCH, BPS_CPUCL0_QCH, "GATE_BPS_CPUCL0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH, CPUCL0_GLB_CMU_CPUCL0_GLB_QCH, "GATE_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_CSSYS_QCH, CSSYS_QCH, "GATE_CSSYS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_CPUCL0_QCH, D_TZPC_CPUCL0_QCH, "GATE_D_TZPC_CPUCL0_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH, RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH, "GATE_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH", NULL, 0, VCLK_GATE, NULL),
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|
HWACG_VCLK(GATE_SECJTAG_QCH, SECJTAG_QCH, "GATE_SECJTAG_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_G_DBGCORE_QCH, SLH_AXI_MI_G_DBGCORE_QCH, "GATE_SLH_AXI_MI_G_DBGCORE_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_G_INT_CSSYS_QCH, SLH_AXI_MI_G_INT_CSSYS_QCH, "GATE_SLH_AXI_MI_G_INT_CSSYS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_G_INT_DBGCORE_QCH, SLH_AXI_MI_G_INT_DBGCORE_QCH, "GATE_SLH_AXI_MI_G_INT_DBGCORE_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_CPUCL0_QCH, SLH_AXI_MI_P_CPUCL0_QCH, "GATE_SLH_AXI_MI_P_CPUCL0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_G_CSSYS_QCH, SLH_AXI_SI_G_CSSYS_QCH, "GATE_SLH_AXI_SI_G_CSSYS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_G_INT_CSSYS_QCH, SLH_AXI_SI_G_INT_CSSYS_QCH, "GATE_SLH_AXI_SI_G_INT_CSSYS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_G_INT_DBGCORE_QCH, SLH_AXI_SI_G_INT_DBGCORE_QCH, "GATE_SLH_AXI_SI_G_INT_DBGCORE_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CPUCL0_QCH, SYSREG_CPUCL0_QCH, "GATE_SYSREG_CPUCL0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CMU_CPUCL1_CMUREF_QCH, CMU_CPUCL1_CMUREF_QCH, "GATE_CMU_CPUCL1_CMUREF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CMU_CPUCL1_SHORTSTOP_QCH, CMU_CPUCL1_SHORTSTOP_QCH, "GATE_CMU_CPUCL1_SHORTSTOP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CPUCL1_QCH_BIG, CPUCL1_QCH_BIG, "GATE_CPUCL1_QCH_BIG", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CPUCL1_QCH_DDD_HC0, CPUCL1_QCH_DDD_HC0, "GATE_CPUCL1_QCH_DDD_HC0", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CPUCL1_QCH_DDD_HC1, CPUCL1_QCH_DDD_HC1, "GATE_CPUCL1_QCH_DDD_HC1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CPUCL1_CMU_CPUCL1_QCH, CPUCL1_CMU_CPUCL1_QCH, "GATE_CPUCL1_CMU_CPUCL1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_CPUCL1_QCH_PCLK, HTU_CPUCL1_QCH_PCLK, "GATE_HTU_CPUCL1_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_CPUCL1_QCH_CLK, HTU_CPUCL1_QCH_CLK, "GATE_HTU_CPUCL1_QCH_CLK", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e8825_csis_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_CSIS_CMU_CSIS_QCH, CSIS_CMU_CSIS_QCH, "GATE_CSIS_CMU_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CSIS_PDP_QCH_VOTF0, CSIS_PDP_QCH_VOTF0, "GATE_CSIS_PDP_QCH_VOTF0", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CSIS_PDP_QCH_DMA, CSIS_PDP_QCH_DMA, "GATE_CSIS_PDP_QCH_DMA", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CSIS_PDP_QCH_PDP_TOP, CSIS_PDP_QCH_PDP_TOP, "GATE_CSIS_PDP_QCH_PDP_TOP", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CSIS_PDP_QCH_MCB, CSIS_PDP_QCH_MCB, "GATE_CSIS_PDP_QCH_MCB", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CSIS_PDP_QCH_VOTF1, CSIS_PDP_QCH_VOTF1, "GATE_CSIS_PDP_QCH_VOTF1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CSIS_PDP_QCH_C2_PDP, CSIS_PDP_QCH_C2_PDP, "GATE_CSIS_PDP_QCH_C2_PDP", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_CSIS_QCH, D_TZPC_CSIS_QCH, "GATE_D_TZPC_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_SOTF0_TAACSIS_QCH, LH_AST_MI_SOTF0_TAACSIS_QCH, "GATE_LH_AST_MI_SOTF0_TAACSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_SOTF1_TAACSIS_QCH, LH_AST_MI_SOTF1_TAACSIS_QCH, "GATE_LH_AST_MI_SOTF1_TAACSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_SOTF2_TAACSIS_QCH, LH_AST_MI_SOTF2_TAACSIS_QCH, "GATE_LH_AST_MI_SOTF2_TAACSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_ZOTF0_TAACSIS_QCH, LH_AST_MI_ZOTF0_TAACSIS_QCH, "GATE_LH_AST_MI_ZOTF0_TAACSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_ZOTF1_TAACSIS_QCH, LH_AST_MI_ZOTF1_TAACSIS_QCH, "GATE_LH_AST_MI_ZOTF1_TAACSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_ZOTF2_TAACSIS_QCH, LH_AST_MI_ZOTF2_TAACSIS_QCH, "GATE_LH_AST_MI_ZOTF2_TAACSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_OTF0_CSISTAA_QCH, LH_AST_SI_OTF0_CSISTAA_QCH, "GATE_LH_AST_SI_OTF0_CSISTAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_OTF1_CSISTAA_QCH, LH_AST_SI_OTF1_CSISTAA_QCH, "GATE_LH_AST_SI_OTF1_CSISTAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_OTF2_CSISTAA_QCH, LH_AST_SI_OTF2_CSISTAA_QCH, "GATE_LH_AST_SI_OTF2_CSISTAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D0_CSIS_QCH, LH_AXI_SI_D0_CSIS_QCH, "GATE_LH_AXI_SI_D0_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D1_CSIS_QCH, LH_AXI_SI_D1_CSIS_QCH, "GATE_LH_AXI_SI_D1_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D2_CSIS_QCH, LH_AXI_SI_D2_CSIS_QCH, "GATE_LH_AXI_SI_D2_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D3_CSIS_QCH, LH_AXI_SI_D3_CSIS_QCH, "GATE_LH_AXI_SI_D3_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0, MIPI_DCPHY_LINK_WRAP_QCH_CSIS0, "GATE_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1, MIPI_DCPHY_LINK_WRAP_QCH_CSIS1, "GATE_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2, MIPI_DCPHY_LINK_WRAP_QCH_CSIS2, "GATE_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3, MIPI_DCPHY_LINK_WRAP_QCH_CSIS3, "GATE_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4, MIPI_DCPHY_LINK_WRAP_QCH_CSIS4, "GATE_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5, MIPI_DCPHY_LINK_WRAP_QCH_CSIS5, "GATE_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_CSIS_D0_QCH, PPMU_CSIS_D0_QCH, "GATE_PPMU_CSIS_D0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_CSIS_D1_QCH, PPMU_CSIS_D1_QCH, "GATE_PPMU_CSIS_D1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_CSIS_D2_QCH, PPMU_CSIS_D2_QCH, "GATE_PPMU_CSIS_D2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_CSIS_D3_QCH, PPMU_CSIS_D3_QCH, "GATE_PPMU_CSIS_D3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_CSIS_DMA0_QCH, QE_CSIS_DMA0_QCH, "GATE_QE_CSIS_DMA0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_CSIS_DMA1_QCH, QE_CSIS_DMA1_QCH, "GATE_QE_CSIS_DMA1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_CSIS_DMA2_QCH, QE_CSIS_DMA2_QCH, "GATE_QE_CSIS_DMA2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_CSIS_DMA3_QCH, QE_CSIS_DMA3_QCH, "GATE_QE_CSIS_DMA3_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_PDP_AF0_QCH, QE_PDP_AF0_QCH, "GATE_QE_PDP_AF0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_PDP_AF1_QCH, QE_PDP_AF1_QCH, "GATE_QE_PDP_AF1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_PDP_AF2_QCH, QE_PDP_AF2_QCH, "GATE_QE_PDP_AF2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_PDP_STAT_IMG0_QCH, QE_PDP_STAT_IMG0_QCH, "GATE_QE_PDP_STAT_IMG0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_PDP_STAT_IMG1_QCH, QE_PDP_STAT_IMG1_QCH, "GATE_QE_PDP_STAT_IMG1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_PDP_STAT_IMG2_QCH, QE_PDP_STAT_IMG2_QCH, "GATE_QE_PDP_STAT_IMG2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_STRP0_QCH, QE_STRP0_QCH, "GATE_QE_STRP0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_STRP1_QCH, QE_STRP1_QCH, "GATE_QE_STRP1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_STRP2_QCH, QE_STRP2_QCH, "GATE_QE_STRP2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_ZSL0_QCH, QE_ZSL0_QCH, "GATE_QE_ZSL0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_ZSL1_QCH, QE_ZSL1_QCH, "GATE_QE_ZSL1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_ZSL2_QCH, QE_ZSL2_QCH, "GATE_QE_ZSL2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_CSIS_QCH, SLH_AXI_MI_P_CSIS_QCH, "GATE_SLH_AXI_MI_P_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_CSIS_QCH_S1, SYSMMU_D0_CSIS_QCH_S1, "GATE_SYSMMU_D0_CSIS_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_CSIS_QCH_S2, SYSMMU_D0_CSIS_QCH_S2, "GATE_SYSMMU_D0_CSIS_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_CSIS_QCH_S1, SYSMMU_D1_CSIS_QCH_S1, "GATE_SYSMMU_D1_CSIS_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_CSIS_QCH_S2, SYSMMU_D1_CSIS_QCH_S2, "GATE_SYSMMU_D1_CSIS_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D2_CSIS_QCH_S1, SYSMMU_D2_CSIS_QCH_S1, "GATE_SYSMMU_D2_CSIS_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D2_CSIS_QCH_S2, SYSMMU_D2_CSIS_QCH_S2, "GATE_SYSMMU_D2_CSIS_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D3_CSIS_QCH_S2, SYSMMU_D3_CSIS_QCH_S2, "GATE_SYSMMU_D3_CSIS_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D3_CSIS_QCH_S1, SYSMMU_D3_CSIS_QCH_S1, "GATE_SYSMMU_D3_CSIS_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_CSIS_QCH, SYSREG_CSIS_QCH, "GATE_SYSREG_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE0_CSIS_QCH, VGEN_LITE0_CSIS_QCH, "GATE_VGEN_LITE0_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE1_CSIS_QCH, VGEN_LITE1_CSIS_QCH, "GATE_VGEN_LITE1_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE2_CSIS_QCH, VGEN_LITE2_CSIS_QCH, "GATE_VGEN_LITE2_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
struct init_vclk s5e8825_dpu_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_DPU_QCH_DPU, DPU_QCH_DPU, "GATE_DPU_QCH_DPU", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPU_QCH_DPU_DMA, DPU_QCH_DPU_DMA, "GATE_DPU_QCH_DPU_DMA", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPU_QCH_DPU_DPP, DPU_QCH_DPU_DPP, "GATE_DPU_QCH_DPU_DPP", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPU_QCH_DPU_C2SERV, DPU_QCH_DPU_C2SERV, "GATE_DPU_QCH_DPU_C2SERV", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPU_QCH, DPU_QCH, "GATE_DPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DPU_CMU_DPU_QCH, DPU_CMU_DPU_QCH, "GATE_DPU_CMU_DPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_DPU_QCH, D_TZPC_DPU_QCH, "GATE_D_TZPC_DPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D0_DPU_QCH, LH_AXI_SI_D0_DPU_QCH, "GATE_LH_AXI_SI_D0_DPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D1_DPU_QCH, LH_AXI_SI_D1_DPU_QCH, "GATE_LH_AXI_SI_D1_DPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D0_DPU_QCH, PPMU_D0_DPU_QCH, "GATE_PPMU_D0_DPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D1_DPU_QCH, PPMU_D1_DPU_QCH, "GATE_PPMU_D1_DPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_DPU_QCH, SLH_AXI_MI_P_DPU_QCH, "GATE_SLH_AXI_MI_P_DPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_AXI_D0_DPU_QCH_S1, SYSMMU_AXI_D0_DPU_QCH_S1, "GATE_SYSMMU_AXI_D0_DPU_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_AXI_D0_DPU_QCH_S2, SYSMMU_AXI_D0_DPU_QCH_S2, "GATE_SYSMMU_AXI_D0_DPU_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_AXI_D1_DPU_QCH_S1, SYSMMU_AXI_D1_DPU_QCH_S1, "GATE_SYSMMU_AXI_D1_DPU_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_AXI_D1_DPU_QCH_S2, SYSMMU_AXI_D1_DPU_QCH_S2, "GATE_SYSMMU_AXI_D1_DPU_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_DPU_QCH, SYSREG_DPU_QCH, "GATE_SYSREG_DPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CLUSTER0_QCH_SCLK, CLUSTER0_QCH_SCLK, "GATE_CLUSTER0_QCH_SCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CLUSTER0_QCH_ATCLK, CLUSTER0_QCH_ATCLK, "GATE_CLUSTER0_QCH_ATCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CLUSTER0_QCH_GIC, CLUSTER0_QCH_GIC, "GATE_CLUSTER0_QCH_GIC", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CLUSTER0_QCH_DBG_PD, CLUSTER0_QCH_DBG_PD, "GATE_CLUSTER0_QCH_DBG_PD", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CLUSTER0_QCH_PCLK, CLUSTER0_QCH_PCLK, "GATE_CLUSTER0_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CLUSTER0_QCH_PERIPHCLK, CLUSTER0_QCH_PERIPHCLK, "GATE_CLUSTER0_QCH_PERIPHCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CLUSTER0_QCH_PDBGCLK, CLUSTER0_QCH_PDBGCLK, "GATE_CLUSTER0_QCH_PDBGCLK", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
struct init_vclk s5e8825_dsu_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_CMU_DSU_CMUREF_QCH, CMU_DSU_CMUREF_QCH, "GATE_CMU_DSU_CMUREF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_CMU_DSU_SHORTSTOP_QCH, CMU_DSU_SHORTSTOP_QCH, "GATE_CMU_DSU_SHORTSTOP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DSU_CMU_DSU_QCH, DSU_CMU_DSU_QCH, "GATE_DSU_CMU_DSU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_DSU_QCH_PCLK, HTU_DSU_QCH_PCLK, "GATE_HTU_DSU_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_DSU_QCH_CLK, HTU_DSU_QCH_CLK, "GATE_HTU_DSU_QCH_CLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_G_CPU_QCH, LH_AST_SI_G_CPU_QCH, "GATE_LH_AST_SI_G_CPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D0_MIF_CPU_QCH, LH_AXI_SI_D0_MIF_CPU_QCH, "GATE_LH_AXI_SI_D0_MIF_CPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D1_MIF_CPU_QCH, LH_AXI_SI_D1_MIF_CPU_QCH, "GATE_LH_AXI_SI_D1_MIF_CPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPC_INSTRRET_CLUSTER0_0_QCH, PPC_INSTRRET_CLUSTER0_0_QCH, "GATE_PPC_INSTRRET_CLUSTER0_0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPC_INSTRRET_CLUSTER0_1_QCH, PPC_INSTRRET_CLUSTER0_1_QCH, "GATE_PPC_INSTRRET_CLUSTER0_1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPC_INSTRRUN_CLUSTER0_0_QCH, PPC_INSTRRUN_CLUSTER0_0_QCH, "GATE_PPC_INSTRRUN_CLUSTER0_0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPC_INSTRRUN_CLUSTER0_1_QCH, PPC_INSTRRUN_CLUSTER0_1_QCH, "GATE_PPC_INSTRRUN_CLUSTER0_1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_CPUCL0_QCH, PPMU_CPUCL0_QCH, "GATE_PPMU_CPUCL0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_CPUCL1_QCH, PPMU_CPUCL1_QCH, "GATE_PPMU_CPUCL1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_P_CLUSTER0_QCH, SLH_AXI_SI_P_CLUSTER0_QCH, "GATE_SLH_AXI_SI_P_CLUSTER0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
//G3D
|
|
struct init_vclk s5e8825_g3d_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_D_TZPC_G3D_QCH, D_TZPC_G3D_QCH, "GATE_D_TZPC_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_G3D_CMU_G3D_QCH, G3D_CMU_G3D_QCH, "GATE_G3D_CMU_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPU_QCH, GPU_QCH, "GATE_GPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_G3D_QCH_CLK, HTU_G3D_QCH_CLK, "GATE_HTU_G3D_QCH_CLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_G3D_QCH_PCLK, HTU_G3D_QCH_PCLK, "GATE_HTU_G3D_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LHM_AXI_P_INT_G3D_QCH, LHM_AXI_P_INT_G3D_QCH, "GATE_LHM_AXI_P_INT_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LHS_AXI_P_INT_G3D_QCH, LHS_AXI_P_INT_G3D_QCH, "GATE_LHS_AXI_P_INT_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D_G3D_QCH, LH_AXI_SI_D_G3D_QCH, "GATE_LH_AXI_SI_D_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D_G3D_QCH, PPMU_D_G3D_QCH, "GATE_PPMU_D_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_G3D_QCH, SLH_AXI_MI_P_G3D_QCH, "GATE_SLH_AXI_MI_P_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_G3D_QCH, SYSMMU_D_G3D_QCH, "GATE_SYSMMU_D_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_G3D_QCH, SYSREG_G3D_QCH, "GATE_SYSREG_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_G3D_QCH, VGEN_LITE_G3D_QCH, "GATE_VGEN_LITE_G3D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GNSS_CMU_GNSS_QCH, GNSS_CMU_GNSS_QCH, "GATE_GNSS_CMU_GNSS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
//*****************************HSI***********************
|
|
struct init_vclk s5e8825_hsi_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_D_TZPC_HSI_QCH, D_TZPC_HSI_QCH, "GATE_D_TZPC_HSI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPIO_HSI_QCH, GPIO_HSI_QCH, "GATE_GPIO_HSI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPIO_HSI_UFS_QCH, GPIO_HSI_UFS_QCH, "GATE_GPIO_HSI_UFS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HSI_CMU_HSI_QCH, HSI_CMU_HSI_QCH, "GATE_HSI_CMU_HSI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_HSI_QCH, PPMU_HSI_QCH, "GATE_PPMU_HSI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_S2MPU_D_HSI_QCH_S2, S2MPU_D_HSI_QCH_S2, "GATE_S2MPU_D_HSI_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_HSI_QCH, SLH_AXI_MI_P_HSI_QCH, "GATE_SLH_AXI_MI_P_HSI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_D_HSI_QCH, SLH_AXI_SI_D_HSI_QCH, "GATE_SLH_AXI_SI_D_HSI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_HSI_QCH, SYSREG_HSI_QCH, "GATE_SYSREG_HSI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_UFS_EMBD_QCH, UFS_EMBD_QCH, "GATE_UFS_EMBD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_UFS_EMBD_QCH_FMP, UFS_EMBD_QCH_FMP, "GATE_UFS_EMBD_QCH_FMP", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_HSI_QCH, VGEN_LITE_HSI_QCH, "GATE_VGEN_LITE_HSI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
//******************************ISP***********************
|
|
struct init_vclk s5e8825_isp_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_D_TZPC_ISP_QCH, D_TZPC_ISP_QCH, "GATE_D_TZPC_ISP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ISP_CMU_ISP_QCH, ISP_CMU_ISP_QCH, "GATE_ISP_CMU_ISP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ITP_DNS_QCH_S00, ITP_DNS_QCH_S00, "GATE_ITP_DNS_QCH_S00", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ITP_DNS_QCH_S01, ITP_DNS_QCH_S01, "GATE_ITP_DNS_QCH_S01", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_OTF0_TNRISP_QCH, LH_AST_MI_OTF0_TNRISP_QCH, "GATE_LH_AST_MI_OTF0_TNRISP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_OTF1_TNRISP_QCH, LH_AST_MI_OTF1_TNRISP_QCH, "GATE_LH_AST_MI_OTF1_TNRISP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_OTF_TAAISP_QCH, LH_AST_MI_OTF_TAAISP_QCH, "GATE_LH_AST_MI_OTF_TAAISP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_OTF_ISPMCSC_QCH, LH_AST_SI_OTF_ISPMCSC_QCH, "GATE_LH_AST_SI_OTF_ISPMCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D_ISP_QCH, LH_AXI_SI_D_ISP_QCH, "GATE_LH_AXI_SI_D_ISP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_ISP_QCH, PPMU_ISP_QCH, "GATE_PPMU_ISP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_ISP_QCH, SLH_AXI_MI_P_ISP_QCH, "GATE_SLH_AXI_MI_P_ISP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_ISP_QCH_S1, SYSMMU_D_ISP_QCH_S1, "GATE_SYSMMU_D_ISP_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_ISP_QCH_S2, SYSMMU_D_ISP_QCH_S2, "GATE_SYSMMU_D_ISP_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_ISP_QCH, SYSREG_ISP_QCH, "GATE_SYSREG_ISP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_ISP_QCH, VGEN_LITE_ISP_QCH, "GATE_VGEN_LITE_ISP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
//*******************************M2M**********************
|
|
struct init_vclk s5e8825_m2m_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_D_TZPC_M2M_QCH, D_TZPC_M2M_QCH, "GATE_D_TZPC_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_JPEG0_QCH, JPEG0_QCH, "GATE_JPEG0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D_M2M_QCH, LH_AXI_SI_D_M2M_QCH, "GATE_LH_AXI_SI_D_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_M2M_QCH_S2, M2M_QCH_S2, "GATE_M2M_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_M2M_QCH_S1, M2M_QCH_S1, "GATE_M2M_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_M2M_CMU_M2M_QCH, M2M_CMU_M2M_QCH, "GATE_M2M_CMU_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D_M2M_QCH, PPMU_D_M2M_QCH, "GATE_PPMU_D_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_M2M_QCH, SLH_AXI_MI_P_M2M_QCH, "GATE_SLH_AXI_MI_P_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_M2M_QCH_S1, SYSMMU_D_M2M_QCH_S1, "GATE_SYSMMU_D_M2M_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D_M2M_QCH_S2, SYSMMU_D_M2M_QCH_S2, "GATE_SYSMMU_D_M2M_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_M2M_QCH, SYSREG_M2M_QCH, "GATE_SYSREG_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_M2M_QCH, VGEN_LITE_M2M_QCH, "GATE_VGEN_LITE_M2M_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
} ;
|
|
|
|
//**********************************MCSC*******************
|
|
struct init_vclk s5e8825_mcsc_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_D_TZPC_MCSC_QCH, D_TZPC_MCSC_QCH, "GATE_D_TZPC_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GDC_QCH, GDC_QCH, "GATE_GDC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_OTF_ISPMCSC_QCH, LH_AST_MI_OTF_ISPMCSC_QCH, "GATE_LH_AST_MI_OTF_ISPMCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D0_CSIS_QCH, LH_AXI_MI_D0_CSIS_QCH, "GATE_LH_AXI_MI_D0_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D0_TNR_QCH, LH_AXI_MI_D0_TNR_QCH, "GATE_LH_AXI_MI_D0_TNR_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D1_CSIS_QCH, LH_AXI_MI_D1_CSIS_QCH, "GATE_LH_AXI_MI_D1_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D1_TNR_QCH, LH_AXI_MI_D1_TNR_QCH, "GATE_LH_AXI_MI_D1_TNR_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D2_CSIS_QCH, LH_AXI_MI_D2_CSIS_QCH, "GATE_LH_AXI_MI_D2_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D3_CSIS_QCH, LH_AXI_MI_D3_CSIS_QCH, "GATE_LH_AXI_MI_D3_CSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D_ISP_QCH, LH_AXI_MI_D_ISP_QCH, "GATE_LH_AXI_MI_D_ISP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D_TAA_QCH, LH_AXI_MI_D_TAA_QCH, "GATE_LH_AXI_MI_D_TAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MCSC_QCH, MCSC_QCH, "GATE_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MCSC_CMU_MCSC_QCH, MCSC_CMU_MCSC_QCH, "GATE_MCSC_CMU_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ORBMCH_QCH_ACLK, ORBMCH_QCH_ACLK, "GATE_ORBMCH_QCH_ACLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_ORBMCH_QCH_C2CLK, ORBMCH_QCH_C2CLK, "GATE_ORBMCH_QCH_C2CLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_GDC_QCH, PPMU_GDC_QCH, "GATE_PPMU_GDC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_MCSC_QCH, PPMU_MCSC_QCH, "GATE_PPMU_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_MCSC_QCH, SLH_AXI_MI_P_MCSC_QCH, "GATE_SLH_AXI_MI_P_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_MCSC_QCH_S1, SYSMMU_D0_MCSC_QCH_S1, "GATE_SYSMMU_D0_MCSC_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_MCSC_QCH_S2, SYSMMU_D0_MCSC_QCH_S2, "GATE_SYSMMU_D0_MCSC_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_MCSC_QCH_S1, SYSMMU_D1_MCSC_QCH_S1, "GATE_SYSMMU_D1_MCSC_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_MCSC_QCH_S2, SYSMMU_D1_MCSC_QCH_S2, "GATE_SYSMMU_D1_MCSC_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_MCSC_QCH, SYSREG_MCSC_QCH, "GATE_SYSREG_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TREX_D_CAM_QCH, TREX_D_CAM_QCH, "GATE_TREX_D_CAM_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_GDC_QCH, VGEN_LITE_GDC_QCH, "GATE_VGEN_LITE_GDC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_MCSC_QCH, VGEN_LITE_MCSC_QCH, "GATE_VGEN_LITE_MCSC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
//*********************************MFC*********************
|
|
struct init_vclk s5e8825_mfc_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_D_TZPC_MFC_QCH, D_TZPC_MFC_QCH, "GATE_D_TZPC_MFC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D_MFC_QCH, LH_AXI_SI_D_MFC_QCH, "GATE_LH_AXI_SI_D_MFC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MFC_QCH, MFC_QCH, "GATE_MFC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MFC_CMU_MFC_QCH, MFC_CMU_MFC_QCH, "GATE_MFC_CMU_MFC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_MFC_QCH, PPMU_MFC_QCH, "GATE_PPMU_MFC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH, RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH, "GATE_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_MFC_QCH, SLH_AXI_MI_P_MFC_QCH, "GATE_SLH_AXI_MI_P_MFC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_MFC_QCH_S1, SYSMMU_MFC_QCH_S1, "GATE_SYSMMU_MFC_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_MFC_QCH_S2, SYSMMU_MFC_QCH_S2, "GATE_SYSMMU_MFC_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_MFC_QCH, SYSREG_MFC_QCH, "GATE_SYSREG_MFC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_MFC_QCH, VGEN_LITE_MFC_QCH, "GATE_VGEN_LITE_MFC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
//************************************MIF***********************
|
|
struct init_vclk s5e8825_mif_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_CMU_MIF_CMUREF_QCH, CMU_MIF_CMUREF_QCH, "GATE_CMU_MIF_CMUREF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMC_QCH, DMC_QCH, "GATE_DMC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_MIF_QCH, D_TZPC_MIF_QCH, "GATE_D_TZPC_MIF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D_MIF_CP_QCH, LH_AXI_MI_D_MIF_CP_QCH, "GATE_LH_AXI_MI_D_MIF_CP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D_MIF_CPU_QCH, LH_AXI_MI_D_MIF_CPU_QCH, "GATE_LH_AXI_MI_D_MIF_CPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D_MIF_NRT_QCH, LH_AXI_MI_D_MIF_NRT_QCH, "GATE_LH_AXI_MI_D_MIF_NRT_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D_MIF_RT_QCH, LH_AXI_MI_D_MIF_RT_QCH, "GATE_LH_AXI_MI_D_MIF_RT_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MIF_CMU_MIF_QCH, MIF_CMU_MIF_QCH, "GATE_MIF_CMU_MIF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_DMC_CPU_QCH, PPMU_DMC_CPU_QCH, "GATE_PPMU_DMC_CPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_QE_DMC_CPU_QCH, QE_DMC_CPU_QCH, "GATE_QE_DMC_CPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SFRAPB_BRIDGE_DDRPHY_QCH, SFRAPB_BRIDGE_DDRPHY_QCH, "GATE_SFRAPB_BRIDGE_DDRPHY_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SFRAPB_BRIDGE_DMC_QCH, SFRAPB_BRIDGE_DMC_QCH, "GATE_SFRAPB_BRIDGE_DMC_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SFRAPB_BRIDGE_DMC_PF_QCH, SFRAPB_BRIDGE_DMC_PF_QCH, "GATE_SFRAPB_BRIDGE_DMC_PF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SFRAPB_BRIDGE_DMC_PPMPU_QCH, SFRAPB_BRIDGE_DMC_PPMPU_QCH, "GATE_SFRAPB_BRIDGE_DMC_PPMPU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SFRAPB_BRIDGE_DMC_SECURE_QCH, SFRAPB_BRIDGE_DMC_SECURE_QCH, "GATE_SFRAPB_BRIDGE_DMC_SECURE_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_MIF_QCH, SLH_AXI_MI_P_MIF_QCH, "GATE_SLH_AXI_MI_P_MIF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_MIF_QCH, SYSREG_MIF_QCH, "GATE_SYSREG_MIF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MODEM_CMU_MODEM_QCH, MODEM_CMU_MODEM_QCH, "GATE_MODEM_CMU_MODEM_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(MUX_MIF_DDRPHY2X, CLKMUX_MIF_DDRPHY2X, "MUX_MIF_DDRPHY2X", NULL, 0, 0, NULL),
|
|
};
|
|
//*****************************NPU0**************************
|
|
struct init_vclk s5e8825_npu0_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_D_TZPC_NPU0_QCH, D_TZPC_NPU0_QCH, "GATE_D_TZPC_NPU0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPUCORE_QCH_ACLK, IP_NPUCORE_QCH_ACLK, "GATE_IP_NPUCORE_QCH_ACLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPUCORE_QCH_PCLK, IP_NPUCORE_QCH_PCLK, "GATE_IP_NPUCORE_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D0_NPU0_QCH, LH_AXI_MI_D0_NPU0_QCH, "GATE_LH_AXI_MI_D0_NPU0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D1_NPU0_QCH, LH_AXI_MI_D1_NPU0_QCH, "GATE_LH_AXI_MI_D1_NPU0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D_CTRL_NPU0_QCH, LH_AXI_MI_D_CTRL_NPU0_QCH, "GATE_LH_AXI_MI_D_CTRL_NPU0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D_CMDQ_NPU0_QCH, LH_AXI_SI_D_CMDQ_NPU0_QCH, "GATE_LH_AXI_SI_D_CMDQ_NPU0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D_RQ_NPU0_QCH, LH_AXI_SI_D_RQ_NPU0_QCH, "GATE_LH_AXI_SI_D_RQ_NPU0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_NPU0_CMU_NPU0_QCH, NPU0_CMU_NPU0_QCH, "GATE_NPU0_CMU_NPU0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_NPU0_QCH, SLH_AXI_MI_P_NPU0_QCH, "GATE_SLH_AXI_MI_P_NPU0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_NPU0_QCH, SYSREG_NPU0_QCH, "GATE_SYSREG_NPU0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
//******************************NPUS**************************
|
|
struct init_vclk s5e8825_npus_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_ADM_DAP_NPUS_QCH, ADM_DAP_NPUS_QCH, "GATE_ADM_DAP_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_D_TZPC_NPUS_QCH, D_TZPC_NPUS_QCH, "GATE_D_TZPC_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_NPUS_QCH_PCLK, HTU_NPUS_QCH_PCLK, "GATE_HTU_NPUS_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HTU_NPUS_QCH_CLK, HTU_NPUS_QCH_CLK, "GATE_HTU_NPUS_QCH_CLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPUS_QCH, IP_NPUS_QCH, "GATE_IP_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPUS_QCH_C2A0CLK, IP_NPUS_QCH_C2A0CLK, "GATE_IP_NPUS_QCH_C2A0CLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPUS_QCH_C2A1CLK, IP_NPUS_QCH_C2A1CLK, "GATE_IP_NPUS_QCH_C2A1CLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPUS_QCH_CPU, IP_NPUS_QCH_CPU, "GATE_IP_NPUS_QCH_CPU", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_IP_NPUS_QCH_NEON, IP_NPUS_QCH_NEON, "GATE_IP_NPUS_QCH_NEON", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D_CMDQ_NPU0_QCH, LH_AXI_MI_D_CMDQ_NPU0_QCH, "GATE_LH_AXI_MI_D_CMDQ_NPU0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_MI_D_RQ_NPU0_QCH, LH_AXI_MI_D_RQ_NPU0_QCH, "GATE_LH_AXI_MI_D_RQ_NPU0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D0_NPU0_QCH, LH_AXI_SI_D0_NPU0_QCH, "GATE_LH_AXI_SI_D0_NPU0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D0_NPUS_QCH, LH_AXI_SI_D0_NPUS_QCH, "GATE_LH_AXI_SI_D0_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D1_NPU0_QCH, LH_AXI_SI_D1_NPU0_QCH, "GATE_LH_AXI_SI_D1_NPU0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D1_NPUS_QCH, LH_AXI_SI_D1_NPUS_QCH, "GATE_LH_AXI_SI_D1_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D_CTRL_NPU0_QCH, LH_AXI_SI_D_CTRL_NPU0_QCH, "GATE_LH_AXI_SI_D_CTRL_NPU0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_NPUS_CMU_NPUS_QCH, NPUS_CMU_NPUS_QCH, "GATE_NPUS_CMU_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_NPUS_0_QCH, PPMU_NPUS_0_QCH, "GATE_PPMU_NPUS_0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_NPUS_1_QCH, PPMU_NPUS_1_QCH, "GATE_PPMU_NPUS_1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_INT_NPUS_QCH, SLH_AXI_MI_P_INT_NPUS_QCH, "GATE_SLH_AXI_MI_P_INT_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_NPUS_QCH, SLH_AXI_MI_P_NPUS_QCH, "GATE_SLH_AXI_MI_P_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_P_INT_NPUS_QCH, SLH_AXI_SI_P_INT_NPUS_QCH, "GATE_SLH_AXI_SI_P_INT_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_NPUS_QCH_S1, SYSMMU_D0_NPUS_QCH_S1, "GATE_SYSMMU_D0_NPUS_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_NPUS_QCH_S2, SYSMMU_D0_NPUS_QCH_S2, "GATE_SYSMMU_D0_NPUS_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_NPUS_QCH_S1, SYSMMU_D1_NPUS_QCH_S1, "GATE_SYSMMU_D1_NPUS_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_NPUS_QCH_S2, SYSMMU_D1_NPUS_QCH_S2, "GATE_SYSMMU_D1_NPUS_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_NPUS_QCH, SYSREG_NPUS_QCH, "GATE_SYSREG_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_NPUS_QCH, VGEN_LITE_NPUS_QCH, "GATE_VGEN_LITE_NPUS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
//******************************PERI****************************
|
|
struct init_vclk s5e8825_peri_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_D_TZPC_PERI_QCH, D_TZPC_PERI_QCH, "GATE_D_TZPC_PERI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPIO_PERI_QCH, GPIO_PERI_QCH, "GATE_GPIO_PERI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPIO_PERIMMC_QCH_GPIO, GPIO_PERIMMC_QCH_GPIO, "GATE_GPIO_PERIMMC_QCH_GPIO", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MCT_QCH, MCT_QCH, "GATE_MCT_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MMC_CARD_QCH, MMC_CARD_QCH, "GATE_MMC_CARD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_OTP_CON_TOP_QCH, OTP_CON_TOP_QCH, "GATE_OTP_CON_TOP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PERI_CMU_PERI_QCH, PERI_CMU_PERI_QCH, "GATE_PERI_CMU_PERI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_PERI_QCH, PPMU_PERI_QCH, "GATE_PPMU_PERI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PWM_QCH, PWM_QCH, "GATE_PWM_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_S2MPU_D_PERI_QCH, S2MPU_D_PERI_QCH, "GATE_S2MPU_D_PERI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_PERI_QCH, SLH_AXI_MI_P_PERI_QCH, "GATE_SLH_AXI_MI_P_PERI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_D_PERI_QCH, SLH_AXI_SI_D_PERI_QCH, "GATE_SLH_AXI_SI_D_PERI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_PERI_QCH, SYSREG_PERI_QCH, "GATE_SYSREG_PERI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TMU_QCH, TMU_QCH, "GATE_TMU_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_UART_DBG_QCH, UART_DBG_QCH, "GATE_UART_DBG_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI00_I2C_QCH, USI00_I2C_QCH, "GATE_USI00_I2C_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI00_USI_QCH, USI00_USI_QCH, "GATE_USI00_USI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI01_I2C_QCH, USI01_I2C_QCH, "GATE_USI01_I2C_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI01_USI_QCH, USI01_USI_QCH, "GATE_USI01_USI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI02_I2C_QCH, USI02_I2C_QCH, "GATE_USI02_I2C_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI02_USI_QCH, USI02_USI_QCH, "GATE_USI02_USI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI03_I2C_QCH, USI03_I2C_QCH, "GATE_USI03_I2C_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI03_USI_QCH, USI03_USI_QCH, "GATE_USI03_USI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI04_I2C_QCH, USI04_I2C_QCH, "GATE_USI04_I2C_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI04_USI_QCH, USI04_USI_QCH, "GATE_USI04_USI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI05_I2C_QCH, USI05_I2C_QCH, "GATE_USI05_I2C_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI05_USI_QCH, USI05_USI_QCH, "GATE_USI05_USI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI06_I2C_QCH, USI06_I2C_QCH, "GATE_USI06_I2C_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI06_USI_QCH, USI06_USI_QCH, "GATE_USI06_USI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USI07_I2C_QCH, USI07_I2C_QCH, "GATE_USI07_I2C_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_PERI_QCH, VGEN_LITE_PERI_QCH, "GATE_VGEN_LITE_PERI_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_WDT0_QCH, WDT0_QCH, "GATE_WDT0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_WDT1_QCH, WDT1_QCH, "GATE_WDT1_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
//***********************************S2D*********************
|
|
struct init_vclk s5e8825_s2d_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_S2D_CMU_S2D_QCH, S2D_CMU_S2D_QCH, "GATE_S2D_CMU_S2D_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_G_SCAN2DRAM_QCH, SLH_AXI_MI_G_SCAN2DRAM_QCH, "GATE_SLH_AXI_MI_G_SCAN2DRAM_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
//***********************************TAA*********************
|
|
struct init_vclk s5e8825_taa_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_D_TZPC_TAA_QCH, D_TZPC_TAA_QCH, "GATE_D_TZPC_TAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_OTF0_CSISTAA_QCH, LH_AST_MI_OTF0_CSISTAA_QCH, "GATE_LH_AST_MI_OTF0_CSISTAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_OTF1_CSISTAA_QCH, LH_AST_MI_OTF1_CSISTAA_QCH, "GATE_LH_AST_MI_OTF1_CSISTAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_MI_OTF2_CSISTAA_QCH, LH_AST_MI_OTF2_CSISTAA_QCH, "GATE_LH_AST_MI_OTF2_CSISTAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_OTF_TAAISP_QCH, LH_AST_SI_OTF_TAAISP_QCH, "GATE_LH_AST_SI_OTF_TAAISP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_SOTF0_TAACSIS_QCH, LH_AST_SI_SOTF0_TAACSIS_QCH, "GATE_LH_AST_SI_SOTF0_TAACSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_SOTF1_TAACSIS_QCH, LH_AST_SI_SOTF1_TAACSIS_QCH, "GATE_LH_AST_SI_SOTF1_TAACSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_SOTF2_TAACSIS_QCH, LH_AST_SI_SOTF2_TAACSIS_QCH, "GATE_LH_AST_SI_SOTF2_TAACSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_ZOTF0_TAACSIS_QCH, LH_AST_SI_ZOTF0_TAACSIS_QCH, "GATE_LH_AST_SI_ZOTF0_TAACSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_ZOTF1_TAACSIS_QCH, LH_AST_SI_ZOTF1_TAACSIS_QCH, "GATE_LH_AST_SI_ZOTF1_TAACSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_ZOTF2_TAACSIS_QCH, LH_AST_SI_ZOTF2_TAACSIS_QCH, "GATE_LH_AST_SI_ZOTF2_TAACSIS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D_TAA_QCH, LH_AXI_SI_D_TAA_QCH, "GATE_LH_AXI_SI_D_TAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_TAA_QCH, PPMU_TAA_QCH, "GATE_PPMU_TAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SIPU_TAA_QCH, SIPU_TAA_QCH, "GATE_SIPU_TAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SIPU_TAA_QCH_C2_STAT, SIPU_TAA_QCH_C2_STAT, "GATE_SIPU_TAA_QCH_C2_STAT", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SIPU_TAA_QCH_C2_YDS, SIPU_TAA_QCH_C2_YDS, "GATE_SIPU_TAA_QCH_C2_YDS", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_TAA_QCH, SLH_AXI_MI_P_TAA_QCH, "GATE_SLH_AXI_MI_P_TAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_TAA_QCH_S1, SYSMMU_TAA_QCH_S1, "GATE_SYSMMU_TAA_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_TAA_QCH_S2, SYSMMU_TAA_QCH_S2, "GATE_SYSMMU_TAA_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_TAA_QCH, SYSREG_TAA_QCH, "GATE_SYSREG_TAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TAA_CMU_TAA_QCH, TAA_CMU_TAA_QCH, "GATE_TAA_CMU_TAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE0_TAA_QCH, VGEN_LITE0_TAA_QCH, "GATE_VGEN_LITE0_TAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE1_TAA_QCH, VGEN_LITE1_TAA_QCH, "GATE_VGEN_LITE1_TAA_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
//****************************TNR************************
|
|
struct init_vclk s5e8825_tnr_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_D_TZPC_TNR_QCH, D_TZPC_TNR_QCH, "GATE_D_TZPC_TNR_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_OTF0_TNRISP_QCH, LH_AST_SI_OTF0_TNRISP_QCH, "GATE_LH_AST_SI_OTF0_TNRISP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AST_SI_OTF1_TNRISP_QCH, LH_AST_SI_OTF1_TNRISP_QCH, "GATE_LH_AST_SI_OTF1_TNRISP_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D0_TNR_QCH, LH_AXI_SI_D0_TNR_QCH, "GATE_LH_AXI_SI_D0_TNR_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_LH_AXI_SI_D1_TNR_QCH, LH_AXI_SI_D1_TNR_QCH, "GATE_LH_AXI_SI_D1_TNR_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D0_TNR_QCH, PPMU_D0_TNR_QCH, "GATE_PPMU_D0_TNR_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_D1_TNR_QCH, PPMU_D1_TNR_QCH, "GATE_PPMU_D1_TNR_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_TNR_QCH, SLH_AXI_MI_P_TNR_QCH, "GATE_SLH_AXI_MI_P_TNR_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_TNR_QCH_S1, SYSMMU_D0_TNR_QCH_S1, "GATE_SYSMMU_D0_TNR_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D0_TNR_QCH_S2, SYSMMU_D0_TNR_QCH_S2, "GATE_SYSMMU_D0_TNR_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_TNR_QCH_S1, SYSMMU_D1_TNR_QCH_S1, "GATE_SYSMMU_D1_TNR_QCH_S1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSMMU_D1_TNR_QCH_S2, SYSMMU_D1_TNR_QCH_S2, "GATE_SYSMMU_D1_TNR_QCH_S2", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_TNR_QCH, SYSREG_TNR_QCH, "GATE_SYSREG_TNR_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TNR_QCH_MCFP0, TNR_QCH_MCFP0, "GATE_TNR_QCH_MCFP0", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TNR_QCH_MCFP1, TNR_QCH_MCFP1, "GATE_TNR_QCH_MCFP1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TNR_CMU_TNR_QCH, TNR_CMU_TNR_QCH, "GATE_TNR_CMU_TNR_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_D_TNR_QCH, VGEN_LITE_D_TNR_QCH, "GATE_VGEN_LITE_D_TNR_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
//*************************USB*****************************
|
|
struct init_vclk s5e8825_usb_hwacg_vclks[] = {
|
|
HWACG_VCLK(GATE_D_TZPC_USB_QCH, D_TZPC_USB_QCH, "GATE_D_TZPC_USB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_PPMU_USB_QCH, PPMU_USB_QCH, "GATE_PPMU_USB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_S2MPU_D_USB_QCH, S2MPU_D_USB_QCH, "GATE_S2MPU_D_USB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_P_USB_QCH, SLH_AXI_MI_P_USB_QCH, "GATE_SLH_AXI_MI_P_USB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_D_USB_QCH, SLH_AXI_SI_D_USB_QCH, "GATE_SLH_AXI_SI_D_USB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_D_USBAUD_QCH, SLH_AXI_SI_D_USBAUD_QCH, "GATE_SLH_AXI_SI_D_USBAUD_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_USB_QCH, SYSREG_USB_QCH, "GATE_SYSREG_USB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USB20DRD_TOP_QCH_SLV_CTRL, USB20DRD_TOP_QCH_SLV_CTRL, "GATE_USB20DRD_TOP_QCH_SLV_CTRL", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USB20DRD_TOP_QCH_SLV_LINK, USB20DRD_TOP_QCH_SLV_LINK, "GATE_USB20DRD_TOP_QCH_SLV_LINK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_USB_CMU_USB_QCH, USB_CMU_USB_QCH, "GATE_USB_CMU_USB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VGEN_LITE_USB_QCH, VGEN_LITE_USB_QCH, "GATE_VGEN_LITE_USB_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
} ;
|
|
//***********************************************VTS******************************
|
|
struct init_vclk s5e8825_vts_hwacg_vclks[] = {
|
|
HWACG_VCLK(UMUX_CLK_AUD_DMIC_BUS_USER, MUX_CLK_AUD_DMIC_BUS_USER, "UMUX_CLK_AUD_DMIC_BUS_USER", NULL, 0, 0, NULL),
|
|
HWACG_VCLK(UMUX_CLKCMU_VTS_RCO_USER, MUX_CLKCMU_VTS_RCO_USER, "UMUX_CLKCMU_VTS_RCO_USER", NULL, 0, 0, NULL),
|
|
|
|
HWACG_VCLK(GATE_CM4_VTS_QCH_CPU, CM4_VTS_QCH_CPU, "GATE_CM4_VTS_QCH_CPU", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_AHB0_QCH_PCLK, DMIC_AHB0_QCH_PCLK, "GATE_DMIC_AHB0_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_AHB2_QCH_PCLK, DMIC_AHB2_QCH_PCLK, "GATE_DMIC_AHB2_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_AUD0_QCH_PCLK, DMIC_AUD0_QCH_PCLK, "GATE_DMIC_AUD0_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_AUD0_QCH_DMIC, DMIC_AUD0_QCH_DMIC, "GATE_DMIC_AUD0_QCH_DMIC", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_AUD1_QCH_PCLK, DMIC_AUD1_QCH_PCLK, "GATE_DMIC_AUD1_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_AUD1_QCH_DMIC, DMIC_AUD1_QCH_DMIC, "GATE_DMIC_AUD1_QCH_DMIC", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_IF0_QCH_PCLK, DMIC_IF0_QCH_PCLK, "GATE_DMIC_IF0_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_IF0_QCH_DMIC, DMIC_IF0_QCH_DMIC, "GATE_DMIC_IF0_QCH_DMIC", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_IF1_QCH_PCLK, DMIC_IF1_QCH_PCLK, "GATE_DMIC_IF1_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_DMIC_IF1_QCH_DMIC, DMIC_IF1_QCH_DMIC, "GATE_DMIC_IF1_QCH_DMIC", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_GPIO_VTS_QCH, GPIO_VTS_QCH, "GATE_GPIO_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HWACG_SYS_DMIC0_QCH, HWACG_SYS_DMIC0_QCH, "GATE_HWACG_SYS_DMIC0_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HWACG_SYS_DMIC2_QCH, HWACG_SYS_DMIC2_QCH, "GATE_HWACG_SYS_DMIC2_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_HWACG_SYS_SERIAL_LIF_QCH, HWACG_SYS_SERIAL_LIF_QCH, "GATE_HWACG_SYS_SERIAL_LIF_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MAILBOX_ABOX_VTS_QCH, MAILBOX_ABOX_VTS_QCH, "GATE_MAILBOX_ABOX_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_MAILBOX_AP_VTS_QCH, MAILBOX_AP_VTS_QCH, "GATE_MAILBOX_AP_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SERIAL_LIF_AUD_QCH_PCLK, SERIAL_LIF_AUD_QCH_PCLK, "GATE_SERIAL_LIF_AUD_QCH_PCLK", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SERIAL_LIF_AUD_QCH_AHB, SERIAL_LIF_AUD_QCH_AHB, "GATE_SERIAL_LIF_AUD_QCH_AHB", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SERIAL_LIF_AUD_QCH_LIF, SERIAL_LIF_AUD_QCH_LIF, "GATE_SERIAL_LIF_AUD_QCH_LIF", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_MI_S_VTS_QCH, SLH_AXI_MI_S_VTS_QCH, "GATE_SLH_AXI_MI_S_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SLH_AXI_SI_M_VTS_QCH, SLH_AXI_SI_M_VTS_QCH, "GATE_SLH_AXI_SI_M_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0, SS_VTS_GLUE_QCH_DMIC_AUD_PAD0, "GATE_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1, SS_VTS_GLUE_QCH_DMIC_AUD_PAD1, "GATE_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD0, SS_VTS_GLUE_QCH_DMIC_IF_PAD0, "GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD0", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD1, SS_VTS_GLUE_QCH_DMIC_IF_PAD1, "GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD1", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_SYSREG_VTS_QCH, SYSREG_VTS_QCH, "GATE_SYSREG_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_TIMER_VTS_QCH, TIMER_VTS_QCH, "GATE_TIMER_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_VTS_CMU_VTS_QCH, VTS_CMU_VTS_QCH, "GATE_VTS_CMU_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
HWACG_VCLK(GATE_WDT_VTS_QCH, WDT_VTS_QCH, "GATE_WDT_VTS_QCH", NULL, 0, VCLK_GATE, NULL),
|
|
};
|
|
|
|
|
|
//VCLKS
|
|
struct init_vclk s5e8825_alive_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_ALIVE_USI0, DIV_CLK_ALIVE_USI0, "DOUT_DIV_CLK_ALIVE_USI0", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_ALIVE_I2C, DIV_CLK_ALIVE_I2C, "DOUT_DIV_CLK_ALIVE_I2C", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_ALIVE_I3C_PMIC, DIV_CLK_ALIVE_I3C_PMIC, "DOUT_DIV_CLK_ALIVE_I3C_PMIC", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_ALIVE_DBGCORE_UART, DIV_CLK_ALIVE_DBGCORE_UART, "DOUT_DIV_CLK_ALIVE_DBGCORE_UART", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_ALIVE_BUS, DIV_CLK_ALIVE_BUS, "DOUT_DIV_CLK_ALIVE_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_CMGP_BUS, CLKCMU_CMGP_BUS, "DOUT_CLKCMU_CMGP_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_CMGP_PERI, CLKCMU_CMGP_PERI, "DOUT_CLKCMU_CMGP_PERI", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_CHUBVTS_BUS, CLKCMU_CHUBVTS_BUS, "DOUT_CLKCMU_CHUBVTS_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_CHUB_PERI, CLKCMU_CHUB_PERI, "DOUT_CLKCMU_CHUB_PERI", 0, 0, NULL),
|
|
};
|
|
struct init_vclk s5e8825_top_vclks[] = {
|
|
VCLK(DOUT_CLKCMU_CMU_BOOST, CLKCMU_CMU_BOOST, "DOUT_CLKCMU_CMU_BOOST", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_CIS_CLK0, CLKCMU_CIS_CLK0, "DOUT_CLKCMU_CIS_CLK0", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_CIS_CLK1, CLKCMU_CIS_CLK1, "DOUT_CLKCMU_CIS_CLK1", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_CIS_CLK2, CLKCMU_CIS_CLK2, "DOUT_CLKCMU_CIS_CLK2", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_CIS_CLK3, CLKCMU_CIS_CLK3, "DOUT_CLKCMU_CIS_CLK3", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_CIS_CLK4, CLKCMU_CIS_CLK4, "DOUT_CLKCMU_CIS_CLK4", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_CIS_CLK5, CLKCMU_CIS_CLK5, "DOUT_CLKCMU_CIS_CLK5", 0, 0, NULL),
|
|
//VCLK(DOUT_CLKCMU_HPM, CLKCMU_HPM, "DOUT_CLKCMU_HPM", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_OTP, CLKCMU_OTP, "DOUT_CLKCMU_OTP", 0, 0, NULL),
|
|
};
|
|
|
|
struct init_vclk s5e8825_aud_vclks[] = {
|
|
|
|
VCLK(MOUT_CLK_AUD_UAIF6, MUX_CLK_AUD_UAIF6, "MOUT_CLK_AUD_UAIF6", 0, 0, NULL),
|
|
VCLK(MOUT_CLK_AUD_UAIF0, MUX_CLK_AUD_UAIF0, "MOUT_CLK_AUD_UAIF0", 0, 0, NULL),
|
|
VCLK(MOUT_CLK_AUD_UAIF1, MUX_CLK_AUD_UAIF1, "MOUT_CLK_AUD_UAIF1", 0, 0, NULL),
|
|
VCLK(MOUT_CLK_AUD_UAIF2, MUX_CLK_AUD_UAIF2, "MOUT_CLK_AUD_UAIF2", 0, 0, NULL),
|
|
VCLK(MOUT_CLK_AUD_UAIF3, MUX_CLK_AUD_UAIF3, "MOUT_CLK_AUD_UAIF3", 0, 0, NULL),
|
|
VCLK(MOUT_CLK_AUD_UAIF4, MUX_CLK_AUD_UAIF4, "MOUT_CLK_AUD_UAIF4", 0, 0, NULL),
|
|
VCLK(MOUT_CLK_AUD_UAIF5, MUX_CLK_AUD_UAIF5, "MOUT_CLK_AUD_UAIF5", 0, 0, NULL),
|
|
VCLK(MOUT_CLK_AUD_PCMC, MUX_CLK_AUD_PCMC, "MOUT_CLK_AUD_PCMC", 0, 0, NULL),
|
|
|
|
VCLK(DOUT_CLKCMU_AUD_CPU , CLKCMU_AUD_CPU , "DOUT_CLKCMU_AUD_CPU", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_AUD_BUS , CLKCMU_AUD_BUS , "DOUT_CLKCMU_AUD_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_CPU , DIV_CLK_AUD_CPU , "DOUT_DIV_CLK_AUD_CPU", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_CPU_ACLK , DIV_CLK_AUD_CPU_ACLK , "DOUT_DIV_CLK_AUD_CPU_ACLK", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_CPU_PCLKDBG , DIV_CLK_AUD_CPU_PCLKDBG , "DOUT_DIV_CLK_AUD_CPU_PCLKDBG", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_BUSD , DIV_CLK_AUD_BUSD , "DOUT_DIV_CLK_AUD_BUSD", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_BUSP , DIV_CLK_AUD_BUSP , "DOUT_DIV_CLK_AUD_BUSP", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_AUDIF , DIV_CLK_AUD_AUDIF , "DOUT_DIV_CLK_AUD_AUDIF", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_MCLK , DIV_CLK_AUD_MCLK , "DOUT_DIV_CLK_AUD_MCLK", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_CNT , DIV_CLK_AUD_CNT , "DOUT_DIV_CLK_AUD_CNT", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_DMIC , CLK_AUD_DMIC , "DOUT_DIV_CLK_AUD_DMIC", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_PCMC , DIV_CLK_AUD_PCMC , "DOUT_DIV_CLK_AUD_PCMC", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_DSIF , DIV_CLK_AUD_DSIF , "DOUT_DIV_CLK_AUD_DSIF", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF0 , DIV_CLK_AUD_UAIF0 , "DOUT_DIV_CLK_AUD_UAIF0", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF1 , DIV_CLK_AUD_UAIF1 , "DOUT_DIV_CLK_AUD_UAIF1", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF2 , DIV_CLK_AUD_UAIF2 , "DOUT_DIV_CLK_AUD_UAIF2", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF3 , DIV_CLK_AUD_UAIF3 , "DOUT_DIV_CLK_AUD_UAIF3", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF4 , DIV_CLK_AUD_UAIF4 , "DOUT_DIV_CLK_AUD_UAIF4", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF5 , DIV_CLK_AUD_UAIF5 , "DOUT_DIV_CLK_AUD_UAIF5", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_UAIF6 , DIV_CLK_AUD_UAIF6 , "DOUT_DIV_CLK_AUD_UAIF6", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_FM_SPDY , DIV_CLK_AUD_FM_SPDY , "DOUT_DIV_CLK_AUD_FM_SPDY", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_AUD_FM , DIV_CLK_AUD_FM , "DOUT_DIV_CLK_AUD_FM", 0, 0, NULL),
|
|
VCLK(PLL_OUT_AUD, PLL_AUD, "PLL_OUT_AUD", 0, 0, NULL),
|
|
//VCLK(DOUT_CLKAUD_USB_BUS , GATEi_CLKAUD_USB_BUS , "DOUT_CLKAUD_USB_BUS", 0, 0, NULL),
|
|
//VCLK(DOUT_CLKAUD_USB_USB31DRD , CLKAUD_USB_USB31DRD , "DOUT_CLKAUD_USB_USB31DRD", 0, 0, NULL),
|
|
};
|
|
//BUSC //BUSC //BUSC
|
|
struct init_vclk s5e8825_busc_vclks[] = {
|
|
VCLK(DOUT_CLKCMU_BUSC_BUS , CLKCMU_BUSC_BUS , "DOUT_CLKCMU_BUSC_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_BUSC_BUSP , DIV_CLK_BUSC_BUSP , "DOUT_DIV_CLK_BUSC_BUSP", 0, 0, NULL),
|
|
};
|
|
//core //core //core
|
|
struct init_vclk s5e8825_core_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_CORE_BUSP , DIV_CLK_CORE_BUSP , "DOUT_DIV_CLK_CORE_BUSP", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_CORE_G3D, CLKCMU_CORE_G3D, "DOUT_CLKCMU_CORE_G3D", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_CORE_SSS, CLKCMU_CORE_SSS, "DOUT_CLKCMU_CORE_SSS", 0, 0, NULL),
|
|
};
|
|
//DSU //DSU //DSU
|
|
struct init_vclk s5e8825_dsu_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_DSU_CLUSTER , DIV_CLK_DSU_CLUSTER , "DOUT_DIV_CLK_DSU_CLUSTER", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_DSU_SHORTSTOP , DIV_CLK_DSU_SHORTSTOP , "DOUT_DIV_CLK_DSU_SHORTSTOP", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CLUSTER0_ACLK , DIV_CLK_CLUSTER0_ACLK , "DOUT_DIV_CLK_CLUSTER0_ACLK", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CLUSTER0_ATCLK , DIV_CLK_CLUSTER0_ATCLK , "DOUT_DIV_CLK_CLUSTER0_ATCLK", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CLUSTER0_PCLK , DIV_CLK_CLUSTER0_PCLK , "DOUT_DIV_CLK_CLUSTER0_PCLK", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CLUSTER0_PERIPHCLK , DIV_CLK_CLUSTER0_PERIPHCLK , "DOUT_DIV_CLK_CLUSTER0_PERIPHCLK", 0, 0, NULL),
|
|
};
|
|
//CSIS //CSIS //CSIS
|
|
struct init_vclk s5e8825_csis_vclks[] = {
|
|
VCLK(DOUT_CLKCMU_CSIS_BUS , CLKCMU_CSIS_BUS , "DOUT_CLKCMU_CSIS_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CSIS_BUSP , DIV_CLK_CSIS_BUSP , "DOUT_DIV_CLK_CSIS_BUSP", 0, 0, NULL),
|
|
};
|
|
//DPU //DPU //DPU
|
|
struct init_vclk s5e8825_dpu_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_DPU_BUSP , DIV_CLK_DPU_BUSP , "DOUT_DIV_CLK_DPU_BUSP", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_DPU_BUS , CLKCMU_DPU_BUS , "DOUT_CLKCMU_DPU_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_DPU_DSIM , CLKCMU_DPU_DSIM , "DOUT_CLKCMU_DPU_DSIM", 0, 0, NULL),
|
|
};
|
|
//M2M //M2M //M2M
|
|
struct init_vclk s5e8825_m2m_vclks[] = {
|
|
VCLK(DOUT_CLKCMU_M2M_MSCL , CLKCMU_M2M_MSCL , "DOUT_CLKCMU_M2M_MSCL", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_M2M_BUSP , DIV_CLK_M2M_BUSP , "DOUT_DIV_CLK_M2M_BUSP", 0, 0, NULL),
|
|
};
|
|
//G3D //G3D //G3D
|
|
struct init_vclk s5e8825_g3d_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_G3D_BUSD , DIV_CLK_G3D_BUSD , "DOUT_DIV_CLK_G3D_BUSD", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_G3D_BUSP , DIV_CLK_G3D_BUSP , "DOUT_DIV_CLK_G3D_BUSP", 0, 0, NULL),
|
|
};
|
|
//HSI //HSI //HSI
|
|
struct init_vclk s5e8825_hsi_vclks[] = {
|
|
VCLK(DOUT_CLKCMU_HSI_BUS , CLKCMU_HSI_BUS , "DOUT_CLKCMU_HSI_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_HSI_UFS_EMBD , CLKCMU_HSI_UFS_EMBD , "DOUT_CLKCMU_HSI_UFS_EMBD", 0, 0, NULL),
|
|
};
|
|
//ISP //ISP //ISP
|
|
struct init_vclk s5e8825_isp_vclks[] = {
|
|
VCLK(DOUT_CLKCMU_ISP_BUS, CLKCMU_ISP_BUS, "DOUT_CLKCMU_ISP_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_ISP_BUSP , DIV_CLK_ISP_BUSP , "DOUT_DIV_CLK_ISP_BUSP", 0, 0, NULL),
|
|
};
|
|
//MCSC //MCSC //MCSC
|
|
struct init_vclk s5e8825_mcsc_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_MCSC_BUSP , DIV_CLK_MCSC_BUSP , "DOUT_DIV_CLK_MCSC_BUSP", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_MCSC_BUS, CLKCMU_MCSC_BUS, "DOUT_CLKCMU_MCSC_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_MCSC_GDC, CLKCMU_MCSC_GDC, "DOUT_CLKCMU_MCSC_GDC", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_MCSC_MCSC, CLKCMU_MCSC_MCSC, "DOUT_CLKCMU_MCSC_MCSC", 0, 0, NULL),
|
|
};
|
|
//MFC //MFC //MFC
|
|
struct init_vclk s5e8825_mfc_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_MFC_BUSP , DIV_CLK_MFC_BUSP , "DOUT_DIV_CLK_MFC_BUSP", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_MFC_MFC, CLKCMU_MFC_MFC, "DOUT_CLKCMU_MFC_MFC", 0, 0, NULL),
|
|
};
|
|
//NPU0 //NPU0 //NPU0
|
|
struct init_vclk s5e8825_npu0_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_NPU0_BUS , DIV_CLK_NPU0_BUS , "DOUT_DIV_CLK_NPU0_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_NPU0_BUSP , DIV_CLK_NPU0_BUSP , "DOUT_DIV_CLK_NPU0_BUSP", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_NPU0_BUS , CLKCMU_NPU0_BUS , "DOUT_CLKCMU_NPU0_BUS", 0, 0, NULL),
|
|
};
|
|
//NPUS //NPUS //NPUS
|
|
struct init_vclk s5e8825_npus_vclks[] = {
|
|
VCLK(DOUT_CLKCMU_NPUS_BUS, CLKCMU_NPUS_BUS, "DOUT_CLKCMU_NPUS_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_NPUS_BUS , DIV_CLK_NPUS_BUS , "DOUT_DIV_CLK_NPUS_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_NPUS_BUSP , DIV_CLK_NPUS_BUSP , "DOUT_DIV_CLK_NPUS_BUSP", 0, 0, NULL),
|
|
};
|
|
//PERI //PERI //PERI
|
|
struct init_vclk s5e8825_peri_vclks[] = {
|
|
VCLK(DOUT_CLKCMU_PERI_BUS, CLKCMU_PERI_BUS, "DOUT_CLKCMU_PERI_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_PERI_MMC_CARD, CLKCMU_PERI_MMC_CARD, "DOUT_CLKCMU_PERI_MMC_CARD", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERI_UART_DBG , DIV_CLK_PERI_UART_DBG , "DOUT_DIV_CLK_PERI_UART_DBG", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERI_USI_I2c , DIV_CLK_PERI_USI_I2C , "DOUT_DIV_CLK_PERI_USI_I2c", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERI_USI00_USI , VCLK_DIV_CLK_PERI_USI00_USI , "DOUT_DIV_CLK_PERI_USI00_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERI_USI01_USI , VCLK_DIV_CLK_PERI_USI01_USI , "DOUT_DIV_CLK_PERI_USI01_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERI_USI02_USI , VCLK_DIV_CLK_PERI_USI02_USI , "DOUT_DIV_CLK_PERI_USI02_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERI_USI03_USI , VCLK_DIV_CLK_PERI_USI03_USI , "DOUT_DIV_CLK_PERI_USI03_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERI_USI04_USI , VCLK_DIV_CLK_PERI_USI04_USI , "DOUT_DIV_CLK_PERI_USI04_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERI_USI05_USI , VCLK_DIV_CLK_PERI_USI05_USI , "DOUT_DIV_CLK_PERI_USI05_USI", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_PERI_USI06_USI, VCLK_DIV_CLK_PERI_USI06_USI, "DOUT_DIV_CLK_PERI_USI06_USI", 0, 0, NULL),
|
|
};
|
|
//TAA //TAA //TAA
|
|
struct init_vclk s5e8825_taa_vclks[] = {
|
|
VCLK(DOUT_CLKCMU_TAA_BUS, CLKCMU_TAA_BUS, "DOUT_CLKCMU_TAA_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_TAA_BUSP , DIV_CLK_TAA_BUSP , "DOUT_DIV_CLK_TAA_BUSP", 0, 0, NULL),
|
|
};
|
|
//TNR //TNR //TNR
|
|
struct init_vclk s5e8825_tnr_vclks[] = {
|
|
VCLK(DOUT_CLKCMU_TNR_BUS, CLKCMU_TNR_BUS, "DOUT_CLKCMU_TNR_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_TNR_BUSP , DIV_CLK_TNR_BUSP , "DOUT_DIV_CLK_TNR_BUSP", 0, 0, NULL),
|
|
} ;
|
|
|
|
//cmgp //cmgp //cmgp
|
|
struct init_vclk s5e8825_cmgp_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_CMGP_USI0 , DIV_CLK_CMGP_USI0 , "DOUT_DIV_CLK_CMGP_USI0", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_USI1, DIV_CLK_CMGP_USI1, "DOUT_DIV_CLK_CMGP_USI1", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_USI2, DIV_CLK_CMGP_USI2, "DOUT_DIV_CLK_CMGP_USI2", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_USI3, DIV_CLK_CMGP_USI3, "DOUT_DIV_CLK_CMGP_USI3", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_USI4 , DIV_CLK_CMGP_USI4 , "DOUT_DIV_CLK_CMGP_USI4", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_I2C , DIV_CLK_CMGP_I2C , "DOUT_DIV_CLK_CMGP_I2C", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CMGP_I3C, DIV_CLK_CMGP_I3C, "DOUT_DIV_CLK_CMGP_I3C", 0, 0, NULL),
|
|
};
|
|
//chub //chub //chub
|
|
struct init_vclk s5e8825_chub_vclks[] = {
|
|
VCLK(DOUT_DIV_CLK_CHUB_BUS , DIV_CLK_CHUB_BUS , "DOUT_DIV_CLK_CHUB_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CHUB_USI0 , DIV_CLK_CHUB_USI0 , "DOUT_DIV_CLK_CHUB_USI0", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CHUB_USI1 , DIV_CLK_CHUB_USI1 , "DOUT_DIV_CLK_CHUB_USI1", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CHUB_USI2 , DIV_CLK_CHUB_USI2 , "DOUT_DIV_CLK_CHUB_USI2", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CHUB_I2C , DIV_CLK_CHUB_I2C , "DOUT_DIV_CLK_CHUB_I2C", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CHUB_USI3 , DIV_CLK_CHUB_USI3 , "DOUT_DIV_CLK_CHUB_USI3", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_CHUBVTS_BUS, DIV_CLK_CHUBVTS_BUS, "DOUT_DIV_CLK_CHUBVTS_BUS", 0, 0, NULL),
|
|
};
|
|
//VTS //VTS //VTS
|
|
struct init_vclk s5e8825_vts_vclks[] = {
|
|
VCLK(MOUT_CLK_VTS_DMIC_IF, MUX_CLK_VTS_DMIC_IF, "MOUT_CLK_VTS_DMIC_IF", 0, 0, NULL),
|
|
VCLK(MOUT_MUX_VTS_DMIC_AUD, MUX_VTS_DMIC_AUD, "MOUT_MUX_VTS_DMIC_AUD", 0, 0, NULL),
|
|
VCLK(MOUT_MUX_VTS_SERIAL_LIF, MUX_VTS_SERIAL_LIF, "MOUT_MUX_VTS_SERIAL_LIF", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_VTS_BUS , DIV_CLK_VTS_BUS , "DOUT_DIV_CLK_VTS_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_VTS_DMIC_IF , DIV_CLK_VTS_DMIC_IF , "DOUT_DIV_CLK_VTS_DMIC_IF", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_CLK_VTS_DMIC_DIV2 , DIV_CLK_VTS_DMIC_IF_DIV2 , "DOUT_DIV_CLK_VTS_DMIC_DIV2", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_VTS_DMIC_AUD,DIV_VTS_DMIC_AUD,"DOUT_DIV_VTS_DMIC_AUD", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_VTS_DMIC_AUD_DIV2,DIV_VTS_DMIC_AUD_DIV2,"DOUT_DIV_VTS_DMIC_AUD_DIV2", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_VTS_SERIAL_LIF_CORE,DIV_VTS_SERIAL_LIF_CORE,"DOUT_DIV_VTS_SERIAL_LIF_CORE", 0, 0, NULL),
|
|
VCLK(DOUT_DIV_VTS_SERIAL_LIF,DIV_VTS_SERIAL_LIF,"DOUT_DIV_VTS_SERIAL_LIF", 0, 0, NULL),
|
|
};
|
|
struct init_vclk s5e8825_usb_vclks[] = {
|
|
VCLK(DOUT_CLKCMU_USB_BUS, CLKCMU_USB_BUS, "DOUT_CLKCMU_USB_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_CLKCMU_USB_USB20DRD, CLKCMU_USB_USB20DRD, "DOUT_CLKCMU_USB_USB20DRD", 0, 0, NULL),
|
|
VCLK(DOUT_CLKAUD_USB_BUS, CLKAUD_USB_BUS, "DOUT_CLKAUD_USB_BUS", 0, 0, NULL),
|
|
VCLK(DOUT_CLKAUD_USB_USB20DRD, CLKAUD_USB_USB20DRD, "DOUT_CLKAUD_USB_USB20DRD", 0, 0, NULL),
|
|
};
|
|
|
|
|
|
static struct init_vclk s5e8825_clkout_vclks[] = {
|
|
VCLK(OSC_NFC, VCLK_CLKOUT1, "OSC_NFC", 0, 0, NULL),
|
|
VCLK(OSC_AUD, VCLK_CLKOUT0, "OSC_AUD", 0, 0, NULL),
|
|
};
|
|
|
|
static struct of_device_id ext_clk_match[] = {
|
|
{.compatible = "samsung,s5e8825-oscclk", .data = (void *)0},
|
|
{},
|
|
};
|
|
|
|
void s5e8825_vclk_init(void)
|
|
{
|
|
/* Common clock init */
|
|
cal_clk_disable(VCLK_CLKOUT0);
|
|
}
|
|
|
|
/* register s5e8825 clocks */
|
|
static int s5e8825_clock_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
void __iomem *reg_base;
|
|
|
|
if (np) {
|
|
reg_base = of_iomap(np, 0);
|
|
if (!reg_base)
|
|
panic("%s: failed to map registers\n", __func__);
|
|
} else {
|
|
panic("%s: unable to determine soc\n", __func__);
|
|
}
|
|
|
|
s5e8825_clk_provider = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
|
|
if (!s5e8825_clk_provider)
|
|
panic("%s: unable to allocate context.\n", __func__);
|
|
|
|
samsung_register_of_fixed_ext(s5e8825_clk_provider, s5e8825_fixed_rate_ext_clks,
|
|
ARRAY_SIZE(s5e8825_fixed_rate_ext_clks),
|
|
ext_clk_match);
|
|
|
|
/* register HWACG vclk */
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_alive_hwacg_vclks, ARRAY_SIZE(s5e8825_alive_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_aud_hwacg_vclks, ARRAY_SIZE(s5e8825_aud_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_busc_hwacg_vclks, ARRAY_SIZE(s5e8825_busc_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_chub_hwacg_vclks, ARRAY_SIZE(s5e8825_chub_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_cmgp_hwacg_vclks, ARRAY_SIZE(s5e8825_cmgp_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_top_hwacg_vclks, ARRAY_SIZE(s5e8825_top_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_core_hwacg_vclks, ARRAY_SIZE(s5e8825_core_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_csis_hwacg_vclks, ARRAY_SIZE(s5e8825_csis_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_dpu_hwacg_vclks, ARRAY_SIZE(s5e8825_dpu_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_dsu_hwacg_vclks, ARRAY_SIZE(s5e8825_dsu_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_g3d_hwacg_vclks, ARRAY_SIZE(s5e8825_g3d_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_hsi_hwacg_vclks, ARRAY_SIZE(s5e8825_hsi_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_isp_hwacg_vclks, ARRAY_SIZE(s5e8825_isp_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_m2m_hwacg_vclks, ARRAY_SIZE(s5e8825_m2m_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_mcsc_hwacg_vclks, ARRAY_SIZE(s5e8825_mcsc_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_mfc_hwacg_vclks, ARRAY_SIZE(s5e8825_mfc_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_mif_hwacg_vclks, ARRAY_SIZE(s5e8825_mif_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_npu0_hwacg_vclks, ARRAY_SIZE(s5e8825_npu0_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_npus_hwacg_vclks, ARRAY_SIZE(s5e8825_npus_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_peri_hwacg_vclks, ARRAY_SIZE(s5e8825_peri_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_s2d_hwacg_vclks, ARRAY_SIZE(s5e8825_s2d_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_taa_hwacg_vclks, ARRAY_SIZE(s5e8825_taa_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_tnr_hwacg_vclks, ARRAY_SIZE(s5e8825_tnr_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_usb_hwacg_vclks, ARRAY_SIZE(s5e8825_usb_hwacg_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_vts_hwacg_vclks, ARRAY_SIZE(s5e8825_vts_hwacg_vclks));
|
|
/* register special vclk */
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_alive_vclks, ARRAY_SIZE(s5e8825_alive_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_top_vclks, ARRAY_SIZE(s5e8825_top_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_aud_vclks, ARRAY_SIZE(s5e8825_aud_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_cmgp_vclks, ARRAY_SIZE(s5e8825_cmgp_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_busc_vclks, ARRAY_SIZE(s5e8825_busc_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_core_vclks, ARRAY_SIZE(s5e8825_core_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_dsu_vclks, ARRAY_SIZE(s5e8825_dsu_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_csis_vclks, ARRAY_SIZE(s5e8825_csis_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_m2m_vclks, ARRAY_SIZE(s5e8825_m2m_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_dpu_vclks, ARRAY_SIZE(s5e8825_dpu_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_g3d_vclks, ARRAY_SIZE(s5e8825_g3d_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_hsi_vclks, ARRAY_SIZE(s5e8825_hsi_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_isp_vclks, ARRAY_SIZE(s5e8825_isp_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_mcsc_vclks, ARRAY_SIZE(s5e8825_mcsc_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_mfc_vclks, ARRAY_SIZE(s5e8825_mfc_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_npu0_vclks, ARRAY_SIZE(s5e8825_npu0_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_npus_vclks, ARRAY_SIZE(s5e8825_npus_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_peri_vclks, ARRAY_SIZE(s5e8825_peri_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_taa_vclks, ARRAY_SIZE(s5e8825_taa_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_tnr_vclks, ARRAY_SIZE(s5e8825_tnr_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_vts_vclks, ARRAY_SIZE(s5e8825_vts_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_usb_vclks, ARRAY_SIZE(s5e8825_usb_vclks));
|
|
samsung_register_vclk(s5e8825_clk_provider, s5e8825_clkout_vclks, ARRAY_SIZE(s5e8825_clkout_vclks));
|
|
|
|
clk_register_fixed_factor(NULL, "pwm-clock", "fin_pll", CLK_SET_RATE_PARENT, 1, 1);
|
|
|
|
samsung_clk_of_add_provider(np, s5e8825_clk_provider);
|
|
|
|
s5e8825_vclk_init();
|
|
|
|
pr_info("s5e8825: Clock setup completed\n");
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id of_exynos_clock_match[] = {
|
|
{ .compatible = "samsung,s5e8825-clock", },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, of_exynos_clock_match);
|
|
|
|
static const struct platform_device_id exynos_clock_ids[] = {
|
|
{ "s5e8825-clock", },
|
|
{ }
|
|
};
|
|
|
|
static struct platform_driver s5e8825_clock_driver = {
|
|
.driver = {
|
|
.name = "s5e8825_clock",
|
|
.of_match_table = of_exynos_clock_match,
|
|
},
|
|
.probe = s5e8825_clock_probe,
|
|
.id_table = exynos_clock_ids,
|
|
};
|
|
|
|
static int s5e8825_clock_init(void)
|
|
{
|
|
return platform_driver_register(&s5e8825_clock_driver);
|
|
}
|
|
arch_initcall(s5e8825_clock_init);
|
|
|
|
static void s5e8825_clock_exit(void)
|
|
{
|
|
return platform_driver_unregister(&s5e8825_clock_driver);
|
|
}
|
|
module_exit(s5e8825_clock_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|