/* * Copyright (c) 2018 Samsung Electronics Co., Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * Device Tree binding constants for S5E8825 clock controller. */ #ifndef _DT_BINDINGS_CLOCK_S5E8825_H #define _DT_BINDINGS_CLOCK_S5E8825_H #define NONE (0 + 0) #define OSCCLK (0 + 1) //*********************************ALIVE****************************** #define CLK_ALIVE_BASE (10) #define GATE_ALIVE_CMU_ALIVE_QCH (CLK_ALIVE_BASE + 0) #define GATE_APBIF_CHUB_RTC_QCH (CLK_ALIVE_BASE + 1) #define GATE_APBIF_GPIO_ALIVE_QCH (CLK_ALIVE_BASE + 2) #define GATE_APBIF_PMU_ALIVE_QCH (CLK_ALIVE_BASE + 3) #define GATE_APBIF_RTC_QCH (CLK_ALIVE_BASE + 4) #define GATE_APBIF_SYSREG_VGPIO2AP_QCH (CLK_ALIVE_BASE + 5) #define GATE_APBIF_SYSREG_VGPIO2APM_QCH (CLK_ALIVE_BASE + 6) #define GATE_APBIF_SYSREG_VGPIO2PMU_QCH (CLK_ALIVE_BASE + 7) #define GATE_APBIF_TOP_RTC_QCH (CLK_ALIVE_BASE + 8) #define GATE_DBGCORE_UART_QCH (CLK_ALIVE_BASE + 9) #define GATE_D_TZPC_ALIVE_QCH (CLK_ALIVE_BASE + 10) #define GATE_GREBEINTEGRATION_QCH_GREBE (CLK_ALIVE_BASE + 11) #define GATE_GREBEINTEGRATION_QCH_DBG (CLK_ALIVE_BASE + 12) #define GATE_HW_SCANDUMP_CLKSTOP_CTRL_QCH (CLK_ALIVE_BASE + 13) #define GATE_I2C_ALIVE0_QCH (CLK_ALIVE_BASE + 14) #define GATE_I3C_APM_PMIC_QCH_P (CLK_ALIVE_BASE + 15) #define GATE_I3C_APM_PMIC_QCH_S (CLK_ALIVE_BASE + 16) #define GATE_INTMEM_QCH (CLK_ALIVE_BASE + 17) #define GATE_MAILBOX_APM_AP_QCH (CLK_ALIVE_BASE + 18) #define GATE_MAILBOX_APM_CHUB_QCH (CLK_ALIVE_BASE + 19) #define GATE_MAILBOX_APM_CP_QCH (CLK_ALIVE_BASE + 20) #define GATE_MAILBOX_APM_GNSS_QCH (CLK_ALIVE_BASE + 21) #define GATE_MAILBOX_APM_VTS_QCH (CLK_ALIVE_BASE + 22) #define GATE_MAILBOX_APM_WLBT_QCH (CLK_ALIVE_BASE + 23) #define GATE_MAILBOX_AP_CHUB_QCH (CLK_ALIVE_BASE + 24) #define GATE_MAILBOX_AP_CP_QCH (CLK_ALIVE_BASE + 25) #define GATE_MAILBOX_AP_CP_S_QCH (CLK_ALIVE_BASE + 26) #define GATE_MAILBOX_AP_DBGCORE_QCH (CLK_ALIVE_BASE + 27) #define GATE_MAILBOX_AP_GNSS_QCH (CLK_ALIVE_BASE + 28) #define GATE_MAILBOX_AP_WLBT_BT_QCH (CLK_ALIVE_BASE + 29) #define GATE_MAILBOX_AP_WLBT_WL_QCH (CLK_ALIVE_BASE + 30) #define GATE_MAILBOX_CP_CHUB_QCH (CLK_ALIVE_BASE + 31) #define GATE_MAILBOX_CP_GNSS_QCH (CLK_ALIVE_BASE + 32) #define GATE_MAILBOX_CP_WLBT_BT_QCH (CLK_ALIVE_BASE + 33) #define GATE_MAILBOX_CP_WLBT_WL_QCH (CLK_ALIVE_BASE + 34) #define GATE_MAILBOX_GNSS_CHUB_QCH (CLK_ALIVE_BASE + 35) #define GATE_MAILBOX_GNSS_WLBT_QCH (CLK_ALIVE_BASE + 36) #define GATE_MAILBOX_SHARED_SRAM_QCH (CLK_ALIVE_BASE + 37) #define GATE_MAILBOX_VTS_CHUB_QCH (CLK_ALIVE_BASE + 38) #define GATE_MAILBOX_WLBT_ABOX_QCH (CLK_ALIVE_BASE + 39) #define GATE_MAILBOX_WLBT_CHUB_QCH (CLK_ALIVE_BASE + 40) #define GATE_PMU_INTR_GEN_QCH (CLK_ALIVE_BASE + 41) #define GATE_ROM_CRC32_HOST_QCH (CLK_ALIVE_BASE + 42) #define GATE_RSTNSYNC_CLK_ALIVE_GREBE_QCH (CLK_ALIVE_BASE + 43) #define GATE_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH (CLK_ALIVE_BASE + 44) #define GATE_SLH_AXI_MI_C_CHUBVTS_QCH (CLK_ALIVE_BASE + 45) #define GATE_SLH_AXI_MI_C_GNSS_QCH (CLK_ALIVE_BASE + 46) #define GATE_SLH_AXI_MI_C_MODEM_QCH (CLK_ALIVE_BASE + 47) #define GATE_SLH_AXI_MI_C_WLBT_QCH (CLK_ALIVE_BASE + 48) #define GATE_SLH_AXI_MI_P_APM_QCH (CLK_ALIVE_BASE + 49) #define GATE_SLH_AXI_SI_C_CMGP_QCH (CLK_ALIVE_BASE + 50) #define GATE_SLH_AXI_SI_D_APM_QCH (CLK_ALIVE_BASE + 51) #define GATE_SLH_AXI_SI_G_DBGCORE_QCH (CLK_ALIVE_BASE + 52) #define GATE_SLH_AXI_SI_G_SCAN2DRAM_QCH (CLK_ALIVE_BASE + 53) #define GATE_SLH_AXI_SI_LP_CHUBVTS_QCH (CLK_ALIVE_BASE + 54) #define GATE_SS_DBGCORE_QCH_GREBE (CLK_ALIVE_BASE + 55) #define GATE_SS_DBGCORE_QCH_DBG (CLK_ALIVE_BASE + 56) #define GATE_SYSREG_ALIVE_QCH (CLK_ALIVE_BASE + 57) #define GATE_USI_ALIVE0_QCH (CLK_ALIVE_BASE + 58) #define GATE_VGEN_LITE_ALIVE_QCH (CLK_ALIVE_BASE + 59) #define GATE_WDT_ALIVE_QCH (CLK_ALIVE_BASE + 60) #define DOUT_DIV_CLK_ALIVE_USI0 (CLK_ALIVE_BASE + 61) #define DOUT_DIV_CLK_ALIVE_I2C (CLK_ALIVE_BASE + 62) #define DOUT_DIV_CLK_ALIVE_I3C_PMIC (CLK_ALIVE_BASE + 63) #define DOUT_DIV_CLK_ALIVE_DBGCORE_UART (CLK_ALIVE_BASE + 64) #define DOUT_DIV_CLK_ALIVE_BUS (CLK_ALIVE_BASE + 65) #define DOUT_CLKCMU_CMGP_BUS (CLK_ALIVE_BASE + 66) #define DOUT_CLKCMU_CMGP_PERI (CLK_ALIVE_BASE + 67) #define DOUT_CLKCMU_CHUBVTS_BUS (CLK_ALIVE_BASE + 68) #define DOUT_CLKCMU_CHUB_PERI (CLK_ALIVE_BASE + 69) // **************************AUD************************ #define CLK_AUD_BASE (100) #define GATE_ABOX_QCH_ACLK (CLK_AUD_BASE + 1) #define GATE_ABOX_QCH_BCLK_DSIF (CLK_AUD_BASE + 2) #define GATE_ABOX_QCH_BCLK0 (CLK_AUD_BASE + 3) #define GATE_ABOX_QCH_BCLK1 (CLK_AUD_BASE + 4) #define GATE_ABOX_QCH_BCLK2 (CLK_AUD_BASE + 5) #define GATE_ABOX_QCH_BCLK3 (CLK_AUD_BASE + 6) #define GATE_ABOX_QCH_BCLK4 (CLK_AUD_BASE + 7) #define GATE_ABOX_QCH_CNT (CLK_AUD_BASE + 8) #define GATE_ABOX_QCH_CCLK_ASB (CLK_AUD_BASE + 9) #define GATE_ABOX_QCH_BCLK5 (CLK_AUD_BASE + 10) #define GATE_ABOX_QCH_BCLK6 (CLK_AUD_BASE + 11) #define GATE_ABOX_QCH_CPU (CLK_AUD_BASE + 12) #define GATE_ABOX_QCH_PCMC_CLK (CLK_AUD_BASE + 13) #define GATE_ABOX_QCH_C2A0 (CLK_AUD_BASE + 14) #define GATE_ABOX_QCH_C2A1 (CLK_AUD_BASE + 15) #define GATE_ABOX_QCH_XCLK0 (CLK_AUD_BASE + 16) #define GATE_ABOX_QCH_XCLK1 (CLK_AUD_BASE + 17) #define GATE_ABOX_QCH_XCLK2 (CLK_AUD_BASE + 18) #define GATE_ABOX_QCH_CPU0 (CLK_AUD_BASE + 19) #define GATE_ABOX_QCH_CPU1 (CLK_AUD_BASE + 20) #define GATE_ABOX_QCH_NEON0 (CLK_AUD_BASE + 21) #define GATE_ABOX_QCH_NEON1 (CLK_AUD_BASE + 22) #define GATE_ABOX_QCH_L2 (CLK_AUD_BASE + 23) #define GATE_ABOX_QCH_CCLK_ACP (CLK_AUD_BASE + 24) #define GATE_AUD_CMU_AUD_QCH (CLK_AUD_BASE + 25) #define GATE_DFTMUX_AUD_QCH (CLK_AUD_BASE + 26) #define GATE_D_TZPC_AUD_QCH (CLK_AUD_BASE + 27) #define GATE_LH_AXI_SI_D_AUD_QCH (CLK_AUD_BASE + 28) #define GATE_MAILBOX_AUD0_QCH (CLK_AUD_BASE + 29) #define GATE_MAILBOX_AUD1_QCH (CLK_AUD_BASE + 30) #define GATE_PPMU_AUD_QCH (CLK_AUD_BASE + 31) #define GATE_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH (CLK_AUD_BASE + 32) #define GATE_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH (CLK_AUD_BASE + 33) #define GATE_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH (CLK_AUD_BASE + 34) #define GATE_SLH_AXI_MI_D_USBAUD_QCH (CLK_AUD_BASE + 35) #define GATE_SLH_AXI_MI_P_AUD_QCH (CLK_AUD_BASE + 36) #define GATE_SYSMMU_AUD_QCH_S1 (CLK_AUD_BASE + 37) #define GATE_SYSMMU_AUD_QCH_S2 (CLK_AUD_BASE + 38) #define GATE_SYSREG_AUD_QCH (CLK_AUD_BASE + 39) #define GATE_VGEN_LITE_AUD_QCH (CLK_AUD_BASE + 40) #define GATE_WDT_AUD_QCH (CLK_AUD_BASE + 41) #define DOUT_CLKCMU_AUD_CPU (CLK_AUD_BASE + 42) #define DOUT_CLKCMU_AUD_BUS (CLK_AUD_BASE + 43) #define DOUT_DIV_CLK_AUD_CPU (CLK_AUD_BASE + 44) #define DOUT_DIV_CLK_AUD_CPU_ACLK (CLK_AUD_BASE + 45) #define DOUT_DIV_CLK_AUD_CPU_PCLKDBG (CLK_AUD_BASE + 46) #define DOUT_DIV_CLK_AUD_BUSD (CLK_AUD_BASE + 47) #define DOUT_DIV_CLK_AUD_BUSP (CLK_AUD_BASE + 48) #define DOUT_DIV_CLK_AUD_AUDIF (CLK_AUD_BASE + 49) #define DOUT_DIV_CLK_AUD_MCLK (CLK_AUD_BASE + 50) #define DOUT_DIV_CLK_AUD_CNT (CLK_AUD_BASE + 51) #define DOUT_DIV_CLK_AUD_DMIC (CLK_AUD_BASE + 52) #define DOUT_DIV_CLK_AUD_PCMC (CLK_AUD_BASE + 53) #define DOUT_DIV_CLK_AUD_DSIF (CLK_AUD_BASE + 54) #define DOUT_DIV_CLK_AUD_UAIF0 (CLK_AUD_BASE + 55) #define DOUT_DIV_CLK_AUD_UAIF1 (CLK_AUD_BASE + 56) #define DOUT_DIV_CLK_AUD_UAIF2 (CLK_AUD_BASE + 57) #define DOUT_DIV_CLK_AUD_UAIF3 (CLK_AUD_BASE + 58) #define DOUT_DIV_CLK_AUD_UAIF4 (CLK_AUD_BASE + 59) #define DOUT_DIV_CLK_AUD_UAIF5 (CLK_AUD_BASE + 60) #define DOUT_DIV_CLK_AUD_UAIF6 (CLK_AUD_BASE + 61) #define DOUT_DIV_CLK_AUD_FM_SPDY (CLK_AUD_BASE + 62) #define DOUT_DIV_CLK_AUD_FM (CLK_AUD_BASE + 63) #define DOUT_CLKAUD_USB_BUS (CLK_AUD_BASE + 64) //#define DOUT_CLKAUD_USB_USB31DRD (CLK_AUD_BASE + 64) #define UMUX_CLK_AUD_CPU_PLL (CLK_AUD_BASE + 65) #define UMUX_CLKCMU_AUD_CPU_USER (CLK_AUD_BASE + 66) #define UMUX_CLKCMU_AUD_BUS_USER (CLK_AUD_BASE + 67) #define MOUT_CLK_AUD_UAIF0 (CLK_AUD_BASE + 68) #define MOUT_CLK_AUD_UAIF1 (CLK_AUD_BASE + 69) #define MOUT_CLK_AUD_UAIF2 (CLK_AUD_BASE + 70) #define MOUT_CLK_AUD_UAIF3 (CLK_AUD_BASE + 71) #define MOUT_CLK_AUD_UAIF4 (CLK_AUD_BASE + 72) #define MOUT_CLK_AUD_UAIF5 (CLK_AUD_BASE + 73) #define MOUT_CLK_AUD_UAIF6 (CLK_AUD_BASE + 74) #define MOUT_CLK_AUD_PCMC (CLK_AUD_BASE + 75) #define UMUX_CP_PCMC_CLK_USER (CLK_AUD_BASE + 76) #define PLL_OUT_AUD (CLK_AUD_BASE + 77) #define UMUX_CLK_AUD_DMIC_BUS_USER (CLK_AUD_BASE + 78) #define MOUT_CLK_VTS_DMIC_IF (CLK_AUD_BASE + 79) //*********************************************BUSC**************************** #define CLK_BUSC_BASE (200) #define GATE_BUSC_CMU_BUSC_QCH (CLK_BUSC_BASE + 1) #define GATE_CMU_BUSC_CMUREF_QCH (CLK_BUSC_BASE + 2) #define GATE_D_TZPC_BUSC_QCH (CLK_BUSC_BASE + 3) #define GATE_LH_AXI_MI_D_CHUBVTS_QCH (CLK_BUSC_BASE + 4) #define GATE_LH_AXI_MI_D_MFC_QCH (CLK_BUSC_BASE + 5) #define GATE_PDMA_BUSC_QCH (CLK_BUSC_BASE + 6) #define GATE_SLH_AXI_MI_D_APM_QCH (CLK_BUSC_BASE + 7) #define GATE_SLH_AXI_MI_D_PERI_QCH (CLK_BUSC_BASE + 8) #define GATE_SLH_AXI_MI_D_USB_QCH (CLK_BUSC_BASE + 9) #define GATE_SLH_AXI_MI_P_BUSC_QCH (CLK_BUSC_BASE + 10) #define GATE_SPDMA_BUSC_QCH (CLK_BUSC_BASE + 11) #define GATE_SYSMMU_AXI_D_BUSC_QCH (CLK_BUSC_BASE + 12) #define GATE_SYSREG_BUSC_QCH (CLK_BUSC_BASE + 13) #define GATE_TREX_D_BUSC_QCH (CLK_BUSC_BASE + 14) #define GATE_VGEN_PDMA_QCH (CLK_BUSC_BASE + 15) #define GATE_VGEN_SPDMA_QCH (CLK_BUSC_BASE + 16) #define DOUT_CLKCMU_BUSC_BUS (CLK_BUSC_BASE + 17) #define DOUT_CLKCMU_CMU_BOOST (CLK_BUSC_BASE + 18) #define DOUT_DIV_CLK_BUSC_BUSP (CLK_BUSC_BASE + 19) //***********************************************CHUB******************* #define CLK_CHUB_BASE (250) #define GATE_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH (CLK_CHUB_BASE + 1) #define GATE_APBIF_GPIO_CHUB_QCH (CLK_CHUB_BASE + 2) #define GATE_APBIF_GPIO_CHUBEINT_QCH (CLK_CHUB_BASE + 3) #define GATE_CHUB_CMU_CHUB_QCH (CLK_CHUB_BASE + 4) #define GATE_CM4_CHUB_QCH_CPU (CLK_CHUB_BASE + 5) #define GATE_I2C_CHUB1_QCH (CLK_CHUB_BASE + 6) #define GATE_I2C_CHUB3_QCH (CLK_CHUB_BASE + 7) #define GATE_PWM_CHUB_QCH (CLK_CHUB_BASE + 8) #define GATE_SLH_AXI_MI_S_CHUB_QCH (CLK_CHUB_BASE + 9) #define GATE_SLH_AXI_SI_M_CHUB_QCH (CLK_CHUB_BASE + 10) #define GATE_SYSREG_CHUB_QCH (CLK_CHUB_BASE + 11) #define GATE_SYSREG_COMBINE_CHUB2AP_QCH (CLK_CHUB_BASE + 12) #define GATE_SYSREG_COMBINE_CHUB2APM_QCH (CLK_CHUB_BASE + 13) #define GATE_SYSREG_COMBINE_CHUB2WLBT_QCH (CLK_CHUB_BASE + 14) #define GATE_TIMER_CHUB_QCH (CLK_CHUB_BASE + 15) #define GATE_USI_CHUB0_QCH (CLK_CHUB_BASE + 16) #define GATE_USI_CHUB1_QCH (CLK_CHUB_BASE + 17) #define GATE_USI_CHUB2_QCH (CLK_CHUB_BASE + 18) #define GATE_USI_CHUB3_QCH (CLK_CHUB_BASE + 19) #define GATE_WDT_CHUB_QCH (CLK_CHUB_BASE + 20) #define GATE_BAAW_CHUB_QCH (CLK_CHUB_BASE + 21) #define GATE_BAAW_VTS_QCH (CLK_CHUB_BASE + 22) #define GATE_CHUBVTS_CMU_CHUBVTS_QCH (CLK_CHUB_BASE + 23) #define GATE_D_TZPC_CHUBVTS_QCH (CLK_CHUB_BASE + 24) #define GATE_LH_AXI_SI_D_CHUBVTS_QCH (CLK_CHUB_BASE + 25) #define GATE_SLH_AXI_MI_LP_CHUBVTS_QCH (CLK_CHUB_BASE + 26) #define GATE_SLH_AXI_MI_M_CHUB_QCH (CLK_CHUB_BASE + 27) #define GATE_SLH_AXI_MI_M_VTS_QCH (CLK_CHUB_BASE + 28) #define GATE_SLH_AXI_SI_C_CHUBVTS_QCH (CLK_CHUB_BASE + 29) #define GATE_SLH_AXI_SI_S_CHUB_QCH (CLK_CHUB_BASE + 30) #define GATE_SLH_AXI_SI_S_VTS_QCH (CLK_CHUB_BASE + 31) #define GATE_SWEEPER_C_CHUBVTS_QCH (CLK_CHUB_BASE + 32) #define GATE_SYSREG_CHUBVTS_QCH (CLK_CHUB_BASE + 33) #define GATE_VGEN_LITE_CHUBVTS_QCH (CLK_CHUB_BASE + 34) #define DOUT_DIV_CLK_CHUB_BUS (CLK_CHUB_BASE + 35) #define DOUT_DIV_CLK_CHUB_USI0 (CLK_CHUB_BASE + 36) #define DOUT_DIV_CLK_CHUB_USI1 (CLK_CHUB_BASE + 37) #define DOUT_DIV_CLK_CHUB_USI2 (CLK_CHUB_BASE + 38) #define DOUT_DIV_CLK_CHUB_I2C (CLK_CHUB_BASE + 39) #define DOUT_DIV_CLK_CHUB_USI3 (CLK_CHUB_BASE + 40) #define DOUT_DIV_CLK_CHUBVTS_BUS (CLK_CHUB_BASE + 41) //***********************************CMGP***************************** #define CLK_CMGP_BASE (300) #define GATE_CMGP_CMU_CMGP_QCH (CLK_CMGP_BASE + 1) #define GATE_D_TZPC_CMGP_QCH (CLK_CMGP_BASE + 2) #define GATE_GPIO_CMGP_QCH (CLK_CMGP_BASE + 3) #define GATE_I2C_CMGP0_QCH (CLK_CMGP_BASE + 4) #define GATE_I2C_CMGP1_QCH (CLK_CMGP_BASE + 5) #define GATE_I2C_CMGP2_QCH (CLK_CMGP_BASE + 6) #define GATE_I2C_CMGP3_QCH (CLK_CMGP_BASE + 7) #define GATE_I2C_CMGP4_QCH (CLK_CMGP_BASE + 8) #define GATE_I3C_CMGP_QCH_P (CLK_CMGP_BASE + 9) #define GATE_I3C_CMGP_QCH_S (CLK_CMGP_BASE + 10) #define GATE_SLH_AXI_MI_C_CMGP_QCH (CLK_CMGP_BASE + 11) #define GATE_SYSREG_CMGP_QCH (CLK_CMGP_BASE + 12) #define GATE_SYSREG_CMGP2APM_QCH (CLK_CMGP_BASE + 13) #define GATE_SYSREG_CMGP2CHUB_QCH (CLK_CMGP_BASE + 14) #define GATE_SYSREG_CMGP2CP_QCH (CLK_CMGP_BASE + 15) #define GATE_SYSREG_CMGP2GNSS_QCH (CLK_CMGP_BASE + 16) #define GATE_SYSREG_CMGP2PMU_AP_QCH (CLK_CMGP_BASE + 17) #define GATE_SYSREG_CMGP2WLBT_QCH (CLK_CMGP_BASE + 18) #define GATE_USI_CMGP0_QCH (CLK_CMGP_BASE + 19) #define GATE_USI_CMGP1_QCH (CLK_CMGP_BASE + 20) #define GATE_USI_CMGP2_QCH (CLK_CMGP_BASE + 21) #define GATE_USI_CMGP3_QCH (CLK_CMGP_BASE + 22) #define GATE_USI_CMGP4_QCH (CLK_CMGP_BASE + 23) #define DOUT_DIV_CLK_CMGP_USI0 (CLK_CMGP_BASE + 24) #define DOUT_DIV_CLK_CMGP_USI4 (CLK_CMGP_BASE + 25) #define DOUT_DIV_CLK_CMGP_I2C (CLK_CMGP_BASE + 26) #define DOUT_DIV_CLK_CMGP_ADC (CLK_CMGP_BASE + 27) //#define DOUT_CLKCMU_CMGP_BUS (CLK_CMGP_BASE + 28) #define DOUT_DIV_CLK_CMGP_I3C (CLK_CMGP_BASE + 28) #define DOUT_DIV_CLK_CMGP_USI1 (CLK_CMGP_BASE + 29) #define DOUT_DIV_CLK_CMGP_USI2 (CLK_CMGP_BASE + 30) #define DOUT_DIV_CLK_CMGP_USI3 (CLK_CMGP_BASE + 31) //*************************TOP******************** #define CLK_TOP_BASE (350) #define GATE_CMU_CMU_CMUREF_QCH (CLK_TOP_BASE + 1) #define GATE_DFTMUX_TOP_QCH_CIS_CLK0 (CLK_TOP_BASE + 2) #define GATE_DFTMUX_TOP_QCH_CIS_CLK1 (CLK_TOP_BASE + 3) #define GATE_DFTMUX_TOP_QCH_CIS_CLK2 (CLK_TOP_BASE + 4) #define GATE_DFTMUX_TOP_QCH_CIS_CLK3 (CLK_TOP_BASE + 5) #define GATE_DFTMUX_TOP_QCH_CIS_CLK4 (CLK_TOP_BASE + 6) #define GATE_DFTMUX_TOP_QCH_CIS_CLK5 (CLK_TOP_BASE + 7) #define GATE_OTP_QCH (CLK_TOP_BASE + 8) #define DOUT_CLKCMU_OTP (CLK_TOP_BASE + 9) #define DOUT_CLKCMU_CIS_CLK0 (CLK_TOP_BASE + 10) #define DOUT_CLKCMU_CIS_CLK1 (CLK_TOP_BASE + 11) #define DOUT_CLKCMU_CIS_CLK2 (CLK_TOP_BASE + 12) #define DOUT_CLKCMU_CIS_CLK3 (CLK_TOP_BASE + 13) #define DOUT_CLKCMU_CIS_CLK4 (CLK_TOP_BASE + 14) #define DOUT_CLKCMU_CIS_CLK5 (CLK_TOP_BASE + 15) #define DOUT_CLKCMU_HPM (CLK_TOP_BASE + 16) //***************************CORE********************** #define CLK_CORE_BASE (400) #define GATE_ADM_APB_G_BDU_QCH (CLK_CORE_BASE + 1) #define GATE_BAAW_D_SSS_QCH (CLK_CORE_BASE + 2) #define GATE_BAAW_P_GNSS_QCH (CLK_CORE_BASE + 3) #define GATE_BAAW_P_MODEM_QCH (CLK_CORE_BASE + 4) #define GATE_BAAW_P_WLBT_QCH (CLK_CORE_BASE + 5) #define GATE_BDU_QCH (CLK_CORE_BASE + 6) #define GATE_CMU_CORE_CMUREF_QCH (CLK_CORE_BASE + 7) #define GATE_CORE_CMU_CORE_QCH (CLK_CORE_BASE + 8) #define GATE_DIT_QCH (CLK_CORE_BASE + 9) #define GATE_D_TZPC_CORE_QCH (CLK_CORE_BASE + 10) #define GATE_GIC_QCH (CLK_CORE_BASE + 11) #define GATE_HW_APBSEMA_MEC_QCH (CLK_CORE_BASE + 12) #define GATE_LH_AST_MI_G_CPU_QCH (CLK_CORE_BASE + 13) #define GATE_LH_AXI_MI_D0_DPU_QCH (CLK_CORE_BASE + 14) #define GATE_LH_AXI_MI_D0_NPUS_QCH (CLK_CORE_BASE + 15) #define GATE_LH_AXI_MI_D1_DPU_QCH (CLK_CORE_BASE + 16) #define GATE_LH_AXI_MI_D1_NPUS_QCH (CLK_CORE_BASE + 17) #define GATE_LH_AXI_MI_D_AUD_QCH (CLK_CORE_BASE + 18) #define GATE_LH_AXI_MI_D_G3D_QCH (CLK_CORE_BASE + 19) #define GATE_LH_AXI_MI_D_M2M_QCH (CLK_CORE_BASE + 20) #define GATE_LH_AXI_MI_D_SSS_QCH (CLK_CORE_BASE + 21) #define GATE_LH_AXI_SI_D0_MIF_CP_QCH (CLK_CORE_BASE + 22) #define GATE_LH_AXI_SI_D0_MIF_NRT_QCH (CLK_CORE_BASE + 23) #define GATE_LH_AXI_SI_D0_MIF_RT_QCH (CLK_CORE_BASE + 24) #define GATE_LH_AXI_SI_D1_MIF_CP_QCH (CLK_CORE_BASE + 25) #define GATE_LH_AXI_SI_D1_MIF_NRT_QCH (CLK_CORE_BASE + 26) #define GATE_LH_AXI_SI_D1_MIF_RT_QCH (CLK_CORE_BASE + 27) #define GATE_LH_AXI_SI_D_SSS_QCH (CLK_CORE_BASE + 28) #define GATE_PUF_QCH (CLK_CORE_BASE + 29) #define GATE_RSTNSYNC_I_ARESETN_SSS_QCH (CLK_CORE_BASE + 30) #define GATE_SFR_APBIF_CMU_TOPC_QCH (CLK_CORE_BASE + 31) #define GATE_SIREX_QCH (CLK_CORE_BASE + 32) #define GATE_SLH_AXI_MI_D0_MODEM_QCH (CLK_CORE_BASE + 33) #define GATE_SLH_AXI_MI_D1_MODEM_QCH (CLK_CORE_BASE + 34) #define GATE_SLH_AXI_MI_D_GNSS_QCH (CLK_CORE_BASE + 35) #define GATE_SLH_AXI_MI_D_HSI_QCH (CLK_CORE_BASE + 36) #define GATE_SLH_AXI_MI_D_WLBT_QCH (CLK_CORE_BASE + 37) #define GATE_SLH_AXI_MI_G_CSSYS_QCH (CLK_CORE_BASE + 38) #define GATE_SLH_AXI_MI_P_CLUSTER0_QCH (CLK_CORE_BASE + 39) #define GATE_SLH_AXI_SI_P_APM_QCH (CLK_CORE_BASE + 40) #define GATE_SLH_AXI_SI_P_AUD_QCH (CLK_CORE_BASE + 41) #define GATE_SLH_AXI_SI_P_BUSC_QCH (CLK_CORE_BASE + 42) #define GATE_SLH_AXI_SI_P_CPUCL0_QCH (CLK_CORE_BASE + 43) #define GATE_SLH_AXI_SI_P_CSIS_QCH (CLK_CORE_BASE + 44) #define GATE_SLH_AXI_SI_P_DPU_QCH (CLK_CORE_BASE + 45) #define GATE_SLH_AXI_SI_P_G3D_QCH (CLK_CORE_BASE + 46) #define GATE_SLH_AXI_SI_P_GNSS_QCH (CLK_CORE_BASE + 47) #define GATE_SLH_AXI_SI_P_HSI_QCH (CLK_CORE_BASE + 48) #define GATE_SLH_AXI_SI_P_ISP_QCH (CLK_CORE_BASE + 49) #define GATE_SLH_AXI_SI_P_M2M_QCH (CLK_CORE_BASE + 50) #define GATE_SLH_AXI_SI_P_MCSC_QCH (CLK_CORE_BASE + 51) #define GATE_SLH_AXI_SI_P_MCW_QCH (CLK_CORE_BASE + 52) #define GATE_SLH_AXI_SI_P_MFC_QCH (CLK_CORE_BASE + 53) #define GATE_SLH_AXI_SI_P_MIF0_QCH (CLK_CORE_BASE + 54) #define GATE_SLH_AXI_SI_P_MIF1_QCH (CLK_CORE_BASE + 55) #define GATE_SLH_AXI_SI_P_MODEM_QCH (CLK_CORE_BASE + 56) #define GATE_SLH_AXI_SI_P_NPU0_QCH (CLK_CORE_BASE + 57) #define GATE_SLH_AXI_SI_P_NPUS_QCH (CLK_CORE_BASE + 58) #define GATE_SLH_AXI_SI_P_PERI_QCH (CLK_CORE_BASE + 59) #define GATE_SLH_AXI_SI_P_TAA_QCH (CLK_CORE_BASE + 60) #define GATE_SLH_AXI_SI_P_TNR_QCH (CLK_CORE_BASE + 61) #define GATE_SLH_AXI_SI_P_USB_QCH (CLK_CORE_BASE + 62) #define GATE_SLH_AXI_SI_P_WLBT_QCH (CLK_CORE_BASE + 63) #define GATE_SSS_QCH (CLK_CORE_BASE + 64) #define GATE_SYSMMU_ACEL_D2_MODEM_QCH (CLK_CORE_BASE + 65) #define GATE_SYSMMU_ACEL_D_DIT_QCH (CLK_CORE_BASE + 66) #define GATE_SYSREG_CORE_QCH (CLK_CORE_BASE + 67) #define GATE_TREX_D_CORE_QCH (CLK_CORE_BASE + 68) #define GATE_TREX_D_NRT_QCH (CLK_CORE_BASE + 69) #define GATE_TREX_P_CORE_QCH (CLK_CORE_BASE + 70) #define GATE_VGEN_LITE_CORE_QCH (CLK_CORE_BASE + 71) #define GATE_CMU_CPUCL0_CMUREF_QCH (CLK_CORE_BASE + 72) #define GATE_CMU_CPUCL0_SHORTSTOP_QCH (CLK_CORE_BASE + 73) #define GATE_CPUCL0_QCH (CLK_CORE_BASE + 74) #define GATE_CPUCL0_CMU_CPUCL0_QCH (CLK_CORE_BASE + 75) #define GATE_HTU_CPUCL0_QCH_PCLK (CLK_CORE_BASE + 76) #define GATE_HTU_CPUCL0_QCH_CLK (CLK_CORE_BASE + 77) #define GATE_BPS_CPUCL0_QCH (CLK_CORE_BASE + 78) #define GATE_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH (CLK_CORE_BASE + 79) #define GATE_CSSYS_QCH (CLK_CORE_BASE + 80) #define GATE_D_TZPC_CPUCL0_QCH (CLK_CORE_BASE + 81) #define GATE_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH (CLK_CORE_BASE + 82) #define GATE_SECJTAG_QCH (CLK_CORE_BASE + 83) #define GATE_SLH_AXI_MI_G_DBGCORE_QCH (CLK_CORE_BASE + 84) #define GATE_SLH_AXI_MI_G_INT_CSSYS_QCH (CLK_CORE_BASE + 85) #define GATE_SLH_AXI_MI_G_INT_DBGCORE_QCH (CLK_CORE_BASE + 86) #define GATE_SLH_AXI_MI_P_CPUCL0_QCH (CLK_CORE_BASE + 87) #define GATE_SLH_AXI_SI_G_CSSYS_QCH (CLK_CORE_BASE + 88) #define GATE_SLH_AXI_SI_G_INT_CSSYS_QCH (CLK_CORE_BASE + 89) #define GATE_SLH_AXI_SI_G_INT_DBGCORE_QCH (CLK_CORE_BASE + 90) #define GATE_SYSREG_CPUCL0_QCH (CLK_CORE_BASE + 91) #define GATE_CMU_CPUCL1_CMUREF_QCH (CLK_CORE_BASE + 92) #define GATE_CMU_CPUCL1_SHORTSTOP_QCH (CLK_CORE_BASE + 93) #define GATE_CPUCL1_QCH_BIG (CLK_CORE_BASE + 94) #define GATE_CPUCL1_QCH_DDD_HC0 (CLK_CORE_BASE + 95) #define GATE_CPUCL1_QCH_DDD_HC1 (CLK_CORE_BASE + 96) #define GATE_CPUCL1_CMU_CPUCL1_QCH (CLK_CORE_BASE + 97) #define GATE_HTU_CPUCL1_QCH_PCLK (CLK_CORE_BASE + 98) #define GATE_HTU_CPUCL1_QCH_CLK (CLK_CORE_BASE + 99) #define DOUT_DIV_CLK_CORE_BUSP (CLK_CORE_BASE + 100) #define DOUT_CLKCMU_CORE_G3D (CLK_CORE_BASE + 101) #define DOUT_CLKCMU_CORE_SSS (CLK_CORE_BASE + 102) //CSIS #define CLK_CSIS_BASE (520) #define GATE_CSIS_CMU_CSIS_QCH (CLK_CSIS_BASE + 1) #define GATE_CSIS_PDP_QCH_VOTF0 (CLK_CSIS_BASE + 2) #define GATE_CSIS_PDP_QCH_DMA (CLK_CSIS_BASE + 3) #define GATE_CSIS_PDP_QCH_PDP_TOP (CLK_CSIS_BASE + 4) #define GATE_CSIS_PDP_QCH_MCB (CLK_CSIS_BASE + 5) #define GATE_CSIS_PDP_QCH_VOTF1 (CLK_CSIS_BASE + 6) #define GATE_CSIS_PDP_QCH_C2_PDP (CLK_CSIS_BASE + 7) #define GATE_D_TZPC_CSIS_QCH (CLK_CSIS_BASE + 8) #define GATE_LH_AST_MI_SOTF0_TAACSIS_QCH (CLK_CSIS_BASE + 9) #define GATE_LH_AST_MI_SOTF1_TAACSIS_QCH (CLK_CSIS_BASE + 10) #define GATE_LH_AST_MI_SOTF2_TAACSIS_QCH (CLK_CSIS_BASE + 11) #define GATE_LH_AST_MI_ZOTF0_TAACSIS_QCH (CLK_CSIS_BASE + 12) #define GATE_LH_AST_MI_ZOTF1_TAACSIS_QCH (CLK_CSIS_BASE + 13) #define GATE_LH_AST_MI_ZOTF2_TAACSIS_QCH (CLK_CSIS_BASE + 14) #define GATE_LH_AST_SI_OTF0_CSISTAA_QCH (CLK_CSIS_BASE + 15) #define GATE_LH_AST_SI_OTF1_CSISTAA_QCH (CLK_CSIS_BASE + 16) #define GATE_LH_AST_SI_OTF2_CSISTAA_QCH (CLK_CSIS_BASE + 17) #define GATE_LH_AXI_SI_D0_CSIS_QCH (CLK_CSIS_BASE + 18) #define GATE_LH_AXI_SI_D1_CSIS_QCH (CLK_CSIS_BASE + 19) #define GATE_LH_AXI_SI_D2_CSIS_QCH (CLK_CSIS_BASE + 20) #define GATE_LH_AXI_SI_D3_CSIS_QCH (CLK_CSIS_BASE + 21) #define GATE_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0 (CLK_CSIS_BASE + 22) #define GATE_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1 (CLK_CSIS_BASE + 23) #define GATE_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2 (CLK_CSIS_BASE + 24) #define GATE_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3 (CLK_CSIS_BASE + 25) #define GATE_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4 (CLK_CSIS_BASE + 26) #define GATE_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5 (CLK_CSIS_BASE + 27) #define GATE_PPMU_CSIS_D0_QCH (CLK_CSIS_BASE + 28) #define GATE_PPMU_CSIS_D1_QCH (CLK_CSIS_BASE + 29) #define GATE_PPMU_CSIS_D2_QCH (CLK_CSIS_BASE + 30) #define GATE_PPMU_CSIS_D3_QCH (CLK_CSIS_BASE + 31) #define GATE_QE_CSIS_DMA0_QCH (CLK_CSIS_BASE + 32) #define GATE_QE_CSIS_DMA1_QCH (CLK_CSIS_BASE + 33) #define GATE_QE_CSIS_DMA2_QCH (CLK_CSIS_BASE + 34) #define GATE_QE_CSIS_DMA3_QCH (CLK_CSIS_BASE + 35) #define GATE_QE_PDP_AF0_QCH (CLK_CSIS_BASE + 36) #define GATE_QE_PDP_AF1_QCH (CLK_CSIS_BASE + 37) #define GATE_QE_PDP_AF2_QCH (CLK_CSIS_BASE + 38) #define GATE_QE_PDP_STAT_IMG0_QCH (CLK_CSIS_BASE + 39) #define GATE_QE_PDP_STAT_IMG1_QCH (CLK_CSIS_BASE + 40) #define GATE_QE_PDP_STAT_IMG2_QCH (CLK_CSIS_BASE + 41) #define GATE_QE_STRP0_QCH (CLK_CSIS_BASE + 42) #define GATE_QE_STRP1_QCH (CLK_CSIS_BASE + 43) #define GATE_QE_STRP2_QCH (CLK_CSIS_BASE + 44) #define GATE_QE_ZSL0_QCH (CLK_CSIS_BASE + 45) #define GATE_QE_ZSL1_QCH (CLK_CSIS_BASE + 46) #define GATE_QE_ZSL2_QCH (CLK_CSIS_BASE + 47) #define GATE_SLH_AXI_MI_P_CSIS_QCH (CLK_CSIS_BASE + 48) #define GATE_SYSMMU_D0_CSIS_QCH_S1 (CLK_CSIS_BASE + 49) #define GATE_SYSMMU_D0_CSIS_QCH_S2 (CLK_CSIS_BASE + 50) #define GATE_SYSMMU_D1_CSIS_QCH_S1 (CLK_CSIS_BASE + 51) #define GATE_SYSMMU_D1_CSIS_QCH_S2 (CLK_CSIS_BASE + 52) #define GATE_SYSMMU_D2_CSIS_QCH_S1 (CLK_CSIS_BASE + 53) #define GATE_SYSMMU_D2_CSIS_QCH_S2 (CLK_CSIS_BASE + 54) #define GATE_SYSMMU_D3_CSIS_QCH_S2 (CLK_CSIS_BASE + 55) #define GATE_SYSMMU_D3_CSIS_QCH_S1 (CLK_CSIS_BASE + 56) #define GATE_SYSREG_CSIS_QCH (CLK_CSIS_BASE + 57) #define GATE_VGEN_LITE0_CSIS_QCH (CLK_CSIS_BASE + 58) #define GATE_VGEN_LITE1_CSIS_QCH (CLK_CSIS_BASE + 59) #define GATE_VGEN_LITE2_CSIS_QCH (CLK_CSIS_BASE + 60) #define DOUT_CLKCMU_CSIS_BUS (CLK_CSIS_BASE + 61) #define DOUT_DIV_CLK_CSIS_BUSP (CLK_CSIS_BASE + 62) //DPU #define CLK_DPU_BASE (600) #define GATE_DPU_QCH_DPU (CLK_DPU_BASE + 1) #define GATE_DPU_QCH_DPU_DMA (CLK_DPU_BASE + 2) #define GATE_DPU_QCH_DPU_DPP (CLK_DPU_BASE + 3) #define GATE_DPU_QCH_DPU_C2SERV (CLK_DPU_BASE + 4) #define GATE_DPU_QCH (CLK_DPU_BASE + 5) #define GATE_DPU_CMU_DPU_QCH (CLK_DPU_BASE + 6) #define GATE_D_TZPC_DPU_QCH (CLK_DPU_BASE + 7) #define GATE_LH_AXI_SI_D0_DPU_QCH (CLK_DPU_BASE + 8) #define GATE_LH_AXI_SI_D1_DPU_QCH (CLK_DPU_BASE + 9) #define GATE_PPMU_D0_DPU_QCH (CLK_DPU_BASE + 10) #define GATE_PPMU_D1_DPU_QCH (CLK_DPU_BASE + 11) #define GATE_SLH_AXI_MI_P_DPU_QCH (CLK_DPU_BASE + 12) #define GATE_SYSMMU_AXI_D0_DPU_QCH_S1 (CLK_DPU_BASE + 13) #define GATE_SYSMMU_AXI_D0_DPU_QCH_S2 (CLK_DPU_BASE + 14) #define GATE_SYSMMU_AXI_D1_DPU_QCH_S1 (CLK_DPU_BASE + 15) #define GATE_SYSMMU_AXI_D1_DPU_QCH_S2 (CLK_DPU_BASE + 16) #define GATE_SYSREG_DPU_QCH (CLK_DPU_BASE + 17) #define GATE_CLUSTER0_QCH_SCLK (CLK_DPU_BASE + 18) #define GATE_CLUSTER0_QCH_ATCLK (CLK_DPU_BASE + 19) #define GATE_CLUSTER0_QCH_GIC (CLK_DPU_BASE + 20) #define GATE_CLUSTER0_QCH_DBG_PD (CLK_DPU_BASE + 21) #define GATE_CLUSTER0_QCH_PCLK (CLK_DPU_BASE + 22) #define GATE_CLUSTER0_QCH_PERIPHCLK (CLK_DPU_BASE + 23) #define GATE_CLUSTER0_QCH_PDBGCLK (CLK_DPU_BASE + 24) #define DOUT_DIV_CLK_DPU_BUSP (CLK_DPU_BASE + 25) #define DOUT_CLKCMU_DPU_BUS (CLK_DPU_BASE + 26) #define DOUT_CLKCMU_DPU_DSIM (CLK_DPU_BASE + 27) //DSU #define CLK_DSU_BASE (650) #define GATE_CMU_DSU_CMUREF_QCH (CLK_DSU_BASE + 1) #define GATE_CMU_DSU_SHORTSTOP_QCH (CLK_DSU_BASE + 2) #define GATE_DSU_CMU_DSU_QCH (CLK_DSU_BASE + 3) #define GATE_HTU_DSU_QCH_PCLK (CLK_DSU_BASE + 4) #define GATE_HTU_DSU_QCH_CLK (CLK_DSU_BASE + 5) #define GATE_LH_AST_SI_G_CPU_QCH (CLK_DSU_BASE + 6) #define GATE_LH_AXI_SI_D0_MIF_CPU_QCH (CLK_DSU_BASE + 7) #define GATE_LH_AXI_SI_D1_MIF_CPU_QCH (CLK_DSU_BASE + 8) #define GATE_PPC_INSTRRET_CLUSTER0_0_QCH (CLK_DSU_BASE + 9) #define GATE_PPC_INSTRRET_CLUSTER0_1_QCH (CLK_DSU_BASE + 10) #define GATE_PPC_INSTRRUN_CLUSTER0_0_QCH (CLK_DSU_BASE + 11) #define GATE_PPC_INSTRRUN_CLUSTER0_1_QCH (CLK_DSU_BASE + 12) #define GATE_PPMU_CPUCL0_QCH (CLK_DSU_BASE + 13) #define GATE_PPMU_CPUCL1_QCH (CLK_DSU_BASE + 14) #define GATE_SLH_AXI_SI_P_CLUSTER0_QCH (CLK_DSU_BASE + 15) #define DOUT_DIV_CLK_DSU_CLUSTER (CLK_DSU_BASE + 16) #define DOUT_DIV_CLK_DSU_SHORTSTOP (CLK_DSU_BASE + 17) #define DOUT_DIV_CLK_CLUSTER0_ACLK (CLK_DSU_BASE + 18) #define DOUT_DIV_CLK_CLUSTER0_ATCLK (CLK_DSU_BASE + 19) #define DOUT_DIV_CLK_CLUSTER0_PCLK (CLK_DSU_BASE + 20) #define DOUT_DIV_CLK_CLUSTER0_PERIPHCLK (CLK_DSU_BASE + 21) //***************************G3D************************ #define CLK_G3D_BASE (700) #define GATE_D_TZPC_G3D_QCH (CLK_G3D_BASE + 1) #define GATE_G3D_CMU_G3D_QCH (CLK_G3D_BASE + 2) #define GATE_GPU_QCH (CLK_G3D_BASE + 3) #define GATE_HTU_G3D_QCH_CLK (CLK_G3D_BASE + 4) #define GATE_HTU_G3D_QCH_PCLK (CLK_G3D_BASE + 5) #define GATE_LHM_AXI_P_INT_G3D_QCH (CLK_G3D_BASE + 6) #define GATE_LHS_AXI_P_INT_G3D_QCH (CLK_G3D_BASE + 7) #define GATE_LH_AXI_SI_D_G3D_QCH (CLK_G3D_BASE + 8) #define GATE_PPMU_D_G3D_QCH (CLK_G3D_BASE + 9) #define GATE_SLH_AXI_MI_P_G3D_QCH (CLK_G3D_BASE + 10) #define GATE_SYSMMU_D_G3D_QCH (CLK_G3D_BASE + 11) #define GATE_SYSREG_G3D_QCH (CLK_G3D_BASE + 12) #define GATE_VGEN_LITE_G3D_QCH (CLK_G3D_BASE + 13) #define GATE_GNSS_CMU_GNSS_QCH (CLK_G3D_BASE + 14) #define DOUT_DIV_CLK_G3D_BUSD (CLK_G3D_BASE + 15) #define DOUT_DIV_CLK_G3D_BUSP (CLK_G3D_BASE + 16) //*****************************HSI*********************** #define CLK_HSI_BASE (800) #define GATE_D_TZPC_HSI_QCH (CLK_HSI_BASE + 2) #define GATE_GPIO_HSI_QCH (CLK_HSI_BASE + 3) #define GATE_GPIO_HSI_UFS_QCH (CLK_HSI_BASE + 4) #define GATE_HSI_CMU_HSI_QCH (CLK_HSI_BASE + 5) #define GATE_PPMU_HSI_QCH (CLK_HSI_BASE + 6) #define GATE_S2MPU_D_HSI_QCH_S2 (CLK_HSI_BASE + 7) #define GATE_SLH_AXI_MI_P_HSI_QCH (CLK_HSI_BASE + 8) #define GATE_SLH_AXI_SI_D_HSI_QCH (CLK_HSI_BASE + 9) #define GATE_SYSREG_HSI_QCH (CLK_HSI_BASE + 10) #define GATE_UFS_EMBD_QCH (CLK_HSI_BASE + 11) #define GATE_UFS_EMBD_QCH_FMP (CLK_HSI_BASE + 12) #define GATE_VGEN_LITE_HSI_QCH (CLK_HSI_BASE + 13) #define DOUT_CLKCMU_HSI_BUS (CLK_HSI_BASE + 14) #define DOUT_CLKCMU_HSI_UFS_EMBD (CLK_HSI_BASE + 15) //******************************ISP*********************** #define CLK_ISP_BASE (850) #define GATE_D_TZPC_ISP_QCH (CLK_ISP_BASE + 1) #define GATE_ISP_CMU_ISP_QCH (CLK_ISP_BASE + 2) #define GATE_ITP_DNS_QCH_S00 (CLK_ISP_BASE + 3) #define GATE_ITP_DNS_QCH_S01 (CLK_ISP_BASE + 4) #define GATE_LH_AST_MI_OTF0_TNRISP_QCH (CLK_ISP_BASE + 5) #define GATE_LH_AST_MI_OTF1_TNRISP_QCH (CLK_ISP_BASE + 6) #define GATE_LH_AST_MI_OTF_TAAISP_QCH (CLK_ISP_BASE + 7) #define GATE_LH_AST_SI_OTF_ISPMCSC_QCH (CLK_ISP_BASE + 8) #define GATE_LH_AXI_SI_D_ISP_QCH (CLK_ISP_BASE + 9) #define GATE_PPMU_ISP_QCH (CLK_ISP_BASE + 10) #define GATE_SLH_AXI_MI_P_ISP_QCH (CLK_ISP_BASE + 11) #define GATE_SYSMMU_D_ISP_QCH_S1 (CLK_ISP_BASE + 12) #define GATE_SYSMMU_D_ISP_QCH_S2 (CLK_ISP_BASE + 13) #define GATE_SYSREG_ISP_QCH (CLK_ISP_BASE + 14) #define GATE_VGEN_LITE_ISP_QCH (CLK_ISP_BASE + 15) #define DOUT_DIV_CLK_ISP_BUSP (CLK_ISP_BASE + 16) #define DOUT_CLKCMU_ISP_BUS (CLK_ISP_BASE + 17) //*******************************M2M********************** #define CLK_M2M_BASE (900) #define GATE_D_TZPC_M2M_QCH (CLK_M2M_BASE + 1) #define GATE_JPEG0_QCH (CLK_M2M_BASE + 2) #define GATE_LH_AXI_SI_D_M2M_QCH (CLK_M2M_BASE + 3) #define GATE_M2M_QCH_S2 (CLK_M2M_BASE + 4) #define GATE_M2M_QCH_S1 (CLK_M2M_BASE + 5) #define GATE_M2M_CMU_M2M_QCH (CLK_M2M_BASE + 6) #define GATE_PPMU_D_M2M_QCH (CLK_M2M_BASE + 7) #define GATE_SLH_AXI_MI_P_M2M_QCH (CLK_M2M_BASE + 8) #define GATE_SYSMMU_D_M2M_QCH_S1 (CLK_M2M_BASE + 9) #define GATE_SYSMMU_D_M2M_QCH_S2 (CLK_M2M_BASE + 10) #define GATE_SYSREG_M2M_QCH (CLK_M2M_BASE + 11) #define GATE_VGEN_LITE_M2M_QCH (CLK_M2M_BASE + 12) #define DOUT_CLKCMU_M2M_MSCL (CLK_M2M_BASE + 13) #define DOUT_DIV_CLK_M2M_BUSP (CLK_M2M_BASE + 14) //**********************************MCSC******************* #define CLK_MCSC_BASE (950) #define GATE_D_TZPC_MCSC_QCH (CLK_MCSC_BASE + 1) #define GATE_GDC_QCH (CLK_MCSC_BASE + 2) #define GATE_LH_AST_MI_OTF_ISPMCSC_QCH (CLK_MCSC_BASE + 3) #define GATE_LH_AXI_MI_D0_CSIS_QCH (CLK_MCSC_BASE + 4) #define GATE_LH_AXI_MI_D0_TNR_QCH (CLK_MCSC_BASE + 5) #define GATE_LH_AXI_MI_D1_CSIS_QCH (CLK_MCSC_BASE + 6) #define GATE_LH_AXI_MI_D1_TNR_QCH (CLK_MCSC_BASE + 7) #define GATE_LH_AXI_MI_D2_CSIS_QCH (CLK_MCSC_BASE + 8) #define GATE_LH_AXI_MI_D3_CSIS_QCH (CLK_MCSC_BASE + 9) #define GATE_LH_AXI_MI_D_ISP_QCH (CLK_MCSC_BASE + 10) #define GATE_LH_AXI_MI_D_TAA_QCH (CLK_MCSC_BASE + 11) #define GATE_MCSC_QCH (CLK_MCSC_BASE + 12) #define GATE_MCSC_CMU_MCSC_QCH (CLK_MCSC_BASE + 13) #define GATE_ORBMCH_QCH_ACLK (CLK_MCSC_BASE + 14) #define GATE_ORBMCH_QCH_C2CLK (CLK_MCSC_BASE + 15) #define GATE_PPMU_GDC_QCH (CLK_MCSC_BASE + 16) #define GATE_PPMU_MCSC_QCH (CLK_MCSC_BASE + 17) #define GATE_SLH_AXI_MI_P_MCSC_QCH (CLK_MCSC_BASE + 18) #define GATE_SYSMMU_D0_MCSC_QCH_S1 (CLK_MCSC_BASE + 19) #define GATE_SYSMMU_D0_MCSC_QCH_S2 (CLK_MCSC_BASE + 20) #define GATE_SYSMMU_D1_MCSC_QCH_S1 (CLK_MCSC_BASE + 21) #define GATE_SYSMMU_D1_MCSC_QCH_S2 (CLK_MCSC_BASE + 22) #define GATE_SYSREG_MCSC_QCH (CLK_MCSC_BASE + 23) #define GATE_TREX_D_CAM_QCH (CLK_MCSC_BASE + 24) #define GATE_VGEN_LITE_GDC_QCH (CLK_MCSC_BASE + 25) #define GATE_VGEN_LITE_MCSC_QCH (CLK_MCSC_BASE + 26) #define DOUT_DIV_CLK_MCSC_BUSP (CLK_MCSC_BASE + 27) #define DOUT_CLKCMU_MCSC_BUS (CLK_MCSC_BASE + 28) #define DOUT_CLKCMU_MCSC_GDC (CLK_MCSC_BASE + 29) #define DOUT_CLKCMU_MCSC_MCSC (CLK_MCSC_BASE + 30) //*********************************MFC********************* #define CLK_MFC_BASE (1000) #define GATE_D_TZPC_MFC_QCH (CLK_MFC_BASE + 1) #define GATE_LH_AXI_SI_D_MFC_QCH (CLK_MFC_BASE + 2) #define GATE_MFC_QCH (CLK_MFC_BASE + 3) #define GATE_MFC_CMU_MFC_QCH (CLK_MFC_BASE + 4) #define GATE_PPMU_MFC_QCH (CLK_MFC_BASE + 5) #define GATE_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH (CLK_MFC_BASE + 6) #define GATE_SLH_AXI_MI_P_MFC_QCH (CLK_MFC_BASE + 7) #define GATE_SYSMMU_MFC_QCH_S1 (CLK_MFC_BASE + 8) #define GATE_SYSMMU_MFC_QCH_S2 (CLK_MFC_BASE + 9) #define GATE_SYSREG_MFC_QCH (CLK_MFC_BASE + 10) #define GATE_VGEN_LITE_MFC_QCH (CLK_MFC_BASE + 11) #define DOUT_DIV_CLK_MFC_BUSP (CLK_MFC_BASE + 12) #define DOUT_CLKCMU_MFC_MFC (CLK_MFC_BASE + 13) //************************************MIF*********************** #define CLK_MIF_BASE (1050) #define GATE_CMU_MIF_CMUREF_QCH (CLK_MIF_BASE + 1) #define GATE_DMC_QCH (CLK_MIF_BASE + 2) #define GATE_D_TZPC_MIF_QCH (CLK_MIF_BASE + 3) #define GATE_LH_AXI_MI_D_MIF_CP_QCH (CLK_MIF_BASE + 4) #define GATE_LH_AXI_MI_D_MIF_CPU_QCH (CLK_MIF_BASE + 5) #define GATE_LH_AXI_MI_D_MIF_NRT_QCH (CLK_MIF_BASE + 6) #define GATE_LH_AXI_MI_D_MIF_RT_QCH (CLK_MIF_BASE + 7) #define GATE_MIF_CMU_MIF_QCH (CLK_MIF_BASE + 8) #define GATE_PPMU_DMC_CPU_QCH (CLK_MIF_BASE + 9) #define GATE_QE_DMC_CPU_QCH (CLK_MIF_BASE + 10) #define GATE_SFRAPB_BRIDGE_DDRPHY_QCH (CLK_MIF_BASE + 11) #define GATE_SFRAPB_BRIDGE_DMC_QCH (CLK_MIF_BASE + 12) #define GATE_SFRAPB_BRIDGE_DMC_PF_QCH (CLK_MIF_BASE + 13) #define GATE_SFRAPB_BRIDGE_DMC_PPMPU_QCH (CLK_MIF_BASE + 14) #define GATE_SFRAPB_BRIDGE_DMC_SECURE_QCH (CLK_MIF_BASE + 15) #define GATE_SLH_AXI_MI_P_MIF_QCH (CLK_MIF_BASE + 16) #define GATE_SYSREG_MIF_QCH (CLK_MIF_BASE + 17) #define GATE_MODEM_CMU_MODEM_QCH (CLK_MIF_BASE + 18) #define MUX_MIF_DDRPHY2X (CLK_MIF_BASE + 19) //*****************************NPU0************************** #define CLK_NPU0_BASE (1100) #define GATE_D_TZPC_NPU0_QCH (CLK_NPU0_BASE + 1) #define GATE_IP_NPUCORE_QCH_ACLK (CLK_NPU0_BASE + 2) #define GATE_IP_NPUCORE_QCH_PCLK (CLK_NPU0_BASE + 3) #define GATE_LH_AXI_MI_D0_NPU0_QCH (CLK_NPU0_BASE + 4) #define GATE_LH_AXI_MI_D1_NPU0_QCH (CLK_NPU0_BASE + 5) #define GATE_LH_AXI_MI_D_CTRL_NPU0_QCH (CLK_NPU0_BASE + 6) #define GATE_LH_AXI_SI_D_CMDQ_NPU0_QCH (CLK_NPU0_BASE + 7) #define GATE_LH_AXI_SI_D_RQ_NPU0_QCH (CLK_NPU0_BASE + 8) #define GATE_NPU0_CMU_NPU0_QCH (CLK_NPU0_BASE + 9) #define GATE_SLH_AXI_MI_P_NPU0_QCH (CLK_NPU0_BASE + 10) #define GATE_SYSREG_NPU0_QCH (CLK_NPU0_BASE + 11) #define DOUT_DIV_CLK_NPU0_BUS (CLK_NPU0_BASE + 12) #define DOUT_DIV_CLK_NPU0_BUSP (CLK_NPU0_BASE + 13) #define DOUT_CLKCMU_NPU0_BUS (CLK_NPU0_BASE + 14) //******************************NPUS************************** #define CLK_NPUS_BASE (1150) #define GATE_ADM_DAP_NPUS_QCH (CLK_NPUS_BASE + 1) #define GATE_D_TZPC_NPUS_QCH (CLK_NPUS_BASE + 2) #define GATE_HTU_NPUS_QCH_PCLK (CLK_NPUS_BASE + 3) #define GATE_HTU_NPUS_QCH_CLK (CLK_NPUS_BASE + 4) #define GATE_IP_NPUS_QCH (CLK_NPUS_BASE + 5) #define GATE_IP_NPUS_QCH_C2A0CLK (CLK_NPUS_BASE + 6) #define GATE_IP_NPUS_QCH_C2A1CLK (CLK_NPUS_BASE + 7) #define GATE_IP_NPUS_QCH_CPU (CLK_NPUS_BASE + 8) #define GATE_IP_NPUS_QCH_NEON (CLK_NPUS_BASE + 9) #define GATE_LH_AXI_MI_D_CMDQ_NPU0_QCH (CLK_NPUS_BASE + 10) #define GATE_LH_AXI_MI_D_RQ_NPU0_QCH (CLK_NPUS_BASE + 11) #define GATE_LH_AXI_SI_D0_NPU0_QCH (CLK_NPUS_BASE + 12) #define GATE_LH_AXI_SI_D0_NPUS_QCH (CLK_NPUS_BASE + 13) #define GATE_LH_AXI_SI_D1_NPU0_QCH (CLK_NPUS_BASE + 14) #define GATE_LH_AXI_SI_D1_NPUS_QCH (CLK_NPUS_BASE + 15) #define GATE_LH_AXI_SI_D_CTRL_NPU0_QCH (CLK_NPUS_BASE + 16) #define GATE_NPUS_CMU_NPUS_QCH (CLK_NPUS_BASE + 17) #define GATE_PPMU_NPUS_0_QCH (CLK_NPUS_BASE + 18) #define GATE_PPMU_NPUS_1_QCH (CLK_NPUS_BASE + 19) #define GATE_SLH_AXI_MI_P_INT_NPUS_QCH (CLK_NPUS_BASE + 20) #define GATE_SLH_AXI_MI_P_NPUS_QCH (CLK_NPUS_BASE + 21) #define GATE_SLH_AXI_SI_P_INT_NPUS_QCH (CLK_NPUS_BASE + 22) #define GATE_SYSMMU_D0_NPUS_QCH_S1 (CLK_NPUS_BASE + 23) #define GATE_SYSMMU_D0_NPUS_QCH_S2 (CLK_NPUS_BASE + 24) #define GATE_SYSMMU_D1_NPUS_QCH_S1 (CLK_NPUS_BASE + 25) #define GATE_SYSMMU_D1_NPUS_QCH_S2 (CLK_NPUS_BASE + 26) #define GATE_SYSREG_NPUS_QCH (CLK_NPUS_BASE + 27) #define GATE_VGEN_LITE_NPUS_QCH (CLK_NPUS_BASE + 28) #define DOUT_DIV_CLK_NPUS_BUS (CLK_NPUS_BASE + 29) #define DOUT_DIV_CLK_NPUS_BUSP (CLK_NPUS_BASE + 30) #define DOUT_CLKCMU_NPUS_BUS (CLK_NPUS_BASE + 31) //******************************PERI**************************** #define CLK_PERI_BASE (1200) #define GATE_D_TZPC_PERI_QCH (CLK_PERI_BASE + 1) #define GATE_GPIO_PERI_QCH (CLK_PERI_BASE + 2) #define GATE_GPIO_PERIMMC_QCH_GPIO (CLK_PERI_BASE + 3) #define GATE_MCT_QCH (CLK_PERI_BASE + 4) #define GATE_MMC_CARD_QCH (CLK_PERI_BASE + 5) #define GATE_OTP_CON_TOP_QCH (CLK_PERI_BASE + 6) #define GATE_PERI_CMU_PERI_QCH (CLK_PERI_BASE + 7) #define GATE_PPMU_PERI_QCH (CLK_PERI_BASE + 8) #define GATE_PWM_QCH (CLK_PERI_BASE + 9) #define GATE_S2MPU_D_PERI_QCH (CLK_PERI_BASE + 10) #define GATE_SLH_AXI_MI_P_PERI_QCH (CLK_PERI_BASE + 11) #define GATE_SLH_AXI_SI_D_PERI_QCH (CLK_PERI_BASE + 12) #define GATE_SYSREG_PERI_QCH (CLK_PERI_BASE + 13) #define GATE_TMU_QCH (CLK_PERI_BASE + 14) #define GATE_UART_DBG_QCH (CLK_PERI_BASE + 15) #define GATE_USI00_I2C_QCH (CLK_PERI_BASE + 16) #define GATE_USI00_USI_QCH (CLK_PERI_BASE + 17) #define GATE_USI01_I2C_QCH (CLK_PERI_BASE + 18) #define GATE_USI01_USI_QCH (CLK_PERI_BASE + 19) #define GATE_USI02_I2C_QCH (CLK_PERI_BASE + 20) #define GATE_USI02_USI_QCH (CLK_PERI_BASE + 21) #define GATE_USI03_I2C_QCH (CLK_PERI_BASE + 22) #define GATE_USI03_USI_QCH (CLK_PERI_BASE + 23) #define GATE_USI04_I2C_QCH (CLK_PERI_BASE + 24) #define GATE_USI04_USI_QCH (CLK_PERI_BASE + 25) #define GATE_USI05_I2C_QCH (CLK_PERI_BASE + 26) #define GATE_USI05_USI_QCH (CLK_PERI_BASE + 27) #define GATE_USI06_I2C_QCH (CLK_PERI_BASE + 28) #define GATE_USI06_USI_QCH (CLK_PERI_BASE + 29) #define GATE_USI07_I2C_QCH (CLK_PERI_BASE + 30) #define GATE_VGEN_LITE_PERI_QCH (CLK_PERI_BASE + 31) #define GATE_WDT0_QCH (CLK_PERI_BASE + 32) #define GATE_WDT1_QCH (CLK_PERI_BASE + 33) #define DOUT_DIV_CLK_PERI_UART_DBG (CLK_PERI_BASE + 34) #define DOUT_DIV_CLK_PERI_USI_I2c (CLK_PERI_BASE + 35) #define DOUT_DIV_CLK_PERI_USI00_USI (CLK_PERI_BASE + 36) #define DOUT_DIV_CLK_PERI_USI01_USI (CLK_PERI_BASE + 37) #define DOUT_DIV_CLK_PERI_USI02_USI (CLK_PERI_BASE + 38) #define DOUT_DIV_CLK_PERI_USI03_USI (CLK_PERI_BASE + 39) #define DOUT_DIV_CLK_PERI_USI04_USI (CLK_PERI_BASE + 40) #define DOUT_DIV_CLK_PERI_USI05_USI (CLK_PERI_BASE + 41) #define DOUT_DIV_CLK_PERI_USI06_USI (CLK_PERI_BASE + 42) #define DOUT_CLKCMU_PERI_BUS (CLK_PERI_BASE + 43) #define DOUT_CLKCMU_PERI_MMC_CARD (CLK_PERI_BASE + 44) // ***********************************S2D********************* #define CLK_S2D_BASE (1250) #define GATE_S2D_CMU_S2D_QCH (CLK_S2D_BASE + 1) #define GATE_SLH_AXI_MI_G_SCAN2DRAM_QCH (CLK_S2D_BASE + 2) // ***********************************TAA********************* #define CLK_TAA_BASE (1300) #define GATE_D_TZPC_TAA_QCH (CLK_TAA_BASE + 1) #define GATE_LH_AST_MI_OTF0_CSISTAA_QCH (CLK_TAA_BASE + 2) #define GATE_LH_AST_MI_OTF1_CSISTAA_QCH (CLK_TAA_BASE + 3) #define GATE_LH_AST_MI_OTF2_CSISTAA_QCH (CLK_TAA_BASE + 4) #define GATE_LH_AST_SI_OTF_TAAISP_QCH (CLK_TAA_BASE + 5) #define GATE_LH_AST_SI_SOTF0_TAACSIS_QCH (CLK_TAA_BASE + 6) #define GATE_LH_AST_SI_SOTF1_TAACSIS_QCH (CLK_TAA_BASE + 7) #define GATE_LH_AST_SI_SOTF2_TAACSIS_QCH (CLK_TAA_BASE + 8) #define GATE_LH_AST_SI_ZOTF0_TAACSIS_QCH (CLK_TAA_BASE + 9) #define GATE_LH_AST_SI_ZOTF1_TAACSIS_QCH (CLK_TAA_BASE + 10) #define GATE_LH_AST_SI_ZOTF2_TAACSIS_QCH (CLK_TAA_BASE + 11) #define GATE_LH_AXI_SI_D_TAA_QCH (CLK_TAA_BASE + 12) #define GATE_PPMU_TAA_QCH (CLK_TAA_BASE + 13) #define GATE_SIPU_TAA_QCH (CLK_TAA_BASE + 14) #define GATE_SIPU_TAA_QCH_C2_STAT (CLK_TAA_BASE + 15) #define GATE_SIPU_TAA_QCH_C2_YDS (CLK_TAA_BASE + 16) #define GATE_SLH_AXI_MI_P_TAA_QCH (CLK_TAA_BASE + 17) #define GATE_SYSMMU_TAA_QCH_S1 (CLK_TAA_BASE + 18) #define GATE_SYSMMU_TAA_QCH_S2 (CLK_TAA_BASE + 19) #define GATE_SYSREG_TAA_QCH (CLK_TAA_BASE + 20) #define GATE_TAA_CMU_TAA_QCH (CLK_TAA_BASE + 21) #define GATE_VGEN_LITE0_TAA_QCH (CLK_TAA_BASE + 22) #define GATE_VGEN_LITE1_TAA_QCH (CLK_TAA_BASE + 23) #define DOUT_DIV_CLK_TAA_BUSP (CLK_TAA_BASE + 24) #define DOUT_CLKCMU_TAA_BUS (CLK_TAA_BASE + 25) // ****************************TNR************************ #define CLK_TNR_BASE (1350) #define GATE_D_TZPC_TNR_QCH (CLK_TNR_BASE + 1) #define GATE_LH_AST_SI_OTF0_TNRISP_QCH (CLK_TNR_BASE + 2) #define GATE_LH_AST_SI_OTF1_TNRISP_QCH (CLK_TNR_BASE + 3) #define GATE_LH_AXI_SI_D0_TNR_QCH (CLK_TNR_BASE + 4) #define GATE_LH_AXI_SI_D1_TNR_QCH (CLK_TNR_BASE + 5) #define GATE_PPMU_D0_TNR_QCH (CLK_TNR_BASE + 6) #define GATE_PPMU_D1_TNR_QCH (CLK_TNR_BASE + 7) #define GATE_SLH_AXI_MI_P_TNR_QCH (CLK_TNR_BASE + 8) #define GATE_SYSMMU_D0_TNR_QCH_S1 (CLK_TNR_BASE + 9) #define GATE_SYSMMU_D0_TNR_QCH_S2 (CLK_TNR_BASE + 10) #define GATE_SYSMMU_D1_TNR_QCH_S1 (CLK_TNR_BASE + 11) #define GATE_SYSMMU_D1_TNR_QCH_S2 (CLK_TNR_BASE + 12) #define GATE_SYSREG_TNR_QCH (CLK_TNR_BASE + 13) #define GATE_TNR_QCH_MCFP0 (CLK_TNR_BASE + 14) #define GATE_TNR_QCH_MCFP1 (CLK_TNR_BASE + 15) #define GATE_TNR_CMU_TNR_QCH (CLK_TNR_BASE + 16) #define GATE_VGEN_LITE_D_TNR_QCH (CLK_TNR_BASE + 17) #define DOUT_DIV_CLK_TNR_BUSP (CLK_TNR_BASE + 18) #define DOUT_CLKCMU_TNR_BUS (CLK_TNR_BASE + 19) // *************************USB***************************** #define CLK_USB_BASE (1400) #define GATE_D_TZPC_USB_QCH (CLK_USB_BASE + 1) #define GATE_PPMU_USB_QCH (CLK_USB_BASE + 2) #define GATE_S2MPU_D_USB_QCH (CLK_USB_BASE + 3) #define GATE_SLH_AXI_MI_P_USB_QCH (CLK_USB_BASE + 4) #define GATE_SLH_AXI_SI_D_USB_QCH (CLK_USB_BASE + 5) #define GATE_SLH_AXI_SI_D_USBAUD_QCH (CLK_USB_BASE + 6) #define GATE_SYSREG_USB_QCH (CLK_USB_BASE + 7) #define GATE_USB20DRD_TOP_QCH_SLV_CTRL (CLK_USB_BASE + 8) #define GATE_USB20DRD_TOP_QCH_SLV_LINK (CLK_USB_BASE + 9) #define GATE_USB_CMU_USB_QCH (CLK_USB_BASE + 10) #define GATE_VGEN_LITE_USB_QCH (CLK_USB_BASE + 11) #define DOUT_CLKCMU_USB_BUS (CLK_USB_BASE + 12) #define DOUT_CLKCMU_USB_USB20DRD (CLK_USB_BASE + 13) //#define DOUT_CLKAUD_USB_BUS (CLK_USB_BASE + 14) #define DOUT_CLKAUD_USB_USB20DRD (CLK_USB_BASE + 14) //***********************************************VTS****************************** #define CLK_VTS_BASE (1450) #define GATE_CM4_VTS_QCH_CPU (CLK_VTS_BASE + 1) #define GATE_DMIC_AHB0_QCH_PCLK (CLK_VTS_BASE + 2) #define GATE_DMIC_AHB2_QCH_PCLK (CLK_VTS_BASE + 3) #define GATE_DMIC_AUD0_QCH_PCLK (CLK_VTS_BASE + 4) #define GATE_DMIC_AUD0_QCH_DMIC (CLK_VTS_BASE + 5) #define GATE_DMIC_AUD1_QCH_PCLK (CLK_VTS_BASE + 6) #define GATE_DMIC_AUD1_QCH_DMIC (CLK_VTS_BASE + 7) #define GATE_DMIC_IF0_QCH_PCLK (CLK_VTS_BASE + 8) #define GATE_DMIC_IF0_QCH_DMIC (CLK_VTS_BASE + 9) #define GATE_DMIC_IF1_QCH_PCLK (CLK_VTS_BASE + 10) #define GATE_DMIC_IF1_QCH_DMIC (CLK_VTS_BASE + 11) #define GATE_GPIO_VTS_QCH (CLK_VTS_BASE + 12) #define GATE_HWACG_SYS_DMIC0_QCH (CLK_VTS_BASE + 13) #define GATE_HWACG_SYS_DMIC2_QCH (CLK_VTS_BASE + 14) #define GATE_HWACG_SYS_SERIAL_LIF_QCH (CLK_VTS_BASE + 15) #define GATE_MAILBOX_ABOX_VTS_QCH (CLK_VTS_BASE + 16) #define GATE_MAILBOX_AP_VTS_QCH (CLK_VTS_BASE + 17) #define GATE_SERIAL_LIF_AUD_QCH_PCLK (CLK_VTS_BASE + 18) #define GATE_SERIAL_LIF_AUD_QCH_AHB (CLK_VTS_BASE + 19) #define GATE_SERIAL_LIF_AUD_QCH_LIF (CLK_VTS_BASE + 20) #define GATE_SLH_AXI_MI_S_VTS_QCH (CLK_VTS_BASE + 21) #define GATE_SLH_AXI_SI_M_VTS_QCH (CLK_VTS_BASE + 22) #define GATE_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0 (CLK_VTS_BASE + 23) #define GATE_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1 (CLK_VTS_BASE + 24) #define GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD0 (CLK_VTS_BASE + 25) #define GATE_SS_VTS_GLUE_QCH_DMIC_IF_PAD1 (CLK_VTS_BASE + 26) #define GATE_SYSREG_VTS_QCH (CLK_VTS_BASE + 27) #define GATE_TIMER_VTS_QCH (CLK_VTS_BASE + 28) #define GATE_VTS_CMU_VTS_QCH (CLK_VTS_BASE + 29) #define GATE_WDT_VTS_QCH (CLK_VTS_BASE + 30) #define DOUT_DIV_CLK_VTS_BUS (CLK_VTS_BASE + 31) #define DOUT_DIV_CLK_VTS_DMIC_IF (CLK_VTS_BASE + 32) #define DOUT_DIV_CLK_VTS_DMIC (CLK_VTS_BASE + 33) #define DOUT_DIV_CLK_VTS_DMIC_DIV2 (CLK_VTS_BASE + 34) #define DOUT_DIV_VTS_DMIC_AUD (CLK_VTS_BASE + 35) #define DOUT_DIV_VTS_DMIC_AUD_DIV2 (CLK_VTS_BASE + 36) #define DOUT_DIV_VTS_SERIAL_LIF_CORE (CLK_VTS_BASE + 37) #define DOUT_DIV_VTS_SERIAL_LIF (CLK_VTS_BASE + 38) #define UMUX_CLKCMU_VTS_RCO_USER (CLK_VTS_BASE + 39) #define MOUT_MUX_VTS_DMIC_AUD (CLK_VTS_BASE + 40) #define MOUT_MUX_VTS_SERIAL_LIF (CLK_VTS_BASE + 41) //VPD #define CLK_VPD_BASE (1500) #define DOUT_DIV_CLK_VPD_BUS (CLK_VPD_BASE + 1) #define DOUT_DIV_CLK_VPD_BUSP (CLK_VPD_BASE + 2) /* CLKOUT */ #define CLK_CLKOUT_BASE (1600) #define OSC_NFC (CLK_CLKOUT_BASE + 0) #define OSC_AUD (CLK_CLKOUT_BASE + 1) #define CLK_NR_CLKS (2600 + 1) //DVFS cal-id #define ACPM_DVFS_MIF (0x0B040000) #define ACPM_DVFS_INT (0x0B040001) #define ACPM_DVFS_CPUCL0 (0x0B040002) #define ACPM_DVFS_CPUCL1 (0x0B040003) #define ACPM_DVFS_DSU (0x0B040004) #define ACPM_DVFS_NPU (0x0B040005) #define ACPM_DVFS_DISP (0x0B040006) #define ACPM_DVFS_AUD (0x0B040007) #define ACPM_DVFS_G3D (0x0B040008) #define ACPM_DVFS_CP_CPU (0x0B040009) #define ACPM_DVFS_CP (0x0B04000A) #define ACPM_DVFS_CAM (0x0B04000B) #define ACPM_DVFS_ISP (0x0B04000C) #define ACPM_DVFS_MFC (0x0B04000D) #define ACPM_DVFS_INTSCI (0x0B04000E) #define ACPM_DVFS_INTG3D (0x0B04000F) #define ACPM_DVFS_GNSS (0x0B040010) #define ACPM_DVFS_WLBT (0x0B040011) #define ACPM_DVFS_ALIVE (0x0B040012) #define ACPM_DVFS_CHUB (0x0B040013) #endif /* _DT_BINDINGS_CLOCK_S5E8825_H */