/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Samsung Exynos SoC series dsp driver
 *
 * Copyright (c) 2019 Samsung Electronics Co., Ltd.
 *              http://www.samsung.com/
 */

#ifndef __HW_P0_DSP_HW_P0_MEMORY_H__
#define __HW_P0_DSP_HW_P0_MEMORY_H__

#include "dsp-memory.h"

#define DSP_P0_MEMORY_MAX_SIZE	(SZ_16M)

#define DSP_P0_FW_EXTENSION	"bin"

#define DSP_P0_MASTER_FW_NAME	"dsp_master"	// master boot + stack
#define DSP_P0_MASTER_FW_IOVA	(0x30000000)
#define DSP_P0_MASTER_FW_SIZE	(SZ_1M)

#define DSP_P0_FW_NAME		"dsp"
#define DSP_P0_FW_IOVA		(0x30100000)
#define DSP_P0_FW_SIZE		(SZ_1M * 8)

#define DSP_P0_DHCP_MEM_IOVA	(0x31000000)
#define DSP_P0_DHCP_MEM_SIZE	(SZ_4K)

#define DSP_P0_FW_LOG_IOVA	(DSP_P0_DHCP_MEM_IOVA + DSP_P0_MEMORY_MAX_SIZE)
#define DSP_P0_FW_LOG_SIZE	(SZ_1M)

#define DSP_P0_IVP_PM_NAME	"dsp_ivp_pm"
#define DSP_P0_IVP_PM_IOVA	(DSP_P0_FW_LOG_IOVA + DSP_P0_MEMORY_MAX_SIZE)
#define DSP_P0_IVP_PM_SIZE	(SZ_16M)

#define DSP_P0_IVP_DM_NAME	"dsp_ivp_dm"
#define DSP_P0_IVP_DM_IOVA	(DSP_P0_IVP_PM_IOVA + DSP_P0_MEMORY_MAX_SIZE)
#define DSP_P0_IVP_DM_SIZE	(SZ_128K)

#define DSP_P0_MBOX_MEMORY_IOVA	(DSP_P0_IVP_DM_IOVA + DSP_P0_MEMORY_MAX_SIZE)
#define DSP_P0_MBOX_MEMORY_SIZE	(SZ_8K)

#define DSP_P0_MBOX_POOL_IOVA	(DSP_P0_MBOX_MEMORY_IOVA + \
		DSP_P0_MEMORY_MAX_SIZE)
#define DSP_P0_MBOX_POOL_SIZE	(SZ_128K)

#define DSP_P0_DL_OUT_IOVA	(DSP_P0_MBOX_POOL_IOVA + DSP_P0_MEMORY_MAX_SIZE)
#define DSP_P0_DL_OUT_SIZE	(SZ_1M)

#define DSP_P0_HW_BASE_ADDR		(0x20000000)
#define DSP_P0_SM_BASE_ADDR		(0x120100)
#define DSP_P0_SM(n)			(DSP_P0_SM_BASE_ADDR + (n) * 4)

#define DSP_P0_DHCP_IDX(n)		(0x4 * (n))

#define DSP_P0_SM_USERDEFINED_COUNT	(64)
#define DSP_P0_SM_USERDEFINED_SIZE	(SZ_4 * DSP_P0_SM_USERDEFINED_COUNT)
#define DSP_P0_SM_USERDEFINED_BASE	(DSP_P0_SM(0))
#define DSP_P0_SM_USERDEFINED(n)	(DSP_P0_SM_USERDEFINED_BASE + 0x4 * (n))

#define DSP_P0_SM_FW_INFO_COUNT		(192)
#define DSP_P0_SM_FW_INFO_SIZE		(SZ_4 * DSP_P0_SM_FW_INFO_COUNT)
#define DSP_P0_SM_FW_INFO_BASE		(DSP_P0_SM(DSP_P0_SM_USERDEFINED_COUNT))
#define DSP_P0_SM_FW_INFO(n)		(DSP_P0_SM_FW_INFO_BASE + 0x4 * (n))

enum dsp_p0_dhcp_used_count {
	DSP_P0_DHCP_TO_CC_MBOX		= 0,
	DSP_P0_DHCP_TO_HOST_MBOX	= 8,
	DSP_P0_DHCP_LOG_QUEUE		= 16,
	DSP_P0_DHCP_TO_CC_INT_STATUS	= 24,
	DSP_P0_DHCP_TO_HOST_INT_STATUS,
	DSP_P0_DHCP_FW_RESERVED_SIZE,
	DSP_P0_DHCP_IVP_PM_IOVA,
	DSP_P0_DHCP_RESERVED0,
	DSP_P0_DHCP_RESERVED1,
	DSP_P0_DHCP_RESERVED2,
	DSP_P0_DHCP_IVP_PM_SIZE,
	DSP_P0_DHCP_IVP_DM_IOVA,
	DSP_P0_DHCP_IVP_DM_SIZE,
	DSP_P0_DHCP_RESERVED3,
	DSP_P0_DHCP_RESERVED4,
	DSP_P0_DHCP_RESERVED5,
	DSP_P0_DHCP_RESERVED6,
	DSP_P0_DHCP_MAILBOX_VERSION,
	DSP_P0_DHCP_MESSAGE_VERSION,
	DSP_P0_DHCP_FW_LOG_MEMORY_IOVA,
	DSP_P0_DHCP_FW_LOG_MEMORY_SIZE,
	DSP_P0_DHCP_TO_CC_MBOX_MEMORY_IOVA,
	DSP_P0_DHCP_TO_CC_MBOX_MEMORY_SIZE,
	DSP_P0_DHCP_TO_CC_MBOX_POOL_IOVA,
	DSP_P0_DHCP_TO_CC_MBOX_POOL_SIZE,
	DSP_P0_DHCP_NPU_FW_IOVA,
	DSP_P0_DHCP_KERNEL_MODE,
	DSP_P0_DHCP_DL_OUT_IOVA,
	DSP_P0_DHCP_DL_OUT_SIZE,
	DSP_P0_DHCP_DEBUG_LAYER_START,
	DSP_P0_DHCP_DEBUG_LAYER_END,
	DSP_P0_DHCP_CHIPID_REV,
	DSP_P0_DHCP_PRODUCT_ID,
	DSP_P0_DHCP_DNC_FREQUENCY,
	DSP_P0_DHCP_DSP_FREQUENCY,
	DSP_P0_DHCP_RESERVED7,
	DSP_P0_DHCP_RESERVED8,
	DSP_P0_DHCP_INTERRUPT_MODE,
	DSP_P0_DHCP_DRIVER_VERSION,
	DSP_P0_DHCP_FIRMWARE_VERSION,
	DSP_P0_DHCP_USED_COUNT,
};

enum dsp_p0_priv_mem_id {
	DSP_P0_PRIV_MEM_FW,
	DSP_P0_PRIV_MEM_DHCP,
	DSP_P0_PRIV_MEM_FW_LOG,
	DSP_P0_PRIV_MEM_IVP_PM,
	DSP_P0_PRIV_MEM_IVP_DM,
	DSP_P0_PRIV_MEM_MBOX_MEMORY,
	DSP_P0_PRIV_MEM_MBOX_POOL,
	DSP_P0_PRIV_MEM_DL_OUT,
	DSP_P0_PRIV_MEM_COUNT,
};

enum dsp_p0_reserved_mem_id {
	DSP_P0_RESERVED_MEM_FW_MASTER,
	DSP_P0_RESERVED_MEM_COUNT,
};

int dsp_hw_p0_memory_register_ops(void);

#endif