#ifndef __CMUCAL_SFR_H__ #define __CMUCAL_SFR_H__ #include "../../cmucal.h" enum sfr_block_id { CMU_AUD = SFR_BLOCK_TYPE, CMU_TOP, CMU_CPUCL0, CMU_CPUCL1, CMU_DSU, CMU_MIF, CMU_S2D, CMU_ALIVE, CMU_BUSC, CMU_CHUB, CMU_CHUBVTS, CMU_CMGP, CMU_CORE, CMU_USB, CMU_VTS, CMU_CPUCL0_GLB, CMU_CSIS, CMU_DPU, CMU_G3D, CMU_HSI, CMU_ISP, CMU_M2M, CMU_MCSC, CMU_MFC, CMU_NPU0, CMU_NPUS, CMU_PERI, CMU_TAA, CMU_TNR, CMU_GNSS, CMU_MODEM, end_of_sfr_block, num_of_sfr_block = end_of_sfr_block - SFR_BLOCK_TYPE, }; enum sfr_id { PLL_LOCKTIME_PLL_AUD = SFR_TYPE, PLL_CON3_PLL_AUD, PLL_CON9_PLL_AUD, PLL_CON8_PLL_AUD, PLL_CON4_PLL_AUD, PLL_CON5_PLL_AUD, DBG_NFO_PLL_AUD, PLL_CON0_PLL_AUD, PLL_CON1_PLL_AUD, PLL_CON2_PLL_AUD, PLL_CON6_PLL_AUD, PLL_LOCKTIME_REG_PLL_AUD, PLL_CON7_PLL_AUD, PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, PLL_CON9_PLL_SHARED1, PLL_CON8_PLL_SHARED1, PLL_CON4_PLL_SHARED1, PLL_CON5_PLL_SHARED1, DBG_NFO_PLL_SHARED1, PLL_CON0_PLL_SHARED1, PLL_CON1_PLL_SHARED1, PLL_CON2_PLL_SHARED1, PLL_CON6_PLL_SHARED1, PLL_LOCKTIME_REG_PLL_SHARED1, PLL_CON7_PLL_SHARED1, PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, PLL_CON9_PLL_SHARED0, PLL_CON8_PLL_SHARED0, PLL_CON4_PLL_SHARED0, PLL_CON5_PLL_SHARED0, PLL_CON1_PLL_SHARED0, DBG_NFO_PLL_SHARED0, PLL_CON0_PLL_SHARED0, PLL_CON2_PLL_SHARED0, PLL_CON6_PLL_SHARED0, PLL_LOCKTIME_REG_PLL_SHARED0, PLL_CON7_PLL_SHARED0, PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, PLL_CON9_PLL_G3D, PLL_CON8_PLL_G3D, PLL_CON4_PLL_G3D, PLL_CON5_PLL_G3D, DBG_NFO_PLL_G3D, PLL_CON0_PLL_G3D, PLL_CON1_PLL_G3D, PLL_CON2_PLL_G3D, PLL_CON6_PLL_G3D, PLL_LOCKTIME_REG_PLL_G3D, PLL_CON7_PLL_G3D, PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, PLL_CON9_PLL_MMC, PLL_CON8_PLL_MMC, PLL_CON4_PLL_MMC, PLL_CON5_PLL_MMC, DBG_NFO_PLL_MMC, PLL_CON0_PLL_MMC, PLL_CON1_PLL_MMC, PLL_CON2_PLL_MMC, PLL_CON6_PLL_MMC, PLL_LOCKTIME_REG_PLL_MMC, PLL_CON7_PLL_MMC, PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, PLL_CON9_PLL_SHARED2, PLL_CON8_PLL_SHARED2, PLL_CON4_PLL_SHARED2, PLL_CON5_PLL_SHARED2, DBG_NFO_PLL_SHARED2, PLL_CON0_PLL_SHARED2, PLL_CON1_PLL_SHARED2, PLL_CON2_PLL_SHARED2, PLL_CON6_PLL_SHARED2, PLL_LOCKTIME_REG_PLL_SHARED2, PLL_CON7_PLL_SHARED2, PLL_LOCKTIME_PLL_CPUCL0, PLL_CON3_PLL_CPUCL0, PLL_CON9_PLL_CPUCL0, PLL_CON8_PLL_CPUCL0, PLL_CON4_PLL_CPUCL0, PLL_CON5_PLL_CPUCL0, DBG_NFO_PLL_CPUCL0, PLL_CON0_PLL_CPUCL0, PLL_CON1_PLL_CPUCL0, PLL_CON2_PLL_CPUCL0, PLL_CON6_PLL_CPUCL0, PLL_LOCKTIME_REG_PLL_CPUCL0, PLL_CON7_PLL_CPUCL0, PLL_LOCKTIME_PLL_CPUCL1, PLL_CON3_PLL_CPUCL1, PLL_CON4_PLL_CPUCL1, DBG_NFO_PLL_CPUCL1, PLL_CON0_PLL_CPUCL1, PLL_CON1_PLL_CPUCL1, PLL_CON2_PLL_CPUCL1, PLL_CON6_PLL_CPUCL1, PLL_LOCKTIME_REG_PLL_CPUCL1, PLL_LOCKTIME_PLL_DSU, PLL_CON3_PLL_DSU, PLL_CON9_PLL_DSU, PLL_CON8_PLL_DSU, PLL_CON4_PLL_DSU, PLL_CON5_PLL_DSU, DBG_NFO_PLL_DSU, PLL_CON0_PLL_DSU, PLL_CON1_PLL_DSU, PLL_CON2_PLL_DSU, PLL_CON6_PLL_DSU, PLL_LOCKTIME_REG_PLL_DSU, PLL_CON7_PLL_DSU, PLL_LOCKTIME_PLL_MIF, PLL_CON3_PLL_MIF, PLL_CON4_PLL_MIF, DBG_NFO_PLL_MIF, PLL_CON0_PLL_MIF, PLL_CON1_PLL_MIF, PLL_CON2_PLL_MIF, PLL_LOCKTIME_PLL_MIF_S2D, PLL_CON3_PLL_MIF_S2D, PLL_CON4_PLL_MIF_S2D, DBG_NFO_PLL_MIF_S2D, PLL_CON0_PLL_MIF_S2D, PLL_CON1_PLL_MIF_S2D, PLL_CON2_PLL_MIF_S2D, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS, DBG_NFO_MUX_CLKCMU_CMGP_BUS, CLK_CON_MUX_MUX_CLK_ALIVE_BUS, DBG_NFO_MUX_CLK_ALIVE_BUS, CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI, DBG_NFO_MUX_CLKCMU_CMGP_PERI, CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC, DBG_NFO_MUX_CLK_ALIVE_I3C_PMIC, CLK_CON_MUX_MUX_CLKCMU_CHUBVTS_BUS, DBG_NFO_MUX_CLKCMU_CHUBVTS_BUS, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART, DBG_NFO_MUX_CLK_ALIVE_DBGCORE_UART, CLK_CON_MUX_MUX_CLKCMU_AP2GNSS, DBG_NFO_MUX_CLKCMU_AP2GNSS, CLK_CON_MUX_MUX_CLKCMU_CHUB_PERI, DBG_NFO_MUX_CLKCMU_CHUB_PERI, CLK_CON_MUX_MUX_CLK_ALIVE_USI0, DBG_NFO_MUX_CLK_ALIVE_USI0, CLK_CON_MUX_MUX_CLK_ALIVE_I2C, DBG_NFO_MUX_CLK_ALIVE_I2C, CLK_CON_MUX_MUX_CLK_AUD_UAIF3, DBG_NFO_MUX_CLK_AUD_UAIF3, CLK_CON_MUX_MUX_CLK_AUD_UAIF2, DBG_NFO_MUX_CLK_AUD_UAIF2, CLK_CON_MUX_MUX_CLK_AUD_UAIF1, DBG_NFO_MUX_CLK_AUD_UAIF1, CLK_CON_MUX_MUX_CLK_AUD_UAIF0, DBG_NFO_MUX_CLK_AUD_UAIF0, CLK_CON_MUX_MUX_CLK_AUD_CPU, DBG_NFO_MUX_CLK_AUD_CPU, CLK_CON_MUX_MUX_CLK_AUD_FM, DBG_NFO_MUX_CLK_AUD_FM, CLK_CON_MUX_MUX_CLK_AUD_UAIF4, DBG_NFO_MUX_CLK_AUD_UAIF4, CLK_CON_MUX_MUX_CLK_AUD_UAIF5, DBG_NFO_MUX_CLK_AUD_UAIF5, CLK_CON_MUX_MUX_CLK_AUD_UAIF6, DBG_NFO_MUX_CLK_AUD_UAIF6, CLK_CON_MUX_MUX_CLK_AUD_DSIF, DBG_NFO_MUX_CLK_AUD_DSIF, CLK_CON_MUX_MUX_CLK_AUD_CPU_PLL, DBG_NFO_MUX_CLK_AUD_CPU_PLL, CLK_CON_MUX_MUX_CLK_AUD_BUS, DBG_NFO_MUX_CLK_AUD_BUS, CLK_CON_MUX_MUX_CLK_AUD_PCMC, DBG_NFO_MUX_CLK_AUD_PCMC, CLK_CON_MUX_MUX_BUSC_CMUREF, DBG_NFO_MUX_BUSC_CMUREF, CLK_CON_MUX_MUX_CLK_CHUB_TIMER, DBG_NFO_MUX_CLK_CHUB_TIMER, CLK_CON_MUX_MUX_CLK_CHUB_USI0, DBG_NFO_MUX_CLK_CHUB_USI0, CLK_CON_MUX_MUX_CLK_CHUB_USI1, DBG_NFO_MUX_CLK_CHUB_USI1, CLK_CON_MUX_MUX_CLK_CHUB_USI2, DBG_NFO_MUX_CLK_CHUB_USI2, CLK_CON_MUX_MUX_CLK_CHUB_I2C, DBG_NFO_MUX_CLK_CHUB_I2C, CLK_CON_MUX_MUX_CLK_CHUB_USI3, DBG_NFO_MUX_CLK_CHUB_USI3, CLK_CON_MUX_MUX_CLK_CHUB_BUS, DBG_NFO_MUX_CLK_CHUB_BUS, CLK_CON_MUX_MUX_CLK_CHUBVTS_BUS, DBG_NFO_MUX_CLK_CHUBVTS_BUS, CLK_CON_MUX_MUX_CLK_CMGP_I2C, DBG_NFO_MUX_CLK_CMGP_I2C, CLK_CON_MUX_MUX_CLK_CMGP_USI0, DBG_NFO_MUX_CLK_CMGP_USI0, CLK_CON_MUX_MUX_CLK_CMGP_USI4, DBG_NFO_MUX_CLK_CMGP_USI4, CLK_CON_MUX_MUX_CLK_CMGP_I3C, DBG_NFO_MUX_CLK_CMGP_I3C, CLK_CON_MUX_MUX_CLK_CMGP_BUS, DBG_NFO_MUX_CLK_CMGP_BUS, CLK_CON_MUX_MUX_CLK_CMGP_USI1, DBG_NFO_MUX_CLK_CMGP_USI1, CLK_CON_MUX_MUX_CLK_CMGP_USI2, DBG_NFO_MUX_CLK_CMGP_USI2, CLK_CON_MUX_MUX_CLK_CMGP_USI3, DBG_NFO_MUX_CLK_CMGP_USI3, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, DBG_NFO_MUX_CLKCMU_MFC_MFC, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, DBG_NFO_MUX_CLKCMU_CORE_BUS, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, DBG_NFO_MUX_CLKCMU_MIF_SWITCH, CLK_CON_MUX_MUX_CLKCMU_TAA_BUS, DBG_NFO_MUX_CLKCMU_TAA_BUS, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS, DBG_NFO_MUX_CLKCMU_ISP_BUS, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, DBG_NFO_MUX_CLKCMU_AUD_CPU, CLK_CON_MUX_MUX_CLKCMU_M2M_MSCL, DBG_NFO_MUX_CLKCMU_M2M_MSCL, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS, DBG_NFO_MUX_CLKCMU_CPUCL0_DBG_BUS, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, DBG_NFO_MUX_CLKCMU_CIS_CLK0, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, DBG_NFO_MUX_CLKCMU_CIS_CLK1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, DBG_NFO_MUX_CLKCMU_CIS_CLK2, CLK_CON_MUX_MUX_CLKCMU_HSI_UFS_EMBD, DBG_NFO_MUX_CLKCMU_HSI_UFS_EMBD, CLK_CON_MUX_MUX_CMU_CMUREF, DBG_NFO_MUX_CMU_CMUREF, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, DBG_NFO_MUX_CLKCMU_PERI_BUS, CLK_CON_MUX_MUX_CLKCMU_NPU0_BUS, DBG_NFO_MUX_CLKCMU_NPU0_BUS, CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS, DBG_NFO_MUX_CLKCMU_ALIVE_BUS, CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, DBG_NFO_MUX_CLKCMU_HSI_BUS, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, DBG_NFO_MUX_CLKCMU_MIF_BUSP, CLK_CON_MUX_MUX_CLKCMU_PERI_IP, DBG_NFO_MUX_CLKCMU_PERI_IP, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, DBG_NFO_MUX_CLKCMU_DPU_BUS, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH, CLK_CON_MUX_MUX_CLKCMU_USB_BUS, DBG_NFO_MUX_CLKCMU_USB_BUS, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, DBG_NFO_MUX_CLKCMU_TNR_BUS, CLK_CON_MUX_MUX_CLKCMU_PERI_MMC_CARD, DBG_NFO_MUX_CLKCMU_PERI_MMC_CARD, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, DBG_NFO_MUX_CLKCMU_CMU_BOOST, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, DBG_NFO_MUX_CLKCMU_CORE_G3D, CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, DBG_NFO_MUX_CLKCMU_CSIS_BUS, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS, DBG_NFO_MUX_CLKCMU_MCSC_BUS, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC, DBG_NFO_MUX_CLKCMU_MCSC_GDC, CLK_CON_MUX_MUX_CLKCMU_USB_USB20DRD, DBG_NFO_MUX_CLKCMU_USB_USB20DRD, CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS, DBG_NFO_MUX_CLKCMU_NPUS_BUS, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, DBG_NFO_MUX_CLKCMU_G3D_SWITCH, CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, DBG_NFO_MUX_CLKCMU_CORE_SSS, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS, DBG_NFO_MUX_CLKCMU_BUSC_BUS, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, DBG_NFO_MUX_CLKCMU_CIS_CLK3, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, DBG_NFO_MUX_CLKCMU_CIS_CLK4, CLK_CON_MUX_CLKCMU_G3D_BUS, DBG_NFO_CLKCMU_G3D_BUS, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, DBG_NFO_MUX_CLKCMU_CIS_CLK5, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH, DBG_NFO_MUX_CLKCMU_DSU_SWITCH, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP, DBG_NFO_MUX_CLKCMU_CPUCL0_BUSP, CLK_CON_MUX_MUX_CLKCMU_DPU_DSIM, DBG_NFO_MUX_CLKCMU_DPU_DSIM, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, DBG_NFO_MUX_CLKCMU_MCSC_MCSC, CLK_CON_MUX_MUX_CLKCMU_AUD_BUS, DBG_NFO_MUX_CLKCMU_AUD_BUS, CLK_CON_MUX_MUX_CORE_CMUREF, DBG_NFO_MUX_CORE_CMUREF, CLK_CON_MUX_MUX_CLK_CORE_GIC, DBG_NFO_MUX_CLK_CORE_GIC, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, DBG_NFO_MUX_CLK_CPUCL0_PLL, CLK_CON_MUX_MUX_CPUCL0_CMUREF, DBG_NFO_MUX_CPUCL0_CMUREF, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, DBG_NFO_MUX_CLK_CPUCL1_PLL, CLK_CON_MUX_MUX_CPUCL1_CMUREF, DBG_NFO_MUX_CPUCL1_CMUREF, CLK_CON_MUX_MUX_DSU_CMUREF, DBG_NFO_MUX_DSU_CMUREF, CLK_CON_MUX_MUX_CLK_DSU_PLL, DBG_NFO_MUX_CLK_DSU_PLL, CLK_CON_MUX_MUX_MIF_CMUREF, DBG_NFO_MUX_MIF_CMUREF, CLK_CON_MUX_MUX_CLK_S2D_CORE, DBG_NFO_MUX_CLK_S2D_CORE, CLK_CON_MUX_MUX_CLK_USB_BUS, DBG_NFO_MUX_CLK_USB_BUS, CLK_CON_MUX_MUX_CLK_USB_USB20DRD, DBG_NFO_MUX_CLK_USB_USB20DRD, CLK_CON_MUX_MUX_CLK_VTS_BUS, DBG_NFO_MUX_CLK_VTS_BUS, CLK_CON_MUX_MUX_VTS_DMIC_AUD, DBG_NFO_MUX_VTS_DMIC_AUD, CLK_CON_MUX_MUX_VTS_SERIAL_LIF, DBG_NFO_MUX_VTS_SERIAL_LIF, CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF, DBG_NFO_MUX_CLK_VTS_DMIC_IF, PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER, PLL_CON1_MUX_CLKCMU_ALIVE_BUS_USER, DBG_NFO_MUX_CLKCMU_ALIVE_BUS_USER, PLL_CON0_MUX_CLK_RCO_ALIVE_USER, PLL_CON1_MUX_CLK_RCO_ALIVE_USER, DBG_NFO_MUX_CLK_RCO_ALIVE_USER, PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER, PLL_CON1_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER, DBG_NFO_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER, PLL_CON0_MUX_CLK_ALIVE_TIMER, PLL_CON1_MUX_CLK_ALIVE_TIMER, DBG_NFO_MUX_CLK_ALIVE_TIMER, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, PLL_CON1_MUX_CLKCMU_AUD_CPU_USER, DBG_NFO_MUX_CLKCMU_AUD_CPU_USER, PLL_CON0_MUX_CLKCMU_AUD_BUS_USER, PLL_CON1_MUX_CLKCMU_AUD_BUS_USER, DBG_NFO_MUX_CLKCMU_AUD_BUS_USER, PLL_CON0_MUX_CP_PCMC_CLK_USER, PLL_CON1_MUX_CP_PCMC_CLK_USER, DBG_NFO_MUX_CP_PCMC_CLK_USER, PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER, PLL_CON1_MUX_CLKCMU_BUSC_BUS_USER, DBG_NFO_MUX_CLKCMU_BUSC_BUS_USER, PLL_CON0_MUX_CLK_CHUB_BUS_USER, PLL_CON1_MUX_CLK_CHUB_BUS_USER, DBG_NFO_MUX_CLK_CHUB_BUS_USER, PLL_CON0_MUX_CLKCMU_CHUB_PERI_USER, PLL_CON1_MUX_CLKCMU_CHUB_PERI_USER, DBG_NFO_MUX_CLKCMU_CHUB_PERI_USER, PLL_CON0_MUX_CLKCMU_CHUB_RCO_USER, PLL_CON1_MUX_CLKCMU_CHUB_RCO_USER, DBG_NFO_MUX_CLKCMU_CHUB_RCO_USER, PLL_CON0_MUX_CLKCMU_CHUBVTS_BUS_USER, PLL_CON1_MUX_CLKCMU_CHUBVTS_BUS_USER, DBG_NFO_MUX_CLKCMU_CHUBVTS_BUS_USER, PLL_CON0_MUX_CLKCMU_CHUBVTS_RCO_USER, PLL_CON1_MUX_CLKCMU_CHUBVTS_RCO_USER, DBG_NFO_MUX_CLKCMU_CHUBVTS_RCO_USER, PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER, PLL_CON1_MUX_CLKCMU_CMGP_BUS_USER, DBG_NFO_MUX_CLKCMU_CMGP_BUS_USER, PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER, PLL_CON1_MUX_CLKCMU_CMGP_PERI_USER, DBG_NFO_MUX_CLKCMU_CMGP_PERI_USER, PLL_CON0_MUX_CLKCMU_CMGP_RCO_USER, PLL_CON1_MUX_CLKCMU_CMGP_RCO_USER, DBG_NFO_MUX_CLKCMU_CMGP_RCO_USER, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, PLL_CON1_MUX_CLKCMU_CORE_BUS_USER, DBG_NFO_MUX_CLKCMU_CORE_BUS_USER, PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, PLL_CON1_MUX_CLKCMU_CORE_G3D_USER, DBG_NFO_MUX_CLKCMU_CORE_G3D_USER, PLL_CON0_MUX_CLKCMU_CORE_SSS_USER, PLL_CON1_MUX_CLKCMU_CORE_SSS_USER, DBG_NFO_MUX_CLKCMU_CORE_SSS_USER, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER, DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH_USER, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER, PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_BUS_USER, DBG_NFO_MUX_CLKCMU_CPUCL0_DBG_BUS_USER, PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER, PLL_CON1_MUX_CLKCMU_CPUCL0_BUSP_USER, DBG_NFO_MUX_CLKCMU_CPUCL0_BUSP_USER, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER, DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH_USER, PLL_CON0_MUX_CLKCMU_CSIS_BUS_USER, PLL_CON1_MUX_CLKCMU_CSIS_BUS_USER, DBG_NFO_MUX_CLKCMU_CSIS_BUS_USER, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER, PLL_CON1_MUX_CLKCMU_DPU_BUS_USER, DBG_NFO_MUX_CLKCMU_DPU_BUS_USER, PLL_CON0_MUX_CLKCMU_DPU_DSIM_USER, PLL_CON1_MUX_CLKCMU_DPU_DSIM_USER, DBG_NFO_MUX_CLKCMU_DPU_DSIM_USER, PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER, PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER, DBG_NFO_MUX_CLKCMU_DSU_SWITCH_USER, PLL_CON0_MUX_CLKCMU_G3D_BUS_USER, PLL_CON1_MUX_CLKCMU_G3D_BUS_USER, DBG_NFO_MUX_CLKCMU_G3D_BUS_USER, PLL_CON0_MUX_CLKCMU_HSI_BUS_USER, PLL_CON1_MUX_CLKCMU_HSI_BUS_USER, DBG_NFO_MUX_CLKCMU_HSI_BUS_USER, PLL_CON0_MUX_CLKCMU_HSI_UFS_EMBD_USER, PLL_CON1_MUX_CLKCMU_HSI_UFS_EMBD_USER, DBG_NFO_MUX_CLKCMU_HSI_UFS_EMBD_USER, PLL_CON0_MUX_CLKCMU_ISP_BUS_USER, PLL_CON1_MUX_CLKCMU_ISP_BUS_USER, DBG_NFO_MUX_CLKCMU_ISP_BUS_USER, PLL_CON0_MUX_CLKCMU_M2M_MSCL_USER, PLL_CON1_MUX_CLKCMU_M2M_MSCL_USER, DBG_NFO_MUX_CLKCMU_M2M_MSCL_USER, PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER, PLL_CON1_MUX_CLKCMU_MCSC_BUS_USER, DBG_NFO_MUX_CLKCMU_MCSC_BUS_USER, PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER, PLL_CON1_MUX_CLKCMU_MCSC_GDC_USER, DBG_NFO_MUX_CLKCMU_MCSC_GDC_USER, PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER, PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER, DBG_NFO_MUX_CLKCMU_MCSC_MCSC_USER, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER, PLL_CON1_MUX_CLKCMU_MFC_MFC_USER, DBG_NFO_MUX_CLKCMU_MFC_MFC_USER, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER, PLL_CON1_MUX_CLKCMU_MIF_BUSP_USER, DBG_NFO_MUX_CLKCMU_MIF_BUSP_USER, PLL_CON0_CLKMUX_MIF_DDRPHY2X, PLL_CON1_CLKMUX_MIF_DDRPHY2X, DBG_NFO_CLKMUX_MIF_DDRPHY2X, PLL_CON0_MUX_CLKCMU_NPU0_BUS_USER, PLL_CON1_MUX_CLKCMU_NPU0_BUS_USER, DBG_NFO_MUX_CLKCMU_NPU0_BUS_USER, PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER, PLL_CON1_MUX_CLKCMU_NPUS_BUS_USER, DBG_NFO_MUX_CLKCMU_NPUS_BUS_USER, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, PLL_CON1_MUX_CLKCMU_PERI_BUS_USER, DBG_NFO_MUX_CLKCMU_PERI_BUS_USER, PLL_CON0_MUX_CLKCMU_PERI_USI00_USI_USER, PLL_CON1_MUX_CLKCMU_PERI_USI00_USI_USER, DBG_NFO_MUX_CLKCMU_PERI_USI00_USI_USER, PLL_CON0_MUX_CLKCMU_PERI_USI01_USI_USER, PLL_CON1_MUX_CLKCMU_PERI_USI01_USI_USER, DBG_NFO_MUX_CLKCMU_PERI_USI01_USI_USER, PLL_CON0_MUX_CLKCMU_PERI_USI02_USI_USER, PLL_CON1_MUX_CLKCMU_PERI_USI02_USI_USER, DBG_NFO_MUX_CLKCMU_PERI_USI02_USI_USER, PLL_CON0_MUX_CLKCMU_PERI_USI03_USI_USER, PLL_CON1_MUX_CLKCMU_PERI_USI03_USI_USER, DBG_NFO_MUX_CLKCMU_PERI_USI03_USI_USER, PLL_CON0_MUX_CLKCMU_PERI_USI04_USI_USER, PLL_CON1_MUX_CLKCMU_PERI_USI04_USI_USER, DBG_NFO_MUX_CLKCMU_PERI_USI04_USI_USER, PLL_CON0_MUX_CLKCMU_PERI_USI05_USI_USER, PLL_CON1_MUX_CLKCMU_PERI_USI05_USI_USER, DBG_NFO_MUX_CLKCMU_PERI_USI05_USI_USER, PLL_CON0_MUX_CLKCMU_PERI_USI_I2C_USER, PLL_CON1_MUX_CLKCMU_PERI_USI_I2C_USER, DBG_NFO_MUX_CLKCMU_PERI_USI_I2C_USER, PLL_CON0_MUX_CLKCMU_PERI_UART_DBG, PLL_CON1_MUX_CLKCMU_PERI_UART_DBG, DBG_NFO_MUX_CLKCMU_PERI_UART_DBG, PLL_CON0_MUX_CLKCMU_PERI_MMC_CARD_USER, PLL_CON1_MUX_CLKCMU_PERI_MMC_CARD_USER, DBG_NFO_MUX_CLKCMU_PERI_MMC_CARD_USER, PLL_CON0_MUX_CLKCMU_PERI_USI06_USI_USER, PLL_CON1_MUX_CLKCMU_PERI_USI06_USI_USER, DBG_NFO_MUX_CLKCMU_PERI_USI06_USI_USER, PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D, PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D, DBG_NFO_CLKCMU_MIF_DDRPHY2X_S2D, PLL_CON0_MUX_CLKCMU_TAA_BUS_USER, PLL_CON1_MUX_CLKCMU_TAA_BUS_USER, DBG_NFO_MUX_CLKCMU_TAA_BUS_USER, PLL_CON0_MUX_CLKCMU_TNR_BUS_USER, PLL_CON1_MUX_CLKCMU_TNR_BUS_USER, DBG_NFO_MUX_CLKCMU_TNR_BUS_USER, PLL_CON0_MUX_CLKCMU_USB_BUS_USER, PLL_CON1_MUX_CLKCMU_USB_BUS_USER, DBG_NFO_MUX_CLKCMU_USB_BUS_USER, PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER, PLL_CON1_MUX_CLKCMU_USB_USB20DRD_USER, DBG_NFO_MUX_CLKCMU_USB_USB20DRD_USER, PLL_CON0_MUX_CLKAUD_USB_BUS_USER, PLL_CON1_MUX_CLKAUD_USB_BUS_USER, DBG_NFO_MUX_CLKAUD_USB_BUS_USER, PLL_CON0_MUX_CLKAUD_USB_USB20DRD_USER, PLL_CON1_MUX_CLKAUD_USB_USB20DRD_USER, DBG_NFO_MUX_CLKAUD_USB_USB20DRD_USER, PLL_CON0_MUX_CLKCMU_VTS_BUS_USER, PLL_CON1_MUX_CLKCMU_VTS_BUS_USER, DBG_NFO_MUX_CLKCMU_VTS_BUS_USER, PLL_CON0_MUX_CLKCMU_VTS_RCO_USER, PLL_CON1_MUX_CLKCMU_VTS_RCO_USER, DBG_NFO_MUX_CLKCMU_VTS_RCO_USER, PLL_CON0_MUX_CLK_AUD_DMIC_BUS_USER, PLL_CON1_MUX_CLK_AUD_DMIC_BUS_USER, DBG_NFO_MUX_CLK_AUD_DMIC_BUS_USER, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU, DBG_NFO_MUX_HCHGEN_CLK_AUD_CPU, CLK_CON_DIV_CLKCMU_CMGP_PERI, DBG_NFO_CLKCMU_CMGP_PERI, CLK_CON_DIV_DIV_CLK_ALIVE_BUS, DBG_NFO_DIV_CLK_ALIVE_BUS, CLK_CON_DIV_CLKCMU_CMGP_BUS, DBG_NFO_CLKCMU_CMGP_BUS, CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC, DBG_NFO_DIV_CLK_ALIVE_I3C_PMIC, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART, DBG_NFO_DIV_CLK_ALIVE_DBGCORE_UART, CLK_CON_DIV_CLKCMU_CHUBVTS_BUS, DBG_NFO_CLKCMU_CHUBVTS_BUS, CLK_CON_DIV_CLKCMU_CHUB_PERI, DBG_NFO_CLKCMU_CHUB_PERI, CLK_CON_DIV_DIV_CLK_ALIVE_USI0, DBG_NFO_DIV_CLK_ALIVE_USI0, CLK_CON_DIV_DIV_CLK_ALIVE_I2C, DBG_NFO_DIV_CLK_ALIVE_I2C, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, DBG_NFO_DIV_CLK_AUD_CPU_PCLKDBG, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, DBG_NFO_DIV_CLK_AUD_FM_SPDY, CLK_CON_DIV_DIV_CLK_AUD_UAIF0, DBG_NFO_DIV_CLK_AUD_UAIF0, CLK_CON_DIV_DIV_CLK_AUD_UAIF1, DBG_NFO_DIV_CLK_AUD_UAIF1, CLK_CON_DIV_DIV_CLK_AUD_UAIF2, DBG_NFO_DIV_CLK_AUD_UAIF2, CLK_CON_DIV_DIV_CLK_AUD_UAIF3, DBG_NFO_DIV_CLK_AUD_UAIF3, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, DBG_NFO_DIV_CLK_AUD_CPU_ACLK, CLK_CON_DIV_DIV_CLK_AUD_BUSP, DBG_NFO_DIV_CLK_AUD_BUSP, CLK_CON_DIV_DIV_CLK_AUD_CNT, DBG_NFO_DIV_CLK_AUD_CNT, CLK_CON_DIV_DIV_CLK_AUD_UAIF4, DBG_NFO_DIV_CLK_AUD_UAIF4, CLK_CON_DIV_DIV_CLK_AUD_DSIF, DBG_NFO_DIV_CLK_AUD_DSIF, CLK_CON_DIV_DIV_CLK_AUD_FM, DBG_NFO_DIV_CLK_AUD_FM, CLK_CON_DIV_DIV_CLK_AUD_UAIF5, DBG_NFO_DIV_CLK_AUD_UAIF5, CLK_CON_DIV_DIV_CLK_AUD_UAIF6, DBG_NFO_DIV_CLK_AUD_UAIF6, CLK_CON_DIV_DIV_CLK_AUD_MCLK, DBG_NFO_DIV_CLK_AUD_MCLK, CLK_CON_DIV_DIV_CLK_AUD_AUDIF, DBG_NFO_DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_BUSD, DBG_NFO_DIV_CLK_AUD_BUSD, CLK_CON_DIV_DIV_CLK_AUD_PCMC, DBG_NFO_DIV_CLK_AUD_PCMC, CLK_CON_DIV_CLKAUD_USB_BUS, DBG_NFO_CLKAUD_USB_BUS, CLK_CON_DIV_CLKAUD_USB_USB20DRD, DBG_NFO_CLKAUD_USB_USB20DRD, CLK_CON_DIV_DIV_CLK_AUD_CPU, DBG_NFO_DIV_CLK_AUD_CPU, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP, DBG_NFO_DIV_CLK_AUD_CPU_ACP, CLK_CON_DIV_CLK_AUD_DMIC, DBG_NFO_CLK_AUD_DMIC, CLK_CON_DIV_DIV_CLK_BUSC_BUSP, DBG_NFO_DIV_CLK_BUSC_BUSP, CLK_CON_DIV_DIV_CLK_CHUB_USI0, DBG_NFO_DIV_CLK_CHUB_USI0, CLK_CON_DIV_DIV_CLK_CHUB_USI1, DBG_NFO_DIV_CLK_CHUB_USI1, CLK_CON_DIV_DIV_CLK_CHUB_USI2, DBG_NFO_DIV_CLK_CHUB_USI2, CLK_CON_DIV_DIV_CLK_CHUB_I2C, DBG_NFO_DIV_CLK_CHUB_I2C, CLK_CON_DIV_DIV_CLK_CHUB_USI3, DBG_NFO_DIV_CLK_CHUB_USI3, CLK_CON_DIV_DIV_CLK_CHUB_BUS, DBG_NFO_DIV_CLK_CHUB_BUS, CLK_CON_DIV_DIV_CLK_CHUBVTS_BUS, DBG_NFO_DIV_CLK_CHUBVTS_BUS, CLK_CON_DIV_DIV_CLK_CMGP_I2C, DBG_NFO_DIV_CLK_CMGP_I2C, CLK_CON_DIV_DIV_CLK_CMGP_USI0, DBG_NFO_DIV_CLK_CMGP_USI0, CLK_CON_DIV_DIV_CLK_CMGP_USI4, DBG_NFO_DIV_CLK_CMGP_USI4, CLK_CON_DIV_DIV_CLK_CMGP_I3C, DBG_NFO_DIV_CLK_CMGP_I3C, CLK_CON_DIV_DIV_CLK_CMGP_USI1, DBG_NFO_DIV_CLK_CMGP_USI1, CLK_CON_DIV_DIV_CLK_CMGP_USI2, DBG_NFO_DIV_CLK_CMGP_USI2, CLK_CON_DIV_DIV_CLK_CMGP_USI3, DBG_NFO_DIV_CLK_CMGP_USI3, CLK_CON_DIV_CLKCMU_ALIVE_BUS, DBG_NFO_CLKCMU_ALIVE_BUS, CLK_CON_DIV_CLKCMU_G3D_SWITCH, DBG_NFO_CLKCMU_G3D_SWITCH, CLK_CON_DIV_CLKCMU_PERI_BUS, DBG_NFO_CLKCMU_PERI_BUS, CLK_CON_DIV_CLKCMU_DPU_BUS, DBG_NFO_CLKCMU_DPU_BUS, CLK_CON_DIV_CLKCMU_MFC_MFC, DBG_NFO_CLKCMU_MFC_MFC, CLK_CON_DIV_CLKCMU_CORE_BUS, DBG_NFO_CLKCMU_CORE_BUS, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, DBG_NFO_CLKCMU_CPUCL0_SWITCH, CLK_CON_DIV_CLKCMU_TAA_BUS, DBG_NFO_CLKCMU_TAA_BUS, CLK_CON_DIV_CLKCMU_ISP_BUS, DBG_NFO_CLKCMU_ISP_BUS, CLK_CON_DIV_CLKCMU_AUD_CPU, DBG_NFO_CLKCMU_AUD_CPU, CLK_CON_DIV_CLKCMU_M2M_MSCL, DBG_NFO_CLKCMU_M2M_MSCL, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS, DBG_NFO_CLKCMU_CPUCL0_DBG_BUS, CLK_CON_DIV_CLKCMU_CIS_CLK0, DBG_NFO_CLKCMU_CIS_CLK0, CLK_CON_DIV_CLKCMU_CIS_CLK1, DBG_NFO_CLKCMU_CIS_CLK1, CLK_CON_DIV_CLKCMU_CIS_CLK2, DBG_NFO_CLKCMU_CIS_CLK2, CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD, DBG_NFO_CLKCMU_HSI_UFS_EMBD, CLK_CON_DIV_CLKCMU_NPU0_BUS, DBG_NFO_CLKCMU_NPU0_BUS, CLK_CON_DIV_CLKCMU_MIF_BUSP, DBG_NFO_CLKCMU_MIF_BUSP, CLK_CON_DIV_CLKCMU_PERI_IP, DBG_NFO_CLKCMU_PERI_IP, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, DBG_NFO_CLKCMU_CPUCL1_SWITCH, CLK_CON_DIV_CLKCMU_USB_BUS, DBG_NFO_CLKCMU_USB_BUS, CLK_CON_DIV_CLKCMU_TNR_BUS, DBG_NFO_CLKCMU_TNR_BUS, CLK_CON_DIV_CLKCMU_CMU_BOOST, DBG_NFO_CLKCMU_CMU_BOOST, CLK_CON_DIV_CLKCMU_CORE_G3D, DBG_NFO_CLKCMU_CORE_G3D, CLK_CON_DIV_CLKCMU_CSIS_BUS, DBG_NFO_CLKCMU_CSIS_BUS, CLK_CON_DIV_CLKCMU_MCSC_BUS, DBG_NFO_CLKCMU_MCSC_BUS, CLK_CON_DIV_CLKCMU_HSI_BUS, DBG_NFO_CLKCMU_HSI_BUS, CLK_CON_DIV_CLKCMU_PERI_MMC_CARD, DBG_NFO_CLKCMU_PERI_MMC_CARD, CLK_CON_DIV_CLKCMU_MCSC_GDC, DBG_NFO_CLKCMU_MCSC_GDC, CLK_CON_DIV_CLKCMU_USB_USB20DRD, DBG_NFO_CLKCMU_USB_USB20DRD, CLK_CON_DIV_CLKCMU_NPUS_BUS, DBG_NFO_CLKCMU_NPUS_BUS, CLK_CON_DIV_CLKCMU_CORE_SSS, DBG_NFO_CLKCMU_CORE_SSS, CLK_CON_DIV_CLKCMU_BUSC_BUS, DBG_NFO_CLKCMU_BUSC_BUS, CLK_CON_DIV_CLKCMU_CIS_CLK3, DBG_NFO_CLKCMU_CIS_CLK3, CLK_CON_DIV_CLKCMU_CIS_CLK4, DBG_NFO_CLKCMU_CIS_CLK4, CLK_CON_DIV_CLKCMU_CIS_CLK5, DBG_NFO_CLKCMU_CIS_CLK5, CLK_CON_DIV_CLKCMU_DSU_SWITCH, DBG_NFO_CLKCMU_DSU_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL0_BUSP, DBG_NFO_CLKCMU_CPUCL0_BUSP, CLK_CON_DIV_CLKCMU_DPU_DSIM, DBG_NFO_CLKCMU_DPU_DSIM, CLK_CON_DIV_CLKCMU_MCSC_MCSC, DBG_NFO_CLKCMU_MCSC_MCSC, CLK_CON_DIV_CLKCMU_AUD_BUS, DBG_NFO_CLKCMU_AUD_BUS, CLK_CON_DIV_DIV_CLK_CORE_BUSP, DBG_NFO_DIV_CLK_CORE_BUSP, CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP, DBG_NFO_DIV_CLK_CPUCL0_SHORTSTOP, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG, DBG_NFO_DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP, DBG_NFO_DIV_CLK_CPUCL1_SHORTSTOP, CLK_CON_DIV_DIV_CLK_CPUCL1_HTU, DBG_NFO_DIV_CLK_CPUCL1_HTU, CLK_CON_DIV_DIV_CLK_CSIS_BUSP, DBG_NFO_DIV_CLK_CSIS_BUSP, CLK_CON_DIV_DIV_CLK_DPU_BUSP, DBG_NFO_DIV_CLK_DPU_BUSP, CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP, DBG_NFO_DIV_CLK_DSU_SHORTSTOP, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, DBG_NFO_DIV_CLK_CLUSTER0_ACLK, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, DBG_NFO_DIV_CLK_CLUSTER0_ATCLK, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK, DBG_NFO_DIV_CLK_CLUSTER0_PCLK, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, DBG_NFO_DIV_CLK_CLUSTER0_PERIPHCLK, CLK_CON_DIV_DIV_CLK_G3D_BUSP, DBG_NFO_DIV_CLK_G3D_BUSP, CLK_CON_DIV_DIV_CLK_ISP_BUSP, DBG_NFO_DIV_CLK_ISP_BUSP, CLK_CON_DIV_DIV_CLK_M2M_BUSP, DBG_NFO_DIV_CLK_M2M_BUSP, CLK_CON_DIV_DIV_CLK_MCSC_BUSP, DBG_NFO_DIV_CLK_MCSC_BUSP, CLK_CON_DIV_DIV_CLK_MFC_BUSP, DBG_NFO_DIV_CLK_MFC_BUSP, CLK_CON_DIV_DIV_CLK_NPU0_BUSP, DBG_NFO_DIV_CLK_NPU0_BUSP, CLK_CON_DIV_DIV_CLK_NPUS_BUSP, DBG_NFO_DIV_CLK_NPUS_BUSP, CLK_CON_DIV_DIV_CLK_PERI_USI00_USI, DBG_NFO_DIV_CLK_PERI_USI00_USI, CLK_CON_DIV_DIV_CLK_PERI_USI01_USI, DBG_NFO_DIV_CLK_PERI_USI01_USI, CLK_CON_DIV_DIV_CLK_PERI_USI02_USI, DBG_NFO_DIV_CLK_PERI_USI02_USI, CLK_CON_DIV_DIV_CLK_PERI_USI03_USI, DBG_NFO_DIV_CLK_PERI_USI03_USI, CLK_CON_DIV_DIV_CLK_PERI_USI04_USI, DBG_NFO_DIV_CLK_PERI_USI04_USI, CLK_CON_DIV_DIV_CLK_PERI_USI05_USI, DBG_NFO_DIV_CLK_PERI_USI05_USI, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C, DBG_NFO_DIV_CLK_PERI_USI_I2C, CLK_CON_DIV_DIV_CLK_PERI_UART_DBG, DBG_NFO_DIV_CLK_PERI_UART_DBG, CLK_CON_DIV_DIV_CLK_PERI_USI06_USI, DBG_NFO_DIV_CLK_PERI_USI06_USI, CLK_CON_DIV_DIV_CLK_TAA_BUSP, DBG_NFO_DIV_CLK_TAA_BUSP, CLK_CON_DIV_DIV_CLK_TNR_BUSP, DBG_NFO_DIV_CLK_TNR_BUSP, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF, DBG_NFO_DIV_CLK_VTS_DMIC_IF, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2, DBG_NFO_DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_DIV_DIV_CLK_VTS_BUS, DBG_NFO_DIV_CLK_VTS_BUS, CLK_CON_DIV_DIV_VTS_DMIC_AUD, DBG_NFO_DIV_VTS_DMIC_AUD, CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIV2, DBG_NFO_DIV_VTS_DMIC_AUD_DIV2, CLK_CON_DIV_DIV_VTS_SERIAL_LIF_CORE, DBG_NFO_DIV_VTS_SERIAL_LIF_CORE, CLK_CON_DIV_DIV_VTS_SERIAL_LIF, DBG_NFO_DIV_VTS_SERIAL_LIF, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, DBG_NFO_DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU, DBG_NFO_DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_DSU_CLUSTER, DBG_NFO_DIV_CLK_DSU_CLUSTER, CLK_CON_DIV_DIV_CLK_G3D_BUSD, DBG_NFO_DIV_CLK_G3D_BUSD, CLK_CON_DIV_DIV_CLK_NPU0_BUS, DBG_NFO_DIV_CLK_NPU0_BUS, CLK_CON_DIV_DIV_CLK_NPUS_BUS, DBG_NFO_DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_D_APM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_D_TZPC_ALIVE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_C_CMGP_IPCLKPORT_I_CLK, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_GNSS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_MODEM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_CHUBVTS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_WLBT_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_CHUB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_ABOX_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_WL_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_WLBT_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_WLBT_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_WL_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_SCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_CHUB_RTC_IPCLKPORT_PCLK, CLK_CON_GAT_CLKCMU_VTS_RCO, CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS, CLK_CON_GAT_AP2GNSS_CLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_BT_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_BT_IPCLKPORT_PCLK, CLK_CON_GAT_GATE_CLKCMU_CHUB_PERI, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I2C_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_USI0_IPCLKPORT_CLK, CLK_CON_GAT_CLKCMU_CHUB_RCO, CLK_CON_GAT_CLKCMU_CMGP_RCO, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK, CLK_CON_GAT_CLKCMU_CHUBVTS_RCO, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_LH_AXI_SI_D_AUD_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_NS_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S2_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_SPDY_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_D_USBAUD_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_DBG_IPCLKPORT_CLK, CLK_CON_GAT_GATE_CLKAUD_USB_BUS, CLK_CON_GAT_GATE_CLKAUD_USB_USB20DRD, CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_0, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_2, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_VGENLITE_AUD_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_OSC_SPDY, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_SPDY, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_P_BUSC_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_D_BUSC_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_PERI_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_USB_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_MFC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_APM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA_BUSC_IPCLKPORT_ACLK_PDMA0, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_BUSC_IPCLKPORT_ACLK_PDMA1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSMMU_AXI_D_BUSC_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_PDMA_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_P_BUSC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_D_TZPC_BUSC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_CHUBVTS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_SPDMA_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_SR_CLK_BUSC_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI1_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI2_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2WLBT_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUBEINT_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI3_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_SI_M_CHUB_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_MI_S_CHUB_IPCLKPORT_I_CLK, CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_LH_AXI_SI_D_CHUBVTS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_CHUB_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_VTS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_C_CHUBVTS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_CHUB_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_VTS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SWEEPER_C_CHUBVTS_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BPS_LP_CHUBVTS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_BUS_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SLH_AXI_MI_C_CMGP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI4_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK, CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS, CLK_CON_GAT_CLKCMU_MIF_SWITCH, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, CLK_CON_GAT_GATE_CLKCMU_PERI_MMC_CARD, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, CLK_CON_GAT_GATE_CLKCMU_TAA_BUS, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, CLK_CON_GAT_GATE_CLKCMU_M2M_MSCL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, CLK_CON_GAT_GATE_CLKCMU_HSI_UFS_EMBD, CLK_CON_GAT_GATE_CLKCMU_NPU0_BUS, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, CLK_CON_GAT_GATE_CLKCMU_PERI_IP, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, CLK_CON_GAT_GATE_CLKCMU_USB_BUS, CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS, CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC, CLK_CON_GAT_GATE_CLKCMU_G3D_BUS, CLK_CON_GAT_GATE_CLKCMU_USB_USB20DRD, CLK_CON_GAT_AP2CP_SHARED0_CLK, CLK_CON_GAT_AP2CP_SHARED1_CLK, CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS, CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, CLK_CON_GAT_AP2CP_SHARED2_CLK, CLK_CON_GAT_AP2CP_HISPEEDY_CLK, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP, CLK_CON_GAT_GATE_CLKCMU_DPU_DSIM, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, CLK_CON_GAT_GATE_CLKCMU_AUD_BUS, CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_HSI_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_WLBT_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_WLBT_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_GNSS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_NRT_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKS, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_USB_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_AUD_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_CP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_NRT_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_HSI_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TAA_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_ISP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPU0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_PERI_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_SSS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_SSS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D_DIT_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D_SSS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_CP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_PUF_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPUS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_RT_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_RT_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_BUSC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_G3D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_D_SSS_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_G_BDU_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_NPUS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_NPUS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D2_MODEM_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_I_ARESETN_SSS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AST_MI_G_CPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_P_CLUSTER0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_CORE_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_VGEN_LITE_CORE_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_M2M_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_CORECLK_AN, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_CSSYS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_DBGCORE_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_CSSYS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_DBGCORE_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CORECLK_HC, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF0_CSISTAA_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF1_CSISTAA_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF0_TAACSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF1_TAACSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D3_CSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF2_CSISTAA_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF2_TAACSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE0_CSIS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE1_CSIS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE2_CSIS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DECON, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DMA, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DPP, CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_C2SERV, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S2, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_IPCLKPORT_I_NEWCLK, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_SR_CLK_DPU_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_XIU_D_CPUCL0_IPCLKPORT_ACLK, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D0_MIF_CPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D1_MIF_CPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AST_SI_G_CPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_D_G3D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_SYSMMU_D_G3D_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSMMU_D_G3D_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_D0_G3D_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_VGENLITE_G3D_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_HSI_UID_VGEN_LITE_HSI_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_HSI_UID_HSI_CMU_HSI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_SI_D_HSI_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_MI_P_HSI_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_BUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_HSI_UID_D_TZPC_HSI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, CLK_CON_GAT_GOUT_BLK_HSI_UID_S2MPU_D_HSI_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_UFS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_SR_CLK_HSI_BUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_D_TZPC_ISP_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_ISP_UID_LH_AXI_SI_D_ISP_IPCLKPORT_I_CLK, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_ITP_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_ITP_CLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_DNS_CLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S1, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF_TAAISP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_SI_OTF_ISPMCSC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF0_TNRISP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF1_TNRISP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_XIU_D_ISP_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_VGEN_LITE_ISP_IPCLKPORT_PCLKM, CLK_CON_GAT_CLK_BLK_ISP_UID_VGEN_LITE_ISP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_SLH_AXI_MI_P_ISP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_SR_CLK_ISP_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_JPEG0_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK, CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_M2M_UID_LH_AXI_SI_D_M2M_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_VGEN_LITE_M2M_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKM, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_GDC_IPCLKPORT_ACLKM, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D3_CSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_ISP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_TAA_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_OTF_ISPMCSC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D_MCSC_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_C2CLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_SYSMMU_D0_MCSC_NS_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_MCSC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_GDC_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKS, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_SR_CLK_MFC_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D_MFC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MFC_UID_VGEN_LITE_MFC_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDRPHY_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CPU_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_RT_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_NRT_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CP_IPCLKPORT_I_CLK, CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_NPU0_UID_NPU0_CMU_NPU0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_NPU0_UID_D_TZPC_NPU0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SYSREG_NPU0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SLH_AXI_MI_P_NPU0_IPCLKPORT_I_CLK, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_PCLK, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D_CTRL_NPU0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D0_NPU0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_RQ_NPU0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_CMDQ_NPU0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D1_NPU0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_RQ_NPU0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D_CTRL_NPU0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPU0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPUS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPUS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_CMDQ_NPU0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPU0_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_0_IPCLKPORT_MAINCLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_1_IPCLKPORT_MAINCLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK, CLK_CON_GAT_CLK_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_INT_NPUS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_SI_P_INT_NPUS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKM, CLK_CON_GAT_CLK_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_NPUS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_SR_CLK_NPUS_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK, CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI_I2C_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI01_USI_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI02_USI_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI03_USI_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI04_USI_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI05_USI_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_DBG_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_MI_P_PERI_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_XIU_P_PERI_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_TMU_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_IPCLKPORT_I_PCLK_S0, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_VGEN_LITE_PERI_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_S2MPU_D_PERI_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_I_ACLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_SDCLKIN, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_SI_D_PERI_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERIMMC_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI06_USI_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_IPCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_SR_CLK_PERI_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK, CLK_CON_GAT_GOUT_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AXI_SI_D_TAA_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_SLH_AXI_MI_P_TAA_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_OTF_TAAISP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF0_CSISTAA_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF1_CSISTAA_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF0_TAACSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF1_TAACSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT, CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S1, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF2_CSISTAA_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF2_TAACSIS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE0_TAA_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE1_TAA_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_SR_CLK_TAA_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_TNR_0_IPCLKPORT_PCLKM, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP0, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSP_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF0_TNRISP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF1_TNRISP_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP1, CLK_CON_GAT_GOUT_BLK_TNR_UID_VGEN_LITE_D_TNR_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_SR_CLK_TNR_BUSD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_26, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USB_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_USB_UID_VGEN_LITE_USB_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_USB_UID_D_TZPC_USB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_MI_P_USB_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_USB_UID_S2MPU_D_USB_IPCLKPORT_CLK_S2, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_ACLK_PHYCTRL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_BUS_CLK_EARLY, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_USB_UID_XIU_D_USB_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USBAUD_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_USB_UID_URAM_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_SR_CLK_USB_BUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_VTS_IPCLKPORT_HCLK, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU, CLK_CON_GAT_GOUT_BLK_VTS_UID_CM4_VTS_IPCLKPORT_FCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_VTS_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_MI_S_VTS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_SI_M_VTS_IPCLKPORT_I_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS, CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_SCAN_MUX_IPCLKPORT_D0, CLK_CON_GAT_GOUT_BLK_VTS_UID_AXI2AHB_VTS_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB2AXI_VTS_IPCLKPORT_ACLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_HCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_BCLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK, CLK_CON_DIV_CLKCMU_OTP, CLK_CON_DIV_DIV_CLK_MIF_BUSD, CLK_CON_DIV_CLK_MIF_BUSD_S2D, QCH_CON_ALIVE_CMU_ALIVE_QCH, QCH_CON_APBIF_CHUB_RTC_QCH, QCH_CON_APBIF_GPIO_ALIVE_QCH, QCH_CON_APBIF_PMU_ALIVE_QCH, QCH_CON_APBIF_RTC_QCH, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH, QCH_CON_APBIF_TOP_RTC_QCH, QCH_CON_DBGCORE_UART_QCH, QCH_CON_D_TZPC_ALIVE_QCH, QCH_CON_GREBEINTEGRATION_QCH_GREBE, QCH_CON_GREBEINTEGRATION_QCH_DBG, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH, QCH_CON_I2C_ALIVE0_QCH, QCH_CON_I3C_APM_PMIC_QCH_P, QCH_CON_I3C_APM_PMIC_QCH_S, QCH_CON_INTMEM_QCH, QCH_CON_MAILBOX_APM_AP_QCH, QCH_CON_MAILBOX_APM_CHUB_QCH, QCH_CON_MAILBOX_APM_CP_QCH, QCH_CON_MAILBOX_APM_GNSS_QCH, QCH_CON_MAILBOX_APM_VTS_QCH, QCH_CON_MAILBOX_APM_WLBT_QCH, QCH_CON_MAILBOX_AP_CHUB_QCH, QCH_CON_MAILBOX_AP_CP_QCH, QCH_CON_MAILBOX_AP_CP_S_QCH, QCH_CON_MAILBOX_AP_DBGCORE_QCH, QCH_CON_MAILBOX_AP_GNSS_QCH, QCH_CON_MAILBOX_AP_WLBT_BT_QCH, QCH_CON_MAILBOX_AP_WLBT_WL_QCH, QCH_CON_MAILBOX_CP_CHUB_QCH, QCH_CON_MAILBOX_CP_GNSS_QCH, QCH_CON_MAILBOX_CP_WLBT_BT_QCH, QCH_CON_MAILBOX_CP_WLBT_WL_QCH, QCH_CON_MAILBOX_GNSS_CHUB_QCH, QCH_CON_MAILBOX_GNSS_WLBT_QCH, QCH_CON_MAILBOX_SHARED_SRAM_QCH, QCH_CON_MAILBOX_VTS_CHUB_QCH, QCH_CON_MAILBOX_WLBT_ABOX_QCH, QCH_CON_MAILBOX_WLBT_CHUB_QCH, QCH_CON_PMU_INTR_GEN_QCH, QCH_CON_ROM_CRC32_HOST_QCH, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH, QCH_CON_SLH_AXI_MI_C_CHUBVTS_QCH, QCH_CON_SLH_AXI_MI_C_GNSS_QCH, QCH_CON_SLH_AXI_MI_C_MODEM_QCH, QCH_CON_SLH_AXI_MI_C_WLBT_QCH, QCH_CON_SLH_AXI_MI_P_APM_QCH, QCH_CON_SLH_AXI_SI_C_CMGP_QCH, QCH_CON_SLH_AXI_SI_D_APM_QCH, QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH, QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH, QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH, QCH_CON_SS_DBGCORE_QCH_GREBE, QCH_CON_SS_DBGCORE_QCH_DBG, QCH_CON_SYSREG_ALIVE_QCH, QCH_CON_USI_ALIVE0_QCH, QCH_CON_VGEN_LITE_ALIVE_QCH, QCH_CON_WDT_ALIVE_QCH, QCH_CON_ABOX_QCH_ACLK, QCH_CON_ABOX_QCH_BCLK_DSIF, QCH_CON_ABOX_QCH_BCLK0, QCH_CON_ABOX_QCH_BCLK1, QCH_CON_ABOX_QCH_BCLK2, QCH_CON_ABOX_QCH_BCLK3, QCH_CON_ABOX_QCH_BCLK4, QCH_CON_ABOX_QCH_CNT, QCH_CON_ABOX_QCH_CCLK_ASB, QCH_CON_ABOX_QCH_BCLK5, QCH_CON_ABOX_QCH_BCLK6, DMYQCH_CON_ABOX_QCH_CPU, QCH_CON_ABOX_QCH_PCMC_CLK, QCH_CON_ABOX_QCH_C2A0, QCH_CON_ABOX_QCH_C2A1, QCH_CON_ABOX_QCH_XCLK0, QCH_CON_ABOX_QCH_XCLK1, QCH_CON_ABOX_QCH_XCLK2, QCH_CON_ABOX_QCH_CPU0, QCH_CON_ABOX_QCH_CPU1, QCH_CON_ABOX_QCH_NEON0, QCH_CON_ABOX_QCH_NEON1, QCH_CON_ABOX_QCH_L2, QCH_CON_ABOX_QCH_CCLK_ACP, QCH_CON_AUD_CMU_AUD_QCH, DMYQCH_CON_DFTMUX_AUD_QCH, QCH_CON_D_TZPC_AUD_QCH, QCH_CON_LH_AXI_SI_D_AUD_QCH, QCH_CON_MAILBOX_AUD0_QCH, QCH_CON_MAILBOX_AUD1_QCH, QCH_CON_PPMU_AUD_QCH, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH, QCH_CON_SLH_AXI_MI_D_USBAUD_QCH, QCH_CON_SLH_AXI_MI_P_AUD_QCH, QCH_CON_SYSMMU_AUD_QCH_S1, QCH_CON_SYSMMU_AUD_QCH_S2, QCH_CON_SYSREG_AUD_QCH, QCH_CON_VGEN_LITE_AUD_QCH, QCH_CON_WDT_AUD_QCH, QCH_CON_BUSC_CMU_BUSC_QCH, DMYQCH_CON_CMU_BUSC_CMUREF_QCH, QCH_CON_D_TZPC_BUSC_QCH, QCH_CON_LH_AXI_MI_D_CHUBVTS_QCH, QCH_CON_LH_AXI_MI_D_MFC_QCH, QCH_CON_PDMA_BUSC_QCH, QCH_CON_SLH_AXI_MI_D_APM_QCH, QCH_CON_SLH_AXI_MI_D_PERI_QCH, QCH_CON_SLH_AXI_MI_D_USB_QCH, QCH_CON_SLH_AXI_MI_P_BUSC_QCH, QCH_CON_SPDMA_BUSC_QCH, QCH_CON_SYSMMU_AXI_D_BUSC_QCH, QCH_CON_SYSREG_BUSC_QCH, QCH_CON_TREX_D_BUSC_QCH, QCH_CON_VGEN_PDMA_QCH, QCH_CON_VGEN_SPDMA_QCH, QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH, QCH_CON_APBIF_GPIO_CHUB_QCH, QCH_CON_APBIF_GPIO_CHUBEINT_QCH, QCH_CON_CHUB_CMU_CHUB_QCH, QCH_CON_CM4_CHUB_QCH_CPU, QCH_CON_I2C_CHUB1_QCH, QCH_CON_I2C_CHUB3_QCH, QCH_CON_PWM_CHUB_QCH, QCH_CON_SLH_AXI_MI_S_CHUB_QCH, QCH_CON_SLH_AXI_SI_M_CHUB_QCH, QCH_CON_SYSREG_CHUB_QCH, QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH, QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH, QCH_CON_SYSREG_COMBINE_CHUB2WLBT_QCH, QCH_CON_TIMER_CHUB_QCH, QCH_CON_USI_CHUB0_QCH, QCH_CON_USI_CHUB1_QCH, QCH_CON_USI_CHUB2_QCH, QCH_CON_USI_CHUB3_QCH, QCH_CON_WDT_CHUB_QCH, QCH_CON_BAAW_CHUB_QCH, QCH_CON_BAAW_VTS_QCH, QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH, QCH_CON_D_TZPC_CHUBVTS_QCH, QCH_CON_LH_AXI_SI_D_CHUBVTS_QCH, QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH, QCH_CON_SLH_AXI_MI_M_CHUB_QCH, QCH_CON_SLH_AXI_MI_M_VTS_QCH, QCH_CON_SLH_AXI_SI_C_CHUBVTS_QCH, QCH_CON_SLH_AXI_SI_S_CHUB_QCH, QCH_CON_SLH_AXI_SI_S_VTS_QCH, QCH_CON_SWEEPER_C_CHUBVTS_QCH, QCH_CON_SYSREG_CHUBVTS_QCH, QCH_CON_VGEN_LITE_CHUBVTS_QCH, QCH_CON_CMGP_CMU_CMGP_QCH, QCH_CON_D_TZPC_CMGP_QCH, QCH_CON_GPIO_CMGP_QCH, QCH_CON_I2C_CMGP0_QCH, QCH_CON_I2C_CMGP1_QCH, QCH_CON_I2C_CMGP2_QCH, QCH_CON_I2C_CMGP3_QCH, QCH_CON_I2C_CMGP4_QCH, QCH_CON_I3C_CMGP_QCH_P, QCH_CON_I3C_CMGP_QCH_S, QCH_CON_SLH_AXI_MI_C_CMGP_QCH, QCH_CON_SYSREG_CMGP_QCH, QCH_CON_SYSREG_CMGP2APM_QCH, QCH_CON_SYSREG_CMGP2CHUB_QCH, QCH_CON_SYSREG_CMGP2CP_QCH, QCH_CON_SYSREG_CMGP2GNSS_QCH, QCH_CON_SYSREG_CMGP2PMU_AP_QCH, QCH_CON_SYSREG_CMGP2WLBT_QCH, QCH_CON_USI_CMGP0_QCH, QCH_CON_USI_CMGP1_QCH, QCH_CON_USI_CMGP2_QCH, QCH_CON_USI_CMGP3_QCH, QCH_CON_USI_CMGP4_QCH, DMYQCH_CON_CMU_CMU_CMUREF_QCH, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK4, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK5, DMYQCH_CON_OTP_QCH, DMYQCH_CON_ADM_APB_G_BDU_QCH, QCH_CON_BAAW_D_SSS_QCH, QCH_CON_BAAW_P_GNSS_QCH, QCH_CON_BAAW_P_MODEM_QCH, QCH_CON_BAAW_P_WLBT_QCH, QCH_CON_BDU_QCH, DMYQCH_CON_CMU_CORE_CMUREF_QCH, QCH_CON_CORE_CMU_CORE_QCH, QCH_CON_DIT_QCH, QCH_CON_D_TZPC_CORE_QCH, QCH_CON_GIC_QCH, QCH_CON_HW_APBSEMA_MEC_QCH, QCH_CON_LH_AST_MI_G_CPU_QCH, QCH_CON_LH_AXI_MI_D0_DPU_QCH, QCH_CON_LH_AXI_MI_D0_NPUS_QCH, QCH_CON_LH_AXI_MI_D1_DPU_QCH, QCH_CON_LH_AXI_MI_D1_NPUS_QCH, QCH_CON_LH_AXI_MI_D_AUD_QCH, QCH_CON_LH_AXI_MI_D_G3D_QCH, QCH_CON_LH_AXI_MI_D_M2M_QCH, QCH_CON_LH_AXI_MI_D_SSS_QCH, QCH_CON_LH_AXI_SI_D0_MIF_CP_QCH, QCH_CON_LH_AXI_SI_D0_MIF_NRT_QCH, QCH_CON_LH_AXI_SI_D0_MIF_RT_QCH, QCH_CON_LH_AXI_SI_D1_MIF_CP_QCH, QCH_CON_LH_AXI_SI_D1_MIF_NRT_QCH, QCH_CON_LH_AXI_SI_D1_MIF_RT_QCH, QCH_CON_LH_AXI_SI_D_SSS_QCH, DMYQCH_CON_PUF_QCH, QCH_CON_RSTNSYNC_I_ARESETN_SSS_QCH, QCH_CON_SFR_APBIF_CMU_TOPC_QCH, QCH_CON_SIREX_QCH, QCH_CON_SLH_AXI_MI_D0_MODEM_QCH, QCH_CON_SLH_AXI_MI_D1_MODEM_QCH, QCH_CON_SLH_AXI_MI_D_GNSS_QCH, QCH_CON_SLH_AXI_MI_D_HSI_QCH, QCH_CON_SLH_AXI_MI_D_WLBT_QCH, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH, QCH_CON_SLH_AXI_MI_P_CLUSTER0_QCH, QCH_CON_SLH_AXI_SI_P_APM_QCH, QCH_CON_SLH_AXI_SI_P_AUD_QCH, QCH_CON_SLH_AXI_SI_P_BUSC_QCH, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH, QCH_CON_SLH_AXI_SI_P_CSIS_QCH, QCH_CON_SLH_AXI_SI_P_DPU_QCH, QCH_CON_SLH_AXI_SI_P_G3D_QCH, QCH_CON_SLH_AXI_SI_P_GNSS_QCH, QCH_CON_SLH_AXI_SI_P_HSI_QCH, QCH_CON_SLH_AXI_SI_P_ISP_QCH, QCH_CON_SLH_AXI_SI_P_M2M_QCH, QCH_CON_SLH_AXI_SI_P_MCSC_QCH, QCH_CON_SLH_AXI_SI_P_MCW_QCH, QCH_CON_SLH_AXI_SI_P_MFC_QCH, QCH_CON_SLH_AXI_SI_P_MIF0_QCH, QCH_CON_SLH_AXI_SI_P_MIF1_QCH, QCH_CON_SLH_AXI_SI_P_MODEM_QCH, QCH_CON_SLH_AXI_SI_P_NPU0_QCH, QCH_CON_SLH_AXI_SI_P_NPUS_QCH, QCH_CON_SLH_AXI_SI_P_PERI_QCH, QCH_CON_SLH_AXI_SI_P_TAA_QCH, QCH_CON_SLH_AXI_SI_P_TNR_QCH, QCH_CON_SLH_AXI_SI_P_USB_QCH, QCH_CON_SLH_AXI_SI_P_WLBT_QCH, QCH_CON_SSS_QCH, QCH_CON_SYSMMU_ACEL_D2_MODEM_QCH, QCH_CON_SYSMMU_ACEL_D_DIT_QCH, QCH_CON_SYSREG_CORE_QCH, QCH_CON_TREX_D_CORE_QCH, QCH_CON_TREX_D_NRT_QCH, QCH_CON_TREX_P_CORE_QCH, QCH_CON_VGEN_LITE_CORE_QCH, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH, DMYQCH_CON_CPUCL0_QCH, QCH_CON_CPUCL0_CMU_CPUCL0_QCH, QCH_CON_HTU_CPUCL0_QCH_PCLK, QCH_CON_HTU_CPUCL0_QCH_CLK, QCH_CON_BPS_CPUCL0_QCH, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH, DMYQCH_CON_CSSYS_QCH, QCH_CON_D_TZPC_CPUCL0_QCH, QCH_CON_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH, QCH_CON_SECJTAG_QCH, QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH, QCH_CON_SLH_AXI_MI_G_INT_CSSYS_QCH, QCH_CON_SLH_AXI_MI_G_INT_DBGCORE_QCH, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH, QCH_CON_SLH_AXI_SI_G_INT_CSSYS_QCH, QCH_CON_SLH_AXI_SI_G_INT_DBGCORE_QCH, QCH_CON_SYSREG_CPUCL0_QCH, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH, DMYQCH_CON_CPUCL1_QCH_BIG, DMYQCH_CON_CPUCL1_QCH_DDD_HC0, DMYQCH_CON_CPUCL1_QCH_DDD_HC1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH, QCH_CON_HTU_CPUCL1_QCH_PCLK, QCH_CON_HTU_CPUCL1_QCH_CLK, QCH_CON_CSIS_CMU_CSIS_QCH, QCH_CON_CSIS_PDP_QCH_VOTF0, QCH_CON_CSIS_PDP_QCH_DMA, QCH_CON_CSIS_PDP_QCH_PDP_TOP, QCH_CON_CSIS_PDP_QCH_MCB, QCH_CON_CSIS_PDP_QCH_VOTF1, QCH_CON_CSIS_PDP_QCH_C2_PDP, QCH_CON_D_TZPC_CSIS_QCH, QCH_CON_LH_AST_MI_SOTF0_TAACSIS_QCH, QCH_CON_LH_AST_MI_SOTF1_TAACSIS_QCH, QCH_CON_LH_AST_MI_SOTF2_TAACSIS_QCH, QCH_CON_LH_AST_MI_ZOTF0_TAACSIS_QCH, QCH_CON_LH_AST_MI_ZOTF1_TAACSIS_QCH, QCH_CON_LH_AST_MI_ZOTF2_TAACSIS_QCH, QCH_CON_LH_AST_SI_OTF0_CSISTAA_QCH, QCH_CON_LH_AST_SI_OTF1_CSISTAA_QCH, QCH_CON_LH_AST_SI_OTF2_CSISTAA_QCH, QCH_CON_LH_AXI_SI_D0_CSIS_QCH, QCH_CON_LH_AXI_SI_D1_CSIS_QCH, QCH_CON_LH_AXI_SI_D2_CSIS_QCH, QCH_CON_LH_AXI_SI_D3_CSIS_QCH, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5, QCH_CON_PPMU_CSIS_D0_QCH, QCH_CON_PPMU_CSIS_D1_QCH, QCH_CON_PPMU_CSIS_D2_QCH, QCH_CON_PPMU_CSIS_D3_QCH, QCH_CON_QE_CSIS_DMA0_QCH, QCH_CON_QE_CSIS_DMA1_QCH, QCH_CON_QE_CSIS_DMA2_QCH, QCH_CON_QE_CSIS_DMA3_QCH, QCH_CON_QE_PDP_AF0_QCH, QCH_CON_QE_PDP_AF1_QCH, QCH_CON_QE_PDP_AF2_QCH, QCH_CON_QE_PDP_STAT_IMG0_QCH, QCH_CON_QE_PDP_STAT_IMG1_QCH, QCH_CON_QE_PDP_STAT_IMG2_QCH, QCH_CON_QE_STRP0_QCH, QCH_CON_QE_STRP1_QCH, QCH_CON_QE_STRP2_QCH, QCH_CON_QE_ZSL0_QCH, QCH_CON_QE_ZSL1_QCH, QCH_CON_QE_ZSL2_QCH, QCH_CON_SLH_AXI_MI_P_CSIS_QCH, QCH_CON_SYSMMU_D0_CSIS_QCH_S1, QCH_CON_SYSMMU_D0_CSIS_QCH_S2, QCH_CON_SYSMMU_D1_CSIS_QCH_S1, QCH_CON_SYSMMU_D1_CSIS_QCH_S2, QCH_CON_SYSMMU_D2_CSIS_QCH_S1, QCH_CON_SYSMMU_D2_CSIS_QCH_S2, QCH_CON_SYSMMU_D3_CSIS_QCH_S2, QCH_CON_SYSMMU_D3_CSIS_QCH_S1, QCH_CON_SYSREG_CSIS_QCH, QCH_CON_VGEN_LITE0_CSIS_QCH, QCH_CON_VGEN_LITE1_CSIS_QCH, QCH_CON_VGEN_LITE2_CSIS_QCH, QCH_CON_DPU_QCH_DPU, QCH_CON_DPU_QCH_DPU_DMA, QCH_CON_DPU_QCH_DPU_DPP, QCH_CON_DPU_QCH_DPU_C2SERV, DMYQCH_CON_DPU_QCH, QCH_CON_DPU_CMU_DPU_QCH, QCH_CON_D_TZPC_DPU_QCH, QCH_CON_LH_AXI_SI_D0_DPU_QCH, QCH_CON_LH_AXI_SI_D1_DPU_QCH, QCH_CON_PPMU_D0_DPU_QCH, QCH_CON_PPMU_D1_DPU_QCH, QCH_CON_SLH_AXI_MI_P_DPU_QCH, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S1, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S2, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S1, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S2, QCH_CON_SYSREG_DPU_QCH, QCH_CON_CLUSTER0_QCH_SCLK, QCH_CON_CLUSTER0_QCH_ATCLK, QCH_CON_CLUSTER0_QCH_GIC, QCH_CON_CLUSTER0_QCH_DBG_PD, QCH_CON_CLUSTER0_QCH_PCLK, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK, QCH_CON_CLUSTER0_QCH_PDBGCLK, DMYQCH_CON_CMU_DSU_CMUREF_QCH, QCH_CON_CMU_DSU_SHORTSTOP_QCH, QCH_CON_DSU_CMU_DSU_QCH, QCH_CON_HTU_DSU_QCH_PCLK, QCH_CON_HTU_DSU_QCH_CLK, QCH_CON_LH_AST_SI_G_CPU_QCH, QCH_CON_LH_AXI_SI_D0_MIF_CPU_QCH, QCH_CON_LH_AXI_SI_D1_MIF_CPU_QCH, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH, QCH_CON_PPMU_CPUCL0_QCH, QCH_CON_PPMU_CPUCL1_QCH, QCH_CON_SLH_AXI_SI_P_CLUSTER0_QCH, QCH_CON_D_TZPC_G3D_QCH, QCH_CON_G3D_CMU_G3D_QCH, QCH_CON_GPU_QCH, QCH_CON_HTU_G3D_QCH_CLK, QCH_CON_HTU_G3D_QCH_PCLK, QCH_CON_LHM_AXI_P_INT_G3D_QCH, QCH_CON_LHS_AXI_P_INT_G3D_QCH, QCH_CON_LH_AXI_SI_D_G3D_QCH, QCH_CON_PPMU_D_G3D_QCH, QCH_CON_SLH_AXI_MI_P_G3D_QCH, QCH_CON_SYSMMU_D_G3D_QCH, QCH_CON_SYSREG_G3D_QCH, QCH_CON_VGEN_LITE_G3D_QCH, QCH_CON_GNSS_CMU_GNSS_QCH, QCH_CON_D_TZPC_HSI_QCH, QCH_CON_GPIO_HSI_QCH, QCH_CON_GPIO_HSI_UFS_QCH, QCH_CON_HSI_CMU_HSI_QCH, QCH_CON_PPMU_HSI_QCH, QCH_CON_S2MPU_D_HSI_QCH_S2, QCH_CON_SLH_AXI_MI_P_HSI_QCH, QCH_CON_SLH_AXI_SI_D_HSI_QCH, QCH_CON_SYSREG_HSI_QCH, QCH_CON_UFS_EMBD_QCH, QCH_CON_UFS_EMBD_QCH_FMP, QCH_CON_VGEN_LITE_HSI_QCH, QCH_CON_D_TZPC_ISP_QCH, QCH_CON_ISP_CMU_ISP_QCH, QCH_CON_ITP_DNS_QCH_S00, QCH_CON_ITP_DNS_QCH_S01, QCH_CON_LH_AST_MI_OTF0_TNRISP_QCH, QCH_CON_LH_AST_MI_OTF1_TNRISP_QCH, QCH_CON_LH_AST_MI_OTF_TAAISP_QCH, QCH_CON_LH_AST_SI_OTF_ISPMCSC_QCH, QCH_CON_LH_AXI_SI_D_ISP_QCH, QCH_CON_PPMU_ISP_QCH, QCH_CON_SLH_AXI_MI_P_ISP_QCH, QCH_CON_SYSMMU_D_ISP_QCH_S1, QCH_CON_SYSMMU_D_ISP_QCH_S2, QCH_CON_SYSREG_ISP_QCH, QCH_CON_VGEN_LITE_ISP_QCH, QCH_CON_D_TZPC_M2M_QCH, QCH_CON_JPEG0_QCH, QCH_CON_LH_AXI_SI_D_M2M_QCH, QCH_CON_M2M_QCH_S2, QCH_CON_M2M_QCH_S1, QCH_CON_M2M_CMU_M2M_QCH, QCH_CON_PPMU_D_M2M_QCH, QCH_CON_SLH_AXI_MI_P_M2M_QCH, QCH_CON_SYSMMU_D_M2M_QCH_S1, QCH_CON_SYSMMU_D_M2M_QCH_S2, QCH_CON_SYSREG_M2M_QCH, QCH_CON_VGEN_LITE_M2M_QCH, QCH_CON_D_TZPC_MCSC_QCH, QCH_CON_GDC_QCH, QCH_CON_LH_AST_MI_OTF_ISPMCSC_QCH, QCH_CON_LH_AXI_MI_D0_CSIS_QCH, QCH_CON_LH_AXI_MI_D0_TNR_QCH, QCH_CON_LH_AXI_MI_D1_CSIS_QCH, QCH_CON_LH_AXI_MI_D1_TNR_QCH, QCH_CON_LH_AXI_MI_D2_CSIS_QCH, QCH_CON_LH_AXI_MI_D3_CSIS_QCH, QCH_CON_LH_AXI_MI_D_ISP_QCH, QCH_CON_LH_AXI_MI_D_TAA_QCH, QCH_CON_MCSC_QCH, QCH_CON_MCSC_CMU_MCSC_QCH, QCH_CON_ORBMCH_QCH_ACLK, QCH_CON_ORBMCH_QCH_C2CLK, QCH_CON_PPMU_GDC_QCH, QCH_CON_PPMU_MCSC_QCH, QCH_CON_SLH_AXI_MI_P_MCSC_QCH, QCH_CON_SYSMMU_D0_MCSC_QCH_S1, QCH_CON_SYSMMU_D0_MCSC_QCH_S2, QCH_CON_SYSMMU_D1_MCSC_QCH_S1, QCH_CON_SYSMMU_D1_MCSC_QCH_S2, QCH_CON_SYSREG_MCSC_QCH, QCH_CON_TREX_D_CAM_QCH, QCH_CON_VGEN_LITE_GDC_QCH, QCH_CON_VGEN_LITE_MCSC_QCH, QCH_CON_D_TZPC_MFC_QCH, QCH_CON_LH_AXI_SI_D_MFC_QCH, QCH_CON_MFC_QCH, QCH_CON_MFC_CMU_MFC_QCH, QCH_CON_PPMU_MFC_QCH, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH, QCH_CON_SLH_AXI_MI_P_MFC_QCH, QCH_CON_SYSMMU_MFC_QCH_S1, QCH_CON_SYSMMU_MFC_QCH_S2, QCH_CON_SYSREG_MFC_QCH, QCH_CON_VGEN_LITE_MFC_QCH, DMYQCH_CON_CMU_MIF_CMUREF_QCH, QCH_CON_DMC_QCH, QCH_CON_D_TZPC_MIF_QCH, QCH_CON_LH_AXI_MI_D_MIF_CP_QCH, QCH_CON_LH_AXI_MI_D_MIF_CPU_QCH, QCH_CON_LH_AXI_MI_D_MIF_NRT_QCH, QCH_CON_LH_AXI_MI_D_MIF_RT_QCH, QCH_CON_MIF_CMU_MIF_QCH, QCH_CON_PPMU_DMC_CPU_QCH, QCH_CON_QE_DMC_CPU_QCH, QCH_CON_SFRAPB_BRIDGE_DDRPHY_QCH, QCH_CON_SFRAPB_BRIDGE_DMC_QCH, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH, QCH_CON_SLH_AXI_MI_P_MIF_QCH, QCH_CON_SYSREG_MIF_QCH, QCH_CON_MODEM_CMU_MODEM_QCH, QCH_CON_D_TZPC_NPU0_QCH, QCH_CON_IP_NPUCORE_QCH_ACLK, QCH_CON_IP_NPUCORE_QCH_PCLK, QCH_CON_LH_AXI_MI_D0_NPU0_QCH, QCH_CON_LH_AXI_MI_D1_NPU0_QCH, QCH_CON_LH_AXI_MI_D_CTRL_NPU0_QCH, QCH_CON_LH_AXI_SI_D_CMDQ_NPU0_QCH, QCH_CON_LH_AXI_SI_D_RQ_NPU0_QCH, QCH_CON_NPU0_CMU_NPU0_QCH, QCH_CON_SLH_AXI_MI_P_NPU0_QCH, QCH_CON_SYSREG_NPU0_QCH, DMYQCH_CON_ADM_DAP_NPUS_QCH, QCH_CON_D_TZPC_NPUS_QCH, QCH_CON_HTU_NPUS_QCH_PCLK, QCH_CON_HTU_NPUS_QCH_CLK, QCH_CON_IP_NPUS_QCH, QCH_CON_IP_NPUS_QCH_C2A0CLK, QCH_CON_IP_NPUS_QCH_C2A1CLK, QCH_CON_IP_NPUS_QCH_CPU, QCH_CON_IP_NPUS_QCH_NEON, QCH_CON_LH_AXI_MI_D_CMDQ_NPU0_QCH, QCH_CON_LH_AXI_MI_D_RQ_NPU0_QCH, QCH_CON_LH_AXI_SI_D0_NPU0_QCH, QCH_CON_LH_AXI_SI_D0_NPUS_QCH, QCH_CON_LH_AXI_SI_D1_NPU0_QCH, QCH_CON_LH_AXI_SI_D1_NPUS_QCH, QCH_CON_LH_AXI_SI_D_CTRL_NPU0_QCH, QCH_CON_NPUS_CMU_NPUS_QCH, QCH_CON_PPMU_NPUS_0_QCH, QCH_CON_PPMU_NPUS_1_QCH, QCH_CON_SLH_AXI_MI_P_INT_NPUS_QCH, QCH_CON_SLH_AXI_MI_P_NPUS_QCH, QCH_CON_SLH_AXI_SI_P_INT_NPUS_QCH, QCH_CON_SYSMMU_D0_NPUS_QCH_S1, QCH_CON_SYSMMU_D0_NPUS_QCH_S2, QCH_CON_SYSMMU_D1_NPUS_QCH_S1, QCH_CON_SYSMMU_D1_NPUS_QCH_S2, QCH_CON_SYSREG_NPUS_QCH, QCH_CON_VGEN_LITE_NPUS_QCH, QCH_CON_D_TZPC_PERI_QCH, QCH_CON_GPIO_PERI_QCH, QCH_CON_GPIO_PERIMMC_QCH_GPIO, QCH_CON_MCT_QCH, QCH_CON_MMC_CARD_QCH, QCH_CON_OTP_CON_TOP_QCH, QCH_CON_PERI_CMU_PERI_QCH, QCH_CON_PPMU_PERI_QCH, QCH_CON_PWM_QCH, QCH_CON_S2MPU_D_PERI_QCH, QCH_CON_SLH_AXI_MI_P_PERI_QCH, QCH_CON_SLH_AXI_SI_D_PERI_QCH, QCH_CON_SYSREG_PERI_QCH, QCH_CON_TMU_QCH, QCH_CON_UART_DBG_QCH, QCH_CON_USI00_I2C_QCH, QCH_CON_USI00_USI_QCH, QCH_CON_USI01_I2C_QCH, QCH_CON_USI01_USI_QCH, QCH_CON_USI02_I2C_QCH, QCH_CON_USI02_USI_QCH, QCH_CON_USI03_I2C_QCH, QCH_CON_USI03_USI_QCH, QCH_CON_USI04_I2C_QCH, QCH_CON_USI04_USI_QCH, QCH_CON_USI05_I2C_QCH, QCH_CON_USI05_USI_QCH, QCH_CON_USI06_I2C_QCH, QCH_CON_USI06_USI_QCH, QCH_CON_USI07_I2C_QCH, QCH_CON_VGEN_LITE_PERI_QCH, QCH_CON_WDT0_QCH, QCH_CON_WDT1_QCH, QCH_CON_S2D_CMU_S2D_QCH, QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH, QCH_CON_D_TZPC_TAA_QCH, QCH_CON_LH_AST_MI_OTF0_CSISTAA_QCH, QCH_CON_LH_AST_MI_OTF1_CSISTAA_QCH, QCH_CON_LH_AST_MI_OTF2_CSISTAA_QCH, QCH_CON_LH_AST_SI_OTF_TAAISP_QCH, QCH_CON_LH_AST_SI_SOTF0_TAACSIS_QCH, QCH_CON_LH_AST_SI_SOTF1_TAACSIS_QCH, QCH_CON_LH_AST_SI_SOTF2_TAACSIS_QCH, QCH_CON_LH_AST_SI_ZOTF0_TAACSIS_QCH, QCH_CON_LH_AST_SI_ZOTF1_TAACSIS_QCH, QCH_CON_LH_AST_SI_ZOTF2_TAACSIS_QCH, QCH_CON_LH_AXI_SI_D_TAA_QCH, QCH_CON_PPMU_TAA_QCH, QCH_CON_SIPU_TAA_QCH, QCH_CON_SIPU_TAA_QCH_C2_STAT, QCH_CON_SIPU_TAA_QCH_C2_YDS, QCH_CON_SLH_AXI_MI_P_TAA_QCH, QCH_CON_SYSMMU_TAA_QCH_S1, QCH_CON_SYSMMU_TAA_QCH_S2, QCH_CON_SYSREG_TAA_QCH, QCH_CON_TAA_CMU_TAA_QCH, QCH_CON_VGEN_LITE0_TAA_QCH, QCH_CON_VGEN_LITE1_TAA_QCH, QCH_CON_D_TZPC_TNR_QCH, QCH_CON_LH_AST_SI_OTF0_TNRISP_QCH, QCH_CON_LH_AST_SI_OTF1_TNRISP_QCH, QCH_CON_LH_AXI_SI_D0_TNR_QCH, QCH_CON_LH_AXI_SI_D1_TNR_QCH, QCH_CON_PPMU_D0_TNR_QCH, QCH_CON_PPMU_D1_TNR_QCH, QCH_CON_SLH_AXI_MI_P_TNR_QCH, QCH_CON_SYSMMU_D0_TNR_QCH_S1, QCH_CON_SYSMMU_D0_TNR_QCH_S2, QCH_CON_SYSMMU_D1_TNR_QCH_S1, QCH_CON_SYSMMU_D1_TNR_QCH_S2, QCH_CON_SYSREG_TNR_QCH, QCH_CON_TNR_QCH_MCFP0, QCH_CON_TNR_QCH_MCFP1, QCH_CON_TNR_CMU_TNR_QCH, QCH_CON_VGEN_LITE_D_TNR_QCH, QCH_CON_D_TZPC_USB_QCH, QCH_CON_PPMU_USB_QCH, QCH_CON_S2MPU_D_USB_QCH, QCH_CON_SLH_AXI_MI_P_USB_QCH, QCH_CON_SLH_AXI_SI_D_USB_QCH, QCH_CON_SLH_AXI_SI_D_USBAUD_QCH, QCH_CON_SYSREG_USB_QCH, QCH_CON_USB20DRD_TOP_QCH_SLV_CTRL, QCH_CON_USB20DRD_TOP_QCH_SLV_LINK, QCH_CON_USB_CMU_USB_QCH, QCH_CON_VGEN_LITE_USB_QCH, QCH_CON_CM4_VTS_QCH_CPU, QCH_CON_DMIC_AHB0_QCH_PCLK, QCH_CON_DMIC_AHB2_QCH_PCLK, QCH_CON_DMIC_AUD0_QCH_PCLK, DMYQCH_CON_DMIC_AUD0_QCH_DMIC, QCH_CON_DMIC_AUD1_QCH_PCLK, DMYQCH_CON_DMIC_AUD1_QCH_DMIC, QCH_CON_DMIC_IF0_QCH_PCLK, DMYQCH_CON_DMIC_IF0_QCH_DMIC, QCH_CON_DMIC_IF1_QCH_PCLK, DMYQCH_CON_DMIC_IF1_QCH_DMIC, QCH_CON_GPIO_VTS_QCH, QCH_CON_HWACG_SYS_DMIC0_QCH, QCH_CON_HWACG_SYS_DMIC2_QCH, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH, QCH_CON_MAILBOX_ABOX_VTS_QCH, QCH_CON_MAILBOX_AP_VTS_QCH, QCH_CON_SERIAL_LIF_AUD_QCH_PCLK, DMYQCH_CON_SERIAL_LIF_AUD_QCH_AHB, DMYQCH_CON_SERIAL_LIF_AUD_QCH_LIF, QCH_CON_SLH_AXI_MI_S_VTS_QCH, QCH_CON_SLH_AXI_SI_M_VTS_QCH, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1, QCH_CON_SYSREG_VTS_QCH, QCH_CON_TIMER_VTS_QCH, QCH_CON_VTS_CMU_VTS_QCH, QCH_CON_WDT_VTS_QCH, ALIVE_CMU_ALIVE_CONTROLLER_OPTION, AUD_CMU_AUD_CONTROLLER_OPTION, BUSC_CMU_BUSC_CONTROLLER_OPTION, CHUB_CMU_CHUB_CONTROLLER_OPTION, CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION, CMGP_CMU_CMGP_CONTROLLER_OPTION, CMU_CMU_TOP_CONTROLLER_OPTION, CORE_CMU_CORE_CONTROLLER_OPTION, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION, CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION, CSIS_CMU_CSIS_CONTROLLER_OPTION, DPU_CMU_DPU_CONTROLLER_OPTION, DSU_CMU_DSU_CONTROLLER_OPTION, G3D_CMU_G3D_CONTROLLER_OPTION, GNSS_CMU_GNSS_CONTROLLER_OPTION, HSI_CMU_HSI_CONTROLLER_OPTION, ISP_CMU_ISP_CONTROLLER_OPTION, M2M_CMU_M2M_CONTROLLER_OPTION, MCSC_CMU_MCSC_CONTROLLER_OPTION, MFC_CMU_MFC_CONTROLLER_OPTION, MIF_CMU_MIF_CONTROLLER_OPTION, MODEM_CMU_MODEM_CONTROLLER_OPTION, NPU0_CMU_NPU0_CONTROLLER_OPTION, NPUS_CMU_NPUS_CONTROLLER_OPTION, PERI_CMU_PERI_CONTROLLER_OPTION, S2D_CMU_S2D_CONTROLLER_OPTION, TAA_CMU_TAA_CONTROLLER_OPTION, TNR_CMU_TNR_CONTROLLER_OPTION, USB_CMU_USB_CONTROLLER_OPTION, VTS_CMU_VTS_CONTROLLER_OPTION, end_of_sfr, num_of_sfr = end_of_sfr - SFR_TYPE, }; enum sfr_access_id { PLL_LOCKTIME_PLL_AUD_PLL_LOCK_TIME = SFR_ACCESS_TYPE, PLL_CON3_PLL_AUD_ENABLE, PLL_CON3_PLL_AUD_STABLE, PLL_CON3_PLL_AUD_DIV_P, PLL_CON3_PLL_AUD_DIV_M, PLL_CON3_PLL_AUD_DIV_S, PLL_CON9_PLL_AUD_K, PLL_CON8_PLL_AUD_F, PLL_CON4_PLL_AUD_SSCGEN, PLL_CON5_PLL_AUD_MFR, PLL_CON5_PLL_AUD_MRR, PLL_CON5_PLL_AUD_SEL_PF, PLL_CON4_PLL_AUD_LOCK_CON_IN, PLL_CON4_PLL_AUD_LOCK_CON_OUT, PLL_CON4_PLL_AUD_LOCK_CON_DLY, PLL_CON4_PLL_AUD_AFC_ENB, DBG_NFO_PLL_AUD_AFC_CODE, PLL_CON4_PLL_AUD_BYPASS, PLL_CON0_PLL_AUD_MUX_SEL, PLL_CON0_PLL_AUD_MUX_BUSY, PLL_LOCKTIME_PLL_AUD_RESET_REQ_TIME, PLL_CON1_PLL_AUD_IGNORE_REQ_SYSCLK, PLL_CON4_PLL_AUD_DISABLE_ALL_CLOCK_STOP, PLL_CON4_PLL_AUD_DISABLE_SDIV_CLOCK_STOP, PLL_CON3_PLL_AUD_USE_HW_LOCK_DET, PLL_CON3_PLL_AUD_LOCK_FAIL, PLL_CON3_PLL_AUD_USE_LOCK_FAIL, PLL_CON1_PLL_AUD_ENABLE_AUTOMATIC_BYPASS, PLL_CON1_PLL_AUD_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_PLL_AUD_MANUAL_PLL_CTRL, PLL_CON1_PLL_AUD_AUTO_PLL_CTRL, DBG_NFO_PLL_AUD_DEBUG_INFO, PLL_CON2_PLL_AUD_ENABLE_FILTER_AUTOMATIC_CLKGATING, PLL_CON2_PLL_AUD_FILTER_CNT_EXPIRE_VALUE, PLL_CON1_PLL_AUD_OVERRIDE_BY_HCH, PLL_CON3_PLL_AUD_LOCK_EN, PLL_CON6_PLL_AUD_RESETB_REG, PLL_CON6_PLL_AUD_STABLE_REG, PLL_LOCKTIME_REG_PLL_AUD_PLL_LOCK_TIME_REG, PLL_CON4_PLL_AUD_AFCINIT_SEL, PLL_CON4_PLL_AUD_MASK_SEL, PLL_CON6_PLL_AUD_LDO_SEL, PLL_CON6_PLL_AUD_LDO_CON, PLL_CON7_PLL_AUD_REV, PLL_CON7_PLL_AUD_R_CON, PLL_CON7_PLL_AUD_C_CON, PLL_CON7_PLL_AUD_ICP, PLL_CON7_PLL_AUD_EXT_AFC, PLL_CON7_PLL_AUD_EN_FOUT, PLL_CON7_PLL_AUD_EN_FOUT2, PLL_CON7_PLL_AUD_EN_FOUT3, PLL_CON7_PLL_AUD_EN_FOUT4, PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED1_ENABLE, PLL_CON3_PLL_SHARED1_STABLE, PLL_CON3_PLL_SHARED1_DIV_P, PLL_CON3_PLL_SHARED1_DIV_M, PLL_CON3_PLL_SHARED1_DIV_S, PLL_CON9_PLL_SHARED1_K, PLL_CON8_PLL_SHARED1_F, PLL_CON4_PLL_SHARED1_SSCGEN, PLL_CON5_PLL_SHARED1_MFR, PLL_CON5_PLL_SHARED1_MRR, PLL_CON5_PLL_SHARED1_SEL_PF, PLL_CON4_PLL_SHARED1_LOCK_CON_IN, PLL_CON4_PLL_SHARED1_LOCK_CON_OUT, PLL_CON4_PLL_SHARED1_LOCK_CON_DLY, PLL_CON4_PLL_SHARED1_AFC_ENB, DBG_NFO_PLL_SHARED1_AFC_CODE, PLL_CON4_PLL_SHARED1_BYPASS, PLL_CON0_PLL_SHARED1_MUX_SEL, PLL_CON0_PLL_SHARED1_MUX_BUSY, PLL_LOCKTIME_PLL_SHARED1_RESET_REQ_TIME, PLL_CON1_PLL_SHARED1_IGNORE_REQ_SYSCLK, PLL_CON4_PLL_SHARED1_DISABLE_ALL_CLOCK_STOP, PLL_CON4_PLL_SHARED1_DISABLE_SDIV_CLOCK_STOP, PLL_CON3_PLL_SHARED1_USE_HW_LOCK_DET, PLL_CON3_PLL_SHARED1_LOCK_FAIL, PLL_CON3_PLL_SHARED1_USE_LOCK_FAIL, PLL_CON1_PLL_SHARED1_ENABLE_AUTOMATIC_BYPASS, PLL_CON1_PLL_SHARED1_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_PLL_SHARED1_MANUAL_PLL_CTRL, PLL_CON1_PLL_SHARED1_AUTO_PLL_CTRL, DBG_NFO_PLL_SHARED1_DEBUG_INFO, PLL_CON2_PLL_SHARED1_ENABLE_FILTER_AUTOMATIC_CLKGATING, PLL_CON2_PLL_SHARED1_FILTER_CNT_EXPIRE_VALUE, PLL_CON1_PLL_SHARED1_OVERRIDE_BY_HCH, PLL_CON3_PLL_SHARED1_LOCK_EN, PLL_CON6_PLL_SHARED1_RESETB_REG, PLL_CON6_PLL_SHARED1_STABLE_REG, PLL_LOCKTIME_REG_PLL_SHARED1_PLL_LOCK_TIME_REG, PLL_CON4_PLL_SHARED1_AFCINIT_SEL, PLL_CON4_PLL_SHARED1_MASK_SEL, PLL_CON6_PLL_SHARED1_LDO_SEL, PLL_CON6_PLL_SHARED1_LDO_CON, PLL_CON7_PLL_SHARED1_REV, PLL_CON7_PLL_SHARED1_R_CON, PLL_CON7_PLL_SHARED1_C_CON, PLL_CON7_PLL_SHARED1_ICP, PLL_CON7_PLL_SHARED1_EXT_AFC, PLL_CON7_PLL_SHARED1_EN_FOUT, PLL_CON7_PLL_SHARED1_EN_FOUT2, PLL_CON7_PLL_SHARED1_EN_FOUT3, PLL_CON7_PLL_SHARED1_EN_FOUT4, PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED0_ENABLE, PLL_CON3_PLL_SHARED0_STABLE, PLL_CON3_PLL_SHARED0_DIV_P, PLL_CON3_PLL_SHARED0_DIV_M, PLL_CON3_PLL_SHARED0_DIV_S, PLL_CON9_PLL_SHARED0_K, PLL_CON8_PLL_SHARED0_F, PLL_CON4_PLL_SHARED0_SSCGEN, PLL_CON5_PLL_SHARED0_MFR, PLL_CON5_PLL_SHARED0_MRR, PLL_CON5_PLL_SHARED0_SEL_PF, PLL_CON1_PLL_SHARED0_LOCK_CON_IN, PLL_CON4_PLL_SHARED0_LOCK_CON_OUT, PLL_CON4_PLL_SHARED0_LOCK_CON_DLY, PLL_CON4_PLL_SHARED0_AFC_ENB, DBG_NFO_PLL_SHARED0_AFC_CODE, PLL_CON4_PLL_SHARED0_BYPASS, PLL_CON0_PLL_SHARED0_MUX_SEL, PLL_CON0_PLL_SHARED0_MUX_BUSY, PLL_LOCKTIME_PLL_SHARED0_RESET_REQ_TIME, PLL_CON1_PLL_SHARED0_IGNORE_REQ_SYSCLK, PLL_CON4_PLL_SHARED0_DISABLE_ALL_CLOCK_STOP, PLL_CON4_PLL_SHARED0_DISABLE_SDIV_CLOCK_STOP, PLL_CON3_PLL_SHARED0_USE_HW_LOCK_DET, PLL_CON3_PLL_SHARED0_LOCK_FAIL, PLL_CON3_PLL_SHARED0_USE_LOCK_FAIL, PLL_CON1_PLL_SHARED0_ENABLE_AUTOMATIC_BYPASS, PLL_CON1_PLL_SHARED0_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_PLL_SHARED0_MANUAL_PLL_CTRL, PLL_CON1_PLL_SHARED0_AUTO_PLL_CTRL, DBG_NFO_PLL_SHARED0_DEBUG_INFO, PLL_CON2_PLL_SHARED0_ENABLE_FILTER_AUTOMATIC_CLKGATING, PLL_CON2_PLL_SHARED0_FILTER_CNT_EXPIRE_VALUE, PLL_CON1_PLL_SHARED0_OVERRIDE_BY_HCH, PLL_CON3_PLL_SHARED0_LOCK_EN, PLL_CON6_PLL_SHARED0_RESETB_REG, PLL_CON6_PLL_SHARED0_STABLE_REG, PLL_LOCKTIME_REG_PLL_SHARED0_PLL_LOCK_TIME_REG, PLL_CON4_PLL_SHARED0_AFCINIT_SEL, PLL_CON4_PLL_SHARED0_MASK_SEL, PLL_CON6_PLL_SHARED0_LDO_SEL, PLL_CON6_PLL_SHARED0_LDO_CON, PLL_CON7_PLL_SHARED0_REV, PLL_CON7_PLL_SHARED0_R_CON, PLL_CON7_PLL_SHARED0_C_CON, PLL_CON7_PLL_SHARED0_ICP, PLL_CON7_PLL_SHARED0_EXT_AFC, PLL_CON7_PLL_SHARED0_EN_FOUT, PLL_CON7_PLL_SHARED0_EN_FOUT2, PLL_CON7_PLL_SHARED0_EN_FOUT3, PLL_CON7_PLL_SHARED0_EN_FOUT4, PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, PLL_CON3_PLL_G3D_ENABLE, PLL_CON3_PLL_G3D_STABLE, PLL_CON3_PLL_G3D_DIV_P, PLL_CON3_PLL_G3D_DIV_M, PLL_CON3_PLL_G3D_DIV_S, PLL_CON9_PLL_G3D_K, PLL_CON8_PLL_G3D_F, PLL_CON4_PLL_G3D_SSCGEN, PLL_CON5_PLL_G3D_MFR, PLL_CON5_PLL_G3D_MRR, PLL_CON5_PLL_G3D_SEL_PF, PLL_CON4_PLL_G3D_LOCK_CON_IN, PLL_CON4_PLL_G3D_LOCK_CON_OUT, PLL_CON4_PLL_G3D_LOCK_CON_DLY, PLL_CON4_PLL_G3D_AFC_ENB, DBG_NFO_PLL_G3D_AFC_CODE, PLL_CON4_PLL_G3D_BYPASS, PLL_CON0_PLL_G3D_MUX_SEL, PLL_CON0_PLL_G3D_MUX_BUSY, PLL_LOCKTIME_PLL_G3D_RESET_REQ_TIME, PLL_CON1_PLL_G3D_IGNORE_REQ_SYSCLK, PLL_CON4_PLL_G3D_DISABLE_ALL_CLOCK_STOP, PLL_CON4_PLL_G3D_DISABLE_SDIV_CLOCK_STOP, PLL_CON3_PLL_G3D_USE_HW_LOCK_DET, PLL_CON3_PLL_G3D_LOCK_FAIL, PLL_CON3_PLL_G3D_USE_LOCK_FAIL, PLL_CON1_PLL_G3D_ENABLE_AUTOMATIC_BYPASS, PLL_CON1_PLL_G3D_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_PLL_G3D_MANUAL_PLL_CTRL, PLL_CON1_PLL_G3D_AUTO_PLL_CTRL, DBG_NFO_PLL_G3D_DEBUG_INFO, PLL_CON2_PLL_G3D_ENABLE_FILTER_AUTOMATIC_CLKGATING, PLL_CON2_PLL_G3D_FILTER_CNT_EXPIRE_VALUE, PLL_CON1_PLL_G3D_OVERRIDE_BY_HCH, PLL_CON3_PLL_G3D_LOCK_EN, PLL_CON6_PLL_G3D_RESETB_REG, PLL_CON6_PLL_G3D_STABLE_REG, PLL_LOCKTIME_REG_PLL_G3D_PLL_LOCK_TIME_REG, PLL_CON4_PLL_G3D_AFCINIT_SEL, PLL_CON4_PLL_G3D_MASK_SEL, PLL_CON6_PLL_G3D_LDO_SEL, PLL_CON6_PLL_G3D_LDO_CON, PLL_CON7_PLL_G3D_REV, PLL_CON7_PLL_G3D_R_CON, PLL_CON7_PLL_G3D_C_CON, PLL_CON7_PLL_G3D_ICP, PLL_CON7_PLL_G3D_EXT_AFC, PLL_CON7_PLL_G3D_EN_FOUT, PLL_CON7_PLL_G3D_EN_FOUT2, PLL_CON7_PLL_G3D_EN_FOUT3, PLL_CON7_PLL_G3D_EN_FOUT4, PLL_LOCKTIME_PLL_MMC_PLL_LOCK_TIME, PLL_CON3_PLL_MMC_ENABLE, PLL_CON3_PLL_MMC_STABLE, PLL_CON3_PLL_MMC_DIV_P, PLL_CON3_PLL_MMC_DIV_M, PLL_CON3_PLL_MMC_DIV_S, PLL_CON9_PLL_MMC_K, PLL_CON8_PLL_MMC_F, PLL_CON4_PLL_MMC_SSCGEN, PLL_CON5_PLL_MMC_MFR, PLL_CON5_PLL_MMC_MRR, PLL_CON5_PLL_MMC_SEL_PF, PLL_CON4_PLL_MMC_LOCK_CON_IN, PLL_CON4_PLL_MMC_LOCK_CON_OUT, PLL_CON4_PLL_MMC_LOCK_CON_DLY, PLL_CON4_PLL_MMC_AFC_ENB, DBG_NFO_PLL_MMC_AFC_CODE, PLL_CON4_PLL_MMC_BYPASS, PLL_CON0_PLL_MMC_MUX_SEL, PLL_CON0_PLL_MMC_MUX_BUSY, PLL_LOCKTIME_PLL_MMC_RESET_REQ_TIME, PLL_CON1_PLL_MMC_IGNORE_REQ_SYSCLK, PLL_CON4_PLL_MMC_DISABLE_ALL_CLOCK_STOP, PLL_CON4_PLL_MMC_DISABLE_SDIV_CLOCK_STOP, PLL_CON3_PLL_MMC_USE_HW_LOCK_DET, PLL_CON3_PLL_MMC_LOCK_FAIL, PLL_CON3_PLL_MMC_USE_LOCK_FAIL, PLL_CON1_PLL_MMC_ENABLE_AUTOMATIC_BYPASS, PLL_CON1_PLL_MMC_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_PLL_MMC_MANUAL_PLL_CTRL, PLL_CON1_PLL_MMC_AUTO_PLL_CTRL, DBG_NFO_PLL_MMC_DEBUG_INFO, PLL_CON2_PLL_MMC_ENABLE_FILTER_AUTOMATIC_CLKGATING, PLL_CON2_PLL_MMC_FILTER_CNT_EXPIRE_VALUE, PLL_CON1_PLL_MMC_OVERRIDE_BY_HCH, PLL_CON3_PLL_MMC_LOCK_EN, PLL_CON6_PLL_MMC_RESETB_REG, PLL_CON6_PLL_MMC_STABLE_REG, PLL_LOCKTIME_REG_PLL_MMC_PLL_LOCK_TIME_REG, PLL_CON4_PLL_MMC_AFCINIT_SEL, PLL_CON4_PLL_MMC_MASK_SEL, PLL_CON6_PLL_MMC_LDO_SEL, PLL_CON6_PLL_MMC_LDO_CON, PLL_CON7_PLL_MMC_REV, PLL_CON7_PLL_MMC_R_CON, PLL_CON7_PLL_MMC_C_CON, PLL_CON7_PLL_MMC_ICP, PLL_CON7_PLL_MMC_EXT_AFC, PLL_CON7_PLL_MMC_EN_FOUT, PLL_CON7_PLL_MMC_EN_FOUT2, PLL_CON7_PLL_MMC_EN_FOUT3, PLL_CON7_PLL_MMC_EN_FOUT4, PLL_LOCKTIME_PLL_SHARED2_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED2_ENABLE, PLL_CON3_PLL_SHARED2_STABLE, PLL_CON3_PLL_SHARED2_DIV_P, PLL_CON3_PLL_SHARED2_DIV_M, PLL_CON3_PLL_SHARED2_DIV_S, PLL_CON9_PLL_SHARED2_K, PLL_CON8_PLL_SHARED2_F, PLL_CON4_PLL_SHARED2_SSCGEN, PLL_CON5_PLL_SHARED2_MFR, PLL_CON5_PLL_SHARED2_MRR, PLL_CON5_PLL_SHARED2_SEL_PF, PLL_CON4_PLL_SHARED2_LOCK_CON_IN, PLL_CON4_PLL_SHARED2_LOCK_CON_OUT, PLL_CON4_PLL_SHARED2_LOCK_CON_DLY, PLL_CON4_PLL_SHARED2_AFC_ENB, DBG_NFO_PLL_SHARED2_AFC_CODE, PLL_CON4_PLL_SHARED2_BYPASS, PLL_CON0_PLL_SHARED2_MUX_SEL, PLL_CON0_PLL_SHARED2_MUX_BUSY, PLL_LOCKTIME_PLL_SHARED2_RESET_REQ_TIME, PLL_CON1_PLL_SHARED2_IGNORE_REQ_SYSCLK, PLL_CON4_PLL_SHARED2_DISABLE_ALL_CLOCK_STOP, PLL_CON4_PLL_SHARED2_DISABLE_SDIV_CLOCK_STOP, PLL_CON3_PLL_SHARED2_USE_HW_LOCK_DET, PLL_CON3_PLL_SHARED2_LOCK_FAIL, PLL_CON3_PLL_SHARED2_USE_LOCK_FAIL, PLL_CON1_PLL_SHARED2_ENABLE_AUTOMATIC_BYPASS, PLL_CON1_PLL_SHARED2_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_PLL_SHARED2_MANUAL_PLL_CTRL, PLL_CON1_PLL_SHARED2_AUTO_PLL_CTRL, DBG_NFO_PLL_SHARED2_DEBUG_INFO, PLL_CON2_PLL_SHARED2_ENABLE_FILTER_AUTOMATIC_CLKGATING, PLL_CON2_PLL_SHARED2_FILTER_CNT_EXPIRE_VALUE, PLL_CON1_PLL_SHARED2_OVERRIDE_BY_HCH, PLL_CON3_PLL_SHARED2_LOCK_EN, PLL_CON6_PLL_SHARED2_RESETB_REG, PLL_CON6_PLL_SHARED2_STABLE_REG, PLL_LOCKTIME_REG_PLL_SHARED2_PLL_LOCK_TIME_REG, PLL_CON4_PLL_SHARED2_AFCINIT_SEL, PLL_CON4_PLL_SHARED2_MASK_SEL, PLL_CON6_PLL_SHARED2_LDO_SEL, PLL_CON6_PLL_SHARED2_LDO_CON, PLL_CON7_PLL_SHARED2_REV, PLL_CON7_PLL_SHARED2_R_CON, PLL_CON7_PLL_SHARED2_C_CON, PLL_CON7_PLL_SHARED2_ICP, PLL_CON7_PLL_SHARED2_EXT_AFC, PLL_CON7_PLL_SHARED2_EN_FOUT, PLL_CON7_PLL_SHARED2_EN_FOUT2, PLL_CON7_PLL_SHARED2_EN_FOUT3, PLL_CON7_PLL_SHARED2_EN_FOUT4, PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, PLL_CON3_PLL_CPUCL0_ENABLE, PLL_CON3_PLL_CPUCL0_STABLE, PLL_CON3_PLL_CPUCL0_DIV_P, PLL_CON3_PLL_CPUCL0_DIV_M, PLL_CON3_PLL_CPUCL0_DIV_S, PLL_CON9_PLL_CPUCL0_K, PLL_CON8_PLL_CPUCL0_F, PLL_CON4_PLL_CPUCL0_SSCGEN, PLL_CON5_PLL_CPUCL0_MFR, PLL_CON5_PLL_CPUCL0_MRR, PLL_CON5_PLL_CPUCL0_SEL_PF, PLL_CON4_PLL_CPUCL0_LOCK_CON_IN, PLL_CON4_PLL_CPUCL0_LOCK_CON_OUT, PLL_CON4_PLL_CPUCL0_LOCK_CON_DLY, PLL_CON4_PLL_CPUCL0_AFC_ENB, DBG_NFO_PLL_CPUCL0_AFC_CODE, PLL_CON4_PLL_CPUCL0_BYPASS, PLL_CON0_PLL_CPUCL0_MUX_SEL, PLL_CON0_PLL_CPUCL0_MUX_BUSY, PLL_LOCKTIME_PLL_CPUCL0_RESET_REQ_TIME, PLL_CON1_PLL_CPUCL0_IGNORE_REQ_SYSCLK, PLL_CON4_PLL_CPUCL0_DISABLE_ALL_CLOCK_STOP, PLL_CON4_PLL_CPUCL0_DISABLE_SDIV_CLOCK_STOP, PLL_CON3_PLL_CPUCL0_USE_HW_LOCK_DET, PLL_CON3_PLL_CPUCL0_LOCK_FAIL, PLL_CON3_PLL_CPUCL0_USE_LOCK_FAIL, PLL_CON1_PLL_CPUCL0_ENABLE_AUTOMATIC_BYPASS, PLL_CON1_PLL_CPUCL0_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_PLL_CPUCL0_MANUAL_PLL_CTRL, PLL_CON1_PLL_CPUCL0_AUTO_PLL_CTRL, DBG_NFO_PLL_CPUCL0_DEBUG_INFO, PLL_CON2_PLL_CPUCL0_ENABLE_FILTER_AUTOMATIC_CLKGATING, PLL_CON2_PLL_CPUCL0_FILTER_CNT_EXPIRE_VALUE, PLL_CON1_PLL_CPUCL0_OVERRIDE_BY_HCH, PLL_CON3_PLL_CPUCL0_LOCK_EN, PLL_CON6_PLL_CPUCL0_RESETB_REG, PLL_CON6_PLL_CPUCL0_STABLE_REG, PLL_LOCKTIME_REG_PLL_CPUCL0_PLL_LOCK_TIME_REG, PLL_CON4_PLL_CPUCL0_AFCINIT_SEL, PLL_CON4_PLL_CPUCL0_MASK_SEL, PLL_CON6_PLL_CPUCL0_LDO_SEL, PLL_CON6_PLL_CPUCL0_LDO_CON, PLL_CON7_PLL_CPUCL0_REV, PLL_CON7_PLL_CPUCL0_R_CON, PLL_CON7_PLL_CPUCL0_C_CON, PLL_CON7_PLL_CPUCL0_ICP, PLL_CON7_PLL_CPUCL0_EXT_AFC, PLL_CON7_PLL_CPUCL0_EN_FOUT, PLL_CON7_PLL_CPUCL0_EN_FOUT2, PLL_CON7_PLL_CPUCL0_EN_FOUT3, PLL_CON7_PLL_CPUCL0_EN_FOUT4, PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, PLL_CON3_PLL_CPUCL1_ENABLE, PLL_CON3_PLL_CPUCL1_STABLE, PLL_CON3_PLL_CPUCL1_DIV_P, PLL_CON3_PLL_CPUCL1_DIV_M, PLL_CON3_PLL_CPUCL1_DIV_S, PLL_CON4_PLL_CPUCL1_ICP, PLL_CON4_PLL_CPUCL1_LOCK_CON_IN, PLL_CON4_PLL_CPUCL1_LOCK_CON_OUT, PLL_CON4_PLL_CPUCL1_LOCK_CON_DLY, PLL_CON4_PLL_CPUCL1_AFC_ENB, PLL_CON4_PLL_CPUCL1_EXT_AFC, DBG_NFO_PLL_CPUCL1_AFC_CODE, PLL_CON4_PLL_CPUCL1_FOUT_MASK, PLL_CON4_PLL_CPUCL1_RSEL, PLL_CON4_PLL_CPUCL1_BYPASS, PLL_CON0_PLL_CPUCL1_MUX_SEL, PLL_CON0_PLL_CPUCL1_MUX_BUSY, PLL_LOCKTIME_PLL_CPUCL1_RESET_REQ_TIME, PLL_CON1_PLL_CPUCL1_IGNORE_REQ_SYSCLK, PLL_CON4_PLL_CPUCL1_DISABLE_ALL_CLOCK_STOP, PLL_CON4_PLL_CPUCL1_DISABLE_SDIV_CLOCK_STOP, PLL_CON3_PLL_CPUCL1_USE_HW_LOCK_DET, PLL_CON3_PLL_CPUCL1_LOCK_FAIL, PLL_CON3_PLL_CPUCL1_USE_LOCK_FAIL, PLL_CON1_PLL_CPUCL1_ENABLE_AUTOMATIC_BYPASS, PLL_CON1_PLL_CPUCL1_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_PLL_CPUCL1_MANUAL_PLL_CTRL, PLL_CON1_PLL_CPUCL1_AUTO_PLL_CTRL, DBG_NFO_PLL_CPUCL1_DEBUG_INFO, PLL_CON2_PLL_CPUCL1_ENABLE_FILTER_AUTOMATIC_CLKGATING, PLL_CON2_PLL_CPUCL1_FILTER_CNT_EXPIRE_VALUE, PLL_CON1_PLL_CPUCL1_OVERRIDE_BY_HCH, PLL_CON3_PLL_CPUCL1_LOCK_EN, PLL_CON6_PLL_CPUCL1_RESETB_REG, PLL_CON6_PLL_CPUCL1_VREG_CON, PLL_CON6_PLL_CPUCL1_VBGR_CON, PLL_CON6_PLL_CPUCL1_STABLE_REG, PLL_LOCKTIME_REG_PLL_CPUCL1_PLL_LOCK_TIME_REG, PLL_LOCKTIME_PLL_DSU_PLL_LOCK_TIME, PLL_CON3_PLL_DSU_ENABLE, PLL_CON3_PLL_DSU_STABLE, PLL_CON3_PLL_DSU_DIV_P, PLL_CON3_PLL_DSU_DIV_M, PLL_CON3_PLL_DSU_DIV_S, PLL_CON9_PLL_DSU_K, PLL_CON8_PLL_DSU_F, PLL_CON4_PLL_DSU_SSCGEN, PLL_CON5_PLL_DSU_MFR, PLL_CON5_PLL_DSU_MRR, PLL_CON5_PLL_DSU_SEL_PF, PLL_CON4_PLL_DSU_LOCK_CON_IN, PLL_CON4_PLL_DSU_LOCK_CON_OUT, PLL_CON4_PLL_DSU_LOCK_CON_DLY, PLL_CON4_PLL_DSU_AFC_ENB, DBG_NFO_PLL_DSU_AFC_CODE, PLL_CON4_PLL_DSU_BYPASS, PLL_CON0_PLL_DSU_MUX_SEL, PLL_CON0_PLL_DSU_MUX_BUSY, PLL_LOCKTIME_PLL_DSU_RESET_REQ_TIME, PLL_CON1_PLL_DSU_IGNORE_REQ_SYSCLK, PLL_CON4_PLL_DSU_DISABLE_ALL_CLOCK_STOP, PLL_CON4_PLL_DSU_DISABLE_SDIV_CLOCK_STOP, PLL_CON3_PLL_DSU_USE_HW_LOCK_DET, PLL_CON3_PLL_DSU_LOCK_FAIL, PLL_CON3_PLL_DSU_USE_LOCK_FAIL, PLL_CON1_PLL_DSU_ENABLE_AUTOMATIC_BYPASS, PLL_CON1_PLL_DSU_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_PLL_DSU_MANUAL_PLL_CTRL, PLL_CON1_PLL_DSU_AUTO_PLL_CTRL, DBG_NFO_PLL_DSU_DEBUG_INFO, PLL_CON2_PLL_DSU_ENABLE_FILTER_AUTOMATIC_CLKGATING, PLL_CON2_PLL_DSU_FILTER_CNT_EXPIRE_VALUE, PLL_CON1_PLL_DSU_OVERRIDE_BY_HCH, PLL_CON3_PLL_DSU_LOCK_EN, PLL_CON6_PLL_DSU_RESETB_REG, PLL_CON6_PLL_DSU_STABLE_REG, PLL_LOCKTIME_REG_PLL_DSU_PLL_LOCK_TIME_REG, PLL_CON4_PLL_DSU_AFCINIT_SEL, PLL_CON4_PLL_DSU_MASK_SEL, PLL_CON6_PLL_DSU_LDO_SEL, PLL_CON6_PLL_DSU_LDO_CON, PLL_CON7_PLL_DSU_REV, PLL_CON7_PLL_DSU_R_CON, PLL_CON7_PLL_DSU_C_CON, PLL_CON7_PLL_DSU_ICP, PLL_CON7_PLL_DSU_EXT_AFC, PLL_CON7_PLL_DSU_EN_FOUT, PLL_CON7_PLL_DSU_EN_FOUT2, PLL_CON7_PLL_DSU_EN_FOUT3, PLL_CON7_PLL_DSU_EN_FOUT4, PLL_LOCKTIME_PLL_MIF_PLL_LOCK_TIME, PLL_CON3_PLL_MIF_ENABLE, PLL_CON3_PLL_MIF_STABLE, PLL_CON3_PLL_MIF_DIV_P, PLL_CON3_PLL_MIF_DIV_M, PLL_CON3_PLL_MIF_DIV_S, PLL_CON4_PLL_MIF_ICP, PLL_CON4_PLL_MIF_LOCK_CON_IN, PLL_CON4_PLL_MIF_LOCK_CON_OUT, PLL_CON4_PLL_MIF_LOCK_CON_DLY, PLL_CON4_PLL_MIF_AFC_ENB, PLL_CON4_PLL_MIF_EXT_AFC, DBG_NFO_PLL_MIF_AFC_CODE, PLL_CON4_PLL_MIF_FOUT_MASK, PLL_CON4_PLL_MIF_RSEL, PLL_CON4_PLL_MIF_BYPASS, PLL_CON0_PLL_MIF_MUX_SEL, PLL_CON0_PLL_MIF_MUX_BUSY, PLL_LOCKTIME_PLL_MIF_RESET_REQ_TIME, PLL_CON1_PLL_MIF_IGNORE_REQ_SYSCLK, PLL_CON4_PLL_MIF_DISABLE_ALL_CLOCK_STOP, PLL_CON4_PLL_MIF_DISABLE_SDIV_CLOCK_STOP, PLL_CON3_PLL_MIF_USE_HW_LOCK_DET, PLL_CON3_PLL_MIF_LOCK_FAIL, PLL_CON3_PLL_MIF_USE_LOCK_FAIL, PLL_CON1_PLL_MIF_ENABLE_AUTOMATIC_BYPASS, PLL_CON1_PLL_MIF_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_PLL_MIF_MANUAL_PLL_CTRL, PLL_CON1_PLL_MIF_AUTO_PLL_CTRL, DBG_NFO_PLL_MIF_DEBUG_INFO, PLL_CON2_PLL_MIF_ENABLE_FILTER_AUTOMATIC_CLKGATING, PLL_CON2_PLL_MIF_FILTER_CNT_EXPIRE_VALUE, PLL_CON1_PLL_MIF_OVERRIDE_BY_HCH, PLL_CON3_PLL_MIF_LOCK_EN, PLL_LOCKTIME_PLL_MIF_S2D_PLL_LOCK_TIME, PLL_CON3_PLL_MIF_S2D_ENABLE, PLL_CON3_PLL_MIF_S2D_STABLE, PLL_CON3_PLL_MIF_S2D_DIV_P, PLL_CON3_PLL_MIF_S2D_DIV_M, PLL_CON3_PLL_MIF_S2D_DIV_S, PLL_CON4_PLL_MIF_S2D_ICP, PLL_CON4_PLL_MIF_S2D_LOCK_CON_IN, PLL_CON4_PLL_MIF_S2D_LOCK_CON_OUT, PLL_CON4_PLL_MIF_S2D_LOCK_CON_DLY, PLL_CON4_PLL_MIF_S2D_AFC_ENB, PLL_CON4_PLL_MIF_S2D_EXT_AFC, DBG_NFO_PLL_MIF_S2D_AFC_CODE, PLL_CON4_PLL_MIF_S2D_FOUT_MASK, PLL_CON4_PLL_MIF_S2D_RSEL, PLL_CON4_PLL_MIF_S2D_BYPASS, PLL_CON0_PLL_MIF_S2D_MUX_SEL, PLL_CON0_PLL_MIF_S2D_MUX_BUSY, PLL_LOCKTIME_PLL_MIF_S2D_RESET_REQ_TIME, PLL_CON1_PLL_MIF_S2D_IGNORE_REQ_SYSCLK, PLL_CON4_PLL_MIF_S2D_DISABLE_ALL_CLOCK_STOP, PLL_CON4_PLL_MIF_S2D_DISABLE_SDIV_CLOCK_STOP, PLL_CON3_PLL_MIF_S2D_USE_HW_LOCK_DET, PLL_CON3_PLL_MIF_S2D_LOCK_FAIL, PLL_CON3_PLL_MIF_S2D_USE_LOCK_FAIL, PLL_CON1_PLL_MIF_S2D_ENABLE_AUTOMATIC_BYPASS, PLL_CON1_PLL_MIF_S2D_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_PLL_MIF_S2D_MANUAL_PLL_CTRL, PLL_CON1_PLL_MIF_S2D_AUTO_PLL_CTRL, DBG_NFO_PLL_MIF_S2D_DEBUG_INFO, PLL_CON2_PLL_MIF_S2D_ENABLE_FILTER_AUTOMATIC_CLKGATING, PLL_CON2_PLL_MIF_S2D_FILTER_CNT_EXPIRE_VALUE, PLL_CON1_PLL_MIF_S2D_OVERRIDE_BY_HCH, PLL_CON3_PLL_MIF_S2D_LOCK_EN, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_CMGP_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_ALIVE_BUS_SELECT, CLK_CON_MUX_MUX_CLK_ALIVE_BUS_BUSY, CLK_CON_MUX_MUX_CLK_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_ALIVE_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_ALIVE_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_SELECT, CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_BUSY, CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_CMGP_PERI_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_SELECT, CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_BUSY, CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_ALIVE_I3C_PMIC_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_CHUBVTS_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CHUBVTS_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CHUBVTS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CHUBVTS_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_CHUBVTS_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_SELECT, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_BUSY, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_ALIVE_DBGCORE_UART_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_AP2GNSS_SELECT, CLK_CON_MUX_MUX_CLKCMU_AP2GNSS_BUSY, CLK_CON_MUX_MUX_CLKCMU_AP2GNSS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_AP2GNSS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_AP2GNSS_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_CHUB_PERI_SELECT, CLK_CON_MUX_MUX_CLKCMU_CHUB_PERI_BUSY, CLK_CON_MUX_MUX_CLKCMU_CHUB_PERI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CHUB_PERI_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_CHUB_PERI_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_ALIVE_USI0_SELECT, CLK_CON_MUX_MUX_CLK_ALIVE_USI0_BUSY, CLK_CON_MUX_MUX_CLK_ALIVE_USI0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_ALIVE_USI0_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_ALIVE_USI0_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_ALIVE_I2C_SELECT, CLK_CON_MUX_MUX_CLK_ALIVE_I2C_BUSY, CLK_CON_MUX_MUX_CLK_ALIVE_I2C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_ALIVE_I2C_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_ALIVE_I2C_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_AUD_UAIF3_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF3_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_UAIF3_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_AUD_UAIF3_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_AUD_UAIF2_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_AUD_UAIF1_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_AUD_UAIF0_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_AUD_CPU_SELECT, CLK_CON_MUX_MUX_CLK_AUD_CPU_BUSY, CLK_CON_MUX_MUX_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_CPU_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_AUD_CPU_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_AUD_FM_SELECT, CLK_CON_MUX_MUX_CLK_AUD_FM_BUSY, CLK_CON_MUX_MUX_CLK_AUD_FM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_FM_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_AUD_FM_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_AUD_UAIF4_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF4_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF4_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_UAIF4_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_AUD_UAIF4_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_AUD_UAIF5_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF5_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF5_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_UAIF5_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_AUD_UAIF5_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_AUD_UAIF6_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF6_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF6_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_UAIF6_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_AUD_UAIF6_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_AUD_DSIF_SELECT, CLK_CON_MUX_MUX_CLK_AUD_DSIF_BUSY, CLK_CON_MUX_MUX_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_DSIF_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_AUD_DSIF_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_AUD_CPU_PLL_SELECT, CLK_CON_MUX_MUX_CLK_AUD_CPU_PLL_BUSY, CLK_CON_MUX_MUX_CLK_AUD_CPU_PLL_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_CPU_PLL_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_AUD_CPU_PLL_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_AUD_BUS_SELECT, CLK_CON_MUX_MUX_CLK_AUD_BUS_BUSY, CLK_CON_MUX_MUX_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_AUD_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_AUD_PCMC_SELECT, CLK_CON_MUX_MUX_CLK_AUD_PCMC_BUSY, CLK_CON_MUX_MUX_CLK_AUD_PCMC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_AUD_PCMC_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_AUD_PCMC_DEBUG_INFO, CLK_CON_MUX_MUX_BUSC_CMUREF_SELECT, CLK_CON_MUX_MUX_BUSC_CMUREF_BUSY, CLK_CON_MUX_MUX_BUSC_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_BUSC_CMUREF_OVERRIDE_BY_HCH, DBG_NFO_MUX_BUSC_CMUREF_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_CHUB_TIMER_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_TIMER_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_TIMER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CHUB_TIMER_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_CHUB_TIMER_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_CHUB_USI0_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_USI0_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_USI0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CHUB_USI0_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_CHUB_USI0_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_CHUB_USI1_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_USI1_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_USI1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CHUB_USI1_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_CHUB_USI1_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_CHUB_USI2_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_USI2_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_USI2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CHUB_USI2_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_CHUB_USI2_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_CHUB_I2C_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_I2C_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CHUB_I2C_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_CHUB_I2C_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_CHUB_USI3_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_USI3_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_USI3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CHUB_USI3_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_CHUB_USI3_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_CHUB_BUS_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_BUS_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CHUB_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_CHUB_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_CHUBVTS_BUS_SELECT, CLK_CON_MUX_MUX_CLK_CHUBVTS_BUS_BUSY, CLK_CON_MUX_MUX_CLK_CHUBVTS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CHUBVTS_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_CHUBVTS_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_CMGP_I2C_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_I2C_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CMGP_I2C_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_CMGP_I2C_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_CMGP_USI0_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI0_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CMGP_USI0_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_CMGP_USI0_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_CMGP_USI4_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI4_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI4_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CMGP_USI4_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_CMGP_USI4_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_CMGP_I3C_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_I3C_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_I3C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CMGP_I3C_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_CMGP_I3C_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_CMGP_BUS_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_BUS_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CMGP_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_CMGP_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_CMGP_USI1_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI1_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CMGP_USI1_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_CMGP_USI1_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_CMGP_USI2_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI2_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CMGP_USI2_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_CMGP_USI2_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_CMGP_USI3_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI3_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CMGP_USI3_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_CMGP_USI3_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_SELECT, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_MFC_MFC_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_CORE_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_MIF_SWITCH_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_TAA_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_ISP_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_SELECT, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_BUSY, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_AUD_CPU_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_M2M_MSCL_SELECT, CLK_CON_MUX_MUX_CLKCMU_M2M_MSCL_BUSY, CLK_CON_MUX_MUX_CLKCMU_M2M_MSCL_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_M2M_MSCL_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_M2M_MSCL_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_CPUCL0_DBG_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_CIS_CLK0_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_CIS_CLK1_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_CIS_CLK2_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_HSI_UFS_EMBD_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI_UFS_EMBD_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_HSI_UFS_EMBD_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_HSI_UFS_EMBD_DEBUG_INFO, CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CMU_CMUREF_OVERRIDE_BY_HCH, DBG_NFO_MUX_CMU_CMUREF_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_PERI_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_NPU0_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_NPU0_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_NPU0_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_NPU0_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_NPU0_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_ALIVE_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_HSI_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_HSI_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_HSI_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_MIF_BUSP_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_PERI_IP_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_IP_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERI_IP_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_PERI_IP_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_DPU_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_USB_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_USB_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_USB_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_USB_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_TNR_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_PERI_MMC_CARD_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_MMC_CARD_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_PERI_MMC_CARD_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_PERI_MMC_CARD_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_SELECT, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_BUSY, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_CMU_BOOST_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_SELECT, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_BUSY, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_CORE_G3D_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_CSIS_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_MCSC_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_SELECT, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_BUSY, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_MCSC_GDC_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_USB_USB20DRD_SELECT, CLK_CON_MUX_MUX_CLKCMU_USB_USB20DRD_BUSY, CLK_CON_MUX_MUX_CLKCMU_USB_USB20DRD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_USB_USB20DRD_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_USB_USB20DRD_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_NPUS_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_G3D_SWITCH_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_CORE_SSS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CORE_SSS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CORE_SSS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CORE_SSS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_CORE_SSS_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_BUSC_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_CIS_CLK3_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_CIS_CLK4_DEBUG_INFO, CLK_CON_MUX_CLKCMU_G3D_BUS_SELECT, CLK_CON_MUX_CLKCMU_G3D_BUS_BUSY, CLK_CON_MUX_CLKCMU_G3D_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_CLKCMU_G3D_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_G3D_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_CIS_CLK5_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_DSU_SWITCH_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_CPUCL0_BUSP_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_DPU_DSIM_SELECT, CLK_CON_MUX_MUX_CLKCMU_DPU_DSIM_BUSY, CLK_CON_MUX_MUX_CLKCMU_DPU_DSIM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_DPU_DSIM_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_DPU_DSIM_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_SELECT, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_BUSY, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_MCSC_MCSC_DEBUG_INFO, CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLKCMU_AUD_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CORE_CMUREF_SELECT, CLK_CON_MUX_MUX_CORE_CMUREF_BUSY, CLK_CON_MUX_MUX_CORE_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CORE_CMUREF_OVERRIDE_BY_HCH, DBG_NFO_MUX_CORE_CMUREF_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_CORE_GIC_SELECT, CLK_CON_MUX_MUX_CLK_CORE_GIC_BUSY, CLK_CON_MUX_MUX_CLK_CORE_GIC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CORE_GIC_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_CORE_GIC_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_CPUCL0_PLL_DEBUG_INFO, CLK_CON_MUX_MUX_CPUCL0_CMUREF_SELECT, CLK_CON_MUX_MUX_CPUCL0_CMUREF_BUSY, CLK_CON_MUX_MUX_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CPUCL0_CMUREF_OVERRIDE_BY_HCH, DBG_NFO_MUX_CPUCL0_CMUREF_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_CPUCL1_PLL_DEBUG_INFO, CLK_CON_MUX_MUX_CPUCL1_CMUREF_SELECT, CLK_CON_MUX_MUX_CPUCL1_CMUREF_BUSY, CLK_CON_MUX_MUX_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CPUCL1_CMUREF_OVERRIDE_BY_HCH, DBG_NFO_MUX_CPUCL1_CMUREF_DEBUG_INFO, CLK_CON_MUX_MUX_DSU_CMUREF_SELECT, CLK_CON_MUX_MUX_DSU_CMUREF_BUSY, CLK_CON_MUX_MUX_DSU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_DSU_CMUREF_OVERRIDE_BY_HCH, DBG_NFO_MUX_DSU_CMUREF_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_DSU_PLL_SELECT, CLK_CON_MUX_MUX_CLK_DSU_PLL_BUSY, CLK_CON_MUX_MUX_CLK_DSU_PLL_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_DSU_PLL_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_DSU_PLL_DEBUG_INFO, CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_MIF_CMUREF_OVERRIDE_BY_HCH, DBG_NFO_MUX_MIF_CMUREF_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_S2D_CORE_SELECT, CLK_CON_MUX_MUX_CLK_S2D_CORE_BUSY, CLK_CON_MUX_MUX_CLK_S2D_CORE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_S2D_CORE_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_S2D_CORE_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_USB_BUS_SELECT, CLK_CON_MUX_MUX_CLK_USB_BUS_BUSY, CLK_CON_MUX_MUX_CLK_USB_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_USB_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_USB_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_USB_USB20DRD_SELECT, CLK_CON_MUX_MUX_CLK_USB_USB20DRD_BUSY, CLK_CON_MUX_MUX_CLK_USB_USB20DRD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_USB_USB20DRD_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_USB_USB20DRD_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_VTS_BUS_SELECT, CLK_CON_MUX_MUX_CLK_VTS_BUS_BUSY, CLK_CON_MUX_MUX_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_VTS_BUS_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_VTS_BUS_DEBUG_INFO, CLK_CON_MUX_MUX_VTS_DMIC_AUD_SELECT, CLK_CON_MUX_MUX_VTS_DMIC_AUD_BUSY, CLK_CON_MUX_MUX_VTS_DMIC_AUD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_VTS_DMIC_AUD_OVERRIDE_BY_HCH, DBG_NFO_MUX_VTS_DMIC_AUD_DEBUG_INFO, CLK_CON_MUX_MUX_VTS_SERIAL_LIF_SELECT, CLK_CON_MUX_MUX_VTS_SERIAL_LIF_BUSY, CLK_CON_MUX_MUX_VTS_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_VTS_SERIAL_LIF_OVERRIDE_BY_HCH, DBG_NFO_MUX_VTS_SERIAL_LIF_DEBUG_INFO, CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_SELECT, CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_BUSY, CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_OVERRIDE_BY_HCH, DBG_NFO_MUX_CLK_VTS_DMIC_IF_DEBUG_INFO, PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_ALIVE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_ALIVE_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_ALIVE_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_ALIVE_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLK_RCO_ALIVE_USER_MUX_SEL, PLL_CON0_MUX_CLK_RCO_ALIVE_USER_BUSY, PLL_CON1_MUX_CLK_RCO_ALIVE_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLK_RCO_ALIVE_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLK_RCO_ALIVE_USER_DEBUG_INFO, PLL_CON1_MUX_CLK_RCO_ALIVE_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_MUX_SEL, PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_BUSY, PLL_CON1_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_DEBUG_INFO, PLL_CON1_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLK_ALIVE_TIMER_MUX_SEL, PLL_CON0_MUX_CLK_ALIVE_TIMER_BUSY, PLL_CON1_MUX_CLK_ALIVE_TIMER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLK_ALIVE_TIMER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLK_ALIVE_TIMER_DEBUG_INFO, PLL_CON1_MUX_CLK_ALIVE_TIMER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_BUSY, PLL_CON1_MUX_CLKCMU_AUD_CPU_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_AUD_CPU_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_AUD_CPU_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_AUD_CPU_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_AUD_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_AUD_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_AUD_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_AUD_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_AUD_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_AUD_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CP_PCMC_CLK_USER_MUX_SEL, PLL_CON0_MUX_CP_PCMC_CLK_USER_BUSY, PLL_CON1_MUX_CP_PCMC_CLK_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CP_PCMC_CLK_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CP_PCMC_CLK_USER_DEBUG_INFO, PLL_CON1_MUX_CP_PCMC_CLK_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_BUSC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_BUSC_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_BUSC_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_BUSC_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLK_CHUB_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLK_CHUB_BUS_USER_BUSY, PLL_CON1_MUX_CLK_CHUB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLK_CHUB_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLK_CHUB_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLK_CHUB_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_CHUB_PERI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CHUB_PERI_USER_BUSY, PLL_CON1_MUX_CLKCMU_CHUB_PERI_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_CHUB_PERI_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_CHUB_PERI_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_CHUB_PERI_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_CHUB_RCO_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CHUB_RCO_USER_BUSY, PLL_CON1_MUX_CLKCMU_CHUB_RCO_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_CHUB_RCO_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_CHUB_RCO_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_CHUB_RCO_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_CHUBVTS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CHUBVTS_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_CHUBVTS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_CHUBVTS_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_CHUBVTS_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_CHUBVTS_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_CHUBVTS_RCO_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CHUBVTS_RCO_USER_BUSY, PLL_CON1_MUX_CLKCMU_CHUBVTS_RCO_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_CHUBVTS_RCO_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_CHUBVTS_RCO_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_CHUBVTS_RCO_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_CMGP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_CMGP_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_CMGP_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_CMGP_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER_BUSY, PLL_CON1_MUX_CLKCMU_CMGP_PERI_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_CMGP_PERI_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_CMGP_PERI_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_CMGP_PERI_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_CMGP_RCO_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CMGP_RCO_USER_BUSY, PLL_CON1_MUX_CLKCMU_CMGP_RCO_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_CMGP_RCO_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_CMGP_RCO_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_CMGP_RCO_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_CORE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_CORE_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_CORE_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_CORE_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_CORE_G3D_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CORE_G3D_USER_BUSY, PLL_CON1_MUX_CLKCMU_CORE_G3D_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_CORE_G3D_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_CORE_G3D_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_CORE_G3D_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_CORE_SSS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CORE_SSS_USER_BUSY, PLL_CON1_MUX_CLKCMU_CORE_SSS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_CORE_SSS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_CORE_SSS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_CORE_SSS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL0_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_CPUCL0_BUSP_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_CPUCL0_BUSP_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_CPUCL0_BUSP_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_CSIS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CSIS_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_CSIS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_CSIS_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_CSIS_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_CSIS_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_DPU_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_DPU_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_DPU_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_DPU_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_DPU_DSIM_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DPU_DSIM_USER_BUSY, PLL_CON1_MUX_CLKCMU_DPU_DSIM_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_DPU_DSIM_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_DPU_DSIM_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_DPU_DSIM_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_DSU_SWITCH_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_G3D_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G3D_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_G3D_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_G3D_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_G3D_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_G3D_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_HSI_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_HSI_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_HSI_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_HSI_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_HSI_UFS_EMBD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI_UFS_EMBD_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_HSI_UFS_EMBD_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_HSI_UFS_EMBD_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_HSI_UFS_EMBD_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_ISP_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ISP_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_ISP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_ISP_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_ISP_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_ISP_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_M2M_MSCL_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_M2M_MSCL_USER_BUSY, PLL_CON1_MUX_CLKCMU_M2M_MSCL_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_M2M_MSCL_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_M2M_MSCL_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_M2M_MSCL_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_MCSC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_MCSC_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_MCSC_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_MCSC_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER_BUSY, PLL_CON1_MUX_CLKCMU_MCSC_GDC_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_MCSC_GDC_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_MCSC_GDC_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_MCSC_GDC_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER_BUSY, PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_MCSC_MCSC_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_BUSY, PLL_CON1_MUX_CLKCMU_MFC_MFC_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_MFC_MFC_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_MFC_MFC_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_MFC_MFC_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_BUSY, PLL_CON1_MUX_CLKCMU_MIF_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_MIF_BUSP_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_MIF_BUSP_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_MIF_BUSP_USER_OVERRIDE_BY_HCH, PLL_CON0_CLKMUX_MIF_DDRPHY2X_MUX_SEL, PLL_CON0_CLKMUX_MIF_DDRPHY2X_BUSY, PLL_CON1_CLKMUX_MIF_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_CLKMUX_MIF_DDRPHY2X_IGNORE_REQ_SYSCLK, DBG_NFO_CLKMUX_MIF_DDRPHY2X_DEBUG_INFO, PLL_CON1_CLKMUX_MIF_DDRPHY2X_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_NPU0_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_NPU0_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_NPU0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_NPU0_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_NPU0_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_NPU0_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_NPUS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_NPUS_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_NPUS_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_NPUS_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_PERI_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_PERI_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_PERI_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_PERI_USI00_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_USI00_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_USI00_USI_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_PERI_USI00_USI_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_PERI_USI00_USI_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_PERI_USI00_USI_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_PERI_USI01_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_USI01_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_USI01_USI_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_PERI_USI01_USI_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_PERI_USI01_USI_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_PERI_USI01_USI_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_PERI_USI02_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_USI02_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_USI02_USI_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_PERI_USI02_USI_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_PERI_USI02_USI_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_PERI_USI02_USI_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_PERI_USI03_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_USI03_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_USI03_USI_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_PERI_USI03_USI_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_PERI_USI03_USI_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_PERI_USI03_USI_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_PERI_USI04_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_USI04_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_USI04_USI_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_PERI_USI04_USI_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_PERI_USI04_USI_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_PERI_USI04_USI_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_PERI_USI05_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_USI05_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_USI05_USI_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_PERI_USI05_USI_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_PERI_USI05_USI_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_PERI_USI05_USI_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_PERI_USI_I2C_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_USI_I2C_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_USI_I2C_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_PERI_USI_I2C_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_PERI_USI_I2C_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_PERI_USI_I2C_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_PERI_UART_DBG_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_UART_DBG_BUSY, PLL_CON1_MUX_CLKCMU_PERI_UART_DBG_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_PERI_UART_DBG_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_PERI_UART_DBG_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_PERI_UART_DBG_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_PERI_MMC_CARD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_MMC_CARD_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_PERI_MMC_CARD_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_PERI_MMC_CARD_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_PERI_MMC_CARD_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_PERI_USI06_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_USI06_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_USI06_USI_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_PERI_USI06_USI_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_PERI_USI06_USI_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_PERI_USI06_USI_USER_OVERRIDE_BY_HCH, PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_MUX_SEL, PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_BUSY, PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_IGNORE_REQ_SYSCLK, DBG_NFO_CLKCMU_MIF_DDRPHY2X_S2D_DEBUG_INFO, PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_TAA_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_TAA_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_TAA_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_TAA_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_TAA_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_TAA_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_TNR_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_TNR_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_TNR_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_TNR_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_TNR_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_TNR_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_USB_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_USB_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_USB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_USB_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_USB_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_USB_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER_BUSY, PLL_CON1_MUX_CLKCMU_USB_USB20DRD_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_USB_USB20DRD_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_USB_USB20DRD_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_USB_USB20DRD_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKAUD_USB_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKAUD_USB_BUS_USER_BUSY, PLL_CON1_MUX_CLKAUD_USB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKAUD_USB_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKAUD_USB_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKAUD_USB_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKAUD_USB_USB20DRD_USER_MUX_SEL, PLL_CON0_MUX_CLKAUD_USB_USB20DRD_USER_BUSY, PLL_CON1_MUX_CLKAUD_USB_USB20DRD_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKAUD_USB_USB20DRD_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKAUD_USB_USB20DRD_USER_DEBUG_INFO, PLL_CON1_MUX_CLKAUD_USB_USB20DRD_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_VTS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_VTS_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_VTS_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_VTS_BUS_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLKCMU_VTS_RCO_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_VTS_RCO_USER_BUSY, PLL_CON1_MUX_CLKCMU_VTS_RCO_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLKCMU_VTS_RCO_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLKCMU_VTS_RCO_USER_DEBUG_INFO, PLL_CON1_MUX_CLKCMU_VTS_RCO_USER_OVERRIDE_BY_HCH, PLL_CON0_MUX_CLK_AUD_DMIC_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLK_AUD_DMIC_BUS_USER_BUSY, PLL_CON1_MUX_CLK_AUD_DMIC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, PLL_CON1_MUX_CLK_AUD_DMIC_BUS_USER_IGNORE_REQ_SYSCLK, DBG_NFO_MUX_CLK_AUD_DMIC_BUS_USER_DEBUG_INFO, PLL_CON1_MUX_CLK_AUD_DMIC_BUS_USER_OVERRIDE_BY_HCH, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_BUSY, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_OVERRIDE_BY_HCH, DBG_NFO_MUX_HCHGEN_CLK_AUD_CPU_DEBUG_INFO, CLK_CON_DIV_CLKCMU_CMGP_PERI_DIVRATIO, CLK_CON_DIV_CLKCMU_CMGP_PERI_BUSY, CLK_CON_DIV_CLKCMU_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CMGP_PERI_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_CMGP_PERI_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_ALIVE_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_ALIVE_BUS_BUSY, CLK_CON_DIV_DIV_CLK_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ALIVE_BUS_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_ALIVE_BUS_DEBUG_INFO, CLK_CON_DIV_CLKCMU_CMGP_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CMGP_BUS_BUSY, CLK_CON_DIV_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CMGP_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_CMGP_BUS_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_DIVRATIO, CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_BUSY, CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_ALIVE_I3C_PMIC_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_DIVRATIO, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_BUSY, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_ALIVE_DBGCORE_UART_DEBUG_INFO, CLK_CON_DIV_CLKCMU_CHUBVTS_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CHUBVTS_BUS_BUSY, CLK_CON_DIV_CLKCMU_CHUBVTS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CHUBVTS_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_CHUBVTS_BUS_DEBUG_INFO, CLK_CON_DIV_CLKCMU_CHUB_PERI_DIVRATIO, CLK_CON_DIV_CLKCMU_CHUB_PERI_BUSY, CLK_CON_DIV_CLKCMU_CHUB_PERI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CHUB_PERI_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_CHUB_PERI_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_ALIVE_USI0_DIVRATIO, CLK_CON_DIV_DIV_CLK_ALIVE_USI0_BUSY, CLK_CON_DIV_DIV_CLK_ALIVE_USI0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ALIVE_USI0_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_ALIVE_USI0_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_ALIVE_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_ALIVE_I2C_BUSY, CLK_CON_DIV_DIV_CLK_ALIVE_I2C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ALIVE_I2C_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_ALIVE_I2C_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_CPU_PCLKDBG_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_BUSY, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_FM_SPDY_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_UAIF0_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_UAIF1_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_UAIF2_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_UAIF3_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF3_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_UAIF3_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_UAIF3_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_CPU_ACLK_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_AUD_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_BUSP_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_BUSP_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_CNT_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CNT_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CNT_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_CNT_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_CNT_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_UAIF4_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF4_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF4_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_UAIF4_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_UAIF4_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_DSIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_DSIF_BUSY, CLK_CON_DIV_DIV_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_DSIF_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_DSIF_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_FM_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_FM_BUSY, CLK_CON_DIV_DIV_CLK_AUD_FM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_FM_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_FM_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_UAIF5_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF5_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF5_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_UAIF5_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_UAIF5_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_UAIF6_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF6_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF6_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_UAIF6_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_UAIF6_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_MCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_MCLK_BUSY, CLK_CON_DIV_DIV_CLK_AUD_MCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_MCLK_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_MCLK_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_BUSY, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_AUDIF_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_BUSD_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_BUSD_BUSY, CLK_CON_DIV_DIV_CLK_AUD_BUSD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_BUSD_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_BUSD_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_PCMC_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_PCMC_BUSY, CLK_CON_DIV_DIV_CLK_AUD_PCMC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_PCMC_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_PCMC_DEBUG_INFO, CLK_CON_DIV_CLKAUD_USB_BUS_DIVRATIO, CLK_CON_DIV_CLKAUD_USB_BUS_BUSY, CLK_CON_DIV_CLKAUD_USB_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKAUD_USB_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKAUD_USB_BUS_DEBUG_INFO, CLK_CON_DIV_CLKAUD_USB_USB20DRD_DIVRATIO, CLK_CON_DIV_CLKAUD_USB_USB20DRD_BUSY, CLK_CON_DIV_CLKAUD_USB_USB20DRD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKAUD_USB_USB20DRD_OVERRIDE_BY_HCH, DBG_NFO_CLKAUD_USB_USB20DRD_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_CPU_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_CPU_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_CPU_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_AUD_CPU_ACP_DEBUG_INFO, CLK_CON_DIV_CLK_AUD_DMIC_DIVRATIO, CLK_CON_DIV_CLK_AUD_DMIC_BUSY, CLK_CON_DIV_CLK_AUD_DMIC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLK_AUD_DMIC_OVERRIDE_BY_HCH, DBG_NFO_CLK_AUD_DMIC_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_BUSC_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_BUSC_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_BUSC_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_BUSC_BUSP_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_BUSC_BUSP_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CHUB_USI0_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_USI0_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_USI0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CHUB_USI0_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CHUB_USI0_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CHUB_USI1_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_USI1_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_USI1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CHUB_USI1_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CHUB_USI1_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CHUB_USI2_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_USI2_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_USI2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CHUB_USI2_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CHUB_USI2_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CHUB_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_I2C_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CHUB_I2C_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CHUB_I2C_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CHUB_USI3_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_USI3_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_USI3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CHUB_USI3_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CHUB_USI3_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CHUB_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_BUS_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CHUB_BUS_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CHUB_BUS_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CHUBVTS_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUBVTS_BUS_BUSY, CLK_CON_DIV_DIV_CLK_CHUBVTS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CHUBVTS_BUS_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CHUBVTS_BUS_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CMGP_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_I2C_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CMGP_I2C_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CMGP_I2C_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CMGP_USI0_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI0_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CMGP_USI0_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CMGP_USI0_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CMGP_USI4_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI4_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI4_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CMGP_USI4_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CMGP_USI4_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CMGP_I3C_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_I3C_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_I3C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CMGP_I3C_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CMGP_I3C_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CMGP_USI1_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI1_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CMGP_USI1_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CMGP_USI1_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CMGP_USI2_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI2_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CMGP_USI2_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CMGP_USI2_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CMGP_USI3_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI3_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CMGP_USI3_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CMGP_USI3_DEBUG_INFO, CLK_CON_DIV_CLKCMU_ALIVE_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_ALIVE_BUS_BUSY, CLK_CON_DIV_CLKCMU_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_ALIVE_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_ALIVE_BUS_DEBUG_INFO, CLK_CON_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_G3D_SWITCH_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_G3D_SWITCH_DEBUG_INFO, CLK_CON_DIV_CLKCMU_PERI_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_BUS_BUSY, CLK_CON_DIV_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERI_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_PERI_BUS_DEBUG_INFO, CLK_CON_DIV_CLKCMU_DPU_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_DPU_BUS_BUSY, CLK_CON_DIV_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_DPU_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_DPU_BUS_DEBUG_INFO, CLK_CON_DIV_CLKCMU_MFC_MFC_DIVRATIO, CLK_CON_DIV_CLKCMU_MFC_MFC_BUSY, CLK_CON_DIV_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_MFC_MFC_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_MFC_MFC_DEBUG_INFO, CLK_CON_DIV_CLKCMU_CORE_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CORE_BUS_BUSY, CLK_CON_DIV_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CORE_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_CORE_BUS_DEBUG_INFO, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_CPUCL0_SWITCH_DEBUG_INFO, CLK_CON_DIV_CLKCMU_TAA_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_TAA_BUS_BUSY, CLK_CON_DIV_CLKCMU_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_TAA_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_TAA_BUS_DEBUG_INFO, CLK_CON_DIV_CLKCMU_ISP_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_ISP_BUS_BUSY, CLK_CON_DIV_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_ISP_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_ISP_BUS_DEBUG_INFO, CLK_CON_DIV_CLKCMU_AUD_CPU_DIVRATIO, CLK_CON_DIV_CLKCMU_AUD_CPU_BUSY, CLK_CON_DIV_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_AUD_CPU_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_AUD_CPU_DEBUG_INFO, CLK_CON_DIV_CLKCMU_M2M_MSCL_DIVRATIO, CLK_CON_DIV_CLKCMU_M2M_MSCL_BUSY, CLK_CON_DIV_CLKCMU_M2M_MSCL_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_M2M_MSCL_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_M2M_MSCL_DEBUG_INFO, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_CPUCL0_DBG_BUS_DEBUG_INFO, CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CIS_CLK0_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_CIS_CLK0_DEBUG_INFO, CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CIS_CLK1_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_CIS_CLK1_DEBUG_INFO, CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CIS_CLK2_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_CIS_CLK2_DEBUG_INFO, CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD_BUSY, CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_HSI_UFS_EMBD_DEBUG_INFO, CLK_CON_DIV_CLKCMU_NPU0_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_NPU0_BUS_BUSY, CLK_CON_DIV_CLKCMU_NPU0_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_NPU0_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_NPU0_BUS_DEBUG_INFO, CLK_CON_DIV_CLKCMU_MIF_BUSP_DIVRATIO, CLK_CON_DIV_CLKCMU_MIF_BUSP_BUSY, CLK_CON_DIV_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_MIF_BUSP_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_MIF_BUSP_DEBUG_INFO, CLK_CON_DIV_CLKCMU_PERI_IP_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_IP_BUSY, CLK_CON_DIV_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERI_IP_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_PERI_IP_DEBUG_INFO, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_CPUCL1_SWITCH_DEBUG_INFO, CLK_CON_DIV_CLKCMU_USB_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_USB_BUS_BUSY, CLK_CON_DIV_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_USB_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_USB_BUS_DEBUG_INFO, CLK_CON_DIV_CLKCMU_TNR_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_TNR_BUS_BUSY, CLK_CON_DIV_CLKCMU_TNR_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_TNR_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_TNR_BUS_DEBUG_INFO, CLK_CON_DIV_CLKCMU_CMU_BOOST_DIVRATIO, CLK_CON_DIV_CLKCMU_CMU_BOOST_BUSY, CLK_CON_DIV_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CMU_BOOST_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_CMU_BOOST_DEBUG_INFO, CLK_CON_DIV_CLKCMU_CORE_G3D_DIVRATIO, CLK_CON_DIV_CLKCMU_CORE_G3D_BUSY, CLK_CON_DIV_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CORE_G3D_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_CORE_G3D_DEBUG_INFO, CLK_CON_DIV_CLKCMU_CSIS_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CSIS_BUS_BUSY, CLK_CON_DIV_CLKCMU_CSIS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CSIS_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_CSIS_BUS_DEBUG_INFO, CLK_CON_DIV_CLKCMU_MCSC_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_MCSC_BUS_BUSY, CLK_CON_DIV_CLKCMU_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_MCSC_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_MCSC_BUS_DEBUG_INFO, CLK_CON_DIV_CLKCMU_HSI_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI_BUS_BUSY, CLK_CON_DIV_CLKCMU_HSI_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_HSI_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_HSI_BUS_DEBUG_INFO, CLK_CON_DIV_CLKCMU_PERI_MMC_CARD_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_MMC_CARD_BUSY, CLK_CON_DIV_CLKCMU_PERI_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_PERI_MMC_CARD_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_PERI_MMC_CARD_DEBUG_INFO, CLK_CON_DIV_CLKCMU_MCSC_GDC_DIVRATIO, CLK_CON_DIV_CLKCMU_MCSC_GDC_BUSY, CLK_CON_DIV_CLKCMU_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_MCSC_GDC_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_MCSC_GDC_DEBUG_INFO, CLK_CON_DIV_CLKCMU_USB_USB20DRD_DIVRATIO, CLK_CON_DIV_CLKCMU_USB_USB20DRD_BUSY, CLK_CON_DIV_CLKCMU_USB_USB20DRD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_USB_USB20DRD_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_USB_USB20DRD_DEBUG_INFO, CLK_CON_DIV_CLKCMU_NPUS_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_NPUS_BUS_BUSY, CLK_CON_DIV_CLKCMU_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_NPUS_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_NPUS_BUS_DEBUG_INFO, CLK_CON_DIV_CLKCMU_CORE_SSS_DIVRATIO, CLK_CON_DIV_CLKCMU_CORE_SSS_BUSY, CLK_CON_DIV_CLKCMU_CORE_SSS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CORE_SSS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_CORE_SSS_DEBUG_INFO, CLK_CON_DIV_CLKCMU_BUSC_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_BUSC_BUS_BUSY, CLK_CON_DIV_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_BUSC_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_BUSC_BUS_DEBUG_INFO, CLK_CON_DIV_CLKCMU_CIS_CLK3_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK3_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CIS_CLK3_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_CIS_CLK3_DEBUG_INFO, CLK_CON_DIV_CLKCMU_CIS_CLK4_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK4_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CIS_CLK4_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_CIS_CLK4_DEBUG_INFO, CLK_CON_DIV_CLKCMU_CIS_CLK5_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK5_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CIS_CLK5_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_CIS_CLK5_DEBUG_INFO, CLK_CON_DIV_CLKCMU_DSU_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_DSU_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_DSU_SWITCH_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_DSU_SWITCH_DEBUG_INFO, CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_CPUCL0_BUSP_DEBUG_INFO, CLK_CON_DIV_CLKCMU_DPU_DSIM_DIVRATIO, CLK_CON_DIV_CLKCMU_DPU_DSIM_BUSY, CLK_CON_DIV_CLKCMU_DPU_DSIM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_DPU_DSIM_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_DPU_DSIM_DEBUG_INFO, CLK_CON_DIV_CLKCMU_MCSC_MCSC_DIVRATIO, CLK_CON_DIV_CLKCMU_MCSC_MCSC_BUSY, CLK_CON_DIV_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_MCSC_MCSC_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_MCSC_MCSC_DEBUG_INFO, CLK_CON_DIV_CLKCMU_AUD_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_AUD_BUS_BUSY, CLK_CON_DIV_CLKCMU_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_AUD_BUS_OVERRIDE_BY_HCH, DBG_NFO_CLKCMU_AUD_BUS_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CORE_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CORE_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_CORE_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CORE_BUSP_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CORE_BUSP_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CPUCL0_SHORTSTOP_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CPUCL0_DBG_PCLKDBG_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CPUCL1_SHORTSTOP_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CPUCL1_HTU_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CSIS_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CSIS_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_CSIS_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CSIS_BUSP_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CSIS_BUSP_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_DPU_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DPU_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DPU_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_DPU_BUSP_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_DPU_BUSP_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_BUSY, CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_DSU_SHORTSTOP_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CLUSTER0_ACLK_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CLUSTER0_ATCLK_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CLUSTER0_PCLK_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CLUSTER0_PERIPHCLK_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_G3D_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_G3D_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_G3D_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_G3D_BUSP_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_G3D_BUSP_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_ISP_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_ISP_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_ISP_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_ISP_BUSP_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_ISP_BUSP_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_M2M_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_M2M_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_M2M_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_M2M_BUSP_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_M2M_BUSP_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_MCSC_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MCSC_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MCSC_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_MCSC_BUSP_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_MCSC_BUSP_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_MFC_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MFC_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MFC_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_MFC_BUSP_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_MFC_BUSP_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_NPU0_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_NPU0_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_NPU0_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_NPU0_BUSP_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_NPU0_BUSP_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_NPUS_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_NPUS_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_NPUS_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_NPUS_BUSP_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_NPUS_BUSP_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_PERI_USI00_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI00_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI00_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_PERI_USI00_USI_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_PERI_USI00_USI_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_PERI_USI01_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI01_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI01_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_PERI_USI01_USI_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_PERI_USI01_USI_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_PERI_USI02_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI02_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI02_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_PERI_USI02_USI_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_PERI_USI02_USI_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_PERI_USI03_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI03_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI03_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_PERI_USI03_USI_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_PERI_USI03_USI_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_PERI_USI04_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI04_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI04_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_PERI_USI04_USI_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_PERI_USI04_USI_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_PERI_USI05_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI05_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI05_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_PERI_USI05_USI_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_PERI_USI05_USI_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_PERI_USI_I2C_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_PERI_UART_DBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_UART_DBG_BUSY, CLK_CON_DIV_DIV_CLK_PERI_UART_DBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_PERI_UART_DBG_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_PERI_UART_DBG_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_PERI_USI06_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI06_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI06_USI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_PERI_USI06_USI_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_PERI_USI06_USI_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_TAA_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_TAA_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_TAA_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_TAA_BUSP_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_TAA_BUSP_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_TNR_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_TNR_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_TNR_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_TNR_BUSP_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_TNR_BUSP_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_VTS_DMIC_IF_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_VTS_DMIC_IF_DIV2_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_VTS_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_BUS_BUSY, CLK_CON_DIV_DIV_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_VTS_BUS_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_VTS_BUS_DEBUG_INFO, CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIVRATIO, CLK_CON_DIV_DIV_VTS_DMIC_AUD_BUSY, CLK_CON_DIV_DIV_VTS_DMIC_AUD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_VTS_DMIC_AUD_OVERRIDE_BY_HCH, DBG_NFO_DIV_VTS_DMIC_AUD_DEBUG_INFO, CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIV2_DIVRATIO, CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIV2_BUSY, CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIV2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIV2_OVERRIDE_BY_HCH, DBG_NFO_DIV_VTS_DMIC_AUD_DIV2_DEBUG_INFO, CLK_CON_DIV_DIV_VTS_SERIAL_LIF_CORE_DIVRATIO, CLK_CON_DIV_DIV_VTS_SERIAL_LIF_CORE_BUSY, CLK_CON_DIV_DIV_VTS_SERIAL_LIF_CORE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_VTS_SERIAL_LIF_CORE_OVERRIDE_BY_HCH, DBG_NFO_DIV_VTS_SERIAL_LIF_CORE_DEBUG_INFO, CLK_CON_DIV_DIV_VTS_SERIAL_LIF_DIVRATIO, CLK_CON_DIV_DIV_VTS_SERIAL_LIF_BUSY, CLK_CON_DIV_DIV_VTS_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_VTS_SERIAL_LIF_OVERRIDE_BY_HCH, DBG_NFO_DIV_VTS_SERIAL_LIF_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CPUCL0_CPU_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_CPUCL1_CPU_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_BUSY, CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_DSU_CLUSTER_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_G3D_BUSD_BUSY, CLK_CON_DIV_DIV_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_G3D_BUSD_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_G3D_BUSD_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_NPU0_BUS_BUSY, CLK_CON_DIV_DIV_CLK_NPU0_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_NPU0_BUS_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_NPU0_BUS_DEBUG_INFO, CLK_CON_DIV_DIV_CLK_NPUS_BUS_BUSY, CLK_CON_DIV_DIV_CLK_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_NPUS_BUS_OVERRIDE_BY_HCH, DBG_NFO_DIV_CLK_NPUS_BUS_DEBUG_INFO, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_D_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_D_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_D_TZPC_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_D_TZPC_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_D_TZPC_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_C_CMGP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_C_CMGP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_C_CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_WLBT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_WLBT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_WL_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_WL_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_WL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_WL_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_WL_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_WL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_CHUB_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_CHUB_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_CHUB_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLKCMU_VTS_RCO_CG_VAL, CLK_CON_GAT_CLKCMU_VTS_RCO_MANUAL, CLK_CON_GAT_CLKCMU_VTS_RCO_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_AP2GNSS_CLK_CG_VAL, CLK_CON_GAT_AP2GNSS_CLK_MANUAL, CLK_CON_GAT_AP2GNSS_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_BT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_BT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_BT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_BT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_BT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_BT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CHUB_PERI_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CHUB_PERI_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CHUB_PERI_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_USI0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_USI0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_USI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLKCMU_CHUB_RCO_CG_VAL, CLK_CON_GAT_CLKCMU_CHUB_RCO_MANUAL, CLK_CON_GAT_CLKCMU_CHUB_RCO_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLKCMU_CMGP_RCO_CG_VAL, CLK_CON_GAT_CLKCMU_CMGP_RCO_MANUAL, CLK_CON_GAT_CLKCMU_CMGP_RCO_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLKCMU_CHUBVTS_RCO_CG_VAL, CLK_CON_GAT_CLKCMU_CHUBVTS_RCO_MANUAL, CLK_CON_GAT_CLKCMU_CHUBVTS_RCO_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_LH_AXI_SI_D_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_LH_AXI_SI_D_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_LH_AXI_SI_D_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_NS_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_NS_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S2_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S2_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S2_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_SPDY_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_SPDY_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_SPDY_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_D_USBAUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_D_USBAUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_D_USBAUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_DBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_DBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKAUD_USB_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKAUD_USB_BUS_MANUAL, CLK_CON_GAT_GATE_CLKAUD_USB_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKAUD_USB_USB20DRD_CG_VAL, CLK_CON_GAT_GATE_CLKAUD_USB_USB20DRD_MANUAL, CLK_CON_GAT_GATE_CLKAUD_USB_USB20DRD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_0_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_0_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_1_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_1_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_2_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_2_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_VGENLITE_AUD_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_VGENLITE_AUD_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_VGENLITE_AUD_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_OSC_SPDY_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_OSC_SPDY_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_OSC_SPDY_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_P_BUSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_P_BUSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_P_BUSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_D_BUSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_D_BUSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_D_BUSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_PERI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_PERI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA_BUSC_IPCLKPORT_ACLK_PDMA0_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA_BUSC_IPCLKPORT_ACLK_PDMA0_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA_BUSC_IPCLKPORT_ACLK_PDMA0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_BUSC_IPCLKPORT_ACLK_PDMA1_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_BUSC_IPCLKPORT_ACLK_PDMA1_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_BUSC_IPCLKPORT_ACLK_PDMA1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSMMU_AXI_D_BUSC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSMMU_AXI_D_BUSC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSMMU_AXI_D_BUSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_PDMA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_PDMA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_PDMA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_P_BUSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_P_BUSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_P_BUSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_D_TZPC_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_D_TZPC_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_D_TZPC_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_SPDMA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_SPDMA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_SPDMA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_SR_CLK_BUSC_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_SR_CLK_BUSC_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_SR_CLK_BUSC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUBEINT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUBEINT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUBEINT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_SI_M_CHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_SI_M_CHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_SI_M_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_MI_S_CHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_MI_S_CHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_MI_S_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_LH_AXI_SI_D_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_LH_AXI_SI_D_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_LH_AXI_SI_D_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_CHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_CHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_C_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_C_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_C_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_CHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_CHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SWEEPER_C_CHUBVTS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SWEEPER_C_CHUBVTS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SWEEPER_C_CHUBVTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BPS_LP_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BPS_LP_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BPS_LP_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SLH_AXI_MI_C_CMGP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SLH_AXI_MI_C_CMGP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SLH_AXI_MI_C_CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI4_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI4_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLKCMU_MIF_SWITCH_CG_VAL, CLK_CON_GAT_CLKCMU_MIF_SWITCH_MANUAL, CLK_CON_GAT_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_HSI_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_PERI_MMC_CARD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_MMC_CARD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_TAA_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_TAA_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_MANUAL, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_M2M_MSCL_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_M2M_MSCL_MANUAL, CLK_CON_GAT_GATE_CLKCMU_M2M_MSCL_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_HSI_UFS_EMBD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI_UFS_EMBD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_NPU0_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_NPU0_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_NPU0_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_PERI_IP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_IP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_USB_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_USB_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_TNR_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_TNR_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_TNR_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_G3D_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3D_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3D_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_USB_USB20DRD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_USB_USB20DRD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_USB_USB20DRD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_AP2CP_SHARED0_CLK_CG_VAL, CLK_CON_GAT_AP2CP_SHARED0_CLK_MANUAL, CLK_CON_GAT_AP2CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_AP2CP_SHARED1_CLK_CG_VAL, CLK_CON_GAT_AP2CP_SHARED1_CLK_MANUAL, CLK_CON_GAT_AP2CP_SHARED1_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CORE_SSS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CORE_SSS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CORE_SSS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_AP2CP_SHARED2_CLK_CG_VAL, CLK_CON_GAT_AP2CP_SHARED2_CLK_MANUAL, CLK_CON_GAT_AP2CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_AP2CP_HISPEEDY_CLK_CG_VAL, CLK_CON_GAT_AP2CP_HISPEEDY_CLK_MANUAL, CLK_CON_GAT_AP2CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_DPU_DSIM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DPU_DSIM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DPU_DSIM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GATE_CLKCMU_AUD_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_AUD_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_HSI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_HSI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_HSI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_WLBT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_WLBT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_WLBT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_WLBT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_HSI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_HSI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_HSI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_PERI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_PERI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_SSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_SSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_SSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_SSS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_SSS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_SSS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D_DIT_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D_DIT_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D_DIT_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D_SSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D_SSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D_SSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_PUF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PUF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_RT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_RT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_BUSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_BUSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_BUSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_D_SSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_D_SSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_D_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_G_BDU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_G_BDU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_G_BDU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D2_MODEM_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D2_MODEM_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D2_MODEM_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_I_ARESETN_SSS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_I_ARESETN_SSS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_I_ARESETN_SSS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AST_MI_G_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AST_MI_G_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AST_MI_G_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_P_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_P_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_P_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_CORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_CORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_VGEN_LITE_CORE_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_VGEN_LITE_CORE_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_VGEN_LITE_CORE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_M2M_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_M2M_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_CORECLK_AN_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_CORECLK_AN_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_CORECLK_AN_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CORECLK_HC_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CORECLK_HC_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CORECLK_HC_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF0_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF0_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF0_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF1_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF1_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF1_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D3_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D3_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D3_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF2_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF2_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF2_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE0_CSIS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE0_CSIS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE0_CSIS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE1_CSIS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE1_CSIS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE1_CSIS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE2_CSIS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE2_CSIS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE2_CSIS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DECON_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DECON_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DECON_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DPP_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DPP_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DPP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_C2SERV_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_C2SERV_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_C2SERV_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_IPCLKPORT_I_NEWCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_IPCLKPORT_I_NEWCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_IPCLKPORT_I_NEWCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_SR_CLK_DPU_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_SR_CLK_DPU_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_SR_CLK_DPU_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_XIU_D_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_XIU_D_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_XIU_D_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D0_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D0_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D0_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D1_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D1_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D1_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AST_SI_G_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AST_SI_G_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AST_SI_G_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_D_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_D_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_D_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_SYSMMU_D_G3D_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_SYSMMU_D_G3D_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_SYSMMU_D_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSMMU_D_G3D_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSMMU_D_G3D_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSMMU_D_G3D_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_D0_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_D0_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_D0_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_VGENLITE_G3D_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_VGENLITE_G3D_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_VGENLITE_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_HSI_UID_VGEN_LITE_HSI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_VGEN_LITE_HSI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_VGEN_LITE_HSI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_HSI_UID_HSI_CMU_HSI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_HSI_CMU_HSI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_HSI_CMU_HSI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_SI_D_HSI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_SI_D_HSI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_SI_D_HSI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_MI_P_HSI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_MI_P_HSI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_MI_P_HSI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_HSI_UID_D_TZPC_HSI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_D_TZPC_HSI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_D_TZPC_HSI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_HSI_UID_S2MPU_D_HSI_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_S2MPU_D_HSI_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_S2MPU_D_HSI_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_UFS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_UFS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_SR_CLK_HSI_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_SR_CLK_HSI_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_SR_CLK_HSI_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_D_TZPC_ISP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_D_TZPC_ISP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_D_TZPC_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_ISP_UID_LH_AXI_SI_D_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_LH_AXI_SI_D_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_LH_AXI_SI_D_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_ITP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_ITP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_ITP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_ITP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_ITP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_ITP_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_DNS_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_DNS_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_DNS_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF_TAAISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF_TAAISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF_TAAISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_SI_OTF_ISPMCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_SI_OTF_ISPMCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_SI_OTF_ISPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF0_TNRISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF0_TNRISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF0_TNRISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF1_TNRISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF1_TNRISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF1_TNRISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_XIU_D_ISP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_XIU_D_ISP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_XIU_D_ISP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_VGEN_LITE_ISP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_VGEN_LITE_ISP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_VGEN_LITE_ISP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_ISP_UID_VGEN_LITE_ISP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_VGEN_LITE_ISP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_VGEN_LITE_ISP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_SLH_AXI_MI_P_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SLH_AXI_MI_P_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SLH_AXI_MI_P_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_SR_CLK_ISP_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_SR_CLK_ISP_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_SR_CLK_ISP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_JPEG0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_JPEG0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_JPEG0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_M2M_UID_LH_AXI_SI_D_M2M_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_LH_AXI_SI_D_M2M_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_LH_AXI_SI_D_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_VGEN_LITE_M2M_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_VGEN_LITE_M2M_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_VGEN_LITE_M2M_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_GDC_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_GDC_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_GDC_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D3_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D3_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D3_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_TAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_TAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_OTF_ISPMCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_OTF_ISPMCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_OTF_ISPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_C2CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_C2CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_SYSMMU_D0_MCSC_NS_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_SYSMMU_D0_MCSC_NS_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_SYSMMU_D0_MCSC_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_MCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_MCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_GDC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_GDC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_SR_CLK_MFC_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_SR_CLK_MFC_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_SR_CLK_MFC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MFC_UID_VGEN_LITE_MFC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_VGEN_LITE_MFC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_VGEN_LITE_MFC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDRPHY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDRPHY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_RT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_NPU0_UID_NPU0_CMU_NPU0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPU0_UID_NPU0_CMU_NPU0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPU0_UID_NPU0_CMU_NPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPU0_UID_D_TZPC_NPU0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_D_TZPC_NPU0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_D_TZPC_NPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SYSREG_NPU0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SYSREG_NPU0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SYSREG_NPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SLH_AXI_MI_P_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SLH_AXI_MI_P_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SLH_AXI_MI_P_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D_CTRL_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D_CTRL_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D_CTRL_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D0_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D0_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D0_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_RQ_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_RQ_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_RQ_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_CMDQ_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_CMDQ_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_CMDQ_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D1_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D1_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D1_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_RQ_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_RQ_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_RQ_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D_CTRL_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D_CTRL_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D_CTRL_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_CMDQ_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_CMDQ_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_CMDQ_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_0_IPCLKPORT_MAINCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_0_IPCLKPORT_MAINCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_0_IPCLKPORT_MAINCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_1_IPCLKPORT_MAINCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_1_IPCLKPORT_MAINCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_1_IPCLKPORT_MAINCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_INT_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_INT_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_INT_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_SI_P_INT_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_SI_P_INT_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_SI_P_INT_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_SR_CLK_NPUS_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_SR_CLK_NPUS_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_SR_CLK_NPUS_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI01_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI01_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI01_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI02_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI02_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI02_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI03_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI03_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI03_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI04_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI04_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI04_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI05_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI05_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI05_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_DBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_DBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_MI_P_PERI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_MI_P_PERI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_MI_P_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_XIU_P_PERI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_XIU_P_PERI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_XIU_P_PERI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_TMU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_TMU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_TMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_IPCLKPORT_I_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_IPCLKPORT_I_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_VGEN_LITE_PERI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_VGEN_LITE_PERI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_VGEN_LITE_PERI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_S2MPU_D_PERI_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_S2MPU_D_PERI_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_S2MPU_D_PERI_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_SI_D_PERI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_SI_D_PERI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_SI_D_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERIMMC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERIMMC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERIMMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI06_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI06_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI06_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_SR_CLK_PERI_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_SR_CLK_PERI_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_SR_CLK_PERI_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AXI_SI_D_TAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AXI_SI_D_TAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AXI_SI_D_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_SLH_AXI_MI_P_TAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SLH_AXI_MI_P_TAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SLH_AXI_MI_P_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_OTF_TAAISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_OTF_TAAISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_OTF_TAAISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF0_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF0_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF0_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF1_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF1_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF1_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF2_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF2_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF2_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE0_TAA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE0_TAA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE0_TAA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE1_TAA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE1_TAA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE1_TAA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_SR_CLK_TAA_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_SR_CLK_TAA_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_SR_CLK_TAA_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_TNR_0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_TNR_0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_TNR_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP0_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP0_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF0_TNRISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF0_TNRISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF0_TNRISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF1_TNRISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF1_TNRISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF1_TNRISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP1_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP1_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_VGEN_LITE_D_TNR_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_VGEN_LITE_D_TNR_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_VGEN_LITE_D_TNR_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_SR_CLK_TNR_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_SR_CLK_TNR_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_SR_CLK_TNR_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_26_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_26_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_26_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_VGEN_LITE_USB_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_VGEN_LITE_USB_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_VGEN_LITE_USB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_D_TZPC_USB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_D_TZPC_USB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_D_TZPC_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_MI_P_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_MI_P_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_MI_P_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_S2MPU_D_USB_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_S2MPU_D_USB_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_S2MPU_D_USB_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_ACLK_PHYCTRL_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_ACLK_PHYCTRL_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_ACLK_PHYCTRL_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_BUS_CLK_EARLY_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_BUS_CLK_EARLY_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_BUS_CLK_EARLY_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_XIU_D_USB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_XIU_D_USB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_XIU_D_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USBAUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USBAUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USBAUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_URAM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_URAM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_URAM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_SR_CLK_USB_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_SR_CLK_USB_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_SR_CLK_USB_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_VTS_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_VTS_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_VTS_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_CM4_VTS_IPCLKPORT_FCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_CM4_VTS_IPCLKPORT_FCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_CM4_VTS_IPCLKPORT_FCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_MI_S_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_MI_S_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_MI_S_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_SI_M_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_SI_M_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_SI_M_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_SCAN_MUX_IPCLKPORT_D0_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_SCAN_MUX_IPCLKPORT_D0_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_SCAN_MUX_IPCLKPORT_D0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_AXI2AHB_VTS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_AXI2AHB_VTS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_AXI2AHB_VTS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB2AXI_VTS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB2AXI_VTS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB2AXI_VTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_BCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_BCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_BCLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_DIV_CLK_MIF_BUSD_ENABLE_AUTOMATIC_CLKGATING, CLK_CON_DIV_CLK_MIF_BUSD_S2D_ENABLE_AUTOMATIC_CLKGATING, QCH_CON_ALIVE_CMU_ALIVE_QCH_ENABLE, QCH_CON_ALIVE_CMU_ALIVE_QCH_CLOCK_REQ, QCH_CON_ALIVE_CMU_ALIVE_QCH_EXPIRE_VAL, QCH_CON_ALIVE_CMU_ALIVE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_APBIF_CHUB_RTC_QCH_ENABLE, QCH_CON_APBIF_CHUB_RTC_QCH_CLOCK_REQ, QCH_CON_APBIF_CHUB_RTC_QCH_EXPIRE_VAL, QCH_CON_APBIF_CHUB_RTC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_APBIF_GPIO_ALIVE_QCH_ENABLE, QCH_CON_APBIF_GPIO_ALIVE_QCH_CLOCK_REQ, QCH_CON_APBIF_GPIO_ALIVE_QCH_EXPIRE_VAL, QCH_CON_APBIF_GPIO_ALIVE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE, QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ, QCH_CON_APBIF_PMU_ALIVE_QCH_EXPIRE_VAL, QCH_CON_APBIF_PMU_ALIVE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_APBIF_RTC_QCH_ENABLE, QCH_CON_APBIF_RTC_QCH_CLOCK_REQ, QCH_CON_APBIF_RTC_QCH_EXPIRE_VAL, QCH_CON_APBIF_RTC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_ENABLE, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_CLOCK_REQ, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_EXPIRE_VAL, QCH_CON_APBIF_SYSREG_VGPIO2AP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_ENABLE, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_CLOCK_REQ, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_EXPIRE_VAL, QCH_CON_APBIF_SYSREG_VGPIO2APM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_ENABLE, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_CLOCK_REQ, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_EXPIRE_VAL, QCH_CON_APBIF_SYSREG_VGPIO2PMU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_APBIF_TOP_RTC_QCH_ENABLE, QCH_CON_APBIF_TOP_RTC_QCH_CLOCK_REQ, QCH_CON_APBIF_TOP_RTC_QCH_EXPIRE_VAL, QCH_CON_APBIF_TOP_RTC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_DBGCORE_UART_QCH_ENABLE, QCH_CON_DBGCORE_UART_QCH_CLOCK_REQ, QCH_CON_DBGCORE_UART_QCH_EXPIRE_VAL, QCH_CON_DBGCORE_UART_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_ALIVE_QCH_ENABLE, QCH_CON_D_TZPC_ALIVE_QCH_CLOCK_REQ, QCH_CON_D_TZPC_ALIVE_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_ALIVE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_GREBEINTEGRATION_QCH_GREBE_ENABLE, QCH_CON_GREBEINTEGRATION_QCH_GREBE_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_QCH_GREBE_EXPIRE_VAL, QCH_CON_GREBEINTEGRATION_QCH_GREBE_IGNORE_FORCE_PM_EN, QCH_CON_GREBEINTEGRATION_QCH_DBG_ENABLE, QCH_CON_GREBEINTEGRATION_QCH_DBG_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_QCH_DBG_EXPIRE_VAL, QCH_CON_GREBEINTEGRATION_QCH_DBG_IGNORE_FORCE_PM_EN, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_ENABLE, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_CLOCK_REQ, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_EXPIRE_VAL, QCH_CON_HW_SCANDUMP_CLKSTOP_CTRL_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_ALIVE0_QCH_ENABLE, QCH_CON_I2C_ALIVE0_QCH_CLOCK_REQ, QCH_CON_I2C_ALIVE0_QCH_EXPIRE_VAL, QCH_CON_I2C_ALIVE0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I3C_APM_PMIC_QCH_P_ENABLE, QCH_CON_I3C_APM_PMIC_QCH_P_CLOCK_REQ, QCH_CON_I3C_APM_PMIC_QCH_P_EXPIRE_VAL, QCH_CON_I3C_APM_PMIC_QCH_P_IGNORE_FORCE_PM_EN, QCH_CON_I3C_APM_PMIC_QCH_S_ENABLE, QCH_CON_I3C_APM_PMIC_QCH_S_CLOCK_REQ, QCH_CON_I3C_APM_PMIC_QCH_S_EXPIRE_VAL, QCH_CON_I3C_APM_PMIC_QCH_S_IGNORE_FORCE_PM_EN, QCH_CON_INTMEM_QCH_ENABLE, QCH_CON_INTMEM_QCH_CLOCK_REQ, QCH_CON_INTMEM_QCH_EXPIRE_VAL, QCH_CON_INTMEM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_APM_AP_QCH_ENABLE, QCH_CON_MAILBOX_APM_AP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_AP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_AP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_APM_CHUB_QCH_ENABLE, QCH_CON_MAILBOX_APM_CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_CHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_CHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_APM_CP_QCH_ENABLE, QCH_CON_MAILBOX_APM_CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_CP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_CP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_APM_GNSS_QCH_ENABLE, QCH_CON_MAILBOX_APM_GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_GNSS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_GNSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_APM_VTS_QCH_ENABLE, QCH_CON_MAILBOX_APM_VTS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_VTS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_VTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_APM_WLBT_QCH_ENABLE, QCH_CON_MAILBOX_APM_WLBT_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_WLBT_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_WLBT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_AP_CHUB_QCH_ENABLE, QCH_CON_MAILBOX_AP_CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_CHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_CHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_AP_CP_QCH_ENABLE, QCH_CON_MAILBOX_AP_CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_CP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_CP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_AP_CP_S_QCH_ENABLE, QCH_CON_MAILBOX_AP_CP_S_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_CP_S_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_CP_S_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_AP_DBGCORE_QCH_ENABLE, QCH_CON_MAILBOX_AP_DBGCORE_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_DBGCORE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_AP_GNSS_QCH_ENABLE, QCH_CON_MAILBOX_AP_GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_GNSS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_GNSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_AP_WLBT_BT_QCH_ENABLE, QCH_CON_MAILBOX_AP_WLBT_BT_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_WLBT_BT_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_WLBT_BT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_AP_WLBT_WL_QCH_ENABLE, QCH_CON_MAILBOX_AP_WLBT_WL_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_WLBT_WL_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_WLBT_WL_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_CP_CHUB_QCH_ENABLE, QCH_CON_MAILBOX_CP_CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_CP_CHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_CP_CHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_CP_GNSS_QCH_ENABLE, QCH_CON_MAILBOX_CP_GNSS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_CP_GNSS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_CP_GNSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_CP_WLBT_BT_QCH_ENABLE, QCH_CON_MAILBOX_CP_WLBT_BT_QCH_CLOCK_REQ, QCH_CON_MAILBOX_CP_WLBT_BT_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_CP_WLBT_BT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_CP_WLBT_WL_QCH_ENABLE, QCH_CON_MAILBOX_CP_WLBT_WL_QCH_CLOCK_REQ, QCH_CON_MAILBOX_CP_WLBT_WL_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_CP_WLBT_WL_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_GNSS_CHUB_QCH_ENABLE, QCH_CON_MAILBOX_GNSS_CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_GNSS_CHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_GNSS_CHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_GNSS_WLBT_QCH_ENABLE, QCH_CON_MAILBOX_GNSS_WLBT_QCH_CLOCK_REQ, QCH_CON_MAILBOX_GNSS_WLBT_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_GNSS_WLBT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_SHARED_SRAM_QCH_ENABLE, QCH_CON_MAILBOX_SHARED_SRAM_QCH_CLOCK_REQ, QCH_CON_MAILBOX_SHARED_SRAM_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_SHARED_SRAM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_VTS_CHUB_QCH_ENABLE, QCH_CON_MAILBOX_VTS_CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_VTS_CHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_VTS_CHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_WLBT_ABOX_QCH_ENABLE, QCH_CON_MAILBOX_WLBT_ABOX_QCH_CLOCK_REQ, QCH_CON_MAILBOX_WLBT_ABOX_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_WLBT_ABOX_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_WLBT_CHUB_QCH_ENABLE, QCH_CON_MAILBOX_WLBT_CHUB_QCH_CLOCK_REQ, QCH_CON_MAILBOX_WLBT_CHUB_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_WLBT_CHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PMU_INTR_GEN_QCH_ENABLE, QCH_CON_PMU_INTR_GEN_QCH_CLOCK_REQ, QCH_CON_PMU_INTR_GEN_QCH_EXPIRE_VAL, QCH_CON_PMU_INTR_GEN_QCH_IGNORE_FORCE_PM_EN, QCH_CON_ROM_CRC32_HOST_QCH_ENABLE, QCH_CON_ROM_CRC32_HOST_QCH_CLOCK_REQ, QCH_CON_ROM_CRC32_HOST_QCH_EXPIRE_VAL, QCH_CON_ROM_CRC32_HOST_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_C_CHUBVTS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_C_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_C_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_C_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_C_GNSS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_C_GNSS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_C_GNSS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_C_GNSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_C_MODEM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_C_MODEM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_C_MODEM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_C_MODEM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_C_WLBT_QCH_ENABLE, QCH_CON_SLH_AXI_MI_C_WLBT_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_C_WLBT_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_C_WLBT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_APM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_APM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_APM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_APM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_C_CMGP_QCH_ENABLE, QCH_CON_SLH_AXI_SI_C_CMGP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_C_CMGP_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_C_CMGP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_D_APM_QCH_ENABLE, QCH_CON_SLH_AXI_SI_D_APM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_D_APM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_D_APM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_ENABLE, QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_ENABLE, QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_LP_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SS_DBGCORE_QCH_GREBE_ENABLE, QCH_CON_SS_DBGCORE_QCH_GREBE_CLOCK_REQ, QCH_CON_SS_DBGCORE_QCH_GREBE_EXPIRE_VAL, QCH_CON_SS_DBGCORE_QCH_GREBE_IGNORE_FORCE_PM_EN, QCH_CON_SS_DBGCORE_QCH_DBG_ENABLE, QCH_CON_SS_DBGCORE_QCH_DBG_CLOCK_REQ, QCH_CON_SS_DBGCORE_QCH_DBG_EXPIRE_VAL, QCH_CON_SS_DBGCORE_QCH_DBG_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_ALIVE_QCH_ENABLE, QCH_CON_SYSREG_ALIVE_QCH_CLOCK_REQ, QCH_CON_SYSREG_ALIVE_QCH_EXPIRE_VAL, QCH_CON_SYSREG_ALIVE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI_ALIVE0_QCH_ENABLE, QCH_CON_USI_ALIVE0_QCH_CLOCK_REQ, QCH_CON_USI_ALIVE0_QCH_EXPIRE_VAL, QCH_CON_USI_ALIVE0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE_ALIVE_QCH_ENABLE, QCH_CON_VGEN_LITE_ALIVE_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_ALIVE_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_ALIVE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_WDT_ALIVE_QCH_ENABLE, QCH_CON_WDT_ALIVE_QCH_CLOCK_REQ, QCH_CON_WDT_ALIVE_QCH_EXPIRE_VAL, QCH_CON_WDT_ALIVE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_ACLK_ENABLE, QCH_CON_ABOX_QCH_ACLK_CLOCK_REQ, QCH_CON_ABOX_QCH_ACLK_EXPIRE_VAL, QCH_CON_ABOX_QCH_ACLK_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_BCLK_DSIF_ENABLE, QCH_CON_ABOX_QCH_BCLK_DSIF_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK_DSIF_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK_DSIF_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_BCLK0_ENABLE, QCH_CON_ABOX_QCH_BCLK0_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK0_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK0_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_BCLK1_ENABLE, QCH_CON_ABOX_QCH_BCLK1_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK1_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK1_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_BCLK2_ENABLE, QCH_CON_ABOX_QCH_BCLK2_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK2_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK2_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_BCLK3_ENABLE, QCH_CON_ABOX_QCH_BCLK3_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK3_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK3_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_BCLK4_ENABLE, QCH_CON_ABOX_QCH_BCLK4_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK4_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK4_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_CNT_ENABLE, QCH_CON_ABOX_QCH_CNT_CLOCK_REQ, QCH_CON_ABOX_QCH_CNT_EXPIRE_VAL, QCH_CON_ABOX_QCH_CNT_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_CCLK_ASB_ENABLE, QCH_CON_ABOX_QCH_CCLK_ASB_CLOCK_REQ, QCH_CON_ABOX_QCH_CCLK_ASB_EXPIRE_VAL, QCH_CON_ABOX_QCH_CCLK_ASB_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_BCLK5_ENABLE, QCH_CON_ABOX_QCH_BCLK5_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK5_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK5_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_BCLK6_ENABLE, QCH_CON_ABOX_QCH_BCLK6_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK6_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK6_IGNORE_FORCE_PM_EN, DMYQCH_CON_ABOX_QCH_CPU_ENABLE, DMYQCH_CON_ABOX_QCH_CPU_CLOCK_REQ, DMYQCH_CON_ABOX_QCH_CPU_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_PCMC_CLK_ENABLE, QCH_CON_ABOX_QCH_PCMC_CLK_CLOCK_REQ, QCH_CON_ABOX_QCH_PCMC_CLK_EXPIRE_VAL, QCH_CON_ABOX_QCH_PCMC_CLK_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_C2A0_ENABLE, QCH_CON_ABOX_QCH_C2A0_CLOCK_REQ, QCH_CON_ABOX_QCH_C2A0_EXPIRE_VAL, QCH_CON_ABOX_QCH_C2A0_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_C2A1_ENABLE, QCH_CON_ABOX_QCH_C2A1_CLOCK_REQ, QCH_CON_ABOX_QCH_C2A1_EXPIRE_VAL, QCH_CON_ABOX_QCH_C2A1_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_XCLK0_ENABLE, QCH_CON_ABOX_QCH_XCLK0_CLOCK_REQ, QCH_CON_ABOX_QCH_XCLK0_EXPIRE_VAL, QCH_CON_ABOX_QCH_XCLK0_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_XCLK1_ENABLE, QCH_CON_ABOX_QCH_XCLK1_CLOCK_REQ, QCH_CON_ABOX_QCH_XCLK1_EXPIRE_VAL, QCH_CON_ABOX_QCH_XCLK1_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_XCLK2_ENABLE, QCH_CON_ABOX_QCH_XCLK2_CLOCK_REQ, QCH_CON_ABOX_QCH_XCLK2_EXPIRE_VAL, QCH_CON_ABOX_QCH_XCLK2_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_CPU0_ENABLE, QCH_CON_ABOX_QCH_CPU0_CLOCK_REQ, QCH_CON_ABOX_QCH_CPU0_EXPIRE_VAL, QCH_CON_ABOX_QCH_CPU0_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_CPU1_ENABLE, QCH_CON_ABOX_QCH_CPU1_CLOCK_REQ, QCH_CON_ABOX_QCH_CPU1_EXPIRE_VAL, QCH_CON_ABOX_QCH_CPU1_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_NEON0_ENABLE, QCH_CON_ABOX_QCH_NEON0_CLOCK_REQ, QCH_CON_ABOX_QCH_NEON0_EXPIRE_VAL, QCH_CON_ABOX_QCH_NEON0_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_NEON1_ENABLE, QCH_CON_ABOX_QCH_NEON1_CLOCK_REQ, QCH_CON_ABOX_QCH_NEON1_EXPIRE_VAL, QCH_CON_ABOX_QCH_NEON1_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_L2_ENABLE, QCH_CON_ABOX_QCH_L2_CLOCK_REQ, QCH_CON_ABOX_QCH_L2_EXPIRE_VAL, QCH_CON_ABOX_QCH_L2_IGNORE_FORCE_PM_EN, QCH_CON_ABOX_QCH_CCLK_ACP_ENABLE, QCH_CON_ABOX_QCH_CCLK_ACP_CLOCK_REQ, QCH_CON_ABOX_QCH_CCLK_ACP_EXPIRE_VAL, QCH_CON_ABOX_QCH_CCLK_ACP_IGNORE_FORCE_PM_EN, QCH_CON_AUD_CMU_AUD_QCH_ENABLE, QCH_CON_AUD_CMU_AUD_QCH_CLOCK_REQ, QCH_CON_AUD_CMU_AUD_QCH_EXPIRE_VAL, QCH_CON_AUD_CMU_AUD_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_DFTMUX_AUD_QCH_ENABLE, DMYQCH_CON_DFTMUX_AUD_QCH_CLOCK_REQ, DMYQCH_CON_DFTMUX_AUD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_AUD_QCH_ENABLE, QCH_CON_D_TZPC_AUD_QCH_CLOCK_REQ, QCH_CON_D_TZPC_AUD_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_AUD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D_AUD_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_AUD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_AUD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_AUD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_AUD0_QCH_ENABLE, QCH_CON_MAILBOX_AUD0_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AUD0_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AUD0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_AUD1_QCH_ENABLE, QCH_CON_MAILBOX_AUD1_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AUD1_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AUD1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_AUD_QCH_ENABLE, QCH_CON_PPMU_AUD_QCH_CLOCK_REQ, QCH_CON_PPMU_AUD_QCH_EXPIRE_VAL, QCH_CON_PPMU_AUD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_D_USBAUD_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D_USBAUD_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D_USBAUD_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_D_USBAUD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_AUD_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_AUD_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_AUD_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_AUD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_AUD_QCH_S1_ENABLE, QCH_CON_SYSMMU_AUD_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_AUD_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_AUD_QCH_S1_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_AUD_QCH_S2_ENABLE, QCH_CON_SYSMMU_AUD_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_AUD_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_AUD_QCH_S2_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_AUD_QCH_ENABLE, QCH_CON_SYSREG_AUD_QCH_CLOCK_REQ, QCH_CON_SYSREG_AUD_QCH_EXPIRE_VAL, QCH_CON_SYSREG_AUD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE_AUD_QCH_ENABLE, QCH_CON_VGEN_LITE_AUD_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_AUD_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_AUD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_WDT_AUD_QCH_ENABLE, QCH_CON_WDT_AUD_QCH_CLOCK_REQ, QCH_CON_WDT_AUD_QCH_EXPIRE_VAL, QCH_CON_WDT_AUD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_BUSC_CMU_BUSC_QCH_ENABLE, QCH_CON_BUSC_CMU_BUSC_QCH_CLOCK_REQ, QCH_CON_BUSC_CMU_BUSC_QCH_EXPIRE_VAL, QCH_CON_BUSC_CMU_BUSC_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_CMU_BUSC_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_BUSC_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_BUSC_CMUREF_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_BUSC_QCH_ENABLE, QCH_CON_D_TZPC_BUSC_QCH_CLOCK_REQ, QCH_CON_D_TZPC_BUSC_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_BUSC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D_CHUBVTS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D_MFC_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_MFC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_MFC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_MFC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PDMA_BUSC_QCH_ENABLE, QCH_CON_PDMA_BUSC_QCH_CLOCK_REQ, QCH_CON_PDMA_BUSC_QCH_EXPIRE_VAL, QCH_CON_PDMA_BUSC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_D_APM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D_APM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D_APM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_D_APM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_D_PERI_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D_PERI_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D_PERI_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_D_PERI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_D_USB_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D_USB_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D_USB_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_D_USB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_BUSC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_BUSC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_BUSC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_BUSC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SPDMA_BUSC_QCH_ENABLE, QCH_CON_SPDMA_BUSC_QCH_CLOCK_REQ, QCH_CON_SPDMA_BUSC_QCH_EXPIRE_VAL, QCH_CON_SPDMA_BUSC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_AXI_D_BUSC_QCH_ENABLE, QCH_CON_SYSMMU_AXI_D_BUSC_QCH_CLOCK_REQ, QCH_CON_SYSMMU_AXI_D_BUSC_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_AXI_D_BUSC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_BUSC_QCH_ENABLE, QCH_CON_SYSREG_BUSC_QCH_CLOCK_REQ, QCH_CON_SYSREG_BUSC_QCH_EXPIRE_VAL, QCH_CON_SYSREG_BUSC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_TREX_D_BUSC_QCH_ENABLE, QCH_CON_TREX_D_BUSC_QCH_CLOCK_REQ, QCH_CON_TREX_D_BUSC_QCH_EXPIRE_VAL, QCH_CON_TREX_D_BUSC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_PDMA_QCH_ENABLE, QCH_CON_VGEN_PDMA_QCH_CLOCK_REQ, QCH_CON_VGEN_PDMA_QCH_EXPIRE_VAL, QCH_CON_VGEN_PDMA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_SPDMA_QCH_ENABLE, QCH_CON_VGEN_SPDMA_QCH_CLOCK_REQ, QCH_CON_VGEN_SPDMA_QCH_EXPIRE_VAL, QCH_CON_VGEN_SPDMA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_ENABLE, QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_CLOCK_REQ, QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_EXPIRE_VAL, QCH_CON_APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_APBIF_GPIO_CHUB_QCH_ENABLE, QCH_CON_APBIF_GPIO_CHUB_QCH_CLOCK_REQ, QCH_CON_APBIF_GPIO_CHUB_QCH_EXPIRE_VAL, QCH_CON_APBIF_GPIO_CHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_APBIF_GPIO_CHUBEINT_QCH_ENABLE, QCH_CON_APBIF_GPIO_CHUBEINT_QCH_CLOCK_REQ, QCH_CON_APBIF_GPIO_CHUBEINT_QCH_EXPIRE_VAL, QCH_CON_APBIF_GPIO_CHUBEINT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CHUB_CMU_CHUB_QCH_ENABLE, QCH_CON_CHUB_CMU_CHUB_QCH_CLOCK_REQ, QCH_CON_CHUB_CMU_CHUB_QCH_EXPIRE_VAL, QCH_CON_CHUB_CMU_CHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CM4_CHUB_QCH_CPU_ENABLE, QCH_CON_CM4_CHUB_QCH_CPU_CLOCK_REQ, QCH_CON_CM4_CHUB_QCH_CPU_EXPIRE_VAL, QCH_CON_CM4_CHUB_QCH_CPU_IGNORE_FORCE_PM_EN, QCH_CON_I2C_CHUB1_QCH_ENABLE, QCH_CON_I2C_CHUB1_QCH_CLOCK_REQ, QCH_CON_I2C_CHUB1_QCH_EXPIRE_VAL, QCH_CON_I2C_CHUB1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_CHUB3_QCH_ENABLE, QCH_CON_I2C_CHUB3_QCH_CLOCK_REQ, QCH_CON_I2C_CHUB3_QCH_EXPIRE_VAL, QCH_CON_I2C_CHUB3_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PWM_CHUB_QCH_ENABLE, QCH_CON_PWM_CHUB_QCH_CLOCK_REQ, QCH_CON_PWM_CHUB_QCH_EXPIRE_VAL, QCH_CON_PWM_CHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_S_CHUB_QCH_ENABLE, QCH_CON_SLH_AXI_MI_S_CHUB_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_S_CHUB_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_S_CHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_M_CHUB_QCH_ENABLE, QCH_CON_SLH_AXI_SI_M_CHUB_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_M_CHUB_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_M_CHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CHUB_QCH_ENABLE, QCH_CON_SYSREG_CHUB_QCH_CLOCK_REQ, QCH_CON_SYSREG_CHUB_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_ENABLE, QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_CLOCK_REQ, QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_COMBINE_CHUB2AP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_ENABLE, QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_CLOCK_REQ, QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_EXPIRE_VAL, QCH_CON_SYSREG_COMBINE_CHUB2APM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_COMBINE_CHUB2WLBT_QCH_ENABLE, QCH_CON_SYSREG_COMBINE_CHUB2WLBT_QCH_CLOCK_REQ, QCH_CON_SYSREG_COMBINE_CHUB2WLBT_QCH_EXPIRE_VAL, QCH_CON_SYSREG_COMBINE_CHUB2WLBT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_TIMER_CHUB_QCH_ENABLE, QCH_CON_TIMER_CHUB_QCH_CLOCK_REQ, QCH_CON_TIMER_CHUB_QCH_EXPIRE_VAL, QCH_CON_TIMER_CHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI_CHUB0_QCH_ENABLE, QCH_CON_USI_CHUB0_QCH_CLOCK_REQ, QCH_CON_USI_CHUB0_QCH_EXPIRE_VAL, QCH_CON_USI_CHUB0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI_CHUB1_QCH_ENABLE, QCH_CON_USI_CHUB1_QCH_CLOCK_REQ, QCH_CON_USI_CHUB1_QCH_EXPIRE_VAL, QCH_CON_USI_CHUB1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI_CHUB2_QCH_ENABLE, QCH_CON_USI_CHUB2_QCH_CLOCK_REQ, QCH_CON_USI_CHUB2_QCH_EXPIRE_VAL, QCH_CON_USI_CHUB2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI_CHUB3_QCH_ENABLE, QCH_CON_USI_CHUB3_QCH_CLOCK_REQ, QCH_CON_USI_CHUB3_QCH_EXPIRE_VAL, QCH_CON_USI_CHUB3_QCH_IGNORE_FORCE_PM_EN, QCH_CON_WDT_CHUB_QCH_ENABLE, QCH_CON_WDT_CHUB_QCH_CLOCK_REQ, QCH_CON_WDT_CHUB_QCH_EXPIRE_VAL, QCH_CON_WDT_CHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_BAAW_CHUB_QCH_ENABLE, QCH_CON_BAAW_CHUB_QCH_CLOCK_REQ, QCH_CON_BAAW_CHUB_QCH_EXPIRE_VAL, QCH_CON_BAAW_CHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_BAAW_VTS_QCH_ENABLE, QCH_CON_BAAW_VTS_QCH_CLOCK_REQ, QCH_CON_BAAW_VTS_QCH_EXPIRE_VAL, QCH_CON_BAAW_VTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_ENABLE, QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_CHUBVTS_CMU_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_CHUBVTS_QCH_ENABLE, QCH_CON_D_TZPC_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D_CHUBVTS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_LP_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_M_CHUB_QCH_ENABLE, QCH_CON_SLH_AXI_MI_M_CHUB_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_M_CHUB_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_M_CHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_M_VTS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_M_VTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_M_VTS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_M_VTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_C_CHUBVTS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_C_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_C_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_C_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_S_CHUB_QCH_ENABLE, QCH_CON_SLH_AXI_SI_S_CHUB_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_S_CHUB_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_S_CHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_S_VTS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_S_VTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_S_VTS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_S_VTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SWEEPER_C_CHUBVTS_QCH_ENABLE, QCH_CON_SWEEPER_C_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_SWEEPER_C_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_SWEEPER_C_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CHUBVTS_QCH_ENABLE, QCH_CON_SYSREG_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_SYSREG_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE_CHUBVTS_QCH_ENABLE, QCH_CON_VGEN_LITE_CHUBVTS_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_CHUBVTS_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_CHUBVTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CMGP_CMU_CMGP_QCH_ENABLE, QCH_CON_CMGP_CMU_CMGP_QCH_CLOCK_REQ, QCH_CON_CMGP_CMU_CMGP_QCH_EXPIRE_VAL, QCH_CON_CMGP_CMU_CMGP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_CMGP_QCH_ENABLE, QCH_CON_D_TZPC_CMGP_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CMGP_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_CMGP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_GPIO_CMGP_QCH_ENABLE, QCH_CON_GPIO_CMGP_QCH_CLOCK_REQ, QCH_CON_GPIO_CMGP_QCH_EXPIRE_VAL, QCH_CON_GPIO_CMGP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_CMGP0_QCH_ENABLE, QCH_CON_I2C_CMGP0_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP0_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_CMGP1_QCH_ENABLE, QCH_CON_I2C_CMGP1_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP1_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_CMGP2_QCH_ENABLE, QCH_CON_I2C_CMGP2_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP2_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_CMGP3_QCH_ENABLE, QCH_CON_I2C_CMGP3_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP3_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP3_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I2C_CMGP4_QCH_ENABLE, QCH_CON_I2C_CMGP4_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP4_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP4_QCH_IGNORE_FORCE_PM_EN, QCH_CON_I3C_CMGP_QCH_P_ENABLE, QCH_CON_I3C_CMGP_QCH_P_CLOCK_REQ, QCH_CON_I3C_CMGP_QCH_P_EXPIRE_VAL, QCH_CON_I3C_CMGP_QCH_P_IGNORE_FORCE_PM_EN, QCH_CON_I3C_CMGP_QCH_S_ENABLE, QCH_CON_I3C_CMGP_QCH_S_CLOCK_REQ, QCH_CON_I3C_CMGP_QCH_S_EXPIRE_VAL, QCH_CON_I3C_CMGP_QCH_S_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_C_CMGP_QCH_ENABLE, QCH_CON_SLH_AXI_MI_C_CMGP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_C_CMGP_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_C_CMGP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CMGP_QCH_ENABLE, QCH_CON_SYSREG_CMGP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CMGP2APM_QCH_ENABLE, QCH_CON_SYSREG_CMGP2APM_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2APM_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2APM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CMGP2CHUB_QCH_ENABLE, QCH_CON_SYSREG_CMGP2CHUB_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2CHUB_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2CHUB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CMGP2CP_QCH_ENABLE, QCH_CON_SYSREG_CMGP2CP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2CP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2CP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CMGP2GNSS_QCH_ENABLE, QCH_CON_SYSREG_CMGP2GNSS_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2GNSS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2GNSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_ENABLE, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CMGP2WLBT_QCH_ENABLE, QCH_CON_SYSREG_CMGP2WLBT_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2WLBT_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2WLBT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI_CMGP0_QCH_ENABLE, QCH_CON_USI_CMGP0_QCH_CLOCK_REQ, QCH_CON_USI_CMGP0_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI_CMGP1_QCH_ENABLE, QCH_CON_USI_CMGP1_QCH_CLOCK_REQ, QCH_CON_USI_CMGP1_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI_CMGP2_QCH_ENABLE, QCH_CON_USI_CMGP2_QCH_CLOCK_REQ, QCH_CON_USI_CMGP2_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI_CMGP3_QCH_ENABLE, QCH_CON_USI_CMGP3_QCH_CLOCK_REQ, QCH_CON_USI_CMGP3_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP3_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI_CMGP4_QCH_ENABLE, QCH_CON_USI_CMGP4_QCH_CLOCK_REQ, QCH_CON_USI_CMGP4_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP4_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_CMU_CMU_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CMU_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_CMU_CMUREF_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_CLOCK_REQ, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_IGNORE_FORCE_PM_EN, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_CLOCK_REQ, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_IGNORE_FORCE_PM_EN, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_CLOCK_REQ, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_IGNORE_FORCE_PM_EN, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_CLOCK_REQ, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_IGNORE_FORCE_PM_EN, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK4_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK4_CLOCK_REQ, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK4_IGNORE_FORCE_PM_EN, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK5_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK5_CLOCK_REQ, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK5_IGNORE_FORCE_PM_EN, DMYQCH_CON_OTP_QCH_ENABLE, DMYQCH_CON_OTP_QCH_CLOCK_REQ, DMYQCH_CON_OTP_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_ADM_APB_G_BDU_QCH_ENABLE, DMYQCH_CON_ADM_APB_G_BDU_QCH_CLOCK_REQ, DMYQCH_CON_ADM_APB_G_BDU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_BAAW_D_SSS_QCH_ENABLE, QCH_CON_BAAW_D_SSS_QCH_CLOCK_REQ, QCH_CON_BAAW_D_SSS_QCH_EXPIRE_VAL, QCH_CON_BAAW_D_SSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_BAAW_P_GNSS_QCH_ENABLE, QCH_CON_BAAW_P_GNSS_QCH_CLOCK_REQ, QCH_CON_BAAW_P_GNSS_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_GNSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_BAAW_P_MODEM_QCH_ENABLE, QCH_CON_BAAW_P_MODEM_QCH_CLOCK_REQ, QCH_CON_BAAW_P_MODEM_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_MODEM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_BAAW_P_WLBT_QCH_ENABLE, QCH_CON_BAAW_P_WLBT_QCH_CLOCK_REQ, QCH_CON_BAAW_P_WLBT_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_WLBT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_BDU_QCH_ENABLE, QCH_CON_BDU_QCH_CLOCK_REQ, QCH_CON_BDU_QCH_EXPIRE_VAL, QCH_CON_BDU_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_CMU_CORE_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CORE_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_CORE_CMUREF_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CORE_CMU_CORE_QCH_ENABLE, QCH_CON_CORE_CMU_CORE_QCH_CLOCK_REQ, QCH_CON_CORE_CMU_CORE_QCH_EXPIRE_VAL, QCH_CON_CORE_CMU_CORE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_DIT_QCH_ENABLE, QCH_CON_DIT_QCH_CLOCK_REQ, QCH_CON_DIT_QCH_EXPIRE_VAL, QCH_CON_DIT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_CORE_QCH_ENABLE, QCH_CON_D_TZPC_CORE_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CORE_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_CORE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_GIC_QCH_ENABLE, QCH_CON_GIC_QCH_CLOCK_REQ, QCH_CON_GIC_QCH_EXPIRE_VAL, QCH_CON_GIC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_HW_APBSEMA_MEC_QCH_ENABLE, QCH_CON_HW_APBSEMA_MEC_QCH_CLOCK_REQ, QCH_CON_HW_APBSEMA_MEC_QCH_EXPIRE_VAL, QCH_CON_HW_APBSEMA_MEC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_MI_G_CPU_QCH_ENABLE, QCH_CON_LH_AST_MI_G_CPU_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_CPU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_CPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D0_DPU_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_DPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_DPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D0_DPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D0_NPUS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_NPUS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_NPUS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D0_NPUS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D1_DPU_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_DPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_DPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D1_DPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D1_NPUS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_NPUS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_NPUS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D1_NPUS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D_AUD_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_AUD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_AUD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_AUD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D_G3D_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_G3D_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_G3D_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D_M2M_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_M2M_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_M2M_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_M2M_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D_SSS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_SSS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_SSS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_SSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D0_MIF_CP_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_MIF_CP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_MIF_CP_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_MIF_CP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D0_MIF_NRT_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_MIF_NRT_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_MIF_NRT_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_MIF_NRT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D0_MIF_RT_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_MIF_RT_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_MIF_RT_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_MIF_RT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D1_MIF_CP_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_MIF_CP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_MIF_CP_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_MIF_CP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D1_MIF_NRT_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_MIF_NRT_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_MIF_NRT_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_MIF_NRT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D1_MIF_RT_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_MIF_RT_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_MIF_RT_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_MIF_RT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D_SSS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_SSS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_SSS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_SSS_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_PUF_QCH_ENABLE, DMYQCH_CON_PUF_QCH_CLOCK_REQ, DMYQCH_CON_PUF_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RSTNSYNC_I_ARESETN_SSS_QCH_ENABLE, QCH_CON_RSTNSYNC_I_ARESETN_SSS_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_I_ARESETN_SSS_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_I_ARESETN_SSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_ENABLE, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_CLOCK_REQ, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_EXPIRE_VAL, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SIREX_QCH_ENABLE, QCH_CON_SIREX_QCH_CLOCK_REQ, QCH_CON_SIREX_QCH_EXPIRE_VAL, QCH_CON_SIREX_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_D0_MODEM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_D1_MODEM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_D_GNSS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D_GNSS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D_GNSS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_D_GNSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_D_HSI_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D_HSI_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D_HSI_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_D_HSI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_D_WLBT_QCH_ENABLE, QCH_CON_SLH_AXI_MI_D_WLBT_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_D_WLBT_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_D_WLBT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_CLUSTER0_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_APM_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_APM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_APM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_APM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_AUD_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_AUD_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_AUD_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_AUD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_BUSC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_BUSC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_BUSC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_BUSC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_CSIS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_CSIS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_CSIS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_CSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_DPU_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_DPU_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_DPU_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_DPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_G3D_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_G3D_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_G3D_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_GNSS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_GNSS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_GNSS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_GNSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_HSI_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_HSI_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_HSI_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_HSI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_ISP_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_ISP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_ISP_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_ISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_M2M_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_M2M_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_M2M_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_M2M_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_MCSC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MCSC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MCSC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_MCSC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_MCW_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MCW_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MCW_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_MCW_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_MFC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MFC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MFC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_MFC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_MIF0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MIF0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MIF0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_MIF0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_MIF1_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MIF1_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MIF1_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_MIF1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_MODEM_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MODEM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MODEM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_MODEM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_NPU0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_NPU0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_NPU0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_NPU0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_NPUS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_NPUS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_NPUS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_NPUS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_PERI_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_PERI_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_PERI_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_PERI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_TAA_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_TAA_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_TAA_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_TAA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_TNR_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_TNR_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_TNR_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_TNR_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_USB_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_USB_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_USB_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_USB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_WLBT_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_WLBT_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_WLBT_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_WLBT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SSS_QCH_ENABLE, QCH_CON_SSS_QCH_CLOCK_REQ, QCH_CON_SSS_QCH_EXPIRE_VAL, QCH_CON_SSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_ACEL_D2_MODEM_QCH_ENABLE, QCH_CON_SYSMMU_ACEL_D2_MODEM_QCH_CLOCK_REQ, QCH_CON_SYSMMU_ACEL_D2_MODEM_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_ACEL_D2_MODEM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_ACEL_D_DIT_QCH_ENABLE, QCH_CON_SYSMMU_ACEL_D_DIT_QCH_CLOCK_REQ, QCH_CON_SYSMMU_ACEL_D_DIT_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_ACEL_D_DIT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CORE_QCH_ENABLE, QCH_CON_SYSREG_CORE_QCH_CLOCK_REQ, QCH_CON_SYSREG_CORE_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CORE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_TREX_D_CORE_QCH_ENABLE, QCH_CON_TREX_D_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_D_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_D_CORE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_TREX_D_NRT_QCH_ENABLE, QCH_CON_TREX_D_NRT_QCH_CLOCK_REQ, QCH_CON_TREX_D_NRT_QCH_EXPIRE_VAL, QCH_CON_TREX_D_NRT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_TREX_P_CORE_QCH_ENABLE, QCH_CON_TREX_P_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_P_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_P_CORE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE_CORE_QCH_ENABLE, QCH_CON_VGEN_LITE_CORE_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_CORE_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_CORE_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_CPUCL0_QCH_ENABLE, DMYQCH_CON_CPUCL0_QCH_CLOCK_REQ, DMYQCH_CON_CPUCL0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_HTU_CPUCL0_QCH_PCLK_ENABLE, QCH_CON_HTU_CPUCL0_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_CPUCL0_QCH_PCLK_EXPIRE_VAL, QCH_CON_HTU_CPUCL0_QCH_PCLK_IGNORE_FORCE_PM_EN, QCH_CON_HTU_CPUCL0_QCH_CLK_ENABLE, QCH_CON_HTU_CPUCL0_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_CPUCL0_QCH_CLK_EXPIRE_VAL, QCH_CON_HTU_CPUCL0_QCH_CLK_IGNORE_FORCE_PM_EN, QCH_CON_BPS_CPUCL0_QCH_ENABLE, QCH_CON_BPS_CPUCL0_QCH_CLOCK_REQ, QCH_CON_BPS_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_BPS_CPUCL0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_ENABLE, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_CLOCK_REQ, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_EXPIRE_VAL, QCH_CON_CPUCL0_GLB_CMU_CPUCL0_GLB_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_CSSYS_QCH_ENABLE, DMYQCH_CON_CSSYS_QCH_CLOCK_REQ, DMYQCH_CON_CSSYS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_CPUCL0_QCH_ENABLE, QCH_CON_D_TZPC_CPUCL0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_CPUCL0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SECJTAG_QCH_ENABLE, QCH_CON_SECJTAG_QCH_CLOCK_REQ, QCH_CON_SECJTAG_QCH_EXPIRE_VAL, QCH_CON_SECJTAG_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_ENABLE, QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_G_INT_CSSYS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_G_INT_CSSYS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_G_INT_CSSYS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_G_INT_CSSYS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_G_INT_DBGCORE_QCH_ENABLE, QCH_CON_SLH_AXI_MI_G_INT_DBGCORE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_G_INT_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_G_INT_DBGCORE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_G_INT_CSSYS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_G_INT_CSSYS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_G_INT_CSSYS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_G_INT_CSSYS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_G_INT_DBGCORE_QCH_ENABLE, QCH_CON_SLH_AXI_SI_G_INT_DBGCORE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_G_INT_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_G_INT_DBGCORE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CPUCL0_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_CPUCL1_QCH_BIG_ENABLE, DMYQCH_CON_CPUCL1_QCH_BIG_CLOCK_REQ, DMYQCH_CON_CPUCL1_QCH_BIG_IGNORE_FORCE_PM_EN, DMYQCH_CON_CPUCL1_QCH_DDD_HC0_ENABLE, DMYQCH_CON_CPUCL1_QCH_DDD_HC0_CLOCK_REQ, DMYQCH_CON_CPUCL1_QCH_DDD_HC0_IGNORE_FORCE_PM_EN, DMYQCH_CON_CPUCL1_QCH_DDD_HC1_ENABLE, DMYQCH_CON_CPUCL1_QCH_DDD_HC1_CLOCK_REQ, DMYQCH_CON_CPUCL1_QCH_DDD_HC1_IGNORE_FORCE_PM_EN, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_HTU_CPUCL1_QCH_PCLK_ENABLE, QCH_CON_HTU_CPUCL1_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_CPUCL1_QCH_PCLK_EXPIRE_VAL, QCH_CON_HTU_CPUCL1_QCH_PCLK_IGNORE_FORCE_PM_EN, QCH_CON_HTU_CPUCL1_QCH_CLK_ENABLE, QCH_CON_HTU_CPUCL1_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_CPUCL1_QCH_CLK_EXPIRE_VAL, QCH_CON_HTU_CPUCL1_QCH_CLK_IGNORE_FORCE_PM_EN, QCH_CON_CSIS_CMU_CSIS_QCH_ENABLE, QCH_CON_CSIS_CMU_CSIS_QCH_CLOCK_REQ, QCH_CON_CSIS_CMU_CSIS_QCH_EXPIRE_VAL, QCH_CON_CSIS_CMU_CSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CSIS_PDP_QCH_VOTF0_ENABLE, QCH_CON_CSIS_PDP_QCH_VOTF0_CLOCK_REQ, QCH_CON_CSIS_PDP_QCH_VOTF0_EXPIRE_VAL, QCH_CON_CSIS_PDP_QCH_VOTF0_IGNORE_FORCE_PM_EN, QCH_CON_CSIS_PDP_QCH_DMA_ENABLE, QCH_CON_CSIS_PDP_QCH_DMA_CLOCK_REQ, QCH_CON_CSIS_PDP_QCH_DMA_EXPIRE_VAL, QCH_CON_CSIS_PDP_QCH_DMA_IGNORE_FORCE_PM_EN, QCH_CON_CSIS_PDP_QCH_PDP_TOP_ENABLE, QCH_CON_CSIS_PDP_QCH_PDP_TOP_CLOCK_REQ, QCH_CON_CSIS_PDP_QCH_PDP_TOP_EXPIRE_VAL, QCH_CON_CSIS_PDP_QCH_PDP_TOP_IGNORE_FORCE_PM_EN, QCH_CON_CSIS_PDP_QCH_MCB_ENABLE, QCH_CON_CSIS_PDP_QCH_MCB_CLOCK_REQ, QCH_CON_CSIS_PDP_QCH_MCB_EXPIRE_VAL, QCH_CON_CSIS_PDP_QCH_MCB_IGNORE_FORCE_PM_EN, QCH_CON_CSIS_PDP_QCH_VOTF1_ENABLE, QCH_CON_CSIS_PDP_QCH_VOTF1_CLOCK_REQ, QCH_CON_CSIS_PDP_QCH_VOTF1_EXPIRE_VAL, QCH_CON_CSIS_PDP_QCH_VOTF1_IGNORE_FORCE_PM_EN, QCH_CON_CSIS_PDP_QCH_C2_PDP_ENABLE, QCH_CON_CSIS_PDP_QCH_C2_PDP_CLOCK_REQ, QCH_CON_CSIS_PDP_QCH_C2_PDP_EXPIRE_VAL, QCH_CON_CSIS_PDP_QCH_C2_PDP_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_CSIS_QCH_ENABLE, QCH_CON_D_TZPC_CSIS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CSIS_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_CSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_MI_SOTF0_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_SOTF0_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_SOTF0_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_SOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_MI_SOTF1_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_SOTF1_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_SOTF1_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_SOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_MI_SOTF2_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_SOTF2_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_SOTF2_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_SOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_MI_ZOTF0_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_ZOTF0_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_ZOTF0_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_ZOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_MI_ZOTF1_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_ZOTF1_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_ZOTF1_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_ZOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_MI_ZOTF2_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_ZOTF2_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_ZOTF2_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_ZOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_SI_OTF0_CSISTAA_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF0_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF0_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_OTF0_CSISTAA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_SI_OTF1_CSISTAA_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF1_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF1_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_OTF1_CSISTAA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_SI_OTF2_CSISTAA_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF2_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF2_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_OTF2_CSISTAA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D0_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D1_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D2_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D2_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D2_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D2_CSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D3_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D3_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D3_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D3_CSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0_ENABLE, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0_CLOCK_REQ, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0_EXPIRE_VAL, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS0_IGNORE_FORCE_PM_EN, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1_ENABLE, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1_CLOCK_REQ, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1_EXPIRE_VAL, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS1_IGNORE_FORCE_PM_EN, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2_ENABLE, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2_CLOCK_REQ, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2_EXPIRE_VAL, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS2_IGNORE_FORCE_PM_EN, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3_ENABLE, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3_CLOCK_REQ, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3_EXPIRE_VAL, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS3_IGNORE_FORCE_PM_EN, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4_ENABLE, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4_CLOCK_REQ, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4_EXPIRE_VAL, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS4_IGNORE_FORCE_PM_EN, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5_ENABLE, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5_CLOCK_REQ, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5_EXPIRE_VAL, QCH_CON_MIPI_DCPHY_LINK_WRAP_QCH_CSIS5_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_CSIS_D0_QCH_ENABLE, QCH_CON_PPMU_CSIS_D0_QCH_CLOCK_REQ, QCH_CON_PPMU_CSIS_D0_QCH_EXPIRE_VAL, QCH_CON_PPMU_CSIS_D0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_CSIS_D1_QCH_ENABLE, QCH_CON_PPMU_CSIS_D1_QCH_CLOCK_REQ, QCH_CON_PPMU_CSIS_D1_QCH_EXPIRE_VAL, QCH_CON_PPMU_CSIS_D1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_CSIS_D2_QCH_ENABLE, QCH_CON_PPMU_CSIS_D2_QCH_CLOCK_REQ, QCH_CON_PPMU_CSIS_D2_QCH_EXPIRE_VAL, QCH_CON_PPMU_CSIS_D2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_CSIS_D3_QCH_ENABLE, QCH_CON_PPMU_CSIS_D3_QCH_CLOCK_REQ, QCH_CON_PPMU_CSIS_D3_QCH_EXPIRE_VAL, QCH_CON_PPMU_CSIS_D3_QCH_IGNORE_FORCE_PM_EN, QCH_CON_QE_CSIS_DMA0_QCH_ENABLE, QCH_CON_QE_CSIS_DMA0_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_DMA0_QCH_EXPIRE_VAL, QCH_CON_QE_CSIS_DMA0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_QE_CSIS_DMA1_QCH_ENABLE, QCH_CON_QE_CSIS_DMA1_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_DMA1_QCH_EXPIRE_VAL, QCH_CON_QE_CSIS_DMA1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_QE_CSIS_DMA2_QCH_ENABLE, QCH_CON_QE_CSIS_DMA2_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_DMA2_QCH_EXPIRE_VAL, QCH_CON_QE_CSIS_DMA2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_QE_CSIS_DMA3_QCH_ENABLE, QCH_CON_QE_CSIS_DMA3_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_DMA3_QCH_EXPIRE_VAL, QCH_CON_QE_CSIS_DMA3_QCH_IGNORE_FORCE_PM_EN, QCH_CON_QE_PDP_AF0_QCH_ENABLE, QCH_CON_QE_PDP_AF0_QCH_CLOCK_REQ, QCH_CON_QE_PDP_AF0_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_AF0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_QE_PDP_AF1_QCH_ENABLE, QCH_CON_QE_PDP_AF1_QCH_CLOCK_REQ, QCH_CON_QE_PDP_AF1_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_AF1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_QE_PDP_AF2_QCH_ENABLE, QCH_CON_QE_PDP_AF2_QCH_CLOCK_REQ, QCH_CON_QE_PDP_AF2_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_AF2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_QE_PDP_STAT_IMG0_QCH_ENABLE, QCH_CON_QE_PDP_STAT_IMG0_QCH_CLOCK_REQ, QCH_CON_QE_PDP_STAT_IMG0_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_STAT_IMG0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_QE_PDP_STAT_IMG1_QCH_ENABLE, QCH_CON_QE_PDP_STAT_IMG1_QCH_CLOCK_REQ, QCH_CON_QE_PDP_STAT_IMG1_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_STAT_IMG1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_QE_PDP_STAT_IMG2_QCH_ENABLE, QCH_CON_QE_PDP_STAT_IMG2_QCH_CLOCK_REQ, QCH_CON_QE_PDP_STAT_IMG2_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_STAT_IMG2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_QE_STRP0_QCH_ENABLE, QCH_CON_QE_STRP0_QCH_CLOCK_REQ, QCH_CON_QE_STRP0_QCH_EXPIRE_VAL, QCH_CON_QE_STRP0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_QE_STRP1_QCH_ENABLE, QCH_CON_QE_STRP1_QCH_CLOCK_REQ, QCH_CON_QE_STRP1_QCH_EXPIRE_VAL, QCH_CON_QE_STRP1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_QE_STRP2_QCH_ENABLE, QCH_CON_QE_STRP2_QCH_CLOCK_REQ, QCH_CON_QE_STRP2_QCH_EXPIRE_VAL, QCH_CON_QE_STRP2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_QE_ZSL0_QCH_ENABLE, QCH_CON_QE_ZSL0_QCH_CLOCK_REQ, QCH_CON_QE_ZSL0_QCH_EXPIRE_VAL, QCH_CON_QE_ZSL0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_QE_ZSL1_QCH_ENABLE, QCH_CON_QE_ZSL1_QCH_CLOCK_REQ, QCH_CON_QE_ZSL1_QCH_EXPIRE_VAL, QCH_CON_QE_ZSL1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_QE_ZSL2_QCH_ENABLE, QCH_CON_QE_ZSL2_QCH_CLOCK_REQ, QCH_CON_QE_ZSL2_QCH_EXPIRE_VAL, QCH_CON_QE_ZSL2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_CSIS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_CSIS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_CSIS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_CSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D0_CSIS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_CSIS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_CSIS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_CSIS_QCH_S1_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D0_CSIS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_CSIS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_CSIS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D0_CSIS_QCH_S2_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D1_CSIS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_CSIS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_CSIS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_CSIS_QCH_S1_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D1_CSIS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_CSIS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_CSIS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D1_CSIS_QCH_S2_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D2_CSIS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D2_CSIS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D2_CSIS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D2_CSIS_QCH_S1_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D2_CSIS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D2_CSIS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D2_CSIS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D2_CSIS_QCH_S2_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D3_CSIS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D3_CSIS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D3_CSIS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D3_CSIS_QCH_S2_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D3_CSIS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D3_CSIS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D3_CSIS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D3_CSIS_QCH_S1_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_CSIS_QCH_ENABLE, QCH_CON_SYSREG_CSIS_QCH_CLOCK_REQ, QCH_CON_SYSREG_CSIS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE0_CSIS_QCH_ENABLE, QCH_CON_VGEN_LITE0_CSIS_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE0_CSIS_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE0_CSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE1_CSIS_QCH_ENABLE, QCH_CON_VGEN_LITE1_CSIS_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE1_CSIS_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE1_CSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE2_CSIS_QCH_ENABLE, QCH_CON_VGEN_LITE2_CSIS_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE2_CSIS_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE2_CSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_DPU_QCH_DPU_ENABLE, QCH_CON_DPU_QCH_DPU_CLOCK_REQ, QCH_CON_DPU_QCH_DPU_EXPIRE_VAL, QCH_CON_DPU_QCH_DPU_IGNORE_FORCE_PM_EN, QCH_CON_DPU_QCH_DPU_DMA_ENABLE, QCH_CON_DPU_QCH_DPU_DMA_CLOCK_REQ, QCH_CON_DPU_QCH_DPU_DMA_EXPIRE_VAL, QCH_CON_DPU_QCH_DPU_DMA_IGNORE_FORCE_PM_EN, QCH_CON_DPU_QCH_DPU_DPP_ENABLE, QCH_CON_DPU_QCH_DPU_DPP_CLOCK_REQ, QCH_CON_DPU_QCH_DPU_DPP_EXPIRE_VAL, QCH_CON_DPU_QCH_DPU_DPP_IGNORE_FORCE_PM_EN, QCH_CON_DPU_QCH_DPU_C2SERV_ENABLE, QCH_CON_DPU_QCH_DPU_C2SERV_CLOCK_REQ, QCH_CON_DPU_QCH_DPU_C2SERV_EXPIRE_VAL, QCH_CON_DPU_QCH_DPU_C2SERV_IGNORE_FORCE_PM_EN, DMYQCH_CON_DPU_QCH_ENABLE, DMYQCH_CON_DPU_QCH_CLOCK_REQ, DMYQCH_CON_DPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_DPU_CMU_DPU_QCH_ENABLE, QCH_CON_DPU_CMU_DPU_QCH_CLOCK_REQ, QCH_CON_DPU_CMU_DPU_QCH_EXPIRE_VAL, QCH_CON_DPU_CMU_DPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_DPU_QCH_ENABLE, QCH_CON_D_TZPC_DPU_QCH_CLOCK_REQ, QCH_CON_D_TZPC_DPU_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_DPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D0_DPU_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_DPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_DPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_DPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D1_DPU_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_DPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_DPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_DPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_D0_DPU_QCH_ENABLE, QCH_CON_PPMU_D0_DPU_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_DPU_QCH_EXPIRE_VAL, QCH_CON_PPMU_D0_DPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_D1_DPU_QCH_ENABLE, QCH_CON_PPMU_D1_DPU_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_DPU_QCH_EXPIRE_VAL, QCH_CON_PPMU_D1_DPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_DPU_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_DPU_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_DPU_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_DPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S1_ENABLE, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S1_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S2_ENABLE, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_AXI_D0_DPU_QCH_S2_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S1_ENABLE, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S1_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S2_ENABLE, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_AXI_D1_DPU_QCH_S2_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_DPU_QCH_ENABLE, QCH_CON_SYSREG_DPU_QCH_CLOCK_REQ, QCH_CON_SYSREG_DPU_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CLUSTER0_QCH_SCLK_ENABLE, QCH_CON_CLUSTER0_QCH_SCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_SCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_SCLK_IGNORE_FORCE_PM_EN, QCH_CON_CLUSTER0_QCH_ATCLK_ENABLE, QCH_CON_CLUSTER0_QCH_ATCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_ATCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_ATCLK_IGNORE_FORCE_PM_EN, QCH_CON_CLUSTER0_QCH_GIC_ENABLE, QCH_CON_CLUSTER0_QCH_GIC_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_GIC_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_GIC_IGNORE_FORCE_PM_EN, QCH_CON_CLUSTER0_QCH_DBG_PD_ENABLE, QCH_CON_CLUSTER0_QCH_DBG_PD_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_DBG_PD_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_DBG_PD_IGNORE_FORCE_PM_EN, QCH_CON_CLUSTER0_QCH_PCLK_ENABLE, QCH_CON_CLUSTER0_QCH_PCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_PCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_PCLK_IGNORE_FORCE_PM_EN, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_ENABLE, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_CLOCK_REQ, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_IGNORE_FORCE_PM_EN, QCH_CON_CLUSTER0_QCH_PDBGCLK_ENABLE, QCH_CON_CLUSTER0_QCH_PDBGCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_PDBGCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_PDBGCLK_IGNORE_FORCE_PM_EN, DMYQCH_CON_CMU_DSU_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_DSU_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_DSU_CMUREF_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CMU_DSU_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_DSU_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_DSU_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_DSU_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_DSU_CMU_DSU_QCH_ENABLE, QCH_CON_DSU_CMU_DSU_QCH_CLOCK_REQ, QCH_CON_DSU_CMU_DSU_QCH_EXPIRE_VAL, QCH_CON_DSU_CMU_DSU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_HTU_DSU_QCH_PCLK_ENABLE, QCH_CON_HTU_DSU_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_DSU_QCH_PCLK_EXPIRE_VAL, QCH_CON_HTU_DSU_QCH_PCLK_IGNORE_FORCE_PM_EN, QCH_CON_HTU_DSU_QCH_CLK_ENABLE, QCH_CON_HTU_DSU_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_DSU_QCH_CLK_EXPIRE_VAL, QCH_CON_HTU_DSU_QCH_CLK_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_SI_G_CPU_QCH_ENABLE, QCH_CON_LH_AST_SI_G_CPU_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_CPU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_G_CPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D0_MIF_CPU_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_MIF_CPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_MIF_CPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_MIF_CPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D1_MIF_CPU_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_MIF_CPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_MIF_CPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_MIF_CPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_ENABLE, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_CLOCK_REQ, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_EXPIRE_VAL, QCH_CON_PPC_INSTRRET_CLUSTER0_0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_ENABLE, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_CLOCK_REQ, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_EXPIRE_VAL, QCH_CON_PPC_INSTRRET_CLUSTER0_1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_ENABLE, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_CLOCK_REQ, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_EXPIRE_VAL, QCH_CON_PPC_INSTRRUN_CLUSTER0_0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_ENABLE, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_CLOCK_REQ, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_EXPIRE_VAL, QCH_CON_PPC_INSTRRUN_CLUSTER0_1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_CPUCL0_QCH_ENABLE, QCH_CON_PPMU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_PPMU_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_PPMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_CPUCL1_QCH_ENABLE, QCH_CON_PPMU_CPUCL1_QCH_CLOCK_REQ, QCH_CON_PPMU_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_PPMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_CLUSTER0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_G3D_QCH_ENABLE, QCH_CON_D_TZPC_G3D_QCH_CLOCK_REQ, QCH_CON_D_TZPC_G3D_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_G3D_CMU_G3D_QCH_ENABLE, QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL, QCH_CON_G3D_CMU_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_GPU_QCH_ENABLE, QCH_CON_GPU_QCH_CLOCK_REQ, QCH_CON_GPU_QCH_EXPIRE_VAL, QCH_CON_GPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_HTU_G3D_QCH_CLK_ENABLE, QCH_CON_HTU_G3D_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_G3D_QCH_CLK_EXPIRE_VAL, QCH_CON_HTU_G3D_QCH_CLK_IGNORE_FORCE_PM_EN, QCH_CON_HTU_G3D_QCH_PCLK_ENABLE, QCH_CON_HTU_G3D_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_G3D_QCH_PCLK_EXPIRE_VAL, QCH_CON_HTU_G3D_QCH_PCLK_IGNORE_FORCE_PM_EN, QCH_CON_LHM_AXI_P_INT_G3D_QCH_ENABLE, QCH_CON_LHM_AXI_P_INT_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_INT_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_INT_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LHS_AXI_P_INT_G3D_QCH_ENABLE, QCH_CON_LHS_AXI_P_INT_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_INT_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_INT_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D_G3D_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_G3D_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_G3D_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_D_G3D_QCH_ENABLE, QCH_CON_PPMU_D_G3D_QCH_CLOCK_REQ, QCH_CON_PPMU_D_G3D_QCH_EXPIRE_VAL, QCH_CON_PPMU_D_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_G3D_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_G3D_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_G3D_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D_G3D_QCH_ENABLE, QCH_CON_SYSMMU_D_G3D_QCH_CLOCK_REQ, QCH_CON_SYSMMU_D_G3D_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_D_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_G3D_QCH_ENABLE, QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL, QCH_CON_SYSREG_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE_G3D_QCH_ENABLE, QCH_CON_VGEN_LITE_G3D_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_G3D_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_G3D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_GNSS_CMU_GNSS_QCH_ENABLE, QCH_CON_GNSS_CMU_GNSS_QCH_CLOCK_REQ, QCH_CON_GNSS_CMU_GNSS_QCH_EXPIRE_VAL, QCH_CON_GNSS_CMU_GNSS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_HSI_QCH_ENABLE, QCH_CON_D_TZPC_HSI_QCH_CLOCK_REQ, QCH_CON_D_TZPC_HSI_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_HSI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_GPIO_HSI_QCH_ENABLE, QCH_CON_GPIO_HSI_QCH_CLOCK_REQ, QCH_CON_GPIO_HSI_QCH_EXPIRE_VAL, QCH_CON_GPIO_HSI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_GPIO_HSI_UFS_QCH_ENABLE, QCH_CON_GPIO_HSI_UFS_QCH_CLOCK_REQ, QCH_CON_GPIO_HSI_UFS_QCH_EXPIRE_VAL, QCH_CON_GPIO_HSI_UFS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_HSI_CMU_HSI_QCH_ENABLE, QCH_CON_HSI_CMU_HSI_QCH_CLOCK_REQ, QCH_CON_HSI_CMU_HSI_QCH_EXPIRE_VAL, QCH_CON_HSI_CMU_HSI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_HSI_QCH_ENABLE, QCH_CON_PPMU_HSI_QCH_CLOCK_REQ, QCH_CON_PPMU_HSI_QCH_EXPIRE_VAL, QCH_CON_PPMU_HSI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_S2MPU_D_HSI_QCH_S2_ENABLE, QCH_CON_S2MPU_D_HSI_QCH_S2_CLOCK_REQ, QCH_CON_S2MPU_D_HSI_QCH_S2_EXPIRE_VAL, QCH_CON_S2MPU_D_HSI_QCH_S2_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_HSI_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_HSI_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_HSI_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_HSI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_D_HSI_QCH_ENABLE, QCH_CON_SLH_AXI_SI_D_HSI_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_D_HSI_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_D_HSI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_HSI_QCH_ENABLE, QCH_CON_SYSREG_HSI_QCH_CLOCK_REQ, QCH_CON_SYSREG_HSI_QCH_EXPIRE_VAL, QCH_CON_SYSREG_HSI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_UFS_EMBD_QCH_ENABLE, QCH_CON_UFS_EMBD_QCH_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_EXPIRE_VAL, QCH_CON_UFS_EMBD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_UFS_EMBD_QCH_FMP_ENABLE, QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_FMP_EXPIRE_VAL, QCH_CON_UFS_EMBD_QCH_FMP_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE_HSI_QCH_ENABLE, QCH_CON_VGEN_LITE_HSI_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_HSI_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_HSI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_ISP_QCH_ENABLE, QCH_CON_D_TZPC_ISP_QCH_CLOCK_REQ, QCH_CON_D_TZPC_ISP_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_ISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_ISP_CMU_ISP_QCH_ENABLE, QCH_CON_ISP_CMU_ISP_QCH_CLOCK_REQ, QCH_CON_ISP_CMU_ISP_QCH_EXPIRE_VAL, QCH_CON_ISP_CMU_ISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_ITP_DNS_QCH_S00_ENABLE, QCH_CON_ITP_DNS_QCH_S00_CLOCK_REQ, QCH_CON_ITP_DNS_QCH_S00_EXPIRE_VAL, QCH_CON_ITP_DNS_QCH_S00_IGNORE_FORCE_PM_EN, QCH_CON_ITP_DNS_QCH_S01_ENABLE, QCH_CON_ITP_DNS_QCH_S01_CLOCK_REQ, QCH_CON_ITP_DNS_QCH_S01_EXPIRE_VAL, QCH_CON_ITP_DNS_QCH_S01_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_MI_OTF0_TNRISP_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF0_TNRISP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF0_TNRISP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_OTF0_TNRISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_MI_OTF1_TNRISP_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF1_TNRISP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF1_TNRISP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_OTF1_TNRISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_MI_OTF_TAAISP_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF_TAAISP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF_TAAISP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_OTF_TAAISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_SI_OTF_ISPMCSC_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF_ISPMCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF_ISPMCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_OTF_ISPMCSC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D_ISP_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_ISP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_ISP_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_ISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_ISP_QCH_ENABLE, QCH_CON_PPMU_ISP_QCH_CLOCK_REQ, QCH_CON_PPMU_ISP_QCH_EXPIRE_VAL, QCH_CON_PPMU_ISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_ISP_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_ISP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_ISP_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_ISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D_ISP_QCH_S1_ENABLE, QCH_CON_SYSMMU_D_ISP_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D_ISP_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D_ISP_QCH_S1_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D_ISP_QCH_S2_ENABLE, QCH_CON_SYSMMU_D_ISP_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D_ISP_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D_ISP_QCH_S2_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_ISP_QCH_ENABLE, QCH_CON_SYSREG_ISP_QCH_CLOCK_REQ, QCH_CON_SYSREG_ISP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_ISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE_ISP_QCH_ENABLE, QCH_CON_VGEN_LITE_ISP_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_ISP_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_ISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_M2M_QCH_ENABLE, QCH_CON_D_TZPC_M2M_QCH_CLOCK_REQ, QCH_CON_D_TZPC_M2M_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_M2M_QCH_IGNORE_FORCE_PM_EN, QCH_CON_JPEG0_QCH_ENABLE, QCH_CON_JPEG0_QCH_CLOCK_REQ, QCH_CON_JPEG0_QCH_EXPIRE_VAL, QCH_CON_JPEG0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D_M2M_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_M2M_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_M2M_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_M2M_QCH_IGNORE_FORCE_PM_EN, QCH_CON_M2M_QCH_S2_ENABLE, QCH_CON_M2M_QCH_S2_CLOCK_REQ, QCH_CON_M2M_QCH_S2_EXPIRE_VAL, QCH_CON_M2M_QCH_S2_IGNORE_FORCE_PM_EN, QCH_CON_M2M_QCH_S1_ENABLE, QCH_CON_M2M_QCH_S1_CLOCK_REQ, QCH_CON_M2M_QCH_S1_EXPIRE_VAL, QCH_CON_M2M_QCH_S1_IGNORE_FORCE_PM_EN, QCH_CON_M2M_CMU_M2M_QCH_ENABLE, QCH_CON_M2M_CMU_M2M_QCH_CLOCK_REQ, QCH_CON_M2M_CMU_M2M_QCH_EXPIRE_VAL, QCH_CON_M2M_CMU_M2M_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_D_M2M_QCH_ENABLE, QCH_CON_PPMU_D_M2M_QCH_CLOCK_REQ, QCH_CON_PPMU_D_M2M_QCH_EXPIRE_VAL, QCH_CON_PPMU_D_M2M_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_M2M_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_M2M_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_M2M_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_M2M_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D_M2M_QCH_S1_ENABLE, QCH_CON_SYSMMU_D_M2M_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D_M2M_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D_M2M_QCH_S1_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D_M2M_QCH_S2_ENABLE, QCH_CON_SYSMMU_D_M2M_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D_M2M_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D_M2M_QCH_S2_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_M2M_QCH_ENABLE, QCH_CON_SYSREG_M2M_QCH_CLOCK_REQ, QCH_CON_SYSREG_M2M_QCH_EXPIRE_VAL, QCH_CON_SYSREG_M2M_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE_M2M_QCH_ENABLE, QCH_CON_VGEN_LITE_M2M_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_M2M_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_M2M_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_MCSC_QCH_ENABLE, QCH_CON_D_TZPC_MCSC_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MCSC_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_MCSC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_GDC_QCH_ENABLE, QCH_CON_GDC_QCH_CLOCK_REQ, QCH_CON_GDC_QCH_EXPIRE_VAL, QCH_CON_GDC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_MI_OTF_ISPMCSC_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF_ISPMCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF_ISPMCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_OTF_ISPMCSC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D0_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D0_TNR_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D0_TNR_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D1_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D1_TNR_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D1_TNR_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D2_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D2_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D2_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D2_CSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D3_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D3_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D3_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D3_CSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D_ISP_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_ISP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_ISP_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_ISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D_TAA_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_TAA_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_TAA_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_TAA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MCSC_QCH_ENABLE, QCH_CON_MCSC_QCH_CLOCK_REQ, QCH_CON_MCSC_QCH_EXPIRE_VAL, QCH_CON_MCSC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MCSC_CMU_MCSC_QCH_ENABLE, QCH_CON_MCSC_CMU_MCSC_QCH_CLOCK_REQ, QCH_CON_MCSC_CMU_MCSC_QCH_EXPIRE_VAL, QCH_CON_MCSC_CMU_MCSC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_ORBMCH_QCH_ACLK_ENABLE, QCH_CON_ORBMCH_QCH_ACLK_CLOCK_REQ, QCH_CON_ORBMCH_QCH_ACLK_EXPIRE_VAL, QCH_CON_ORBMCH_QCH_ACLK_IGNORE_FORCE_PM_EN, QCH_CON_ORBMCH_QCH_C2CLK_ENABLE, QCH_CON_ORBMCH_QCH_C2CLK_CLOCK_REQ, QCH_CON_ORBMCH_QCH_C2CLK_EXPIRE_VAL, QCH_CON_ORBMCH_QCH_C2CLK_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_GDC_QCH_ENABLE, QCH_CON_PPMU_GDC_QCH_CLOCK_REQ, QCH_CON_PPMU_GDC_QCH_EXPIRE_VAL, QCH_CON_PPMU_GDC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_MCSC_QCH_ENABLE, QCH_CON_PPMU_MCSC_QCH_CLOCK_REQ, QCH_CON_PPMU_MCSC_QCH_EXPIRE_VAL, QCH_CON_PPMU_MCSC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_MCSC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_MCSC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_MCSC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_MCSC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D0_MCSC_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_MCSC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_MCSC_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_MCSC_QCH_S1_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D0_MCSC_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_MCSC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_MCSC_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D0_MCSC_QCH_S2_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D1_MCSC_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_MCSC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_MCSC_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_MCSC_QCH_S1_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D1_MCSC_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_MCSC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_MCSC_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D1_MCSC_QCH_S2_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_MCSC_QCH_ENABLE, QCH_CON_SYSREG_MCSC_QCH_CLOCK_REQ, QCH_CON_SYSREG_MCSC_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MCSC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_TREX_D_CAM_QCH_ENABLE, QCH_CON_TREX_D_CAM_QCH_CLOCK_REQ, QCH_CON_TREX_D_CAM_QCH_EXPIRE_VAL, QCH_CON_TREX_D_CAM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE_GDC_QCH_ENABLE, QCH_CON_VGEN_LITE_GDC_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_GDC_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_GDC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE_MCSC_QCH_ENABLE, QCH_CON_VGEN_LITE_MCSC_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_MCSC_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_MCSC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_MFC_QCH_ENABLE, QCH_CON_D_TZPC_MFC_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MFC_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_MFC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D_MFC_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_MFC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_MFC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_MFC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MFC_QCH_ENABLE, QCH_CON_MFC_QCH_CLOCK_REQ, QCH_CON_MFC_QCH_EXPIRE_VAL, QCH_CON_MFC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MFC_CMU_MFC_QCH_ENABLE, QCH_CON_MFC_CMU_MFC_QCH_CLOCK_REQ, QCH_CON_MFC_CMU_MFC_QCH_EXPIRE_VAL, QCH_CON_MFC_CMU_MFC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_MFC_QCH_ENABLE, QCH_CON_PPMU_MFC_QCH_CLOCK_REQ, QCH_CON_PPMU_MFC_QCH_EXPIRE_VAL, QCH_CON_PPMU_MFC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_MFC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_MFC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_MFC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_MFC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_MFC_QCH_S1_ENABLE, QCH_CON_SYSMMU_MFC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_MFC_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_MFC_QCH_S1_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_MFC_QCH_S2_ENABLE, QCH_CON_SYSMMU_MFC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_MFC_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_MFC_QCH_S2_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_MFC_QCH_ENABLE, QCH_CON_SYSREG_MFC_QCH_CLOCK_REQ, QCH_CON_SYSREG_MFC_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MFC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE_MFC_QCH_ENABLE, QCH_CON_VGEN_LITE_MFC_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_MFC_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_MFC_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, DMYQCH_CON_CMU_MIF_CMUREF_QCH_IGNORE_FORCE_PM_EN, QCH_CON_DMC_QCH_ENABLE, QCH_CON_DMC_QCH_CLOCK_REQ, QCH_CON_DMC_QCH_EXPIRE_VAL, QCH_CON_DMC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_MIF_QCH_ENABLE, QCH_CON_D_TZPC_MIF_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MIF_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_MIF_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D_MIF_CP_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_MIF_CP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_MIF_CP_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_MIF_CP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D_MIF_CPU_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_MIF_CPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_MIF_CPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_MIF_CPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D_MIF_NRT_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_MIF_NRT_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_MIF_NRT_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_MIF_NRT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D_MIF_RT_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_MIF_RT_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_MIF_RT_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_MIF_RT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MIF_CMU_MIF_QCH_ENABLE, QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL, QCH_CON_MIF_CMU_MIF_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_DMC_CPU_QCH_ENABLE, QCH_CON_PPMU_DMC_CPU_QCH_CLOCK_REQ, QCH_CON_PPMU_DMC_CPU_QCH_EXPIRE_VAL, QCH_CON_PPMU_DMC_CPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_QE_DMC_CPU_QCH_ENABLE, QCH_CON_QE_DMC_CPU_QCH_CLOCK_REQ, QCH_CON_QE_DMC_CPU_QCH_EXPIRE_VAL, QCH_CON_QE_DMC_CPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SFRAPB_BRIDGE_DDRPHY_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DDRPHY_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DDRPHY_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DDRPHY_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SFRAPB_BRIDGE_DMC_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DMC_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DMC_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DMC_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DMC_PF_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DMC_PPMPU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_ENABLE, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_CLOCK_REQ, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_EXPIRE_VAL, QCH_CON_SFRAPB_BRIDGE_DMC_SECURE_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_MIF_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_MIF_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_MIF_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_MIF_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_MIF_QCH_ENABLE, QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MIF_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MODEM_CMU_MODEM_QCH_ENABLE, QCH_CON_MODEM_CMU_MODEM_QCH_CLOCK_REQ, QCH_CON_MODEM_CMU_MODEM_QCH_EXPIRE_VAL, QCH_CON_MODEM_CMU_MODEM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_NPU0_QCH_ENABLE, QCH_CON_D_TZPC_NPU0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_NPU0_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_NPU0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_IP_NPUCORE_QCH_ACLK_ENABLE, QCH_CON_IP_NPUCORE_QCH_ACLK_CLOCK_REQ, QCH_CON_IP_NPUCORE_QCH_ACLK_EXPIRE_VAL, QCH_CON_IP_NPUCORE_QCH_ACLK_IGNORE_FORCE_PM_EN, QCH_CON_IP_NPUCORE_QCH_PCLK_ENABLE, QCH_CON_IP_NPUCORE_QCH_PCLK_CLOCK_REQ, QCH_CON_IP_NPUCORE_QCH_PCLK_EXPIRE_VAL, QCH_CON_IP_NPUCORE_QCH_PCLK_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D0_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D0_NPU0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D1_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D1_NPU0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D_CTRL_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_CTRL_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_CTRL_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_CTRL_NPU0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D_CMDQ_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_CMDQ_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_CMDQ_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_CMDQ_NPU0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D_RQ_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_RQ_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_RQ_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_RQ_NPU0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_NPU0_CMU_NPU0_QCH_ENABLE, QCH_CON_NPU0_CMU_NPU0_QCH_CLOCK_REQ, QCH_CON_NPU0_CMU_NPU0_QCH_EXPIRE_VAL, QCH_CON_NPU0_CMU_NPU0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_NPU0_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_NPU0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_NPU0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_NPU0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_NPU0_QCH_ENABLE, QCH_CON_SYSREG_NPU0_QCH_CLOCK_REQ, QCH_CON_SYSREG_NPU0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_NPU0_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_ADM_DAP_NPUS_QCH_ENABLE, DMYQCH_CON_ADM_DAP_NPUS_QCH_CLOCK_REQ, DMYQCH_CON_ADM_DAP_NPUS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_NPUS_QCH_ENABLE, QCH_CON_D_TZPC_NPUS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_NPUS_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_NPUS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_HTU_NPUS_QCH_PCLK_ENABLE, QCH_CON_HTU_NPUS_QCH_PCLK_CLOCK_REQ, QCH_CON_HTU_NPUS_QCH_PCLK_EXPIRE_VAL, QCH_CON_HTU_NPUS_QCH_PCLK_IGNORE_FORCE_PM_EN, QCH_CON_HTU_NPUS_QCH_CLK_ENABLE, QCH_CON_HTU_NPUS_QCH_CLK_CLOCK_REQ, QCH_CON_HTU_NPUS_QCH_CLK_EXPIRE_VAL, QCH_CON_HTU_NPUS_QCH_CLK_IGNORE_FORCE_PM_EN, QCH_CON_IP_NPUS_QCH_ENABLE, QCH_CON_IP_NPUS_QCH_CLOCK_REQ, QCH_CON_IP_NPUS_QCH_EXPIRE_VAL, QCH_CON_IP_NPUS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_IP_NPUS_QCH_C2A0CLK_ENABLE, QCH_CON_IP_NPUS_QCH_C2A0CLK_CLOCK_REQ, QCH_CON_IP_NPUS_QCH_C2A0CLK_EXPIRE_VAL, QCH_CON_IP_NPUS_QCH_C2A0CLK_IGNORE_FORCE_PM_EN, QCH_CON_IP_NPUS_QCH_C2A1CLK_ENABLE, QCH_CON_IP_NPUS_QCH_C2A1CLK_CLOCK_REQ, QCH_CON_IP_NPUS_QCH_C2A1CLK_EXPIRE_VAL, QCH_CON_IP_NPUS_QCH_C2A1CLK_IGNORE_FORCE_PM_EN, QCH_CON_IP_NPUS_QCH_CPU_ENABLE, QCH_CON_IP_NPUS_QCH_CPU_CLOCK_REQ, QCH_CON_IP_NPUS_QCH_CPU_EXPIRE_VAL, QCH_CON_IP_NPUS_QCH_CPU_IGNORE_FORCE_PM_EN, QCH_CON_IP_NPUS_QCH_NEON_ENABLE, QCH_CON_IP_NPUS_QCH_NEON_CLOCK_REQ, QCH_CON_IP_NPUS_QCH_NEON_EXPIRE_VAL, QCH_CON_IP_NPUS_QCH_NEON_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D_CMDQ_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_CMDQ_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_CMDQ_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_CMDQ_NPU0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_MI_D_RQ_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_RQ_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_RQ_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_RQ_NPU0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D0_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_NPU0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D0_NPUS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_NPUS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_NPUS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_NPUS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D1_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_NPU0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D1_NPUS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_NPUS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_NPUS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_NPUS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D_CTRL_NPU0_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_CTRL_NPU0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_CTRL_NPU0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_CTRL_NPU0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_NPUS_CMU_NPUS_QCH_ENABLE, QCH_CON_NPUS_CMU_NPUS_QCH_CLOCK_REQ, QCH_CON_NPUS_CMU_NPUS_QCH_EXPIRE_VAL, QCH_CON_NPUS_CMU_NPUS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_NPUS_0_QCH_ENABLE, QCH_CON_PPMU_NPUS_0_QCH_CLOCK_REQ, QCH_CON_PPMU_NPUS_0_QCH_EXPIRE_VAL, QCH_CON_PPMU_NPUS_0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_NPUS_1_QCH_ENABLE, QCH_CON_PPMU_NPUS_1_QCH_CLOCK_REQ, QCH_CON_PPMU_NPUS_1_QCH_EXPIRE_VAL, QCH_CON_PPMU_NPUS_1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_INT_NPUS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_INT_NPUS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_INT_NPUS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_INT_NPUS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_NPUS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_NPUS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_NPUS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_NPUS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_P_INT_NPUS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_INT_NPUS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_INT_NPUS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_INT_NPUS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D0_NPUS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_NPUS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_NPUS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_NPUS_QCH_S1_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D0_NPUS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_NPUS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_NPUS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D0_NPUS_QCH_S2_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D1_NPUS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_NPUS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_NPUS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_NPUS_QCH_S1_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D1_NPUS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_NPUS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_NPUS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D1_NPUS_QCH_S2_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_NPUS_QCH_ENABLE, QCH_CON_SYSREG_NPUS_QCH_CLOCK_REQ, QCH_CON_SYSREG_NPUS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_NPUS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE_NPUS_QCH_ENABLE, QCH_CON_VGEN_LITE_NPUS_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_NPUS_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_NPUS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_PERI_QCH_ENABLE, QCH_CON_D_TZPC_PERI_QCH_CLOCK_REQ, QCH_CON_D_TZPC_PERI_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_PERI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_GPIO_PERI_QCH_ENABLE, QCH_CON_GPIO_PERI_QCH_CLOCK_REQ, QCH_CON_GPIO_PERI_QCH_EXPIRE_VAL, QCH_CON_GPIO_PERI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_GPIO_PERIMMC_QCH_GPIO_ENABLE, QCH_CON_GPIO_PERIMMC_QCH_GPIO_CLOCK_REQ, QCH_CON_GPIO_PERIMMC_QCH_GPIO_EXPIRE_VAL, QCH_CON_GPIO_PERIMMC_QCH_GPIO_IGNORE_FORCE_PM_EN, QCH_CON_MCT_QCH_ENABLE, QCH_CON_MCT_QCH_CLOCK_REQ, QCH_CON_MCT_QCH_EXPIRE_VAL, QCH_CON_MCT_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MMC_CARD_QCH_ENABLE, QCH_CON_MMC_CARD_QCH_CLOCK_REQ, QCH_CON_MMC_CARD_QCH_EXPIRE_VAL, QCH_CON_MMC_CARD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_OTP_CON_TOP_QCH_ENABLE, QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL, QCH_CON_OTP_CON_TOP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PERI_CMU_PERI_QCH_ENABLE, QCH_CON_PERI_CMU_PERI_QCH_CLOCK_REQ, QCH_CON_PERI_CMU_PERI_QCH_EXPIRE_VAL, QCH_CON_PERI_CMU_PERI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_PERI_QCH_ENABLE, QCH_CON_PPMU_PERI_QCH_CLOCK_REQ, QCH_CON_PPMU_PERI_QCH_EXPIRE_VAL, QCH_CON_PPMU_PERI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PWM_QCH_ENABLE, QCH_CON_PWM_QCH_CLOCK_REQ, QCH_CON_PWM_QCH_EXPIRE_VAL, QCH_CON_PWM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_S2MPU_D_PERI_QCH_ENABLE, QCH_CON_S2MPU_D_PERI_QCH_CLOCK_REQ, QCH_CON_S2MPU_D_PERI_QCH_EXPIRE_VAL, QCH_CON_S2MPU_D_PERI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_PERI_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_PERI_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_PERI_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_PERI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_D_PERI_QCH_ENABLE, QCH_CON_SLH_AXI_SI_D_PERI_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_D_PERI_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_D_PERI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_PERI_QCH_ENABLE, QCH_CON_SYSREG_PERI_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERI_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PERI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_TMU_QCH_ENABLE, QCH_CON_TMU_QCH_CLOCK_REQ, QCH_CON_TMU_QCH_EXPIRE_VAL, QCH_CON_TMU_QCH_IGNORE_FORCE_PM_EN, QCH_CON_UART_DBG_QCH_ENABLE, QCH_CON_UART_DBG_QCH_CLOCK_REQ, QCH_CON_UART_DBG_QCH_EXPIRE_VAL, QCH_CON_UART_DBG_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI00_I2C_QCH_ENABLE, QCH_CON_USI00_I2C_QCH_CLOCK_REQ, QCH_CON_USI00_I2C_QCH_EXPIRE_VAL, QCH_CON_USI00_I2C_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI00_USI_QCH_ENABLE, QCH_CON_USI00_USI_QCH_CLOCK_REQ, QCH_CON_USI00_USI_QCH_EXPIRE_VAL, QCH_CON_USI00_USI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI01_I2C_QCH_ENABLE, QCH_CON_USI01_I2C_QCH_CLOCK_REQ, QCH_CON_USI01_I2C_QCH_EXPIRE_VAL, QCH_CON_USI01_I2C_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI01_USI_QCH_ENABLE, QCH_CON_USI01_USI_QCH_CLOCK_REQ, QCH_CON_USI01_USI_QCH_EXPIRE_VAL, QCH_CON_USI01_USI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI02_I2C_QCH_ENABLE, QCH_CON_USI02_I2C_QCH_CLOCK_REQ, QCH_CON_USI02_I2C_QCH_EXPIRE_VAL, QCH_CON_USI02_I2C_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI02_USI_QCH_ENABLE, QCH_CON_USI02_USI_QCH_CLOCK_REQ, QCH_CON_USI02_USI_QCH_EXPIRE_VAL, QCH_CON_USI02_USI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI03_I2C_QCH_ENABLE, QCH_CON_USI03_I2C_QCH_CLOCK_REQ, QCH_CON_USI03_I2C_QCH_EXPIRE_VAL, QCH_CON_USI03_I2C_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI03_USI_QCH_ENABLE, QCH_CON_USI03_USI_QCH_CLOCK_REQ, QCH_CON_USI03_USI_QCH_EXPIRE_VAL, QCH_CON_USI03_USI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI04_I2C_QCH_ENABLE, QCH_CON_USI04_I2C_QCH_CLOCK_REQ, QCH_CON_USI04_I2C_QCH_EXPIRE_VAL, QCH_CON_USI04_I2C_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI04_USI_QCH_ENABLE, QCH_CON_USI04_USI_QCH_CLOCK_REQ, QCH_CON_USI04_USI_QCH_EXPIRE_VAL, QCH_CON_USI04_USI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI05_I2C_QCH_ENABLE, QCH_CON_USI05_I2C_QCH_CLOCK_REQ, QCH_CON_USI05_I2C_QCH_EXPIRE_VAL, QCH_CON_USI05_I2C_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI05_USI_QCH_ENABLE, QCH_CON_USI05_USI_QCH_CLOCK_REQ, QCH_CON_USI05_USI_QCH_EXPIRE_VAL, QCH_CON_USI05_USI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI06_I2C_QCH_ENABLE, QCH_CON_USI06_I2C_QCH_CLOCK_REQ, QCH_CON_USI06_I2C_QCH_EXPIRE_VAL, QCH_CON_USI06_I2C_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI06_USI_QCH_ENABLE, QCH_CON_USI06_USI_QCH_CLOCK_REQ, QCH_CON_USI06_USI_QCH_EXPIRE_VAL, QCH_CON_USI06_USI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USI07_I2C_QCH_ENABLE, QCH_CON_USI07_I2C_QCH_CLOCK_REQ, QCH_CON_USI07_I2C_QCH_EXPIRE_VAL, QCH_CON_USI07_I2C_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE_PERI_QCH_ENABLE, QCH_CON_VGEN_LITE_PERI_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_PERI_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_PERI_QCH_IGNORE_FORCE_PM_EN, QCH_CON_WDT0_QCH_ENABLE, QCH_CON_WDT0_QCH_CLOCK_REQ, QCH_CON_WDT0_QCH_EXPIRE_VAL, QCH_CON_WDT0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_WDT1_QCH_ENABLE, QCH_CON_WDT1_QCH_CLOCK_REQ, QCH_CON_WDT1_QCH_EXPIRE_VAL, QCH_CON_WDT1_QCH_IGNORE_FORCE_PM_EN, QCH_CON_S2D_CMU_S2D_QCH_ENABLE, QCH_CON_S2D_CMU_S2D_QCH_CLOCK_REQ, QCH_CON_S2D_CMU_S2D_QCH_EXPIRE_VAL, QCH_CON_S2D_CMU_S2D_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_TAA_QCH_ENABLE, QCH_CON_D_TZPC_TAA_QCH_CLOCK_REQ, QCH_CON_D_TZPC_TAA_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_TAA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_MI_OTF0_CSISTAA_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF0_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF0_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_OTF0_CSISTAA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_MI_OTF1_CSISTAA_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF1_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF1_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_OTF1_CSISTAA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_MI_OTF2_CSISTAA_QCH_ENABLE, QCH_CON_LH_AST_MI_OTF2_CSISTAA_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_OTF2_CSISTAA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_OTF2_CSISTAA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_SI_OTF_TAAISP_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF_TAAISP_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF_TAAISP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_OTF_TAAISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_SI_SOTF0_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_SOTF0_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_SOTF0_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_SOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_SI_SOTF1_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_SOTF1_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_SOTF1_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_SOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_SI_SOTF2_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_SOTF2_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_SOTF2_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_SOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_SI_ZOTF0_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_ZOTF0_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_ZOTF0_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_ZOTF0_TAACSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_SI_ZOTF1_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_ZOTF1_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_ZOTF1_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_ZOTF1_TAACSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_SI_ZOTF2_TAACSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_ZOTF2_TAACSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_ZOTF2_TAACSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_ZOTF2_TAACSIS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D_TAA_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_TAA_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_TAA_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_TAA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_TAA_QCH_ENABLE, QCH_CON_PPMU_TAA_QCH_CLOCK_REQ, QCH_CON_PPMU_TAA_QCH_EXPIRE_VAL, QCH_CON_PPMU_TAA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SIPU_TAA_QCH_ENABLE, QCH_CON_SIPU_TAA_QCH_CLOCK_REQ, QCH_CON_SIPU_TAA_QCH_EXPIRE_VAL, QCH_CON_SIPU_TAA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SIPU_TAA_QCH_C2_STAT_ENABLE, QCH_CON_SIPU_TAA_QCH_C2_STAT_CLOCK_REQ, QCH_CON_SIPU_TAA_QCH_C2_STAT_EXPIRE_VAL, QCH_CON_SIPU_TAA_QCH_C2_STAT_IGNORE_FORCE_PM_EN, QCH_CON_SIPU_TAA_QCH_C2_YDS_ENABLE, QCH_CON_SIPU_TAA_QCH_C2_YDS_CLOCK_REQ, QCH_CON_SIPU_TAA_QCH_C2_YDS_EXPIRE_VAL, QCH_CON_SIPU_TAA_QCH_C2_YDS_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_TAA_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_TAA_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_TAA_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_TAA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_TAA_QCH_S1_ENABLE, QCH_CON_SYSMMU_TAA_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_TAA_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_TAA_QCH_S1_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_TAA_QCH_S2_ENABLE, QCH_CON_SYSMMU_TAA_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_TAA_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_TAA_QCH_S2_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_TAA_QCH_ENABLE, QCH_CON_SYSREG_TAA_QCH_CLOCK_REQ, QCH_CON_SYSREG_TAA_QCH_EXPIRE_VAL, QCH_CON_SYSREG_TAA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_TAA_CMU_TAA_QCH_ENABLE, QCH_CON_TAA_CMU_TAA_QCH_CLOCK_REQ, QCH_CON_TAA_CMU_TAA_QCH_EXPIRE_VAL, QCH_CON_TAA_CMU_TAA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE0_TAA_QCH_ENABLE, QCH_CON_VGEN_LITE0_TAA_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE0_TAA_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE0_TAA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE1_TAA_QCH_ENABLE, QCH_CON_VGEN_LITE1_TAA_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE1_TAA_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE1_TAA_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_TNR_QCH_ENABLE, QCH_CON_D_TZPC_TNR_QCH_CLOCK_REQ, QCH_CON_D_TZPC_TNR_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_TNR_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_SI_OTF0_TNRISP_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF0_TNRISP_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF0_TNRISP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_OTF0_TNRISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AST_SI_OTF1_TNRISP_QCH_ENABLE, QCH_CON_LH_AST_SI_OTF1_TNRISP_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_OTF1_TNRISP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_OTF1_TNRISP_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D0_TNR_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_TNR_QCH_IGNORE_FORCE_PM_EN, QCH_CON_LH_AXI_SI_D1_TNR_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_TNR_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_D0_TNR_QCH_ENABLE, QCH_CON_PPMU_D0_TNR_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_TNR_QCH_EXPIRE_VAL, QCH_CON_PPMU_D0_TNR_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_D1_TNR_QCH_ENABLE, QCH_CON_PPMU_D1_TNR_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_TNR_QCH_EXPIRE_VAL, QCH_CON_PPMU_D1_TNR_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_TNR_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_TNR_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_TNR_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_TNR_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D0_TNR_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_TNR_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_TNR_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_TNR_QCH_S1_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D0_TNR_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_TNR_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_TNR_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D0_TNR_QCH_S2_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D1_TNR_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_TNR_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_TNR_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_TNR_QCH_S1_IGNORE_FORCE_PM_EN, QCH_CON_SYSMMU_D1_TNR_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_TNR_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_TNR_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D1_TNR_QCH_S2_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_TNR_QCH_ENABLE, QCH_CON_SYSREG_TNR_QCH_CLOCK_REQ, QCH_CON_SYSREG_TNR_QCH_EXPIRE_VAL, QCH_CON_SYSREG_TNR_QCH_IGNORE_FORCE_PM_EN, QCH_CON_TNR_QCH_MCFP0_ENABLE, QCH_CON_TNR_QCH_MCFP0_CLOCK_REQ, QCH_CON_TNR_QCH_MCFP0_EXPIRE_VAL, QCH_CON_TNR_QCH_MCFP0_IGNORE_FORCE_PM_EN, QCH_CON_TNR_QCH_MCFP1_ENABLE, QCH_CON_TNR_QCH_MCFP1_CLOCK_REQ, QCH_CON_TNR_QCH_MCFP1_EXPIRE_VAL, QCH_CON_TNR_QCH_MCFP1_IGNORE_FORCE_PM_EN, QCH_CON_TNR_CMU_TNR_QCH_ENABLE, QCH_CON_TNR_CMU_TNR_QCH_CLOCK_REQ, QCH_CON_TNR_CMU_TNR_QCH_EXPIRE_VAL, QCH_CON_TNR_CMU_TNR_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE_D_TNR_QCH_ENABLE, QCH_CON_VGEN_LITE_D_TNR_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_D_TNR_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_D_TNR_QCH_IGNORE_FORCE_PM_EN, QCH_CON_D_TZPC_USB_QCH_ENABLE, QCH_CON_D_TZPC_USB_QCH_CLOCK_REQ, QCH_CON_D_TZPC_USB_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_USB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_PPMU_USB_QCH_ENABLE, QCH_CON_PPMU_USB_QCH_CLOCK_REQ, QCH_CON_PPMU_USB_QCH_EXPIRE_VAL, QCH_CON_PPMU_USB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_S2MPU_D_USB_QCH_ENABLE, QCH_CON_S2MPU_D_USB_QCH_CLOCK_REQ, QCH_CON_S2MPU_D_USB_QCH_EXPIRE_VAL, QCH_CON_S2MPU_D_USB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_P_USB_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_USB_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_USB_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_USB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_D_USB_QCH_ENABLE, QCH_CON_SLH_AXI_SI_D_USB_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_D_USB_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_D_USB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_D_USBAUD_QCH_ENABLE, QCH_CON_SLH_AXI_SI_D_USBAUD_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_D_USBAUD_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_D_USBAUD_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_USB_QCH_ENABLE, QCH_CON_SYSREG_USB_QCH_CLOCK_REQ, QCH_CON_SYSREG_USB_QCH_EXPIRE_VAL, QCH_CON_SYSREG_USB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_USB20DRD_TOP_QCH_SLV_CTRL_ENABLE, QCH_CON_USB20DRD_TOP_QCH_SLV_CTRL_CLOCK_REQ, QCH_CON_USB20DRD_TOP_QCH_SLV_CTRL_EXPIRE_VAL, QCH_CON_USB20DRD_TOP_QCH_SLV_CTRL_IGNORE_FORCE_PM_EN, QCH_CON_USB20DRD_TOP_QCH_SLV_LINK_ENABLE, QCH_CON_USB20DRD_TOP_QCH_SLV_LINK_CLOCK_REQ, QCH_CON_USB20DRD_TOP_QCH_SLV_LINK_EXPIRE_VAL, QCH_CON_USB20DRD_TOP_QCH_SLV_LINK_IGNORE_FORCE_PM_EN, QCH_CON_USB_CMU_USB_QCH_ENABLE, QCH_CON_USB_CMU_USB_QCH_CLOCK_REQ, QCH_CON_USB_CMU_USB_QCH_EXPIRE_VAL, QCH_CON_USB_CMU_USB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VGEN_LITE_USB_QCH_ENABLE, QCH_CON_VGEN_LITE_USB_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_USB_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_USB_QCH_IGNORE_FORCE_PM_EN, QCH_CON_CM4_VTS_QCH_CPU_ENABLE, QCH_CON_CM4_VTS_QCH_CPU_CLOCK_REQ, QCH_CON_CM4_VTS_QCH_CPU_EXPIRE_VAL, QCH_CON_CM4_VTS_QCH_CPU_IGNORE_FORCE_PM_EN, QCH_CON_DMIC_AHB0_QCH_PCLK_ENABLE, QCH_CON_DMIC_AHB0_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AHB0_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AHB0_QCH_PCLK_IGNORE_FORCE_PM_EN, QCH_CON_DMIC_AHB2_QCH_PCLK_ENABLE, QCH_CON_DMIC_AHB2_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AHB2_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AHB2_QCH_PCLK_IGNORE_FORCE_PM_EN, QCH_CON_DMIC_AUD0_QCH_PCLK_ENABLE, QCH_CON_DMIC_AUD0_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AUD0_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AUD0_QCH_PCLK_IGNORE_FORCE_PM_EN, DMYQCH_CON_DMIC_AUD0_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_AUD0_QCH_DMIC_CLOCK_REQ, DMYQCH_CON_DMIC_AUD0_QCH_DMIC_IGNORE_FORCE_PM_EN, QCH_CON_DMIC_AUD1_QCH_PCLK_ENABLE, QCH_CON_DMIC_AUD1_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AUD1_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AUD1_QCH_PCLK_IGNORE_FORCE_PM_EN, DMYQCH_CON_DMIC_AUD1_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_AUD1_QCH_DMIC_CLOCK_REQ, DMYQCH_CON_DMIC_AUD1_QCH_DMIC_IGNORE_FORCE_PM_EN, QCH_CON_DMIC_IF0_QCH_PCLK_ENABLE, QCH_CON_DMIC_IF0_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_IF0_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_IF0_QCH_PCLK_IGNORE_FORCE_PM_EN, DMYQCH_CON_DMIC_IF0_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_IF0_QCH_DMIC_CLOCK_REQ, DMYQCH_CON_DMIC_IF0_QCH_DMIC_IGNORE_FORCE_PM_EN, QCH_CON_DMIC_IF1_QCH_PCLK_ENABLE, QCH_CON_DMIC_IF1_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_IF1_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_IF1_QCH_PCLK_IGNORE_FORCE_PM_EN, DMYQCH_CON_DMIC_IF1_QCH_DMIC_ENABLE, DMYQCH_CON_DMIC_IF1_QCH_DMIC_CLOCK_REQ, DMYQCH_CON_DMIC_IF1_QCH_DMIC_IGNORE_FORCE_PM_EN, QCH_CON_GPIO_VTS_QCH_ENABLE, QCH_CON_GPIO_VTS_QCH_CLOCK_REQ, QCH_CON_GPIO_VTS_QCH_EXPIRE_VAL, QCH_CON_GPIO_VTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_HWACG_SYS_DMIC0_QCH_ENABLE, QCH_CON_HWACG_SYS_DMIC0_QCH_CLOCK_REQ, QCH_CON_HWACG_SYS_DMIC0_QCH_EXPIRE_VAL, QCH_CON_HWACG_SYS_DMIC0_QCH_IGNORE_FORCE_PM_EN, QCH_CON_HWACG_SYS_DMIC2_QCH_ENABLE, QCH_CON_HWACG_SYS_DMIC2_QCH_CLOCK_REQ, QCH_CON_HWACG_SYS_DMIC2_QCH_EXPIRE_VAL, QCH_CON_HWACG_SYS_DMIC2_QCH_IGNORE_FORCE_PM_EN, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_ENABLE, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_CLOCK_REQ, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_EXPIRE_VAL, QCH_CON_HWACG_SYS_SERIAL_LIF_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_ABOX_VTS_QCH_ENABLE, QCH_CON_MAILBOX_ABOX_VTS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_ABOX_VTS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_ABOX_VTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_MAILBOX_AP_VTS_QCH_ENABLE, QCH_CON_MAILBOX_AP_VTS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_VTS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_VTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SERIAL_LIF_AUD_QCH_PCLK_ENABLE, QCH_CON_SERIAL_LIF_AUD_QCH_PCLK_CLOCK_REQ, QCH_CON_SERIAL_LIF_AUD_QCH_PCLK_EXPIRE_VAL, QCH_CON_SERIAL_LIF_AUD_QCH_PCLK_IGNORE_FORCE_PM_EN, DMYQCH_CON_SERIAL_LIF_AUD_QCH_AHB_ENABLE, DMYQCH_CON_SERIAL_LIF_AUD_QCH_AHB_CLOCK_REQ, DMYQCH_CON_SERIAL_LIF_AUD_QCH_AHB_IGNORE_FORCE_PM_EN, DMYQCH_CON_SERIAL_LIF_AUD_QCH_LIF_ENABLE, DMYQCH_CON_SERIAL_LIF_AUD_QCH_LIF_CLOCK_REQ, DMYQCH_CON_SERIAL_LIF_AUD_QCH_LIF_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_MI_S_VTS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_S_VTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_S_VTS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_S_VTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_SLH_AXI_SI_M_VTS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_M_VTS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_M_VTS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_M_VTS_QCH_IGNORE_FORCE_PM_EN, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0_ENABLE, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0_CLOCK_REQ, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD0_IGNORE_FORCE_PM_EN, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1_ENABLE, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1_CLOCK_REQ, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_AUD_PAD1_IGNORE_FORCE_PM_EN, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_ENABLE, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_CLOCK_REQ, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD0_IGNORE_FORCE_PM_EN, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_ENABLE, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_CLOCK_REQ, DMYQCH_CON_SS_VTS_GLUE_QCH_DMIC_IF_PAD1_IGNORE_FORCE_PM_EN, QCH_CON_SYSREG_VTS_QCH_ENABLE, QCH_CON_SYSREG_VTS_QCH_CLOCK_REQ, QCH_CON_SYSREG_VTS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_VTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_TIMER_VTS_QCH_ENABLE, QCH_CON_TIMER_VTS_QCH_CLOCK_REQ, QCH_CON_TIMER_VTS_QCH_EXPIRE_VAL, QCH_CON_TIMER_VTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_VTS_CMU_VTS_QCH_ENABLE, QCH_CON_VTS_CMU_VTS_QCH_CLOCK_REQ, QCH_CON_VTS_CMU_VTS_QCH_EXPIRE_VAL, QCH_CON_VTS_CMU_VTS_QCH_IGNORE_FORCE_PM_EN, QCH_CON_WDT_VTS_QCH_ENABLE, QCH_CON_WDT_VTS_QCH_CLOCK_REQ, QCH_CON_WDT_VTS_QCH_EXPIRE_VAL, QCH_CON_WDT_VTS_QCH_IGNORE_FORCE_PM_EN, ALIVE_CMU_ALIVE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, ALIVE_CMU_ALIVE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, BUSC_CMU_BUSC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, BUSC_CMU_BUSC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, CHUB_CMU_CHUB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CHUB_CMU_CHUB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CHUBVTS_CMU_CHUBVTS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL0_GLB_CMU_CPUCL0_GLB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, DPU_CMU_DPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DPU_CMU_DPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, DSU_CMU_DSU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DSU_CMU_DSU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, GNSS_CMU_GNSS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, GNSS_CMU_GNSS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, HSI_CMU_HSI_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, HSI_CMU_HSI_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, ISP_CMU_ISP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, ISP_CMU_ISP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, M2M_CMU_M2M_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, M2M_CMU_M2M_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, MODEM_CMU_MODEM_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MODEM_CMU_MODEM_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, NPU0_CMU_NPU0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NPU0_CMU_NPU0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, NPUS_CMU_NPUS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NPUS_CMU_NPUS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, PERI_CMU_PERI_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, PERI_CMU_PERI_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, TAA_CMU_TAA_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, TAA_CMU_TAA_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, TNR_CMU_TNR_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, TNR_CMU_TNR_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, USB_CMU_USB_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, USB_CMU_USB_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, end_of_sfr_access, num_of_sfr_access = end_of_sfr_access - SFR_ACCESS_TYPE, }; #endif