/* * Copyright (c) 2019 Samsung Electronics Co., Ltd. * * Author: Hajun Sung * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * Device Tree binding constants for S5E8825 interrupt controller. */ #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_S5E8825_H #define _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_S5E8825_H #include #define I3C_APM_PMIC_O_INTERRUPT 0 #define INTREQ__ALIVE_CP_ACTIVE 1 #define INTREQ__ALIVE_EINT0 2 #define INTREQ__ALIVE_EINT1 3 #define INTREQ__ALIVE_EINT2 4 #define INTREQ__ALIVE_EINT3 5 #define INTREQ__ALIVE_EINT4 6 #define INTREQ__ALIVE_EINT5 7 #define INTREQ__ALIVE_EINT6 8 #define INTREQ__ALIVE_EINT7 9 #define INTREQ__ALIVE_EINT8 10 #define INTREQ__ALIVE_EINT9 11 #define INTREQ__ALIVE_EINT10 12 #define INTREQ__ALIVE_EINT11 13 #define INTREQ__ALIVE_EXT_INTC0 14 #define INTREQ__ALIVE_EXT_INTC1 15 #define INTREQ__ALIVE_EXT_INTC2 16 #define INTREQ__ALIVE_EXT_INTC3 17 #define INTREQ__ALIVE_EXT_INTC4 18 #define INTREQ__ALIVE_EXT_INTC5 19 #define INTREQ__ALIVE_EXT_INTC6 20 #define INTREQ__ALIVE_EXT_INTC7 21 #define INTREQ__ALIVE_GNSS_ACTIVE 22 #define INTREQ__ALIVE_WLBT_ACTIVE 23 #define INTREQ__COMB_NONSECURE_SYSREG_VGPIO2AP 24 #define INTREQ__COMB_SFI_CE_NONSECURE_SYSREG_APM 25 #define INTREQ__COMB_SFI_UCE_NONSECURE_SYSREG_APM 26 #define INTREQ__DBGCORE_UART 27 #define INTREQ__I2C_ALIVE0 28 #define INTREQ__MAILBOX_APM2AP 29 #define INTREQ__MAILBOX_CHUB2AP 30 #define INTREQ__MAILBOX_CP2AP_0 31 #define INTREQ__MAILBOX_CP2AP_1 32 #define INTREQ__MAILBOX_CP2AP_2 33 #define INTREQ__MAILBOX_CP2AP_3 34 #define INTREQ__MAILBOX_CP2AP_4 35 #define INTREQ__MAILBOX_DBGCORE2AP 36 #define INTREQ__MAILBOX_GNSS2AP 37 #define INTREQ__MAILBOX_WLBT2ABOX 38 #define INTREQ__MAILBOX_WLBT_BT2AP 39 #define INTREQ__MAILBOX_WLBT_WL2AP 40 #define INTREQ__NOTIFY 41 #define INTREQ__RTC_ALARM_INT 42 #define INTREQ__RTC_TIC_INT_0 43 #define INTREQ__S_MAILBOX_CP2AP 44 #define INTREQ__TOP_RTC_ALARM_INT 45 #define INTREQ__TOP_RTC_TIC_INT_0 46 #define INTREQ__USI_ALIVE0 47 #define INTREQ__AUD_ABOX_GIC400_MCPU 48 #define INTREQ__AUD_WDT 49 #define INTREQ__SYSMMU_ABOX_S1_NS 50 #define INTREQ__SYSMMU_ABOX_S1_S 51 #define INTREQ__SYSMMU_ABOX_S2_NS 52 #define INTREQ__SYSMMU_ABOX_S2_S 53 #define INTREQ__PDMA0 54 #define INTREQ__SPDMA0 55 #define INTREQ__SYSMMU_AXI_D_BUSC_O_INTERRUPT_S2_NS 56 #define INTREQ__SYSMMU_AXI_D_BUSC_O_INTERRUPT_S2_S 57 #define INTREQ__TREX_D_BUSC_DEBUGINTERRUPT1 58 #define INTREQ__TREX_D_BUSC_PPCINTERRUPT_CORE0 59 #define INTREQ__EXT_INTE0 60 #define INTREQ__EXT_INTE1 61 #define INTREQ__EXT_INTH0_0 62 #define INTREQ__EXT_INTH0_1 63 #define INTREQ__EXT_INTH0_2 64 #define INTREQ__EXT_INTH0_3 65 #define INTREQ__EXT_INTH0_4 66 #define INTREQ__EXT_INTH0_5 67 #define INTREQ__EXT_INTH0_6 68 #define INTREQ__EXT_INTH0_7 69 #define INTREQ__EXT_INTH1_0 70 #define INTREQ__EXT_INTH1_1 71 #define INTREQ__EXT_INTH1_2 72 #define INTREQ__EXT_INTH1_3 73 #define INTREQ__I2C_CHUB1 74 #define INTREQ__I2C_CHUB3 75 #define INTREQ__MAILBOX_AP_VTS 76 #define INTREQ__TIMER_CHUB 77 #define INTREQ__USI_CHUB0 78 #define INTREQ__USI_CHUB1 79 #define INTREQ__USI_CHUB2 80 #define INTREQ__USI_CHUB3 81 #define INTREQ__WDT_CHUB 82 #define INTREQ__WDT_VTS 83 #define INTRQ_PWM_CHUB_0 84 #define INTRQ_PWM_CHUB_1 85 #define INTRQ_PWM_CHUB_2 86 #define INTRQ_PWM_CHUB_3 87 #define INTREQ__EXT_INTM00 88 #define INTREQ__EXT_INTM01 89 #define INTREQ__EXT_INTM02 90 #define INTREQ__EXT_INTM03 91 #define INTREQ__EXT_INTM04 92 #define INTREQ__EXT_INTM05 93 #define INTREQ__EXT_INTM06 94 #define INTREQ__EXT_INTM07 95 #define INTREQ__EXT_INTM08 96 #define INTREQ__EXT_INTM09 97 #define INTREQ__EXT_INTM10 98 #define INTREQ__EXT_INTM11 99 #define INTREQ__EXT_INTM12 100 #define INTREQ__EXT_INTM13 101 #define INTREQ__EXT_INTM14 102 #define INTREQ__EXT_INTM15 103 #define INTREQ__EXT_INTM16 104 #define INTREQ__EXT_INTM17 105 #define INTREQ__EXT_INTM18 106 #define INTREQ__EXT_INTM19 107 #define INTREQ__EXT_INTM20 108 #define INTREQ__CPUCL0_CTIIRQ_0 109 #define INTREQ__CPUCL0_CTIIRQ_1 110 #define INTREQ__CPUCL0_CTIIRQ_2 111 #define INTREQ__CPUCL0_CTIIRQ_3 112 #define INTREQ__CPUCL0_CTIIRQ_4 113 #define INTREQ__CPUCL0_CTIIRQ_5 114 #define INTREQ__CPUCL0_CTIIRQ_6 115 #define INTREQ__CPUCL0_CTIIRQ_7 116 #define INTREQ__CPUCL0_PMBIRQ_6 117 #define INTREQ__CPUCL0_PMBIRQ_7 118 #define INTREQ__I2C_CMGP0 119 #define INTREQ__I2C_CMGP1 120 #define INTREQ__I2C_CMGP2 121 #define INTREQ__I2C_CMGP3 122 #define INTREQ__I2C_CMGP4 123 #define INTREQ__I3C_CMGP 124 #define INTREQ__USI_CMGP0 125 #define INTREQ__USI_CMGP1 126 #define INTREQ__USI_CMGP2 127 #define INTREQ__USI_CMGP3 128 #define INTREQ__USI_CMGP4 129 #define INTREQ__CPUCL0_CLUSTERPMUIRQ 130 #define INTREQ__CPUCL0_COMMIRQ_0 131 #define INTREQ__CPUCL0_COMMIRQ_1 132 #define INTREQ__CPUCL0_COMMIRQ_2 133 #define INTREQ__CPUCL0_COMMIRQ_3 134 #define INTREQ__CPUCL0_COMMIRQ_4 135 #define INTREQ__CPUCL0_COMMIRQ_5 136 #define INTREQ__CPUCL0_COMMIRQ_6 137 #define INTREQ__CPUCL0_COMMIRQ_7 138 #define INTREQ__CPUCL0_ERRIRQ_0 139 #define INTREQ__CPUCL0_ERRIRQ_1 140 #define INTREQ__CPUCL0_ERRIRQ_2 141 #define INTREQ__CPUCL0_ERRIRQ_3 142 #define INTREQ__CPUCL0_ERRIRQ_4 143 #define INTREQ__CPUCL0_ERRIRQ_5 144 #define INTREQ__CPUCL0_ERRIRQ_6 145 #define INTREQ__CPUCL0_ERRIRQ_7 146 #define INTREQ__CPUCL0_ERRIRQ_8 147 #define INTREQ__CPUCL0_FAULTIRQ_0 148 #define INTREQ__CPUCL0_FAULTIRQ_1 149 #define INTREQ__CPUCL0_FAULTIRQ_2 150 #define INTREQ__CPUCL0_FAULTIRQ_3 151 #define INTREQ__CPUCL0_FAULTIRQ_4 152 #define INTREQ__CPUCL0_FAULTIRQ_5 153 #define INTREQ__CPUCL0_FAULTIRQ_6 154 #define INTREQ__CPUCL0_FAULTIRQ_7 155 #define INTREQ__CPUCL0_FAULTIRQ_8 156 #define INTREQ__CPUCL0_PMUIRQ_0 157 #define INTREQ__CPUCL0_PMUIRQ_1 158 #define INTREQ__CPUCL0_PMUIRQ_2 159 #define INTREQ__CPUCL0_PMUIRQ_3 160 #define INTREQ__CPUCL0_PMUIRQ_4 161 #define INTREQ__CPUCL0_PMUIRQ_5 162 #define INTREQ__CPUCL0_PMUIRQ_6 163 #define INTREQ__CPUCL0_PMUIRQ_7 164 #define INTREQ__OCP_REATOR_CPUCL0_0 165 #define INTREQ__OCP_REATOR_CPUCL0_1 166 #define INTREQ__OCP_REATOR_DSU 167 #define INTREQ__PPC_INSTRRET_LOWER_CPUCL0_0 168 #define INTREQ__PPC_INSTRRET_LOWER_CPUCL0_1 169 #define INTREQ__PPC_INSTRRET_UPPER_CPUCL0_0 170 #define INTREQ__PPC_INSTRRET_UPPER_CPUCL0_1 171 #define INTREQ__PPC_INSTRRUN_LOWER_CPUCL0_0 172 #define INTREQ__PPC_INSTRRUN_LOWER_CPUCL0_1 173 #define INTREQ__PPC_INSTRRUN_UPPER_CPUCL0_0 174 #define INTREQ__PPC_INSTRRUN_UPPER_CPUCL0_1 175 #define INTREQ__PPMU_LOWER_CPUCL0 176 #define INTREQ__PPMU_LOWER_CPUCL1 177 #define INTREQ__CSIS0 178 #define INTREQ__CSIS1 179 #define INTREQ__CSIS2 180 #define INTREQ__CSIS3 181 #define INTREQ__CSIS4 182 #define INTREQ__CSIS5 183 #define INTREQ__CSIS_DMA0 184 #define INTREQ__CSIS_DMA1 185 #define INTREQ__CSIS_DMA2 186 #define INTREQ__CSIS_DMA3 187 #define INTREQ__OVERFLOW 188 #define INTREQ__PDP_TOP0 189 #define INTREQ__PDP_TOP1 190 #define INTREQ__PDP_TOP2 191 #define INTREQ__PDP_TOP3 192 #define INTREQ__PDP_TOP4 193 #define INTREQ__PDP_TOP5 194 #define INTREQ__PDP_TOP6 195 #define INTREQ__PDP_TOP7 196 #define INTREQ__STRP_DMA0 197 #define INTREQ__STRP_DMA1 198 #define INTREQ__STRP_DMA2 199 #define INTREQ__SYSMMU_D0_CSIS_S1_NS 200 #define INTREQ__SYSMMU_D0_CSIS_S1_S 201 #define INTREQ__SYSMMU_D0_CSIS_S2_NS 202 #define INTREQ__SYSMMU_D0_CSIS_S2_S 203 #define INTREQ__SYSMMU_D1_CSIS_S1_NS 204 #define INTREQ__SYSMMU_D1_CSIS_S1_S 205 #define INTREQ__SYSMMU_D1_CSIS_S2_NS 206 #define INTREQ__SYSMMU_D1_CSIS_S2_S 207 #define INTREQ__SYSMMU_D2_CSIS_S1_NS 208 #define INTREQ__SYSMMU_D2_CSIS_S1_S 209 #define INTREQ__SYSMMU_D2_CSIS_S2_NS 210 #define INTREQ__SYSMMU_D2_CSIS_S2_S 211 #define INTREQ__SYSMMU_D3_CSIS_S1_NS 212 #define INTREQ__SYSMMU_D3_CSIS_S1_S 213 #define INTREQ__SYSMMU_D3_CSIS_S2_NS 214 #define INTREQ__SYSMMU_D3_CSIS_S2_S 215 #define INTREQ__ZSL_DMA0 216 #define INTREQ__ZSL_DMA1 217 #define INTREQ__ZSL_DMA2 218 #define INTREQ__DPU_DECON0_DQE_DIMMING_END 219 #define INTREQ__DPU_DECON0_DQE_DIMMING_START 220 #define INTREQ__DPU_DECON0_EXTRA 221 #define INTREQ__HDCP 222 #define INTREQ__TBASE 223 #define INTREQ__SECURE_LOG 224 #define INTREQ__RPMB 225 #define INTREQ__DPU_DECON0_FRAME_DONE 226 #define INTREQ__DPU_DECON0_FRAME_START 227 #define INTREQ__DPU_DECON1_DQE_DIMMING_END 228 #define INTREQ__DPU_DECON1_DQE_DIMMING_START 229 #define INTREQ__DPU_DECON1_EXTRA 230 #define INTREQ__DPU_DECON1_FRAME_DONE 231 #define INTREQ__DPU_DECON1_FRAME_START 232 #define INTREQ__DPU_DMA_DSIMFC0 233 #define INTREQ__DPU_DMA_L0 234 #define INTREQ__DPU_DMA_L1 235 #define INTREQ__DPU_DMA_L2 236 #define INTREQ__DPU_DMA_L3 237 #define INTREQ__DPU_DMA_L4 238 #define INTREQ__DPU_DMA_L5 239 #define INTREQ__DPU_DMA_L6 240 #define INTREQ__DPU_DMA_L7 241 #define INTREQ__DPU_DMA_RCD0 242 #define INTREQ__DPU_DMA_WB 243 #define INTREQ__DPU_DPP_L0 244 #define INTREQ__DPU_DPP_L1 245 #define INTREQ__DPU_DPP_L2 246 #define INTREQ__DPU_DPP_L3 247 #define INTREQ__DPU_DPP_L4 248 #define INTREQ__DPU_DPP_L5 249 #define INTREQ__DPU_DPP_L6 250 #define INTREQ__DPU_DPP_L7 251 #define INTREQ__DPU_DSIM0 252 #define INTREQ__SYSMMU_D0_DPU_S1_NS 253 #define INTREQ__SYSMMU_D0_DPU_S1_S 254 #define INTREQ__SYSMMU_D0_DPU_S2_NS 255 #define INTREQ__SYSMMU_D0_DPU_S2_S 256 #define INTREQ__SYSMMU_D1_DPU_S1_NS 257 #define INTREQ__SYSMMU_D1_DPU_S1_S 258 #define INTREQ__SYSMMU_D1_DPU_S2_NS 259 #define INTREQ__SYSMMU_D1_DPU_S2_S 260 #define INTREQ__G3D_IRQEVENT 261 #define INTREQ__G3D_IRQGPU 262 #define INTREQ__G3D_IRQJOB 263 #define INTREQ__G3D_IRQMMU 264 #define INTREQ__G3D_O_OCP_THROTT 265 #define INTREQ__SYSMMU_D_G3D_S2_NS 266 #define INTREQ__SYSMMU_D_G3D_S2_S 267 #define INTREQ__GNSS_SW_INT 268 #define INTREQ__GNSS_WAKEUP_INT 269 #define INTREQ__GNSS_WDOG_RESET 270 #define INTREQ__GPIO_HSI 271 #define INTREQ__GPIO_HSI_UFS 272 #define INTREQ__S2MPU_D_HSI_NS 273 #define INTREQ__S2MPU_D_HSI_S 274 #define INTREQ__UFS_EMBD 275 #define INTREQ__ISP_0 276 #define INTREQ__ISP_1 277 #define INTREQ__SYSMMU_ISP_S1_NS 278 #define INTREQ__SYSMMU_ISP_S1_S 279 #define INTREQ__SYSMMU_ISP_S2_NS 280 #define INTREQ__DERATE_INTR_MIF1 281 #define INTREQ__DMC_INTR_MIF1 282 #define INTREQ__DMC_PEREV_INTR_MIF1 283 #define INTREQ__HIGHTEMP_INTR_MIF1 284 #define INTREQ__NORMTEMP_INTR_MIF1 285 #define INTREQ__PPMU_UPPER_OR_NORMAL_MIF1 286 #define INTREQ__TEMPERR_INTR_MIF1 287 #define INTREQ__SYSMMU_ISP_S2_S 288 #define INTREQ__JPEG0 289 #define INTREQ__MSCL 290 #define INTREQ__SYSMMU_D_M2M_S1_NS 291 #define INTREQ__SYSMMU_D_M2M_S1_S 292 #define INTREQ__SYSMMU_D_M2M_S2_NS 293 #define INTREQ__SYSMMU_D_M2M_S2_S 294 #define INTREQ__GDC_IRQ 295 #define INTREQ__MCSC_IRQ 296 #define INTREQ__ORBMCH_O_INT 297 #define INTREQ__SYSMMU_D0_MCSC_S1_NS 298 #define INTREQ__SYSMMU_D0_MCSC_S1_S 299 #define INTREQ__SYSMMU_D0_MCSC_S2_NS 300 #define INTREQ__SYSMMU_D0_MCSC_S2_S 301 #define INTREQ__SYSMMU_D1_MCSC_S1_NS 302 #define INTREQ__SYSMMU_D1_MCSC_S1_S 303 #define INTREQ__SYSMMU_D1_MCSC_S2_NS 304 #define INTREQ__SYSMMU_D1_MCSC_S2_S 305 #define INTREQ__TREX_D_CAM_DEBUGINTERRUPT 306 #define INTREQ__MFC 307 #define INTREQ__SYSMMU_MFC_INTERRUPT_S1_NS 308 #define INTREQ__SYSMMU_MFC_INTERRUPT_S1_S 309 #define INTREQ__SYSMMU_MFC_INTERRUPT_S2_NS 310 #define INTREQ__SYSMMU_MFC_INTERRUPT_S2_S 311 #define INTREQ__DERATE_INTR_MIF0 312 #define INTREQ__DMC_ASP_INTR_MIF0 313 #define INTREQ__DMC_INTR_MIF0 314 #define INTREQ__DMC_PEREV_INTR_MIF0 315 #define INTREQ__DMC_PPMPU_INTR_MIF0 316 #define INTREQ__HIGHTEMP_INTR_MIF0 317 #define INTREQ__NORMTEMP_INTR_MIF0 318 #define INTREQ__PPMU_UPPER_OR_NORMAL_MIF0 319 #define INTREQ__TEMPERR_INTR_MIF0 320 #define INTREQ__DMC_ASP_INTR_MIF1 321 #define INTREQ__DMC_PPMPU_INTR_MIF1 322 #define INTREQ__RESET_REQ 323 #define SFR_BUS_RDY 324 #define INTREQ__OCP_THROTT_INTR_NPUS 325 #define INTREQ__SYSMMU_D0_NPUS_INTERRUPT_S1_NS 326 #define INTREQ__SYSMMU_D0_NPUS_INTERRUPT_S1_S 327 #define INTREQ__SYSMMU_D0_NPUS_INTERRUPT_S2_NS 328 #define INTREQ__SYSMMU_D0_NPUS_INTERRUPT_S2_S 329 #define INTREQ__SYSMMU_D1_NPUS_INTERRUPT_S1_NS 330 #define INTREQ__SYSMMU_D1_NPUS_INTERRUPT_S1_S 331 #define INTREQ__SYSMMU_D1_NPUS_INTERRUPT_S2_NS 332 #define INTREQ__SYSMMU_D1_NPUS_INTERRUPT_S2_S 333 #define O_INTREQ_NS_NPUS_HOST_0 334 #define O_INTREQ_NS_NPUS_HOST_1 335 #define O_INTREQ_NS_NPUS_HOST_2 336 #define O_INTREQ_NS_NPUS_HOST_3 337 #define O_INTREQ_NS_NPUS_HOST_4 338 #define O_INTREQ_NS_NPUS_HOST_5 339 #define O_INTREQ_NS_NPUS_HOST_6 340 #define O_INTREQ_NS_NPUS_HOST_7 341 #define O_INTREQ_S_NPUS_HOST_0 342 #define O_INTREQ_S_NPUS_HOST_1 343 #define O_INTREQ_S_NPUS_HOST_2 344 #define O_INTREQ_S_NPUS_HOST_3 345 #define O_INTREQ_S_NPUS_HOST_4 346 #define O_INTREQ_S_NPUS_HOST_5 347 #define O_INTREQ_S_NPUS_HOST_6 348 #define O_INTREQ_S_NPUS_HOST_7 349 #define INTREQ__GPIO_PERI 350 #define INTREQ__GPIO_PERIMMC 351 #define INTREQ__MCT_G0 352 #define INTREQ__MCT_G1 353 #define INTREQ__MCT_G2 354 #define INTREQ__MCT_G3 355 #define INTREQ__MCT_L0 356 #define INTREQ__MCT_L1 357 #define INTREQ__MCT_L2 358 #define INTREQ__MCT_L3 359 #define INTREQ__MCT_L4 360 #define INTREQ__MCT_L5 361 #define INTREQ__MCT_L6 362 #define INTREQ__MCT_L7 363 #define INTREQ__MMC_CARD 364 #define INTREQ__OTP_CON_TOP 365 #define INTREQ__PWM0 366 #define INTREQ__PWM1 367 #define INTREQ__PWM2 368 #define INTREQ__PWM3 369 #define INTREQ__PWM4 370 #define INTREQ__S2MPU_D_PERI_S2_NS 371 #define INTREQ__S2MPU_D_PERI_S2_S 372 #define INTREQ__TMU 373 #define INTREQ__UART_DBG 374 #define INTREQ__USI00_I2C 375 #define INTREQ__USI00_USI 376 #define INTREQ__USI01_I2C 377 #define INTREQ__USI01_USI 378 #define INTREQ__USI02_I2C 379 #define INTREQ__USI02_USI 380 #define INTREQ__USI03_I2C 381 #define INTREQ__USI03_USI 382 #define INTREQ__USI04_I2C 383 #define INTREQ__USI04_USI 384 #define INTREQ__USI05_I2C 385 #define INTREQ__USI05_USI 386 #define INTREQ__USI06_I2C 387 #define INTREQ__USI06_USI 388 #define INTREQ__USI07_I2C 389 #define INTREQ__WDT0 390 #define INTREQ__WDT1 391 #define INTREQ__SYSMMU_TAA_S1_NS 392 #define INTREQ__SYSMMU_TAA_S1_S 393 #define INTREQ__SYSMMU_TAA_S2_NS 394 #define INTREQ__SYSMMU_TAA_S2_S 395 #define INTREQ__TAA_CH0_0 396 #define INTREQ__TAA_CH0_1 397 #define INTREQ__TAA_CH1_0 398 #define INTREQ__TAA_CH1_1 399 #define INTREQ__TAA_CH2_0 400 #define INTREQ__TAA_CH2_1 401 #define INTREQ__SYSMMU_D0_TNR_S1_NS 402 #define INTREQ__SYSMMU_D0_TNR_S1_S 403 #define INTREQ__SYSMMU_D0_TNR_S2_NS 404 #define INTREQ__SYSMMU_D0_TNR_S2_S 405 #define INTREQ__SYSMMU_D1_TNR_S1_NS 406 #define INTREQ__SYSMMU_D1_TNR_S1_S 407 #define INTREQ__SYSMMU_D1_TNR_S2_NS 408 #define INTREQ__SYSMMU_D1_TNR_S2_S 409 #define INTREQ__TNR_0 410 #define INTREQ__TNR_1 411 #define INTREQ__S2MPU_D_USB_NS 412 #define INTREQ__S2MPU_D_USB_S 413 #define INTREQ__USB2_REMOTE_CONNECT_GIC 414 #define INTREQ__USB2_REMOTE_TIMER_GIC 415 #define INTREQ__USB2_REMOTE_WAKEUP_GIC 416 #define INTREQ__USB2_REWA_WAKEUP_REQ 417 #define INTREQ__USB20DRD_GIC0 418 #define INTREQ__USB20DRD_GIC1 419 #define INTREQ__USB20_PHY_FSVMINUS_GIC 420 #define INTREQ__USB20_PHY_FSVPLUS_GIC 421 #define WB2AP_CFG_REQ 422 #define WB2AP_WDOG_RESET_REQ_IRQ 423 #define INTREQ__TEEGRIS_EVENT 428 #define INTREQ__TEEGRIS_PANIC 429 #define INTREQ__S2_LV3_TABLE_ALLOC 430 #define INTREQ_SYSMMU_ACEL_D2_MODEM_S 458 #define INTREQ_SYSMMU_ACEL_D2_MODEM_NS 459 #define INTREQ_SYSMMU_ACEL_D_DIT_S 460 #define INTREQ_SYSMMU_ACEL_D_DIT_NS 461 #define INTREQ__TREX_D_CORE_MODEM1 462 #define INTREQ__TREX_D_CORE_CORE1 463 #define INTREQ__PUF_UNCORRECT_INT 464 #define INTREQ__PUF_SEC_INT 465 #define INTREQ__CORE_CON_ALIVE_INTERRUPT 466 #define INTREQ__HWSEMA_ACK_INT 467 #define INTREQ__HWSEMA_TIMEOUT 468 #define INTREQ__HWSEMA_INT 469 #define INTREQ__HWSEMA_DMA 470 #define INTREQ__HWSEMA_KM 471 #define INTREQ__TREX_D_NRT_DEBUG_INT 472 #define INTREQ__TREX_P_CORE_DEBUG_INT 473 #define INTREQ__TREX_D_CORE_DEBUG_INT 474 #define INTREQ__DIT_RX2_END 475 #define INTREQ__DIT_RX1_END 476 #define INTREQ__DIT_RX0_END 477 #define INTREQ__DIT_TX_END 478 #define INTREQ__DIT_BUS_ERR 479 #endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_S5E8825_H */