/dts-v1/;

/ {
	interrupt-parent = <0x01>;
	#address-cells = <0x02>;
	#size-cells = <0x02>;
	model = "Xiaomi Redmi Note 7";
	compatible = "xiaomi,lavender", "qcom,sdm660";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	clocks {

		xo_board {
			compatible = "fixed-clock";
			#clock-cells = <0x00>;
			clock-frequency = <0x124f800>;
			clock-output-names = "xo_board";
			phandle = <0x0f>;
		};

		sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0x00>;
			clock-frequency = <0x7ffc>;
			clock-output-names = "sleep_clk";
			phandle = <0x10>;
		};
	};

	cpus {
		#address-cells = <0x02>;
		#size-cells = <0x00>;

		cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo260";
			reg = <0x00 0x100>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x400>;
			next-level-cache = <0x02>;
			phandle = <0x08>;

			l2-cache {
				compatible = "cache";
				cache-level = <0x02>;
				phandle = <0x02>;
			};

			l1-icache {
				compatible = "cache";
				phandle = <0x11>;
			};

			l1-dcache {
				compatible = "cache";
				phandle = <0x12>;
			};
		};

		cpu@101 {
			device_type = "cpu";
			compatible = "qcom,kryo260";
			reg = <0x00 0x101>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x400>;
			next-level-cache = <0x02>;
			phandle = <0x09>;

			l1-icache {
				compatible = "cache";
				phandle = <0x13>;
			};

			l1-dcache {
				compatible = "cache";
				phandle = <0x14>;
			};
		};

		cpu@102 {
			device_type = "cpu";
			compatible = "qcom,kryo260";
			reg = <0x00 0x102>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x400>;
			next-level-cache = <0x02>;
			phandle = <0x0a>;

			l1-icache {
				compatible = "cache";
				phandle = <0x15>;
			};

			l1-dcache {
				compatible = "cache";
				phandle = <0x16>;
			};
		};

		cpu@103 {
			device_type = "cpu";
			compatible = "qcom,kryo260";
			reg = <0x00 0x103>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x400>;
			next-level-cache = <0x02>;
			phandle = <0x0b>;

			l1-icache {
				compatible = "cache";
				phandle = <0x17>;
			};

			l1-dcache {
				compatible = "cache";
				phandle = <0x18>;
			};
		};

		cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo260";
			reg = <0x00 0x00>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x280>;
			next-level-cache = <0x03>;
			phandle = <0x04>;

			l2-cache {
				compatible = "cache";
				cache-level = <0x02>;
				phandle = <0x03>;
			};

			l1-icache {
				compatible = "cache";
				phandle = <0x19>;
			};

			l1-dcache {
				compatible = "cache";
				phandle = <0x1a>;
			};
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "qcom,kryo260";
			reg = <0x00 0x01>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x280>;
			next-level-cache = <0x03>;
			phandle = <0x05>;

			l1-icache {
				compatible = "cache";
				phandle = <0x1b>;
			};

			l1-dcache {
				compatible = "cache";
				phandle = <0x1c>;
			};
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "qcom,kryo260";
			reg = <0x00 0x02>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x280>;
			next-level-cache = <0x03>;
			phandle = <0x06>;

			l1-icache {
				compatible = "cache";
				phandle = <0x1d>;
			};

			l1-dcache {
				compatible = "cache";
				phandle = <0x1e>;
			};
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "qcom,kryo260";
			reg = <0x00 0x03>;
			enable-method = "psci";
			capacity-dmips-mhz = <0x280>;
			next-level-cache = <0x03>;
			phandle = <0x07>;

			l1-icache {
				compatible = "cache";
				phandle = <0x1f>;
			};

			l1-dcache {
				compatible = "cache";
				phandle = <0x20>;
			};
		};

		cpu-map {

			cluster0 {

				core0 {
					cpu = <0x04>;
				};

				core1 {
					cpu = <0x05>;
				};

				core2 {
					cpu = <0x06>;
				};

				core3 {
					cpu = <0x07>;
				};
			};

			cluster1 {

				core0 {
					cpu = <0x08>;
				};

				core1 {
					cpu = <0x09>;
				};

				core2 {
					cpu = <0x0a>;
				};

				core3 {
					cpu = <0x0b>;
				};
			};
		};
	};

	firmware {

		scm {
			compatible = "qcom,scm";
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00 0x00 0x00 0x00>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <0x01 0x01 0x08 0x01 0x02 0x08 0x01 0x03 0x08 0x01 0x00 0x08>;
	};

	soc {
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		ranges = <0x00 0x00 0x00 0xffffffff>;
		compatible = "simple-bus";
		phandle = <0x21>;

		clock-controller@100000 {
			compatible = "qcom,gcc-sdm660";
			#clock-cells = <0x01>;
			#reset-cells = <0x01>;
			#power-domain-cells = <0x01>;
			reg = <0x100000 0x94000>;
			phandle = <0x0d>;
		};

		pinctrl@3100000 {
			compatible = "qcom,sdm660-pinctrl";
			reg = <0x3100000 0x400000 0x3500000 0x400000 0x3900000 0x400000>;
			reg-names = "south", "center", "north";
			interrupts = <0x00 0xd0 0x04>;
			gpio-controller;
			gpio-ranges = <0x0c 0x00 0x00 0x72>;
			#gpio-cells = <0x02>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			gpio-reserved-ranges = <0x08 0x04>;
			phandle = <0x0c>;

			uart_console_active {
				phandle = <0x0e>;

				pinmux {
					pins = "gpio4", "gpio5";
					function = "blsp_uart2";
				};

				pinconf {
					pins = "gpio4", "gpio5";
					drive-strength = <0x02>;
					bias-disable;
				};
			};
		};

		spmi@800f000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0x800f000 0x1000 0x8400000 0x1000000 0x9400000 0x1000000 0xa400000 0x220000 0x800a000 0x3000>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <0x00 0x146 0x04>;
			qcom,ee = <0x00>;
			qcom,channel = <0x00>;
			#address-cells = <0x02>;
			#size-cells = <0x00>;
			interrupt-controller;
			#interrupt-cells = <0x04>;
			cell-index = <0x00>;
			phandle = <0x22>;
		};

		serial@c170000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xc170000 0x1000>;
			interrupts = <0x00 0x6c 0x04>;
			clocks = <0x0d 0x23 0x0d 0x19>;
			clock-names = "core", "iface";
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <0x0e>;
			phandle = <0x23>;
		};

		timer@17920000 {
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0x17920000 0x1000>;

			frame@17921000 {
				frame-number = <0x00>;
				interrupts = <0x00 0x08 0x04 0x00 0x07 0x04>;
				reg = <0x17921000 0x1000 0x17922000 0x1000>;
			};

			frame@17923000 {
				frame-number = <0x01>;
				interrupts = <0x00 0x09 0x04>;
				reg = <0x17923000 0x1000>;
				status = "disabled";
			};

			frame@17924000 {
				frame-number = <0x02>;
				interrupts = <0x00 0x0a 0x04>;
				reg = <0x17924000 0x1000>;
				status = "disabled";
			};

			frame@17925000 {
				frame-number = <0x03>;
				interrupts = <0x00 0x0b 0x04>;
				reg = <0x17925000 0x1000>;
				status = "disabled";
			};

			frame@17926000 {
				frame-number = <0x04>;
				interrupts = <0x00 0x0c 0x04>;
				reg = <0x17926000 0x1000>;
				status = "disabled";
			};

			frame@17927000 {
				frame-number = <0x05>;
				interrupts = <0x00 0x0d 0x04>;
				reg = <0x17927000 0x1000>;
				status = "disabled";
			};

			frame@17928000 {
				frame-number = <0x06>;
				interrupts = <0x00 0x0e 0x04>;
				reg = <0x17928000 0x1000>;
				status = "disabled";
			};
		};

		interrupt-controller@17a00000 {
			compatible = "arm,gic-v3";
			reg = <0x17a00000 0x10000 0x17b00000 0x100000>;
			#interrupt-cells = <0x03>;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges;
			interrupt-controller;
			#redistributor-regions = <0x01>;
			redistributor-stride = <0x00 0x20000>;
			interrupts = <0x01 0x09 0x04>;
			phandle = <0x01>;
		};
	};

	aliases {
		serial0 = "/soc/serial@c170000";
	};

	reserved-memory {
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;

		ramoops@a0000000 {
			compatible = "ramoops";
			reg = <0x00 0xa0000000 0x00 0x400000>;
			console-size = <0x20000>;
			record-size = <0x20000>;
			ftrace-size = <0x00>;
			pmsg-size = <0x20000>;
		};
	};

	__symbols__ {
		xo_board = "/clocks/xo_board";
		sleep_clk = "/clocks/sleep_clk";
		CPU0 = "/cpus/cpu@100";
		L2_1 = "/cpus/cpu@100/l2-cache";
		L1_I_100 = "/cpus/cpu@100/l1-icache";
		L1_D_100 = "/cpus/cpu@100/l1-dcache";
		CPU1 = "/cpus/cpu@101";
		L1_I_101 = "/cpus/cpu@101/l1-icache";
		L1_D_101 = "/cpus/cpu@101/l1-dcache";
		CPU2 = "/cpus/cpu@102";
		L1_I_102 = "/cpus/cpu@102/l1-icache";
		L1_D_102 = "/cpus/cpu@102/l1-dcache";
		CPU3 = "/cpus/cpu@103";
		L1_I_103 = "/cpus/cpu@103/l1-icache";
		L1_D_103 = "/cpus/cpu@103/l1-dcache";
		CPU4 = "/cpus/cpu@0";
		L2_0 = "/cpus/cpu@0/l2-cache";
		L1_I_0 = "/cpus/cpu@0/l1-icache";
		L1_D_0 = "/cpus/cpu@0/l1-dcache";
		CPU5 = "/cpus/cpu@1";
		L1_I_1 = "/cpus/cpu@1/l1-icache";
		L1_D_1 = "/cpus/cpu@1/l1-dcache";
		CPU6 = "/cpus/cpu@2";
		L1_I_2 = "/cpus/cpu@2/l1-icache";
		L1_D_2 = "/cpus/cpu@2/l1-dcache";
		CPU7 = "/cpus/cpu@3";
		L1_I_3 = "/cpus/cpu@3/l1-icache";
		L1_D_3 = "/cpus/cpu@3/l1-dcache";
		soc = "/soc";
		gcc = "/soc/clock-controller@100000";
		tlmm = "/soc/pinctrl@3100000";
		uart_console_active = "/soc/pinctrl@3100000/uart_console_active";
		spmi_bus = "/soc/spmi@800f000";
		blsp1_uart2 = "/soc/serial@c170000";
		intc = "/soc/interrupt-controller@17a00000";
	};
};