/* SPDX-License-Identifier: GPL-2.0 */ /* * Samsung Exynos SoC series dsp driver * * Copyright (c) 2019 Samsung Electronics Co., Ltd. * http://www.samsung.com/ */ #ifndef __HW_P0_DSP_HW_P0_CTRL_H__ #define __HW_P0_DSP_HW_P0_CTRL_H__ #include "dsp-ctrl.h" enum dsp_p0_reg_id { /* REG_DNC_CTRL_NS */ DSP_P0_DNCC_NS_VERSION, DSP_P0_DNCC_NS_CLOCK_CONFIG, DSP_P0_DNCC_NS_CPU_AxUSER_AxCACHE, DSP_P0_DNCC_NS_HOST_BUS_RESP_ENABLE, DSP_P0_DNCC_NS_WDT_CNT_EN, DSP_P0_DNCC_NS_STM_CTRL, DSP_P0_DNCC_NS_STM_FUNC$, DSP_P0_DNCC_NS_OTF_BASE_ADDR, DSP_P0_DNCC_NS_OTF_STRIDE, DSP_P0_DNCC_NS_OTF_FORMAT, DSP_P0_DNCC_NS_OTF_STATUS, DSP_P0_DNCC_NS_DBG_ENABLE, DSP_P0_DNCC_NS_DBG_REG0, DSP_P0_DNCC_NS_DBG_REG1, DSP_P0_DNCC_NS_DBG_REG2, DSP_P0_DNCC_NS_DBG_REG3, DSP_P0_DNCC_NS_STATUS_INT_BUS_SECURE_ERROR_RD, DSP_P0_DNCC_NS_STATUS_INT_BUS_SECURE_ERROR_WR, DSP_P0_DNCC_NS_STATUS_INT_BUS_ERROR_RD, DSP_P0_DNCC_NS_STATUS_INT_BUS_ERROR_WR, DSP_P0_DNCC_NS_STATUS_MOCK$, DSP_P0_DNCC_NS_IRQ_DBG_STATUS_FR_PBOX, DSP_P0_DNCC_NS_IRQ_DBG_MSTATUS_FR_PBOX, DSP_P0_DNCC_NS_IRQ_DBG_ENABLE_FR_PBOX, DSP_P0_DNCC_NS_IRQ_DBG_CLR_FR_PBOX, DSP_P0_DNCC_NS_IRQ_STATUS_TO_CC, DSP_P0_DNCC_NS_IRQ_MSTATUS_TO_CC, DSP_P0_DNCC_NS_IRQ_ENABLE_TO_CC, DSP_P0_DNCC_NS_IRQ_SET_TO_CC, DSP_P0_DNCC_NS_IRQ_CLR_TO_CC, DSP_P0_DNCC_NS_IRQ_STATUS_TO_HOST, DSP_P0_DNCC_NS_IRQ_MSTATUS_TO_HOST, DSP_P0_DNCC_NS_IRQ_ENABLE_TO_HOST, DSP_P0_DNCC_NS_IRQ_SET_TO_HOST, DSP_P0_DNCC_NS_IRQ_CLR_TO_HOST, DSP_P0_DNCC_NS_IRQ_STATUS_FR_CC_TO_GNPU0, DSP_P0_DNCC_NS_IRQ_MSTATUS_FR_CC_TO_GNPU0, DSP_P0_DNCC_NS_IRQ_ENABLE_FR_CC_TO_GNPU0, DSP_P0_DNCC_NS_IRQ_SET_FR_CC_TO_GNPU0, DSP_P0_DNCC_NS_IRQ_CLR_FR_CC_TO_GNPU0, DSP_P0_DNCC_NS_IRQ_STATUS_FR_CC_TO_GNPU1, DSP_P0_DNCC_NS_IRQ_MSTATUS_FR_CC_TO_GNPU1, DSP_P0_DNCC_NS_IRQ_ENABLE_FR_CC_TO_GNPU1, DSP_P0_DNCC_NS_IRQ_SET_FR_CC_TO_GNPU1, DSP_P0_DNCC_NS_IRQ_CLR_FR_CC_TO_GNPU1, DSP_P0_DNCC_NS_IRQ_STATUS_FR_GNPU_TO_CC, DSP_P0_DNCC_NS_IRQ_MSTATUS_FR_GNPU_TO_CC, DSP_P0_DNCC_NS_IRQ_ENABLE_FR_GNPU_TO_CC, DSP_P0_DNCC_NS_IRQ_SET_FR_GNPU_TO_CC, DSP_P0_DNCC_NS_IRQ_CLR_FR_GNPU_TO_CC, DSP_P0_DNCC_NS_IRQ_DBG_STATUS_TO_SRESETN, DSP_P0_DNCC_NS_IRQ_DBG_MSTATUS_TO_SRESETN, DSP_P0_DNCC_NS_IRQ_DBG_ENABLE_TO_SRESETN, DSP_P0_DNCC_NS_IRQ_DBG_CLR_TO_SRESETN, DSP_P0_DNCC_NS_IRQ_MBOX_ENABLE_FR_CC, DSP_P0_DNCC_NS_IRQ_MBOX_ENABLE_TO_CC, DSP_P0_DNCC_NS_IRQ_MBOX_STATUS_FR_CC, DSP_P0_DNCC_NS_IRQ_MBOX_STATUS_TO_CC, DSP_P0_DNCC_NS_IRQ_MBOX_MSTATUS_FR_CC, DSP_P0_DNCC_NS_IRQ_MBOX_MSTATUS_TO_CC, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_HOST_INTR, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_HOST$, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_ABOX_INTR, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_ABOX$, DSP_P0_DNCC_NS_MBOX_FR_HOST_TO_CC_INTR, DSP_P0_DNCC_NS_MBOX_FR_HOST_TO_CC$, DSP_P0_DNCC_NS_MBOX_FR_ABOX_TO_CC_INTR, DSP_P0_DNCC_NS_MBOX_FR_ABOX_TO_CC$, DSP_P0_DNCC_NS_MBOX_FR_IVP0_TH0_TO_CC_INTR, DSP_P0_DNCC_NS_MBOX_FR_IVP0_TH0_TO_CC$, DSP_P0_DNCC_NS_MBOX_FR_IVP0_TH1_TO_CC_INTR, DSP_P0_DNCC_NS_MBOX_FR_IVP0_TH1_TO_CC$, DSP_P0_DNCC_NS_MBOX_FR_IVP1_TH0_TO_CC_INTR, DSP_P0_DNCC_NS_MBOX_FR_IVP1_TH0_TO_CC$, DSP_P0_DNCC_NS_MBOX_FR_IVP1_TH1_TO_CC_INTR, DSP_P0_DNCC_NS_MBOX_FR_IVP1_TH1_TO_CC$, DSP_P0_DNCC_NS_MBOX_FR_IVP2_TH0_TO_CC_INTR, DSP_P0_DNCC_NS_MBOX_FR_IVP2_TH0_TO_CC$, DSP_P0_DNCC_NS_MBOX_FR_IVP2_TH1_TO_CC_INTR, DSP_P0_DNCC_NS_MBOX_FR_IVP2_TH1_TO_CC$, DSP_P0_DNCC_NS_MBOX_FR_IVP3_TH0_TO_CC_INTR, DSP_P0_DNCC_NS_MBOX_FR_IVP3_TH0_TO_CC$, DSP_P0_DNCC_NS_MBOX_FR_IVP3_TH1_TO_CC_INTR, DSP_P0_DNCC_NS_MBOX_FR_IVP3_TH1_TO_CC$, DSP_P0_DNCC_NS_MBOX_FR_GNPU0_TO_CC_INTR, DSP_P0_DNCC_NS_MBOX_FR_GNPU0_TO_CC$, DSP_P0_DNCC_NS_MBOX_FR_GNPU1_TO_CC_INTR, DSP_P0_DNCC_NS_MBOX_FR_GNPU1_TO_CC$, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_GNPU0_0_INTR, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_GNPU0_0, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_GNPU0_1_INTR, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_GNPU0_1, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_GNPU0_2_INTR, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_GNPU0_2, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_GNPU0_3_INTR, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_GNPU0_3, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_GNPU1_0_INTR, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_GNPU1_0, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_GNPU1_1_INTR, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_GNPU1_1, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_GNPU1_2_INTR, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_GNPU1_2, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_GNPU1_3_INTR, DSP_P0_DNCC_NS_MBOX_FR_CC_TO_GNPU1_3, /* REG_CPU_SS */ DSP_P0_DNC_CPU_REMAPS0_NS, DSP_P0_DNC_CPU_REMAPS1, DSP_P0_DNC_CPU_REMAPD0_NS, DSP_P0_DNC_CPU_REMAPD1, DSP_P0_DNC_CPU_RUN, DSP_P0_DNC_CPU_EVENT, DSP_P0_DNC_CPU_RELEASE, DSP_P0_DNC_CPU_RELEASE_NS, DSP_P0_DNC_CPU_CFGEND, DSP_P0_DNC_CPU_CFGTE, DSP_P0_DNC_CPU_VINITHI, DSP_P0_DNC_CPU_EVENT_STATUS, DSP_P0_DNC_CPU_WFI_STATUS, DSP_P0_DNC_CPU_WFE_STATUS, DSP_P0_DNC_CPU_PC_L, DSP_P0_DNC_CPU_PC_H, DSP_P0_DNC_CPU_ACTIVE_CNT_L, DSP_P0_DNC_CPU_ACTIVE_CNT_H, DSP_P0_DNC_CPU_STALL_CNT, DSP_P0_DNC_CPU_ALIVE_CTRL, /* REG_DSP0_CTRL */ DSP_P0_DSP0_CTRL_BUSACTREQ, DSP_P0_DSP0_CTRL_SWRESET, DSP_P0_DSP0_CTRL_CORE_ID, DSP_P0_DSP0_CTRL_PERF_MON_ENABLE, DSP_P0_DSP0_CTRL_PERF_MON_CLEAR, DSP_P0_DSP0_CTRL_DBG_MON_ENABLE, DSP_P0_DSP0_CTRL_DBG_INTR_STATUS, DSP_P0_DSP0_CTRL_DBG_INTR_ENABLE, DSP_P0_DSP0_CTRL_DBG_INTR_CLEAR, DSP_P0_DSP0_CTRL_DBG_INTR_MSTATUS, DSP_P0_DSP0_CTRL_IVP_SFR2AXI_SGMO, DSP_P0_DSP0_CTRL_SRESET_DONE_STATUS, DSP_P0_DSP0_CTRL_VM_STATCK_START$, DSP_P0_DSP0_CTRL_VM_STATCK_END$, DSP_P0_DSP0_CTRL_VM_MODE, DSP_P0_DSP0_CTRL_PERF_IVP0_TH0_PC, DSP_P0_DSP0_CTRL_PERF_IVP0_TH0_VALID_CNTL, DSP_P0_DSP0_CTRL_PERF_IVP0_TH0_VALID_CNTH, DSP_P0_DSP0_CTRL_PERF_IVP0_TH0_STALL_CNT, DSP_P0_DSP0_CTRL_PERF_IVP0_TH1_PC, DSP_P0_DSP0_CTRL_PERF_IVP0_TH1_VALID_CNTL, DSP_P0_DSP0_CTRL_PERF_IVP0_TH1_VALID_CNTH, DSP_P0_DSP0_CTRL_PERF_IVP0_TH1_STALL_CNT, DSP_P0_DSP0_CTRL_PERF_IVP0_IC_REQL, DSP_P0_DSP0_CTRL_PERF_IVP0_IC_REQH, DSP_P0_DSP0_CTRL_PERF_IVP0_IC_MISS, DSP_P0_DSP0_CTRL_PERF_IVP0_INST_CNTL$, DSP_P0_DSP0_CTRL_PERF_IVP0_INST_CNTH$, DSP_P0_DSP0_CTRL_PERF_IVP1_TH0_PC, DSP_P0_DSP0_CTRL_PERF_IVP1_TH0_VALID_CNTL, DSP_P0_DSP0_CTRL_PERF_IVP1_TH0_VALID_CNTH, DSP_P0_DSP0_CTRL_PERF_IVP1_TH0_STALL_CNT, DSP_P0_DSP0_CTRL_PERF_IVP1_TH1_PC, DSP_P0_DSP0_CTRL_PERF_IVP1_TH1_VALID_CNTL, DSP_P0_DSP0_CTRL_PERF_IVP1_TH1_VALID_CNTH, DSP_P0_DSP0_CTRL_PERF_IVP1_TH1_STALL_CNT, DSP_P0_DSP0_CTRL_PERF_IVP1_IC_REQL, DSP_P0_DSP0_CTRL_PERF_IVP1_IC_REQH, DSP_P0_DSP0_CTRL_PERF_IVP1_IC_MISS, DSP_P0_DSP0_CTRL_PERF_IVP1_INST_CNTL$, DSP_P0_DSP0_CTRL_PERF_IVP1_INST_CNTH$, DSP_P0_DSP0_CTRL_DBG_IVP0_ADDR_PM, DSP_P0_DSP0_CTRL_DBG_IVP0_ADDR_DM, DSP_P0_DSP0_CTRL_DBG_IVP0_ERROR_INFO, DSP_P0_DSP0_CTRL_DBG_IVP1_ADDR_PM, DSP_P0_DSP0_CTRL_DBG_IVP1_ADDR_DM, DSP_P0_DSP0_CTRL_DBG_IVP1_ERROR_INFO, DSP_P0_DSP0_CTRL_PERF_IVP0_STALL_CNTL, DSP_P0_DSP0_CTRL_PERF_IVP0_STALL_CNTH, DSP_P0_DSP0_CTRL_PERF_IVP0_SFR_STALL_CNTL, DSP_P0_DSP0_CTRL_PERF_IVP0_SFR_STALL_CNTH, DSP_P0_DSP0_CTRL_PERF_IVP0_VM0_STALL_CNTL, DSP_P0_DSP0_CTRL_PERF_IVP0_VM0_STALL_CNTH, DSP_P0_DSP0_CTRL_PERF_IVP0_VM1_STALL_CNTL, DSP_P0_DSP0_CTRL_PERF_IVP0_VM1_STALL_CNTH, DSP_P0_DSP0_CTRL_PERF_IVP1_STALL_CNTL, DSP_P0_DSP0_CTRL_PERF_IVP1_STALL_CNTH, DSP_P0_DSP0_CTRL_PERF_IVP1_SFR_STALL_CNTL, DSP_P0_DSP0_CTRL_PERF_IVP1_SFR_STALL_CNTH, DSP_P0_DSP0_CTRL_PERF_IVP1_VM0_STALL_CNTL, DSP_P0_DSP0_CTRL_PERF_IVP1_VM0_STALL_CNTH, DSP_P0_DSP0_CTRL_PERF_IVP1_VM1_STALL_CNTL, DSP_P0_DSP0_CTRL_PERF_IVP1_VM1_STALL_CNTH, DSP_P0_DSP0_CTRL_SM_ID$, DSP_P0_DSP0_CTRL_SM_ADDR$, DSP_P0_DSP0_CTRL_IVP0_STM_FUNC_STATUS, DSP_P0_DSP0_CTRL_IVP1_STM_FUNC_STATUS, DSP_P0_DSP0_CTRL_AXI_ERROR_RD, DSP_P0_DSP0_CTRL_AXI_ERROR_WR, DSP_P0_DSP0_CTRL_RD_MOCNT$, DSP_P0_DSP0_CTRL_WR_MOCNT$, DSP_P0_DSP0_CTRL_IVP0_WAKEUP, DSP_P0_DSP0_CTRL_IVP0_INTR_STATUS_TH$, DSP_P0_DSP0_CTRL_IVP0_INTR_ENABLE_TH$, DSP_P0_DSP0_CTRL_IVP0_SWI_SET_TH$, DSP_P0_DSP0_CTRL_IVP0_SWI_CLEAR_TH$, DSP_P0_DSP0_CTRL_IVP0_MASKED_STATUS_TH$, DSP_P0_DSP0_CTRL_IVP0_IC_BASE_ADDR, DSP_P0_DSP0_CTRL_IVP0_IC_CODE_SIZE, DSP_P0_DSP0_CTRL_IVP0_IC_INVALID_REQ, DSP_P0_DSP0_CTRL_IVP0_IC_INVALID_STATUS, DSP_P0_DSP0_CTRL_IVP0_DM_STACK_START$, DSP_P0_DSP0_CTRL_IVP0_DM_STACK_END$, DSP_P0_DSP0_CTRL_IVP0_STATUS, DSP_P0_DSP0_CTRL_IVP1_WAKEUP, DSP_P0_DSP0_CTRL_IVP1_INTR_STATUS_TH$, DSP_P0_DSP0_CTRL_IVP1_INTR_ENABLE_TH$, DSP_P0_DSP0_CTRL_IVP1_SWI_SET_TH$, DSP_P0_DSP0_CTRL_IVP1_SWI_CLEAR_TH$, DSP_P0_DSP0_CTRL_IVP1_MASKED_STATUS_TH$, DSP_P0_DSP0_CTRL_IVP1_IC_BASE_ADDR, DSP_P0_DSP0_CTRL_IVP1_IC_CODE_SIZE, DSP_P0_DSP0_CTRL_IVP1_IC_INVALID_REQ, DSP_P0_DSP0_CTRL_IVP1_IC_INVALID_STATUS, DSP_P0_DSP0_CTRL_IVP1_DM_STACK_START$, DSP_P0_DSP0_CTRL_IVP1_DM_STACK_END$, DSP_P0_DSP0_CTRL_IVP1_STATUS, DSP_P0_DSP0_CTRL_IVP0_MAILBOX_INTR_TH0, DSP_P0_DSP0_CTRL_IVP0_MAILBOX_TH0_$, DSP_P0_DSP0_CTRL_IVP0_MAILBOX_INTR_TH1, DSP_P0_DSP0_CTRL_IVP0_MAILBOX_TH1_$, DSP_P0_DSP0_CTRL_IVP1_MAILBOX_INTR_TH0, DSP_P0_DSP0_CTRL_IVP1_MAILBOX_TH0_$, DSP_P0_DSP0_CTRL_IVP1_MAILBOX_INTR_TH1, DSP_P0_DSP0_CTRL_IVP1_MAILBOX_TH1_$, DSP_P0_DSP0_CTRL_IVP0_MSG_TH0_$, DSP_P0_DSP0_CTRL_IVP0_MSG_TH1_$, DSP_P0_DSP0_CTRL_IVP1_MSG_TH0_$, DSP_P0_DSP0_CTRL_IVP1_MSG_TH1_$, /* REG_DSP1_CTRL */ DSP_P0_DSP1_CTRL_BUSACTREQ, DSP_P0_DSP1_CTRL_SWRESET, DSP_P0_DSP1_CTRL_CORE_ID, DSP_P0_DSP1_CTRL_PERF_MON_ENABLE, DSP_P0_DSP1_CTRL_PERF_MON_CLEAR, DSP_P0_DSP1_CTRL_DBG_MON_ENABLE, DSP_P0_DSP1_CTRL_DBG_INTR_STATUS, DSP_P0_DSP1_CTRL_DBG_INTR_ENABLE, DSP_P0_DSP1_CTRL_DBG_INTR_CLEAR, DSP_P0_DSP1_CTRL_DBG_INTR_MSTATUS, DSP_P0_DSP1_CTRL_IVP_SFR2AXI_SGMO, DSP_P0_DSP1_CTRL_SRESET_DONE_STATUS, DSP_P0_DSP1_CTRL_VM_STATCK_START$, DSP_P0_DSP1_CTRL_VM_STATCK_END$, DSP_P0_DSP1_CTRL_VM_MODE, DSP_P0_DSP1_CTRL_PERF_IVP0_TH0_PC, DSP_P0_DSP1_CTRL_PERF_IVP0_TH0_VALID_CNTL, DSP_P0_DSP1_CTRL_PERF_IVP0_TH0_VALID_CNTH, DSP_P0_DSP1_CTRL_PERF_IVP0_TH0_STALL_CNT, DSP_P0_DSP1_CTRL_PERF_IVP0_TH1_PC, DSP_P0_DSP1_CTRL_PERF_IVP0_TH1_VALID_CNTL, DSP_P0_DSP1_CTRL_PERF_IVP0_TH1_VALID_CNTH, DSP_P0_DSP1_CTRL_PERF_IVP0_TH1_STALL_CNT, DSP_P0_DSP1_CTRL_PERF_IVP0_IC_REQL, DSP_P0_DSP1_CTRL_PERF_IVP0_IC_REQH, DSP_P0_DSP1_CTRL_PERF_IVP0_IC_MISS, DSP_P0_DSP1_CTRL_PERF_IVP0_INST_CNTL$, DSP_P0_DSP1_CTRL_PERF_IVP0_INST_CNTH$, DSP_P0_DSP1_CTRL_PERF_IVP1_TH0_PC, DSP_P0_DSP1_CTRL_PERF_IVP1_TH0_VALID_CNTL, DSP_P0_DSP1_CTRL_PERF_IVP1_TH0_VALID_CNTH, DSP_P0_DSP1_CTRL_PERF_IVP1_TH0_STALL_CNT, DSP_P0_DSP1_CTRL_PERF_IVP1_TH1_PC, DSP_P0_DSP1_CTRL_PERF_IVP1_TH1_VALID_CNTL, DSP_P0_DSP1_CTRL_PERF_IVP1_TH1_VALID_CNTH, DSP_P0_DSP1_CTRL_PERF_IVP1_TH1_STALL_CNT, DSP_P0_DSP1_CTRL_PERF_IVP1_IC_REQL, DSP_P0_DSP1_CTRL_PERF_IVP1_IC_REQH, DSP_P0_DSP1_CTRL_PERF_IVP1_IC_MISS, DSP_P0_DSP1_CTRL_PERF_IVP1_INST_CNTL$, DSP_P0_DSP1_CTRL_PERF_IVP1_INST_CNTH$, DSP_P0_DSP1_CTRL_DBG_IVP0_ADDR_PM, DSP_P0_DSP1_CTRL_DBG_IVP0_ADDR_DM, DSP_P0_DSP1_CTRL_DBG_IVP0_ERROR_INFO, DSP_P0_DSP1_CTRL_DBG_IVP1_ADDR_PM, DSP_P0_DSP1_CTRL_DBG_IVP1_ADDR_DM, DSP_P0_DSP1_CTRL_DBG_IVP1_ERROR_INFO, DSP_P0_DSP1_CTRL_PERF_IVP0_STALL_CNTL, DSP_P0_DSP1_CTRL_PERF_IVP0_STALL_CNTH, DSP_P0_DSP1_CTRL_PERF_IVP0_SFR_STALL_CNTL, DSP_P0_DSP1_CTRL_PERF_IVP0_SFR_STALL_CNTH, DSP_P0_DSP1_CTRL_PERF_IVP0_VM0_STALL_CNTL, DSP_P0_DSP1_CTRL_PERF_IVP0_VM0_STALL_CNTH, DSP_P0_DSP1_CTRL_PERF_IVP0_VM1_STALL_CNTL, DSP_P0_DSP1_CTRL_PERF_IVP0_VM1_STALL_CNTH, DSP_P0_DSP1_CTRL_PERF_IVP1_STALL_CNTL, DSP_P0_DSP1_CTRL_PERF_IVP1_STALL_CNTH, DSP_P0_DSP1_CTRL_PERF_IVP1_SFR_STALL_CNTL, DSP_P0_DSP1_CTRL_PERF_IVP1_SFR_STALL_CNTH, DSP_P0_DSP1_CTRL_PERF_IVP1_VM0_STALL_CNTL, DSP_P0_DSP1_CTRL_PERF_IVP1_VM0_STALL_CNTH, DSP_P0_DSP1_CTRL_PERF_IVP1_VM1_STALL_CNTL, DSP_P0_DSP1_CTRL_PERF_IVP1_VM1_STALL_CNTH, DSP_P0_DSP1_CTRL_SM_ID$, DSP_P0_DSP1_CTRL_SM_ADDR$, DSP_P0_DSP1_CTRL_IVP0_STM_FUNC_STATUS, DSP_P0_DSP1_CTRL_IVP1_STM_FUNC_STATUS, DSP_P0_DSP1_CTRL_AXI_ERROR_RD, DSP_P0_DSP1_CTRL_AXI_ERROR_WR, DSP_P0_DSP1_CTRL_RD_MOCNT$, DSP_P0_DSP1_CTRL_WR_MOCNT$, DSP_P0_DSP1_CTRL_IVP0_WAKEUP, DSP_P0_DSP1_CTRL_IVP0_INTR_STATUS_TH$, DSP_P0_DSP1_CTRL_IVP0_INTR_ENABLE_TH$, DSP_P0_DSP1_CTRL_IVP0_SWI_SET_TH$, DSP_P0_DSP1_CTRL_IVP0_SWI_CLEAR_TH$, DSP_P0_DSP1_CTRL_IVP0_MASKED_STATUS_TH$, DSP_P0_DSP1_CTRL_IVP0_IC_BASE_ADDR, DSP_P0_DSP1_CTRL_IVP0_IC_CODE_SIZE, DSP_P0_DSP1_CTRL_IVP0_IC_INVALID_REQ, DSP_P0_DSP1_CTRL_IVP0_IC_INVALID_STATUS, DSP_P0_DSP1_CTRL_IVP0_DM_STACK_START$, DSP_P0_DSP1_CTRL_IVP0_DM_STACK_END$, DSP_P0_DSP1_CTRL_IVP0_STATUS, DSP_P0_DSP1_CTRL_IVP1_WAKEUP, DSP_P0_DSP1_CTRL_IVP1_INTR_STATUS_TH$, DSP_P0_DSP1_CTRL_IVP1_INTR_ENABLE_TH$, DSP_P0_DSP1_CTRL_IVP1_SWI_SET_TH$, DSP_P0_DSP1_CTRL_IVP1_SWI_CLEAR_TH$, DSP_P0_DSP1_CTRL_IVP1_MASKED_STATUS_TH$, DSP_P0_DSP1_CTRL_IVP1_IC_BASE_ADDR, DSP_P0_DSP1_CTRL_IVP1_IC_CODE_SIZE, DSP_P0_DSP1_CTRL_IVP1_IC_INVALID_REQ, DSP_P0_DSP1_CTRL_IVP1_IC_INVALID_STATUS, DSP_P0_DSP1_CTRL_IVP1_DM_STACK_START$, DSP_P0_DSP1_CTRL_IVP1_DM_STACK_END$, DSP_P0_DSP1_CTRL_IVP1_STATUS, DSP_P0_DSP1_CTRL_IVP0_MAILBOX_INTR_TH0, DSP_P0_DSP1_CTRL_IVP0_MAILBOX_TH0_$, DSP_P0_DSP1_CTRL_IVP0_MAILBOX_INTR_TH1, DSP_P0_DSP1_CTRL_IVP0_MAILBOX_TH1_$, DSP_P0_DSP1_CTRL_IVP1_MAILBOX_INTR_TH0, DSP_P0_DSP1_CTRL_IVP1_MAILBOX_TH0_$, DSP_P0_DSP1_CTRL_IVP1_MAILBOX_INTR_TH1, DSP_P0_DSP1_CTRL_IVP1_MAILBOX_TH1_$, DSP_P0_DSP1_CTRL_IVP0_MSG_TH0_$, DSP_P0_DSP1_CTRL_IVP0_MSG_TH1_$, DSP_P0_DSP1_CTRL_IVP1_MSG_TH0_$, DSP_P0_DSP1_CTRL_IVP1_MSG_TH1_$, DSP_P0_REG_END, }; int dsp_hw_p0_ctrl_register_ops(void); #endif