#ifndef __CMUCAL_QCH_H__ #define __CMUCAL_QCH_H__ #include "../../cmucal.h" enum qch_id { ALIVE_CMU_ALIVE_QCH = QCH_TYPE, APBIF_GPIO_ALIVE_QCH, APBIF_INTCOMB_VGPIO2AP_QCH, APBIF_INTCOMB_VGPIO2APM_QCH, APBIF_INTCOMB_VGPIO2PMU_QCH, APBIF_PMU_ALIVE_QCH, APM_DMA_QCH_APB, CHUB_RTC_QCH, CLKMON_QCH, DBGCORE_UART_QCH, DTZPC_ALIVE_QCH, GREBEINTEGRATION_QCH_GREBE, GREBEINTEGRATION_QCH_DBG, HW_SCANDUMP_CLKSTOP_CTRL_QCH, INTMEM_QCH, LH_AXI_SI_D_APM_QCH, MAILBOX_APM_AP_QCH, MAILBOX_APM_AUD_QCH, MAILBOX_APM_CHUB_QCH, MAILBOX_APM_CP_QCH, MAILBOX_APM_CP_1_QCH, MAILBOX_APM_GNSS_QCH, MAILBOX_APM_VTS_QCH, MAILBOX_AP_CHUB_QCH, MAILBOX_AP_CP_QCH, MAILBOX_AP_CP_S_QCH, MAILBOX_AP_DBGCORE_QCH, MAILBOX_AP_GNSS_QCH, MAILBOX_CP_CHUB_QCH, MAILBOX_CP_GNSS_QCH, MAILBOX_GNSS_CHUB_QCH, MAILBOX_SHARED_SRAM_QCH, MCT_ALIVE_QCH, PMU_QCH_PMU, PMU_QCH_PMLINK, PMU_INTR_GEN_QCH, RSTNSYNC_CLK_ALIVE_GREBE_QCH, RTC_QCH, SLH_AXI_MI_ID_DBGCORE_QCH, SLH_AXI_MI_LD_CHUBVTS_QCH, SLH_AXI_MI_LD_GNSS_QCH, SLH_AXI_MI_LP_MODEM_QCH, SLH_AXI_MI_P_APM_QCH, SLH_AXI_SI_IP_APM_QCH, SLH_AXI_SI_LP_ALIVEDNC_QCH, SLH_AXI_SI_LP_CHUBVTS_QCH, SLH_AXI_SI_LP_CMGP_QCH, SLH_AXI_SI_LP_PPU_QCH, SPC_ALIVE_QCH, SPMI_MASTER_PMIC_QCH_P, SPMI_MASTER_PMIC_QCH_S, SWEEPER_P_ALIVE_QCH, SYSREG_ALIVE_QCH, TOP_RTC_QCH, VGEN_LITE_ALIVE_QCH, WDT_ALIVE_QCH, ALLCSIS_CMU_ALLCSIS_QCH, CSIS_PDP_QCH_VOTF0, CSIS_PDP_QCH_DMA, CSIS_PDP_QCH_MCB, CSIS_PDP_QCH_VOTF1, CSIS_PDP_QCH_PDP, CSIS_PDP_QCH_PDP_VOTF, LH_AST_MI_OTF0_BRPCSIS_QCH, LH_AST_MI_OTF1_BRPCSIS_QCH, LH_AST_SI_OTF0_CSISCSTAT_QCH, LH_AST_SI_OTF1_CSISCSTAT_QCH, LH_AST_SI_OTF2_CSISCSTAT_QCH, LH_AST_SI_OTF3_CSISCSTAT_QCH, LH_AST_SI_OTF_CSISBRP_QCH, LH_AXI_MI_LP_INT_P0OIS_CSIS_QCH, LH_AXI_SI_D0_CSIS_QCH, LH_AXI_SI_D1_CSIS_QCH, LH_AXI_SI_D2_CSIS_QCH, LH_AXI_SI_LP_INT_P0OIS_CSIS_QCH, LH_AXI_SI_LP_INT_P0P1_CSIS_QCH, OIS_MCU_TOP_QCH, PPMU_D0_QCH, PPMU_D1_QCH, PPMU_D2_QCH, QE_CSIS_WDMA0_QCH, QE_CSIS_WDMA1_QCH, QE_CSIS_WDMA2_QCH, QE_CSIS_WDMA3_QCH, QE_CSIS_WDMA4_QCH, QE_PDP_D0_QCH, RSTNSYNC_CLK_ALLCSIS_NOCD_QCH, RSTNSYNC_CLK_ALLCSIS_NOCP_QCH, RSTNSYNC_CLK_ALLCSIS_OIS_MCU_QCH, RSTNSYNC_CLK_ALLCSIS_OIS_MCU_CPU_SW_RESET_QCH, RSTNSYNC_SR_CLK_ALLCSIS_NOCD_QCH, RSTNSYNC_SR_CLK_ALLCSIS_NOCP_QCH, RSTNSYNC_SR_CLK_ALLCSIS_OIS_MCU_QCH, SIU_G_PPMU_CSIS_QCH, SLH_AST_SI_G_PPMU_CSIS_QCH, SLH_AXI_MI_P_CSIS_QCH, SLH_AXI_SI_LP_CSISPERIC2_QCH, SYSMMU_D0_CSIS_QCH_S1, SYSMMU_D0_CSIS_QCH_S2, SYSMMU_D1_CSIS_QCH_S1, SYSMMU_D1_CSIS_QCH_S2, SYSMMU_D2_CSIS_QCH_S1, SYSMMU_D2_CSIS_QCH_S2, VGEN_LITE_D0_QCH, VGEN_LITE_D1_QCH, ABOX_QCH_ACLK, ABOX_QCH_BCLK_DSIF, ABOX_QCH_BCLK0, ABOX_QCH_BCLK1, ABOX_QCH_BCLK2, ABOX_QCH_BCLK3, ABOX_QCH_CPU, ABOX_QCH_BCLK4, ABOX_QCH_CNT, ABOX_QCH_BCLK5, ABOX_QCH_CCLK_ASB, ABOX_QCH_BCLK6, ABOX_QCH_XCLK0, ABOX_QCH_PCMC_CLK, ABOX_QCH_C2A0, ABOX_QCH_C2A1, ABOX_QCH_XCLK1, ABOX_QCH_XCLK2, ABOX_QCH_CPU0, ABOX_QCH_CPU1, ABOX_QCH_CPU2, ABOX_QCH_NEON0, ABOX_QCH_NEON1, ABOX_QCH_NEON2, ABOX_QCH_L2, ABOX_QCH_CCLK_ACP, ABOX_QCH_ACLK_ACP, ABOX_QCH_ACLK_ASB, AUD_CMU_AUD_QCH, BAAW_D_AUDCHUBVTS_QCH, DFTMUX_AUD_QCH, DMAILBOX_AUD_QCH_PCLK, DMAILBOX_AUD_QCH_ACLK, DMAILBOX_AUD_QCH_CCLK, DMIC_AUD0_QCH_PCLK, DMIC_AUD0_QCH_DMIC, DMIC_AUD1_QCH_PCLK, DMIC_AUD1_QCH_DMIC, DMIC_AUD2_QCH_PCLK, DMIC_AUD2_QCH_DMIC, D_TZPC_AUD_QCH, LH_AXI_MI_PERI_ASB_QCH, LH_AXI_SI_PERI_ASB_QCH, LH_QDI_SI_D_AUD_QCH, MAILBOX_AUD0_QCH, MAILBOX_AUD1_QCH, MAILBOX_AUD2_QCH, MAILBOX_AUD3_QCH, PPMU_AUD_QCH, RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH, RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH, RSTNSYNC_CLK_AUD_CPU2_SW_RESET_QCH, RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH, SERIAL_LIF_QCH_PCLK, SERIAL_LIF_QCH_BCLK, SERIAL_LIF_QCH_ACLK, SERIAL_LIF_QCH_CCLK, SLH_AST_SI_G_PPMU_AUD_QCH, SLH_AXI_MI_LD_HSI0AUD_QCH, SLH_AXI_MI_P_AUD_QCH, SLH_AXI_SI_LD_AUDHSI0_QCH, SLH_AXI_SI_LP_AUDCHUBVTS_QCH, SMMU_AUD_QCH_S1, SMMU_AUD_QCH_S2, SYSREG_AUD_QCH, TREX_AUD_QCH, VGEN_LITE_AUD_QCH, WDT_AUD_QCH, ADD_BRP_QCH, BRP_CMU_BRP_QCH, BUSIF_ADD_BRP_QCH, BYRP_QCH, BYRP_QCH_C2S_ZSL, BYRP_QCH_C2S_BYR, D_TZPC_BRP_QCH, LH_AST_MI_OTF_CSISBRP_QCH, LH_AST_SI_OTF0_BRPCSIS_QCH, LH_AST_SI_OTF1_BRPCSIS_QCH, LH_AST_SI_OTF_BRPMCSC_QCH, LH_AXI_SI_D0_BRP_QCH, LH_AXI_SI_D1_BRP_QCH, LH_AXI_SI_D2_BRP_QCH, L_SIU_BRP_QCH, PPMU_D0_BRP_QCH, PPMU_D1_BRP_QCH, PPMU_D2_BRP_QCH, RGBP_QCH, RGBP_QCH_VOTF0, RGBP_QCH_VOTF1, SLH_AST_SI_G_PPMU_BRP_QCH, SLH_AXI_MI_P_BRP_QCH, SYSMMU_D0_BRP_QCH_S1, SYSMMU_D0_BRP_QCH_S2, SYSMMU_D1_BRP_QCH_S1, SYSMMU_D1_BRP_QCH_S2, SYSMMU_D2_BRP_QCH_S1, SYSMMU_D2_BRP_QCH_S2, SYSREG_BRP_QCH, VGEN_LITE_BYRP_QCH, VGEN_LITE_RGBP_QCH, APBIF_CHUB_COMBINE_WAKEUP_SRC_QCH, APBIF_GPIO_CHUB_QCH, CHUB_CMU_CHUB_QCH, CM4_CHUB_QCH_CPU, I2C_CHUB_QCH, I3C_CHUB_QCH_S, I3C_CHUB_QCH_P, LH_AXI_MI_IP_VC2CHUB_QCH, LH_AXI_SI_ID_CHUB2VC_QCH, MAILBOX_CHUB_ABOX_QCH, MAILBOX_CHUB_DNC_QCH, PWM_CHUB_QCH, SPI_I2C_CHUB0_QCH, SPI_I2C_CHUB1_QCH, SPI_MULTI_SLV_Q_CTRL_CHUB_QCH, SYSREG_CHUB_QCH, SYSREG_COMBINE_CHUB2AP_QCH, SYSREG_COMBINE_CHUB2APM_QCH, TIMER_CHUB_QCH, USI_CHUB0_QCH, USI_CHUB1_QCH, USI_CHUB2_QCH, USI_CHUB3_QCH, WDT_CHUB_QCH, APBIF_UPMU_CHUB_QCH, APB_SEMA_DMAILBOX_QCH, APB_SEMA_PDMA_QCH, BAAW_CHUB_QCH, BAAW_LD_CHUBVTS_QCH, CHUBVTS_CMU_CHUBVTS_QCH, CHUB_ALV_QCH_PMU, DMAILBOX_CHUBVTS_QCH_PCLK, DMAILBOX_CHUBVTS_QCH_ACLK, DMAILBOX_CHUBVTS_QCH_CCLK, D_TZPC_CHUBVTS_QCH, LH_AXI_MI_ID_CHUB2VC_QCH, LH_AXI_MI_ID_VTS2VC_QCH, LH_AXI_SI_IP_VC2CHUB_QCH, LH_AXI_SI_IP_VC2VTS_QCH, MAILBOX_VTS_CHUB_QCH, PDMA_CHUBVTS_QCH, SLH_AXI_MI_LP_AUDCHUBVTS_QCH, SLH_AXI_MI_LP_CHUBVTS_QCH, SLH_AXI_MI_LP_DNCCHUBVTS_QCH, SLH_AXI_SI_LD_CHUBVTS_QCH, SWEEPER_LD_CHUBVTS_QCH, SYSREG_CHUBVTS_QCH, VGEN_LITE_CHUBVTS_QCH, APBIF_GPIO_CMGP_QCH, CMGP_CMU_CMGP_QCH, CMGP_I2C_QCH, D_TZPC_CMGP_QCH, I2C_CMGP2_QCH, I2C_CMGP3_QCH, I2C_CMGP4_QCH, I2C_CMGP5_QCH, I2C_CMGP6_QCH, SLH_AXI_MI_LP_CMGP_QCH, SLH_AXI_SI_LP_CMGPUFD_QCH, SPI_I2C_CMGP0_QCH, SPI_I2C_CMGP1_QCH, SPI_MULTI_SLV_Q_CTRL_CMGP_QCH, SYSREG_CMGP_QCH, SYSREG_CMGP2APM_QCH, SYSREG_CMGP2CHUB_QCH, SYSREG_CMGP2CP_QCH, SYSREG_CMGP2GNSS_QCH, SYSREG_CMGP2PMU_AP_QCH, USI_CMGP0_QCH, USI_CMGP1_QCH, USI_CMGP2_QCH, USI_CMGP3_QCH, USI_CMGP4_QCH, USI_CMGP5_QCH, USI_CMGP6_QCH, CMU_TOP_CMUREF_QCH, DFTMUX_CMU_QCH_CIS_CLK0, DFTMUX_CMU_QCH_CIS_CLK1, DFTMUX_CMU_QCH_CIS_CLK2, DFTMUX_CMU_QCH_CIS_CLK3, DFTMUX_CMU_QCH_CIS_CLK4, DFTMUX_CMU_QCH_CIS_CLK5, DFTMUX_CMU_QCH_CIS_CLK6, DFTMUX_CMU_QCH_CIS_CLK7, ADD_CPUCL0_0_QCH, BUSIF_ADD_CPUCL0_0_QCH, BUSIF_STR_CPUCL0_0_QCH, BUSIF_STR_CPUCL0_0_QCH_CORE, CMU_CPUCL0_CMUREF_QCH, CPUCL0_QCH_CORE0, CPUCL0_QCH_CORE1, CPUCL0_QCH_CORE2, CPUCL0_QCH_CORE3, CPUCL0_QCH_COMPLEX0, CPUCL0_QCH_COMPLEX1, CPUCL0_CMU_CPUCL0_QCH, HTU_CPUCL0_QCH_PCLK, HTU_CPUCL0_QCH_CLK, LH_ATB_SI_IT_DDCLIT_QCH, RSTNSYNC_CLK_CPUCL0_POWERIP_QCH, RSTNSYNC_SR_CLK_CPUCL0_HTU_QCH, RSTNSYNC_SR_CLK_CPUCL0_POWERIP_QCH, STR_CPUCL0_0_QCH, U_DDD_CTRL_CORE__CPUCL0_QCH, BPS_CPUCL0_QCH, BUSIF_DDC_CPUCL0_0_QCH, BUSIF_DDC_CPUCL0_1_QCH, CFM_CPUCL0_QCH, CPUCL0_GLB_CMU_CPUCL0_GLB_QCH, CSSYS_QCH, D_TZPC_CPUCL0_QCH, LH_ATB_MI_IT_CLUSTER0_QCH, LH_ATB_MI_IT_DDCBIG_QCH, LH_ATB_MI_IT_DDCDSU_QCH, LH_ATB_MI_IT_DDCLIT_QCH, LH_ATB_MI_IT_DDCMID0_QCH, LH_ATB_MI_IT_DDCMID1_QCH, LH_ATB_MI_IT_DDCMID2_QCH, LH_ATB_MI_T_BDU_QCH, LH_ATB_MI_T_DDCG3D_QCH, LH_AXI_SI_G_CSSYS_QCH, PMU_PCSM_PM_QCH, RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH, RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH, SECJTAG_QCH, SLH_AXI_MI_G_DBGCORE_QCH, SLH_AXI_MI_IG_CSSYS_QCH, SLH_AXI_MI_IG_DBGCORE_QCH, SLH_AXI_MI_IG_ETR_QCH, SLH_AXI_MI_IG_STM_QCH, SLH_AXI_MI_P_CPUCL0_QCH, SLH_AXI_SI_IG_CSSYS_QCH, SLH_AXI_SI_IG_DBGCORE_QCH, SLH_AXI_SI_IG_ETR_QCH, SLH_AXI_SI_IG_STM_QCH, SYSREG_CPUCL0_QCH, TREX_CPUCL0_QCH, ADD_CPUCL0_1_QCH, BUSIF_ADD_CPUCL0_1_QCH, BUSIF_STR_CPUCL0_1_QCH, BUSIF_STR_CPUCL0_1_QCH_CORE, CMU_CPUCL1_CMUREF_QCH, CPUCL1_QCH_CORE4, CPUCL1_QCH_CORE5, CPUCL1_QCH_CORE6, CPUCL1_CMU_CPUCL1_QCH, HTU_CPUCL1_0_QCH_PCLK, HTU_CPUCL1_0_QCH_CLK, HTU_CPUCL1_1_QCH_PCLK, HTU_CPUCL1_1_QCH_CLK, HTU_CPUCL1_2_QCH_CLK, HTU_CPUCL1_2_QCH_PCLK, LH_ATB_SI_IT_DDCMID0_QCH, LH_ATB_SI_IT_DDCMID1_QCH, LH_ATB_SI_IT_DDCMID2_QCH, RSTNSYNC_CLK_CPUCL1_POWERIP_QCH, RSTNSYNC_SR_CLK_CPUCL1_HTU_QCH, RSTNSYNC_SR_CLK_CPUCL1_POWERIP_QCH, STR_CPUCL0_1_QCH, U_DDD_CTRL_CORE__CPUCL1_0_QCH, U_DDD_CTRL_CORE__CPUCL1_1_QCH, U_DDD_CTRL_CORE__CPUCL1_2_QCH, ADD_CPUCL0_2_QCH, BUSIF_ADD_CPUCL0_2_QCH, BUSIF_STR_CPUCL0_2_QCH, BUSIF_STR_CPUCL0_2_QCH_CORE, CMU_CPUCL2_CMUREF_QCH, CPUCL2_QCH_CORE7, CPUCL2_CMU_CPUCL2_QCH, HTU_CPUCL2_QCH_PCLK, HTU_CPUCL2_QCH_CLK, LH_ATB_SI_IT_DDCBIG_QCH, RSTNSYNC_CLK_CPUCL2_POWERIP_QCH, RSTNSYNC_SR_CLK_CPUCL2_HTU_QCH, RSTNSYNC_SR_CLK_CPUCL2_POWERIP_QCH, STR_CPUCL0_2_QCH, U_DDD_CTRL_CORE__CPUCL2_QCH, CSIS_CMU_CSIS_QCH, D_TZPC_CSIS_QCH, LH_AXI_MI_LP_INT_P0P1_CSIS_QCH, MIPI_PHY_LINK_WRAP_QCH_CSIS0, MIPI_PHY_LINK_WRAP_QCH_CSIS1, MIPI_PHY_LINK_WRAP_QCH_CSIS2, MIPI_PHY_LINK_WRAP_QCH_CSIS3, MIPI_PHY_LINK_WRAP_QCH_CSIS4, MIPI_PHY_LINK_WRAP_QCH_CSIS5, MIPI_PHY_LINK_WRAP_QCH_CSIS6, MIPI_PHY_LINK_WRAP_QCH_UFD, SLH_AST_SI_OTF_CSISUFD_QCH, SLH_AXI_MI_LP_UFDCSIS_QCH, SYSREG_CSIS_QCH, CSTAT_CMU_CSTAT_QCH, D_TZPC_CSTAT_QCH, LH_AST_MI_OTF0_CSISCSTAT_QCH, LH_AST_MI_OTF1_CSISCSTAT_QCH, LH_AST_MI_OTF2_CSISCSTAT_QCH, LH_AST_MI_OTF3_CSISCSTAT_QCH, LH_AXI_SI_D_CSTAT_QCH, PPMU_CSTAT_QCH, SIPU_CSTAT_QCH, SIPU_CSTAT_QCH_C2RD, SIPU_CSTAT_QCH_C2DS, SLH_AST_SI_G_PPMU_CSTAT_QCH, SLH_AXI_MI_P_CSTAT_QCH, SYSMMU_D_CSTAT_QCH_S1, SYSMMU_D_CSTAT_QCH_S2, SYSREG_CSTAT_QCH, VGEN_LITE_CSTAT0_QCH, VGEN_LITE_CSTAT1_QCH, APBIF_S2D_DBGCORE_QCH, ASYNCAHBMASTER_DBGCORE_QCH, DBGCORE_CMU_DBGCORE_QCH, D_TZPC_DBGCORE_QCH, GREBEINTEGRATION_DBGCORE_QCH_DBG, GREBEINTEGRATION_DBGCORE_QCH_GREBE, MDIS_DBGCORE_QCH, MDIS_DBGCORE_QCH_OSC, RSTNSYNC_CLK_DBGCORE_GREBE_QCH, SLH_AXI_MI_IP_APM_QCH, SLH_AXI_SI_G_DBGCORE_QCH, SLH_AXI_SI_G_SCAN2DRAM_QCH, SLH_AXI_SI_ID_DBGCORE_QCH, SYSREG_DBGCORE_QCH, SYSREG_DBGCORE_CORE_QCH, WDT_DBGCORE_QCH, ADD_DNC_QCH, ADM_DAP_DNC_QCH, BAAW_DNCCHUBVTS_QCH, BUSIF_ADD_DNC_QCH, BUSIF_DDD_DNC_QCH, DNC_CMU_DNC_QCH, D_TZPC_DNC_QCH, HTU_DNC_QCH_PCLK, HTU_DNC_QCH_CLK, IP_DNC_QCH, LH_AST_MI_OTF_UFDDNC_QCH, LH_AXI_MI_LD_DSP0DNC_SFR_QCH, LH_AXI_MI_LD_DSP0DNC_SHMEM_QCH, LH_AXI_MI_LD_GNPU0DNC_SHMEM_QCH, LH_AXI_MI_LD_GNPU1DNC_SHMEM_QCH, LH_AXI_MI_LD_RQ_GNPU0_QCH, LH_AXI_MI_LD_RQ_GNPU1_QCH, LH_AXI_MI_LD_SDMADNC_DATA0_QCH, LH_AXI_MI_LD_SDMADNC_DATA1_QCH, LH_AXI_MI_LD_SDMADNC_DATA2_QCH, LH_AXI_MI_LD_SDMADNC_DATA3_QCH, LH_AXI_MI_LD_SDMADNC_DATA4_QCH, LH_AXI_MI_LD_SDMADNC_DATA5_QCH, LH_AXI_MI_LD_SDMADNC_DATA6_QCH, LH_AXI_MI_LD_SDMADNC_DATA7_QCH, LH_AXI_MI_LD_SDMADNC_MMU0_QCH, LH_AXI_MI_LD_SDMADNC_MMU1_QCH, LH_AXI_MI_LD_SDMADNC_MMU2_QCH, LH_AXI_MI_LD_SDMADNC_MMU3_QCH, LH_AXI_MI_LP_IPDNC_QCH, LH_AXI_SI_LD0_GNPU0_QCH, LH_AXI_SI_LD0_GNPU1_QCH, LH_AXI_SI_LD1_GNPU0_QCH, LH_AXI_SI_LD1_GNPU1_QCH, LH_AXI_SI_LD_CTRL_GNPU0_QCH, LH_AXI_SI_LD_CTRL_GNPU1_QCH, LH_AXI_SI_LD_DNCDSP0_DMA_QCH, LH_AXI_SI_LD_DNCDSP0_SFR_QCH, LH_AXI_SI_LP_DNCSDMA_QCH, LH_AXI_SI_LP_IPDNC_QCH, PPMU_IPDNC_QCH, PPMU_SDMA0_QCH, PPMU_SDMA1_QCH, PPMU_SDMA2_QCH, PPMU_SDMA3_QCH, SIU_G_PPMU_DNC_QCH, SLH_AST_SI_G_PPMU_DNC_QCH, SLH_AXI_MI_LD_CMDQ_GNPU0_QCH, SLH_AXI_MI_LD_CMDQ_GNPU1_QCH, SLH_AXI_MI_LD_DSP0DNC_CACHE_QCH, SLH_AXI_MI_LD_UFDDNC_QCH, SLH_AXI_MI_LP_ALIVEDNC_QCH, SLH_AXI_MI_P_DNC_QCH, SLH_AXI_SI_LP_DNCCHUBVTS_QCH, SLH_AXI_SI_LP_DSP0_QCH, SLH_AXI_SI_LP_GNPU0_QCH, SLH_AXI_SI_LP_GNPU1_QCH, SLH_AXI_SI_LP_SDMA_QCH, SYSMMU_IPDNC_QCH_S1, SYSMMU_IPDNC_QCH_S2, SYSMMU_SDMA0_QCH_S1, SYSMMU_SDMA0_QCH_S2, SYSMMU_SDMA1_QCH_S1, SYSMMU_SDMA1_QCH_S2, SYSMMU_SDMA2_QCH_S1, SYSMMU_SDMA2_QCH_S2, SYSMMU_SDMA3_QCH_S1, SYSMMU_SDMA3_QCH_S2, SYSREG_DNC_QCH, TREX_D_DNC_QCH, VGEN_DNC_QCH, VGEN_LITE_DNC_QCH, DPUB_QCH_DECON, DPUB_QCH_ALV_DSIM0, DPUB_QCH_ALV_DSIM1, DPUB_QCH_ALV_DSIM2, DPUB_QCH_OSC_DSIM0, DPUB_QCH_OSC_DSIM1, DPUB_QCH_OSC_DSIM2, DPUB_CMU_DPUB_QCH, D_TZPC_DPUB_QCH, SLH_AXI_MI_P_DPUB_QCH, SYSREG_DPUB_QCH, UPI_M0_QCH, DPUF_QCH_DPUF0, DPUF_QCH_VOTF0, DPUF_QCH_DPUF1, DPUF_QCH_VOTF1, DPUF_QCH_SRAMC, DPUF_CMU_DPUF_QCH, D_TZPC_DPUF_QCH, D_TZPC_DPUF1_QCH, LH_AXI_SI_D1_DPUF_QCH, PPMU_D0_DPUF0_QCH, PPMU_D0_DPUF1_QCH, PPMU_D1_DPUF0_QCH, PPMU_D1_DPUF1_QCH, SIU_DPUF_QCH, SLH_AST_SI_G_PPMU_DPUF_QCH, SLH_AXI_MI_P_DPUF_QCH, SLH_AXI_SI_D0_DPUF_QCH, SYSMMU_D0_DPUF0_QCH_S1, SYSMMU_D0_DPUF0_QCH_S2, SYSMMU_D0_DPUF1_QCH_S1, SYSMMU_D0_DPUF1_QCH_S2, SYSMMU_D1_DPUF0_QCH_S1, SYSMMU_D1_DPUF0_QCH_S2, SYSMMU_D1_DPUF1_QCH_S1, SYSMMU_D1_DPUF1_QCH_S2, SYSREG_DPUF_QCH, DPUF1_QCH_DPUF, DPUF1_QCH_VOTF, DPUF1_CMU_DPUF1_QCH, LH_AXI_SI_D0_DPUF1DPUF0_QCH, LH_AXI_SI_D1_DPUF1DPUF0_QCH, PPMU_DPUF1D0_QCH, PPMU_DPUF1D1_QCH, SIU_DPUF1_QCH, SLH_ASTL_SI_G_PPMU_DPUF1_QCH, SLH_AXI_MI_P_DPUF1_QCH, SYSMMU_DPUF1D0_QCH_S1, SYSMMU_DPUF1D0_QCH_S2, SYSMMU_DPUF1D1_QCH_S1, SYSMMU_DPUF1D1_QCH_S2, SYSREG_DPUF1_QCH, DRCP_QCH, DRCP_CMU_DRCP_QCH, D_TZPC_DRCP_QCH, LH_AST_MI_OTF_YUVPDRCP_QCH, LH_AST_SI_OTF_DRCPMCSC_QCH, LH_AXI_SI_D_DRCP_QCH, PPMU_D_DRCP_QCH, SLH_ASTL_SI_G_PPMU_DRCP_QCH, SLH_AXI_MI_P_DRCP_QCH, SYSMMU_D_DRCP_QCH_S2, SYSMMU_D_DRCP_QCH_S1, SYSREG_DRCP_QCH, VGEN_LITE_D_DRCP_QCH, DSP_CMU_DSP_QCH, D_TZPC_DSP_QCH, IP_DSP_QCH, LH_AST_MI_LD_STRM_SDMADSP_QCH, LH_AXI_MI_LD_DNCDSP_DMA_QCH, LH_AXI_MI_LD_DNCDSP_SFR_QCH, LH_AXI_SI_LD_DSPDNC_SFR_QCH, LH_AXI_SI_LD_DSPDNC_SHMEM_QCH, SLH_AXI_MI_LP_DSP_QCH, SLH_AXI_SI_LD_DSPDNC_CACHE_QCH, SYSREG_DSP_QCH, BUSIF_STR_CPUCL0_3_QCH, BUSIF_STR_CPUCL0_3_QCH_CORE, CLUSTER0_QCH_SCLK, CLUSTER0_QCH_ATCLK, CLUSTER0_QCH_PDBGCLK, CLUSTER0_QCH_PCLK, CLUSTER0_QCH_PERIPHCLK, CLUSTER0_QCH_PPUCLK, CLUSTER0_QCH_GIC, CMU_DSU_CMUREF_QCH, DSU_CMU_DSU_QCH, HTU_DSU_QCH_PCLK, HTU_DSU_QCH_CLK, LH_ACEL_MI_D0_ACP_QCH, LH_ACEL_MI_D1_ACP_QCH, LH_AST_MI_LD_IRI_GICCPU_CLUSTER0_QCH, LH_AST_SI_LD_ICC_CPUGIC_CLUSTER0_QCH, LH_ATB_SI_IT_CLUSTER0_QCH, LH_ATB_SI_IT_DDCDSU_QCH, LH_CHI_SI_D0_CLUSTER0_QCH, LH_CHI_SI_D1_CLUSTER0_QCH, PPC_INSTRRET_CLUSTER0_0_QCH, PPC_INSTRRET_CLUSTER0_1_QCH, PPC_INSTRRUN_CLUSTER0_0_QCH, PPC_INSTRRUN_CLUSTER0_1_QCH, RSTNSYNC_CLK_CLUSTER_ACLK_QCH, RSTNSYNC_CLK_CLUSTER_ATCLK_QCH, RSTNSYNC_CLK_CLUSTER_GICCLK_QCH, RSTNSYNC_CLK_CLUSTER_MPACTCLK_QCH, RSTNSYNC_CLK_CLUSTER_PCLK_QCH, RSTNSYNC_CLK_CLUSTER_PERIPHCLK_QCH, RSTNSYNC_CLK_CLUSTER_PPUCLK_QCH, RSTNSYNC_CLK_CLUSTER_SCLK_QCH, RSTNSYNC_CLK_DSU_POWERIP_QCH, RSTNSYNC_SR_CLK_DSU_HTU_QCH, RSTNSYNC_SR_CLK_DSU_POWERIP_QCH, SLH_AXI_MI_IP_UTILITY_QCH, SLH_AXI_MI_LP_PPU_QCH, SLH_AXI_SI_IP_UTILITY_QCH, SLH_AXI_SI_P_CLUSTER0_NOCL0_QCH, STR_CPUCL0_3_QCH, U_DDD_CTRL_CORE__DSU_QCH, BG3D_PWRCTL_QCH, CFM_G3D_QCH, D_TZPC_G3D_QCH, G3D_CMU_G3D_QCH, SLH_AXI_MI_P_G3D_QCH, SLH_AXI_SI_P_INT_G3D_QCH, SYSREG_G3D_QCH, ADD_APBIF_G3D_QCH, ADD_G3D_QCH, ADM_DAP_G_G3D_QCH, ASB_G3D_QCH_LH_D0_G3D, ASB_G3D_QCH_LH_D1_G3D, ASB_G3D_QCH_LH_D2_G3D, ASB_G3D_QCH_LH_D3_G3D, ASB_G3D_QCH_S_LH_P_G3D, BUSIF_DDC_G3D_QCH, G3DCORE_CMU_G3DCORE_QCH, GPU_QCH_CLK, GPU_QCH_PCLK, HTU_G3D_QCH_PCLK, HTU_G3D_QCH_CLK, LH_ATB_SI_T_DDCG3D_QCH, RSTNSYNC_CLK_G3DCORE_FREE_OSCCLK_QCH, RSTNSYNC_CLK_G3DCORE_NOCP_QCH, RSTNSYNC_CLK_G3D_POWERIP_QCH, RSTNSYNC_SR_CLK_G3DCORE_FREE_OSCCLK_QCH, RSTNSYNC_SR_CLK_G3DCORE_NOCP_QCH, RSTNSYNC_SR_CLK_G3D_POWERIP_QCH, STR_MUX_G3D_QCH_PCLK, STR_MUX_G3D_QCH_CORE, U_DDD_CTRL_CORE__G3D_QCH, D_TZPC_GNPU_QCH, GNPU_CMU_GNPU_QCH, IP_NPUCORE_QCH_CORE, IP_NPUCORE_QCH_SRAM, LH_AXI_MI_LD0_GNPU_QCH, LH_AXI_MI_LD1_GNPU_QCH, LH_AXI_MI_LD_CTRL_GNPU_QCH, LH_AXI_SI_LD_GNPUDNC_SHMEM_QCH, LH_AXI_SI_LD_RQ_GNPU_QCH, SLH_AXI_MI_LP_GNPU_QCH, SLH_AXI_SI_LD_CMDQ_GNPU_QCH, SYSREG_GNPU_QCH, GNSS_CMU_GNSS_QCH, DP_LINK_QCH_OSC_CLK, DP_LINK_QCH_PCLK, DP_LINK_QCH_GTC_CLK, D_TZPC_HSI0_QCH, HSI0_CMU_HSI0_QCH, PPMU_HSI0_BUS1_QCH, SLH_ACEL_SI_D_HSI0_QCH, SLH_AST_SI_G_PPMU_HSI0_QCH, SLH_AXI_MI_LD_AUDHSI0_QCH, SLH_AXI_MI_P_HSI0_QCH, SLH_AXI_SI_LD_HSI0AUD_QCH, SPC_HSI0_QCH, SYSMMU_D_HSI0_QCH, SYSREG_HSI0_QCH, USB32DRD_QCH_S_SUBCTRL, USB32DRD_QCH_S_LINK, USB32DRD_QCH_S_CTRL, USB32DRD_QCH_S_TCA, USB32DRD_QCH_S_EUSBCTL, USB32DRD_QCH_S_EUSBPHY, VGEN_LITE_HSI0_QCH, D_TZPC_HSI1_QCH, GPIO_HSI1_QCH, HSI1_CMU_HSI1_QCH, LH_ACEL_SI_D_HSI1_QCH, PCIE_GEN2_QCH_AXI, PCIE_GEN2_QCH_PCS_APB, PCIE_GEN2_QCH_DBI, PCIE_GEN2_QCH_APB, PCIE_GEN2_QCH_REF, PCIE_GEN2_QCH_PMA_APB, PCIE_GEN2_QCH_UDBG_APB, PCIE_GEN3_QCH_APB, PCIE_GEN3_QCH_DBI, PCIE_GEN3_QCH_AXI, PCIE_GEN3_QCH_PCS_APB, PCIE_GEN3_QCH_REF, PCIE_GEN3_QCH_UDBG_APB, PCIE_GEN3_QCH_PMA_APB, PCIE_IA_GEN2_QCH, PCIE_IA_GEN3_QCH, PPMU_HSI1_QCH, SLH_AST_SI_G_PPMU_HSI1_QCH, SLH_AXI_MI_P_HSI1_QCH, SYSMMU_HSI1_QCH_S1, SYSMMU_HSI1_QCH_S2, SYSREG_HSI1_QCH, VGEN_LITE_HSI1_QCH, D_TZPC_LME_QCH, GDC_QCH, GDC_QCH_C2_M, GDC_QCH_C2_S, LH_ACEL_SI_D_LME_QCH, LH_AXI_MI_ID_LME_QCH, LH_AXI_SI_ID_LME_QCH, LME_QCH_0, LME_CMU_LME_QCH, PPMU_D_LME_QCH, QE_D1_LME_QCH, SLH_AST_SI_G_PPMU_LME_QCH, SLH_AXI_MI_P_LME_QCH, SYSMMU_D_LME_QCH_S1, SYSMMU_D_LME_QCH_S2, SYSREG_LME_QCH, VGEN_LITE_D_GDC_QCH, VGEN_LITE_D_LME_QCH, D_TZPC_M2M_QCH, FRC_MC_QCH, JPEG0_QCH, JPEG1_QCH, JSQZ_QCH, LH_ACEL_SI_D_M2M_QCH, LH_AXI_MI_FRC_MC_QCH, LH_AXI_SI_FRC_MC_QCH, M2M_QCH, M2M_QCH_VOTF, M2M_CMU_M2M_QCH, PPMU_D_M2M_QCH, QE_FRC_MC_QCH, QE_JPEG0_QCH, QE_JPEG1_QCH, QE_JSQZ_QCH, QE_M2M_QCH, SLH_AST_SI_G_PPMU_M2M_QCH, SLH_AXI_MI_P_M2M_QCH, SYSMMU_D_M2M_PM_QCH_S2, SYSMMU_D_M2M_PM_QCH_S1, SYSREG_M2M_QCH, VGEN_LITE_M2M_QCH, D_TZPC_MCSC_QCH, LH_AST_MI_OTF0_YUVPMCSC_QCH, LH_AST_MI_OTF1_YUVPMCSC_QCH, LH_AST_MI_OTF_BRPMCSC_QCH, LH_AST_SI_OTF_MCSCYUVP_QCH, LH_AXI_MI_ID_MCSC0_QCH, LH_AXI_MI_ID_MCSC1_QCH, LH_AXI_MI_ID_MCSC2_QCH, LH_AXI_MI_ID_MCSC3_QCH, LH_AXI_MI_ID_MCSC4_QCH, LH_AXI_MI_ID_MCSC5_QCH, LH_AXI_MI_ID_MCSC6_QCH, LH_AXI_SI_D1_MCSC_QCH, LH_AXI_SI_D2_MCSC_QCH, LH_AXI_SI_D3_MCSC_QCH, LH_AXI_SI_D4_MCSC_QCH, LH_AXI_SI_ID_MCSC0_QCH, LH_AXI_SI_ID_MCSC1_QCH, LH_AXI_SI_ID_MCSC2_QCH, LH_AXI_SI_ID_MCSC3_QCH, LH_AXI_SI_ID_MCSC4_QCH, LH_AXI_SI_ID_MCSC5_QCH, LH_AXI_SI_ID_MCSC6_QCH, MCFP_QCH, MCSC_QCH, MCSC_QCH_C2R, MCSC_QCH_C2W, MCSC_CMU_MCSC_QCH, PPMU_D0_MCSC_QCH, PPMU_D1_MCSC_QCH, PPMU_D2_MCSC_QCH, PPMU_D3_MCSC_QCH, PPMU_D4_MCSC_QCH, SIU_G_PPMU_MCSC_QCH, SLH_AST_SI_G_PPMU_MCSC_QCH, SLH_AXI_MI_P_MCSC_QCH, SLH_AXI_SI_D0_MCSC_QCH, SYSMMU_D0_MCSC_QCH_S1, SYSMMU_D0_MCSC_QCH_S2, SYSMMU_D1_MCSC_QCH_S1, SYSMMU_D1_MCSC_QCH_S2, SYSMMU_D2_MCSC_QCH_S1, SYSMMU_D2_MCSC_QCH_S2, SYSMMU_D3_MCSC_QCH_S1, SYSMMU_D3_MCSC_QCH_S2, SYSMMU_D4_MCSC_QCH_S1, SYSMMU_D4_MCSC_QCH_S2, SYSREG_MCSC_QCH, VGEN_LITE_D0_MCSC_QCH, VGEN_LITE_D1_MCSC_QCH, VGEN_LITE_D2_MCSC_QCH, D_TZPC_MFC0_QCH, LH_AST_MI_OTF0_MFC1MFC0_QCH, LH_AST_MI_OTF1_MFC1MFC0_QCH, LH_AST_MI_OTF2_MFC1MFC0_QCH, LH_AST_MI_OTF3_MFC1MFC0_QCH, LH_AST_SI_OTF0_MFC0MFC1_QCH, LH_AST_SI_OTF1_MFC0MFC1_QCH, LH_AST_SI_OTF2_MFC0MFC1_QCH, LH_AST_SI_OTF3_MFC0MFC1_QCH, LH_ATB_MFC0_QCH_MI, LH_ATB_MFC0_QCH_SI, LH_AXI_MI_ID_MFC0_QCH, LH_AXI_SI_D0_MFC0_QCH, LH_AXI_SI_D1_MFC0_QCH, LH_AXI_SI_ID_MFC0_QCH, MFC0_QCH, MFC0_QCH_VOTF, MFC0_CMU_MFC0_QCH, PPMU_MFC0D0_QCH, PPMU_MFC0D1_QCH, PPMU_WFD_QCH, RSTNSYNC_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_NOCD_WFD_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF0_MFC0_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF1_MFC0_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF2_MFC0_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_MI_OTF3_MFC0_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF0_MFC0_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF1_MFC0_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF2_MFC0_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC0_NOCD_LH_AST_SI_OTF3_MFC0_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_MI_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC0_NOCD_LH_ATB_MFC0_SI_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC0_NOCD_MFC0_SW_RESET_QCH, SIU_G_PPMU_MFC0_QCH, SLH_AST_SI_G_PPMU_MFC0_QCH, SLH_AXI_MI_P_MFC0_QCH, SYSMMU_MFC0D0_QCH_S1, SYSMMU_MFC0D0_QCH_S2, SYSMMU_MFC0D1_QCH_S1, SYSMMU_MFC0D1_QCH_S2, SYSREG_MFC0_QCH, VGEN_LITE_MFC0_QCH, WFD_QCH, ADM_APB_MFC0MFC1_QCH, D_TZPC_MFC1_QCH, LH_AST_MI_OTF0_MFC0MFC1_QCH, LH_AST_MI_OTF1_MFC0MFC1_QCH, LH_AST_MI_OTF2_MFC0MFC1_QCH, LH_AST_MI_OTF3_MFC0MFC1_QCH, LH_AST_SI_OTF0_MFC1MFC0_QCH, LH_AST_SI_OTF1_MFC1MFC0_QCH, LH_AST_SI_OTF2_MFC1MFC0_QCH, LH_AST_SI_OTF3_MFC1MFC0_QCH, LH_AXI_SI_D0_MFC1_QCH, LH_AXI_SI_D1_MFC1_QCH, MFC1_QCH, MFC1_CMU_MFC1_QCH, PPMU_MFC1D0_QCH, PPMU_MFC1D1_QCH, RSTNSYNC_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF0_MFC1_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF1_MFC1_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF2_MFC1_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_MI_OTF3_MFC1_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF0_MFC1_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF1_MFC1_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF2_MFC1_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC1_NOCD_LH_AST_SI_OTF3_MFC1_SW_RESET_QCH, RSTNSYNC_SR_CLK_MFC1_NOCD_MFC1_SW_RESET_QCH, SIU_G_PPMU_MFC1_QCH, SLH_AST_SI_G_PPMU_MFC1_QCH, SLH_AXI_MI_P_MFC1_QCH, SYSMMU_MFC1D0_QCH_S1, SYSMMU_MFC1D0_QCH_S2, SYSMMU_MFC1D1_QCH_S1, SYSMMU_MFC1D1_QCH_S2, SYSREG_MFC1_QCH, VGEN_MFC1_QCH, BUSIF_DDD_MIF_QCH, CMU_MIF_CMUREF_QCH, DMC_QCH, D_TZPC_MIF_QCH, MIF_CMU_MIF_QCH, QCH_ADAPTER_DDRPHY_QCH, QCH_ADAPTER_DMC_QCH, QCH_ADAPTER_PPC_DEBUG_QCH, SLH_AST_SI_G_PPMU_MIF_QCH, SLH_AXI_MI_P_MIF_QCH, SPC_MIF_QCH, SYSREG_MIF_QCH, SYSREG_PRIVATE_MIF_QCH, BAAW_CP_QCH, BAAW_P_GNSS_QCH, BDU_QCH, CACHEAID_NOCL0_QCH, CCI_QCH, CCI_QCH_S, CMU_NOCL0_CMUREF_QCH, D_TZPC_NOCL0_QCH, LH_ACEL_MI_D0_G3D_QCH, LH_ACEL_MI_D1_G3D_QCH, LH_ACEL_MI_D2_G3D_QCH, LH_ACEL_MI_D3_G3D_QCH, LH_ACEL_SI_D0_ACP_QCH, LH_ACEL_SI_D1_ACP_QCH, LH_AST_MI_G_NOCL1A_QCH, LH_AST_MI_G_NOCL1B_QCH, LH_AST_MI_G_NOCL1C_QCH, LH_ATB_SI_T_BDU_QCH, LH_AXI_MI_D_APM_QCH, LH_AXI_MI_G_CSSYS_QCH, LH_AXI_MI_IG_CSSYS_NOCL0_QCH, LH_AXI_SI_IG_CSSYS_NOCL0_QCH, LH_CHI_MI_D0_CLUSTER0_QCH, LH_CHI_MI_D1_CLUSTER0_QCH, LH_QDI_MI_D_AUD_QCH, NOCIF_CMUTOPC_QCH, NOCL0_CMU_NOCL0_QCH, PBHA_GEN_D0_MODEM_QCH, PBHA_GEN_D1_MODEM_QCH, PPC_SCI_QCH, PPMU_APM_QCH, PPMU_CPUCL0_0_QCH, PPMU_CPUCL0_1_QCH, PPMU_G3D0_QCH, PPMU_G3D1_QCH, PPMU_G3D2_QCH, PPMU_G3D3_QCH, PPMU_SYNC_GEN_QCH, RSTNSYNC_CLK_NOCL0_NOCD_CCI_QCH, RSTNSYNC_CLK_NOCL0_NOCP_CCI_QCH, RSTNSYNC_SR_CLK_NOCL0_NOCD_CCI_QCH, SIU_G0_PPMU_NOCL0_QCH, SIU_G1_PPMU_NOCL0_QCH, SIU_G2_PPMU_NOCL0_QCH, SIU_G3_PPMU_NOCL0_QCH, SIU_G4_PPMU_NOCL0_QCH, SIU_G5_PPMU_NOCL0_QCH, SLH_ACEL_MI_D_SSP_QCH, SLH_AST_MI_G_PPMU_AUD_QCH, SLH_AST_MI_G_PPMU_GNSS_QCH, SLH_AST_MI_G_PPMU_MIF0_QCH, SLH_AST_MI_G_PPMU_MIF1_QCH, SLH_AST_MI_G_PPMU_MIF2_QCH, SLH_AST_MI_G_PPMU_MIF3_QCH, SLH_AST_MI_G_PPMU_MODEM_QCH, SLH_AST_MI_G_PPMU_NOCL1A_QCH, SLH_AST_MI_G_PPMU_NOCL1B_QCH, SLH_AST_MI_G_PPMU_NOCL1C_QCH, SLH_AST_MI_G_PPMU_SSP_QCH, SLH_AST_MI_G_PPMU_UFD_QCH, SLH_AST_MI_IG_DEBUG_MUX_NOCL0_QCH, SLH_AST_MI_IG_PPMU_P_CLUSTER0_QCH, SLH_AST_SI_IG_DEBUG_MUX_NOCL0_QCH, SLH_AST_SI_IG_PPMU_P_CLUSTER0_QCH, SLH_AXI_MI_D0_MODEM_QCH, SLH_AXI_MI_D1_MODEM_QCH, SLH_AXI_MI_D2_MODEM_QCH, SLH_AXI_MI_D_UFD_QCH, SLH_AXI_MI_P_CLUSTER0_NOCL0_QCH, SLH_AXI_SI_P_APM_QCH, SLH_AXI_SI_P_AUD_QCH, SLH_AXI_SI_P_CPUCL0_QCH, SLH_AXI_SI_P_G3D_QCH, SLH_AXI_SI_P_GNSS_QCH, SLH_AXI_SI_P_MCW_QCH, SLH_AXI_SI_P_MIF0_QCH, SLH_AXI_SI_P_MIF1_QCH, SLH_AXI_SI_P_MIF2_QCH, SLH_AXI_SI_P_MIF3_QCH, SLH_AXI_SI_P_MODEM_QCH, SLH_AXI_SI_P_PERIC1_QCH, SLH_AXI_SI_P_PERIS_QCH, SLH_AXI_SI_P_PERISGIC_QCH, SLH_AXI_SI_P_SSP_QCH, SLH_AXI_SI_P_UFD_QCH, SYSMMU_MODEM_QCH_S1, SYSMMU_MODEM_QCH_S2, SYSMMU_S2_APM_QCH, SYSMMU_S2_G3D_QCH_S0, SYSMMU_S2_G3D_QCH_S1, SYSMMU_S2_G3D_QCH_S2, SYSMMU_S2_G3D_QCH_S3, SYSMMU_S2_G3D_QCH_S4, SYSREG_NOCL0_QCH, TREX_D0_ACP_QCH, TREX_D1_ACP_QCH, TREX_D_NOCL0_QCH, TREX_P_NOCL0_QCH, VGEN_D0_G3D_QCH, VGEN_D1_G3D_QCH, VGEN_D2_G3D_QCH, VGEN_D3_G3D_QCH, VGEN_LITE_MODEM_QCH, WOW_DVFS_D0_CPUCL0_QCH, WOW_DVFS_D0_G3D_QCH, WOW_DVFS_D0_MIF_QCH, WOW_DVFS_D1_CPUCL0_QCH, WOW_DVFS_D1_MIF_QCH, WOW_DVFS_D2_MIF_QCH, WOW_DVFS_D3_MIF_QCH, WOW_DVFS_IRPS0_QCH, WOW_DVFS_IRPS1_QCH, WOW_DVFS_IRPS2_QCH, WOW_DVFS_IRPS3_QCH, WOW_DVFS_NOCL0_QCH, BAAW_P_DNC_QCH, CMU_NOCL1A_CMUREF_QCH, D_TZPC_NOCL1A_QCH, LH_ACEL_MI_D_HSI1_QCH, LH_ACEL_MI_D_LME_QCH, LH_ACEL_MI_D_M2M_QCH, LH_AST_SI_G_NOCL1A_QCH, LH_AXI_MI_D0_MFC0_QCH, LH_AXI_MI_D0_MFC1_QCH, LH_AXI_MI_D1_DPUF_QCH, LH_AXI_MI_D1_MFC0_QCH, LH_AXI_MI_D1_MFC1_QCH, NOCL1A_CMU_NOCL1A_QCH, SIU_2X1_P0_NOCL1A_QCH, SIU_4X1_P0_NOCL1A_QCH, SIU_8X1_P0_NOCL1A_QCH, SLH_AST_MI_G_PPMU_DNC_QCH, SLH_AST_MI_G_PPMU_DPUF_QCH, SLH_AST_MI_G_PPMU_HSI1_QCH, SLH_AST_MI_G_PPMU_LME_QCH, SLH_AST_MI_G_PPMU_M2M_QCH, SLH_AST_MI_G_PPMU_MFC0_QCH, SLH_AST_MI_G_PPMU_MFC1_QCH, SLH_AST_MI_IG_DEBUG_MUX_NOCL1A_QCH, SLH_AST_MI_IG_PPMU_NOCL1A_QCH, SLH_AST_SI_G_PPMU_NOCL1A_QCH, SLH_AST_SI_IG_DEBUG_MUX_NOCL1A_QCH, SLH_AST_SI_IG_PPMU_NOCL1A_QCH, SLH_AXI_MI_D0_DPUF_QCH, SLH_AXI_SI_P_DNC_QCH, SLH_AXI_SI_P_DPUB_QCH, SLH_AXI_SI_P_DPUF_QCH, SLH_AXI_SI_P_HSI1_QCH, SLH_AXI_SI_P_LME_QCH, SLH_AXI_SI_P_M2M_QCH, SLH_AXI_SI_P_MFC0_QCH, SLH_AXI_SI_P_MFC1_QCH, SLH_AXI_SI_P_PERIC0_QCH, SLH_AXI_SI_P_PERIC2_QCH, SYSREG_NOCL1A_QCH, TREX_D_NOCL1A_QCH, TREX_P_NOCL1A_QCH, CMU_NOCL1B_CMUREF_QCH, DIT_QCH, D_TZPC_NOCL1B_QCH, LH_ACEL_MI_D_UFS_QCH, LH_ACEL_MI_ID_DIT_QCH, LH_ACEL_SI_ID_DIT_QCH, LH_AST_SI_G_NOCL1B_QCH, LH_AXI_MI_ID_TT_QCH, LH_AXI_SI_ID_TT_QCH, NOCL1B_CMU_NOCL1B_QCH, PDMA_QCH, PPMU_DIT_QCH, PPMU_D_TT_QCH, QE_PDMA_QCH, QE_SPDMA_QCH, SIU_8X1_P0_NOCL1B_QCH, SLH_ACEL_MI_D_HSI0_QCH, SLH_AST_MI_G_PPMU_HSI0_QCH, SLH_AST_MI_G_PPMU_UFS_QCH, SLH_AST_MI_IG_DEBUG_MUX_NOCL1B_QCH, SLH_AST_MI_IG_PPMU_DIT_QCH, SLH_AST_MI_IG_PPMU_TREXP_QCH, SLH_AST_MI_IG_PPMU_XIU_D_TT_QCH, SLH_AST_SI_G_PPMU_NOCL1B_QCH, SLH_AST_SI_IG_DEBUG_MUX_NOCL1B_QCH, SLH_AST_SI_IG_PPMU_DIT_QCH, SLH_AST_SI_IG_PPMU_TREXP_QCH, SLH_AST_SI_IG_PPMU_XIU_D_TT_QCH, SLH_AXI_SI_P_HSI0_QCH, SLH_AXI_SI_P_UFS_QCH, SPDMA_QCH, SYSMMU_S2_DIT_QCH, SYSMMU_S2_TT_QCH, SYSREG_NOCL1B_QCH, TREX_D_NOCL1B_QCH, TREX_P_NOCL1B_QCH, VGEN_LITE_NOCL1B_QCH, VGEN_PDMA_QCH, VGEN_SPDMA_QCH, CMU_NOCL1C_CMUREF_QCH, D_TZPC_NOCL1C_QCH, LH_AST_SI_G_NOCL1C_QCH, LH_AXI_MI_D0_BRP_QCH, LH_AXI_MI_D0_CSIS_QCH, LH_AXI_MI_D0_YUVP_QCH, LH_AXI_MI_D1_BRP_QCH, LH_AXI_MI_D1_CSIS_QCH, LH_AXI_MI_D1_MCSC_QCH, LH_AXI_MI_D2_BRP_QCH, LH_AXI_MI_D2_CSIS_QCH, LH_AXI_MI_D2_MCSC_QCH, LH_AXI_MI_D3_MCSC_QCH, LH_AXI_MI_D4_MCSC_QCH, LH_AXI_MI_D_CSTAT_QCH, NOCL1C_CMU_NOCL1C_QCH, SIU_8X1_P0_NOCL1C_QCH, SLH_AST_MI_G_PPMU_BRP_QCH, SLH_AST_MI_G_PPMU_CSIS_QCH, SLH_AST_MI_G_PPMU_CSTAT_QCH, SLH_AST_MI_G_PPMU_MCSC_QCH, SLH_AST_MI_G_PPMU_YUVP_QCH, SLH_AST_MI_IG_DEBUG_MUX_NOCL1C_QCH, SLH_AST_MI_IG_PPMU_NOCL1C_QCH, SLH_AST_SI_G_PPMU_NOCL1C_QCH, SLH_AST_SI_IG_DEBUG_MUX_NOCL1C_QCH, SLH_AST_SI_IG_PPMU_NOCL1C_QCH, SLH_AXI_MI_D0_MCSC_QCH, SLH_AXI_MI_D1_YUVP_QCH, SLH_AXI_SI_P_BRP_QCH, SLH_AXI_SI_P_CSIS_QCH, SLH_AXI_SI_P_CSTAT_QCH, SLH_AXI_SI_P_MCSC_QCH, SLH_AXI_SI_P_YUVP_QCH, SYSREG_NOCL1C_QCH, TREX_D_NOCL1C_QCH, TREX_P_NOCL1C_QCH, D_TZPC_PERIC0_QCH, GPIO_PERIC0_QCH, I3C00_QCH_S, I3C00_QCH_P, I3C01_QCH_S, I3C01_QCH_P, I3C02_QCH_S, I3C02_QCH_P, PERIC0_CMU_PERIC0_QCH, SLH_AXI_MI_P_PERIC0_QCH, SYSREG_PERIC0_QCH, USI04_I2C_QCH, USI04_USI_QCH, BT_UART_QCH, D_TZPC_PERIC1_QCH, GPIO_PERIC1_QCH, PERIC1_CMU_PERIC1_QCH, SLH_AXI_MI_P_PERIC1_QCH, SPI_MULTI_SLV_Q_CTRL_PERIC1_QCH, SYSREG_PERIC1_QCH, USI07_SPI_I2C_QCH, USI07_USI_QCH, USI08_SPI_I2C_QCH, USI08_USI_QCH, USI09_I2C_QCH, USI09_USI_QCH, USI10_I2C_QCH, USI10_USI_QCH, DBG_UART_QCH, D_TZPC_PERIC2_QCH, GPIO_PERIC2_QCH, I3C03_OIS_QCH_S, I3C03_OIS_QCH_P, I3C04_QCH_S, I3C04_QCH_P, I3C05_QCH_S, I3C05_QCH_P, I3C06_QCH_S, I3C06_QCH_P, I3C07_QCH_S, I3C07_QCH_P, I3C08_QCH_S, I3C08_QCH_P, I3C09_QCH_S, I3C09_QCH_P, I3C10_QCH_S, I3C10_QCH_P, I3C11_QCH_S, I3C11_QCH_P, PERIC2_CMU_PERIC2_QCH, PWM_QCH, SLH_AXI_MI_LP_CSISPERIC2_QCH, SLH_AXI_MI_P_PERIC2_QCH, SPI_MULTI_SLV_Q_CTRL_PERIC2_QCH, SYSREG_PERIC2_QCH, USI00_SPI_I2C_QCH, USI00_USI_QCH, USI01_SPI_I2C_QCH, USI01_USI_QCH, USI02_I2C_QCH, USI02_USI_QCH, USI03_I2C_QCH, USI03_USI_QCH, USI05_I2C_QCH, USI05_USI_OIS_QCH, USI06_I2C_QCH, USI06_USI_OIS_QCH, USI11_I2C_QCH, USI11_USI_QCH, BUSIF_DDD_PERIS_QCH, DFTMUX_PERIS_QCH, D_TZPC_PERIS_QCH, GIC_QCH, LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_QCH, LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_QCH, MCT_QCH, OTP_CON_BIRA_QCH, OTP_CON_TOP_QCH, PERIS_CMU_PERIS_QCH, SLH_AXI_MI_P_PERIS_QCH, SLH_AXI_MI_P_PERISGIC_QCH, SYSREG_PERIS_QCH, TMU_SUB_QCH, TMU_TOP_QCH, WDT0_QCH, WDT1_QCH, BIS_S2D_QCH, S2D_CMU_S2D_QCH, SLH_AXI_MI_G_SCAN2DRAM_QCH, D_TZPC_SDMA_QCH, IP_SDMA_QCH, LH_AST_SI_LD_STRM_SDMADSP0_QCH, LH_AXI_MI_LP_DNCSDMA_QCH, LH_AXI_SI_LD_SDMADNC_DATA0_QCH, LH_AXI_SI_LD_SDMADNC_DATA1_QCH, LH_AXI_SI_LD_SDMADNC_DATA2_QCH, LH_AXI_SI_LD_SDMADNC_DATA3_QCH, LH_AXI_SI_LD_SDMADNC_DATA4_QCH, LH_AXI_SI_LD_SDMADNC_DATA5_QCH, LH_AXI_SI_LD_SDMADNC_DATA6_QCH, LH_AXI_SI_LD_SDMADNC_DATA7_QCH, LH_AXI_SI_LD_SDMADNC_MMU0_QCH, LH_AXI_SI_LD_SDMADNC_MMU1_QCH, LH_AXI_SI_LD_SDMADNC_MMU2_QCH, LH_AXI_SI_LD_SDMADNC_MMU3_QCH, SDMA_CMU_SDMA_QCH, SLH_AXI_MI_LP_SDMA_QCH, SYSREG_SDMA_QCH, BAAW_SSS_QCH, D_TZPC_SSP_QCH, HW_APBSEMA_MEC_QCH, LH_AXI_MI_L_STRONG_QCH, PPMU_SSP_QCH, QE_SSS_QCH, QE_STRONG_QCH, SLH_ACEL_SI_D_SSP_QCH, SLH_AST_SI_G_PPMU_SSP_QCH, SLH_AXI_MI_P_SSP_QCH, SSP_CMU_SSP_QCH, SSS_QCH, SYSMMU_SSP_QCH, SYSREG_SSP_QCH, VGEN_LITE_SSP_QCH, RSTNSYNC_CLK_STRONG_FREE_OSCCLK_QCH, RSTNSYNC_CLK_STRONG_FREE_OSCCLK_CPU_QCH, STRONG_CMU_STRONG_QCH, BAAW_D_UFDDNC_QCH, D_TZPC_UFD_QCH, I3C_UFD_QCH_PCLK, I3C_UFD_QCH_SCLK, LH_AST_SI_OTF_UFDDNC_QCH, PDMA_UFD_QCH, PPMU_D_UFD_QCH, RSTNSYNC_CLK_UFD_NOC_UFD_SW_RESET_QCH, RSTNSYNC_SR_CLK_UFD_NOC_LH_AST_SI_OTF_UFDDNC_SW_RESET_QCH, RSTNSYNC_SR_CLK_UFD_NOC_SLH_AST_MI_OTF_CSISUFD_SW_RESET_QCH, SLH_AST_MI_OTF_CSISUFD_QCH, SLH_AST_SI_G_PPMU_UFD_QCH, SLH_AXI_MI_LP_CMGPUFD_QCH, SLH_AXI_MI_P_UFD_QCH, SLH_AXI_SI_D_UFD_QCH, SLH_AXI_SI_LD_UFDDNC_QCH, SLH_AXI_SI_LP_UFDCSIS_QCH, SRAM_MIU_UFD_QCH, SYSMMU_D_UFD_QCH_S1, SYSMMU_D_UFD_QCH_S2, SYSREG_UFD_QCH, SYSREG_UFD_SECURE_QCH, UFD_CMU_UFD_QCH, VGEN_LITE_D_UFD_QCH, UFD_QCH, D_TZPC_UFS_QCH, GPIO_HSI1UFS_QCH, GPIO_UFS_QCH, LH_ACEL_SI_D_UFS_QCH, MMC_CARD_QCH, PPMU_UFS_QCH, SLH_AST_SI_G_PPMU_UFS_QCH, SLH_AXI_MI_P_UFS_QCH, SPC_UFS_QCH, SYSMMU_UFS_QCH_S2, SYSREG_UFS_QCH, UFS_CMU_UFS_QCH, UFS_EMBD_QCH_FMP, UFS_EMBD_QCH, VGEN_LITE_UFS_QCH, ASYNCINTERRUPT_VTS_QCH_ASYNCINTERRUPT_VT, BAAW_VTS_QCH, DMIC_IF0_QCH_PCLK, DMIC_IF0_QCH_DMIC, DMIC_IF1_QCH_PCLK, DMIC_IF1_QCH_DMIC, DMIC_IF2_QCH_PCLK, DMIC_IF2_QCH_DMIC, GPIO_VTS_QCH, INTMEM_CODE_QCH, INTMEM_DATA0_QCH, INTMEM_DATA1_QCH, INTMEM_PCM_QCH, LH_AXI_MI_IP_VC2VTS_QCH, LH_AXI_SI_ID_VTS2VC_QCH, MAILBOX_ABOX_VTS_QCH, MAILBOX_AP_VTS_QCH, MAILBOX_DNC_VTS_QCH, SERIAL_LIF_VT_QCH_PCLK, SERIAL_LIF_VT_QCH_CCLK, SERIAL_LIF_VT_QCH_ACLK, SERIAL_LIF_VT_QCH_BCLK, SS_VTS_GLUE_QCH_DMIC_IF_PAD0, SS_VTS_GLUE_QCH_DMIC_IF_PAD1, SS_VTS_GLUE_QCH_DMIC_IF_PAD2, SS_VTS_GLUE_QCH_DMIC_AUD_DIV2_CLK, SYSREG_VTS_QCH, TIMER_QCH, TIMER1_QCH, TIMER2_QCH, VTS_CMU_VTS_QCH, WDT_VTS_QCH, YAMIN_MCU_VTS_QCH_CLKIN, YAMIN_MCU_VTS_QCH_DBGCLK, BUSIF_DDD_YUVP_QCH, D_TZPC_YUVP_QCH, LH_AST_MI_OTF_MCSCYUVP_QCH, LH_AST_SI_OTF0_YUVPMCSC_QCH, LH_AST_SI_OTF1_YUVPMCSC_QCH, LH_AXI_SI_D0_YUVP_QCH, PPMU_D0_YUVP_QCH, PPMU_D1_YUVP_QCH, SIU_G_PPMU_YUVP_QCH, SLH_AST_SI_G_PPMU_YUVP_QCH, SLH_AXI_MI_P_YUVP_QCH, SLH_AXI_SI_D1_YUVP_QCH, SYSMMU_D0_YUVP_QCH_S1, SYSMMU_D0_YUVP_QCH_S2, SYSMMU_D1_YUVP_QCH_S1, SYSMMU_D1_YUVP_QCH_S2, SYSREG_YUVP_QCH, VGEN_LITE_D0_YUVP_QCH, VGEN_LITE_D1_YUVP_QCH, YUVP_QCH, YUVP_QCH_VOTF0, YUVP_QCH_VOTF1, YUVP_CMU_YUVP_QCH, end_of_qch, num_of_qch = (end_of_qch - QCH_TYPE) & MASK_OF_ID, }; enum option_id { CTRL_OPTION_CMU_ALIVE = OPTION_TYPE, CTRL_OPTION_CMU_ALLCSIS, CTRL_OPTION_CMU_AUD, CTRL_OPTION_CMU_BRP, CTRL_OPTION_CMU_CHUB, CTRL_OPTION_CMU_CHUBVTS, CTRL_OPTION_CMU_CMGP, CTRL_OPTION_CMU_TOP, CTRL_OPTION_CMU_CPUCL0, CTRL_OPTION_CMU_CPUCL0_GLB, CTRL_OPTION_CMU_CPUCL1, CTRL_OPTION_CMU_CPUCL2, CTRL_OPTION_CMU_CSIS, CTRL_OPTION_CMU_CSTAT, CTRL_OPTION_CMU_DBGCORE, CTRL_OPTION_CMU_DNC, CTRL_OPTION_CMU_DPUB, CTRL_OPTION_CMU_DPUF, CTRL_OPTION_CMU_DPUF1, CTRL_OPTION_CMU_DRCP, CTRL_OPTION_CMU_DSP, CTRL_OPTION_CMU_DSU, CTRL_OPTION_CMU_G3D, CTRL_OPTION_CMU_G3DCORE, CTRL_OPTION_CMU_GNPU, CTRL_OPTION_CMU_GNSS, CTRL_OPTION_CMU_HSI0, CTRL_OPTION_CMU_HSI1, CTRL_OPTION_CMU_LME, CTRL_OPTION_CMU_M2M, CTRL_OPTION_CMU_MCSC, CTRL_OPTION_CMU_MFC0, CTRL_OPTION_CMU_MFC1, CTRL_OPTION_CMU_MIF, CTRL_OPTION_CMU_NOCL0, CTRL_OPTION_CMU_NOCL1A, CTRL_OPTION_CMU_NOCL1B, CTRL_OPTION_CMU_NOCL1C, CTRL_OPTION_CMU_PERIC0, CTRL_OPTION_CMU_PERIC1, CTRL_OPTION_CMU_PERIC2, CTRL_OPTION_CMU_PERIS, CTRL_OPTION_CMU_S2D, CTRL_OPTION_CMU_SDMA, CTRL_OPTION_CMU_SSP, CTRL_OPTION_CMU_STRONG, CTRL_OPTION_CMU_UFD, CTRL_OPTION_CMU_UFS, CTRL_OPTION_CMU_VTS, CTRL_OPTION_CMU_YUVP, end_of_option, num_of_option = (end_of_option - OPTION_TYPE) & MASK_OF_ID, }; #endif