#include "../../cmucal.h"
#include "cmucal-node.h"
#include "cmucal-sfr.h"

struct cmucal_pll_table pll_aud_rate_table[] = {
	PLL_RATE_MPSF(1500000000, 173, 3, 0, 972644901),
	PLL_RATE_MPSF(1400000000, 162, 3, 0, 972644901),
	PLL_RATE_MPSF(1300000000, 150, 3, 0, 972644901),
	PLL_RATE_MPSF(1179648000, 272, 3, 1, 972644901),
};

struct cmucal_pll_table pll_shared1_rate_table[] = {
	PLL_RATE_MPSK(1332999936, 205, 4, 0, 0),
};

struct cmucal_pll_table pll_shared0_rate_table[] = {
	PLL_RATE_MPSK(1599000064, 123, 2, 0, 0),
	PLL_RATE_MPSK(1599000064, 246, 4, 0, 0),
};

struct cmucal_pll_table pll_g3d_rate_table[] = {
	PLL_RATE_MPSK(1100000000, 138, 4, 0, 0),
	PLL_RATE_MPSK(600000000, 92, 2, 1, 0),
	PLL_RATE_MPSK(400000000, 123, 4, 1, 0),
	PLL_RATE_MPSK(200000000, 123, 4, 2, 0),
};

struct cmucal_pll_table pll_mmc_rate_table[] = {
	PLL_RATE_MPSF(800000000, 123, 4, 0, 330382100),
	PLL_RATE_MPSF(800000000, 123, 4, 0, 330382100),
	PLL_RATE_MPSF(400000000, 123, 4, 1, 330382100),
};

struct cmucal_pll_table pll_shared2_rate_table[] = {
	PLL_RATE_MPSK(936000000, 72, 2, 0, 0),
};

struct cmucal_pll_table pll_cpucl0_rate_table[] = {
	PLL_RATE_MPSK(2000000000, 231, 3, 0, 0),
	PLL_RATE_MPSK(1700000000, 196, 3, 0, 0),
	PLL_RATE_MPSK(1500000000, 173, 3, 0, 0),
	PLL_RATE_MPSK(1000000000, 115, 3, 0, 0),
	PLL_RATE_MPSK(450000000, 104, 3, 1, 0),
	PLL_RATE_MPSK(200000000, 246, 4, 3, 0),
};

struct cmucal_pll_table pll_cpucl1_rate_table[] = {
	PLL_RATE_MPSK(2600000000, 300, 3, 0, 0),
	PLL_RATE_MPSK(2000000000, 231, 3, 0, 0),
	PLL_RATE_MPSK(1700000000, 196, 3, 0, 0),
	PLL_RATE_MPSK(1100000000, 127, 3, 0, 0),
	PLL_RATE_MPSK(500000000, 115, 3, 0, 0),
	PLL_RATE_MPSK(500000000, 115, 3, 1, 0),
};

struct cmucal_pll_table pll_dsu_rate_table[] = {
	PLL_RATE_MPSK(1800000000, 208, 3, 0, 0),
	PLL_RATE_MPSK(1500000000, 173, 3, 0, 0),
	PLL_RATE_MPSK(1200000000, 139, 3, 0, 0),
	PLL_RATE_MPSK(800000000, 92, 3, 0, 0),
	PLL_RATE_MPSK(400000000, 92, 3, 1, 0),
	PLL_RATE_MPSK(150000000, 69, 3, 2, 0),
};

struct cmucal_pll_table pll_mif_rate_table[] = {
	PLL_RATE_MPS(4265999872, 246, 3, 0),
	PLL_RATE_MPS(3078000128, 410, 4, 1),
	PLL_RATE_MPS(1410000000, 323, 3, 2),
	PLL_RATE_MPS(710000000, 323, 3, 4),
};

struct cmucal_pll_table pll_mif_s2d_rate_table[] = {
	PLL_RATE_MPS(26000000, 200, 13, 0),
};



unsigned int cmucal_pll_size = 11;
struct cmucal_pll cmucal_pll_list[] = {
	CLK_RPLL(frd_2021_rpll, PLL_AUD, OSCCLK_AUD, PLL_LOCKTIME_PLL_AUD_PLL_LOCK_TIME, PLL_CON3_PLL_AUD_ENABLE, PLL_CON3_PLL_AUD_STABLE, PLL_CON3_PLL_AUD_DIV_P, PLL_CON3_PLL_AUD_DIV_M, PLL_CON3_PLL_AUD_DIV_S, PLL_CON8_PLL_AUD_F, pll_aud_rate_table, 150, 500),
	CLK_RPLL(frd_2021_rpll, PLL_SHARED1, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED1_ENABLE, PLL_CON3_PLL_SHARED1_STABLE, PLL_CON3_PLL_SHARED1_DIV_P, PLL_CON3_PLL_SHARED1_DIV_M, PLL_CON3_PLL_SHARED1_DIV_S, PLL_CON8_PLL_SHARED1_F, pll_shared1_rate_table, 150, 500),
	CLK_RPLL(frd_2021_rpll, PLL_SHARED0, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED0_ENABLE, PLL_CON3_PLL_SHARED0_STABLE, PLL_CON3_PLL_SHARED0_DIV_P, PLL_CON3_PLL_SHARED0_DIV_M, PLL_CON3_PLL_SHARED0_DIV_S, PLL_CON8_PLL_SHARED0_F, pll_shared0_rate_table, 150, 500),
	CLK_RPLL(frd_2021_rpll, PLL_G3D, OSCCLK_CMU, PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, PLL_CON3_PLL_G3D_ENABLE, PLL_CON3_PLL_G3D_STABLE, PLL_CON3_PLL_G3D_DIV_P, PLL_CON3_PLL_G3D_DIV_M, PLL_CON3_PLL_G3D_DIV_S, PLL_CON8_PLL_G3D_F, pll_g3d_rate_table, 150, 500),
	CLK_RPLL(frd_2021_rpll, PLL_MMC, OSCCLK_CMU, PLL_LOCKTIME_PLL_MMC_PLL_LOCK_TIME, PLL_CON3_PLL_MMC_ENABLE, PLL_CON3_PLL_MMC_STABLE, PLL_CON3_PLL_MMC_DIV_P, PLL_CON3_PLL_MMC_DIV_M, PLL_CON3_PLL_MMC_DIV_S, PLL_CON8_PLL_MMC_F, pll_mmc_rate_table, 150, 500),
	CLK_RPLL(frd_2021_rpll, PLL_SHARED2, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED2_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED2_ENABLE, PLL_CON3_PLL_SHARED2_STABLE, PLL_CON3_PLL_SHARED2_DIV_P, PLL_CON3_PLL_SHARED2_DIV_M, PLL_CON3_PLL_SHARED2_DIV_S, PLL_CON8_PLL_SHARED2_F, pll_shared2_rate_table, 150, 500),
	CLK_RPLL(frd_2021_rpll, PLL_CPUCL0, OSCCLK_CPUCL0, PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, PLL_CON3_PLL_CPUCL0_ENABLE, PLL_CON3_PLL_CPUCL0_STABLE, PLL_CON3_PLL_CPUCL0_DIV_P, PLL_CON3_PLL_CPUCL0_DIV_M, PLL_CON3_PLL_CPUCL0_DIV_S, PLL_CON8_PLL_CPUCL0_F, pll_cpucl0_rate_table, 150, 500),
	CLK_PLL(pll_0522x, PLL_CPUCL1, OSCCLK_CPUCL1, PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, PLL_CON3_PLL_CPUCL1_ENABLE, PLL_CON3_PLL_CPUCL1_STABLE, PLL_CON3_PLL_CPUCL1_DIV_P, PLL_CON3_PLL_CPUCL1_DIV_M, PLL_CON3_PLL_CPUCL1_DIV_S, EMPTY_CAL_ID, pll_cpucl1_rate_table, 0, 0),
	CLK_RPLL(frd_2021_rpll, PLL_DSU, OSCCLK_DSU, PLL_LOCKTIME_PLL_DSU_PLL_LOCK_TIME, PLL_CON3_PLL_DSU_ENABLE, PLL_CON3_PLL_DSU_STABLE, PLL_CON3_PLL_DSU_DIV_P, PLL_CON3_PLL_DSU_DIV_M, PLL_CON3_PLL_DSU_DIV_S, PLL_CON8_PLL_DSU_F, pll_dsu_rate_table, 150, 500),
	CLK_RPLL(frd_5008_ipll, PLL_MIF, OSCCLK_MIF, PLL_LOCKTIME_PLL_MIF_PLL_LOCK_TIME, PLL_CON3_PLL_MIF_ENABLE, PLL_CON3_PLL_MIF_STABLE, PLL_CON3_PLL_MIF_DIV_P, PLL_CON3_PLL_MIF_DIV_M, PLL_CON3_PLL_MIF_DIV_S, EMPTY_CAL_ID, pll_mif_rate_table, 0, 0),
	CLK_RPLL(frd_5008_ipll, PLL_MIF_S2D, OSCCLK_S2D, PLL_LOCKTIME_PLL_MIF_S2D_PLL_LOCK_TIME, PLL_CON3_PLL_MIF_S2D_ENABLE, PLL_CON3_PLL_MIF_S2D_STABLE, PLL_CON3_PLL_MIF_S2D_DIV_P, PLL_CON3_PLL_MIF_S2D_DIV_M, PLL_CON3_PLL_MIF_S2D_DIV_S, EMPTY_CAL_ID, pll_mif_s2d_rate_table, 0, 0),
	 };

enum clk_id cmucal_mux_clkcmu_cmgp_bus_parents[] = {
	MUX_CLK_RCO_ALIVE_USER,
	RCO_400,
	MUX_CLKCMU_ALIVE_BUS_USER,
	OSCCLK_RCO_ALIVE,
};
enum clk_id cmucal_mux_clk_alive_bus_parents[] = {
	MUX_CLK_RCO_ALIVE_USER,
	RCO_400,
	MUX_CLKCMU_ALIVE_BUS_USER,
	OSCCLK_RCO_ALIVE,
};
enum clk_id cmucal_mux_clkcmu_cmgp_peri_parents[] = {
	MUX_CLK_RCO_ALIVE_USER,
	RCO_400,
	MUX_CLKCMU_ALIVE_BUS_USER,
	OSCCLK_RCO_ALIVE,
};
enum clk_id cmucal_mux_clk_alive_i3c_pmic_parents[] = {
	DIV_CLK_ALIVE_I3C_PMIC,
	MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER,
};
enum clk_id cmucal_mux_clkcmu_chubvts_bus_parents[] = {
	MUX_CLK_RCO_ALIVE_USER,
	RCO_400,
	MUX_CLKCMU_ALIVE_BUS_USER,
	OSCCLK_RCO_ALIVE,
};
enum clk_id cmucal_mux_clk_alive_dbgcore_uart_parents[] = {
	OSCCLK_RCO_ALIVE,
	MUX_CLK_ALIVE_BUS,
};
enum clk_id cmucal_mux_clkcmu_ap2gnss_parents[] = {
	MUX_CLKCMU_ALIVE_BUS_USER,
	RCO_400,
};
enum clk_id cmucal_mux_clkcmu_chub_peri_parents[] = {
	MUX_CLK_RCO_ALIVE_USER,
	RCO_400,
	MUX_CLKCMU_ALIVE_BUS_USER,
	OSCCLK_RCO_ALIVE,
};
enum clk_id cmucal_mux_clk_alive_usi0_parents[] = {
	OSCCLK_RCO_ALIVE,
	MUX_CLK_ALIVE_BUS,
};
enum clk_id cmucal_mux_clk_alive_i2c_parents[] = {
	OSCCLK_RCO_ALIVE,
	MUX_CLK_ALIVE_BUS,
};
enum clk_id cmucal_mux_clk_aud_uaif3_parents[] = {
	DIV_CLK_AUD_AUDIF,
	IOCLK_AUDIOCDCLK3,
};
enum clk_id cmucal_mux_clk_aud_uaif2_parents[] = {
	DIV_CLK_AUD_AUDIF,
	IOCLK_AUDIOCDCLK2,
};
enum clk_id cmucal_mux_clk_aud_uaif1_parents[] = {
	DIV_CLK_AUD_AUDIF,
	IOCLK_AUDIOCDCLK1,
};
enum clk_id cmucal_mux_clk_aud_uaif0_parents[] = {
	DIV_CLK_AUD_AUDIF,
	IOCLK_AUDIOCDCLK0,
};
enum clk_id cmucal_mux_clk_aud_cpu_parents[] = {
	MUX_CLK_AUD_CPU_PLL,
	MUX_CLKCMU_AUD_CPU_USER,
};
enum clk_id cmucal_mux_clk_aud_fm_parents[] = {
	OSCCLK_AUD,
	DIV_CLK_AUD_FM_SPDY,
};
enum clk_id cmucal_mux_clk_aud_uaif4_parents[] = {
	DIV_CLK_AUD_AUDIF,
	IOCLK_AUDIOCDCLK4,
};
enum clk_id cmucal_mux_clk_aud_uaif5_parents[] = {
	DIV_CLK_AUD_AUDIF,
	IOCLK_AUDIOCDCLK5,
};
enum clk_id cmucal_mux_clk_aud_uaif6_parents[] = {
	DIV_CLK_AUD_AUDIF,
	IOCLK_AUDIOCDCLK6,
};
enum clk_id cmucal_mux_clk_aud_dsif_parents[] = {
	DIV_CLK_AUD_AUDIF,
	CLKIO_AUD_DSIF,
};
enum clk_id cmucal_mux_clk_aud_cpu_pll_parents[] = {
	PLL_AUD_D1,
	PLL_AUD_D2,
	PLL_AUD_D3,
	PLL_AUD_D4,
};
enum clk_id cmucal_mux_clk_aud_bus_parents[] = {
	OSCCLK_AUD,
	MUX_CLKCMU_AUD_BUS_USER,
};
enum clk_id cmucal_mux_clk_aud_pcmc_parents[] = {
	MUX_CP_PCMC_CLK_USER,
	DIV_CLK_AUD_PCMC,
};
enum clk_id cmucal_mux_busc_cmuref_parents[] = {
	OSCCLK_BUSC,
	CLKCMU_CMU_BOOST,
};
enum clk_id cmucal_mux_clk_chub_timer_parents[] = {
	OSCCLK_RCO_CHUB,
	RTCCLK_CHUB,
};
enum clk_id cmucal_mux_clk_chub_usi0_parents[] = {
	MUX_CLKCMU_CHUB_RCO_USER,
	MUX_CLKCMU_CHUB_PERI_USER,
};
enum clk_id cmucal_mux_clk_chub_usi1_parents[] = {
	MUX_CLKCMU_CHUB_RCO_USER,
	MUX_CLKCMU_CHUB_PERI_USER,
};
enum clk_id cmucal_mux_clk_chub_usi2_parents[] = {
	MUX_CLKCMU_CHUB_RCO_USER,
	MUX_CLKCMU_CHUB_PERI_USER,
};
enum clk_id cmucal_mux_clk_chub_i2c_parents[] = {
	MUX_CLKCMU_CHUB_RCO_USER,
	MUX_CLKCMU_CHUB_PERI_USER,
};
enum clk_id cmucal_mux_clk_chub_usi3_parents[] = {
	MUX_CLKCMU_CHUB_RCO_USER,
	MUX_CLKCMU_CHUB_PERI_USER,
};
enum clk_id cmucal_mux_clk_chub_bus_parents[] = {
	MUX_CLKCMU_CHUB_RCO_USER,
	MUX_CLK_CHUB_BUS_USER,
};
enum clk_id cmucal_mux_clk_chubvts_bus_parents[] = {
	MUX_CLKCMU_CHUBVTS_BUS_USER,
	MUX_CLKCMU_CHUBVTS_RCO_USER,
};
enum clk_id cmucal_mux_clk_cmgp_i2c_parents[] = {
	MUX_CLKCMU_CMGP_RCO_USER,
	MUX_CLKCMU_CMGP_PERI_USER,
};
enum clk_id cmucal_mux_clk_cmgp_usi0_parents[] = {
	MUX_CLKCMU_CMGP_RCO_USER,
	MUX_CLKCMU_CMGP_PERI_USER,
};
enum clk_id cmucal_mux_clk_cmgp_usi4_parents[] = {
	MUX_CLKCMU_CMGP_RCO_USER,
	MUX_CLKCMU_CMGP_PERI_USER,
};
enum clk_id cmucal_mux_clk_cmgp_i3c_parents[] = {
	MUX_CLKCMU_CMGP_RCO_USER,
	MUX_CLKCMU_CMGP_PERI_USER,
};
enum clk_id cmucal_mux_clk_cmgp_bus_parents[] = {
	MUX_CLKCMU_CMGP_RCO_USER,
	MUX_CLKCMU_CMGP_BUS_USER,
};
enum clk_id cmucal_mux_clk_cmgp_usi1_parents[] = {
	MUX_CLKCMU_CMGP_RCO_USER,
	MUX_CLKCMU_CMGP_PERI_USER,
};
enum clk_id cmucal_mux_clk_cmgp_usi2_parents[] = {
	MUX_CLKCMU_CMGP_RCO_USER,
	MUX_CLKCMU_CMGP_PERI_USER,
};
enum clk_id cmucal_mux_clk_cmgp_usi3_parents[] = {
	MUX_CLKCMU_CMGP_RCO_USER,
	MUX_CLKCMU_CMGP_PERI_USER,
};
enum clk_id cmucal_mux_clkcmu_mfc_mfc_parents[] = {
	PLL_SHARED1_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
	PLL_SHARED0_D4,
};
enum clk_id cmucal_mux_clkcmu_core_bus_parents[] = {
	PLL_SHARED0_D2,
	PLL_SHARED1_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
};
enum clk_id cmucal_mux_clkcmu_cpucl0_switch_parents[] = {
	PLL_SHARED0_D2,
	PLL_SHARED1_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
};
enum clk_id cmucal_mux_clkcmu_mif_switch_parents[] = {
	PLL_SHARED0_D1,
	PLL_SHARED1_D1,
	PLL_SHARED0_D2,
	PLL_SHARED2_D1,
};
enum clk_id cmucal_mux_clkcmu_taa_bus_parents[] = {
	PLL_SHARED1_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
	PLL_SHARED0_D4,
};
enum clk_id cmucal_mux_clkcmu_isp_bus_parents[] = {
	PLL_SHARED1_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
	PLL_SHARED0_D4,
};
enum clk_id cmucal_mux_clkcmu_aud_cpu_parents[] = {
	PLL_SHARED0_D2,
	PLL_SHARED1_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
};
enum clk_id cmucal_mux_clkcmu_m2m_mscl_parents[] = {
	PLL_SHARED0_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D2,
	PLL_SHARED0_D4,
};
enum clk_id cmucal_mux_clkcmu_cpucl0_dbg_bus_parents[] = {
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
	PLL_SHARED0_D4,
	PLL_SHARED1_D4,
};
enum clk_id cmucal_mux_clkcmu_cis_clk0_parents[] = {
	OSCCLK_CMU,
	PLL_SHARED0_D4,
};
enum clk_id cmucal_mux_clkcmu_cis_clk1_parents[] = {
	OSCCLK_CMU,
	PLL_SHARED0_D4,
};
enum clk_id cmucal_mux_clkcmu_cis_clk2_parents[] = {
	OSCCLK_CMU,
	PLL_SHARED0_D4,
};
enum clk_id cmucal_mux_clkcmu_hsi_ufs_embd_parents[] = {
	OSCCLK_CMU,
	PLL_SHARED0_D2,
	PLL_SHARED0_D4,
	PLL_SHARED1_D4,
};
enum clk_id cmucal_mux_cmu_cmuref_parents[] = {
	OSCCLK_CMU,
	CLKCMU_CMU_BOOST,
};
enum clk_id cmucal_mux_clkcmu_peri_bus_parents[] = {
	PLL_SHARED0_D4,
	PLL_SHARED1_D4,
	PLL_MMC_D2,
	OSCCLK_CMU,
};
enum clk_id cmucal_mux_clkcmu_npu0_bus_parents[] = {
	PLL_SHARED2_D1,
	PLL_SHARED1_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
};
enum clk_id cmucal_mux_clkcmu_alive_bus_parents[] = {
	PLL_SHARED0_D2,
	PLL_SHARED1_D4,
};
enum clk_id cmucal_mux_clkcmu_hsi_bus_parents[] = {
	PLL_SHARED0_D4,
	PLL_SHARED1_D4,
	PLL_MMC_D2,
	OSCCLK_CMU,
};
enum clk_id cmucal_mux_clkcmu_mif_busp_parents[] = {
	PLL_SHARED0_D4,
	PLL_SHARED1_D4,
};
enum clk_id cmucal_mux_clkcmu_peri_ip_parents[] = {
	PLL_SHARED0_D4,
	PLL_SHARED1_D4,
};
enum clk_id cmucal_mux_clkcmu_dpu_bus_parents[] = {
	PLL_SHARED1_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
	PLL_SHARED0_D4,
};
enum clk_id cmucal_mux_clkcmu_cpucl1_switch_parents[] = {
	PLL_SHARED0_D2,
	PLL_SHARED1_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
};
enum clk_id cmucal_mux_clkcmu_usb_bus_parents[] = {
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
	PLL_SHARED0_D4,
	PLL_SHARED1_D4,
};
enum clk_id cmucal_mux_clkcmu_tnr_bus_parents[] = {
	PLL_SHARED1_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
	PLL_SHARED0_D4,
};
enum clk_id cmucal_mux_clkcmu_peri_mmc_card_parents[] = {
	OSCCLK_CMU,
	PLL_SHARED0_D2,
	PLL_MMC,
	PLL_SHARED1_D2,
};
enum clk_id cmucal_mux_clkcmu_cmu_boost_parents[] = {
	PLL_SHARED0_D4,
	PLL_SHARED1_D4,
};
enum clk_id cmucal_mux_clkcmu_core_g3d_parents[] = {
	PLL_G3D,
	PLL_SHARED1_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
};
enum clk_id cmucal_mux_clkcmu_csis_bus_parents[] = {
	PLL_SHARED1_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
	PLL_SHARED0_D4,
};
enum clk_id cmucal_mux_clkcmu_mcsc_bus_parents[] = {
	PLL_SHARED1_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
	PLL_SHARED0_D4,
};
enum clk_id cmucal_mux_clkcmu_mcsc_gdc_parents[] = {
	PLL_SHARED1_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
	PLL_SHARED0_D4,
};
enum clk_id cmucal_mux_clkcmu_usb_usb20drd_parents[] = {
	OSCCLK_CMU,
	PLL_SHARED0_D3,
	PLL_SHARED0_D4,
	PLL_SHARED1_D4,
};
enum clk_id cmucal_mux_clkcmu_npus_bus_parents[] = {
	PLL_SHARED0_D2,
	PLL_SHARED1_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
};
enum clk_id cmucal_mux_clkcmu_g3d_switch_parents[] = {
	PLL_SHARED0_D2,
	PLL_SHARED1_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
};
enum clk_id cmucal_mux_clkcmu_core_sss_parents[] = {
	PLL_SHARED0_D2,
	PLL_SHARED1_D4,
};
enum clk_id cmucal_mux_clkcmu_busc_bus_parents[] = {
	PLL_SHARED0_D2,
	PLL_SHARED1_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
};
enum clk_id cmucal_mux_clkcmu_cis_clk3_parents[] = {
	OSCCLK_CMU,
	PLL_SHARED0_D4,
};
enum clk_id cmucal_mux_clkcmu_cis_clk4_parents[] = {
	OSCCLK_CMU,
	PLL_SHARED0_D4,
};
enum clk_id cmucal_clkcmu_g3d_bus_parents[] = {
	PLL_G3D,
	CLKCMU_G3D_SWITCH,
};
enum clk_id cmucal_mux_clkcmu_cis_clk5_parents[] = {
	OSCCLK_CMU,
	PLL_SHARED0_D4,
};
enum clk_id cmucal_mux_clkcmu_dsu_switch_parents[] = {
	PLL_SHARED0_D2,
	PLL_SHARED1_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
};
enum clk_id cmucal_mux_clkcmu_cpucl0_busp_parents[] = {
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
	PLL_SHARED0_D4,
	PLL_SHARED1_D4,
};
enum clk_id cmucal_mux_clkcmu_dpu_dsim_parents[] = {
	PLL_SHARED0_D4,
	PLL_SHARED1_D4,
};
enum clk_id cmucal_mux_clkcmu_mcsc_mcsc_parents[] = {
	PLL_SHARED1_D2,
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
	PLL_SHARED0_D4,
};
enum clk_id cmucal_mux_clkcmu_aud_bus_parents[] = {
	PLL_SHARED0_D3,
	PLL_SHARED1_D3,
	PLL_SHARED0_D4,
	PLL_SHARED1_D4,
};
enum clk_id cmucal_mux_core_cmuref_parents[] = {
	OSCCLK_CORE,
	CLKCMU_CMU_BOOST,
};
enum clk_id cmucal_mux_clk_core_gic_parents[] = {
	DIV_CLK_CORE_BUSP,
	OSCCLK_CORE,
};
enum clk_id cmucal_mux_clk_cpucl0_pll_parents[] = {
	PLL_CPUCL0,
	MUX_CLKCMU_CPUCL0_SWITCH_USER,
	OSCCLK_CPUCL0,
};
enum clk_id cmucal_mux_cpucl0_cmuref_parents[] = {
	OSCCLK_CPUCL0,
	CLKCMU_CMU_BOOST,
};
enum clk_id cmucal_mux_clk_cpucl1_pll_parents[] = {
	PLL_CPUCL1,
	MUX_CLKCMU_CPUCL1_SWITCH_USER,
	OSCCLK_CPUCL1,
};
enum clk_id cmucal_mux_cpucl1_cmuref_parents[] = {
	OSCCLK_CPUCL1,
	CLKCMU_CMU_BOOST,
};
enum clk_id cmucal_mux_dsu_cmuref_parents[] = {
	OSCCLK_DSU,
	CLKCMU_CMU_BOOST,
};
enum clk_id cmucal_mux_clk_dsu_pll_parents[] = {
	PLL_DSU,
	MUX_CLKCMU_DSU_SWITCH_USER,
	OSCCLK_DSU,
};
enum clk_id cmucal_mux_mif_cmuref_parents[] = {
	OSCCLK_MIF,
	CLKCMU_CMU_BOOST,
};
enum clk_id cmucal_mux_clk_s2d_core_parents[] = {
	OSCCLK_S2D,
	CLK_MIF_BUSD_S2D,
};
enum clk_id cmucal_mux_clk_usb_bus_parents[] = {
	MUX_CLKCMU_USB_BUS_USER,
	MUX_CLKAUD_USB_BUS_USER,
};
enum clk_id cmucal_mux_clk_usb_usb20drd_parents[] = {
	MUX_CLKCMU_USB_USB20DRD_USER,
	MUX_CLKAUD_USB_USB20DRD_USER,
};
enum clk_id cmucal_mux_clk_vts_bus_parents[] = {
	MUX_CLKCMU_VTS_RCO_USER,
	MUX_CLKCMU_VTS_BUS_USER,
};
enum clk_id cmucal_mux_vts_dmic_aud_parents[] = {
	MUX_CLK_AUD_DMIC_BUS_USER,
	MUX_CLKCMU_VTS_RCO_USER,
};
enum clk_id cmucal_mux_vts_serial_lif_parents[] = {
	MUX_CLKCMU_VTS_RCO_USER,
	MUX_CLK_AUD_DMIC_BUS_USER,
};
enum clk_id cmucal_mux_clk_vts_dmic_if_parents[] = {
	MUX_CLK_AUD_DMIC_BUS_USER,
	MUX_CLKCMU_VTS_RCO_USER,
};
enum clk_id cmucal_mux_clkcmu_alive_bus_user_parents[] = {
	OSCCLK_RCO_ALIVE,
	CLKCMU_ALIVE_BUS,
};
enum clk_id cmucal_mux_clk_rco_alive_user_parents[] = {
	OSCCLK_RCO_ALIVE,
	CLK_RCO_ALIVE,
};
enum clk_id cmucal_mux_clkmux_alive_rco_i3c_pmic_user_parents[] = {
	OSCCLK_RCO_ALIVE,
	CLK_RCO_I3C_PMIC,
};
enum clk_id cmucal_mux_clk_alive_timer_parents[] = {
	OSCCLK_RCO_ALIVE,
	OSCCLK_ALIVE,
};
enum clk_id cmucal_mux_clkcmu_aud_cpu_user_parents[] = {
	OSCCLK_AUD,
	CLKCMU_AUD_CPU,
};
enum clk_id cmucal_mux_clkcmu_aud_bus_user_parents[] = {
	OSCCLK_AUD,
	CLKCMU_AUD_BUS,
};
enum clk_id cmucal_mux_cp_pcmc_clk_user_parents[] = {
	OSCCLK_AUD,
	PCMC_CLK,
};
enum clk_id cmucal_mux_clkcmu_busc_bus_user_parents[] = {
	OSCCLK_BUSC,
	CLKCMU_BUSC_BUS,
};
enum clk_id cmucal_mux_clk_chub_bus_user_parents[] = {
	OSCCLK_RCO_CHUB,
	CLKCMU_CHUBVTS_BUS,
};
enum clk_id cmucal_mux_clkcmu_chub_peri_user_parents[] = {
	OSCCLK_RCO_CHUB,
	CLKCMU_CHUB_PERI,
};
enum clk_id cmucal_mux_clkcmu_chub_rco_user_parents[] = {
	OSCCLK_RCO_CHUB,
	CLKCMU_CHUB_RCO,
};
enum clk_id cmucal_mux_clkcmu_chubvts_bus_user_parents[] = {
	OSCCLK_RCO_CHUBVTS,
	CLKCMU_CHUBVTS_BUS,
};
enum clk_id cmucal_mux_clkcmu_chubvts_rco_user_parents[] = {
	OSCCLK_RCO_CHUBVTS,
	CLKCMU_CHUBVTS_RCO,
};
enum clk_id cmucal_mux_clkcmu_cmgp_bus_user_parents[] = {
	OSCCLK_RCO_CMGP,
	CLKCMU_CMGP_BUS,
};
enum clk_id cmucal_mux_clkcmu_cmgp_peri_user_parents[] = {
	OSCCLK_RCO_CMGP,
	CLKCMU_CMGP_PERI,
};
enum clk_id cmucal_mux_clkcmu_cmgp_rco_user_parents[] = {
	OSCCLK_RCO_CMGP,
	CLKCMU_CMGP_RCO,
};
enum clk_id cmucal_mux_clkcmu_core_bus_user_parents[] = {
	OSCCLK_CORE,
	CLKCMU_CORE_BUS,
};
enum clk_id cmucal_mux_clkcmu_core_g3d_user_parents[] = {
	OSCCLK_CORE,
	CLKCMU_CORE_G3D,
};
enum clk_id cmucal_mux_clkcmu_core_sss_user_parents[] = {
	OSCCLK_CORE,
	CLKCMU_CORE_SSS,
};
enum clk_id cmucal_mux_clkcmu_cpucl0_switch_user_parents[] = {
	OSCCLK_CPUCL0,
	CLKCMU_CPUCL0_SWITCH,
};
enum clk_id cmucal_mux_clkcmu_cpucl0_dbg_bus_user_parents[] = {
	OSCCLK_CPUCL0,
	CLKCMU_CPUCL0_DBG_BUS,
};
enum clk_id cmucal_mux_clkcmu_cpucl0_busp_user_parents[] = {
	OSCCLK_CPUCL0,
	CLKCMU_CPUCL0_BUSP,
};
enum clk_id cmucal_mux_clkcmu_cpucl1_switch_user_parents[] = {
	OSCCLK_CPUCL1,
	CLKCMU_CPUCL1_SWITCH,
};
enum clk_id cmucal_mux_clkcmu_csis_bus_user_parents[] = {
	OSCCLK_CSIS,
	CLKCMU_CSIS_BUS,
};
enum clk_id cmucal_mux_clkcmu_dpu_bus_user_parents[] = {
	OSCCLK_DPU,
	CLKCMU_DPU_BUS,
};
enum clk_id cmucal_mux_clkcmu_dpu_dsim_user_parents[] = {
	OSCCLK_DPU,
	CLKCMU_DPU_DSIM,
};
enum clk_id cmucal_mux_clkcmu_dsu_switch_user_parents[] = {
	OSCCLK_DSU,
	CLKCMU_DSU_SWITCH,
};
enum clk_id cmucal_mux_clkcmu_g3d_bus_user_parents[] = {
	OSCCLK_G3D,
	CLKCMU_G3D_BUS,
};
enum clk_id cmucal_mux_clkcmu_hsi_bus_user_parents[] = {
	OSCCLK_HSI,
	CLKCMU_HSI_BUS,
};
enum clk_id cmucal_mux_clkcmu_hsi_ufs_embd_user_parents[] = {
	OSCCLK_HSI,
	CLKCMU_HSI_UFS_EMBD,
};
enum clk_id cmucal_mux_clkcmu_isp_bus_user_parents[] = {
	OSCCLK_ISP,
	CLKCMU_ISP_BUS,
};
enum clk_id cmucal_mux_clkcmu_m2m_mscl_user_parents[] = {
	OSCCLK_M2M,
	CLKCMU_M2M_MSCL,
};
enum clk_id cmucal_mux_clkcmu_mcsc_bus_user_parents[] = {
	OSCCLK_MCSC,
	CLKCMU_MCSC_BUS,
};
enum clk_id cmucal_mux_clkcmu_mcsc_gdc_user_parents[] = {
	OSCCLK_MCSC,
	CLKCMU_MCSC_GDC,
};
enum clk_id cmucal_mux_clkcmu_mcsc_mcsc_user_parents[] = {
	OSCCLK_MCSC,
	CLKCMU_MCSC_MCSC,
};
enum clk_id cmucal_mux_clkcmu_mfc_mfc_user_parents[] = {
	OSCCLK_MFC,
	CLKCMU_MFC_MFC,
};
enum clk_id cmucal_mux_clkcmu_mif_busp_user_parents[] = {
	OSCCLK_MIF,
	CLKCMU_MIF_BUSP,
};
enum clk_id cmucal_clkmux_mif_ddrphy2x_parents[] = {
	OSCCLK_MIF,
	CLKCMU_MIF_SWITCH,
	PLL_MIF,
};
enum clk_id cmucal_mux_clkcmu_npu0_bus_user_parents[] = {
	OSCCLK_NPU0,
	CLKCMU_NPU0_BUS,
};
enum clk_id cmucal_mux_clkcmu_npus_bus_user_parents[] = {
	OSCCLK_NPUS,
	CLKCMU_NPUS_BUS,
};
enum clk_id cmucal_mux_clkcmu_peri_bus_user_parents[] = {
	OSCCLK_PERI,
	CLKCMU_PERI_BUS,
};
enum clk_id cmucal_mux_clkcmu_peri_usi00_usi_user_parents[] = {
	OSCCLK_PERI,
	CLKCMU_PERI_IP,
};
enum clk_id cmucal_mux_clkcmu_peri_usi01_usi_user_parents[] = {
	OSCCLK_PERI,
	CLKCMU_PERI_IP,
};
enum clk_id cmucal_mux_clkcmu_peri_usi02_usi_user_parents[] = {
	OSCCLK_PERI,
	CLKCMU_PERI_IP,
};
enum clk_id cmucal_mux_clkcmu_peri_usi03_usi_user_parents[] = {
	OSCCLK_PERI,
	CLKCMU_PERI_IP,
};
enum clk_id cmucal_mux_clkcmu_peri_usi04_usi_user_parents[] = {
	OSCCLK_PERI,
	CLKCMU_PERI_IP,
};
enum clk_id cmucal_mux_clkcmu_peri_usi05_usi_user_parents[] = {
	OSCCLK_PERI,
	CLKCMU_PERI_IP,
};
enum clk_id cmucal_mux_clkcmu_peri_usi_i2c_user_parents[] = {
	OSCCLK_PERI,
	CLKCMU_PERI_IP,
};
enum clk_id cmucal_mux_clkcmu_peri_uart_dbg_parents[] = {
	OSCCLK_PERI,
	CLKCMU_PERI_IP,
};
enum clk_id cmucal_mux_clkcmu_peri_mmc_card_user_parents[] = {
	OSCCLK_PERI,
	CLKCMU_PERI_MMC_CARD,
};
enum clk_id cmucal_mux_clkcmu_peri_usi06_usi_user_parents[] = {
	OSCCLK_PERI,
	CLKCMU_PERI_IP,
};
enum clk_id cmucal_clkcmu_mif_ddrphy2x_s2d_parents[] = {
	OSCCLK_S2D,
	PLL_MIF_S2D,
};
enum clk_id cmucal_mux_clkcmu_taa_bus_user_parents[] = {
	OSCCLK_TAA,
	CLKCMU_TAA_BUS,
};
enum clk_id cmucal_mux_clkcmu_tnr_bus_user_parents[] = {
	OSCCLK_TNR,
	CLKCMU_TNR_BUS,
};
enum clk_id cmucal_mux_clkcmu_usb_bus_user_parents[] = {
	OSCCLK_USB,
	CLKCMU_USB_BUS,
};
enum clk_id cmucal_mux_clkcmu_usb_usb20drd_user_parents[] = {
	OSCCLK_USB,
	CLKCMU_USB_USB20DRD,
};
enum clk_id cmucal_mux_clkaud_usb_bus_user_parents[] = {
	OSCCLK_USB,
	CLKAUD_USB_BUS,
};
enum clk_id cmucal_mux_clkaud_usb_usb20drd_user_parents[] = {
	OSCCLK_USB,
	CLKAUD_USB_USB20DRD,
};
enum clk_id cmucal_mux_clkcmu_vts_bus_user_parents[] = {
	OSCCLK_RCO_VTS,
	CLKCMU_CHUBVTS_BUS,
};
enum clk_id cmucal_mux_clkcmu_vts_rco_user_parents[] = {
	OSCCLK_RCO_VTS,
	CLKCMU_VTS_RCO,
};
enum clk_id cmucal_mux_clk_aud_dmic_bus_user_parents[] = {
	OSCCLK_RCO_VTS,
	CLK_AUD_DMIC,
};
enum clk_id cmucal_mux_hchgen_clk_aud_cpu_parents[] = {
	MUX_CLK_AUD_CPU,
	OSCCLK_AUD,
};
unsigned int cmucal_mux_size = 190;
struct cmucal_mux cmucal_mux_list[] = {
	CLK_MUX(MUX_CLKCMU_CMGP_BUS, cmucal_mux_clkcmu_cmgp_bus_parents, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_ALIVE_BUS, cmucal_mux_clk_alive_bus_parents, CLK_CON_MUX_MUX_CLK_ALIVE_BUS_SELECT, CLK_CON_MUX_MUX_CLK_ALIVE_BUS_BUSY, CLK_CON_MUX_MUX_CLK_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CMGP_PERI, cmucal_mux_clkcmu_cmgp_peri_parents, CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_SELECT, CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_BUSY, CLK_CON_MUX_MUX_CLKCMU_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_ALIVE_I3C_PMIC, cmucal_mux_clk_alive_i3c_pmic_parents, CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_SELECT, CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_BUSY, CLK_CON_MUX_MUX_CLK_ALIVE_I3C_PMIC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CHUBVTS_BUS, cmucal_mux_clkcmu_chubvts_bus_parents, CLK_CON_MUX_MUX_CLKCMU_CHUBVTS_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CHUBVTS_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CHUBVTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_ALIVE_DBGCORE_UART, cmucal_mux_clk_alive_dbgcore_uart_parents, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_SELECT, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_BUSY, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_AP2GNSS, cmucal_mux_clkcmu_ap2gnss_parents, CLK_CON_MUX_MUX_CLKCMU_AP2GNSS_SELECT, CLK_CON_MUX_MUX_CLKCMU_AP2GNSS_BUSY, CLK_CON_MUX_MUX_CLKCMU_AP2GNSS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CHUB_PERI, cmucal_mux_clkcmu_chub_peri_parents, CLK_CON_MUX_MUX_CLKCMU_CHUB_PERI_SELECT, CLK_CON_MUX_MUX_CLKCMU_CHUB_PERI_BUSY, CLK_CON_MUX_MUX_CLKCMU_CHUB_PERI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_ALIVE_USI0, cmucal_mux_clk_alive_usi0_parents, CLK_CON_MUX_MUX_CLK_ALIVE_USI0_SELECT, CLK_CON_MUX_MUX_CLK_ALIVE_USI0_BUSY, CLK_CON_MUX_MUX_CLK_ALIVE_USI0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_ALIVE_I2C, cmucal_mux_clk_alive_i2c_parents, CLK_CON_MUX_MUX_CLK_ALIVE_I2C_SELECT, CLK_CON_MUX_MUX_CLK_ALIVE_I2C_BUSY, CLK_CON_MUX_MUX_CLK_ALIVE_I2C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_AUD_UAIF3, cmucal_mux_clk_aud_uaif3_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF3_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF3_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_AUD_UAIF2, cmucal_mux_clk_aud_uaif2_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_AUD_UAIF1, cmucal_mux_clk_aud_uaif1_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_AUD_UAIF0, cmucal_mux_clk_aud_uaif0_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_AUD_CPU, cmucal_mux_clk_aud_cpu_parents, CLK_CON_MUX_MUX_CLK_AUD_CPU_SELECT, CLK_CON_MUX_MUX_CLK_AUD_CPU_BUSY, CLK_CON_MUX_MUX_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_AUD_FM, cmucal_mux_clk_aud_fm_parents, CLK_CON_MUX_MUX_CLK_AUD_FM_SELECT, CLK_CON_MUX_MUX_CLK_AUD_FM_BUSY, CLK_CON_MUX_MUX_CLK_AUD_FM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_AUD_UAIF4, cmucal_mux_clk_aud_uaif4_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF4_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF4_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF4_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_AUD_UAIF5, cmucal_mux_clk_aud_uaif5_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF5_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF5_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF5_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_AUD_UAIF6, cmucal_mux_clk_aud_uaif6_parents, CLK_CON_MUX_MUX_CLK_AUD_UAIF6_SELECT, CLK_CON_MUX_MUX_CLK_AUD_UAIF6_BUSY, CLK_CON_MUX_MUX_CLK_AUD_UAIF6_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_AUD_DSIF, cmucal_mux_clk_aud_dsif_parents, CLK_CON_MUX_MUX_CLK_AUD_DSIF_SELECT, CLK_CON_MUX_MUX_CLK_AUD_DSIF_BUSY, CLK_CON_MUX_MUX_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_AUD_CPU_PLL, cmucal_mux_clk_aud_cpu_pll_parents, CLK_CON_MUX_MUX_CLK_AUD_CPU_PLL_SELECT, CLK_CON_MUX_MUX_CLK_AUD_CPU_PLL_BUSY, CLK_CON_MUX_MUX_CLK_AUD_CPU_PLL_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_AUD_BUS, cmucal_mux_clk_aud_bus_parents, CLK_CON_MUX_MUX_CLK_AUD_BUS_SELECT, CLK_CON_MUX_MUX_CLK_AUD_BUS_BUSY, CLK_CON_MUX_MUX_CLK_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_AUD_PCMC, cmucal_mux_clk_aud_pcmc_parents, CLK_CON_MUX_MUX_CLK_AUD_PCMC_SELECT, CLK_CON_MUX_MUX_CLK_AUD_PCMC_BUSY, CLK_CON_MUX_MUX_CLK_AUD_PCMC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_BUSC_CMUREF, cmucal_mux_busc_cmuref_parents, CLK_CON_MUX_MUX_BUSC_CMUREF_SELECT, CLK_CON_MUX_MUX_BUSC_CMUREF_BUSY, CLK_CON_MUX_MUX_BUSC_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CHUB_TIMER, cmucal_mux_clk_chub_timer_parents, CLK_CON_MUX_MUX_CLK_CHUB_TIMER_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_TIMER_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_TIMER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CHUB_USI0, cmucal_mux_clk_chub_usi0_parents, CLK_CON_MUX_MUX_CLK_CHUB_USI0_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_USI0_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_USI0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CHUB_USI1, cmucal_mux_clk_chub_usi1_parents, CLK_CON_MUX_MUX_CLK_CHUB_USI1_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_USI1_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_USI1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CHUB_USI2, cmucal_mux_clk_chub_usi2_parents, CLK_CON_MUX_MUX_CLK_CHUB_USI2_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_USI2_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_USI2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CHUB_I2C, cmucal_mux_clk_chub_i2c_parents, CLK_CON_MUX_MUX_CLK_CHUB_I2C_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_I2C_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CHUB_USI3, cmucal_mux_clk_chub_usi3_parents, CLK_CON_MUX_MUX_CLK_CHUB_USI3_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_USI3_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_USI3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CHUB_BUS, cmucal_mux_clk_chub_bus_parents, CLK_CON_MUX_MUX_CLK_CHUB_BUS_SELECT, CLK_CON_MUX_MUX_CLK_CHUB_BUS_BUSY, CLK_CON_MUX_MUX_CLK_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CHUBVTS_BUS, cmucal_mux_clk_chubvts_bus_parents, CLK_CON_MUX_MUX_CLK_CHUBVTS_BUS_SELECT, CLK_CON_MUX_MUX_CLK_CHUBVTS_BUS_BUSY, CLK_CON_MUX_MUX_CLK_CHUBVTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CMGP_I2C, cmucal_mux_clk_cmgp_i2c_parents, CLK_CON_MUX_MUX_CLK_CMGP_I2C_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_I2C_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CMGP_USI0, cmucal_mux_clk_cmgp_usi0_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI0_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI0_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CMGP_USI4, cmucal_mux_clk_cmgp_usi4_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI4_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI4_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI4_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CMGP_I3C, cmucal_mux_clk_cmgp_i3c_parents, CLK_CON_MUX_MUX_CLK_CMGP_I3C_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_I3C_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_I3C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CMGP_BUS, cmucal_mux_clk_cmgp_bus_parents, CLK_CON_MUX_MUX_CLK_CMGP_BUS_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_BUS_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CMGP_USI1, cmucal_mux_clk_cmgp_usi1_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI1_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI1_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CMGP_USI2, cmucal_mux_clk_cmgp_usi2_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI2_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI2_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CMGP_USI3, cmucal_mux_clk_cmgp_usi3_parents, CLK_CON_MUX_MUX_CLK_CMGP_USI3_SELECT, CLK_CON_MUX_MUX_CLK_CMGP_USI3_BUSY, CLK_CON_MUX_MUX_CLK_CMGP_USI3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_MFC_MFC, cmucal_mux_clkcmu_mfc_mfc_parents, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_SELECT, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CORE_BUS, cmucal_mux_clkcmu_core_bus_parents, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CPUCL0_SWITCH, cmucal_mux_clkcmu_cpucl0_switch_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_MIF_SWITCH, cmucal_mux_clkcmu_mif_switch_parents, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_TAA_BUS, cmucal_mux_clkcmu_taa_bus_parents, CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_ISP_BUS, cmucal_mux_clkcmu_isp_bus_parents, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_AUD_CPU, cmucal_mux_clkcmu_aud_cpu_parents, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_SELECT, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_BUSY, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_M2M_MSCL, cmucal_mux_clkcmu_m2m_mscl_parents, CLK_CON_MUX_MUX_CLKCMU_M2M_MSCL_SELECT, CLK_CON_MUX_MUX_CLKCMU_M2M_MSCL_BUSY, CLK_CON_MUX_MUX_CLKCMU_M2M_MSCL_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CPUCL0_DBG_BUS, cmucal_mux_clkcmu_cpucl0_dbg_bus_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CIS_CLK0, cmucal_mux_clkcmu_cis_clk0_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CIS_CLK1, cmucal_mux_clkcmu_cis_clk1_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CIS_CLK2, cmucal_mux_clkcmu_cis_clk2_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_HSI_UFS_EMBD, cmucal_mux_clkcmu_hsi_ufs_embd_parents, CLK_CON_MUX_MUX_CLKCMU_HSI_UFS_EMBD_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI_UFS_EMBD_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CMU_CMUREF, cmucal_mux_cmu_cmuref_parents, CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERI_BUS, cmucal_mux_clkcmu_peri_bus_parents, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_NPU0_BUS, cmucal_mux_clkcmu_npu0_bus_parents, CLK_CON_MUX_MUX_CLKCMU_NPU0_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_NPU0_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_NPU0_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_ALIVE_BUS, cmucal_mux_clkcmu_alive_bus_parents, CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_HSI_BUS, cmucal_mux_clkcmu_hsi_bus_parents, CLK_CON_MUX_MUX_CLKCMU_HSI_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_MIF_BUSP, cmucal_mux_clkcmu_mif_busp_parents, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERI_IP, cmucal_mux_clkcmu_peri_ip_parents, CLK_CON_MUX_MUX_CLKCMU_PERI_IP_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_IP_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_DPU_BUS, cmucal_mux_clkcmu_dpu_bus_parents, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CPUCL1_SWITCH, cmucal_mux_clkcmu_cpucl1_switch_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_USB_BUS, cmucal_mux_clkcmu_usb_bus_parents, CLK_CON_MUX_MUX_CLKCMU_USB_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_USB_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_TNR_BUS, cmucal_mux_clkcmu_tnr_bus_parents, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERI_MMC_CARD, cmucal_mux_clkcmu_peri_mmc_card_parents, CLK_CON_MUX_MUX_CLKCMU_PERI_MMC_CARD_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERI_MMC_CARD_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERI_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CMU_BOOST, cmucal_mux_clkcmu_cmu_boost_parents, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_SELECT, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_BUSY, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CORE_G3D, cmucal_mux_clkcmu_core_g3d_parents, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_SELECT, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_BUSY, CLK_CON_MUX_MUX_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CSIS_BUS, cmucal_mux_clkcmu_csis_bus_parents, CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_MCSC_BUS, cmucal_mux_clkcmu_mcsc_bus_parents, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_MCSC_GDC, cmucal_mux_clkcmu_mcsc_gdc_parents, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_SELECT, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_BUSY, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_USB_USB20DRD, cmucal_mux_clkcmu_usb_usb20drd_parents, CLK_CON_MUX_MUX_CLKCMU_USB_USB20DRD_SELECT, CLK_CON_MUX_MUX_CLKCMU_USB_USB20DRD_BUSY, CLK_CON_MUX_MUX_CLKCMU_USB_USB20DRD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_NPUS_BUS, cmucal_mux_clkcmu_npus_bus_parents, CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_G3D_SWITCH, cmucal_mux_clkcmu_g3d_switch_parents, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CORE_SSS, cmucal_mux_clkcmu_core_sss_parents, CLK_CON_MUX_MUX_CLKCMU_CORE_SSS_SELECT, CLK_CON_MUX_MUX_CLKCMU_CORE_SSS_BUSY, CLK_CON_MUX_MUX_CLKCMU_CORE_SSS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_BUSC_BUS, cmucal_mux_clkcmu_busc_bus_parents, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CIS_CLK3, cmucal_mux_clkcmu_cis_clk3_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CIS_CLK4, cmucal_mux_clkcmu_cis_clk4_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CLKCMU_G3D_BUS, cmucal_clkcmu_g3d_bus_parents, CLK_CON_MUX_CLKCMU_G3D_BUS_SELECT, CLK_CON_MUX_CLKCMU_G3D_BUS_BUSY, CLK_CON_MUX_CLKCMU_G3D_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CIS_CLK5, cmucal_mux_clkcmu_cis_clk5_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_DSU_SWITCH, cmucal_mux_clkcmu_dsu_switch_parents, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CPUCL0_BUSP, cmucal_mux_clkcmu_cpucl0_busp_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_DPU_DSIM, cmucal_mux_clkcmu_dpu_dsim_parents, CLK_CON_MUX_MUX_CLKCMU_DPU_DSIM_SELECT, CLK_CON_MUX_MUX_CLKCMU_DPU_DSIM_BUSY, CLK_CON_MUX_MUX_CLKCMU_DPU_DSIM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_MCSC_MCSC, cmucal_mux_clkcmu_mcsc_mcsc_parents, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_SELECT, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_BUSY, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_AUD_BUS, cmucal_mux_clkcmu_aud_bus_parents, CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_SELECT, CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_BUSY, CLK_CON_MUX_MUX_CLKCMU_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CORE_CMUREF, cmucal_mux_core_cmuref_parents, CLK_CON_MUX_MUX_CORE_CMUREF_SELECT, CLK_CON_MUX_MUX_CORE_CMUREF_BUSY, CLK_CON_MUX_MUX_CORE_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CORE_GIC, cmucal_mux_clk_core_gic_parents, CLK_CON_MUX_MUX_CLK_CORE_GIC_SELECT, CLK_CON_MUX_MUX_CLK_CORE_GIC_BUSY, CLK_CON_MUX_MUX_CLK_CORE_GIC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CPUCL0_PLL, cmucal_mux_clk_cpucl0_pll_parents, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CPUCL0_CMUREF, cmucal_mux_cpucl0_cmuref_parents, CLK_CON_MUX_MUX_CPUCL0_CMUREF_SELECT, CLK_CON_MUX_MUX_CPUCL0_CMUREF_BUSY, CLK_CON_MUX_MUX_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_CPUCL1_PLL, cmucal_mux_clk_cpucl1_pll_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CPUCL1_CMUREF, cmucal_mux_cpucl1_cmuref_parents, CLK_CON_MUX_MUX_CPUCL1_CMUREF_SELECT, CLK_CON_MUX_MUX_CPUCL1_CMUREF_BUSY, CLK_CON_MUX_MUX_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_DSU_CMUREF, cmucal_mux_dsu_cmuref_parents, CLK_CON_MUX_MUX_DSU_CMUREF_SELECT, CLK_CON_MUX_MUX_DSU_CMUREF_BUSY, CLK_CON_MUX_MUX_DSU_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_DSU_PLL, cmucal_mux_clk_dsu_pll_parents, CLK_CON_MUX_MUX_CLK_DSU_PLL_SELECT, CLK_CON_MUX_MUX_CLK_DSU_PLL_BUSY, CLK_CON_MUX_MUX_CLK_DSU_PLL_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_MIF_CMUREF, cmucal_mux_mif_cmuref_parents, CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_S2D_CORE, cmucal_mux_clk_s2d_core_parents, CLK_CON_MUX_MUX_CLK_S2D_CORE_SELECT, CLK_CON_MUX_MUX_CLK_S2D_CORE_BUSY, CLK_CON_MUX_MUX_CLK_S2D_CORE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_USB_BUS, cmucal_mux_clk_usb_bus_parents, CLK_CON_MUX_MUX_CLK_USB_BUS_SELECT, CLK_CON_MUX_MUX_CLK_USB_BUS_BUSY, CLK_CON_MUX_MUX_CLK_USB_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_USB_USB20DRD, cmucal_mux_clk_usb_usb20drd_parents, CLK_CON_MUX_MUX_CLK_USB_USB20DRD_SELECT, CLK_CON_MUX_MUX_CLK_USB_USB20DRD_BUSY, CLK_CON_MUX_MUX_CLK_USB_USB20DRD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_VTS_BUS, cmucal_mux_clk_vts_bus_parents, CLK_CON_MUX_MUX_CLK_VTS_BUS_SELECT, CLK_CON_MUX_MUX_CLK_VTS_BUS_BUSY, CLK_CON_MUX_MUX_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_VTS_DMIC_AUD, cmucal_mux_vts_dmic_aud_parents, CLK_CON_MUX_MUX_VTS_DMIC_AUD_SELECT, CLK_CON_MUX_MUX_VTS_DMIC_AUD_BUSY, CLK_CON_MUX_MUX_VTS_DMIC_AUD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_VTS_SERIAL_LIF, cmucal_mux_vts_serial_lif_parents, CLK_CON_MUX_MUX_VTS_SERIAL_LIF_SELECT, CLK_CON_MUX_MUX_VTS_SERIAL_LIF_BUSY, CLK_CON_MUX_MUX_VTS_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_VTS_DMIC_IF, cmucal_mux_clk_vts_dmic_if_parents, CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_SELECT, CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_BUSY, CLK_CON_MUX_MUX_CLK_VTS_DMIC_IF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(ALIVE_CMU_ALIVE_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(AUD_CMU_AUD_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(BUSC_CMU_BUSC_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(CHUB_CMU_CHUB_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(CHUBVTS_CMU_CHUBVTS_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(CMGP_CMU_CMGP_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(CMU_CMU_TOP_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(CORE_CMU_CORE_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(CPUCL0_CMU_CPUCL0_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(CPUCL0_GLB_CMU_CPUCL0_GLB_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(CPUCL1_CMU_CPUCL1_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(CSIS_CMU_CSIS_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(DPU_CMU_DPU_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(DSU_CMU_DSU_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(G3D_CMU_G3D_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(HSI_CMU_HSI_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(ISP_CMU_ISP_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(M2M_CMU_M2M_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(MCSC_CMU_MCSC_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(MFC_CMU_MFC_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(MIF_CMU_MIF_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(NPU0_CMU_NPU0_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(NPUS_CMU_NPUS_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(PERI_CMU_PERI_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(TAA_CMU_TAA_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(TNR_CMU_TNR_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(USB_CMU_USB_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(VTS_CMU_VTS_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID),
	CLK_MUX(MUX_CLKCMU_ALIVE_BUS_USER, cmucal_mux_clkcmu_alive_bus_user_parents, PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ALIVE_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_ALIVE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_RCO_ALIVE_USER, cmucal_mux_clk_rco_alive_user_parents, PLL_CON0_MUX_CLK_RCO_ALIVE_USER_MUX_SEL, PLL_CON0_MUX_CLK_RCO_ALIVE_USER_BUSY, PLL_CON1_MUX_CLK_RCO_ALIVE_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER, cmucal_mux_clkmux_alive_rco_i3c_pmic_user_parents, PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_MUX_SEL, PLL_CON0_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_BUSY, PLL_CON1_MUX_CLKMUX_ALIVE_RCO_I3C_PMIC_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_ALIVE_TIMER, cmucal_mux_clk_alive_timer_parents, PLL_CON0_MUX_CLK_ALIVE_TIMER_MUX_SEL, PLL_CON0_MUX_CLK_ALIVE_TIMER_BUSY, PLL_CON1_MUX_CLK_ALIVE_TIMER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_AUD_CPU_USER, cmucal_mux_clkcmu_aud_cpu_user_parents, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_AUD_CPU_USER_BUSY, PLL_CON1_MUX_CLKCMU_AUD_CPU_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_AUD_BUS_USER, cmucal_mux_clkcmu_aud_bus_user_parents, PLL_CON0_MUX_CLKCMU_AUD_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_AUD_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_AUD_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CP_PCMC_CLK_USER, cmucal_mux_cp_pcmc_clk_user_parents, PLL_CON0_MUX_CP_PCMC_CLK_USER_MUX_SEL, PLL_CON0_MUX_CP_PCMC_CLK_USER_BUSY, PLL_CON1_MUX_CP_PCMC_CLK_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_BUSC_BUS_USER, cmucal_mux_clkcmu_busc_bus_user_parents, PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_BUSC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),

	CLK_MUX(MUX_CLK_CHUB_BUS_USER, cmucal_mux_clk_chub_bus_user_parents, PLL_CON0_MUX_CLK_CHUB_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLK_CHUB_BUS_USER_BUSY, PLL_CON1_MUX_CLK_CHUB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CHUB_PERI_USER, cmucal_mux_clkcmu_chub_peri_user_parents, PLL_CON0_MUX_CLKCMU_CHUB_PERI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CHUB_PERI_USER_BUSY, PLL_CON1_MUX_CLKCMU_CHUB_PERI_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CHUB_RCO_USER, cmucal_mux_clkcmu_chub_rco_user_parents, PLL_CON0_MUX_CLKCMU_CHUB_RCO_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CHUB_RCO_USER_BUSY, PLL_CON1_MUX_CLKCMU_CHUB_RCO_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CHUBVTS_BUS_USER, cmucal_mux_clkcmu_chubvts_bus_user_parents, PLL_CON0_MUX_CLKCMU_CHUBVTS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CHUBVTS_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_CHUBVTS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CHUBVTS_RCO_USER, cmucal_mux_clkcmu_chubvts_rco_user_parents, PLL_CON0_MUX_CLKCMU_CHUBVTS_RCO_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CHUBVTS_RCO_USER_BUSY, PLL_CON1_MUX_CLKCMU_CHUBVTS_RCO_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CMGP_BUS_USER, cmucal_mux_clkcmu_cmgp_bus_user_parents, PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CMGP_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_CMGP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CMGP_PERI_USER, cmucal_mux_clkcmu_cmgp_peri_user_parents, PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CMGP_PERI_USER_BUSY, PLL_CON1_MUX_CLKCMU_CMGP_PERI_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CMGP_RCO_USER, cmucal_mux_clkcmu_cmgp_rco_user_parents, PLL_CON0_MUX_CLKCMU_CMGP_RCO_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CMGP_RCO_USER_BUSY, PLL_CON1_MUX_CLKCMU_CMGP_RCO_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CORE_BUS_USER, cmucal_mux_clkcmu_core_bus_user_parents, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_CORE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CORE_G3D_USER, cmucal_mux_clkcmu_core_g3d_user_parents, PLL_CON0_MUX_CLKCMU_CORE_G3D_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CORE_G3D_USER_BUSY, PLL_CON1_MUX_CLKCMU_CORE_G3D_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CORE_SSS_USER, cmucal_mux_clkcmu_core_sss_user_parents, PLL_CON0_MUX_CLKCMU_CORE_SSS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CORE_SSS_USER_BUSY, PLL_CON1_MUX_CLKCMU_CORE_SSS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CPUCL0_SWITCH_USER, cmucal_mux_clkcmu_cpucl0_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CPUCL0_DBG_BUS_USER, cmucal_mux_clkcmu_cpucl0_dbg_bus_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CPUCL0_BUSP_USER, cmucal_mux_clkcmu_cpucl0_busp_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_BUSP_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL0_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CPUCL1_SWITCH_USER, cmucal_mux_clkcmu_cpucl1_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_CSIS_BUS_USER, cmucal_mux_clkcmu_csis_bus_user_parents, PLL_CON0_MUX_CLKCMU_CSIS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CSIS_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_CSIS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_DPU_BUS_USER, cmucal_mux_clkcmu_dpu_bus_user_parents, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_DPU_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_DPU_DSIM_USER, cmucal_mux_clkcmu_dpu_dsim_user_parents, PLL_CON0_MUX_CLKCMU_DPU_DSIM_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DPU_DSIM_USER_BUSY, PLL_CON1_MUX_CLKCMU_DPU_DSIM_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_DSU_SWITCH_USER, cmucal_mux_clkcmu_dsu_switch_user_parents, PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DSU_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_DSU_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_G3D_BUS_USER, cmucal_mux_clkcmu_g3d_bus_user_parents, PLL_CON0_MUX_CLKCMU_G3D_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G3D_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_G3D_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_HSI_BUS_USER, cmucal_mux_clkcmu_hsi_bus_user_parents, PLL_CON0_MUX_CLKCMU_HSI_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_HSI_UFS_EMBD_USER, cmucal_mux_clkcmu_hsi_ufs_embd_user_parents, PLL_CON0_MUX_CLKCMU_HSI_UFS_EMBD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI_UFS_EMBD_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_ISP_BUS_USER, cmucal_mux_clkcmu_isp_bus_user_parents, PLL_CON0_MUX_CLKCMU_ISP_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ISP_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_ISP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_M2M_MSCL_USER, cmucal_mux_clkcmu_m2m_mscl_user_parents, PLL_CON0_MUX_CLKCMU_M2M_MSCL_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_M2M_MSCL_USER_BUSY, PLL_CON1_MUX_CLKCMU_M2M_MSCL_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_MCSC_BUS_USER, cmucal_mux_clkcmu_mcsc_bus_user_parents, PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MCSC_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_MCSC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_MCSC_GDC_USER, cmucal_mux_clkcmu_mcsc_gdc_user_parents, PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MCSC_GDC_USER_BUSY, PLL_CON1_MUX_CLKCMU_MCSC_GDC_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_MCSC_MCSC_USER, cmucal_mux_clkcmu_mcsc_mcsc_user_parents, PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER_BUSY, PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_MFC_MFC_USER, cmucal_mux_clkcmu_mfc_mfc_user_parents, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_BUSY, PLL_CON1_MUX_CLKCMU_MFC_MFC_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_MIF_BUSP_USER, cmucal_mux_clkcmu_mif_busp_user_parents, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MIF_BUSP_USER_BUSY, PLL_CON1_MUX_CLKCMU_MIF_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CLKMUX_MIF_DDRPHY2X, cmucal_clkmux_mif_ddrphy2x_parents, PLL_CON0_CLKMUX_MIF_DDRPHY2X_MUX_SEL, PLL_CON0_CLKMUX_MIF_DDRPHY2X_BUSY, PLL_CON1_CLKMUX_MIF_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_NPU0_BUS_USER, cmucal_mux_clkcmu_npu0_bus_user_parents, PLL_CON0_MUX_CLKCMU_NPU0_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_NPU0_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_NPU0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_NPUS_BUS_USER, cmucal_mux_clkcmu_npus_bus_user_parents, PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_NPUS_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_NPUS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERI_BUS_USER, cmucal_mux_clkcmu_peri_bus_user_parents, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERI_USI00_USI_USER, cmucal_mux_clkcmu_peri_usi00_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERI_USI00_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_USI00_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_USI00_USI_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERI_USI01_USI_USER, cmucal_mux_clkcmu_peri_usi01_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERI_USI01_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_USI01_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_USI01_USI_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERI_USI02_USI_USER, cmucal_mux_clkcmu_peri_usi02_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERI_USI02_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_USI02_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_USI02_USI_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERI_USI03_USI_USER, cmucal_mux_clkcmu_peri_usi03_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERI_USI03_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_USI03_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_USI03_USI_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERI_USI04_USI_USER, cmucal_mux_clkcmu_peri_usi04_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERI_USI04_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_USI04_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_USI04_USI_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERI_USI05_USI_USER, cmucal_mux_clkcmu_peri_usi05_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERI_USI05_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_USI05_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_USI05_USI_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERI_USI_I2C_USER, cmucal_mux_clkcmu_peri_usi_i2c_user_parents, PLL_CON0_MUX_CLKCMU_PERI_USI_I2C_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_USI_I2C_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_USI_I2C_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERI_UART_DBG, cmucal_mux_clkcmu_peri_uart_dbg_parents, PLL_CON0_MUX_CLKCMU_PERI_UART_DBG_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_UART_DBG_BUSY, PLL_CON1_MUX_CLKCMU_PERI_UART_DBG_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERI_MMC_CARD_USER, cmucal_mux_clkcmu_peri_mmc_card_user_parents, PLL_CON0_MUX_CLKCMU_PERI_MMC_CARD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_MMC_CARD_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_PERI_USI06_USI_USER, cmucal_mux_clkcmu_peri_usi06_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERI_USI06_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERI_USI06_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERI_USI06_USI_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(CLKCMU_MIF_DDRPHY2X_S2D, cmucal_clkcmu_mif_ddrphy2x_s2d_parents, PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_MUX_SEL, PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_BUSY, PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_TAA_BUS_USER, cmucal_mux_clkcmu_taa_bus_user_parents, PLL_CON0_MUX_CLKCMU_TAA_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_TAA_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_TAA_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_TNR_BUS_USER, cmucal_mux_clkcmu_tnr_bus_user_parents, PLL_CON0_MUX_CLKCMU_TNR_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_TNR_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_TNR_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_USB_BUS_USER, cmucal_mux_clkcmu_usb_bus_user_parents, PLL_CON0_MUX_CLKCMU_USB_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_USB_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_USB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_USB_USB20DRD_USER, cmucal_mux_clkcmu_usb_usb20drd_user_parents, PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_USB_USB20DRD_USER_BUSY, PLL_CON1_MUX_CLKCMU_USB_USB20DRD_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKAUD_USB_BUS_USER, cmucal_mux_clkaud_usb_bus_user_parents, PLL_CON0_MUX_CLKAUD_USB_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKAUD_USB_BUS_USER_BUSY, PLL_CON1_MUX_CLKAUD_USB_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKAUD_USB_USB20DRD_USER, cmucal_mux_clkaud_usb_usb20drd_user_parents, PLL_CON0_MUX_CLKAUD_USB_USB20DRD_USER_MUX_SEL, PLL_CON0_MUX_CLKAUD_USB_USB20DRD_USER_BUSY, PLL_CON1_MUX_CLKAUD_USB_USB20DRD_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_VTS_BUS_USER, cmucal_mux_clkcmu_vts_bus_user_parents, PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_VTS_BUS_USER_BUSY, PLL_CON1_MUX_CLKCMU_VTS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLKCMU_VTS_RCO_USER, cmucal_mux_clkcmu_vts_rco_user_parents, PLL_CON0_MUX_CLKCMU_VTS_RCO_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_VTS_RCO_USER_BUSY, PLL_CON1_MUX_CLKCMU_VTS_RCO_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_CLK_AUD_DMIC_BUS_USER, cmucal_mux_clk_aud_dmic_bus_user_parents, PLL_CON0_MUX_CLK_AUD_DMIC_BUS_USER_MUX_SEL, PLL_CON0_MUX_CLK_AUD_DMIC_BUS_USER_BUSY, PLL_CON1_MUX_CLK_AUD_DMIC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_MUX(MUX_HCHGEN_CLK_AUD_CPU, cmucal_mux_hchgen_clk_aud_cpu_parents, EMPTY_CAL_ID, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_BUSY, CLK_CON_MUX_MUX_HCHGEN_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
};

unsigned int cmucal_div_size = 131;
struct cmucal_div cmucal_div_list[] = {
	CLK_DIV(CLKCMU_CMGP_PERI, GATE_CLKCMU_CMGP_PERI, CLK_CON_DIV_CLKCMU_CMGP_PERI_DIVRATIO, CLK_CON_DIV_CLKCMU_CMGP_PERI_BUSY, CLK_CON_DIV_CLKCMU_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ALIVE_BUS, MUX_CLK_ALIVE_BUS, CLK_CON_DIV_DIV_CLK_ALIVE_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_ALIVE_BUS_BUSY, CLK_CON_DIV_DIV_CLK_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CMGP_BUS, GATE_CLKCMU_CMGP_BUS, CLK_CON_DIV_CLKCMU_CMGP_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CMGP_BUS_BUSY, CLK_CON_DIV_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ALIVE_I3C_PMIC, MUX_CLK_ALIVE_BUS, CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_DIVRATIO, CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_BUSY, CLK_CON_DIV_DIV_CLK_ALIVE_I3C_PMIC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ALIVE_DBGCORE_UART, MUX_CLK_ALIVE_DBGCORE_UART, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_DIVRATIO, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_BUSY, CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CHUBVTS_BUS, GATE_CLKCMU_CHUB_BUS, CLK_CON_DIV_CLKCMU_CHUBVTS_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CHUBVTS_BUS_BUSY, CLK_CON_DIV_CLKCMU_CHUBVTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CHUB_PERI, GATE_CLKCMU_CHUB_PERI, CLK_CON_DIV_CLKCMU_CHUB_PERI_DIVRATIO, CLK_CON_DIV_CLKCMU_CHUB_PERI_BUSY, CLK_CON_DIV_CLKCMU_CHUB_PERI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ALIVE_USI0, MUX_CLK_ALIVE_USI0, CLK_CON_DIV_DIV_CLK_ALIVE_USI0_DIVRATIO, CLK_CON_DIV_DIV_CLK_ALIVE_USI0_BUSY, CLK_CON_DIV_DIV_CLK_ALIVE_USI0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ALIVE_I2C, MUX_CLK_ALIVE_I2C, CLK_CON_DIV_DIV_CLK_ALIVE_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_ALIVE_I2C_BUSY, CLK_CON_DIV_DIV_CLK_ALIVE_I2C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_CPU_PCLKDBG, DIV_CLK_AUD_CPU, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_FM_SPDY, TICK_USB, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_BUSY, CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_UAIF0, MUX_CLK_AUD_UAIF0, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_UAIF1, MUX_CLK_AUD_UAIF1, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_UAIF2, MUX_CLK_AUD_UAIF2, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_UAIF3, MUX_CLK_AUD_UAIF3, CLK_CON_DIV_DIV_CLK_AUD_UAIF3_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF3_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_CPU_ACLK, DIV_CLK_AUD_CPU, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_BUSP, DIV_CLK_AUD_BUSD, CLK_CON_DIV_DIV_CLK_AUD_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_AUD_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_CNT, PLL_AUD_D2, CLK_CON_DIV_DIV_CLK_AUD_CNT_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CNT_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CNT_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_UAIF4, MUX_CLK_AUD_UAIF4, CLK_CON_DIV_DIV_CLK_AUD_UAIF4_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF4_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF4_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_DSIF, MUX_CLK_AUD_DSIF, CLK_CON_DIV_DIV_CLK_AUD_DSIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_DSIF_BUSY, CLK_CON_DIV_DIV_CLK_AUD_DSIF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_FM, MUX_CLK_AUD_FM, CLK_CON_DIV_DIV_CLK_AUD_FM_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_FM_BUSY, CLK_CON_DIV_DIV_CLK_AUD_FM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_UAIF5, MUX_CLK_AUD_UAIF5, CLK_CON_DIV_DIV_CLK_AUD_UAIF5_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF5_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF5_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_UAIF6, MUX_CLK_AUD_UAIF6, CLK_CON_DIV_DIV_CLK_AUD_UAIF6_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_UAIF6_BUSY, CLK_CON_DIV_DIV_CLK_AUD_UAIF6_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_MCLK, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_MCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_MCLK_BUSY, CLK_CON_DIV_DIV_CLK_AUD_MCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_AUDIF, PLL_AUD_D3, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_BUSY, CLK_CON_DIV_DIV_CLK_AUD_AUDIF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_BUSD, MUX_CLK_AUD_BUS, CLK_CON_DIV_DIV_CLK_AUD_BUSD_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_BUSD_BUSY, CLK_CON_DIV_DIV_CLK_AUD_BUSD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_PCMC, DIV_CLK_AUD_AUDIF, CLK_CON_DIV_DIV_CLK_AUD_PCMC_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_PCMC_BUSY, CLK_CON_DIV_DIV_CLK_AUD_PCMC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKAUD_USB_BUS, GATE_CLKAUD_USB_BUS, CLK_CON_DIV_CLKAUD_USB_BUS_DIVRATIO, CLK_CON_DIV_CLKAUD_USB_BUS_BUSY, CLK_CON_DIV_CLKAUD_USB_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKAUD_USB_USB20DRD, GATE_CLKAUD_USB_USB20DRD, CLK_CON_DIV_CLKAUD_USB_USB20DRD_DIVRATIO, CLK_CON_DIV_CLKAUD_USB_USB20DRD_BUSY, CLK_CON_DIV_CLKAUD_USB_USB20DRD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_CPU, MUX_HCHGEN_CLK_AUD_CPU, CLK_CON_DIV_DIV_CLK_AUD_CPU_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_AUD_CPU_ACP, DIV_CLK_AUD_CPU, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_BUSY, CLK_CON_DIV_DIV_CLK_AUD_CPU_ACP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLK_AUD_DMIC, PLL_AUD_D2, CLK_CON_DIV_CLK_AUD_DMIC_DIVRATIO, CLK_CON_DIV_CLK_AUD_DMIC_BUSY, CLK_CON_DIV_CLK_AUD_DMIC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_BUSC_BUSP, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_DIV_DIV_CLK_BUSC_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_BUSC_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_BUSC_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CHUB_USI0, MUX_CLK_CHUB_USI0, CLK_CON_DIV_DIV_CLK_CHUB_USI0_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_USI0_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_USI0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CHUB_USI1, MUX_CLK_CHUB_USI1, CLK_CON_DIV_DIV_CLK_CHUB_USI1_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_USI1_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_USI1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CHUB_USI2, MUX_CLK_CHUB_USI2, CLK_CON_DIV_DIV_CLK_CHUB_USI2_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_USI2_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_USI2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CHUB_I2C, MUX_CLK_CHUB_I2C, CLK_CON_DIV_DIV_CLK_CHUB_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_I2C_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_I2C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CHUB_USI3, MUX_CLK_CHUB_USI3, CLK_CON_DIV_DIV_CLK_CHUB_USI3_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_USI3_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_USI3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CHUB_BUS, MUX_CLK_CHUB_BUS, CLK_CON_DIV_DIV_CLK_CHUB_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUB_BUS_BUSY, CLK_CON_DIV_DIV_CLK_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CHUBVTS_BUS, MUX_CLK_CHUBVTS_BUS, CLK_CON_DIV_DIV_CLK_CHUBVTS_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_CHUBVTS_BUS_BUSY, CLK_CON_DIV_DIV_CLK_CHUBVTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CMGP_I2C, MUX_CLK_CMGP_I2C, CLK_CON_DIV_DIV_CLK_CMGP_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_I2C_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_I2C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CMGP_USI0, MUX_CLK_CMGP_USI0, CLK_CON_DIV_DIV_CLK_CMGP_USI0_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI0_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CMGP_USI4, MUX_CLK_CMGP_USI4, CLK_CON_DIV_DIV_CLK_CMGP_USI4_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI4_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI4_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CMGP_I3C, MUX_CLK_CMGP_I3C, CLK_CON_DIV_DIV_CLK_CMGP_I3C_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_I3C_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_I3C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CMGP_USI1, MUX_CLK_CMGP_USI1, CLK_CON_DIV_DIV_CLK_CMGP_USI1_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI1_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CMGP_USI2, MUX_CLK_CMGP_USI2, CLK_CON_DIV_DIV_CLK_CMGP_USI2_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI2_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CMGP_USI3, MUX_CLK_CMGP_USI3, CLK_CON_DIV_DIV_CLK_CMGP_USI3_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMGP_USI3_BUSY, CLK_CON_DIV_DIV_CLK_CMGP_USI3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_ALIVE_BUS, GATE_CLKCMU_ALIVE_BUS, CLK_CON_DIV_CLKCMU_ALIVE_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_ALIVE_BUS_BUSY, CLK_CON_DIV_CLKCMU_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_G3D_SWITCH, GATE_CLKCMU_G3D_SWITCH, CLK_CON_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERI_BUS, GATE_CLKCMU_PERI_BUS, CLK_CON_DIV_CLKCMU_PERI_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_BUS_BUSY, CLK_CON_DIV_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_DPU_BUS, GATE_CLKCMU_DPU_BUS, CLK_CON_DIV_CLKCMU_DPU_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_DPU_BUS_BUSY, CLK_CON_DIV_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_MFC_MFC, GATE_CLKCMU_MFC_MFC, CLK_CON_DIV_CLKCMU_MFC_MFC_DIVRATIO, CLK_CON_DIV_CLKCMU_MFC_MFC_BUSY, CLK_CON_DIV_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CORE_BUS, GATE_CLKCMU_CORE_BUS, CLK_CON_DIV_CLKCMU_CORE_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CORE_BUS_BUSY, CLK_CON_DIV_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CPUCL0_SWITCH, GATE_CLKCMU_CPUCL0_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_TAA_BUS, GATE_CLKCMU_TAA_BUS, CLK_CON_DIV_CLKCMU_TAA_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_TAA_BUS_BUSY, CLK_CON_DIV_CLKCMU_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_ISP_BUS, GATE_CLKCMU_ISP_BUS, CLK_CON_DIV_CLKCMU_ISP_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_ISP_BUS_BUSY, CLK_CON_DIV_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_AUD_CPU, GATE_CLKCMU_AUD_CPU, CLK_CON_DIV_CLKCMU_AUD_CPU_DIVRATIO, CLK_CON_DIV_CLKCMU_AUD_CPU_BUSY, CLK_CON_DIV_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_M2M_MSCL, GATE_CLKCMU_M2M_MSCL, CLK_CON_DIV_CLKCMU_M2M_MSCL_DIVRATIO, CLK_CON_DIV_CLKCMU_M2M_MSCL_BUSY, CLK_CON_DIV_CLKCMU_M2M_MSCL_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CPUCL0_DBG_BUS, GATE_CLKCMU_CPUCL0_DBG_BUS, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CIS_CLK0, GATE_CLKCMU_CIS_CLK0, CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CIS_CLK1, GATE_CLKCMU_CIS_CLK1, CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CIS_CLK2, GATE_CLKCMU_CIS_CLK2, CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_HSI_UFS_EMBD, GATE_CLKCMU_HSI_UFS_EMBD, CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD_BUSY, CLK_CON_DIV_CLKCMU_HSI_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_NPU0_BUS, GATE_CLKCMU_NPU0_BUS, CLK_CON_DIV_CLKCMU_NPU0_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_NPU0_BUS_BUSY, CLK_CON_DIV_CLKCMU_NPU0_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_MIF_BUSP, GATE_CLKCMU_MIF_BUSP, CLK_CON_DIV_CLKCMU_MIF_BUSP_DIVRATIO, CLK_CON_DIV_CLKCMU_MIF_BUSP_BUSY, CLK_CON_DIV_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERI_IP, GATE_CLKCMU_PERI_IP, CLK_CON_DIV_CLKCMU_PERI_IP_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_IP_BUSY, CLK_CON_DIV_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CPUCL1_SWITCH, GATE_CLKCMU_CPUCL1_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_USB_BUS, GATE_CLKCMU_USB_BUS, CLK_CON_DIV_CLKCMU_USB_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_USB_BUS_BUSY, CLK_CON_DIV_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_TNR_BUS, GATE_CLKCMU_TNR_BUS, CLK_CON_DIV_CLKCMU_TNR_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_TNR_BUS_BUSY, CLK_CON_DIV_CLKCMU_TNR_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CMU_BOOST, MUX_CLKCMU_CMU_BOOST, CLK_CON_DIV_CLKCMU_CMU_BOOST_DIVRATIO, CLK_CON_DIV_CLKCMU_CMU_BOOST_BUSY, CLK_CON_DIV_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CORE_G3D, GATE_CLKCMU_CORE_G3D, CLK_CON_DIV_CLKCMU_CORE_G3D_DIVRATIO, CLK_CON_DIV_CLKCMU_CORE_G3D_BUSY, CLK_CON_DIV_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CSIS_BUS, GATE_CLKCMU_CSIS_BUS, CLK_CON_DIV_CLKCMU_CSIS_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_CSIS_BUS_BUSY, CLK_CON_DIV_CLKCMU_CSIS_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_MCSC_BUS, GATE_CLKCMU_MCSC_BUS, CLK_CON_DIV_CLKCMU_MCSC_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_MCSC_BUS_BUSY, CLK_CON_DIV_CLKCMU_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_HSI_BUS, GATE_CLKCMU_HSI_BUS, CLK_CON_DIV_CLKCMU_HSI_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI_BUS_BUSY, CLK_CON_DIV_CLKCMU_HSI_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_PERI_MMC_CARD, GATE_CLKCMU_PERI_MMC_CARD, CLK_CON_DIV_CLKCMU_PERI_MMC_CARD_DIVRATIO, CLK_CON_DIV_CLKCMU_PERI_MMC_CARD_BUSY, CLK_CON_DIV_CLKCMU_PERI_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_MCSC_GDC, GATE_CLKCMU_MCSC_GDC, CLK_CON_DIV_CLKCMU_MCSC_GDC_DIVRATIO, CLK_CON_DIV_CLKCMU_MCSC_GDC_BUSY, CLK_CON_DIV_CLKCMU_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_USB_USB20DRD, GATE_CLKCMU_USB_USB20DRD, CLK_CON_DIV_CLKCMU_USB_USB20DRD_DIVRATIO, CLK_CON_DIV_CLKCMU_USB_USB20DRD_BUSY, CLK_CON_DIV_CLKCMU_USB_USB20DRD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_NPUS_BUS, GATE_CLKCMU_NPUS_BUS, CLK_CON_DIV_CLKCMU_NPUS_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_NPUS_BUS_BUSY, CLK_CON_DIV_CLKCMU_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CORE_SSS, GATE_CLKCMU_CORE_SSS, CLK_CON_DIV_CLKCMU_CORE_SSS_DIVRATIO, CLK_CON_DIV_CLKCMU_CORE_SSS_BUSY, CLK_CON_DIV_CLKCMU_CORE_SSS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_BUSC_BUS, GATE_CLKCMU_BUSC_BUS, CLK_CON_DIV_CLKCMU_BUSC_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_BUSC_BUS_BUSY, CLK_CON_DIV_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CIS_CLK3, GATE_CLKCMU_CIS_CLK3, CLK_CON_DIV_CLKCMU_CIS_CLK3_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK3_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CIS_CLK4, GATE_CLKCMU_CIS_CLK4, CLK_CON_DIV_CLKCMU_CIS_CLK4_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK4_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CIS_CLK5, GATE_CLKCMU_CIS_CLK5, CLK_CON_DIV_CLKCMU_CIS_CLK5_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK5_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_DSU_SWITCH, GATE_CLKCMU_DSU_SWITCH, CLK_CON_DIV_CLKCMU_DSU_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_DSU_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_CPUCL0_BUSP, GATE_CLKCMU_CPUCL0_BUSP, CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_DPU_DSIM, GATE_CLKCMU_DPU_DSIM, CLK_CON_DIV_CLKCMU_DPU_DSIM_DIVRATIO, CLK_CON_DIV_CLKCMU_DPU_DSIM_BUSY, CLK_CON_DIV_CLKCMU_DPU_DSIM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_MCSC_MCSC, GATE_CLKCMU_MCSC_MCSC, CLK_CON_DIV_CLKCMU_MCSC_MCSC_DIVRATIO, CLK_CON_DIV_CLKCMU_MCSC_MCSC_BUSY, CLK_CON_DIV_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(CLKCMU_AUD_BUS, GATE_CLKCMU_AUD_BUS, CLK_CON_DIV_CLKCMU_AUD_BUS_DIVRATIO, CLK_CON_DIV_CLKCMU_AUD_BUS_BUSY, CLK_CON_DIV_CLKCMU_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CORE_BUSP, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_DIV_DIV_CLK_CORE_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CORE_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_CORE_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CPUCL0_SHORTSTOP, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_SHORTSTOP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CPUCL0_DBG_PCLKDBG, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CPUCL1_SHORTSTOP, DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_SHORTSTOP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CPUCL1_HTU, MUX_CLK_CPUCL1_PLL, CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_HTU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CSIS_BUSP, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_DIV_DIV_CLK_CSIS_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CSIS_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_CSIS_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_DPU_BUSP, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_DIV_DIV_CLK_DPU_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DPU_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_DPU_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_DSU_SHORTSTOP, DIV_CLK_DSU_CLUSTER, CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_BUSY, CLK_CON_DIV_DIV_CLK_DSU_SHORTSTOP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CLUSTER0_ACLK, DIV_CLK_DSU_CLUSTER, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CLUSTER0_ATCLK, DIV_CLK_DSU_CLUSTER, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CLUSTER0_PCLK, DIV_CLK_DSU_CLUSTER, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CLUSTER0_PERIPHCLK, DIV_CLK_DSU_CLUSTER, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_G3D_BUSP, MUX_CLKCMU_G3D_BUS_USER, CLK_CON_DIV_DIV_CLK_G3D_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_G3D_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_G3D_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_ISP_BUSP, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_DIV_DIV_CLK_ISP_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_ISP_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_ISP_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_M2M_BUSP, MUX_CLKCMU_M2M_MSCL_USER, CLK_CON_DIV_DIV_CLK_M2M_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_M2M_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_M2M_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_MCSC_BUSP, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_DIV_DIV_CLK_MCSC_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MCSC_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MCSC_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_MFC_BUSP, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_DIV_DIV_CLK_MFC_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MFC_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_MFC_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_NPU0_BUSP, DIV_CLK_NPU0_BUS, CLK_CON_DIV_DIV_CLK_NPU0_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_NPU0_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_NPU0_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_NPUS_BUSP, DIV_CLK_NPUS_BUS, CLK_CON_DIV_DIV_CLK_NPUS_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_NPUS_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_NPUS_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_PERI_USI00_USI, MUX_CLKCMU_PERI_USI00_USI_USER, CLK_CON_DIV_DIV_CLK_PERI_USI00_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI00_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI00_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_PERI_USI01_USI, MUX_CLKCMU_PERI_USI01_USI_USER, CLK_CON_DIV_DIV_CLK_PERI_USI01_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI01_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI01_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_PERI_USI02_USI, MUX_CLKCMU_PERI_USI02_USI_USER, CLK_CON_DIV_DIV_CLK_PERI_USI02_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI02_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI02_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_PERI_USI03_USI, MUX_CLKCMU_PERI_USI03_USI_USER, CLK_CON_DIV_DIV_CLK_PERI_USI03_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI03_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI03_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_PERI_USI04_USI, MUX_CLKCMU_PERI_USI04_USI_USER, CLK_CON_DIV_DIV_CLK_PERI_USI04_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI04_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI04_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_PERI_USI05_USI, MUX_CLKCMU_PERI_USI05_USI_USER, CLK_CON_DIV_DIV_CLK_PERI_USI05_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI05_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI05_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_PERI_USI_I2C, MUX_CLKCMU_PERI_USI_I2C_USER, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI_I2C_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_PERI_UART_DBG, MUX_CLKCMU_PERI_UART_DBG, CLK_CON_DIV_DIV_CLK_PERI_UART_DBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_UART_DBG_BUSY, CLK_CON_DIV_DIV_CLK_PERI_UART_DBG_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_PERI_USI06_USI, MUX_CLKCMU_PERI_USI06_USI_USER, CLK_CON_DIV_DIV_CLK_PERI_USI06_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERI_USI06_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERI_USI06_USI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_TAA_BUSP, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_DIV_DIV_CLK_TAA_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_TAA_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_TAA_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_TNR_BUSP, MUX_CLKCMU_TNR_BUS_USER, CLK_CON_DIV_DIV_CLK_TNR_BUSP_DIVRATIO, CLK_CON_DIV_DIV_CLK_TNR_BUSP_BUSY, CLK_CON_DIV_DIV_CLK_TNR_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_VTS_DMIC_IF, MUX_CLK_VTS_DMIC_IF, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_VTS_DMIC_IF_DIV2, DIV_CLK_VTS_DMIC_IF, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_BUSY, CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_VTS_BUS, MUX_CLK_VTS_BUS, CLK_CON_DIV_DIV_CLK_VTS_BUS_DIVRATIO, CLK_CON_DIV_DIV_CLK_VTS_BUS_BUSY, CLK_CON_DIV_DIV_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_VTS_DMIC_AUD, MUX_VTS_DMIC_AUD, CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIVRATIO, CLK_CON_DIV_DIV_VTS_DMIC_AUD_BUSY, CLK_CON_DIV_DIV_VTS_DMIC_AUD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_VTS_DMIC_AUD_DIV2, DIV_VTS_DMIC_AUD, CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIV2_DIVRATIO, CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIV2_BUSY, CLK_CON_DIV_DIV_VTS_DMIC_AUD_DIV2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_VTS_SERIAL_LIF_CORE, MUX_CLK_VTS_BUS, CLK_CON_DIV_DIV_VTS_SERIAL_LIF_CORE_DIVRATIO, CLK_CON_DIV_DIV_VTS_SERIAL_LIF_CORE_BUSY, CLK_CON_DIV_DIV_VTS_SERIAL_LIF_CORE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_VTS_SERIAL_LIF, MUX_VTS_SERIAL_LIF, CLK_CON_DIV_DIV_VTS_SERIAL_LIF_DIVRATIO, CLK_CON_DIV_DIV_VTS_SERIAL_LIF_BUSY, CLK_CON_DIV_DIV_VTS_SERIAL_LIF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CPUCL0_CPU, MUX_CLK_CPUCL0_PLL, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_CPUCL1_CPU, MUX_CLK_CPUCL1_PLL, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_DSU_CLUSTER, MUX_CLK_DSU_PLL, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_BUSY, CLK_CON_DIV_DIV_CLK_DSU_CLUSTER_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_G3D_BUSD, MUX_CLKCMU_G3D_BUS_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_G3D_BUSD_BUSY, CLK_CON_DIV_DIV_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_NPU0_BUS, MUX_CLKCMU_NPU0_BUS_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_NPU0_BUS_BUSY, CLK_CON_DIV_DIV_CLK_NPU0_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_DIV(DIV_CLK_NPUS_BUS, MUX_CLKCMU_NPUS_BUS_USER, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_NPUS_BUS_BUSY, CLK_CON_DIV_DIV_CLK_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING),

};

unsigned int cmucal_gate_size = 1006;
struct cmucal_gate cmucal_gate_list[] = {
	CLK_GATE(GOUT_BLK_ALIVE_UID_SLH_AXI_SI_D_APM_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_D_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_D_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK, OSCCLK_RCO_ALIVE, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CMGP_PERI, MUX_CLKCMU_CMGP_PERI, CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CMGP_PERI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_INTMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_D_TZPC_ALIVE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_D_TZPC_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_D_TZPC_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_D_TZPC_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_G_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_SLH_AXI_SI_C_CMGP_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_C_CMGP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_C_CMGP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_C_CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CMGP_BUS, MUX_CLKCMU_CMGP_BUS, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CMGP_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_GNSS_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_MODEM_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_CHUBVTS_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_WLBT_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_WLBT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_WLBT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_MI_C_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_CHUB_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_ABOX_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_ABOX_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_ABOX_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_WLBT_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_WL_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_WL_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_WL_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_WL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_APM_WLBT_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_WLBT_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_WL_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_WL_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_WL_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_WL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_VTS_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_SCLK, MUX_CLK_ALIVE_I3C_PMIC, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I3C_APM_PMIC_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK, MUX_CLK_ALIVE_I3C_PMIC, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I3C_PMIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK, DIV_CLK_ALIVE_DBGCORE_UART, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_SYSREG_VGPIO2PMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK, DIV_CLK_ALIVE_DBGCORE_UART, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_APBIF_CHUB_RTC_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_CHUB_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_CHUB_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_APBIF_CHUB_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLKCMU_VTS_RCO, MUX_CLK_RCO_ALIVE_USER, CLK_CON_GAT_CLKCMU_VTS_RCO_CG_VAL, CLK_CON_GAT_CLKCMU_VTS_RCO_MANUAL, CLK_CON_GAT_CLKCMU_VTS_RCO_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CHUB_BUS, MUX_CLKCMU_CHUBVTS_BUS, CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(AP2GNSS_CLK, MUX_CLKCMU_AP2GNSS, CLK_CON_GAT_AP2GNSS_CLK_CG_VAL, CLK_CON_GAT_AP2GNSS_CLK_MANUAL, CLK_CON_GAT_AP2GNSS_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_BT_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_BT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_BT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_AP_WLBT_BT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_BT_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_BT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_BT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_CP_WLBT_BT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CHUB_PERI, MUX_CLKCMU_CHUB_PERI, CLK_CON_GAT_GATE_CLKCMU_CHUB_PERI_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CHUB_PERI_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CHUB_PERI_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_IPCLK, DIV_CLK_ALIVE_I2C, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_I2C_ALIVE0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_IPCLK, DIV_CLK_ALIVE_USI0, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_USI_ALIVE0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I2C_IPCLKPORT_CLK, DIV_CLK_ALIVE_I2C, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_USI0_IPCLKPORT_CLK, DIV_CLK_ALIVE_USI0, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_USI0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_USI0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_USI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLKCMU_CHUB_RCO, MUX_CLK_RCO_ALIVE_USER, CLK_CON_GAT_CLKCMU_CHUB_RCO_CG_VAL, CLK_CON_GAT_CLKCMU_CHUB_RCO_MANUAL, CLK_CON_GAT_CLKCMU_CHUB_RCO_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLKCMU_CMGP_RCO, MUX_CLK_RCO_ALIVE_USER, CLK_CON_GAT_CLKCMU_CMGP_RCO_CG_VAL, CLK_CON_GAT_CLKCMU_CMGP_RCO_MANUAL, CLK_CON_GAT_CLKCMU_CMGP_RCO_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK, DIV_CLK_ALIVE_BUS, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLKCMU_CHUBVTS_RCO, MUX_CLK_RCO_ALIVE_USER, CLK_CON_GAT_CLKCMU_CHUBVTS_RCO_CG_VAL, CLK_CON_GAT_CLKCMU_CHUBVTS_RCO_MANUAL, CLK_CON_GAT_CLKCMU_CHUBVTS_RCO_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_BUSD_IPCLKPORT_CLK, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK, DIV_CLK_AUD_BUSD, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_LH_AXI_SI_D_AUD_IPCLKPORT_I_CLK, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_LH_AXI_SI_D_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_LH_AXI_SI_D_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_LH_AXI_SI_D_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0, DIV_CLK_AUD_UAIF0, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1, DIV_CLK_AUD_UAIF1, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3, DIV_CLK_AUD_UAIF3, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_AUD_CPU_PCLKDBG, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK, OSCCLK_AUD, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF0, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF1, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF2, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF3, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK, DIV_CLK_AUD_CPU_ACLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2, DIV_CLK_AUD_UAIF2, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK, DIV_CLK_AUD_BUSP, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK, DIV_CLK_AUD_BUSP, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S1, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK, DIV_CLK_AUD_CPU, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_NS_IPCLKPORT_PCLKM, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_NS_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_NS_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S_IPCLKPORT_PCLKM, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP, DIV_CLK_AUD_CPU_PCLKDBG, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT, DIV_CLK_AUD_CNT, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK, DIV_CLK_AUD_CNT, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_CNT_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4, DIV_CLK_AUD_UAIF4, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF4_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S2_IPCLKPORT_PCLKM, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S2_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S2_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_SYSMMU_AUD_S2_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF4, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB, DIV_CLK_AUD_CPU_ACLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32, DIV_CLK_AUD_CPU, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S2, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSMMU_AUD_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK, DIV_CLK_AUD_CPU, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU0_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK, DIV_CLK_AUD_CPU, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU1_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK, DIV_CLK_AUD_DSIF, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF, DIV_CLK_AUD_DSIF, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_SPDY_IPCLKPORT_CLK, DIV_CLK_AUD_FM, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_SPDY_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_SPDY_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_SPDY_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5, DIV_CLK_AUD_UAIF5, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF5_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6, DIV_CLK_AUD_UAIF6, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF6_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF5, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF5_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK, DIV_CLK_AUD_UAIF6, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_UAIF6_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK, DIV_CLK_AUD_MCLK, CLK_CON_GAT_GOUT_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_MAILBOX_AUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK, DIV_CLK_AUD_BUSP, CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_D_TZPC_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_SLH_AXI_MI_D_USBAUD_IPCLKPORT_I_CLK, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_D_USBAUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_D_USBAUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SLH_AXI_MI_D_USBAUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK, MUX_CLK_AUD_PCMC, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_PCMC_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK, MUX_CLK_AUD_PCMC, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_PCMC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A0_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_C2A1_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_IPCLKPORT_CLK, MUX_CLK_AUD_FM, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_FM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_DBG_IPCLKPORT_CLK, DIV_CLK_AUD_CPU, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_DBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_DBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKAUD_USB_BUS, PLL_AUD_D3, CLK_CON_GAT_GATE_CLKAUD_USB_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKAUD_USB_BUS_MANUAL, CLK_CON_GAT_GATE_CLKAUD_USB_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKAUD_USB_USB20DRD, PLL_AUD_D3, CLK_CON_GAT_GATE_CLKAUD_USB_USB20DRD_CG_VAL, CLK_CON_GAT_GATE_CLKAUD_USB_USB20DRD_MANUAL, CLK_CON_GAT_GATE_CLKAUD_USB_USB20DRD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_0, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_0_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_0_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_1, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_1_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_1_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_2, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_2_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_2_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_XCLK_2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_AD_APB_VGENLITE_AUD_IPCLKPORT_PCLKM, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_VGENLITE_AUD_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_VGENLITE_AUD_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_AD_APB_VGENLITE_AUD_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK, DIV_CLK_AUD_CPU_ACP, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP, DIV_CLK_AUD_CPU_ACP, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ACP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_OSC_SPDY, MUX_CLK_AUD_FM, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_OSC_SPDY_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_OSC_SPDY_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_OSC_SPDY_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_SPDY, DIV_CLK_AUD_FM, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_SPDY_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK, DIV_CLK_AUD_BUSD, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_OSCCLK_IPCLKPORT_CLK, OSCCLK_AUD, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AUD_UID_RSTNSYNC_SR_CLK_AUD_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKM, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKS, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_XIU_P_BUSC_IPCLKPORT_ACLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_P_BUSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_P_BUSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_P_BUSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_XIU_D_BUSC_IPCLKPORT_ACLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_D_BUSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_D_BUSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_XIU_D_BUSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_PERI_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_PERI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_PERI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_USB_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LH_AXI_MI_D_MFC_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_APM_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_PDMA_BUSC_IPCLKPORT_ACLK_PDMA0, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA_BUSC_IPCLKPORT_ACLK_PDMA0_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA_BUSC_IPCLKPORT_ACLK_PDMA0_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA_BUSC_IPCLKPORT_ACLK_PDMA0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_SPDMA_BUSC_IPCLKPORT_ACLK_PDMA1, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_BUSC_IPCLKPORT_ACLK_PDMA1_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_BUSC_IPCLKPORT_ACLK_PDMA1_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_BUSC_IPCLKPORT_ACLK_PDMA1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_SYSMMU_AXI_D_BUSC_IPCLKPORT_CLK_S2, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSMMU_AXI_D_BUSC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSMMU_AXI_D_BUSC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSMMU_AXI_D_BUSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_VGEN_PDMA_IPCLKPORT_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_PDMA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_PDMA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_PDMA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_OSCCLK_IPCLKPORT_CLK, OSCCLK_BUSC, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_SLH_AXI_MI_P_BUSC_IPCLKPORT_I_CLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_P_BUSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_P_BUSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SLH_AXI_MI_P_BUSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_D_TZPC_BUSC_IPCLKPORT_PCLK, DIV_CLK_BUSC_BUSP, CLK_CON_GAT_GOUT_BLK_BUSC_UID_D_TZPC_BUSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_D_TZPC_BUSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_D_TZPC_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_LH_AXI_MI_D_CHUBVTS_IPCLKPORT_I_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LH_AXI_MI_D_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_VGEN_SPDMA_IPCLKPORT_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_SPDMA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_SPDMA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_VGEN_SPDMA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_BUSC_UID_RSTNSYNC_SR_CLK_BUSC_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_BUSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_SR_CLK_BUSC_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_SR_CLK_BUSC_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_SR_CLK_BUSC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_CHUB_COMBINE_WAKEUP_SRC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_CM4_CHUB_IPCLKPORT_FCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_PWM_CHUB_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_TIMER_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_WDT_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK, RTCCLK_CHUB, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_RTCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK, OSCCLK_RCO_CHUB, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK, MUX_CLK_CHUB_TIMER, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_TIMER_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_IPCLK, DIV_CLK_CHUB_I2C, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK, DIV_CLK_CHUB_USI0, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK, DIV_CLK_CHUB_USI1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK, DIV_CLK_CHUB_USI2, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK, DIV_CLK_CHUB_I2C, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK, DIV_CLK_CHUB_USI0, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI1_IPCLKPORT_CLK, DIV_CLK_CHUB_USI1, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI2_IPCLKPORT_CLK, DIV_CLK_CHUB_USI2, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2WLBT_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SYSREG_COMBINE_CHUB2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUBEINT_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUBEINT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUBEINT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_APBIF_GPIO_CHUBEINT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_IPCLK, DIV_CLK_CHUB_I2C, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_I2C_CHUB3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK, DIV_CLK_CHUB_USI3, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_USI_CHUB3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI3_IPCLKPORT_CLK, DIV_CLK_CHUB_USI3, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_RSTNSYNC_CLK_CHUB_USI3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_AHB_BUSMATRIX_CHUB_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_SLH_AXI_SI_M_CHUB_IPCLKPORT_I_CLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_SI_M_CHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_SI_M_CHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_SI_M_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUB_UID_SLH_AXI_MI_S_CHUB_IPCLKPORT_I_CLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_MI_S_CHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_MI_S_CHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUB_UID_SLH_AXI_MI_S_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK, DIV_CLK_CHUB_BUS, CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUB_UID_CHUB_CMU_CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK, DIV_CLK_CHUBVTS_BUS, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CHUBVTS_UID_CHUBVTS_CMU_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUBVTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK, DIV_CLK_CHUBVTS_BUS, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK, DIV_CLK_CHUBVTS_BUS, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_D_TZPC_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUBVTS_UID_LH_AXI_SI_D_CHUBVTS_IPCLKPORT_I_CLK, DIV_CLK_CHUBVTS_BUS, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_LH_AXI_SI_D_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_LH_AXI_SI_D_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_LH_AXI_SI_D_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_CHUB_IPCLKPORT_I_CLK, DIV_CLK_CHUBVTS_BUS, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_CHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_CHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK, DIV_CLK_CHUBVTS_BUS, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_LP_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_VTS_IPCLKPORT_I_CLK, DIV_CLK_CHUBVTS_BUS, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_MI_M_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_C_CHUBVTS_IPCLKPORT_I_CLK, DIV_CLK_CHUBVTS_BUS, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_C_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_C_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_C_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_CHUB_IPCLKPORT_I_CLK, DIV_CLK_CHUBVTS_BUS, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_CHUB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_CHUB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_CHUB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_VTS_IPCLKPORT_I_CLK, DIV_CLK_CHUBVTS_BUS, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SLH_AXI_SI_S_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUBVTS_UID_SWEEPER_C_CHUBVTS_IPCLKPORT_ACLK, DIV_CLK_CHUBVTS_BUS, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SWEEPER_C_CHUBVTS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SWEEPER_C_CHUBVTS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SWEEPER_C_CHUBVTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK, DIV_CLK_CHUBVTS_BUS, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_SYSREG_CHUBVTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK, DIV_CLK_CHUBVTS_BUS, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_VGEN_LITE_CHUBVTS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK, DIV_CLK_CHUBVTS_BUS, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_XIU_DP_CHUBVTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUBVTS_UID_BPS_LP_CHUBVTS_IPCLKPORT_I_CLK, DIV_CLK_CHUBVTS_BUS, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BPS_LP_CHUBVTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BPS_LP_CHUBVTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BPS_LP_CHUBVTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK, DIV_CLK_CHUBVTS_BUS, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_BAAW_CHUB_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_BUS_IPCLKPORT_CLK, DIV_CLK_CHUBVTS_BUS, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CHUBVTS_UID_RSTNSYNC_CLK_CHUBVTS_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK, DIV_CLK_CMGP_USI0, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI0, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_SLH_AXI_MI_C_CMGP_IPCLKPORT_I_CLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SLH_AXI_MI_C_CMGP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SLH_AXI_MI_C_CMGP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SLH_AXI_MI_C_CMGP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK, OSCCLK_RCO_CMGP, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK, DIV_CLK_CMGP_I3C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I3C_CMGP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK, DIV_CLK_CMGP_I3C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I3C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2WLBT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI4, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI4_IPCLKPORT_CLK, DIV_CLK_CMGP_USI4, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI4_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI4_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK, DIV_CLK_CMGP_I2C, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI2, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK, DIV_CLK_CMGP_USI3, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK, MUX_CLK_CMGP_BUS, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK, DIV_CLK_CMGP_USI1, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK, DIV_CLK_CMGP_USI2, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK, DIV_CLK_CMGP_USI3, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_ALIVE_BUS, MUX_CLKCMU_ALIVE_BUS, CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ALIVE_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLKCMU_MIF_SWITCH, MUX_CLKCMU_MIF_SWITCH, CLK_CON_GAT_CLKCMU_MIF_SWITCH_CG_VAL, CLK_CON_GAT_CLKCMU_MIF_SWITCH_MANUAL, CLK_CON_GAT_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_MFC_MFC, MUX_CLKCMU_MFC_MFC, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_HSI_BUS, MUX_CLKCMU_HSI_BUS, CLK_CON_GAT_GATE_CLKCMU_HSI_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERI_MMC_CARD, MUX_CLKCMU_PERI_MMC_CARD, CLK_CON_GAT_GATE_CLKCMU_PERI_MMC_CARD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_MMC_CARD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_DPU_BUS, MUX_CLKCMU_DPU_BUS, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_G3D_SWITCH, MUX_CLKCMU_G3D_SWITCH, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERI_BUS, MUX_CLKCMU_PERI_BUS, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CORE_BUS, MUX_CLKCMU_CORE_BUS, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CPUCL0_SWITCH, MUX_CLKCMU_CPUCL0_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_TAA_BUS, MUX_CLKCMU_TAA_BUS, CLK_CON_GAT_GATE_CLKCMU_TAA_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_TAA_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_TAA_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_ISP_BUS, MUX_CLKCMU_ISP_BUS, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ISP_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_AUD_CPU, MUX_CLKCMU_AUD_CPU, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_MANUAL, CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_M2M_MSCL, MUX_CLKCMU_M2M_MSCL, CLK_CON_GAT_GATE_CLKCMU_M2M_MSCL_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_M2M_MSCL_MANUAL, CLK_CON_GAT_GATE_CLKCMU_M2M_MSCL_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CPUCL0_DBG_BUS, MUX_CLKCMU_CPUCL0_DBG_BUS, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CIS_CLK0, MUX_CLKCMU_CIS_CLK0, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CIS_CLK1, MUX_CLKCMU_CIS_CLK1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CIS_CLK2, MUX_CLKCMU_CIS_CLK2, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_HSI_UFS_EMBD, MUX_CLKCMU_HSI_UFS_EMBD, CLK_CON_GAT_GATE_CLKCMU_HSI_UFS_EMBD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI_UFS_EMBD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_NPU0_BUS, MUX_CLKCMU_NPU0_BUS, CLK_CON_GAT_GATE_CLKCMU_NPU0_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_NPU0_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_NPU0_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_MIF_BUSP, MUX_CLKCMU_MIF_BUSP, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_PERI_IP, MUX_CLKCMU_PERI_IP, CLK_CON_GAT_GATE_CLKCMU_PERI_IP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERI_IP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERI_IP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CPUCL1_SWITCH, MUX_CLKCMU_CPUCL1_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_USB_BUS, MUX_CLKCMU_USB_BUS, CLK_CON_GAT_GATE_CLKCMU_USB_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_USB_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_USB_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_TNR_BUS, MUX_CLKCMU_TNR_BUS, CLK_CON_GAT_GATE_CLKCMU_TNR_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_TNR_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_TNR_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CORE_G3D, MUX_CLKCMU_CORE_G3D, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CORE_G3D_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CSIS_BUS, MUX_CLKCMU_CSIS_BUS, CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_MCSC_BUS, MUX_CLKCMU_MCSC_BUS, CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_MCSC_GDC, MUX_CLKCMU_MCSC_GDC, CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_G3D_BUS, PLL_G3D, CLK_CON_GAT_GATE_CLKCMU_G3D_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3D_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3D_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_USB_USB20DRD, MUX_CLKCMU_USB_USB20DRD, CLK_CON_GAT_GATE_CLKCMU_USB_USB20DRD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_USB_USB20DRD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_USB_USB20DRD_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(AP2CP_SHARED0_CLK, PLL_SHARED1, CLK_CON_GAT_AP2CP_SHARED0_CLK_CG_VAL, CLK_CON_GAT_AP2CP_SHARED0_CLK_MANUAL, CLK_CON_GAT_AP2CP_SHARED0_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(AP2CP_SHARED1_CLK, PLL_SHARED0, CLK_CON_GAT_AP2CP_SHARED1_CLK_CG_VAL, CLK_CON_GAT_AP2CP_SHARED1_CLK_MANUAL, CLK_CON_GAT_AP2CP_SHARED1_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_NPUS_BUS, MUX_CLKCMU_NPUS_BUS, CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_NPUS_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CORE_SSS, MUX_CLKCMU_CORE_SSS, CLK_CON_GAT_GATE_CLKCMU_CORE_SSS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CORE_SSS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CORE_SSS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(AP2CP_SHARED2_CLK, PLL_SHARED0, CLK_CON_GAT_AP2CP_SHARED2_CLK_CG_VAL, CLK_CON_GAT_AP2CP_SHARED2_CLK_MANUAL, CLK_CON_GAT_AP2CP_SHARED2_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(AP2CP_HISPEEDY_CLK, PLL_SHARED0, CLK_CON_GAT_AP2CP_HISPEEDY_CLK_CG_VAL, CLK_CON_GAT_AP2CP_HISPEEDY_CLK_MANUAL, CLK_CON_GAT_AP2CP_HISPEEDY_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_BUSC_BUS, MUX_CLKCMU_BUSC_BUS, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CIS_CLK3, MUX_CLKCMU_CIS_CLK3, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CIS_CLK4, MUX_CLKCMU_CIS_CLK4, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CIS_CLK5, MUX_CLKCMU_CIS_CLK5, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_DSU_SWITCH, MUX_CLKCMU_DSU_SWITCH, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_CPUCL0_BUSP, MUX_CLKCMU_CPUCL0_BUSP, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_BUSP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_DPU_DSIM, MUX_CLKCMU_DPU_DSIM, CLK_CON_GAT_GATE_CLKCMU_DPU_DSIM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DPU_DSIM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DPU_DSIM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_MCSC_MCSC, MUX_CLKCMU_MCSC_MCSC, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GATE_CLKCMU_AUD_BUS, MUX_CLKCMU_AUD_BUS, CLK_CON_GAT_GATE_CLKCMU_AUD_BUS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_AUD_BUS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_AUD_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK, OSCCLK_CORE, CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_ACLK_P_CORE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_DIT_IPCLKPORT_ICLKL2A_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_MI_D_HSI_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_HSI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_HSI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_HSI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P_CORE_IPCLKPORT_PCLK_P_CORE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_MI_D_WLBT_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_WLBT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_WLBT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_WLBT_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_WLBT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_WLBT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_WLBT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D0_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D1_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_MI_D_GNSS_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_D_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_NRT_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK, MUX_CLKCMU_CORE_G3D_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKS, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKS, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM, MUX_CLK_CORE_GIC, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_AXI_GIC_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK, MUX_CLKCMU_CORE_G3D_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_GCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_NRT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SIREX_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_USB_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MODEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_GIC_IPCLKPORT_CLK, MUX_CLK_CORE_GIC, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LH_AXI_MI_D_AUD_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_CP_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_NRT_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_HSI_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_HSI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_HSI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_HSI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TAA_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_GNSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_MODEM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_P_WLBT_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_ISP_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPU0_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_PERI_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_PERI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_PERI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LH_AXI_MI_D_SSS_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_SSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_SSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_SSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_SSS_IPCLKPORT_CLK, MUX_CLKCMU_CORE_SSS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_SSS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_SSS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_SSS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SYSMMU_ACEL_D_DIT_IPCLKPORT_CLK_S2, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D_DIT_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D_DIT_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D_DIT_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LH_AXI_SI_D_SSS_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_SSS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D_SSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D_SSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D_SSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_CP_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_ACLK, MUX_CLKCMU_CORE_SSS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_PUF_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_SSS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PUF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PUF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK, MUX_CLK_CORE_GIC, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKS, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_SSS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_PUF_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPUS_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_RT_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_RT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D0_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_RT_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_RT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_SI_D1_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_BUSC_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_BUSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_BUSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_BUSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_MCW_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LH_AXI_MI_D_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_G3D_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BAAW_D_SSS_IPCLKPORT_I_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_D_SSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_D_SSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BAAW_D_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_XIU_G_BDU_IPCLKPORT_ACLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_G_BDU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_G_BDU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_XIU_G_BDU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_PPC_DEBUG_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPC_DEBUG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LH_AXI_MI_D0_NPUS_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D0_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LH_AXI_MI_D1_NPUS_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SYSMMU_ACEL_D2_MODEM_IPCLKPORT_CLK_S2, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D2_MODEM_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D2_MODEM_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSMMU_ACEL_D2_MODEM_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_RSTNSYNC_I_ARESETN_SSS_IPCLKPORT_CLK, MUX_CLKCMU_CORE_SSS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_I_ARESETN_SSS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_I_ARESETN_SSS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_I_ARESETN_SSS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_SI_P_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LH_AST_MI_G_CPU_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AST_MI_G_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AST_MI_G_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AST_MI_G_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_SLH_AXI_MI_P_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_P_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_P_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_SLH_AXI_MI_P_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_VGEN_LITE_CORE_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_CORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_CORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_VGEN_LITE_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_AD_APB_VGEN_LITE_CORE_IPCLKPORT_PCLKM, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_VGEN_LITE_CORE_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_VGEN_LITE_CORE_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_AD_APB_VGEN_LITE_CORE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_LH_AXI_MI_D_M2M_IPCLKPORT_I_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_M2M_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_M2M_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_LH_AXI_MI_D_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_HW_APBSEMA_MEC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_CORE_BUS_USER, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSP_IPCLKPORT_CLK, DIV_CLK_CORE_BUSP, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_OSCCLK_IPCLKPORT_CLK, OSCCLK_CORE, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_SR_CLK_CORE_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK, OSCCLK_CPUCL0, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK, MUX_CLK_CPUCL0_PLL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK, MUX_CLK_CPUCL0_PLL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_CORECLK_AN, DIV_CLK_CPUCL0_CPU, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_CORECLK_AN_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_CORECLK_AN_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_CORECLK_AN_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HTU_CPUCL0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_CPUCL0_GLB_CMU_CPUCL0_GLB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_CSSYS_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_CSSYS_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_DBGCORE_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_G_INT_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_CSSYS_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_DBGCORE_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SLH_AXI_SI_G_INT_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK, MUX_CLKCMU_CPUCL0_DBG_BUS_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_OSCCLK_IPCLKPORT_CLK, OSCCLK_CPUCL0, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_GLB_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM, DIV_CLK_CLUSTER0_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_GLB_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_GLB_UID_RSTNSYNC_CLK_CPUCL0_CSSYS_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CORECLK_HC, DIV_CLK_CPUCL1_CPU, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CORECLK_HC_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CORECLK_HC_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CORECLK_HC_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK, DIV_CLK_CPUCL1_HTU, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_HTU_DIV_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK, DIV_CLK_CPUCL1_HTU, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_HTU_CPUCL1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK, OSCCLK_CPUCL1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_MCB_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_SI_OTF0_CSISTAA_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF0_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF0_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF0_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_SI_OTF1_CSISTAA_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF1_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF1_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF1_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF0_TAACSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF1_TAACSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS4_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_DCPHY_LINK_WRAP_IPCLKPORT_CSIS_LINK_ACLK_CSIS5_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D2_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_ACLK_VOTF1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSIS_PDP_IPCLKPORT_I_PDP_C2CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D3_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D2_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D4_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_CSIS_D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D3_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_LH_AXI_SI_D3_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D3_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D3_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D3_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_AF2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK, DIV_CLK_CSIS_BUSP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_PDP_STAT_IMG2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_SI_OTF2_CSISTAA_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF2_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF2_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_OTF2_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF2_TAACSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_SOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_VGEN_LITE0_CSIS_IPCLKPORT_CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE0_CSIS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE0_CSIS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE0_CSIS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_VGEN_LITE1_CSIS_IPCLKPORT_CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE1_CSIS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE1_CSIS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE1_CSIS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_VGEN_LITE2_CSIS_IPCLKPORT_CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE2_CSIS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE2_CSIS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_VGEN_LITE2_CSIS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_CSIS_BUS_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_SR_CLK_CSIS_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S1, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_ACLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_PCLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D0_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK, OSCCLK_DPU, CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DECON, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DECON_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DECON_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DECON_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DMA, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DPP, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DPP_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DPP_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DPP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S2, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D0_DPU_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKM, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_C2SERV, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_C2SERV_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_C2SERV_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_C2SERV_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_ACLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_PCLK, DIV_CLK_DPU_BUSP, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_D1_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S1, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S2, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_AXI_D1_DPU_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_DPU_UID_DPU_IPCLKPORT_I_NEWCLK, MUX_CLKCMU_DPU_DSIM_USER, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_IPCLKPORT_I_NEWCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_IPCLKPORT_I_NEWCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_IPCLKPORT_I_NEWCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DPU_UID_RSTNSYNC_SR_CLK_DPU_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_DPU_BUS_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_SR_CLK_DPU_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_SR_CLK_DPU_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_SR_CLK_DPU_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ACLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_SLH_AXI_SI_P_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_XIU_D_CPUCL0_IPCLKPORT_ACLK, DIV_CLK_CLUSTER0_ACLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_XIU_D_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_XIU_D_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_XIU_D_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_DSU_CMU_DSU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_LH_AXI_SI_D0_MIF_CPU_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ACLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D0_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D0_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D0_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_LH_AXI_SI_D1_MIF_CPU_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ACLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D1_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D1_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AXI_SI_D1_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK, DIV_CLK_CLUSTER0_PERIPHCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK, DIV_CLK_CLUSTER0_PERIPHCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRUN_CLUSTER0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK, DIV_CLK_CLUSTER0_PERIPHCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK, DIV_CLK_CLUSTER0_PERIPHCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPC_INSTRRET_CLUSTER0_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER0_ACLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER0_PERIPHCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PERIPHCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK, DIV_CLK_CLUSTER0_PCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK, DIV_CLK_CLUSTER0_PERIPHCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK, DIV_CLK_DSU_CLUSTER, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK, MUX_CLK_DSU_PLL, CLK_CON_GAT_GOUT_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_HTU_DSU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_OSCCLK_IPCLKPORT_CLK, OSCCLK_DSU, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK, MUX_CLK_DSU_PLL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_RSTNSYNC_CLK_DSU_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_CLUSTER0_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER0_PCLK, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DSU_UID_RSTNSYNC_CLK_CLUSTER_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_ACLK, DIV_CLK_CLUSTER0_ACLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_ACLK, DIV_CLK_CLUSTER0_ACLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_PCLK, MUX_CLKCMU_CPUCL0_BUSP_USER, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_PPMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_DSU_UID_LH_AST_SI_G_CPU_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ACLK, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AST_SI_G_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AST_SI_G_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DSU_UID_LH_AST_SI_G_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK, OSCCLK_G3D, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_P_INT_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_INT_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_LH_AXI_SI_D_G3D_IPCLKPORT_I_CLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_D_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_D_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_D_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_BUSP, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_ACLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_PPMU_D_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_AS_APB_SYSMMU_D_G3D_IPCLKPORT_PCLKM, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_SYSMMU_D_G3D_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_SYSMMU_D_G3D_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_SYSMMU_D_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_SYSMMU_D_G3D_IPCLKPORT_CLK_S2, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSMMU_D_G3D_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSMMU_D_G3D_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSMMU_D_G3D_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_G3D_BUS_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_HTU_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK, MUX_CLKCMU_G3D_BUS_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_XIU_D0_G3D_IPCLKPORT_ACLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_D0_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_D0_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_D0_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_AS_APB_VGENLITE_G3D_IPCLKPORT_PCLKM, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_VGENLITE_G3D_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_VGENLITE_G3D_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_AS_APB_VGENLITE_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_BUSD_IPCLKPORT_CLK, DIV_CLK_G3D_BUSD, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_SR_CLK_G3D_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK, AP2GNSS_CLK, CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GNSS_UID_GNSS_CMU_GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_HSI_UID_VGEN_LITE_HSI_IPCLKPORT_CLK, MUX_CLKCMU_HSI_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI_UID_VGEN_LITE_HSI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_VGEN_LITE_HSI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_VGEN_LITE_HSI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_HSI_UID_HSI_CMU_HSI_IPCLKPORT_PCLK, MUX_CLKCMU_HSI_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI_UID_HSI_CMU_HSI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_HSI_CMU_HSI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_HSI_CMU_HSI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK, MUX_CLKCMU_HSI_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_SYSREG_HSI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_HSI_UID_GPIO_HSI_IPCLKPORT_PCLK, MUX_CLKCMU_HSI_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_HSI_UID_SLH_AXI_SI_D_HSI_IPCLKPORT_I_CLK, MUX_CLKCMU_HSI_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_SI_D_HSI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_SI_D_HSI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_SI_D_HSI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_HSI_UID_SLH_AXI_MI_P_HSI_IPCLKPORT_I_CLK, MUX_CLKCMU_HSI_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_MI_P_HSI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_MI_P_HSI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_SLH_AXI_MI_P_HSI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_ACLK, MUX_CLKCMU_HSI_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_PCLK, MUX_CLKCMU_HSI_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_PPMU_HSI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_BUS_IPCLKPORT_CLK, MUX_CLKCMU_HSI_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_OSCCLK_IPCLKPORT_CLK, OSCCLK_HSI, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_CLK_HSI_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_HSI_UID_D_TZPC_HSI_IPCLKPORT_PCLK, MUX_CLKCMU_HSI_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI_UID_D_TZPC_HSI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_D_TZPC_HSI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_D_TZPC_HSI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK, MUX_CLKCMU_HSI_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, MUX_CLKCMU_HSI_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, MUX_CLKCMU_HSI_UFS_EMBD_USER, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_HSI_UID_S2MPU_D_HSI_IPCLKPORT_CLK_S2, MUX_CLKCMU_HSI_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI_UID_S2MPU_D_HSI_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_S2MPU_D_HSI_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_S2MPU_D_HSI_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_HSI_UID_GPIO_HSI_UFS_IPCLKPORT_PCLK, MUX_CLKCMU_HSI_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_UFS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_UFS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_GPIO_HSI_UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_HSI_UID_RSTNSYNC_SR_CLK_HSI_BUS_IPCLKPORT_CLK, MUX_CLKCMU_HSI_BUS_USER, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_SR_CLK_HSI_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_SR_CLK_HSI_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI_UID_RSTNSYNC_SR_CLK_HSI_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSREG_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_ISP_CMU_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_RSTNSYNC_CLK_ISP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISP_UID_D_TZPC_ISP_IPCLKPORT_PCLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_GOUT_BLK_ISP_UID_D_TZPC_ISP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_D_TZPC_ISP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_D_TZPC_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_PCLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_ISP_UID_LH_AXI_SI_D_ISP_IPCLKPORT_I_CLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_CLK_BLK_ISP_UID_LH_AXI_SI_D_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_LH_AXI_SI_D_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_LH_AXI_SI_D_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_ACLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_PPMU_ISP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISP_UID_AD_APB_ITP_IPCLKPORT_PCLKM, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_ITP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_ITP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_ITP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_ITP_CLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_ITP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_ITP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_ITP_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_DNS_CLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_DNS_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_DNS_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_ITP_DNS_IPCLKPORT_I_DNS_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S1, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S2, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SYSMMU_D_ISP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISP_UID_LH_AST_MI_OTF_TAAISP_IPCLKPORT_I_CLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF_TAAISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF_TAAISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF_TAAISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISP_UID_LH_AST_SI_OTF_ISPMCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_SI_OTF_ISPMCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_SI_OTF_ISPMCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_SI_OTF_ISPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISP_UID_LH_AST_MI_OTF0_TNRISP_IPCLKPORT_I_CLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF0_TNRISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF0_TNRISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF0_TNRISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISP_UID_LH_AST_MI_OTF1_TNRISP_IPCLKPORT_I_CLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF1_TNRISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF1_TNRISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_LH_AST_MI_OTF1_TNRISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISP_UID_XIU_D_ISP_IPCLKPORT_ACLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_XIU_D_ISP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_XIU_D_ISP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_XIU_D_ISP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISP_UID_AD_APB_VGEN_LITE_ISP_IPCLKPORT_PCLKM, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_VGEN_LITE_ISP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_VGEN_LITE_ISP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_AD_APB_VGEN_LITE_ISP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_ISP_UID_VGEN_LITE_ISP_IPCLKPORT_CLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_CLK_BLK_ISP_UID_VGEN_LITE_ISP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ISP_UID_VGEN_LITE_ISP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ISP_UID_VGEN_LITE_ISP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISP_UID_SLH_AXI_MI_P_ISP_IPCLKPORT_I_CLK, DIV_CLK_ISP_BUSP, CLK_CON_GAT_GOUT_BLK_ISP_UID_SLH_AXI_MI_P_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SLH_AXI_MI_P_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_SLH_AXI_MI_P_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_ISP_UID_RSTNSYNC_SR_CLK_ISP_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_ISP_BUS_USER, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_SR_CLK_ISP_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_SR_CLK_ISP_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ISP_UID_RSTNSYNC_SR_CLK_ISP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF, MUX_CLKCMU_M2M_MSCL_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_VOTF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK, DIV_CLK_M2M_BUSP, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_M2M_UID_M2M_CMU_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK, DIV_CLK_M2M_BUSP, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSREG_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK, DIV_CLK_M2M_BUSP, CLK_CON_GAT_GOUT_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SLH_AXI_MI_P_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1, MUX_CLKCMU_M2M_MSCL_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_MSCL_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK, DIV_CLK_M2M_BUSP, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_PPMU_D_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_MSCL_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_XIU_D_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK, DIV_CLK_M2M_BUSP, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK, MUX_CLKCMU_M2M_MSCL_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_M2M_UID_AS_APB_JPEG0_IPCLKPORT_PCLKM, MUX_CLKCMU_M2M_MSCL_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_JPEG0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_JPEG0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_JPEG0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK, MUX_CLKCMU_M2M_MSCL_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_JPEG0_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK, DIV_CLK_M2M_BUSP, CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_D_TZPC_M2M_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2, MUX_CLKCMU_M2M_MSCL_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_SYSMMU_D_M2M_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_M2M_UID_LH_AXI_SI_D_M2M_IPCLKPORT_I_CLK, MUX_CLKCMU_M2M_MSCL_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_LH_AXI_SI_D_M2M_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_LH_AXI_SI_D_M2M_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_LH_AXI_SI_D_M2M_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK, MUX_CLKCMU_M2M_MSCL_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1, MUX_CLKCMU_M2M_MSCL_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_M2M_IPCLKPORT_ACLK_2X1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_M2M_UID_AS_APB_VGEN_LITE_M2M_IPCLKPORT_PCLKM, MUX_CLKCMU_M2M_MSCL_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_VGEN_LITE_M2M_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_VGEN_LITE_M2M_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_AS_APB_VGEN_LITE_M2M_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK, MUX_CLKCMU_M2M_MSCL_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_VGEN_LITE_M2M_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK, MUX_CLKCMU_M2M_MSCL_USER, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_M2M_UID_RSTNSYNC_SR_CLK_M2M_BUSD_MSCL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK, MUX_CLKCMU_MCSC_GDC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM, MUX_CLKCMU_MCSC_GDC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_GDC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_GDC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_PCLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK, MUX_CLKCMU_MCSC_GDC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKM, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_AD_AXI_GDC_IPCLKPORT_ACLKM, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_GDC_IPCLKPORT_ACLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_GDC_IPCLKPORT_ACLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_GDC_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_PCLK, DIV_CLK_MCSC_BUSP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_TREX_D_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D2_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_LH_AXI_MI_D3_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D3_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D3_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D3_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_LH_AXI_MI_D_ISP_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_ISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_ISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_ISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_LH_AXI_MI_D_TAA_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_TAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_TAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_MI_D_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_LH_AST_MI_OTF_ISPMCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_OTF_ISPMCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_OTF_ISPMCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_OTF_ISPMCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_XIU_D_MCSC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_XIU_D_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_C2CLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_C2CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_C2CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ORBMCH_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_AD_APB_SYSMMU_D0_MCSC_NS_IPCLKPORT_PCLKM, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_SYSMMU_D0_MCSC_NS_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_SYSMMU_D0_MCSC_NS_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_SYSMMU_D0_MCSC_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_VGEN_LITE_MCSC_IPCLKPORT_CLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_MCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_MCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_VGEN_LITE_GDC_IPCLKPORT_CLK, MUX_CLKCMU_MCSC_GDC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_GDC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_GDC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_VGEN_LITE_GDC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKS, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_AXI_MCSC_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_MCSC_BUS_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_SR_CLK_MCSC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_RSTNSYNC_SR_CLK_MFC_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_SR_CLK_MFC_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_SR_CLK_MFC_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_SR_CLK_MFC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_LH_AXI_SI_D_MFC_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S1, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S2, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_MFC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK, DIV_CLK_MFC_BUSP, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MFC_UID_VGEN_LITE_MFC_IPCLKPORT_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_VGEN_LITE_MFC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_VGEN_LITE_MFC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_VGEN_LITE_MFC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDRPHY_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDRPHY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDRPHY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK, OSCCLK_MIF, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK, DIV_CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK, DIV_CLK_MIF_BUSD, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK, DIV_CLK_MIF_BUSD, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_SECURE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SFRAPB_BRIDGE_DMC_PPMPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK, DIV_CLK_MIF_BUSD, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QE_DMC_CPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_PPMU_DMC_CPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PPMPU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF, MUX_CLKCMU_MIF_BUSP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_PF_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CPU_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUSD, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_RT_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUSD, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_RT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_RT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_RT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_NRT_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUSD, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_NRT_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_NRT_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_NRT_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CP_IPCLKPORT_I_CLK, DIV_CLK_MIF_BUSD, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_D_MIF_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK, AP2CP_SHARED0_CLK, CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MODEM_UID_MODEM_CMU_MODEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSD_IPCLKPORT_CLK, DIV_CLK_NPU0_BUS, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSP_IPCLKPORT_CLK, DIV_CLK_NPU0_BUSP, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_NPU0_UID_NPU0_CMU_NPU0_IPCLKPORT_PCLK, DIV_CLK_NPU0_BUSP, CLK_CON_GAT_CLK_BLK_NPU0_UID_NPU0_CMU_NPU0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPU0_UID_NPU0_CMU_NPU0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPU0_UID_NPU0_CMU_NPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPU0_UID_D_TZPC_NPU0_IPCLKPORT_PCLK, DIV_CLK_NPU0_BUSP, CLK_CON_GAT_GOUT_BLK_NPU0_UID_D_TZPC_NPU0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_D_TZPC_NPU0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_D_TZPC_NPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPU0_UID_SYSREG_NPU0_IPCLKPORT_PCLK, DIV_CLK_NPU0_BUSP, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SYSREG_NPU0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SYSREG_NPU0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SYSREG_NPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPU0_UID_SLH_AXI_MI_P_NPU0_IPCLKPORT_I_CLK, DIV_CLK_NPU0_BUSP, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SLH_AXI_MI_P_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SLH_AXI_MI_P_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_SLH_AXI_MI_P_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_PCLK, DIV_CLK_NPU0_BUSP, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_ACLK, DIV_CLK_NPU0_BUS, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPU0_UID_IP_NPUCORE_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPU0_UID_LH_AXI_MI_D_CTRL_NPU0_IPCLKPORT_I_CLK, DIV_CLK_NPU0_BUSP, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D_CTRL_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D_CTRL_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D_CTRL_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPU0_UID_LH_AXI_MI_D0_NPU0_IPCLKPORT_I_CLK, DIV_CLK_NPU0_BUS, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D0_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D0_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D0_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPU0_UID_LH_AXI_SI_D_RQ_NPU0_IPCLKPORT_I_CLK, DIV_CLK_NPU0_BUS, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_RQ_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_RQ_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_RQ_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPU0_UID_LH_AXI_SI_D_CMDQ_NPU0_IPCLKPORT_I_CLK, DIV_CLK_NPU0_BUS, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_CMDQ_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_CMDQ_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_SI_D_CMDQ_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPU0_UID_LH_AXI_MI_D1_NPU0_IPCLKPORT_I_CLK, DIV_CLK_NPU0_BUS, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D1_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D1_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPU0_UID_LH_AXI_MI_D1_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_VGEN_LITE_NPUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_LH_AXI_MI_D_RQ_NPU0_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_RQ_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_RQ_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_RQ_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_LH_AXI_SI_D_CTRL_NPU0_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D_CTRL_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D_CTRL_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D_CTRL_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPU0_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPUS_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D0_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPUS_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D0_NPUS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_DBGCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK, MUX_CLKCMU_NPUS_BUS_USER, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK, MUX_CLKCMU_NPUS_BUS_USER, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_HTU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_LH_AXI_MI_D_CMDQ_NPU0_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_CMDQ_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_CMDQ_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_MI_D_CMDQ_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SYSMMU_D1_NPUS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPU0_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPU0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPU0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_LH_AXI_SI_D1_NPU0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_DS_256_128_0_IPCLKPORT_MAINCLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_0_IPCLKPORT_MAINCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_0_IPCLKPORT_MAINCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_0_IPCLKPORT_MAINCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_DS_256_128_1_IPCLKPORT_MAINCLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_1_IPCLKPORT_MAINCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_1_IPCLKPORT_MAINCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_DS_256_128_1_IPCLKPORT_MAINCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK, OSCCLK_NPUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A0CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_C2A1CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_CLK_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_D_TZPC_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_PPMU_NPUS_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_INT_NPUS_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_INT_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_INT_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_INT_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_SLH_AXI_SI_P_INT_NPUS_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_SI_P_INT_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_SI_P_INT_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_SI_P_INT_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_IP_NPUS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_CLK_NPUS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKS, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKM, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_AD_APB_SYSMMU_D0_NPUS_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_CLK_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_SYSREG_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_NPUS_IPCLKPORT_I_CLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_NPUS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_NPUS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_SLH_AXI_MI_P_NPUS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_ADM_DAP_NPUS_IPCLKPORT_DAPCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_NPUS_UID_RSTNSYNC_SR_CLK_NPUS_BUSD_IPCLKPORT_CLK, DIV_CLK_NPUS_BUS, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_SR_CLK_NPUS_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_SR_CLK_NPUS_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NPUS_UID_RSTNSYNC_SR_CLK_NPUS_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_HTU_NPUS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK, DIV_CLK_NPUS_BUSP, CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NPUS_UID_NPUS_CMU_NPUS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERI_UID_PERI_CMU_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUSP_IPCLKPORT_CLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK, OSCCLK_PERI, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERI_UID_RSTNSYNC_CLK_PERI_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK, DIV_CLK_PERI_USI00_USI, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI00_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI_I2C_IPCLKPORT_CLK, DIV_CLK_PERI_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI_I2C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI_I2C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI_I2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI01_USI_IPCLKPORT_CLK, DIV_CLK_PERI_USI01_USI, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI01_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI01_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI01_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI02_USI_IPCLKPORT_CLK, DIV_CLK_PERI_USI02_USI, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI02_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI02_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI02_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI03_USI_IPCLKPORT_CLK, DIV_CLK_PERI_USI03_USI, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI03_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI03_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI03_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI04_USI_IPCLKPORT_CLK, DIV_CLK_PERI_USI04_USI, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI04_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI04_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI04_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI05_USI_IPCLKPORT_CLK, DIV_CLK_PERI_USI05_USI, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI05_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI05_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI05_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_DBG_IPCLKPORT_CLK, DIV_CLK_PERI_UART_DBG, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_DBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_DBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_UART_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_SLH_AXI_MI_P_PERI_IPCLKPORT_I_CLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_MI_P_PERI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_MI_P_PERI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_MI_P_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_D_TZPC_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_XIU_P_PERI_IPCLKPORT_ACLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_XIU_P_PERI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_XIU_P_PERI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_XIU_P_PERI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_WDT0_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_WDT1_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_WDT1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_TMU_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_TMU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_TMU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_TMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, OSCCLK_PERI, CLK_CON_GAT_CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_PWM_IPCLKPORT_I_PCLK_S0, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_IPCLKPORT_I_PCLK_S0_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_IPCLKPORT_I_PCLK_S0_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_PWM_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_IPCLK, DIV_CLK_PERI_UART_DBG, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_UART_DBG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI00_USI, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI00_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI01_USI, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI01_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI02_USI, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI03_USI, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI03_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI04_USI, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI04_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI05_USI, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI05_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI02_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_VGEN_LITE_PERI_IPCLKPORT_CLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_VGEN_LITE_PERI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_VGEN_LITE_PERI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_VGEN_LITE_PERI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_S2MPU_D_PERI_IPCLKPORT_CLK_S2, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_S2MPU_D_PERI_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_S2MPU_D_PERI_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_S2MPU_D_PERI_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_I_ACLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_SDCLKIN, MUX_CLKCMU_PERI_MMC_CARD_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_ACLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_PPMU_PERI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_SLH_AXI_SI_D_PERI_IPCLKPORT_I_CLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_SI_D_PERI_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_SI_D_PERI_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_SLH_AXI_SI_D_PERI_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_GPIO_PERIMMC_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERIMMC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERIMMC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_GPIO_PERIMMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI06_USI_IPCLKPORT_CLK, DIV_CLK_PERI_USI06_USI, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI06_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI06_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_CLK_PERI_USI06_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI06_USI, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI06_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_IPCLK, DIV_CLK_PERI_USI_I2C, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_PCLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_USI07_I2C_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_PERI_UID_RSTNSYNC_SR_CLK_PERI_BUSP_IPCLKPORT_CLK, MUX_CLKCMU_PERI_BUS_USER, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_SR_CLK_PERI_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_SR_CLK_PERI_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERI_UID_RSTNSYNC_SR_CLK_PERI_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK, MUX_CLK_S2D_CORE, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK, MUX_CLK_S2D_CORE, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK, MUX_CLK_S2D_CORE, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK, I_SCLK_S2D, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK, MUX_CLK_S2D_CORE, CLK_CON_GAT_GOUT_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_SLH_AXI_MI_G_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK, I_SCLK_S2D, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_LH_AXI_SI_D_TAA_IPCLKPORT_I_CLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AXI_SI_D_TAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AXI_SI_D_TAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AXI_SI_D_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_SLH_AXI_MI_P_TAA_IPCLKPORT_I_CLK, DIV_CLK_TAA_BUSP, CLK_CON_GAT_GOUT_BLK_TAA_UID_SLH_AXI_MI_P_TAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SLH_AXI_MI_P_TAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SLH_AXI_MI_P_TAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK, DIV_CLK_TAA_BUSP, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSREG_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK, DIV_CLK_TAA_BUSP, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK, DIV_CLK_TAA_BUSP, CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_TAA_UID_TAA_CMU_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_LH_AST_SI_OTF_TAAISP_IPCLKPORT_I_CLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_OTF_TAAISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_OTF_TAAISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_OTF_TAAISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK, DIV_CLK_TAA_BUSP, CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_D_TZPC_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_LH_AST_MI_OTF0_CSISTAA_IPCLKPORT_I_CLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF0_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF0_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF0_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK, OSCCLK_TAA, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_CLK_TAA_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK, DIV_CLK_TAA_BUSP, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_PPMU_TAA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_LH_AST_MI_OTF1_CSISTAA_IPCLKPORT_I_CLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF1_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF1_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF1_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_LH_AST_SI_SOTF0_TAACSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF0_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF0_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF0_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_LH_AST_SI_SOTF1_TAACSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF1_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF1_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF1_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_STAT_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_AD_APB_TAA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S1, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S2, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SYSMMU_TAA_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_XIU_D_TAA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_SIPU_TAA_IPCLKPORT_CLK_C2COM_YDS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_LH_AST_MI_OTF2_CSISTAA_IPCLKPORT_I_CLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF2_CSISTAA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF2_CSISTAA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_MI_OTF2_CSISTAA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_ZOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_LH_AST_SI_SOTF2_TAACSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF2_TAACSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF2_TAACSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_LH_AST_SI_SOTF2_TAACSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_VGEN_LITE0_TAA_IPCLKPORT_CLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE0_TAA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE0_TAA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE0_TAA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_VGEN_LITE1_TAA_IPCLKPORT_CLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE1_TAA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE1_TAA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_VGEN_LITE1_TAA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TAA_UID_RSTNSYNC_SR_CLK_TAA_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_TAA_BUS_USER, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_SR_CLK_TAA_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_SR_CLK_TAA_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TAA_UID_RSTNSYNC_SR_CLK_TAA_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_BUSP, CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK, DIV_CLK_TNR_BUSP, CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_APB_ASYNC_TNR_0_IPCLKPORT_PCLKM, MUX_CLKCMU_TNR_BUS_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_TNR_0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_TNR_0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_TNR_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK, MUX_CLKCMU_TNR_BUS_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK, MUX_CLKCMU_TNR_BUS_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_BUSP, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_BUSP, CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_BUS_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_BUSP, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_BUS_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_BUSP, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_BUS_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1, MUX_CLKCMU_TNR_BUS_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2, MUX_CLKCMU_TNR_BUS_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1, MUX_CLKCMU_TNR_BUS_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2, MUX_CLKCMU_TNR_BUS_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP0, MUX_CLKCMU_TNR_BUS_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP0_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP0_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_TNR_BUS_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSP_IPCLKPORT_CLK, DIV_CLK_TNR_BUSP, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_LH_AST_SI_OTF0_TNRISP_IPCLKPORT_I_CLK, MUX_CLKCMU_TNR_BUS_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF0_TNRISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF0_TNRISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF0_TNRISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_BUS_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_LH_AST_SI_OTF1_TNRISP_IPCLKPORT_I_CLK, MUX_CLKCMU_TNR_BUS_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF1_TNRISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF1_TNRISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_OTF1_TNRISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP1, MUX_CLKCMU_TNR_BUS_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP1_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP1_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MCFP1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_VGEN_LITE_D_TNR_IPCLKPORT_CLK, MUX_CLKCMU_TNR_BUS_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_VGEN_LITE_D_TNR_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_VGEN_LITE_D_TNR_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_VGEN_LITE_D_TNR_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_TNR_UID_RSTNSYNC_SR_CLK_TNR_BUSD_IPCLKPORT_CLK, MUX_CLKCMU_TNR_BUS_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_SR_CLK_TNR_BUSD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_SR_CLK_TNR_BUSD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_SR_CLK_TNR_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_26, MUX_CLK_USB_USB20DRD, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_26_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_26_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_I_USB20DRD_REF_CLK_26_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK, MUX_CLK_USB_BUS, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_USB_UID_SLH_AXI_SI_D_USB_IPCLKPORT_I_CLK, MUX_CLK_USB_BUS, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK, MUX_CLK_USB_BUS, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_CLK_USB_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_USB_UID_VGEN_LITE_USB_IPCLKPORT_CLK, MUX_CLK_USB_BUS, CLK_CON_GAT_GOUT_BLK_USB_UID_VGEN_LITE_USB_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_VGEN_LITE_USB_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_VGEN_LITE_USB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_USB_UID_D_TZPC_USB_IPCLKPORT_PCLK, MUX_CLK_USB_BUS, CLK_CON_GAT_GOUT_BLK_USB_UID_D_TZPC_USB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_D_TZPC_USB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_D_TZPC_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_USB_UID_SLH_AXI_MI_P_USB_IPCLKPORT_I_CLK, MUX_CLK_USB_BUS, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_MI_P_USB_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_MI_P_USB_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_MI_P_USB_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK, MUX_CLK_USB_BUS, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_PPMU_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_USB_UID_S2MPU_D_USB_IPCLKPORT_CLK_S2, MUX_CLK_USB_BUS, CLK_CON_GAT_GOUT_BLK_USB_UID_S2MPU_D_USB_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_S2MPU_D_USB_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_S2MPU_D_USB_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK, MUX_CLK_USB_BUS, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SYSREG_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_ACLK_PHYCTRL, MUX_CLK_USB_BUS, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_ACLK_PHYCTRL_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_ACLK_PHYCTRL_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_ACLK_PHYCTRL_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_BUS_CLK_EARLY, MUX_CLK_USB_BUS, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_BUS_CLK_EARLY_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_BUS_CLK_EARLY_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_USB20DRD_TOP_IPCLKPORT_BUS_CLK_EARLY_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK, MUX_CLK_USB_BUS, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_USB_UID_USB_CMU_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_USB_UID_XIU_D_USB_IPCLKPORT_ACLK, MUX_CLK_USB_BUS, CLK_CON_GAT_GOUT_BLK_USB_UID_XIU_D_USB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_XIU_D_USB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_XIU_D_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_USB_UID_SLH_AXI_SI_D_USBAUD_IPCLKPORT_I_CLK, MUX_CLK_USB_BUS, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USBAUD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USBAUD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_SLH_AXI_SI_D_USBAUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_USB_UID_URAM_IPCLKPORT_ACLK, MUX_CLK_USB_BUS, CLK_CON_GAT_GOUT_BLK_USB_UID_URAM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_URAM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_URAM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_USB_UID_RSTNSYNC_SR_CLK_USB_BUS_IPCLKPORT_CLK, MUX_CLK_USB_BUS, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_SR_CLK_USB_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_SR_CLK_USB_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_USB_UID_RSTNSYNC_SR_CLK_USB_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_AHB_BUSMATRIX_VTS_IPCLKPORT_HCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_VTS_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_VTS_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB_BUSMATRIX_VTS_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK, OSCCLK_RCO_VTS, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK, DIV_CLK_VTS_DMIC_IF, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_CM4_VTS_IPCLKPORT_FCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_CM4_VTS_IPCLKPORT_FCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_CM4_VTS_IPCLKPORT_FCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_CM4_VTS_IPCLKPORT_FCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_TIMER_VTS_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_VTS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_VTS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_TIMER_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK, DIV_CLK_VTS_DMIC_IF, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK, DIV_CLK_VTS_DMIC_IF, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_SLH_AXI_MI_S_VTS_IPCLKPORT_I_CLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_MI_S_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_MI_S_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_MI_S_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_SLH_AXI_SI_M_VTS_IPCLKPORT_I_CLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_SI_M_VTS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_SI_M_VTS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SLH_AXI_SI_M_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(CLK_BLK_VTS_UID_U_DMIC_CLK_SCAN_MUX_IPCLKPORT_D0, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_SCAN_MUX_IPCLKPORT_D0_CG_VAL, CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_SCAN_MUX_IPCLKPORT_D0_MANUAL, CLK_CON_GAT_CLK_BLK_VTS_UID_U_DMIC_CLK_SCAN_MUX_IPCLKPORT_D0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_AXI2AHB_VTS_IPCLKPORT_CLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_AXI2AHB_VTS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_AXI2AHB_VTS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_AXI2AHB_VTS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_AHB2AXI_VTS_IPCLKPORT_ACLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB2AXI_VTS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB2AXI_VTS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_AHB2AXI_VTS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_HCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_BUS_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK, DIV_CLK_VTS_BUS, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_HWACG_SYS_SERIAL_LIF_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK, DIV_VTS_DMIC_AUD_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK, DIV_VTS_DMIC_AUD, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK, DIV_VTS_DMIC_AUD_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD0_IPCLKPORT_DMIC_AUD_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK, DIV_VTS_DMIC_AUD, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AUD1_IPCLKPORT_DMIC_AUD_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_BCLK, DIV_VTS_SERIAL_LIF, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_BCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_BCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_BCLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_CLK, DIV_VTS_SERIAL_LIF_CORE, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SERIAL_LIF_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0, DIV_VTS_DMIC_AUD_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1, DIV_VTS_DMIC_AUD_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_PAD_CLK1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1, DIV_CLK_VTS_DMIC_IF_DIV2, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK, DIV_VTS_DMIC_AUD, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_AUD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK, DIV_VTS_SERIAL_LIF_CORE, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
	CLK_GATE(GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK, DIV_VTS_SERIAL_LIF, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING),
};

unsigned int cmucal_fixed_rate_size = 45;
struct cmucal_clk_fixed_rate cmucal_fixed_rate_list[] = {
	FIXEDRATE(OSCCLK_RCO_ALIVE, 24576000, EMPTY_CAL_ID),
	FIXEDRATE(CLK_RCO_ALIVE, 60000000, EMPTY_CAL_ID),
	FIXEDRATE(CLK_RCO_I3C_PMIC, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(RTCCLK_ALIVE, 287000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_ALIVE, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_AUD, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(IOCLK_AUDIOCDCLK0, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(IOCLK_AUDIOCDCLK1, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(IOCLK_AUDIOCDCLK2, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(IOCLK_AUDIOCDCLK3, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(IOCLK_AUDIOCDCLK4, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(TICK_USB, 60000000, EMPTY_CAL_ID),
	FIXEDRATE(IOCLK_AUDIOCDCLK5, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(IOCLK_AUDIOCDCLK6, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(CLKIO_AUD_DSIF, 25000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_BUSC, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_RCO_CHUB, 24576000, EMPTY_CAL_ID),
	FIXEDRATE(RTCCLK_CHUB, 25000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_RCO_CHUBVTS, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_RCO_CMGP, 24576000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_CMU, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_CORE, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_CPUCL0, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_CPUCL1, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_CSIS, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_DPU, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_DSU, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_G3D, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_HSI, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_ISP, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_M2M, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_MCSC, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_MFC, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_MIF, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(PCMC_CLK, 50000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_NPU0, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_NPUS, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_PERI, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_S2D, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(I_SCLK_S2D, 100000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_TAA, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_TNR, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_USB, 26000000, EMPTY_CAL_ID),
	FIXEDRATE(OSCCLK_RCO_VTS, 24576000, EMPTY_CAL_ID),
	FIXEDRATE(RCO_400, 393216000, EMPTY_CAL_ID),
};

unsigned int cmucal_fixed_factor_size = 16;
struct cmucal_clk_fixed_factor cmucal_fixed_factor_list[] = {
	FIXEDFACTOR(CLKCMU_OTP, OSCCLK_CMU, 7, CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING),
	FIXEDFACTOR(DIV_CLK_MIF_BUSD, CLKMUX_MIF_DDRPHY2X, 7, CLK_CON_DIV_DIV_CLK_MIF_BUSD_ENABLE_AUTOMATIC_CLKGATING),
	FIXEDFACTOR(CLK_MIF_BUSD_S2D, CLKCMU_MIF_DDRPHY2X_S2D, 3, CLK_CON_DIV_CLK_MIF_BUSD_S2D_ENABLE_AUTOMATIC_CLKGATING),
	FIXEDFACTOR(PLL_SHARED0_D1, PLL_SHARED0, 0, EMPTY_CAL_ID),
	FIXEDFACTOR(PLL_SHARED0_D2, PLL_SHARED0, 1, EMPTY_CAL_ID),
	FIXEDFACTOR(PLL_SHARED0_D3, PLL_SHARED0, 2, EMPTY_CAL_ID),
	FIXEDFACTOR(PLL_SHARED0_D4, PLL_SHARED0, 3, EMPTY_CAL_ID),
	FIXEDFACTOR(PLL_SHARED1_D1, PLL_SHARED1, 0, EMPTY_CAL_ID),
	FIXEDFACTOR(PLL_SHARED1_D2, PLL_SHARED1, 1, EMPTY_CAL_ID),
	FIXEDFACTOR(PLL_SHARED1_D3, PLL_SHARED1, 2, EMPTY_CAL_ID),
	FIXEDFACTOR(PLL_SHARED1_D4, PLL_SHARED1, 3, EMPTY_CAL_ID),
	FIXEDFACTOR(PLL_SHARED2_D1, PLL_SHARED2, 0, EMPTY_CAL_ID),
	FIXEDFACTOR(PLL_SHARED2_D2, PLL_SHARED2, 1, EMPTY_CAL_ID),
	FIXEDFACTOR(PLL_SHARED2_D3, PLL_SHARED2, 2, EMPTY_CAL_ID),
	FIXEDFACTOR(PLL_SHARED2_D4, PLL_SHARED2, 3, EMPTY_CAL_ID),
	FIXEDFACTOR(PLL_MMC_D2, PLL_MMC, 1, EMPTY_CAL_ID),
	FIXEDFACTOR(PLL_AUD_D1, PLL_AUD, 0, EMPTY_CAL_ID),
	FIXEDFACTOR(PLL_AUD_D2, PLL_AUD, 1, EMPTY_CAL_ID),
	FIXEDFACTOR(PLL_AUD_D3, PLL_AUD, 2, EMPTY_CAL_ID),
	FIXEDFACTOR(PLL_AUD_D4, PLL_AUD, 3, EMPTY_CAL_ID),
};