// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * ALSA SoC - Samsung Abox SoC dependent layer
 *
 * Copyright (c) 2018 Samsung Electronics Co. Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/io.h>
#include <linux/regmap.h>
#include "abox.h"
#include "abox_soc.h"

int abox_soc_ver(struct device *adev)
{
	struct abox_data *data = dev_get_drvdata(adev);

	return readl(data->sfr_base + ABOX_VERSION) >> ABOX_VERSION_L;
}

int abox_soc_vercmp(struct device *adev, int m, int n, int r)
{
	return ABOX_SOC_VERSION(m, n, r) - abox_soc_ver(adev);
}

static bool volatile_reg_legacy(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case ABOX_SYSPOWER_CTRL:
	case ABOX_SYSPOWER_STATUS:
	case ABOX_SPUS_CTRL2:
	case ABOX_SPUS_CTRL3:
	case ABOX_SPUM_CTRL2:
	case ABOX_SPUM_CTRL3:
	case ABOX_UAIF_STATUS(0):
	case ABOX_UAIF_STATUS(1):
	case ABOX_UAIF_STATUS(2):
	case ABOX_UAIF_STATUS(3):
	case ABOX_UAIF_STATUS(4):
	case ABOX_DSIF_STATUS:
	case ABOX_RDMA_CTRL1(0):
	case ABOX_RDMA_STATUS(0):
	case ABOX_RDMA_CTRL1(1):
	case ABOX_RDMA_STATUS(1):
	case ABOX_RDMA_CTRL1(2):
	case ABOX_RDMA_STATUS(2):
	case ABOX_RDMA_CTRL1(3):
	case ABOX_RDMA_STATUS(3):
	case ABOX_RDMA_CTRL1(4):
	case ABOX_RDMA_STATUS(4):
	case ABOX_RDMA_CTRL1(5):
	case ABOX_RDMA_STATUS(5):
	case ABOX_RDMA_CTRL1(6):
	case ABOX_RDMA_STATUS(6):
	case ABOX_RDMA_CTRL1(7):
	case ABOX_RDMA_STATUS(7):
	case ABOX_WDMA_STATUS(0):
	case ABOX_WDMA_STATUS(1):
	case ABOX_WDMA_STATUS(2):
	case ABOX_WDMA_STATUS(3):
	case ABOX_WDMA_STATUS(4):
	case ABOX_CA7_R(0):
	case ABOX_CA7_R(1):
	case ABOX_CA7_R(2):
	case ABOX_CA7_R(3):
	case ABOX_CA7_R(4):
	case ABOX_CA7_R(5):
	case ABOX_CA7_R(6):
	case ABOX_CA7_R(7):
	case ABOX_CA7_R(8):
	case ABOX_CA7_R(9):
	case ABOX_CA7_R(10):
	case ABOX_CA7_R(11):
	case ABOX_CA7_R(12):
	case ABOX_CA7_R(13):
	case ABOX_CA7_R(14):
	case ABOX_CA7_PC:
		return true;
	default:
		return false;
	}
}

static bool readable_reg_legacy(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case ABOX_IP_INDEX:
	case ABOX_VERSION:
	case ABOX_SYSPOWER_CTRL:
	case ABOX_SYSPOWER_STATUS:
	case ABOX_SYSTEM_CONFIG0:
	case ABOX_REMAP_MASK:
	case ABOX_REMAP_ADDR:
	case ABOX_DYN_CLOCK_OFF:
	case ABOX_QCHANNEL_DISABLE:
	case ABOX_ROUTE_CTRL0:
	case ABOX_ROUTE_CTRL1:
	case ABOX_ROUTE_CTRL2:
	case ABOX_SPUS_CTRL0:
	case ABOX_SPUS_CTRL1:
	case ABOX_SPUS_CTRL2:
	case ABOX_SPUS_CTRL3:
	case ABOX_SPUS_SBANK_RDMA(0):
	case ABOX_SPUS_SBANK_RDMA(1):
	case ABOX_SPUS_SBANK_RDMA(2):
	case ABOX_SPUS_SBANK_RDMA(3):
	case ABOX_SPUS_SBANK_RDMA(4):
	case ABOX_SPUS_SBANK_RDMA(5):
	case ABOX_SPUS_SBANK_RDMA(6):
	case ABOX_SPUS_SBANK_RDMA(7):
	case ABOX_SPUS_SBANK_ASRC(0):
	case ABOX_SPUS_SBANK_ASRC(1):
	case ABOX_SPUS_SBANK_ASRC(2):
	case ABOX_SPUS_SBANK_ASRC(3):
	case ABOX_SPUS_SBANK_ASRC(4):
	case ABOX_SPUS_SBANK_ASRC(5):
	case ABOX_SPUS_SBANK_ASRC(6):
	case ABOX_SPUS_SBANK_ASRC(7):
	case ABOX_SPUS_SBANK_MIXP:
	case ABOX_SPUS_CTRL_SIFS_CNT(0):
	case ABOX_SPUS_CTRL_SIFS_CNT(1):
	case ABOX_SPUM_CTRL0:
	case ABOX_SPUM_CTRL1:
	case ABOX_SPUM_CTRL2:
	case ABOX_SPUM_CTRL3:
	case ABOX_SPUM_SBANK_RSRC(0):
	case ABOX_SPUM_SBANK_RSRC(1):
	case ABOX_SPUM_SBANK_NSRC(0):
	case ABOX_SPUM_SBANK_NSRC(1):
	case ABOX_SPUM_SBANK_NSRC(2):
	case ABOX_SPUM_SBANK_NSRC(3):
	case ABOX_SPUM_SBANK_RECP:
	case ABOX_SPUM_SBANK_ASRC(0):
	case ABOX_SPUM_SBANK_ASRC(1):
	case ABOX_SPUM_SBANK_ASRC(2):
	case ABOX_SPUM_SBANK_ASRC(3):
	case ABOX_UAIF_CTRL0(0):
	case ABOX_UAIF_CTRL1(0):
	case ABOX_UAIF_STATUS(0):
	case ABOX_UAIF_CTRL0(1):
	case ABOX_UAIF_CTRL1(1):
	case ABOX_UAIF_STATUS(1):
	case ABOX_UAIF_CTRL0(2):
	case ABOX_UAIF_CTRL1(2):
	case ABOX_UAIF_STATUS(2):
	case ABOX_UAIF_CTRL0(3):
	case ABOX_UAIF_CTRL1(3):
	case ABOX_UAIF_STATUS(3):
	case ABOX_UAIF_CTRL0(4):
	case ABOX_UAIF_CTRL1(4):
	case ABOX_UAIF_STATUS(4):
	case ABOX_DSIF_CTRL:
	case ABOX_DSIF_STATUS:
	case ABOX_RDMA_CTRL0(0):
	case ABOX_RDMA_CTRL1(0):
	case ABOX_RDMA_BUF_STR(0):
	case ABOX_RDMA_BUF_END(0):
	case ABOX_RDMA_BUF_OFFSET(0):
	case ABOX_RDMA_STR_POINT(0):
	case ABOX_RDMA_VOL_FACTOR(0):
	case ABOX_RDMA_VOL_CHANGE(0):
	case ABOX_RDMA_SBANK_LIMIT(0):
	case ABOX_RDMA_STATUS(0):
	case ABOX_RDMA_CTRL0(1):
	case ABOX_RDMA_CTRL1(1):
	case ABOX_RDMA_BUF_STR(1):
	case ABOX_RDMA_BUF_END(1):
	case ABOX_RDMA_BUF_OFFSET(1):
	case ABOX_RDMA_STR_POINT(1):
	case ABOX_RDMA_VOL_FACTOR(1):
	case ABOX_RDMA_VOL_CHANGE(1):
	case ABOX_RDMA_SBANK_LIMIT(1):
	case ABOX_RDMA_STATUS(1):
	case ABOX_RDMA_CTRL0(2):
	case ABOX_RDMA_CTRL1(2):
	case ABOX_RDMA_BUF_STR(2):
	case ABOX_RDMA_BUF_END(2):
	case ABOX_RDMA_BUF_OFFSET(2):
	case ABOX_RDMA_STR_POINT(2):
	case ABOX_RDMA_VOL_FACTOR(2):
	case ABOX_RDMA_VOL_CHANGE(2):
	case ABOX_RDMA_SBANK_LIMIT(2):
	case ABOX_RDMA_STATUS(2):
	case ABOX_RDMA_CTRL0(3):
	case ABOX_RDMA_CTRL1(3):
	case ABOX_RDMA_BUF_STR(3):
	case ABOX_RDMA_BUF_END(3):
	case ABOX_RDMA_BUF_OFFSET(3):
	case ABOX_RDMA_STR_POINT(3):
	case ABOX_RDMA_VOL_FACTOR(3):
	case ABOX_RDMA_VOL_CHANGE(3):
	case ABOX_RDMA_SBANK_LIMIT(3):
	case ABOX_RDMA_STATUS(3):
	case ABOX_RDMA_CTRL0(4):
	case ABOX_RDMA_CTRL1(4):
	case ABOX_RDMA_BUF_STR(4):
	case ABOX_RDMA_BUF_END(4):
	case ABOX_RDMA_BUF_OFFSET(4):
	case ABOX_RDMA_STR_POINT(4):
	case ABOX_RDMA_VOL_FACTOR(4):
	case ABOX_RDMA_VOL_CHANGE(4):
	case ABOX_RDMA_SBANK_LIMIT(4):
	case ABOX_RDMA_STATUS(4):
	case ABOX_RDMA_CTRL0(5):
	case ABOX_RDMA_CTRL1(5):
	case ABOX_RDMA_BUF_STR(5):
	case ABOX_RDMA_BUF_END(5):
	case ABOX_RDMA_BUF_OFFSET(5):
	case ABOX_RDMA_STR_POINT(5):
	case ABOX_RDMA_VOL_FACTOR(5):
	case ABOX_RDMA_VOL_CHANGE(5):
	case ABOX_RDMA_SBANK_LIMIT(5):
	case ABOX_RDMA_STATUS(5):
	case ABOX_RDMA_CTRL0(6):
	case ABOX_RDMA_CTRL1(6):
	case ABOX_RDMA_BUF_STR(6):
	case ABOX_RDMA_BUF_END(6):
	case ABOX_RDMA_BUF_OFFSET(6):
	case ABOX_RDMA_STR_POINT(6):
	case ABOX_RDMA_VOL_FACTOR(6):
	case ABOX_RDMA_VOL_CHANGE(6):
	case ABOX_RDMA_SBANK_LIMIT(6):
	case ABOX_RDMA_STATUS(6):
	case ABOX_RDMA_CTRL0(7):
	case ABOX_RDMA_CTRL1(7):
	case ABOX_RDMA_BUF_STR(7):
	case ABOX_RDMA_BUF_END(7):
	case ABOX_RDMA_BUF_OFFSET(7):
	case ABOX_RDMA_STR_POINT(7):
	case ABOX_RDMA_VOL_FACTOR(7):
	case ABOX_RDMA_VOL_CHANGE(7):
	case ABOX_RDMA_SBANK_LIMIT(7):
	case ABOX_RDMA_STATUS(7):
	case ABOX_SPUS_ASRC_CTRL(0):
	case ABOX_SPUS_ASRC_IS_PARA0(0):
	case ABOX_SPUS_ASRC_IS_PARA1(0):
	case ABOX_SPUS_ASRC_OS_PARA0(0):
	case ABOX_SPUS_ASRC_OS_PARA1(0):
	case ABOX_SPUS_ASRC_DITHER_CTRL(0):
	case ABOX_SPUS_ASRC_SEED_IN(0):
	case ABOX_SPUS_ASRC_SEED_OUT(0):
	case ABOX_SPUS_ASRC_FILTER_CTRL(0):
	case ABOX_SPUS_ASRC_CTRL(1):
	case ABOX_SPUS_ASRC_IS_PARA0(1):
	case ABOX_SPUS_ASRC_IS_PARA1(1):
	case ABOX_SPUS_ASRC_OS_PARA0(1):
	case ABOX_SPUS_ASRC_OS_PARA1(1):
	case ABOX_SPUS_ASRC_DITHER_CTRL(1):
	case ABOX_SPUS_ASRC_SEED_IN(1):
	case ABOX_SPUS_ASRC_SEED_OUT(1):
	case ABOX_SPUS_ASRC_FILTER_CTRL(1):
	case ABOX_SPUS_ASRC_CTRL(2):
	case ABOX_SPUS_ASRC_IS_PARA0(2):
	case ABOX_SPUS_ASRC_IS_PARA1(2):
	case ABOX_SPUS_ASRC_OS_PARA0(2):
	case ABOX_SPUS_ASRC_OS_PARA1(2):
	case ABOX_SPUS_ASRC_DITHER_CTRL(2):
	case ABOX_SPUS_ASRC_SEED_IN(2):
	case ABOX_SPUS_ASRC_SEED_OUT(2):
	case ABOX_SPUS_ASRC_FILTER_CTRL(2):
	case ABOX_SPUS_ASRC_CTRL(3):
	case ABOX_SPUS_ASRC_IS_PARA0(3):
	case ABOX_SPUS_ASRC_IS_PARA1(3):
	case ABOX_SPUS_ASRC_OS_PARA0(3):
	case ABOX_SPUS_ASRC_OS_PARA1(3):
	case ABOX_SPUS_ASRC_DITHER_CTRL(3):
	case ABOX_SPUS_ASRC_SEED_IN(3):
	case ABOX_SPUS_ASRC_SEED_OUT(3):
	case ABOX_SPUS_ASRC_FILTER_CTRL(3):
	case ABOX_SPUS_ASRC_CTRL(4):
	case ABOX_SPUS_ASRC_IS_PARA0(4):
	case ABOX_SPUS_ASRC_IS_PARA1(4):
	case ABOX_SPUS_ASRC_OS_PARA0(4):
	case ABOX_SPUS_ASRC_OS_PARA1(4):
	case ABOX_SPUS_ASRC_DITHER_CTRL(4):
	case ABOX_SPUS_ASRC_SEED_IN(4):
	case ABOX_SPUS_ASRC_SEED_OUT(4):
	case ABOX_SPUS_ASRC_FILTER_CTRL(4):
	case ABOX_SPUS_ASRC_CTRL(5):
	case ABOX_SPUS_ASRC_IS_PARA0(5):
	case ABOX_SPUS_ASRC_IS_PARA1(5):
	case ABOX_SPUS_ASRC_OS_PARA0(5):
	case ABOX_SPUS_ASRC_OS_PARA1(5):
	case ABOX_SPUS_ASRC_DITHER_CTRL(5):
	case ABOX_SPUS_ASRC_SEED_IN(5):
	case ABOX_SPUS_ASRC_SEED_OUT(5):
	case ABOX_SPUS_ASRC_FILTER_CTRL(5):
	case ABOX_SPUS_ASRC_CTRL(6):
	case ABOX_SPUS_ASRC_IS_PARA0(6):
	case ABOX_SPUS_ASRC_IS_PARA1(6):
	case ABOX_SPUS_ASRC_OS_PARA0(6):
	case ABOX_SPUS_ASRC_OS_PARA1(6):
	case ABOX_SPUS_ASRC_DITHER_CTRL(6):
	case ABOX_SPUS_ASRC_SEED_IN(6):
	case ABOX_SPUS_ASRC_SEED_OUT(6):
	case ABOX_SPUS_ASRC_FILTER_CTRL(6):
	case ABOX_SPUS_ASRC_CTRL(7):
	case ABOX_SPUS_ASRC_IS_PARA0(7):
	case ABOX_SPUS_ASRC_IS_PARA1(7):
	case ABOX_SPUS_ASRC_OS_PARA0(7):
	case ABOX_SPUS_ASRC_OS_PARA1(7):
	case ABOX_SPUS_ASRC_DITHER_CTRL(7):
	case ABOX_SPUS_ASRC_SEED_IN(7):
	case ABOX_SPUS_ASRC_SEED_OUT(7):
	case ABOX_SPUS_ASRC_FILTER_CTRL(7):
	case ABOX_WDMA_CTRL(0):
	case ABOX_WDMA_BUF_STR(0):
	case ABOX_WDMA_BUF_END(0):
	case ABOX_WDMA_BUF_OFFSET(0):
	case ABOX_WDMA_STR_POINT(0):
	case ABOX_WDMA_VOL_FACTOR(0):
	case ABOX_WDMA_VOL_CHANGE(0):
	case ABOX_WDMA_SBANK_LIMIT(0):
	case ABOX_WDMA_STATUS(0):
	case ABOX_WDMA_CTRL(1):
	case ABOX_WDMA_BUF_STR(1):
	case ABOX_WDMA_BUF_END(1):
	case ABOX_WDMA_BUF_OFFSET(1):
	case ABOX_WDMA_STR_POINT(1):
	case ABOX_WDMA_VOL_FACTOR(1):
	case ABOX_WDMA_VOL_CHANGE(1):
	case ABOX_WDMA_SBANK_LIMIT(1):
	case ABOX_WDMA_STATUS(1):
	case ABOX_WDMA_CTRL(2):
	case ABOX_WDMA_BUF_STR(2):
	case ABOX_WDMA_BUF_END(2):
	case ABOX_WDMA_BUF_OFFSET(2):
	case ABOX_WDMA_STR_POINT(2):
	case ABOX_WDMA_VOL_FACTOR(2):
	case ABOX_WDMA_VOL_CHANGE(2):
	case ABOX_WDMA_SBANK_LIMIT(2):
	case ABOX_WDMA_STATUS(2):
	case ABOX_WDMA_CTRL(3):
	case ABOX_WDMA_BUF_STR(3):
	case ABOX_WDMA_BUF_END(3):
	case ABOX_WDMA_BUF_OFFSET(3):
	case ABOX_WDMA_STR_POINT(3):
	case ABOX_WDMA_VOL_FACTOR(3):
	case ABOX_WDMA_VOL_CHANGE(3):
	case ABOX_WDMA_SBANK_LIMIT(3):
	case ABOX_WDMA_STATUS(3):
	case ABOX_WDMA_CTRL(4):
	case ABOX_WDMA_BUF_STR(4):
	case ABOX_WDMA_BUF_END(4):
	case ABOX_WDMA_BUF_OFFSET(4):
	case ABOX_WDMA_STR_POINT(4):
	case ABOX_WDMA_VOL_FACTOR(4):
	case ABOX_WDMA_VOL_CHANGE(4):
	case ABOX_WDMA_SBANK_LIMIT(4):
	case ABOX_WDMA_STATUS(4):
	case ABOX_SPUM_ASRC_CTRL(0):
	case ABOX_SPUM_ASRC_IS_PARA0(0):
	case ABOX_SPUM_ASRC_IS_PARA1(0):
	case ABOX_SPUM_ASRC_OS_PARA0(0):
	case ABOX_SPUM_ASRC_OS_PARA1(0):
	case ABOX_SPUM_ASRC_DITHER_CTRL(0):
	case ABOX_SPUM_ASRC_SEED_IN(0):
	case ABOX_SPUM_ASRC_SEED_OUT(0):
	case ABOX_SPUM_ASRC_FILTER_CTRL(0):
	case ABOX_SPUM_ASRC_CTRL(1):
	case ABOX_SPUM_ASRC_IS_PARA0(1):
	case ABOX_SPUM_ASRC_IS_PARA1(1):
	case ABOX_SPUM_ASRC_OS_PARA0(1):
	case ABOX_SPUM_ASRC_OS_PARA1(1):
	case ABOX_SPUM_ASRC_DITHER_CTRL(1):
	case ABOX_SPUM_ASRC_SEED_IN(1):
	case ABOX_SPUM_ASRC_SEED_OUT(1):
	case ABOX_SPUM_ASRC_FILTER_CTRL(1):
	case ABOX_SPUM_ASRC_CTRL(2):
	case ABOX_SPUM_ASRC_IS_PARA0(2):
	case ABOX_SPUM_ASRC_IS_PARA1(2):
	case ABOX_SPUM_ASRC_OS_PARA0(2):
	case ABOX_SPUM_ASRC_OS_PARA1(2):
	case ABOX_SPUM_ASRC_DITHER_CTRL(2):
	case ABOX_SPUM_ASRC_SEED_IN(2):
	case ABOX_SPUM_ASRC_SEED_OUT(2):
	case ABOX_SPUM_ASRC_FILTER_CTRL(2):
	case ABOX_SPUM_ASRC_CTRL(3):
	case ABOX_SPUM_ASRC_IS_PARA0(3):
	case ABOX_SPUM_ASRC_IS_PARA1(3):
	case ABOX_SPUM_ASRC_OS_PARA0(3):
	case ABOX_SPUM_ASRC_OS_PARA1(3):
	case ABOX_SPUM_ASRC_DITHER_CTRL(3):
	case ABOX_SPUM_ASRC_SEED_IN(3):
	case ABOX_SPUM_ASRC_SEED_OUT(3):
	case ABOX_SPUM_ASRC_FILTER_CTRL(3):
	case ABOX_CA7_R(0):
	case ABOX_CA7_R(1):
	case ABOX_CA7_R(2):
	case ABOX_CA7_R(3):
	case ABOX_CA7_R(4):
	case ABOX_CA7_R(5):
	case ABOX_CA7_R(6):
	case ABOX_CA7_R(7):
	case ABOX_CA7_R(8):
	case ABOX_CA7_R(9):
	case ABOX_CA7_R(10):
	case ABOX_CA7_R(11):
	case ABOX_CA7_R(12):
	case ABOX_CA7_R(13):
	case ABOX_CA7_R(14):
	case ABOX_CA7_PC:
	case ABOX_COEF_2EVEN0(0):
	case ABOX_COEF_2EVEN1(0):
	case ABOX_COEF_2EVEN2(0):
	case ABOX_COEF_2EVEN3(0):
	case ABOX_COEF_2EVEN4(0):
	case ABOX_COEF_2EVEN5(0):
	case ABOX_COEF_2EVEN6(0):
	case ABOX_COEF_2EVEN7(0):
	case ABOX_COEF_2EVEN8(0):
	case ABOX_COEF_2EVEN9(0):
	case ABOX_COEF_2ODD0(0):
	case ABOX_COEF_2ODD1(0):
	case ABOX_COEF_2ODD2(0):
	case ABOX_COEF_2ODD3(0):
	case ABOX_COEF_2ODD4(0):
	case ABOX_COEF_2ODD5(0):
	case ABOX_COEF_2ODD6(0):
	case ABOX_COEF_2ODD7(0):
	case ABOX_COEF_2ODD8(0):
	case ABOX_COEF_4EVEN0(0):
	case ABOX_COEF_4EVEN1(0):
	case ABOX_COEF_4EVEN2(0):
	case ABOX_COEF_4ODD0(0):
	case ABOX_COEF_4ODD1(0):
	case ABOX_COEF_8EVEN0(0):
	case ABOX_COEF_8EVEN1(0):
	case ABOX_COEF_8EVEN2(0):
	case ABOX_COEF_8ODD0(0):
	case ABOX_COEF_8ODD1(0):
	case ABOX_COEF_2EVEN0(1):
	case ABOX_COEF_2EVEN1(1):
	case ABOX_COEF_2EVEN2(1):
	case ABOX_COEF_2EVEN3(1):
	case ABOX_COEF_2EVEN4(1):
	case ABOX_COEF_2EVEN5(1):
	case ABOX_COEF_2EVEN6(1):
	case ABOX_COEF_2EVEN7(1):
	case ABOX_COEF_2EVEN8(1):
	case ABOX_COEF_2EVEN9(1):
	case ABOX_COEF_2ODD0(1):
	case ABOX_COEF_2ODD1(1):
	case ABOX_COEF_2ODD2(1):
	case ABOX_COEF_2ODD3(1):
	case ABOX_COEF_2ODD4(1):
	case ABOX_COEF_2ODD5(1):
	case ABOX_COEF_2ODD6(1):
	case ABOX_COEF_2ODD7(1):
	case ABOX_COEF_2ODD8(1):
	case ABOX_COEF_4EVEN0(1):
	case ABOX_COEF_4EVEN1(1):
	case ABOX_COEF_4EVEN2(1):
	case ABOX_COEF_4ODD0(1):
	case ABOX_COEF_4ODD1(1):
	case ABOX_COEF_8EVEN0(1):
	case ABOX_COEF_8EVEN1(1):
	case ABOX_COEF_8EVEN2(1):
	case ABOX_COEF_8ODD0(1):
	case ABOX_COEF_8ODD1(1):
		return true;
	default:
		return false;
	}
}

static bool writeable_reg_legacy(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case ABOX_SYSPOWER_CTRL:
	case ABOX_SYSTEM_CONFIG0:
	case ABOX_REMAP_MASK:
	case ABOX_REMAP_ADDR:
	case ABOX_DYN_CLOCK_OFF:
	case ABOX_QCHANNEL_DISABLE:
	case ABOX_ROUTE_CTRL0:
	case ABOX_ROUTE_CTRL1:
	case ABOX_ROUTE_CTRL2:
	case ABOX_SPUS_CTRL0:
	case ABOX_SPUS_CTRL1:
	case ABOX_SPUS_CTRL2:
	case ABOX_SPUS_CTRL3:
	case ABOX_SPUS_SBANK_RDMA(0):
	case ABOX_SPUS_SBANK_RDMA(1):
	case ABOX_SPUS_SBANK_RDMA(2):
	case ABOX_SPUS_SBANK_RDMA(3):
	case ABOX_SPUS_SBANK_RDMA(4):
	case ABOX_SPUS_SBANK_RDMA(5):
	case ABOX_SPUS_SBANK_RDMA(6):
	case ABOX_SPUS_SBANK_RDMA(7):
	case ABOX_SPUS_SBANK_ASRC(0):
	case ABOX_SPUS_SBANK_ASRC(1):
	case ABOX_SPUS_SBANK_ASRC(2):
	case ABOX_SPUS_SBANK_ASRC(3):
	case ABOX_SPUS_SBANK_ASRC(4):
	case ABOX_SPUS_SBANK_ASRC(5):
	case ABOX_SPUS_SBANK_ASRC(6):
	case ABOX_SPUS_SBANK_ASRC(7):
	case ABOX_SPUS_SBANK_MIXP:
	case ABOX_SPUS_CTRL_SIFS_CNT(0):
	case ABOX_SPUS_CTRL_SIFS_CNT(1):
	case ABOX_SPUM_CTRL0:
	case ABOX_SPUM_CTRL1:
	case ABOX_SPUM_CTRL2:
	case ABOX_SPUM_CTRL3:
	case ABOX_SPUM_SBANK_RSRC(0):
	case ABOX_SPUM_SBANK_RSRC(1):
	case ABOX_SPUM_SBANK_NSRC(0):
	case ABOX_SPUM_SBANK_NSRC(1):
	case ABOX_SPUM_SBANK_NSRC(2):
	case ABOX_SPUM_SBANK_NSRC(3):
	case ABOX_SPUM_SBANK_RECP:
	case ABOX_SPUM_SBANK_ASRC(0):
	case ABOX_SPUM_SBANK_ASRC(1):
	case ABOX_SPUM_SBANK_ASRC(2):
	case ABOX_SPUM_SBANK_ASRC(3):
	case ABOX_UAIF_CTRL0(0):
	case ABOX_UAIF_CTRL1(0):
	case ABOX_UAIF_CTRL0(1):
	case ABOX_UAIF_CTRL1(1):
	case ABOX_UAIF_CTRL0(2):
	case ABOX_UAIF_CTRL1(2):
	case ABOX_UAIF_CTRL0(3):
	case ABOX_UAIF_CTRL1(3):
	case ABOX_UAIF_CTRL0(4):
	case ABOX_UAIF_CTRL1(4):
	case ABOX_DSIF_CTRL:
	case ABOX_RDMA_CTRL0(0):
	case ABOX_RDMA_CTRL1(0):
	case ABOX_RDMA_BUF_STR(0):
	case ABOX_RDMA_BUF_END(0):
	case ABOX_RDMA_BUF_OFFSET(0):
	case ABOX_RDMA_STR_POINT(0):
	case ABOX_RDMA_VOL_FACTOR(0):
	case ABOX_RDMA_VOL_CHANGE(0):
	case ABOX_RDMA_SBANK_LIMIT(0):
	case ABOX_RDMA_CTRL0(1):
	case ABOX_RDMA_CTRL1(1):
	case ABOX_RDMA_BUF_STR(1):
	case ABOX_RDMA_BUF_END(1):
	case ABOX_RDMA_BUF_OFFSET(1):
	case ABOX_RDMA_STR_POINT(1):
	case ABOX_RDMA_VOL_FACTOR(1):
	case ABOX_RDMA_VOL_CHANGE(1):
	case ABOX_RDMA_SBANK_LIMIT(1):
	case ABOX_RDMA_CTRL0(2):
	case ABOX_RDMA_CTRL1(2):
	case ABOX_RDMA_BUF_STR(2):
	case ABOX_RDMA_BUF_END(2):
	case ABOX_RDMA_BUF_OFFSET(2):
	case ABOX_RDMA_STR_POINT(2):
	case ABOX_RDMA_VOL_FACTOR(2):
	case ABOX_RDMA_VOL_CHANGE(2):
	case ABOX_RDMA_SBANK_LIMIT(2):
	case ABOX_RDMA_CTRL0(3):
	case ABOX_RDMA_CTRL1(3):
	case ABOX_RDMA_BUF_STR(3):
	case ABOX_RDMA_BUF_END(3):
	case ABOX_RDMA_BUF_OFFSET(3):
	case ABOX_RDMA_STR_POINT(3):
	case ABOX_RDMA_VOL_FACTOR(3):
	case ABOX_RDMA_VOL_CHANGE(3):
	case ABOX_RDMA_SBANK_LIMIT(3):
	case ABOX_RDMA_CTRL0(4):
	case ABOX_RDMA_CTRL1(4):
	case ABOX_RDMA_STR_POINT(4):
	case ABOX_RDMA_VOL_FACTOR(4):
	case ABOX_RDMA_VOL_CHANGE(4):
	case ABOX_RDMA_SBANK_LIMIT(4):
	case ABOX_RDMA_CTRL0(5):
	case ABOX_RDMA_CTRL1(5):
	case ABOX_RDMA_BUF_STR(5):
	case ABOX_RDMA_BUF_END(5):
	case ABOX_RDMA_BUF_OFFSET(5):
	case ABOX_RDMA_STR_POINT(5):
	case ABOX_RDMA_VOL_FACTOR(5):
	case ABOX_RDMA_VOL_CHANGE(5):
	case ABOX_RDMA_SBANK_LIMIT(5):
	case ABOX_RDMA_CTRL0(6):
	case ABOX_RDMA_CTRL1(6):
	case ABOX_RDMA_BUF_STR(6):
	case ABOX_RDMA_BUF_END(6):
	case ABOX_RDMA_BUF_OFFSET(6):
	case ABOX_RDMA_STR_POINT(6):
	case ABOX_RDMA_VOL_FACTOR(6):
	case ABOX_RDMA_VOL_CHANGE(6):
	case ABOX_RDMA_SBANK_LIMIT(6):
	case ABOX_RDMA_CTRL0(7):
	case ABOX_RDMA_CTRL1(7):
	case ABOX_RDMA_BUF_STR(7):
	case ABOX_RDMA_BUF_END(7):
	case ABOX_RDMA_BUF_OFFSET(7):
	case ABOX_RDMA_STR_POINT(7):
	case ABOX_RDMA_VOL_FACTOR(7):
	case ABOX_RDMA_VOL_CHANGE(7):
	case ABOX_RDMA_SBANK_LIMIT(7):
	case ABOX_SPUS_ASRC_CTRL(0):
	case ABOX_SPUS_ASRC_IS_PARA0(0):
	case ABOX_SPUS_ASRC_IS_PARA1(0):
	case ABOX_SPUS_ASRC_OS_PARA0(0):
	case ABOX_SPUS_ASRC_OS_PARA1(0):
	case ABOX_SPUS_ASRC_DITHER_CTRL(0):
	case ABOX_SPUS_ASRC_SEED_IN(0):
	case ABOX_SPUS_ASRC_SEED_OUT(0):
	case ABOX_SPUS_ASRC_FILTER_CTRL(0):
	case ABOX_SPUS_ASRC_CTRL(1):
	case ABOX_SPUS_ASRC_IS_PARA0(1):
	case ABOX_SPUS_ASRC_IS_PARA1(1):
	case ABOX_SPUS_ASRC_OS_PARA0(1):
	case ABOX_SPUS_ASRC_OS_PARA1(1):
	case ABOX_SPUS_ASRC_DITHER_CTRL(1):
	case ABOX_SPUS_ASRC_SEED_IN(1):
	case ABOX_SPUS_ASRC_SEED_OUT(1):
	case ABOX_SPUS_ASRC_FILTER_CTRL(1):
	case ABOX_SPUS_ASRC_CTRL(2):
	case ABOX_SPUS_ASRC_IS_PARA0(2):
	case ABOX_SPUS_ASRC_IS_PARA1(2):
	case ABOX_SPUS_ASRC_OS_PARA0(2):
	case ABOX_SPUS_ASRC_OS_PARA1(2):
	case ABOX_SPUS_ASRC_DITHER_CTRL(2):
	case ABOX_SPUS_ASRC_SEED_IN(2):
	case ABOX_SPUS_ASRC_SEED_OUT(2):
	case ABOX_SPUS_ASRC_FILTER_CTRL(2):
	case ABOX_SPUS_ASRC_CTRL(3):
	case ABOX_SPUS_ASRC_IS_PARA0(3):
	case ABOX_SPUS_ASRC_IS_PARA1(3):
	case ABOX_SPUS_ASRC_OS_PARA0(3):
	case ABOX_SPUS_ASRC_OS_PARA1(3):
	case ABOX_SPUS_ASRC_DITHER_CTRL(3):
	case ABOX_SPUS_ASRC_SEED_IN(3):
	case ABOX_SPUS_ASRC_SEED_OUT(3):
	case ABOX_SPUS_ASRC_FILTER_CTRL(3):
	case ABOX_SPUS_ASRC_CTRL(4):
	case ABOX_SPUS_ASRC_IS_PARA0(4):
	case ABOX_SPUS_ASRC_IS_PARA1(4):
	case ABOX_SPUS_ASRC_OS_PARA0(4):
	case ABOX_SPUS_ASRC_OS_PARA1(4):
	case ABOX_SPUS_ASRC_DITHER_CTRL(4):
	case ABOX_SPUS_ASRC_SEED_IN(4):
	case ABOX_SPUS_ASRC_SEED_OUT(4):
	case ABOX_SPUS_ASRC_FILTER_CTRL(4):
	case ABOX_SPUS_ASRC_CTRL(5):
	case ABOX_SPUS_ASRC_IS_PARA0(5):
	case ABOX_SPUS_ASRC_IS_PARA1(5):
	case ABOX_SPUS_ASRC_OS_PARA0(5):
	case ABOX_SPUS_ASRC_OS_PARA1(5):
	case ABOX_SPUS_ASRC_DITHER_CTRL(5):
	case ABOX_SPUS_ASRC_SEED_IN(5):
	case ABOX_SPUS_ASRC_SEED_OUT(5):
	case ABOX_SPUS_ASRC_FILTER_CTRL(5):
	case ABOX_SPUS_ASRC_CTRL(6):
	case ABOX_SPUS_ASRC_IS_PARA0(6):
	case ABOX_SPUS_ASRC_IS_PARA1(6):
	case ABOX_SPUS_ASRC_OS_PARA0(6):
	case ABOX_SPUS_ASRC_OS_PARA1(6):
	case ABOX_SPUS_ASRC_DITHER_CTRL(6):
	case ABOX_SPUS_ASRC_SEED_IN(6):
	case ABOX_SPUS_ASRC_SEED_OUT(6):
	case ABOX_SPUS_ASRC_FILTER_CTRL(6):
	case ABOX_SPUS_ASRC_CTRL(7):
	case ABOX_SPUS_ASRC_IS_PARA0(7):
	case ABOX_SPUS_ASRC_IS_PARA1(7):
	case ABOX_SPUS_ASRC_OS_PARA0(7):
	case ABOX_SPUS_ASRC_OS_PARA1(7):
	case ABOX_SPUS_ASRC_DITHER_CTRL(7):
	case ABOX_SPUS_ASRC_SEED_IN(7):
	case ABOX_SPUS_ASRC_SEED_OUT(7):
	case ABOX_SPUS_ASRC_FILTER_CTRL(7):
	case ABOX_WDMA_CTRL(0):
	case ABOX_WDMA_BUF_STR(0):
	case ABOX_WDMA_BUF_END(0):
	case ABOX_WDMA_BUF_OFFSET(0):
	case ABOX_WDMA_STR_POINT(0):
	case ABOX_WDMA_VOL_FACTOR(0):
	case ABOX_WDMA_VOL_CHANGE(0):
	case ABOX_WDMA_SBANK_LIMIT(0):
	case ABOX_WDMA_CTRL(1):
	case ABOX_WDMA_BUF_STR(1):
	case ABOX_WDMA_BUF_END(1):
	case ABOX_WDMA_BUF_OFFSET(1):
	case ABOX_WDMA_STR_POINT(1):
	case ABOX_WDMA_VOL_FACTOR(1):
	case ABOX_WDMA_VOL_CHANGE(1):
	case ABOX_WDMA_SBANK_LIMIT(1):
	case ABOX_WDMA_CTRL(2):
	case ABOX_WDMA_BUF_STR(2):
	case ABOX_WDMA_BUF_END(2):
	case ABOX_WDMA_BUF_OFFSET(2):
	case ABOX_WDMA_STR_POINT(2):
	case ABOX_WDMA_VOL_FACTOR(2):
	case ABOX_WDMA_VOL_CHANGE(2):
	case ABOX_WDMA_SBANK_LIMIT(2):
	case ABOX_WDMA_CTRL(3):
	case ABOX_WDMA_BUF_STR(3):
	case ABOX_WDMA_BUF_END(3):
	case ABOX_WDMA_BUF_OFFSET(3):
	case ABOX_WDMA_STR_POINT(3):
	case ABOX_WDMA_VOL_FACTOR(3):
	case ABOX_WDMA_VOL_CHANGE(3):
	case ABOX_WDMA_SBANK_LIMIT(3):
	case ABOX_WDMA_CTRL(4):
	case ABOX_WDMA_BUF_STR(4):
	case ABOX_WDMA_BUF_END(4):
	case ABOX_WDMA_BUF_OFFSET(4):
	case ABOX_WDMA_STR_POINT(4):
	case ABOX_WDMA_VOL_FACTOR(4):
	case ABOX_WDMA_VOL_CHANGE(4):
	case ABOX_WDMA_SBANK_LIMIT(4):
	case ABOX_SPUM_ASRC_CTRL(0):
	case ABOX_SPUM_ASRC_IS_PARA0(0):
	case ABOX_SPUM_ASRC_IS_PARA1(0):
	case ABOX_SPUM_ASRC_OS_PARA0(0):
	case ABOX_SPUM_ASRC_OS_PARA1(0):
	case ABOX_SPUM_ASRC_DITHER_CTRL(0):
	case ABOX_SPUM_ASRC_SEED_IN(0):
	case ABOX_SPUM_ASRC_SEED_OUT(0):
	case ABOX_SPUM_ASRC_FILTER_CTRL(0):
	case ABOX_SPUM_ASRC_CTRL(1):
	case ABOX_SPUM_ASRC_IS_PARA0(1):
	case ABOX_SPUM_ASRC_IS_PARA1(1):
	case ABOX_SPUM_ASRC_OS_PARA0(1):
	case ABOX_SPUM_ASRC_OS_PARA1(1):
	case ABOX_SPUM_ASRC_DITHER_CTRL(1):
	case ABOX_SPUM_ASRC_SEED_IN(1):
	case ABOX_SPUM_ASRC_SEED_OUT(1):
	case ABOX_SPUM_ASRC_FILTER_CTRL(1):
	case ABOX_SPUM_ASRC_CTRL(2):
	case ABOX_SPUM_ASRC_IS_PARA0(2):
	case ABOX_SPUM_ASRC_IS_PARA1(2):
	case ABOX_SPUM_ASRC_OS_PARA0(2):
	case ABOX_SPUM_ASRC_OS_PARA1(2):
	case ABOX_SPUM_ASRC_DITHER_CTRL(2):
	case ABOX_SPUM_ASRC_SEED_IN(2):
	case ABOX_SPUM_ASRC_SEED_OUT(2):
	case ABOX_SPUM_ASRC_FILTER_CTRL(2):
	case ABOX_SPUM_ASRC_CTRL(3):
	case ABOX_SPUM_ASRC_IS_PARA0(3):
	case ABOX_SPUM_ASRC_IS_PARA1(3):
	case ABOX_SPUM_ASRC_OS_PARA0(3):
	case ABOX_SPUM_ASRC_OS_PARA1(3):
	case ABOX_SPUM_ASRC_DITHER_CTRL(3):
	case ABOX_SPUM_ASRC_SEED_IN(3):
	case ABOX_SPUM_ASRC_SEED_OUT(3):
	case ABOX_SPUM_ASRC_FILTER_CTRL(3):
		return true;
	default:
		return false;
	}
}

static bool volatile_reg_9820(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case ABOX_RDMA_CTRL1(8):
	case ABOX_RDMA_STATUS(8):
	case ABOX_RDMA_CTRL1(9):
	case ABOX_RDMA_STATUS(9):
	case ABOX_RDMA_CTRL1(10):
	case ABOX_RDMA_STATUS(10):
	case ABOX_RDMA_CTRL1(11):
	case ABOX_RDMA_STATUS(11):
	case ABOX_WDMA_STATUS(5):
	case ABOX_WDMA_STATUS(6):
	case ABOX_WDMA_STATUS(7):
	case ABOX_CA32_CORE0_R(0):
	case ABOX_CA32_CORE0_R(1):
	case ABOX_CA32_CORE0_R(2):
	case ABOX_CA32_CORE0_R(3):
	case ABOX_CA32_CORE0_R(4):
	case ABOX_CA32_CORE0_R(5):
	case ABOX_CA32_CORE0_R(6):
	case ABOX_CA32_CORE0_R(7):
	case ABOX_CA32_CORE0_R(8):
	case ABOX_CA32_CORE0_R(9):
	case ABOX_CA32_CORE0_R(10):
	case ABOX_CA32_CORE0_R(11):
	case ABOX_CA32_CORE0_R(12):
	case ABOX_CA32_CORE0_R(13):
	case ABOX_CA32_CORE0_R(14):
	case ABOX_CA32_CORE0_R(15):
	case ABOX_CA32_CORE0_R(16):
	case ABOX_CA32_CORE0_R(17):
	case ABOX_CA32_CORE0_R(18):
	case ABOX_CA32_CORE0_R(19):
	case ABOX_CA32_CORE0_R(20):
	case ABOX_CA32_CORE0_R(21):
	case ABOX_CA32_CORE0_R(22):
	case ABOX_CA32_CORE0_R(23):
	case ABOX_CA32_CORE0_R(24):
	case ABOX_CA32_CORE0_R(25):
	case ABOX_CA32_CORE0_R(26):
	case ABOX_CA32_CORE0_R(27):
	case ABOX_CA32_CORE0_R(28):
	case ABOX_CA32_CORE0_R(29):
	case ABOX_CA32_CORE0_R(30):
	case ABOX_CA32_CORE0_PC:
	case ABOX_CA32_CORE1_R(0):
	case ABOX_CA32_CORE1_R(1):
	case ABOX_CA32_CORE1_R(2):
	case ABOX_CA32_CORE1_R(3):
	case ABOX_CA32_CORE1_R(4):
	case ABOX_CA32_CORE1_R(5):
	case ABOX_CA32_CORE1_R(6):
	case ABOX_CA32_CORE1_R(7):
	case ABOX_CA32_CORE1_R(8):
	case ABOX_CA32_CORE1_R(9):
	case ABOX_CA32_CORE1_R(10):
	case ABOX_CA32_CORE1_R(11):
	case ABOX_CA32_CORE1_R(12):
	case ABOX_CA32_CORE1_R(13):
	case ABOX_CA32_CORE1_R(14):
	case ABOX_CA32_CORE1_R(15):
	case ABOX_CA32_CORE1_R(16):
	case ABOX_CA32_CORE1_R(17):
	case ABOX_CA32_CORE1_R(18):
	case ABOX_CA32_CORE1_R(19):
	case ABOX_CA32_CORE1_R(20):
	case ABOX_CA32_CORE1_R(21):
	case ABOX_CA32_CORE1_R(22):
	case ABOX_CA32_CORE1_R(23):
	case ABOX_CA32_CORE1_R(24):
	case ABOX_CA32_CORE1_R(25):
	case ABOX_CA32_CORE1_R(26):
	case ABOX_CA32_CORE1_R(27):
	case ABOX_CA32_CORE1_R(28):
	case ABOX_CA32_CORE1_R(29):
	case ABOX_CA32_CORE1_R(30):
	case ABOX_CA32_CORE1_PC:
	case ABOX_CA32_STATUS:
		return true;
	default:
		return volatile_reg_legacy(dev, reg);
	}
}

static bool readable_reg_9820(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case ABOX_DYN_CLOCK_OFF1:
	case ABOX_TICK_DIV_RATIO:
	case ABOX_MO_CTRL:
	case ABOX_SPUS_CTRL4:
	case ABOX_SPUS_CTRL5:
	case ABOX_SPUS_CTRL_FC1:
	case ABOX_SPUS_SBANK_RDMA(8):
	case ABOX_SPUS_SBANK_RDMA(9):
	case ABOX_SPUS_SBANK_RDMA(10):
	case ABOX_SPUS_SBANK_RDMA(11):
	case ABOX_SPUS_SBANK_ASRC(8):
	case ABOX_SPUS_SBANK_ASRC(9):
	case ABOX_SPUS_SBANK_ASRC(10):
	case ABOX_SPUS_SBANK_ASRC(11):
	case ABOX_SPUS_CTRL_SIFS_CNT(2):
	case ABOX_SPUS_CTRL_SIFS_CNT(3):
	case ABOX_SPUS_CTRL_SIFS_CNT(4):
	case ABOX_SPUM_CTRL4:
	case ABOX_SPUM_SBANK_NSRC(4):
	case ABOX_SPUM_SBANK_NSRC(5):
	case ABOX_SPUM_SBANK_NSRC(6):
	case ABOX_SPUM_SBANK_ASRC(4):
	case ABOX_SPUM_SBANK_ASRC(5):
	case ABOX_SPUM_SBANK_ASRC(6):
	case ABOX_SPUM_SBANK_ASRC(7):
	case ABOX_RDMA_CTRL0(8):
	case ABOX_RDMA_CTRL1(8):
	case ABOX_RDMA_BUF_STR(8):
	case ABOX_RDMA_BUF_END(8):
	case ABOX_RDMA_BUF_OFFSET(8):
	case ABOX_RDMA_STR_POINT(8):
	case ABOX_RDMA_VOL_FACTOR(8):
	case ABOX_RDMA_VOL_CHANGE(8):
	case ABOX_RDMA_SBANK_LIMIT(8):
	case ABOX_RDMA_STATUS(8):
	case ABOX_RDMA_CTRL0(9):
	case ABOX_RDMA_CTRL1(9):
	case ABOX_RDMA_BUF_STR(9):
	case ABOX_RDMA_BUF_END(9):
	case ABOX_RDMA_BUF_OFFSET(9):
	case ABOX_RDMA_STR_POINT(9):
	case ABOX_RDMA_VOL_FACTOR(9):
	case ABOX_RDMA_VOL_CHANGE(9):
	case ABOX_RDMA_SBANK_LIMIT(9):
	case ABOX_RDMA_STATUS(9):
	case ABOX_RDMA_CTRL0(10):
	case ABOX_RDMA_CTRL1(10):
	case ABOX_RDMA_BUF_STR(10):
	case ABOX_RDMA_BUF_END(10):
	case ABOX_RDMA_BUF_OFFSET(10):
	case ABOX_RDMA_STR_POINT(10):
	case ABOX_RDMA_VOL_FACTOR(10):
	case ABOX_RDMA_VOL_CHANGE(10):
	case ABOX_RDMA_SBANK_LIMIT(10):
	case ABOX_RDMA_STATUS(10):
	case ABOX_RDMA_CTRL0(11):
	case ABOX_RDMA_CTRL1(11):
	case ABOX_RDMA_BUF_STR(11):
	case ABOX_RDMA_BUF_END(11):
	case ABOX_RDMA_BUF_OFFSET(11):
	case ABOX_RDMA_STR_POINT(11):
	case ABOX_RDMA_VOL_FACTOR(11):
	case ABOX_RDMA_VOL_CHANGE(11):
	case ABOX_RDMA_SBANK_LIMIT(11):
	case ABOX_RDMA_STATUS(11):
	case ABOX_SPUS_ASRC_CTRL(8):
	case ABOX_SPUS_ASRC_IS_PARA0(8):
	case ABOX_SPUS_ASRC_IS_PARA1(8):
	case ABOX_SPUS_ASRC_OS_PARA0(8):
	case ABOX_SPUS_ASRC_OS_PARA1(8):
	case ABOX_SPUS_ASRC_DITHER_CTRL(8):
	case ABOX_SPUS_ASRC_SEED_IN(8):
	case ABOX_SPUS_ASRC_SEED_OUT(8):
	case ABOX_SPUS_ASRC_FILTER_CTRL(8):
	case ABOX_SPUS_ASRC_CTRL(9):
	case ABOX_SPUS_ASRC_IS_PARA0(9):
	case ABOX_SPUS_ASRC_IS_PARA1(9):
	case ABOX_SPUS_ASRC_OS_PARA0(9):
	case ABOX_SPUS_ASRC_OS_PARA1(9):
	case ABOX_SPUS_ASRC_DITHER_CTRL(9):
	case ABOX_SPUS_ASRC_SEED_IN(9):
	case ABOX_SPUS_ASRC_SEED_OUT(9):
	case ABOX_SPUS_ASRC_FILTER_CTRL(9):
	case ABOX_SPUS_ASRC_CTRL(10):
	case ABOX_SPUS_ASRC_IS_PARA0(10):
	case ABOX_SPUS_ASRC_IS_PARA1(10):
	case ABOX_SPUS_ASRC_OS_PARA0(10):
	case ABOX_SPUS_ASRC_OS_PARA1(10):
	case ABOX_SPUS_ASRC_DITHER_CTRL(10):
	case ABOX_SPUS_ASRC_SEED_IN(10):
	case ABOX_SPUS_ASRC_SEED_OUT(10):
	case ABOX_SPUS_ASRC_FILTER_CTRL(10):
	case ABOX_SPUS_ASRC_CTRL(11):
	case ABOX_SPUS_ASRC_IS_PARA0(11):
	case ABOX_SPUS_ASRC_IS_PARA1(11):
	case ABOX_SPUS_ASRC_OS_PARA0(11):
	case ABOX_SPUS_ASRC_OS_PARA1(11):
	case ABOX_SPUS_ASRC_DITHER_CTRL(11):
	case ABOX_SPUS_ASRC_SEED_IN(11):
	case ABOX_SPUS_ASRC_SEED_OUT(11):
	case ABOX_SPUS_ASRC_FILTER_CTRL(11):
	case ABOX_WDMA_CTRL(5):
	case ABOX_WDMA_BUF_STR(5):
	case ABOX_WDMA_BUF_END(5):
	case ABOX_WDMA_BUF_OFFSET(5):
	case ABOX_WDMA_STR_POINT(5):
	case ABOX_WDMA_VOL_FACTOR(5):
	case ABOX_WDMA_VOL_CHANGE(5):
	case ABOX_WDMA_SBANK_LIMIT(5):
	case ABOX_WDMA_STATUS(5):
	case ABOX_WDMA_CTRL(6):
	case ABOX_WDMA_BUF_STR(6):
	case ABOX_WDMA_BUF_END(6):
	case ABOX_WDMA_BUF_OFFSET(6):
	case ABOX_WDMA_STR_POINT(6):
	case ABOX_WDMA_VOL_FACTOR(6):
	case ABOX_WDMA_VOL_CHANGE(6):
	case ABOX_WDMA_SBANK_LIMIT(6):
	case ABOX_WDMA_STATUS(6):
	case ABOX_WDMA_CTRL(7):
	case ABOX_WDMA_BUF_STR(7):
	case ABOX_WDMA_BUF_END(7):
	case ABOX_WDMA_BUF_OFFSET(7):
	case ABOX_WDMA_STR_POINT(7):
	case ABOX_WDMA_VOL_FACTOR(7):
	case ABOX_WDMA_VOL_CHANGE(7):
	case ABOX_WDMA_SBANK_LIMIT(7):
	case ABOX_WDMA_STATUS(7):
	case ABOX_SPUM_ASRC_CTRL(4):
	case ABOX_SPUM_ASRC_IS_PARA0(4):
	case ABOX_SPUM_ASRC_IS_PARA1(4):
	case ABOX_SPUM_ASRC_OS_PARA0(4):
	case ABOX_SPUM_ASRC_OS_PARA1(4):
	case ABOX_SPUM_ASRC_DITHER_CTRL(4):
	case ABOX_SPUM_ASRC_SEED_IN(4):
	case ABOX_SPUM_ASRC_SEED_OUT(4):
	case ABOX_SPUM_ASRC_FILTER_CTRL(4):
	case ABOX_SPUM_ASRC_CTRL(5):
	case ABOX_SPUM_ASRC_IS_PARA0(5):
	case ABOX_SPUM_ASRC_IS_PARA1(5):
	case ABOX_SPUM_ASRC_OS_PARA0(5):
	case ABOX_SPUM_ASRC_OS_PARA1(5):
	case ABOX_SPUM_ASRC_DITHER_CTRL(5):
	case ABOX_SPUM_ASRC_SEED_IN(5):
	case ABOX_SPUM_ASRC_SEED_OUT(5):
	case ABOX_SPUM_ASRC_FILTER_CTRL(5):
	case ABOX_SPUM_ASRC_CTRL(6):
	case ABOX_SPUM_ASRC_IS_PARA0(6):
	case ABOX_SPUM_ASRC_IS_PARA1(6):
	case ABOX_SPUM_ASRC_OS_PARA0(6):
	case ABOX_SPUM_ASRC_OS_PARA1(6):
	case ABOX_SPUM_ASRC_DITHER_CTRL(6):
	case ABOX_SPUM_ASRC_SEED_IN(6):
	case ABOX_SPUM_ASRC_SEED_OUT(6):
	case ABOX_SPUM_ASRC_FILTER_CTRL(6):
	case ABOX_SPUM_ASRC_CTRL(7):
	case ABOX_SPUM_ASRC_IS_PARA0(7):
	case ABOX_SPUM_ASRC_IS_PARA1(7):
	case ABOX_SPUM_ASRC_OS_PARA0(7):
	case ABOX_SPUM_ASRC_OS_PARA1(7):
	case ABOX_SPUM_ASRC_DITHER_CTRL(7):
	case ABOX_SPUM_ASRC_SEED_IN(7):
	case ABOX_SPUM_ASRC_SEED_OUT(7):
	case ABOX_SPUM_ASRC_FILTER_CTRL(7):
	case ABOX_CA32_CORE0_R(0):
	case ABOX_CA32_CORE0_R(1):
	case ABOX_CA32_CORE0_R(2):
	case ABOX_CA32_CORE0_R(3):
	case ABOX_CA32_CORE0_R(4):
	case ABOX_CA32_CORE0_R(5):
	case ABOX_CA32_CORE0_R(6):
	case ABOX_CA32_CORE0_R(7):
	case ABOX_CA32_CORE0_R(8):
	case ABOX_CA32_CORE0_R(9):
	case ABOX_CA32_CORE0_R(10):
	case ABOX_CA32_CORE0_R(11):
	case ABOX_CA32_CORE0_R(12):
	case ABOX_CA32_CORE0_R(13):
	case ABOX_CA32_CORE0_R(14):
	case ABOX_CA32_CORE0_R(15):
	case ABOX_CA32_CORE0_R(16):
	case ABOX_CA32_CORE0_R(17):
	case ABOX_CA32_CORE0_R(18):
	case ABOX_CA32_CORE0_R(19):
	case ABOX_CA32_CORE0_R(20):
	case ABOX_CA32_CORE0_R(21):
	case ABOX_CA32_CORE0_R(22):
	case ABOX_CA32_CORE0_R(23):
	case ABOX_CA32_CORE0_R(24):
	case ABOX_CA32_CORE0_R(25):
	case ABOX_CA32_CORE0_R(26):
	case ABOX_CA32_CORE0_R(27):
	case ABOX_CA32_CORE0_R(28):
	case ABOX_CA32_CORE0_R(29):
	case ABOX_CA32_CORE0_R(30):
	case ABOX_CA32_CORE0_PC:
	case ABOX_CA32_CORE1_R(0):
	case ABOX_CA32_CORE1_R(1):
	case ABOX_CA32_CORE1_R(2):
	case ABOX_CA32_CORE1_R(3):
	case ABOX_CA32_CORE1_R(4):
	case ABOX_CA32_CORE1_R(5):
	case ABOX_CA32_CORE1_R(6):
	case ABOX_CA32_CORE1_R(7):
	case ABOX_CA32_CORE1_R(8):
	case ABOX_CA32_CORE1_R(9):
	case ABOX_CA32_CORE1_R(10):
	case ABOX_CA32_CORE1_R(11):
	case ABOX_CA32_CORE1_R(12):
	case ABOX_CA32_CORE1_R(13):
	case ABOX_CA32_CORE1_R(14):
	case ABOX_CA32_CORE1_R(15):
	case ABOX_CA32_CORE1_R(16):
	case ABOX_CA32_CORE1_R(17):
	case ABOX_CA32_CORE1_R(18):
	case ABOX_CA32_CORE1_R(19):
	case ABOX_CA32_CORE1_R(20):
	case ABOX_CA32_CORE1_R(21):
	case ABOX_CA32_CORE1_R(22):
	case ABOX_CA32_CORE1_R(23):
	case ABOX_CA32_CORE1_R(24):
	case ABOX_CA32_CORE1_R(25):
	case ABOX_CA32_CORE1_R(26):
	case ABOX_CA32_CORE1_R(27):
	case ABOX_CA32_CORE1_R(28):
	case ABOX_CA32_CORE1_R(29):
	case ABOX_CA32_CORE1_R(30):
	case ABOX_CA32_CORE1_PC:
	case ABOX_CA32_STATUS:
		return true;
	default:
		return readable_reg_legacy(dev, reg);
	}
}

static bool writeable_reg_9820(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case ABOX_DYN_CLOCK_OFF1:
	case ABOX_SPUS_CTRL4:
	case ABOX_SPUS_CTRL5:
	case ABOX_SPUS_CTRL_FC1:
	case ABOX_SPUS_SBANK_RDMA(8):
	case ABOX_SPUS_SBANK_RDMA(9):
	case ABOX_SPUS_SBANK_RDMA(10):
	case ABOX_SPUS_SBANK_RDMA(11):
	case ABOX_SPUS_SBANK_ASRC(8):
	case ABOX_SPUS_SBANK_ASRC(9):
	case ABOX_SPUS_SBANK_ASRC(10):
	case ABOX_SPUS_SBANK_ASRC(11):
	case ABOX_SPUS_CTRL_SIFS_CNT(2):
	case ABOX_SPUS_CTRL_SIFS_CNT(3):
	case ABOX_SPUS_CTRL_SIFS_CNT(4):
	case ABOX_SPUM_CTRL4:
	case ABOX_SPUM_SBANK_NSRC(4):
	case ABOX_SPUM_SBANK_NSRC(5):
	case ABOX_SPUM_SBANK_NSRC(6):
	case ABOX_SPUM_SBANK_ASRC(4):
	case ABOX_SPUM_SBANK_ASRC(5):
	case ABOX_SPUM_SBANK_ASRC(6):
	case ABOX_SPUM_SBANK_ASRC(7):
	case ABOX_SPUS_ASRC_CTRL(8):
	case ABOX_SPUS_ASRC_IS_PARA0(8):
	case ABOX_SPUS_ASRC_IS_PARA1(8):
	case ABOX_SPUS_ASRC_OS_PARA0(8):
	case ABOX_SPUS_ASRC_OS_PARA1(8):
	case ABOX_SPUS_ASRC_DITHER_CTRL(8):
	case ABOX_SPUS_ASRC_SEED_IN(8):
	case ABOX_SPUS_ASRC_SEED_OUT(8):
	case ABOX_SPUS_ASRC_FILTER_CTRL(8):
	case ABOX_SPUS_ASRC_CTRL(9):
	case ABOX_SPUS_ASRC_IS_PARA0(9):
	case ABOX_SPUS_ASRC_IS_PARA1(9):
	case ABOX_SPUS_ASRC_OS_PARA0(9):
	case ABOX_SPUS_ASRC_OS_PARA1(9):
	case ABOX_SPUS_ASRC_DITHER_CTRL(9):
	case ABOX_SPUS_ASRC_SEED_IN(9):
	case ABOX_SPUS_ASRC_SEED_OUT(9):
	case ABOX_SPUS_ASRC_FILTER_CTRL(9):
	case ABOX_SPUS_ASRC_CTRL(10):
	case ABOX_SPUS_ASRC_IS_PARA0(10):
	case ABOX_SPUS_ASRC_IS_PARA1(10):
	case ABOX_SPUS_ASRC_OS_PARA0(10):
	case ABOX_SPUS_ASRC_OS_PARA1(10):
	case ABOX_SPUS_ASRC_DITHER_CTRL(10):
	case ABOX_SPUS_ASRC_SEED_IN(10):
	case ABOX_SPUS_ASRC_SEED_OUT(10):
	case ABOX_SPUS_ASRC_FILTER_CTRL(10):
	case ABOX_SPUS_ASRC_CTRL(11):
	case ABOX_SPUS_ASRC_IS_PARA0(11):
	case ABOX_SPUS_ASRC_IS_PARA1(11):
	case ABOX_SPUS_ASRC_OS_PARA0(11):
	case ABOX_SPUS_ASRC_OS_PARA1(11):
	case ABOX_SPUS_ASRC_DITHER_CTRL(11):
	case ABOX_SPUS_ASRC_SEED_IN(11):
	case ABOX_SPUS_ASRC_SEED_OUT(11):
	case ABOX_SPUS_ASRC_FILTER_CTRL(11):
	case ABOX_SPUM_ASRC_CTRL(4):
	case ABOX_SPUM_ASRC_IS_PARA0(4):
	case ABOX_SPUM_ASRC_IS_PARA1(4):
	case ABOX_SPUM_ASRC_OS_PARA0(4):
	case ABOX_SPUM_ASRC_OS_PARA1(4):
	case ABOX_SPUM_ASRC_DITHER_CTRL(4):
	case ABOX_SPUM_ASRC_SEED_IN(4):
	case ABOX_SPUM_ASRC_SEED_OUT(4):
	case ABOX_SPUM_ASRC_FILTER_CTRL(4):
	case ABOX_SPUM_ASRC_CTRL(5):
	case ABOX_SPUM_ASRC_IS_PARA0(5):
	case ABOX_SPUM_ASRC_IS_PARA1(5):
	case ABOX_SPUM_ASRC_OS_PARA0(5):
	case ABOX_SPUM_ASRC_OS_PARA1(5):
	case ABOX_SPUM_ASRC_DITHER_CTRL(5):
	case ABOX_SPUM_ASRC_SEED_IN(5):
	case ABOX_SPUM_ASRC_SEED_OUT(5):
	case ABOX_SPUM_ASRC_FILTER_CTRL(5):
	case ABOX_SPUM_ASRC_CTRL(6):
	case ABOX_SPUM_ASRC_IS_PARA0(6):
	case ABOX_SPUM_ASRC_IS_PARA1(6):
	case ABOX_SPUM_ASRC_OS_PARA0(6):
	case ABOX_SPUM_ASRC_OS_PARA1(6):
	case ABOX_SPUM_ASRC_DITHER_CTRL(6):
	case ABOX_SPUM_ASRC_SEED_IN(6):
	case ABOX_SPUM_ASRC_SEED_OUT(6):
	case ABOX_SPUM_ASRC_FILTER_CTRL(6):
	case ABOX_SPUM_ASRC_CTRL(7):
	case ABOX_SPUM_ASRC_IS_PARA0(7):
	case ABOX_SPUM_ASRC_IS_PARA1(7):
	case ABOX_SPUM_ASRC_OS_PARA0(7):
	case ABOX_SPUM_ASRC_OS_PARA1(7):
	case ABOX_SPUM_ASRC_DITHER_CTRL(7):
	case ABOX_SPUM_ASRC_SEED_IN(7):
	case ABOX_SPUM_ASRC_SEED_OUT(7):
	case ABOX_SPUM_ASRC_FILTER_CTRL(7):
		return true;
	default:
		return writeable_reg_legacy(dev, reg);
	}
}

static bool volatile_reg_9830(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case ABOX_IP_INDEX:
	case ABOX_VERSION:
	case ABOX_SYSPOWER_STATUS:
	case ABOX_UAIF_STATUS(0):
	case ABOX_UAIF_STATUS(1):
	case ABOX_UAIF_STATUS(2):
	case ABOX_UAIF_STATUS(3):
	case ABOX_UAIF_STATUS(4):
	case ABOX_UAIF_STATUS(5):
	case ABOX_UAIF_STATUS(6):
	case ABOX_DSIF_STATUS:
	case ABOX_RDMA_CTRL1(0):
	case ABOX_RDMA_STATUS(0):
	case ABOX_RDMA_CTRL1(1):
	case ABOX_RDMA_STATUS(1):
	case ABOX_RDMA_CTRL1(2):
	case ABOX_RDMA_STATUS(2):
	case ABOX_RDMA_CTRL1(3):
	case ABOX_RDMA_STATUS(3):
	case ABOX_RDMA_CTRL1(4):
	case ABOX_RDMA_STATUS(4):
	case ABOX_RDMA_CTRL1(5):
	case ABOX_RDMA_STATUS(5):
	case ABOX_RDMA_CTRL1(6):
	case ABOX_RDMA_STATUS(6):
	case ABOX_RDMA_CTRL1(7):
	case ABOX_RDMA_STATUS(7):
	case ABOX_RDMA_CTRL1(8):
	case ABOX_RDMA_STATUS(8):
	case ABOX_RDMA_CTRL1(9):
	case ABOX_RDMA_STATUS(9):
	case ABOX_RDMA_CTRL1(10):
	case ABOX_RDMA_STATUS(10):
	case ABOX_RDMA_CTRL1(11):
	case ABOX_RDMA_STATUS(11):
	case ABOX_WDMA_STATUS(0):
	case ABOX_WDMA_DUAL_STATUS(0):
	case ABOX_WDMA_STATUS(1):
	case ABOX_WDMA_DUAL_STATUS(1):
	case ABOX_WDMA_STATUS(2):
	case ABOX_WDMA_DUAL_STATUS(2):
	case ABOX_WDMA_STATUS(3):
	case ABOX_WDMA_DUAL_STATUS(3):
	case ABOX_WDMA_STATUS(4):
	case ABOX_WDMA_DUAL_STATUS(4):
	case ABOX_WDMA_DEBUG_STATUS(0):
	case ABOX_WDMA_DEBUG_STATUS(1):
	case ABOX_WDMA_DEBUG_STATUS(2):
	case ABOX_WDMA_DEBUG_STATUS(3):
	case ABOX_WDMA_DEBUG_STATUS(4):
	case ABOX_WDMA_DEBUG_STATUS(5):
	case ABOX_CA32_CORE0_R(0) ... ABOX_CA32_CORE0_PC:
	case ABOX_CA32_CORE1_R(0) ... ABOX_CA32_CORE1_PC:
	case ABOX_CA32_STATUS:
	case ABOX_AUDEN_RDMA_STATUS(0):
	case ABOX_AUDEN_RDMA_STATUS(1):
	case ABOX_AUDEN_RDMA_STATUS(2):
	case ABOX_AUDEN_RDMA_STATUS(3):
	case ABOX_AUDEN_RDMA_STATUS(4):
	case ABOX_AUDEN_RDMA_STATUS(5):
	case ABOX_AUDEN_RDMA_STATUS(6):
	case ABOX_AUDEN_RDMA_STATUS(7):
	case ABOX_AUDEN_RDMA_STATUS(8):
	case ABOX_AUDEN_RDMA_STATUS(9):
	case ABOX_AUDEN_RDMA_STATUS(10):
	case ABOX_AUDEN_RDMA_STATUS(11):
	case ABOX_AUDEN_WDMA_STATUS(0):
	case ABOX_AUDEN_WDMA_STATUS(1):
	case ABOX_AUDEN_WDMA_STATUS(2):
	case ABOX_AUDEN_WDMA_STATUS(3):
	case ABOX_AUDEN_WDMA_STATUS(4):
	case ABOX_AUDEN_WDMA_STATUS(5):
	case ABOX_AUDEN_WDMA_STATUS(6):
	case ABOX_AUDEN_WDMA_STATUS(7):
		return true;
	default:
		return false;
	}
}

static bool readable_reg_9830(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case ABOX_IP_INDEX:
	case ABOX_VERSION:
	case ABOX_SYSPOWER_CTRL:
	case ABOX_SYSPOWER_STATUS:
	case ABOX_SYSTEM_CONFIG0:
	case ABOX_REMAP_MASK:
	case ABOX_REMAP_ADDR:
	case ABOX_DYN_CLOCK_OFF:
	case ABOX_DYN_CLOCK_OFF1:
	case ABOX_QCHANNEL_DISABLE:
	case ABOX_ROUTE_CTRL0:
	case ABOX_ROUTE_CTRL1:
	case ABOX_ROUTE_CTRL2:
	case ABOX_TICK_DIV_RATIO:
	case ABOX_TICK_GEN:
	case ABOX_ROUTE_CTRL3:
	case ABOX_ROUTE_CTRL4:
	case ABOX_SW_PDI_CTRL0 ... ABOX_SW_PDI_CTRL3:
	case ABOX_SPUS_CTRL_FC0:
	case ABOX_SPUS_CTRL_FC1:
	case ABOX_SPUS_CTRL_FC2:
	case ABOX_SPUS_CTRL1 ... ABOX_SPUS_CTRL5:
	case ABOX_SPUS_SBANK_RDMA(0) ... ABOX_SPUS_SBANK_RDMA(11):
	case ABOX_SPUS_SBANK_ASRC(0) ... ABOX_SPUS_SBANK_ASRC(7):
	case ABOX_SPUS_SBANK_MIXP:
	case ABOX_SPUS_SBANK_SIDETONE:
	case ABOX_SPUS_CTRL_SIFS_CNT(0):
	case ABOX_SPUS_CTRL_SIFS_CNT(1):
	case ABOX_SPUS_CTRL_SIFS_CNT(2):
	case ABOX_SPUS_CTRL_SIFS_CNT(3):
	case ABOX_SPUS_CTRL_SIFS_CNT(4):
	case ABOX_SPUS_CTRL_SIFS_CNT(5):
	case ABOX_SPUS_LATENCY_CTRL0:
	case ABOX_SPUS_LATENCY_CTRL1:
	case ABOX_SPUS_LATENCY_CTRL2:
	case ABOX_SPUS_LATENCY_CTRL3:
	case ABOX_SPUM_CTRL0:
	case ABOX_SPUM_CTRL1:
	case ABOX_SPUM_CTRL3:
	case ABOX_SPUM_CTRL4:
	case ABOX_SPUM_SBANK_NSRC(0) ... ABOX_SPUM_SBANK_NSRC(4):
	case ABOX_SPUM_SBANK_ASRC(0) ... ABOX_SPUM_SBANK_ASRC(3):
	case ABOX_AUDEN_FC0_MAIN_CTRL ... ABOX_AUDEN_FC6_WDMA_CTRL:
	case ABOX_AUDEN_MIXP_CTRL(0) ... ABOX_AUDEN_MIXP_CTRL(2):
	case ABOX_AUDEN_SBANK_RDMA(0) ... ABOX_AUDEN_SBANK_RDMA(11):
	case ABOX_AUDEN_SBANK_ASRC(0) ... ABOX_AUDEN_SBANK_ASRC(11):
	case ABOX_AUDEN_SBANK_MIXP(0) ... ABOX_AUDEN_SBANK_MIXP(2):
	case ABOX_AUDEN_ASRC_PERF_CON(0) ... ABOX_AUDEN_ASRC_PERF_CON(11):
	case ABOX_UAIF_CTRL0(0) ... ABOX_UAIF_STATUS(0):
	case ABOX_UAIF_CTRL0(1) ... ABOX_UAIF_STATUS(1):
	case ABOX_UAIF_CTRL0(2) ... ABOX_UAIF_STATUS(2):
	case ABOX_UAIF_CTRL0(3) ... ABOX_UAIF_STATUS(3):
	case ABOX_UAIF_CTRL0(4) ... ABOX_UAIF_STATUS(4):
	case ABOX_UAIF_CTRL0(5) ... ABOX_UAIF_STATUS(5):
	case ABOX_UAIF_CTRL0(6) ... ABOX_UAIF_STATUS(6):
	case ABOX_DSIF_CTRL:
	case ABOX_DSIF_STATUS:
		return true;

	case ABOX_RDMA_CTRL0(0) ... ABOX_RDMA_STATUS(11):
		switch (0xff & reg) {
		case 0x00 ... 0x28:
		case 0x30:
			return true;
		default:
			return false;
		}

	case ABOX_SPUS_ASRC_CTRL(0) ... ABOX_SPUS_ASRC_FILTER_CTRL(7):
		switch (0xff & reg) {
		case 0x00:
		case 0x10 ... 0x2c:
			return true;
		default:
			return false;
		}

	case ABOX_WDMA_CTRL(0) ... ABOX_WDMA_DUAL_STATUS(4):
		switch (0xff & reg) {
		case 0x00:
		case 0x08 ... 0x28:
		case 0x30:
		case 0x80:
		case 0x88 ... 0x94:
		case 0xb0:
			return true;
		default:
			return false;
		}

	case ABOX_WDMA_DEBUG_CTRL(0) ... ABOX_WDMA_DEBUG_STATUS(5):
		switch (0xff & reg) {
		case 0x00:
		case 0x08 ... 0x20:
		case 0x30:
			return true;
		default:
			return false;
		}

	case ABOX_SPUM_ASRC_CTRL(0) ... ABOX_SPUM_ASRC_FILTER_CTRL(3):
		switch (0xff & reg) {
		case 0x00:
		case 0x10 ... 0x2c:
			return true;
		default:
			return false;
		}

	case ABOX_CA32_CORE0_R(0) ... ABOX_CA32_CORE0_PC:
	case ABOX_CA32_CORE1_R(0) ... ABOX_CA32_CORE1_PC:
	case ABOX_CA32_STATUS:
	case ABOX_COEF_2EVEN0(0) ... ABOX_COEF_8ODD1(0):
	case ABOX_COEF_2EVEN0(1) ... ABOX_COEF_8ODD1(1):
		return true;

	case ABOX_AUDEN_RDMA_CTRL0(0) ... ABOX_AUDEN_RDMA_STATUS(11):
		switch (0xff & reg) {
		case 0x00 ... 0x20:
		case 0x30:
			return true;
		default:
			return false;
		}

	case ABOX_AUDEN_ASRC_CTRL(0) ... ABOX_AUDEN_ASRC_FILTER_CTRL(11):
		switch (0xff & reg) {
		case 0x00:
		case 0x10 ... 0x2c:
			return true;
		default:
			return false;
		}

	case ABOX_AUDEN_WDMA_CTRL(0) ... ABOX_AUDEN_WDMA_STATUS(7):
		switch (0xff & reg) {
		case 0x00:
		case 0x08 ... 0x20:
		case 0x30:
			return true;
		default:
			return false;
		}

	case ABOX_SOUNDWIRE_INFO:
	case ABOX_SIDETONE_CTRL:
	case ABOX_SIDETONE_GAIN_CTRL:
	case ABOX_SIDETONE_FILTER_CTRL0:
	case ABOX_SIDETONE_FILTER_CTRL1:
	case ABOX_SIDETONE_HPF_COEF0:
	case ABOX_SIDETONE_HPF_COEF1:
	case ABOX_SIDETONE_HPF_COEF2:
	case ABOX_SIDETONE_HPF_COEF3:
	case ABOX_SIDETONE_HPF_COEF4:
	case ABOX_SIDETONE_PEAK0_COEF0:
	case ABOX_SIDETONE_PEAK0_COEF1:
	case ABOX_SIDETONE_PEAK0_COEF2:
	case ABOX_SIDETONE_PEAK0_COEF3:
	case ABOX_SIDETONE_PEAK0_COEF4:
	case ABOX_SIDETONE_PEAK1_COEF0:
	case ABOX_SIDETONE_PEAK1_COEF1:
	case ABOX_SIDETONE_PEAK1_COEF2:
	case ABOX_SIDETONE_PEAK1_COEF3:
	case ABOX_SIDETONE_PEAK1_COEF4:
	case ABOX_SIDETONE_PEAK2_COEF0:
	case ABOX_SIDETONE_PEAK2_COEF1:
	case ABOX_SIDETONE_PEAK2_COEF2:
	case ABOX_SIDETONE_PEAK2_COEF3:
	case ABOX_SIDETONE_PEAK2_COEF4:
	case ABOX_SIDETONE_LOWSH_COEF0:
	case ABOX_SIDETONE_LOWSH_COEF1:
	case ABOX_SIDETONE_LOWSH_COEF2:
	case ABOX_SIDETONE_LOWSH_COEF3:
	case ABOX_SIDETONE_LOWSH_COEF4:
	case ABOX_SIDETONE_HIGHSH_COEF0:
	case ABOX_SIDETONE_HIGHSH_COEF1:
	case ABOX_SIDETONE_HIGHSH_COEF2:
	case ABOX_SIDETONE_HIGHSH_COEF3:
	case ABOX_SIDETONE_HIGHSH_COEF4:
		return true;
	default:
		return false;
	}
}

static bool writeable_reg_9830(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case ABOX_SYSPOWER_CTRL:
	case ABOX_SYSTEM_CONFIG0:
	case ABOX_REMAP_MASK:
	case ABOX_REMAP_ADDR:
	case ABOX_DYN_CLOCK_OFF:
	case ABOX_DYN_CLOCK_OFF1:
	case ABOX_QCHANNEL_DISABLE:
	case ABOX_ROUTE_CTRL0:
	case ABOX_ROUTE_CTRL1:
	case ABOX_ROUTE_CTRL2:
	case ABOX_TICK_DIV_RATIO:
	case ABOX_TICK_GEN:
	case ABOX_ROUTE_CTRL3:
	case ABOX_ROUTE_CTRL4:
	case ABOX_SW_PDI_CTRL0 ... ABOX_SW_PDI_CTRL3:
	case ABOX_SPUS_CTRL_FC0:
	case ABOX_SPUS_CTRL_FC1:
	case ABOX_SPUS_CTRL_FC2:
	case ABOX_SPUS_CTRL1 ... ABOX_SPUS_CTRL5:
	case ABOX_SPUS_SBANK_RDMA(0) ... ABOX_SPUS_SBANK_RDMA(11):
	case ABOX_SPUS_SBANK_ASRC(0) ... ABOX_SPUS_SBANK_ASRC(7):
	case ABOX_SPUS_SBANK_MIXP:
	case ABOX_SPUS_SBANK_SIDETONE:
	case ABOX_SPUS_CTRL_SIFS_CNT(0):
	case ABOX_SPUS_CTRL_SIFS_CNT(1):
	case ABOX_SPUS_CTRL_SIFS_CNT(2):
	case ABOX_SPUS_CTRL_SIFS_CNT(3):
	case ABOX_SPUS_CTRL_SIFS_CNT(4):
	case ABOX_SPUS_CTRL_SIFS_CNT(5):
	case ABOX_SPUS_LATENCY_CTRL0:
	case ABOX_SPUS_LATENCY_CTRL1:
	case ABOX_SPUS_LATENCY_CTRL2:
	case ABOX_SPUS_LATENCY_CTRL3:
	case ABOX_SPUM_CTRL0:
	case ABOX_SPUM_CTRL1:
	case ABOX_SPUM_CTRL3:
	case ABOX_SPUM_CTRL4:
	case ABOX_SPUM_SBANK_NSRC(0) ... ABOX_SPUM_SBANK_NSRC(4):
	case ABOX_SPUM_SBANK_ASRC(0) ... ABOX_SPUM_SBANK_ASRC(3):
	case ABOX_AUDEN_FC0_MAIN_CTRL ... ABOX_AUDEN_FC6_WDMA_CTRL:
	case ABOX_AUDEN_MIXP_CTRL(0) ... ABOX_AUDEN_MIXP_CTRL(2):
	case ABOX_AUDEN_SBANK_RDMA(0) ... ABOX_AUDEN_SBANK_RDMA(11):
	case ABOX_AUDEN_SBANK_ASRC(0) ... ABOX_AUDEN_SBANK_ASRC(11):
	case ABOX_AUDEN_SBANK_MIXP(0) ... ABOX_AUDEN_SBANK_MIXP(2):
	case ABOX_AUDEN_ASRC_PERF_CON(0) ... ABOX_AUDEN_ASRC_PERF_CON(11):
	case ABOX_UAIF_CTRL0(0) ... ABOX_UAIF_IRQ_CTRL(0):
	case ABOX_UAIF_CTRL0(1) ... ABOX_UAIF_IRQ_CTRL(1):
	case ABOX_UAIF_CTRL0(2) ... ABOX_UAIF_IRQ_CTRL(2):
	case ABOX_UAIF_CTRL0(3) ... ABOX_UAIF_IRQ_CTRL(3):
	case ABOX_UAIF_CTRL0(4) ... ABOX_UAIF_IRQ_CTRL(4):
	case ABOX_UAIF_CTRL0(5) ... ABOX_UAIF_IRQ_CTRL(5):
	case ABOX_UAIF_CTRL0(6) ... ABOX_UAIF_IRQ_CTRL(6):
	case ABOX_DSIF_CTRL:
		return true;

	case ABOX_RDMA_CTRL0(0) ... ABOX_RDMA_STATUS(11):
		switch (0xff & reg) {
		case 0x00 ... 0x28:
			return true;
		default:
			return false;
		}

	case ABOX_SPUS_ASRC_CTRL(0) ... ABOX_SPUS_ASRC_FILTER_CTRL(7):
		switch (0xff & reg) {
		case 0x00:
		case 0x10 ... 0x2c:
			return true;
		default:
			return false;
		}

	case ABOX_WDMA_CTRL(0) ... ABOX_WDMA_DUAL_STATUS(4):
		switch (0xff & reg) {
		case 0x00:
		case 0x08 ... 0x28:
		case 0x80:
		case 0x88 ... 0x94:
			return true;
		default:
			return false;
		}

	case ABOX_WDMA_DEBUG_CTRL(0) ... ABOX_WDMA_DEBUG_STATUS(5):
		switch (0xff & reg) {
		case 0x00:
		case 0x08 ... 0x20:
			return true;
		default:
			return false;
		}

	case ABOX_SPUM_ASRC_CTRL(0) ... ABOX_SPUM_ASRC_FILTER_CTRL(3):
		switch (0xff & reg) {
		case 0x00:
		case 0x10 ... 0x2c:
			return true;
		default:
			return false;
		}

	case ABOX_COEF_2EVEN0(0) ... ABOX_COEF_8ODD1(0):
	case ABOX_COEF_2EVEN0(1) ... ABOX_COEF_8ODD1(1):
		return true;

	case ABOX_AUDEN_RDMA_CTRL0(0) ... ABOX_AUDEN_RDMA_STATUS(11):
		switch (0xff & reg) {
		case 0x00 ... 0x20:
			return true;
		default:
			return false;
		}

	case ABOX_AUDEN_ASRC_CTRL(0) ... ABOX_AUDEN_ASRC_FILTER_CTRL(11):
		switch (0xff & reg) {
		case 0x00:
		case 0x10 ... 0x2c:
			return true;
		default:
			return false;
		}

	case ABOX_AUDEN_WDMA_CTRL(0) ... ABOX_AUDEN_WDMA_STATUS(7):
		switch (0xff & reg) {
		case 0x00:
		case 0x08 ... 0x20:
			return true;
		default:
			return false;
		}

	case ABOX_SOUNDWIRE_INFO:
	case ABOX_SIDETONE_CTRL:
	case ABOX_SIDETONE_GAIN_CTRL:
	case ABOX_SIDETONE_FILTER_CTRL0:
	case ABOX_SIDETONE_FILTER_CTRL1:
	case ABOX_SIDETONE_HPF_COEF0:
	case ABOX_SIDETONE_HPF_COEF1:
	case ABOX_SIDETONE_HPF_COEF2:
	case ABOX_SIDETONE_HPF_COEF3:
	case ABOX_SIDETONE_HPF_COEF4:
	case ABOX_SIDETONE_PEAK0_COEF0:
	case ABOX_SIDETONE_PEAK0_COEF1:
	case ABOX_SIDETONE_PEAK0_COEF2:
	case ABOX_SIDETONE_PEAK0_COEF3:
	case ABOX_SIDETONE_PEAK0_COEF4:
	case ABOX_SIDETONE_PEAK1_COEF0:
	case ABOX_SIDETONE_PEAK1_COEF1:
	case ABOX_SIDETONE_PEAK1_COEF2:
	case ABOX_SIDETONE_PEAK1_COEF3:
	case ABOX_SIDETONE_PEAK1_COEF4:
	case ABOX_SIDETONE_PEAK2_COEF0:
	case ABOX_SIDETONE_PEAK2_COEF1:
	case ABOX_SIDETONE_PEAK2_COEF2:
	case ABOX_SIDETONE_PEAK2_COEF3:
	case ABOX_SIDETONE_PEAK2_COEF4:
	case ABOX_SIDETONE_LOWSH_COEF0:
	case ABOX_SIDETONE_LOWSH_COEF1:
	case ABOX_SIDETONE_LOWSH_COEF2:
	case ABOX_SIDETONE_LOWSH_COEF3:
	case ABOX_SIDETONE_LOWSH_COEF4:
	case ABOX_SIDETONE_HIGHSH_COEF0:
	case ABOX_SIDETONE_HIGHSH_COEF1:
	case ABOX_SIDETONE_HIGHSH_COEF2:
	case ABOX_SIDETONE_HIGHSH_COEF3:
	case ABOX_SIDETONE_HIGHSH_COEF4:
		return true;
	default:
		return false;
	}
}

static bool volatile_reg_9630(struct device *dev, unsigned int reg)
{
	return volatile_reg_9830(dev, reg);
}

static bool readable_reg_9630(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case ABOX_SPDYIF_CTRL:
		return true;
	default:
		return readable_reg_9830(dev, reg);
	}
}

static bool writeable_reg_9630(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case ABOX_SPDYIF_CTRL:
		return true;
	default:
		return writeable_reg_9830(dev, reg);
	}
}

static const struct reg_default reg_defaults_8895[] = {
	{0x0000, 0x41424F58},
	{0x0010, 0x00000000},
	{0x0014, 0x00000000},
	{0x0020, 0x00000000},
	{0x0024, 0xFFF00000},
	{0x0028, 0x13F00000},
	{0x0030, 0x7FFFFFFF},
	{0x0040, 0x00000000},
	{0x0044, 0x00000000},
	{0x0048, 0x00000000},
	{0x0200, 0x00000000},
	{0x0204, 0x00000000},
	{0x0208, 0x00000000},
	{0x020C, 0x00000000},
	{0x0220, 0x00000000},
	{0x0224, 0x00000000},
	{0x0228, 0x00000000},
	{0x022C, 0x00000000},
	{0x0230, 0x00000000},
	{0x0234, 0x00000000},
	{0x0238, 0x00000000},
	{0x023C, 0x00000000},
	{0x0240, 0x00000000},
	{0x0260, 0x00000000},
	{0x0300, 0x00000000},
	{0x0304, 0x00000000},
	{0x0308, 0x00000000},
	{0x030C, 0x00000000},
	{0x0320, 0x00000000},
	{0x0324, 0x00000000},
	{0x0328, 0x00000000},
	{0x032C, 0x00000000},
	{0x0330, 0x00000000},
	{0x0334, 0x00000000},
	{0x0338, 0x00000000},
	{0x033C, 0x00000000},
	{0x0340, 0x00000000},
	{0x0344, 0x00000000},
	{0x0348, 0x00000000},
	{0x0500, 0x01000000},
	{0x0504, 0x00000000},
	{0x050C, 0x00000000},
	{0x0510, 0x01000000},
	{0x0514, 0x00000000},
	{0x051C, 0x00000000},
	{0x0520, 0x01000000},
	{0x0524, 0x00000000},
	{0x052C, 0x00000000},
	{0x0530, 0x01000000},
	{0x0534, 0x00000000},
	{0x053C, 0x00000000},
	{0x0540, 0x01000000},
	{0x0544, 0x00000000},
	{0x054C, 0x00000000},
	{0x0550, 0x00000000},
	{0x0554, 0x00000000},
};

static const struct reg_default reg_defaults_9810[] = {
	{0x0000, 0x41424F58},
	{0x0010, 0x00000000},
	{0x0014, 0x00000000},
	{0x0020, 0x00004444},
	{0x0024, 0xFFF00000},
	{0x0028, 0x17D00000},
	{0x0030, 0x7FFFFFFF},
	{0x0038, 0x00000000},
	{0x0040, 0x00000000},
	{0x0044, 0x00000000},
	{0x0048, 0x00000000},
	{0x0200, 0x00000000},
	{0x0204, 0x00000000},
	{0x0208, 0x00000000},
	{0x020C, 0x00000000},
	{0x0220, 0x00000000},
	{0x0224, 0x00000000},
	{0x0228, 0x00000000},
	{0x022C, 0x00000000},
	{0x0230, 0x00000000},
	{0x0234, 0x00000000},
	{0x0238, 0x00000000},
	{0x023C, 0x00000000},
	{0x0240, 0x00000000},
	{0x0260, 0x00000000},
	{0x0280, 0x00000000},
	{0x0284, 0x00000000},
	{0x0300, 0x00000000},
	{0x0304, 0x00000000},
	{0x0308, 0x00000000},
	{0x030C, 0x00000000},
	{0x0320, 0x00000000},
	{0x0324, 0x00000000},
	{0x0328, 0x00000000},
	{0x032C, 0x00000000},
	{0x0330, 0x00000000},
	{0x0334, 0x00000000},
	{0x0338, 0x00000000},
	{0x033C, 0x00000000},
	{0x0340, 0x00000000},
	{0x0344, 0x00000000},
	{0x0348, 0x00000000},
	{0x0500, 0x01000010},
	{0x0504, 0x00000000},
	{0x050C, 0x00000000},
	{0x0510, 0x01000010},
	{0x0514, 0x00000000},
	{0x051C, 0x00000000},
	{0x0520, 0x01000010},
	{0x0524, 0x00000000},
	{0x052C, 0x00000000},
	{0x0530, 0x01000010},
	{0x0534, 0x00000000},
	{0x053C, 0x00000000},
	{0x0540, 0x01000010},
	{0x0544, 0x00000000},
	{0x054C, 0x00000000},
	{0x0550, 0x00000000},
	{0x0554, 0x00000000},
};

static const struct reg_default reg_defaults_9820[] = {
	{0x0000, 0x41424F58},
	{0x0010, 0x00000000},
	{0x0014, 0x00000000},
	{0x0020, 0x00004444},
	{0x0024, 0xFFF00000},
	{0x0028, 0x18D00000},
	{0x0030, 0x7FFFFFFF},
	{0x0034, 0x0000001F},
	{0x0038, 0x00000000},
	{0x0040, 0x00000000},
	{0x0044, 0x00000000},
	{0x0048, 0x00000000},
	{0x0050, 0x000004E1},
	{0x0054, 0x0C72108C},
	{0x0200, 0x00000000},
	{0x0204, 0x00000000},
	{0x0208, 0x00000000},
	{0x020C, 0x00000000},
	{0x0210, 0x32100000},
	{0x0214, 0xBA987654},
	{0x0218, 0x00000000},
	{0x0220, 0x00000000},
	{0x0224, 0x00000000},
	{0x0228, 0x00000000},
	{0x022C, 0x00000000},
	{0x0230, 0x00000000},
	{0x0234, 0x00000000},
	{0x0238, 0x00000000},
	{0x023C, 0x00000000},
	{0x0240, 0x00000000},
	{0x0244, 0x00000000},
	{0x0248, 0x00000000},
	{0x024C, 0x00000000},
	{0x0250, 0x00000000},
	{0x0254, 0x00000000},
	{0x0258, 0x00000000},
	{0x025C, 0x00000000},
	{0x0260, 0x00000000},
	{0x0264, 0x00000000},
	{0x0268, 0x00000000},
	{0x026C, 0x00000000},
	{0x0270, 0x00000000},
	{0x0274, 0x00000000},
	{0x0278, 0x00000000},
	{0x027C, 0x00000000},
	{0x0280, 0x00000000},
	{0x028C, 0x00000000},
	{0x0290, 0x00000000},
	{0x0294, 0x00000000},
	{0x0298, 0x00000000},
	{0x029C, 0x00000000},
	{0x0300, 0x00000000},
	{0x0304, 0x00000000},
	{0x0308, 0x00000000},
	{0x030C, 0x00000000},
	{0x0310, 0x76543210},
	{0x0320, 0x00000000},
	{0x0324, 0x00000000},
	{0x0328, 0x00000000},
	{0x032C, 0x00000000},
	{0x0330, 0x00000000},
	{0x0334, 0x00000000},
	{0x0338, 0x00000000},
	{0x033C, 0x00000000},
	{0x0340, 0x00000000},
	{0x0348, 0x00000000},
	{0x034C, 0x00000000},
	{0x0350, 0x00000000},
	{0x0354, 0x00000000},
	{0x0358, 0x00000000},
	{0x035C, 0x00000000},
	{0x0360, 0x00000000},
	{0x0364, 0x00000000},
	{0x0368, 0x00000000},
	{0x0500, 0x01000010},
	{0x0504, 0x00000000},
	{0x050C, 0x00000000},
	{0x0510, 0x01000010},
	{0x0514, 0x00000000},
	{0x051C, 0x00000000},
	{0x0520, 0x01000010},
	{0x0524, 0x00000000},
	{0x052C, 0x00000000},
	{0x0530, 0x01000010},
	{0x0534, 0x00000000},
	{0x053C, 0x00000000},
	{0x0540, 0x01000010},
	{0x0544, 0x00000000},
	{0x054C, 0x00000000},
	{0x0550, 0x00000000},
	{0x0554, 0x00000000},
	{0x1000, 0x00400000},
	{0x1004, 0x00000000},
	{0x1008, 0x00000000},
	{0x100C, 0x00000000},
	{0x1010, 0x00000000},
	{0x1014, 0x00000000},
	{0x1018, 0x00000000},
	{0x101C, 0x00000000},
	{0x1020, 0x00000000},
	{0x1030, 0x00000000},
	{0x1100, 0x00400000},
	{0x1104, 0x00000000},
	{0x1108, 0x00000000},
	{0x110C, 0x00000000},
	{0x1110, 0x00000000},
	{0x1114, 0x00000000},
	{0x1118, 0x00000000},
	{0x111C, 0x00000000},
	{0x1120, 0x00000000},
	{0x1130, 0x00000000},
	{0x1200, 0x00400000},
	{0x1204, 0x00000000},
	{0x1208, 0x00000000},
	{0x120C, 0x00000000},
	{0x1210, 0x00000000},
	{0x1214, 0x00000000},
	{0x1218, 0x00000000},
	{0x121C, 0x00000000},
	{0x1220, 0x00000000},
	{0x1230, 0x00000000},
	{0x1300, 0x00400000},
	{0x1304, 0x00000000},
	{0x1308, 0x00000000},
	{0x130C, 0x00000000},
	{0x1310, 0x00000000},
	{0x1314, 0x00000000},
	{0x1318, 0x00000000},
	{0x131C, 0x00000000},
	{0x1320, 0x00000000},
	{0x1330, 0x00000000},
	{0x1400, 0x00400000},
	{0x1404, 0x00000000},
	{0x1408, 0x00000000},
	{0x140C, 0x00000000},
	{0x1410, 0x00000000},
	{0x1414, 0x00000000},
	{0x1418, 0x00000000},
	{0x141C, 0x00000000},
	{0x1420, 0x00000000},
	{0x1430, 0x00000000},
	{0x1500, 0x00400000},
	{0x1504, 0x00000000},
	{0x1508, 0x00000000},
	{0x150C, 0x00000000},
	{0x1510, 0x00000000},
	{0x1514, 0x00000000},
	{0x1518, 0x00000000},
	{0x151C, 0x00000000},
	{0x1520, 0x00000000},
	{0x1530, 0x00000000},
	{0x1600, 0x00400000},
	{0x1604, 0x00000000},
	{0x1608, 0x00000000},
	{0x160C, 0x00000000},
	{0x1610, 0x00000000},
	{0x1614, 0x00000000},
	{0x1618, 0x00000000},
	{0x161C, 0x00000000},
	{0x1620, 0x00000000},
	{0x1630, 0x00000000},
	{0x1700, 0x00400000},
	{0x1704, 0x00000000},
	{0x1708, 0x00000000},
	{0x170C, 0x00000000},
	{0x1710, 0x00000000},
	{0x1714, 0x00000000},
	{0x1718, 0x00000000},
	{0x171C, 0x00000000},
	{0x1720, 0x00000000},
	{0x1730, 0x00000000},
	{0x1800, 0x00400000},
	{0x1804, 0x00000000},
	{0x1808, 0x00000000},
	{0x180C, 0x00000000},
	{0x1810, 0x00000000},
	{0x1814, 0x00000000},
	{0x1818, 0x00000000},
	{0x181C, 0x00000000},
	{0x1820, 0x00000000},
	{0x1830, 0x00000000},
	{0x1900, 0x00400000},
	{0x1904, 0x00000000},
	{0x1908, 0x00000000},
	{0x190C, 0x00000000},
	{0x1910, 0x00000000},
	{0x1914, 0x00000000},
	{0x1918, 0x00000000},
	{0x191C, 0x00000000},
	{0x1920, 0x00000000},
	{0x1930, 0x00000000},
	{0x1A00, 0x00400000},
	{0x1A04, 0x00000000},
	{0x1A08, 0x00000000},
	{0x1A0C, 0x00000000},
	{0x1A10, 0x00000000},
	{0x1A14, 0x00000000},
	{0x1A18, 0x00000000},
	{0x1A1C, 0x00000000},
	{0x1A20, 0x00000000},
	{0x1A30, 0x00000000},
	{0x1B00, 0x00400000},
	{0x1B04, 0x00000000},
	{0x1B08, 0x00000000},
	{0x1B0C, 0x00000000},
	{0x1B10, 0x00000000},
	{0x1B14, 0x00000000},
	{0x1B18, 0x00000000},
	{0x1B1C, 0x00000000},
	{0x1B20, 0x00000000},
	{0x1B30, 0x00000000},
	{0x2000, 0x00000000},
	{0x2010, 0x00000000},
	{0x2014, 0x00000000},
	{0x2018, 0x00000000},
	{0x201C, 0x00000000},
	{0x2020, 0x00000000},
	{0x2024, 0x00000000},
	{0x2028, 0x00000000},
	{0x202C, 0x00000000},
	{0x2100, 0x00000000},
	{0x2110, 0x00000000},
	{0x2114, 0x00000000},
	{0x2118, 0x00000000},
	{0x211C, 0x00000000},
	{0x2120, 0x00000000},
	{0x2124, 0x00000000},
	{0x2128, 0x00000000},
	{0x212C, 0x00000000},
	{0x2200, 0x00000000},
	{0x2210, 0x00000000},
	{0x2214, 0x00000000},
	{0x2218, 0x00000000},
	{0x221C, 0x00000000},
	{0x2220, 0x00000000},
	{0x2224, 0x00000000},
	{0x2228, 0x00000000},
	{0x222C, 0x00000000},
	{0x2300, 0x00000000},
	{0x2310, 0x00000000},
	{0x2314, 0x00000000},
	{0x2318, 0x00000000},
	{0x231C, 0x00000000},
	{0x2320, 0x00000000},
	{0x2324, 0x00000000},
	{0x2328, 0x00000000},
	{0x232C, 0x00000000},
	{0x2400, 0x00000000},
	{0x2410, 0x00000000},
	{0x2414, 0x00000000},
	{0x2418, 0x00000000},
	{0x241C, 0x00000000},
	{0x2420, 0x00000000},
	{0x2424, 0x00000000},
	{0x2428, 0x00000000},
	{0x242C, 0x00000000},
	{0x2500, 0x00000000},
	{0x2510, 0x00000000},
	{0x2514, 0x00000000},
	{0x2518, 0x00000000},
	{0x251C, 0x00000000},
	{0x2520, 0x00000000},
	{0x2524, 0x00000000},
	{0x2528, 0x00000000},
	{0x252C, 0x00000000},
	{0x2600, 0x00000000},
	{0x2610, 0x00000000},
	{0x2614, 0x00000000},
	{0x2618, 0x00000000},
	{0x261C, 0x00000000},
	{0x2620, 0x00000000},
	{0x2624, 0x00000000},
	{0x2628, 0x00000000},
	{0x262C, 0x00000000},
	{0x2700, 0x00000000},
	{0x2710, 0x00000000},
	{0x2714, 0x00000000},
	{0x2718, 0x00000000},
	{0x271C, 0x00000000},
	{0x2720, 0x00000000},
	{0x2724, 0x00000000},
	{0x2728, 0x00000000},
	{0x272C, 0x00000000},
	{0x2800, 0x00000000},
	{0x2810, 0x00000000},
	{0x2814, 0x00000000},
	{0x2818, 0x00000000},
	{0x281C, 0x00000000},
	{0x2820, 0x00000000},
	{0x2824, 0x00000000},
	{0x2828, 0x00000000},
	{0x282C, 0x00000000},
	{0x2900, 0x00000000},
	{0x2910, 0x00000000},
	{0x2914, 0x00000000},
	{0x2918, 0x00000000},
	{0x291C, 0x00000000},
	{0x2920, 0x00000000},
	{0x2924, 0x00000000},
	{0x2928, 0x00000000},
	{0x292C, 0x00000000},
	{0x2A00, 0x00000000},
	{0x2A10, 0x00000000},
	{0x2A14, 0x00000000},
	{0x2A18, 0x00000000},
	{0x2A1C, 0x00000000},
	{0x2A20, 0x00000000},
	{0x2A24, 0x00000000},
	{0x2A28, 0x00000000},
	{0x2A2C, 0x00000000},
	{0x2B00, 0x00000000},
	{0x2B10, 0x00000000},
	{0x2B14, 0x00000000},
	{0x2B18, 0x00000000},
	{0x2B1C, 0x00000000},
	{0x2B20, 0x00000000},
	{0x2B24, 0x00000000},
	{0x2B28, 0x00000000},
	{0x2B2C, 0x00000000},
	{0x3000, 0x00400000},
	{0x3008, 0x00000000},
	{0x300C, 0x00000000},
	{0x3010, 0x00000000},
	{0x3014, 0x00000000},
	{0x3018, 0x00000000},
	{0x301C, 0x00000000},
	{0x3020, 0x00000000},
	{0x3030, 0x00000000},
	{0x3100, 0x00400000},
	{0x3108, 0x00000000},
	{0x310C, 0x00000000},
	{0x3110, 0x00000000},
	{0x3114, 0x00000000},
	{0x3118, 0x00000000},
	{0x311C, 0x00000000},
	{0x3120, 0x00000000},
	{0x3130, 0x00000000},
	{0x3200, 0x00400000},
	{0x3208, 0x00000000},
	{0x320C, 0x00000000},
	{0x3210, 0x00000000},
	{0x3214, 0x00000000},
	{0x3218, 0x00000000},
	{0x321C, 0x00000000},
	{0x3220, 0x00000000},
	{0x3230, 0x00000000},
	{0x3300, 0x00400000},
	{0x3308, 0x00000000},
	{0x330C, 0x00000000},
	{0x3310, 0x00000000},
	{0x3314, 0x00000000},
	{0x3318, 0x00000000},
	{0x331C, 0x00000000},
	{0x3320, 0x00000000},
	{0x3330, 0x00000000},
	{0x3400, 0x00400000},
	{0x3408, 0x00000000},
	{0x340C, 0x00000000},
	{0x3410, 0x00000000},
	{0x3414, 0x00000000},
	{0x3418, 0x00000000},
	{0x341C, 0x00000000},
	{0x3420, 0x00000000},
	{0x3430, 0x00000000},
	{0x3500, 0x00400000},
	{0x3508, 0x00000000},
	{0x350C, 0x00000000},
	{0x3510, 0x00000000},
	{0x3514, 0x00000000},
	{0x3518, 0x00000000},
	{0x351C, 0x00000000},
	{0x3520, 0x00000000},
	{0x3530, 0x00000000},
	{0x3600, 0x00400000},
	{0x3608, 0x00000000},
	{0x360C, 0x00000000},
	{0x3610, 0x00000000},
	{0x3614, 0x00000000},
	{0x3618, 0x00000000},
	{0x361C, 0x00000000},
	{0x3620, 0x00000000},
	{0x3630, 0x00000000},
	{0x3700, 0x00400000},
	{0x3708, 0x00000000},
	{0x370C, 0x00000000},
	{0x3710, 0x00000000},
	{0x3714, 0x00000000},
	{0x3718, 0x00000000},
	{0x371C, 0x00000000},
	{0x3720, 0x00000000},
	{0x3730, 0x00000000},
	{0x4000, 0x00000000},
	{0x4010, 0x00000000},
	{0x4014, 0x00000000},
	{0x4018, 0x00000000},
	{0x401C, 0x00000000},
	{0x4020, 0x00000000},
	{0x4024, 0x00000000},
	{0x4028, 0x00000000},
	{0x402C, 0x00000000},
	{0x4100, 0x00000000},
	{0x4110, 0x00000000},
	{0x4114, 0x00000000},
	{0x4118, 0x00000000},
	{0x411C, 0x00000000},
	{0x4120, 0x00000000},
	{0x4124, 0x00000000},
	{0x4128, 0x00000000},
	{0x412C, 0x00000000},
	{0x4200, 0x00000000},
	{0x4210, 0x00000000},
	{0x4214, 0x00000000},
	{0x4218, 0x00000000},
	{0x421C, 0x00000000},
	{0x4220, 0x00000000},
	{0x4224, 0x00000000},
	{0x4228, 0x00000000},
	{0x422C, 0x00000000},
	{0x4300, 0x00000000},
	{0x4310, 0x00000000},
	{0x4314, 0x00000000},
	{0x4318, 0x00000000},
	{0x431C, 0x00000000},
	{0x4320, 0x00000000},
	{0x4324, 0x00000000},
	{0x4328, 0x00000000},
	{0x432C, 0x00000000},
	{0x4400, 0x00000000},
	{0x4410, 0x00000000},
	{0x4414, 0x00000000},
	{0x4418, 0x00000000},
	{0x441C, 0x00000000},
	{0x4420, 0x00000000},
	{0x4424, 0x00000000},
	{0x4428, 0x00000000},
	{0x442C, 0x00000000},
	{0x4500, 0x00000000},
	{0x4510, 0x00000000},
	{0x4514, 0x00000000},
	{0x4518, 0x00000000},
	{0x451C, 0x00000000},
	{0x4520, 0x00000000},
	{0x4524, 0x00000000},
	{0x4528, 0x00000000},
	{0x452C, 0x00000000},
	{0x4600, 0x00000000},
	{0x4610, 0x00000000},
	{0x4614, 0x00000000},
	{0x4618, 0x00000000},
	{0x461C, 0x00000000},
	{0x4620, 0x00000000},
	{0x4624, 0x00000000},
	{0x4628, 0x00000000},
	{0x462C, 0x00000000},
	{0x4700, 0x00000000},
	{0x4710, 0x00000000},
	{0x4714, 0x00000000},
	{0x4718, 0x00000000},
	{0x471C, 0x00000000},
	{0x4720, 0x00000000},
	{0x4724, 0x00000000},
	{0x4728, 0x00000000},
	{0x472C, 0x00000000},
	{0x7000, 0x028C77F5},
	{0x7004, 0x14B2CC4B},
	{0x7008, 0x2FC5569B},
	{0x700C, 0x49CFDC49},
	{0x7010, 0x5DE13770},
	{0x7014, 0x6B829664},
	{0x7018, 0x7427A7B6},
	{0x701C, 0x79827551},
	{0x7020, 0x7CEF562B},
	{0x7024, 0x7F6D9A7D},
	{0x7028, 0x09CD03E0},
	{0x702C, 0x21D4005E},
	{0x7030, 0x3D5CCE0A},
	{0x7034, 0x54B1FC98},
	{0x7038, 0x656D7776},
	{0x703C, 0x70583CC5},
	{0x7040, 0x77261896},
	{0x7044, 0x7B64DD82},
	{0x7048, 0x7E3F01DC},
	{0x704C, 0x03A315A5},
	{0x7050, 0x2128EBC9},
	{0x7054, 0x64BD0D3F},
	{0x7058, 0x0E955F07},
	{0x705C, 0x3CA7D896},
	{0x7060, 0x02DA4CF0},
	{0x7064, 0x1C1A1599},
	{0x7068, 0x612F333A},
	{0x706C, 0x0BC9B8F1},
	{0x7070, 0x369D88A0},
	{0x7100, 0x014B8816},
	{0x7104, 0x0B0F7FF9},
	{0x7108, 0x1BD33F7E},
	{0x710C, 0x2F993C8A},
	{0x7110, 0x42EFD988},
	{0x7114, 0x53D56218},
	{0x7118, 0x61AB90DC},
	{0x711C, 0x6CC00746},
	{0x7120, 0x75DA7EBE},
	{0x7124, 0x7DFC48C6},
	{0x7128, 0x0514063A},
	{0x712C, 0x12CFE5C3},
	{0x7130, 0x25946D33},
	{0x7134, 0x397BF07D},
	{0x7138, 0x4BC1BE21},
	{0x713C, 0x5B218944},
	{0x7140, 0x67835DCA},
	{0x7144, 0x717D64BD},
	{0x7148, 0x79F8D0E6},
	{0x714C, 0x03A315A5},
	{0x7150, 0x2128EBC9},
	{0x7154, 0x64BD0D3F},
	{0x7158, 0x0E955F07},
	{0x715C, 0x3CA7D896},
	{0x7160, 0x02DA4CF0},
	{0x7164, 0x1C1A1599},
	{0x7168, 0x612F333A},
	{0x716C, 0x0BC9B8F1},
	{0x7170, 0x369D88A0},
};

static const struct reg_sequence patch_legacy[] = {
	{ABOX_SPUM_CTRL0, ABOX_FUNC_CHAIN_RSRC_RECP_MASK},
};

static const struct reg_sequence patch_9820[] = {
	{ABOX_SPUM_CTRL0, ABOX_FUNC_CHAIN_RSRC_RECP_MASK},

	/* 0x0000 */
	{ABOX_SPUS_SBANK_RDMA(0), (SZ_512 << 16) | (0 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(1), (SZ_512 << 16) | (1 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(2), (SZ_512 << 16) | (2 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(3), (SZ_512 << 16) | (3 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(4), (SZ_512 << 16) | (4 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(5), (SZ_512 << 16) | (5 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(6), (SZ_512 << 16) | (6 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(7), (SZ_512 << 16) | (7 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(8), (SZ_512 << 16) | (8 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(9), (SZ_512 << 16) | (9 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(10), (SZ_512 << 16) | (10 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(11), (SZ_512 << 16) | (11 * SZ_512)},
	/* 0x1800 */
	{ABOX_SPUS_SBANK_ASRC(0), (0x2c0 << 16) | (0x1800 + 0x000)},
	{ABOX_SPUS_SBANK_ASRC(1), (0x1a0 << 16) | (0x1800 + 0x2c0)},
	{ABOX_SPUS_SBANK_ASRC(2), (0x1a0 << 16) | (0x1800 + 0x460)},
	{ABOX_SPUS_SBANK_ASRC(3), (0x190 << 16) | (0x1800 + 0x600)},
	/* 0x2000 */
	{ABOX_SPUS_SBANK_ASRC(4), (0x2c0 << 16) | (0x2000 + 0x000)},
	{ABOX_SPUS_SBANK_ASRC(5), (0x1a0 << 16) | (0x2000 + 0x2c0)},
	{ABOX_SPUS_SBANK_ASRC(6), (0x1a0 << 16) | (0x2000 + 0x460)},
	{ABOX_SPUS_SBANK_ASRC(7), (0x190 << 16) | (0x2000 + 0x600)},
	/* 0x2800 */
	{ABOX_SPUS_SBANK_ASRC(8), (0x2c0 << 16) | (0x2800 + 0x000)},
	{ABOX_SPUS_SBANK_ASRC(9), (0x1a0 << 16) | (0x2800 + 0x2c0)},
	{ABOX_SPUS_SBANK_ASRC(10), (0x1a0 << 16) | (0x2800 + 0x460)},
	{ABOX_SPUS_SBANK_ASRC(11), (0x190 << 16) | (0x2800 + 0x600)},
	/* 0x3000 */
	{ABOX_SPUS_SBANK_MIXP, (SZ_128 << 16) | 0x3000},

	/* 0x0000 */
	{ABOX_SPUM_SBANK_RSRC(0), (SZ_512 << 16) | (0 * SZ_512)},
	{ABOX_SPUM_SBANK_RSRC(1), (SZ_512 << 16) | (1 * SZ_512)},
	{ABOX_SPUM_SBANK_NSRC(0), (SZ_512 << 16) | (2 * SZ_512)},
	{ABOX_SPUM_SBANK_NSRC(1), (SZ_512 << 16) | (3 * SZ_512)},
	{ABOX_SPUM_SBANK_NSRC(2), (SZ_512 << 16) | (4 * SZ_512)},
	{ABOX_SPUM_SBANK_NSRC(3), (SZ_512 << 16) | (5 * SZ_512)},
	{ABOX_SPUM_SBANK_NSRC(4), (SZ_512 << 16) | (6 * SZ_512)},
	{ABOX_SPUM_SBANK_NSRC(5), (SZ_512 << 16) | (7 * SZ_512)},
	{ABOX_SPUM_SBANK_NSRC(6), (SZ_512 << 16) | (8 * SZ_512)},
	{ABOX_SPUM_SBANK_RECP, (SZ_256 << 16) | (9 * SZ_512)},
	/* 0x1400 */
	{ABOX_SPUM_SBANK_ASRC(0), (0x2c0 << 16) | (0x1400 + 0x000)},
	{ABOX_SPUM_SBANK_ASRC(1), (0x1a0 << 16) | (0x1400 + 0x2c0)},
	{ABOX_SPUM_SBANK_ASRC(2), (0x1a0 << 16) | (0x1400 + 0x460)},
	{ABOX_SPUM_SBANK_ASRC(3), (0x190 << 16) | (0x1400 + 0x600)},
	/* 0x1c00 */
	{ABOX_SPUM_SBANK_ASRC(4), (0x2c0 << 16) | (0x1c00 + 0x000)},
	{ABOX_SPUM_SBANK_ASRC(5), (0x1a0 << 16) | (0x1c00 + 0x2c0)},
	{ABOX_SPUM_SBANK_ASRC(6), (0x1a0 << 16) | (0x1c00 + 0x460)},
	{ABOX_SPUM_SBANK_ASRC(7), (0x190 << 16) | (0x1c00 + 0x600)},
};

static const struct reg_sequence patch_9830[] = {
	/* 0x0000 */
	{ABOX_SPUS_SBANK_RDMA(0), (SZ_512 << 16) | (0 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(1), (SZ_512 << 16) | (1 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(2), (SZ_512 << 16) | (2 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(3), (SZ_512 << 16) | (3 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(4), (SZ_512 << 16) | (4 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(5), (SZ_512 << 16) | (5 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(6), (SZ_512 << 16) | (6 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(7), (SZ_512 << 16) | (7 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(8), (SZ_512 << 16) | (8 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(9), (SZ_512 << 16) | (9 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(10), (SZ_512 << 16) | (10 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(11), (SZ_512 << 16) | (11 * SZ_512)},
	/* 0x1800 */
	{ABOX_SPUS_SBANK_ASRC(0), (0x2c0 << 16) | (0x1800 + 0x000)},
	{ABOX_SPUS_SBANK_ASRC(1), (0x1a0 << 16) | (0x1800 + 0x2c0)},
	{ABOX_SPUS_SBANK_ASRC(2), (0x1a0 << 16) | (0x1800 + 0x460)},
	{ABOX_SPUS_SBANK_ASRC(3), (0x110 << 16) | (0x1800 + 0x600)},
	/* 0x2000 */
	{ABOX_SPUS_SBANK_ASRC(4), (0x2c0 << 16) | (0x2000 + 0x000)},
	{ABOX_SPUS_SBANK_ASRC(5), (0x1a0 << 16) | (0x2000 + 0x2c0)},
	{ABOX_SPUS_SBANK_ASRC(6), (0x1a0 << 16) | (0x2000 + 0x460)},
	{ABOX_SPUS_SBANK_ASRC(7), (0x110 << 16) | (0x2000 + 0x600)},
	/* 0x2800 */
	{ABOX_SPUS_SBANK_MIXP, (SZ_128 << 16) | 0x2800},
	{ABOX_SPUS_SBANK_SIDETONE, (SZ_512 << 16) | 0x2a00},

	/* 0x0000 */
	{ABOX_SPUM_SBANK_NSRC(0), (SZ_512 << 16) | (0 * SZ_512)},
	{ABOX_SPUM_SBANK_NSRC(1), (SZ_512 << 16) | (1 * SZ_512)},
	{ABOX_SPUM_SBANK_NSRC(2), (SZ_512 << 16) | (2 * SZ_512)},
	{ABOX_SPUM_SBANK_NSRC(3), (SZ_512 << 16) | (3 * SZ_512)},
	{ABOX_SPUM_SBANK_NSRC(4), (SZ_512 << 16) | (4 * SZ_512)},
	/* 0x0a00 */
	{ABOX_SPUM_SBANK_ASRC(0), (0x2c0 << 16) | (0x0a00 + 0x000)},
	{ABOX_SPUM_SBANK_ASRC(1), (0x1a0 << 16) | (0x0a00 + 0x2c0)},
	{ABOX_SPUM_SBANK_ASRC(2), (0x1a0 << 16) | (0x0a00 + 0x460)},
	{ABOX_SPUM_SBANK_ASRC(3), (0x190 << 16) | (0x0a00 + 0x600)},

	/* Set default volume to 1.0 */
	{ABOX_RDMA_VOL_FACTOR(0), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(1), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(2), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(3), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(4), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(5), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(6), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(7), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(8), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(9), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(10), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(11), 0x1 << 23},

	{ABOX_WDMA_VOL_FACTOR(0), 0x1 << 23},
	{ABOX_WDMA_VOL_FACTOR(1), 0x1 << 23},
	{ABOX_WDMA_VOL_FACTOR(2), 0x1 << 23},
	{ABOX_WDMA_VOL_FACTOR(3), 0x1 << 23},
	{ABOX_WDMA_VOL_FACTOR(4), 0x1 << 23},

	{ABOX_WDMA_DEBUG_VOL_FACTOR(0), 0x1 << 23},
	{ABOX_WDMA_DEBUG_VOL_FACTOR(1), 0x1 << 23},
	{ABOX_WDMA_DEBUG_VOL_FACTOR(2), 0x1 << 23},
	{ABOX_WDMA_DEBUG_VOL_FACTOR(3), 0x1 << 23},
	{ABOX_WDMA_DEBUG_VOL_FACTOR(4), 0x1 << 23},
	{ABOX_WDMA_DEBUG_VOL_FACTOR(5), 0x1 << 23},

	/* Set default RDMA DST_BIT_WIDTH to 16bit */
	{ABOX_RDMA_BIT_CTRL0(0x0), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0x1), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0x2), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0x3), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0x4), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0x5), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0x6), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0x7), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0x8), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0x9), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0xa), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0xb), 0x1},

	/* Set default WDMA DST_BIT_WIDTH to 16bit */
	{ABOX_WDMA_BIT_CTRL0(0x0), 0x1},
	{ABOX_WDMA_BIT_CTRL0(0x1), 0x1},
	{ABOX_WDMA_BIT_CTRL0(0x2), 0x1},
	{ABOX_WDMA_BIT_CTRL0(0x3), 0x1},
	{ABOX_WDMA_BIT_CTRL0(0x4), 0x1},

	/* Set default buffer configuration */
	{ABOX_RDMA_BUF_STR(0x0), IOVA_RDMA_BUFFER(0x0)},
	{ABOX_RDMA_BUF_END(0x0), IOVA_RDMA_BUFFER(0x0) + BUFFER_BYTES_MIN},
	{ABOX_RDMA_BUF_OFFSET(0x0), BUFFER_BYTES_MIN / 2},
	{ABOX_RDMA_STR_POINT(0x0), IOVA_RDMA_BUFFER(0x0)},

	{ABOX_RDMA_BUF_STR(0x1), IOVA_RDMA_BUFFER(0x1)},
	{ABOX_RDMA_BUF_END(0x1), IOVA_RDMA_BUFFER(0x1) + BUFFER_BYTES_MIN},
	{ABOX_RDMA_BUF_OFFSET(0x1), BUFFER_BYTES_MIN / 2},
	{ABOX_RDMA_STR_POINT(0x1), IOVA_RDMA_BUFFER(0x1)},

	{ABOX_RDMA_BUF_STR(0x2), IOVA_RDMA_BUFFER(0x2)},
	{ABOX_RDMA_BUF_END(0x2), IOVA_RDMA_BUFFER(0x2) + BUFFER_BYTES_MIN},
	{ABOX_RDMA_BUF_OFFSET(0x2), BUFFER_BYTES_MIN / 2},
	{ABOX_RDMA_STR_POINT(0x2), IOVA_RDMA_BUFFER(0x2)},

	{ABOX_RDMA_BUF_STR(0x3), IOVA_RDMA_BUFFER(0x3)},
	{ABOX_RDMA_BUF_END(0x3), IOVA_RDMA_BUFFER(0x3) + BUFFER_BYTES_MIN},
	{ABOX_RDMA_BUF_OFFSET(0x3), BUFFER_BYTES_MIN / 2},
	{ABOX_RDMA_STR_POINT(0x3), IOVA_RDMA_BUFFER(0x3)},

	{ABOX_RDMA_BUF_STR(0x4), IOVA_RDMA_BUFFER(0x4)},
	{ABOX_RDMA_BUF_END(0x4), IOVA_RDMA_BUFFER(0x4) + BUFFER_BYTES_MIN},
	{ABOX_RDMA_BUF_OFFSET(0x4), BUFFER_BYTES_MIN / 2},
	{ABOX_RDMA_STR_POINT(0x4), IOVA_RDMA_BUFFER(0x4)},

	{ABOX_RDMA_BUF_STR(0x5), IOVA_RDMA_BUFFER(0x5)},
	{ABOX_RDMA_BUF_END(0x5), IOVA_RDMA_BUFFER(0x5) + BUFFER_BYTES_MIN},
	{ABOX_RDMA_BUF_OFFSET(0x5), BUFFER_BYTES_MIN / 2},
	{ABOX_RDMA_STR_POINT(0x5), IOVA_RDMA_BUFFER(0x5)},

	{ABOX_RDMA_BUF_STR(0x6), IOVA_RDMA_BUFFER(0x6)},
	{ABOX_RDMA_BUF_END(0x6), IOVA_RDMA_BUFFER(0x6) + BUFFER_BYTES_MIN},
	{ABOX_RDMA_BUF_OFFSET(0x6), BUFFER_BYTES_MIN / 2},
	{ABOX_RDMA_STR_POINT(0x6), IOVA_RDMA_BUFFER(0x6)},

	{ABOX_RDMA_BUF_STR(0x7), IOVA_RDMA_BUFFER(0x7)},
	{ABOX_RDMA_BUF_END(0x7), IOVA_RDMA_BUFFER(0x7) + BUFFER_BYTES_MIN},
	{ABOX_RDMA_BUF_OFFSET(0x7), BUFFER_BYTES_MIN / 2},
	{ABOX_RDMA_STR_POINT(0x7), IOVA_RDMA_BUFFER(0x7)},

	{ABOX_RDMA_BUF_STR(0x8), IOVA_RDMA_BUFFER(0x8)},
	{ABOX_RDMA_BUF_END(0x8), IOVA_RDMA_BUFFER(0x8) + BUFFER_BYTES_MIN},
	{ABOX_RDMA_BUF_OFFSET(0x8), BUFFER_BYTES_MIN / 2},
	{ABOX_RDMA_STR_POINT(0x8), IOVA_RDMA_BUFFER(0x8)},

	{ABOX_RDMA_BUF_STR(0x9), IOVA_RDMA_BUFFER(0x9)},
	{ABOX_RDMA_BUF_END(0x9), IOVA_RDMA_BUFFER(0x9) + BUFFER_BYTES_MIN},
	{ABOX_RDMA_BUF_OFFSET(0x9), BUFFER_BYTES_MIN / 2},
	{ABOX_RDMA_STR_POINT(0x9), IOVA_RDMA_BUFFER(0x9)},

	{ABOX_RDMA_BUF_STR(0xa), IOVA_RDMA_BUFFER(0xa)},
	{ABOX_RDMA_BUF_END(0xa), IOVA_RDMA_BUFFER(0xa) + BUFFER_BYTES_MIN},
	{ABOX_RDMA_BUF_OFFSET(0xa), BUFFER_BYTES_MIN / 2},
	{ABOX_RDMA_STR_POINT(0xa), IOVA_RDMA_BUFFER(0xa)},

	{ABOX_RDMA_BUF_STR(0xb), IOVA_RDMA_BUFFER(0xb)},
	{ABOX_RDMA_BUF_END(0xb), IOVA_RDMA_BUFFER(0xb) + BUFFER_BYTES_MIN},
	{ABOX_RDMA_BUF_OFFSET(0xb), BUFFER_BYTES_MIN / 2},
	{ABOX_RDMA_STR_POINT(0xb), IOVA_RDMA_BUFFER(0xb)},

	{ABOX_WDMA_BUF_STR(0x0), IOVA_WDMA_BUFFER(0x0)},
	{ABOX_WDMA_BUF_END(0x0), IOVA_WDMA_BUFFER(0x0) + BUFFER_BYTES_MIN},
	{ABOX_WDMA_BUF_OFFSET(0x0), BUFFER_BYTES_MIN / 2},
	{ABOX_WDMA_STR_POINT(0x0), IOVA_WDMA_BUFFER(0x0)},

	{ABOX_WDMA_BUF_STR(0x1), IOVA_WDMA_BUFFER(0x1)},
	{ABOX_WDMA_BUF_END(0x1), IOVA_WDMA_BUFFER(0x1) + BUFFER_BYTES_MIN},
	{ABOX_WDMA_BUF_OFFSET(0x1), BUFFER_BYTES_MIN / 2},
	{ABOX_WDMA_STR_POINT(0x1), IOVA_WDMA_BUFFER(0x1)},

	{ABOX_WDMA_BUF_STR(0x2), IOVA_WDMA_BUFFER(0x2)},
	{ABOX_WDMA_BUF_END(0x2), IOVA_WDMA_BUFFER(0x2) + BUFFER_BYTES_MIN},
	{ABOX_WDMA_BUF_OFFSET(0x2), BUFFER_BYTES_MIN / 2},
	{ABOX_WDMA_STR_POINT(0x2), IOVA_WDMA_BUFFER(0x2)},

	{ABOX_WDMA_BUF_STR(0x3), IOVA_WDMA_BUFFER(0x3)},
	{ABOX_WDMA_BUF_END(0x3), IOVA_WDMA_BUFFER(0x3) + BUFFER_BYTES_MIN},
	{ABOX_WDMA_BUF_OFFSET(0x3), BUFFER_BYTES_MIN / 2},
	{ABOX_WDMA_STR_POINT(0x3), IOVA_WDMA_BUFFER(0x3)},

	{ABOX_WDMA_BUF_STR(0x4), IOVA_WDMA_BUFFER(0x4)},
	{ABOX_WDMA_BUF_END(0x4), IOVA_WDMA_BUFFER(0x4) + BUFFER_BYTES_MIN},
	{ABOX_WDMA_BUF_OFFSET(0x4), BUFFER_BYTES_MIN / 2},
	{ABOX_WDMA_STR_POINT(0x4), IOVA_WDMA_BUFFER(0x4)},
};

static const struct reg_sequence patch_9630[] = {
	/* 0x0000 */
	{ABOX_SPUS_SBANK_RDMA(0), (SZ_512 << 16) | (0 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(1), (SZ_512 << 16) | (1 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(2), (SZ_512 << 16) | (2 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(3), (SZ_512 << 16) | (3 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(4), (SZ_512 << 16) | (4 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(5), (SZ_512 << 16) | (5 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(6), (SZ_512 << 16) | (6 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(7), (SZ_512 << 16) | (7 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(8), (SZ_512 << 16) | (8 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(9), (SZ_512 << 16) | (9 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(10), (SZ_512 << 16) | (10 * SZ_512)},
	{ABOX_SPUS_SBANK_RDMA(11), (SZ_512 << 16) | (11 * SZ_512)},
	/* 0x1800 */
	{ABOX_SPUS_SBANK_ASRC(0), (0x2c0 << 16) | (0x1800 + 0x000)},
	{ABOX_SPUS_SBANK_ASRC(1), (0x1a0 << 16) | (0x1800 + 0x2c0)},
	{ABOX_SPUS_SBANK_ASRC(2), (0x1a0 << 16) | (0x1800 + 0x460)},
	{ABOX_SPUS_SBANK_ASRC(3), (0x110 << 16) | (0x1800 + 0x600)},
	/* 0x2000 */
	{ABOX_SPUS_SBANK_ASRC(4), (0x2c0 << 16) | (0x2000 + 0x000)},
	{ABOX_SPUS_SBANK_ASRC(5), (0x1a0 << 16) | (0x2000 + 0x2c0)},
	{ABOX_SPUS_SBANK_ASRC(6), (0x1a0 << 16) | (0x2000 + 0x460)},
	{ABOX_SPUS_SBANK_ASRC(7), (0x110 << 16) | (0x2000 + 0x600)},
	/* 0x2800 */
	{ABOX_SPUS_SBANK_MIXP, (SZ_128 << 16) | 0x2800},
	{ABOX_SPUS_SBANK_SIDETONE, (SZ_512 << 16) | 0x2a00},

	/* 0x0000 */
	{ABOX_SPUM_SBANK_NSRC(0), (SZ_512 << 16) | (0 * SZ_512)},
	{ABOX_SPUM_SBANK_NSRC(1), (SZ_512 << 16) | (1 * SZ_512)},
	{ABOX_SPUM_SBANK_NSRC(2), (SZ_512 << 16) | (2 * SZ_512)},
	{ABOX_SPUM_SBANK_NSRC(3), (SZ_512 << 16) | (3 * SZ_512)},
	{ABOX_SPUM_SBANK_NSRC(4), (SZ_512 << 16) | (4 * SZ_512)},
	/* 0x0a00 */
	{ABOX_SPUM_SBANK_ASRC(0), (0x2c0 << 16) | (0x0a00 + 0x000)},
	{ABOX_SPUM_SBANK_ASRC(1), (0x1a0 << 16) | (0x0a00 + 0x2c0)},
	{ABOX_SPUM_SBANK_ASRC(2), (0x1a0 << 16) | (0x0a00 + 0x460)},
	{ABOX_SPUM_SBANK_ASRC(3), (0x190 << 16) | (0x0a00 + 0x600)},

	/* Set default volume to 1.0 */
	{ABOX_RDMA_VOL_FACTOR(0), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(1), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(2), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(3), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(4), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(5), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(6), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(7), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(8), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(9), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(10), 0x1 << 23},
	{ABOX_RDMA_VOL_FACTOR(11), 0x1 << 23},

	{ABOX_WDMA_VOL_FACTOR(0), 0x1 << 23},
	{ABOX_WDMA_VOL_FACTOR(1), 0x1 << 23},
	{ABOX_WDMA_VOL_FACTOR(2), 0x1 << 23},
	{ABOX_WDMA_VOL_FACTOR(3), 0x1 << 23},
	{ABOX_WDMA_VOL_FACTOR(4), 0x1 << 23},

	{ABOX_WDMA_DEBUG_VOL_FACTOR(0), 0x1 << 23},
	{ABOX_WDMA_DEBUG_VOL_FACTOR(1), 0x1 << 23},
	{ABOX_WDMA_DEBUG_VOL_FACTOR(2), 0x1 << 23},
	{ABOX_WDMA_DEBUG_VOL_FACTOR(3), 0x1 << 23},
	{ABOX_WDMA_DEBUG_VOL_FACTOR(4), 0x1 << 23},
	{ABOX_WDMA_DEBUG_VOL_FACTOR(5), 0x1 << 23},

	/* Set default RDMA DST_BIT_WIDTH to 16bit */
	{ABOX_RDMA_BIT_CTRL0(0x0), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0x1), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0x2), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0x3), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0x4), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0x5), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0x6), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0x7), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0x8), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0x9), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0xa), 0x1},
	{ABOX_RDMA_BIT_CTRL0(0xb), 0x1},

	/* Set default WDMA DST_BIT_WIDTH to 16bit */
	{ABOX_WDMA_BIT_CTRL0(0x0), 0x1},
	{ABOX_WDMA_BIT_CTRL0(0x1), 0x1},
	{ABOX_WDMA_BIT_CTRL0(0x2), 0x1},
	{ABOX_WDMA_BIT_CTRL0(0x3), 0x1},
	{ABOX_WDMA_BIT_CTRL0(0x4), 0x1},
};

static struct regmap_config regmap_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,
	.max_register = ABOX_MAX_REGISTERS,
	.cache_type = REGCACHE_RBTREE,
	.fast_io = true,
};

struct regmap *abox_soc_get_regmap(struct device *adev)
{
	struct abox_data *data = dev_get_drvdata(adev);
	struct regmap *regmap;
	const struct reg_sequence *regs = NULL;
	int num_regs = 0;

	if (!IS_ERR_OR_NULL(data->regmap))
		return data->regmap;

	if (IS_ENABLED(CONFIG_SOC_EXYNOS8895)) {
		regmap_config.reg_defaults = reg_defaults_8895;
		regmap_config.num_reg_defaults = ARRAY_SIZE(reg_defaults_8895);
		regmap_config.volatile_reg = volatile_reg_legacy;
		regmap_config.readable_reg = readable_reg_legacy;
		regmap_config.writeable_reg = writeable_reg_legacy;
		regs = patch_legacy;
		num_regs = ARRAY_SIZE(patch_legacy);
	} else if (IS_ENABLED(CONFIG_SOC_EXYNOS9810)) {
		regmap_config.reg_defaults = reg_defaults_9810;
		regmap_config.num_reg_defaults = ARRAY_SIZE(reg_defaults_9810);
		regmap_config.volatile_reg = volatile_reg_legacy;
		regmap_config.readable_reg = readable_reg_legacy;
		regmap_config.writeable_reg = writeable_reg_legacy;
		regs = patch_legacy;
		num_regs = ARRAY_SIZE(patch_legacy);
	} else if (IS_ENABLED(CONFIG_SOC_EXYNOS9820)) {
		regmap_config.reg_defaults = reg_defaults_9820;
		regmap_config.num_reg_defaults = ARRAY_SIZE(reg_defaults_9820);
		regmap_config.volatile_reg = volatile_reg_9820;
		regmap_config.readable_reg = readable_reg_9820;
		regmap_config.writeable_reg = writeable_reg_9820;
		regs = patch_9820;
		num_regs = ARRAY_SIZE(patch_9820);
	} else if (IS_ENABLED(CONFIG_SOC_EXYNOS9830)) {
		/* Reading back mechanism of regmap cache is used. */
		regmap_config.num_reg_defaults_raw = ABOX_MAX_REGISTERS + 1;
		regmap_config.volatile_reg = volatile_reg_9830;
		regmap_config.readable_reg = readable_reg_9830;
		regmap_config.writeable_reg = writeable_reg_9830;
		regs = patch_9830;
		num_regs = ARRAY_SIZE(patch_9830);
	} else if (IS_ENABLED(CONFIG_SOC_EXYNOS9630)) {
		/* Reading back mechanism of regmap cache is used. */
		regmap_config.num_reg_defaults_raw = ABOX_MAX_REGISTERS + 1;
		regmap_config.volatile_reg = volatile_reg_9630;
		regmap_config.readable_reg = readable_reg_9630;
		regmap_config.writeable_reg = writeable_reg_9630;
		regs = patch_9630;
		num_regs = ARRAY_SIZE(patch_9630);
	} else {
		BUG_ON(1);
	}

	regmap = devm_regmap_init_mmio(adev, data->sfr_base, &regmap_config);
	if (regs)
		regmap_multi_reg_write(regmap, regs, num_regs);

	return regmap;
}