/* * s2mpu13-private.h - Voltage regulator driver for the s2mpu13 * * Copyright (C) 2020 Samsung Electrnoics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __LINUX_MFD_S2MPU13_REGULATOR_H #define __LINUX_MFD_S2MPU13_REGULATOR_H #include #if IS_ENABLED(CONFIG_S2MPU13_ADC) #include #include #include #include #endif #define S2MPU13_REG_INVALID (0xFF) /* PMIC COMMON(Top-Level) Registers addr*/ #define S2MPU13_PMIC_REG_VGPIO0 0x00 #define S2MPU13_PMIC_REG_VGPIO1 0x01 #define S2MPU13_PMIC_REG_VGPIO2 0x02 #define S2MPU13_PMIC_REG_VGPIO3 0x03 #define S2MPU13_PMIC_REG_DYN_ADDR 0x04 #define S2MPU13_PMIC_REG_PMIC_ID 0x0D #define S2MPU13_PMIC_REG_I3C_CONFIG 0x0E #define S2MPU13_PMIC_REG_I3C_STSA 0x0F #define S2MPU13_PMIC_REG_IRQM 0x10 /* IRQM reg */ #define S2MPU13_PMIC_PM_IRQM (1 << 0) /* PMIC CHIP ID */ #define CHIP_ID_MASK (0x0F) /* GPIO */ #define S2MPU13_GPIO_SETH (0x05) #define S2MPU13_GPIO_SET2 (0x06) #define S2MPU13_GPIO_SET3 (0x07) #define S2MPU13_GPIO_SET4 (0x08) #define S2MPU13_GPIO_SET1 (0x09) #define S2MPU13_GPIO_SET6 (0x0A) #define S2MPU13_GPIO_SET7 (0x0B) #define S2MPU13_GPIO_SET8 (0x0C) /* IBI table check*/ #define S2MPU13_IBI0_PMIC_S (1 << 0) #define S2MPU13_IBI0_PMIC_M (1 << 4) #define S2MPU13_IBI1_ADC (1 << 0) #define S2MPU13_IBI1_DCXO (1 << 1) #define S2MPU13_IBI1_ONOB (1 << 7) /* PMIC Registers */ #define S2MPU13_PMIC_REG_INT1 0x00 #define S2MPU13_PMIC_REG_INT2 0x01 #define S2MPU13_PMIC_REG_INT3 0x02 #define S2MPU13_PMIC_REG_INT4 0x03 #define S2MPU13_PMIC_REG_INT5 0x04 #define S2MPU13_PMIC_REG_INT6 0x05 #define S2MPU13_PMIC_REG_INT7 0x06 #define S2MPU13_PMIC_REG_INT1M 0x07 #define S2MPU13_PMIC_REG_INT2M 0x08 #define S2MPU13_PMIC_REG_INT3M 0x09 #define S2MPU13_PMIC_REG_INT4M 0x0A #define S2MPU13_PMIC_REG_INT5M 0x0B #define S2MPU13_PMIC_REG_INT6M 0x0C #define S2MPU13_PMIC_REG_INT7M 0x0D #define S2MPU13_PMIC_REG_STATUS1 0x0E #define S2MPU13_PMIC_REG_STATUS2 0x0F #define S2MPU13_PMIC_REG_PWRONSRC 0x10 #define S2MPU13_PMIC_REG_OFFSRC1 0x11 #define S2MPU13_PMIC_REG_OFFSRC2 0x12 #define S2MPU13_PMIC_REG_OFFSRC1_2 0x13 #define S2MPU13_PMIC_REG_OFFSRC2_2 0x14 #define S2MPU13_PMIC_REG_OFFSRC1_3 0x15 #define S2MPU13_PMIC_REG_OFFSRC2_3 0x16 #define S2MPU13_PMIC_REG_BUCHG 0x17 #define S2MPU13_PMIC_REG_RTCBUF 0x18 #define S2MPU13_PMIC_REG_CTRL1 0x19 #define S2MPU13_PMIC_REG_CTRL2 0x1A #define S2MPU13_PMIC_REG_CTRL3 0x1B #define S2MPU13_PMIC_REG_UVLO_OTP 0x1C #define S2MPU13_PMIC_REG_CFG1 0x1D #define S2MPU13_PMIC_REG_CFG2 0x1E #define S2MPU13_PMIC_REG_B1M_CTRL 0x1F #define S2MPU13_PMIC_REG_B1M_OUT1 0x20 #define S2MPU13_PMIC_REG_B1M_OUT2 0x21 #define S2MPU13_PMIC_REG_B2M_CTRL 0x22 #define S2MPU13_PMIC_REG_B2M_OUT1 0x23 #define S2MPU13_PMIC_REG_B2M_OUT2 0x24 #define S2MPU13_PMIC_REG_B3M_CTRL 0x25 #define S2MPU13_PMIC_REG_B3M_OUT1 0x26 #define S2MPU13_PMIC_REG_B3M_OUT2 0x27 #define S2MPU13_PMIC_REG_B4M_CTRL 0x28 #define S2MPU13_PMIC_REG_B4M_OUT1 0x29 #define S2MPU13_PMIC_REG_B4M_OUT2 0x2A #define S2MPU13_PMIC_REG_B5M_CTRL 0x2B #define S2MPU13_PMIC_REG_B5M_OUT1 0x2C #define S2MPU13_PMIC_REG_B5M_OUT2 0x2D #define S2MPU13_PMIC_REG_B6M_CTRL 0x2E #define S2MPU13_PMIC_REG_B6M_OUT1 0x2F #define S2MPU13_PMIC_REG_B6M_OUT2 0x30 #define S2MPU13_PMIC_REG_B7M_CTRL 0x31 #define S2MPU13_PMIC_REG_B7M_OUT1 0x32 #define S2MPU13_PMIC_REG_B7M_OUT2 0x33 #define S2MPU13_PMIC_REG_B8M_CTRL 0x34 #define S2MPU13_PMIC_REG_B8M_OUT1 0x35 #define S2MPU13_PMIC_REG_B8M_OUT2 0x36 #define S2MPU13_PMIC_REG_B9M_CTRL 0x37 #define S2MPU13_PMIC_REG_B9M_OUT1 0x38 #define S2MPU13_PMIC_REG_B9M_OUT2 0x39 #define S2MPU13_PMIC_REG_B10M_CTRL 0x3A #define S2MPU13_PMIC_REG_B10M_OUT1 0x3B #define S2MPU13_PMIC_REG_B10M_OUT2 0x3C #define S2MPU13_PMIC_REG_AVP_CTRL 0x3D #define S2MPU13_PMIC_REG_BUCK_RAMP_UP1M 0x3E #define S2MPU13_PMIC_REG_BUCK_RAMP_UP2M 0x3F #define S2MPU13_PMIC_REG_BUCK_RAMP_UP3M 0x40 #define S2MPU13_PMIC_REG_LDO_RAMP_UP1M 0x41 #define S2MPU13_PMIC_REG_LDO_RAMP_UP2M 0x42 #define S2MPU13_PMIC_REG_BUCK_RAMP_DN1M 0x43 #define S2MPU13_PMIC_REG_BUCK_RAMP_DN2M 0x44 #define S2MPU13_PMIC_REG_BUCK_RAMP_DN3M 0x45 #define S2MPU13_PMIC_REG_LDO_RAMP_DN1M 0x46 #define S2MPU13_PMIC_REG_LDO_RAMP_DN2M 0x47 #define S2MPU13_PMIC_REG_L1CTRL 0x48 #define S2MPU13_PMIC_REG_L2CTRL 0x49 #define S2MPU13_PMIC_REG_L3CTRL 0x4A #define S2MPU13_PMIC_REG_L4CTRL 0x4B #define S2MPU13_PMIC_REG_L5CTRL1 0x4C #define S2MPU13_PMIC_REG_L5CTRL2 0x4D #define S2MPU13_PMIC_REG_L6CTRL 0x4E #define S2MPU13_PMIC_REG_L7CTRL 0x4F #define S2MPU13_PMIC_REG_L8CTRL 0x50 #define S2MPU13_PMIC_REG_L9CTRL 0x51 #define S2MPU13_PMIC_REG_L10CTRL 0x52 #define S2MPU13_PMIC_REG_L11CTRL 0x53 #define S2MPU13_PMIC_REG_L12CTRL 0x54 #define S2MPU13_PMIC_REG_L13CTRL 0x55 #define S2MPU13_PMIC_REG_L14CTRL 0x56 #define S2MPU13_PMIC_REG_L15CTRL 0x57 #define S2MPU13_PMIC_REG_L16CTRL 0x58 #define S2MPU13_PMIC_REG_L17CTRL 0x59 #define S2MPU13_PMIC_REG_L18CTRL 0x5A #define S2MPU13_PMIC_REG_L19CTRL 0x5B #define S2MPU13_PMIC_REG_L20CTRL 0x5C #define S2MPU13_PMIC_REG_L21CTRL1 0x5D #define S2MPU13_PMIC_REG_L21CTRL2 0x5E #define S2MPU13_PMIC_REG_L22CTRL 0x5F #define S2MPU13_PMIC_REG_L23CTRL 0x60 #define S2MPU13_PMIC_REG_L24CTRL 0x61 #define S2MPU13_PMIC_REG_L25CTRL 0x62 #define S2MPU13_PMIC_REG_L26CTRL 0x63 #define S2MPU13_PMIC_REG_L27CTRL 0x64 #define S2MPU13_PMIC_REG_L28CTRL 0x65 #define S2MPU13_PMIC_REG_LDO_DSCH1 0x66 #define S2MPU13_PMIC_REG_LDO_DSCH2 0x67 #define S2MPU13_PMIC_REG_LDO_DSCH3 0x68 #define S2MPU13_PMIC_REG_LDO_DSCH4 0x69 #define S2MPU13_PMIC_REG_LDO_DSCH5 0x6A #define S2MPU13_PMIC_REG_LDO_DSCH6 0x6B #define S2MPU13_PMIC_REG_SEL_VGPIO0M 0x6C #define S2MPU13_PMIC_REG_SEL_VGPIO1M 0x6D #define S2MPU13_PMIC_REG_SEL_VGPIO2M 0x6E #define S2MPU13_PMIC_REG_SEL_VGPIO3M 0x6F #define S2MPU13_PMIC_REG_SEL_VGPIO4M 0x70 #define S2MPU13_PMIC_REG_SEL_VGPIO5M 0x71 #define S2MPU13_PMIC_REG_SEL_VGPIO6M 0x72 #define S2MPU13_PMIC_REG_SEL_VGPIO7M 0x73 #define S2MPU13_PMIC_REG_SEL_VGPIO8M 0x74 #define S2MPU13_PMIC_REG_SEL_VGPIO9M 0x75 #define S2MPU13_PMIC_REG_SEL_VGPIO10M 0x76 #define S2MPU13_PMIC_REG_SEL_VGPIO11M 0x77 #define S2MPU13_PMIC_REG_SEL_VGPIO12M 0x78 #define S2MPU13_PMIC_REG_SEL_VGPIO13M 0x79 #define S2MPU13_PMIC_REG_SEL_VGPIO14M 0x7A #define S2MPU13_PMIC_REG_SEL_VGPIO15M 0x7B #define S2MPU13_PMIC_REG_SEL_VGPIO16M 0x7C #define S2MPU13_PMIC_REG_SEL_VGPIO17M 0x7D #define S2MPU13_PMIC_REG_SEL_VGPIO18M 0x7E #define S2MPU13_PMIC_REG_SEL_DVS_EN0M 0x7F #define S2MPU13_PMIC_REG_SEL_DVS_EN1M 0x80 #define S2MPU13_PMIC_REG_SEL_DVS_EN2M 0x81 #define S2MPU13_PMIC_REG_SEL_DVS_EN3M 0x82 #define S2MPU13_PMIC_REG_ONSEQ_CTRL1M 0x83 #define S2MPU13_PMIC_REG_ONSEQ_CTRL2M 0x84 #define S2MPU13_PMIC_REG_ONSEQ_CTRL3M 0x85 #define S2MPU13_PMIC_REG_ONSEQ_CTRL4M 0x86 #define S2MPU13_PMIC_REG_ONSEQ_CTRL5M 0x87 #define S2MPU13_PMIC_REG_ONSEQ_CTRL6M 0x88 #define S2MPU13_PMIC_REG_ONSEQ_CTRL7M 0x89 #define S2MPU13_PMIC_REG_ONSEQ_CTRL8M 0x8A #define S2MPU13_PMIC_REG_ONSEQ_CTRL9M 0x8B #define S2MPU13_PMIC_REG_ONSEQ_CTRL10M 0x8C #define S2MPU13_PMIC_REG_ONSEQ_CTRL11M 0x8D #define S2MPU13_PMIC_REG_ONSEQ_CTRL12M 0x8E #define S2MPU13_PMIC_REG_ONSEQ_CTRL13M 0x8F #define S2MPU13_PMIC_REG_ONSEQ_CTRL14M 0x90 #define S2MPU13_PMIC_REG_ONSEQ_CTRL15M 0x91 #define S2MPU13_PMIC_REG_ONSEQ_CTRL16M 0x92 #define S2MPU13_PMIC_REG_ONSEQ_CTRL17M 0x93 #define S2MPU13_PMIC_REG_ONSEQ_CTRL18M 0x94 #define S2MPU13_PMIC_REG_ONSEQ_CTRL19M 0x95 #define S2MPU13_PMIC_REG_ONSEQ_CTRL20M 0x96 #define S2MPU13_PMIC_REG_ONSEQ_CTRL21M 0x97 #define S2MPU13_PMIC_REG_ONSEQ_CTRL22M 0x98 #define S2MPU13_PMIC_REG_ONSEQ_CTRL23M 0x99 #define S2MPU13_PMIC_REG_ONSEQ_CTRL24M 0x9A #define S2MPU13_PMIC_REG_ONSEQ_CTRL25M 0x9B #define S2MPU13_PMIC_REG_ONSEQ_CTRL26M 0x9C #define S2MPU13_PMIC_REG_ONSEQ_CTRL27M 0x9D #define S2MPU13_PMIC_REG_ONSEQ_CTRL28M 0x9E #define S2MPU13_PMIC_REG_ONSEQ_CTRL29M 0x9F #define S2MPU13_PMIC_REG_ONSEQ_CTRL30M 0xA0 #define S2MPU13_PMIC_REG_ONSEQ_CTRL31M 0xA1 #define S2MPU13_PMIC_REG_ONSEQ_CTRL32M 0xA2 #define S2MPU13_PMIC_REG_OFF_CTRL1M 0xA3 #define S2MPU13_PMIC_REG_OFF_CTRL2M 0xA4 #define S2MPU13_PMIC_REG_OFF_CTRL3M 0xA5 #define S2MPU13_PMIC_REG_OFF_CTRL4M 0xA6 #define S2MPU13_PMIC_REG_OFF_CTRL5M 0xA7 #define S2MPU13_PMIC_REG_OFF_SEQ_CTRL1M 0xA8 #define S2MPU13_PMIC_REG_OFF_SEQ_CTRL2M 0xA9 #define S2MPU13_PMIC_REG_OFF_SEQ_CTRL3M 0xAA #define S2MPU13_PMIC_REG_OFF_SEQ_CTRL4M 0xAB #define S2MPU13_PMIC_REG_OFF_SEQ_CTRL5M 0xAC #define S2MPU13_PMIC_REG_OFF_SEQ_CTRL6M 0xAD #define S2MPU13_PMIC_REG_OFF_SEQ_CTRL7M 0xAE #define S2MPU13_PMIC_REG_OFF_SEQ_CTRL8M 0xAF #define S2MPU13_PMIC_REG_OFF_SEQ_CTRL9M 0xB0 #define S2MPU13_PMIC_REG_OFF_SEQ_CTRL10M 0xB1 #define S2MPU13_PMIC_REG_OFF_SEQ_CTRL11M 0xB2 #define S2MPU13_PMIC_REG_OFF_SEQ_CTRL12M 0xB3 #define S2MPU13_PMIC_REG_OFF_SEQ_CTRL13M 0xB4 #define S2MPU13_PMIC_REG_OFF_SEQ_CTRL14M 0xB5 #define S2MPU13_PMIC_REG_OFF_SEQ_CTRL15M 0xB6 #define S2MPU13_PMIC_REG_OFF_SEQ_CTRL16M 0xB7 #define S2MPU13_PMIC_REG_OFF_SEQ_CTRL17M 0xB8 #define S2MPU13_PMIC_REG_OFF_SEQ_CTRL18M 0xB9 #define S2MPU13_PMIC_REG_OFF_SEQ_CTRL19M 0xBA #define S2MPU13_PMIC_REG_SEQ_CTRL 0xBB #define S2MPU13_PMIC_REG_SUB_CTRL 0xBC #define S2MPU13_PMIC_REG_CFG_PM2 0xBD #define S2MPU13_PMIC_REG_AFM_WARN_B1M 0xBE #define S2MPU13_PMIC_REG_BUCK_OI_EN1M 0xBF #define S2MPU13_PMIC_REG_BUCK_OI_EN2M 0xC0 #define S2MPU13_PMIC_REG_BUCK_OI_PD_EN1M 0xC1 #define S2MPU13_PMIC_REG_BUCK_OI_PD_EN2M 0xC2 #define S2MPU13_PMIC_REG_BUCK_OI_CTRL1M 0xC3 #define S2MPU13_PMIC_REG_BUCK_OI_CTRL2M 0xC4 #define S2MPU13_PMIC_REG_BUCK_OI_CTRL3M 0xC5 #define S2MPU13_PMIC_REG_BUCK_OI_CTRL4M 0xC6 #define S2MPU13_PMIC_REG_BUCK_OI_CTRL5M 0xC7 #define S2MPU13_PMIC_REG_LDO_OI_EN_M 0xC8 #define S2MPU13_PMIC_REG_LDO_OI_PD_EN_M 0xC9 #define S2MPU13_PMIC_REG_LDO_OI_CTRL_M 0xCA #define S2MPU13_PMIC_REG_CFG_PM3 0xCF #define S2MPU13_PMIC_REG_PSI_CTRL0 0xD0 #define S2MPU13_PMIC_REG_PSI_CTRL1 0xD1 #define S2MPU13_PMIC_REG_PSI_CTRL2 0xD2 #define S2MPU13_PMIC_REG_OFF_SEQ_SKIP 0xD3 #define S2MPU13_PMIC_REG_SEL_HW_GPIO 0xD4 #define S2MPU13_PMIC_REG_CFG_PM4 0xD5 #define S2MPU13_PMIC_REG_CFG_PM5 0xD6 #define S2MPU13_PMIC_REG_REBOOT_OPTION 0xD7 #define S2MPU13_PMIC_REG_WDT_SET 0xD8 #define S2MPU13_PMIC_REG_PROT_CTRL 0xD9 #define S2MPU13_PMIC_REG_PWRONSRC2 0xDA #define S2MPU13_PMIC_REG_M_VGPIO0 0xF0 #define S2MPU13_PMIC_REG_M_VGPIO1 0xF1 #define S2MPU13_PMIC_REG_M_VGPIO2 0xF2 #define S2MPU13_PMIC_REG_M_VGPIO3 0xF3 #define S2MPU13_PMIC_REG_EXT_CTRL5 0xFB #define S2MPU13_PMIC_REG_EXT_CTRL4 0xFC #define S2MPU13_PMIC_REG_EXT_CTRL3 0xFD #define S2MPU13_PMIC_REG_EXT_CTRL2 0xFE #define S2MPU13_PMIC_REG_EXT_CTRL1 0xFF /* regulator mask */ #define BUCK_RAMP_MASK (0x03) #define LDO_RAMP_MASK (0x03) /* SEL_VGPIO (CONTROL_SEL) */ #define S2MPU13_SEL_VGPIO_NUM 19 #define S2MPU13_SEL_VGPIO_MAX_VAL (0xFF) #define S2MPU13_PWREN_CPUCL0_MASK 0x00 #define S2MPU13_PWREN_MIF_MASK 0x01 #define S2MPU13_PWREN_CP_MASK 0x02 #define S2MPU13_PWREN_CLK_MASK 0x03 #define S2MPU13_PWREN_G3D_MASK 0x04 #define S2MPU13_PWREN_RF0_MASK 0x05 #define S2MPU13_PWREN_GNSS_MASK 0x06 #define S2MPU13_PWREN_WLBT_MASK 0x07 #define S2MPU13_PWREN_CPUCL1_MASK 0x08 #define S2MPU13_PWREN_CPUCL2_MASK 0x09 #define S2MPU13_PWREN_NPU_MASK 0x0A #define S2MPU13_PWREN_CAM_MASK 0x0B #define S2MPU13_PWREN_RF1_MASK 0x0C #define S2MPU13_PWREN_NFC_MASK 0x0D #define S2MPU13_PWREN_RF0_GNSS_MASK 0x0E #define S2MPU13_PWREN_CLK_NFC_MASK 0x0F /* S2MPU13 regulator ids */ enum S2MPU13_regulators { S2MPU13_LDO1, S2MPU13_LDO2, //S2MPU13_LDO3, //S2MPU13_LDO4, //S2MPU13_LDO5, //S2MPU13_LDO6, S2MPU13_LDO7, //S2MPU13_LDO8, S2MPU13_LDO9, S2MPU13_LDO10, S2MPU13_LDO11, S2MPU13_LDO12, S2MPU13_LDO13, S2MPU13_LDO14, //S2MPU13_LDO15, //S2MPU13_LDO16, S2MPU13_LDO17, //S2MPU13_LDO18, //S2MPU13_LDO19, //S2MPU13_LDO20, S2MPU13_LDO21, S2MPU13_LDO22, S2MPU13_LDO23, //S2MPU13_LDO24, S2MPU13_LDO25, S2MPU13_LDO26, S2MPU13_LDO27, //S2MPU13_LDO28, S2MPU13_BUCK1, //S2MPU13_BUCK2, //S2MPU13_BUCK3, S2MPU13_BUCK4, S2MPU13_BUCK5, S2MPU13_BUCK6, //S2MPU13_BUCK7, S2MPU13_BUCK8, S2MPU13_BUCK9, S2MPU13_BUCK10, S2MPU13_REG_MAX, }; /* BUCKs 1M~7M */ #define S2MPU13_BUCK_MIN1 300000 #define S2MPU13_BUCK_STEP1 6250 /* BUCK 8M */ #define S2MPU13_BUCK_MIN2 300000 #define S2MPU13_BUCK_STEP2 6250 /* BUCK 9M */ #define S2MPU13_BUCK_MIN3 300000 #define S2MPU13_BUCK_STEP3 6250 /* BUCK 10M */ #define S2MPU13_BUCK_MIN4 600000 #define S2MPU13_BUCK_STEP4 12500 /* LDOs 4M/5M/6M/7M/9M/10M/21M */ #define S2MPU13_LDO_MIN1 300000 #define S2MPU13_LDO_STEP1 25000 /* LDOs 3M/8M */ #define S2MPU13_LDO_MIN2 425000 #define S2MPU13_LDO_STEP2 12500 /* LDOs 1M/11M/12M/15M/17M/18M */ #define S2MPU13_LDO_MIN3 725000 #define S2MPU13_LDO_STEP3 12500 /* LDOs 2M/13M/14M/16M/19M/20M/22M/23M/24M/25M/26M/27M/28M */ #define S2MPU13_LDO_MIN4 700000 #define S2MPU13_LDO_STEP4 25000 /* LDO/BUCK output voltage control */ #define S2MPU13_LDO_VSEL_MASK 0x3F /* LDO_CTRL reg */ #define S2MPU13_BUCK_VSEL_MASK 0xFF /* BUCK_OUT reg */ #define S2MPU13_LDO_N_VOLTAGES (S2MPU13_LDO_VSEL_MASK + 1) #define S2MPU13_BUCK_N_VOLTAGES (S2MPU13_BUCK_VSEL_MASK + 1) /* Buck/LDO Enable control [7:6] */ #define S2MPU13_ENABLE_SHIFT (0x06) #define S2MPU13_ENABLE_MASK (0x03 << S2MPU13_ENABLE_SHIFT) #define S2MPU13_SEL_VGPIO_ON (0x01 << S2MPU13_ENABLE_SHIFT) #define S2MPU13_SEL_VGPIO__NORMAL_ON (0x02 << S2MPU13_ENABLE_SHIFT) /* only LDO */ /* soft-start time */ #define S2MPU13_ENABLE_TIME_LDO 128 #define S2MPU13_ENABLE_TIME_BUCK 130 #define S2MPU13_REGULATOR_MAX (S2MPU13_REG_MAX) /* AFM_WARN reg */ #define S2MPU13_AFM_WARN_EN_SHIFT 7 #define S2MPU13_AFM_WARN_CNT_SHIFT 6 #define S2MPU13_AFM_WARN_DVS_MASK_SHIFT 5 #define S2MPU13_AFM_WARN_LV_SHIFT 0 /* VGPIO_RX_MONITOR ADDR. */ #define VGPIO_I3C_BASE 0x11A00000 #define VGPIO_MONITOR_ADDR 0x2414 /* VGPIO_PENDING_CLEAR */ #define SYSREG_VGPIO2AP 0x11A40000 #define INTC0_IPEND 0x0290 /* POWER-KEY MASK */ #define S2MPU13_STATUS1_PWRON (1 << 0) #define S2MPU13_FALLING_EDGE (1 << 1) /* INT1 reg */ #define S2MPU13_RISING_EDGE (1 << 0) /* INT1 reg */ /* * sec_opmode_data - regulator operation mode data * @id: regulator id * @mode: regulator operation mode */ enum s2mpu13_irq_source { S2MPU13_PMIC_INT1 = 0, S2MPU13_PMIC_INT2, S2MPU13_PMIC_INT3, S2MPU13_PMIC_INT4, S2MPU13_PMIC_INT5, S2MPU13_PMIC_INT6, S2MPU13_IRQ_GROUP_NR, }; #define S2MPU13_NUM_IRQ_PMIC_REGS 6 /* INT1 ~ INT6 */ #define S2MPU13_BUCK_MAX 10 /* BUCK 1M ~ 10M */ #define S2MPU13_TEMP_MAX 2 /* 140C, 120C */ #define S2MPU13_LDO_MAX 4 /* LDO 1M, 2M, 11M, 13M */ enum s2mpu13_irq { /* PMIC */ S2MPU13_PMIC_IRQ_PWRONF_INT1, S2MPU13_PMIC_IRQ_PWRONR_INT1, S2MPU13_PMIC_IRQ_JIGONBF_INT1, S2MPU13_PMIC_IRQ_JIGONBR_INT1, S2MPU13_PMIC_IRQ_ACOKF_INT1, S2MPU13_PMIC_IRQ_ACOKR_INT1, S2MPU13_PMIC_IRQ_PWRON1S_INT1, S2MPU13_PMIC_IRQ_MRB_INT1, S2MPU13_PMIC_IRQ_RTC60S_INT2, S2MPU13_PMIC_IRQ_RTCA1_INT2, S2MPU13_PMIC_IRQ_RTCA0_INT2, S2MPU13_PMIC_IRQ_SMPL_INT2, S2MPU13_PMIC_IRQ_RTC1S_INT2, S2MPU13_PMIC_IRQ_WTSR_INT2, S2MPU13_PMIC_IRQ_ADCDONE_INT2, S2MPU13_PMIC_IRQ_WRSTB_INT2, S2MPU13_PMIC_IRQ_OCP_B1M_INT3, S2MPU13_PMIC_IRQ_OCP_B2M_INT3, S2MPU13_PMIC_IRQ_OCP_B3M_INT3, S2MPU13_PMIC_IRQ_OCP_B4M_INT3, S2MPU13_PMIC_IRQ_OCP_B5M_INT3, S2MPU13_PMIC_IRQ_OCP_B6M_INT3, S2MPU13_PMIC_IRQ_OCP_B7M_INT3, S2MPU13_PMIC_IRQ_OCP_B8M_INT3, S2MPU13_PMIC_IRQ_OCP_B9M_INT4, S2MPU13_PMIC_IRQ_OCP_B10M_INT4, S2MPU13_PMIC_IRQ_SC_LDO1M_INT4, S2MPU13_PMIC_IRQ_SC_LDO2M_INT4, S2MPU13_PMIC_IRQ_SC_LDO11M_INT4, S2MPU13_PMIC_IRQ_SC_LDO13M_INT4, S2MPU13_PMIC_IRQ_OI_B1M_INT5, S2MPU13_PMIC_IRQ_OI_B2M_INT5, S2MPU13_PMIC_IRQ_OI_B3M_INT5, S2MPU13_PMIC_IRQ_OI_B4M_INT5, S2MPU13_PMIC_IRQ_OI_B5M_INT5, S2MPU13_PMIC_IRQ_OI_B6M_INT5, S2MPU13_PMIC_IRQ_OI_B7M_INT5, S2MPU13_PMIC_IRQ_OI_B8M_INT5, S2MPU13_PMIC_IRQ_OI_B9M_INT6, S2MPU13_PMIC_IRQ_OI_B10M_INT6, S2MPU13_PMIC_IRQ_INT120C_INT6, S2MPU13_PMIC_IRQ_INT140C_INT6, S2MPU13_PMIC_IRQ_TSD_INT6, S2MPU13_PMIC_IRQ_TIMEOUT2_INT6, S2MPU13_PMIC_IRQ_TIMEOUT3_INT6, S2MPU13_IRQ_NR, }; enum sec_device_type { S2MPU13X, }; struct s2mpu13_dev { struct device *dev; struct i2c_client *i2c; struct i2c_client *pmic; struct i2c_client *rtc; struct i2c_client *debug_i2c; struct mutex i2c_lock; struct apm_ops *ops; int type; int device_type; int irq; int irq_base; bool wakeup; struct mutex irqlock; int irq_masks_cur[S2MPU13_IRQ_GROUP_NR]; int irq_masks_cache[S2MPU13_IRQ_GROUP_NR]; /* pmic VER/REV register */ u8 pmic_rev; /* pmic Rev */ struct s2mpu13_platform_data *pdata; /* VGPIO_RX_MONITOR */ void __iomem *mem_base; void __iomem *sysreg_pending; /* Work queue */ struct workqueue_struct *irq_wqueue; struct delayed_work irq_work; #if IS_ENABLED(CONFIG_S2MPU13_ADC) struct i2c_client *adc_i2c; #endif struct i2c_client *gpio_i2c; }; enum s2mpu13_types { TYPE_S2MPU13, }; /* INSTACOK API */ extern int s2mpu13_set_instacok(void); /* Reboot_option API */ extern int s2mpu13_set_reboot_option(void); extern int s2mpu13_irq_init(struct s2mpu13_dev *s2mpu13); extern void s2mpu13_irq_exit(struct s2mpu13_dev *s2mpu13); /* GPIO API function */ extern int s2mpu13_write_gpio(unsigned char reg, unsigned char value); extern int s2mpu13_read_gpio(unsigned char reg, unsigned char *dest); /* S2MPU13 shared i2c API function */ extern int s2mpu13_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest); extern int s2mpu13_bulk_read(struct i2c_client *i2c, u8 reg, int count, u8 *buf); extern int s2mpu13_write_reg(struct i2c_client *i2c, u8 reg, u8 value); extern int s2mpu13_bulk_write(struct i2c_client *i2c, u8 reg, int count, u8 *buf); extern int s2mpu13_write_word(struct i2c_client *i2c, u8 reg, u16 value); extern int s2mpu13_read_word(struct i2c_client *i2c, u8 reg); extern int s2mpu13_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask); extern int pmic_read_pwrkey_status(void); #if IS_ENABLED(CONFIG_MFD_S2MPU14) extern void s2mpu14_call_notifier(void); extern int s2mpu14_power_off_wa(void); #endif #endif /* __LINUX_MFD_S2MPU13_REGULATOR_H */