#ifndef __CMUCAL_QCH_H__ #define __CMUCAL_QCH_H__ #include "../cmucal.h" enum qch_id { ALIVE_CMU_ALIVE_QCH = QCH_TYPE, APBIF_PMU_ALIVE_QCH, APBIF_RTC_QCH, APBIF_SYSREG_VGPIO2AP_QCH, APBIF_SYSREG_VGPIO2APM_QCH, APBIF_SYSREG_VGPIO2PMU_QCH, APBIF_TOP_RTC_QCH, CLKMON_QCH, DBGCORE_UART_QCH, DOUBLE_IP_BATCHER_QCH_APM, DOUBLE_IP_BATCHER_QCH_CPU, DOUBLE_IP_BATCHER_QCH_SEMA, DTZPC_ALIVE_QCH, GPIO_ALIVE_QCH, GREBEINTEGRATION_QCH_GREBE, GREBEINTEGRATION_QCH_DBG, HW_SCANDUMP_CLKSTOP_CTRL_QCH, I3C_PMIC_QCH_P, I3C_PMIC_QCH_S, INTMEM_QCH, LHM_AXI_C_MODEM_QCH, LHM_AXI_C_VTS_QCH, LHM_AXI_P_APM_QCH, LHS_AXI_C_CMGP_QCH, LHS_AXI_D_APM_QCH, LHS_AXI_G_DBGCORE_QCH, LHS_AXI_G_SCAN2DRAM_QCH, LHS_AXI_LP_VTS_QCH, MAILBOX_APM_AP_QCH, MAILBOX_APM_CP_QCH, MAILBOX_AP_CP_QCH, MAILBOX_AP_CP_S_QCH, MAILBOX_AP_DBGCORE_QCH, PEM_QCH, PMU_INTR_GEN_QCH, ROM_CRC32_HOST_QCH, RSTNSYNC_CLK_ALIVE_GREBE_QCH, RSTNSYNC_CLK_ALIVE_GREBE_DBGCORE_QCH, SS_DBGCORE_QCH_GREBE, SS_DBGCORE_QCH_DBG, SWEEPER_P_ALIVE_QCH, SYSREG_ALIVE_QCH, VGEN_LITE_ALIVE_QCH, WDT_ALIVE_QCH, ABOX_QCH_ACLK, ABOX_QCH_BCLK_DSIF, ABOX_QCH_BCLK0, ABOX_QCH_BCLK1, ABOX_QCH_BCLK2, ABOX_QCH_BCLK3, ABOX_QCH_CPU, ABOX_QCH_BCLK4, ABOX_QCH_CNT, ABOX_QCH_BCLK5, ABOX_QCH_CCLK_ASB, ABOX_QCH_SCLK, ABOX_QCH_BCLK6, ABOX_QCH_XCLK, ABOX_QCH_PCMC_CLK, ABOX_QCH_C2A0, ABOX_QCH_C2A1, AUD_CMU_AUD_QCH, BAAW_D_AUDVTS_QCH, D_TZPC_AUD_QCH, LHM_AXI_D_HSI0AUD_QCH, LHM_AXI_P_AUD_QCH, LHS_AXI_D_AUD_QCH, LHS_AXI_D_AUDHSI0_QCH, LHS_AXI_D_AUDVTS_QCH, MAILBOX_AUD0_QCH, MAILBOX_AUD1_QCH, MAILBOX_AUD2_QCH, MAILBOX_AUD3_QCH, PPMU_AUD_QCH, RSTNSYNC_CLK_AUD_CPU0_SW_RESET_QCH, RSTNSYNC_CLK_AUD_CPU1_SW_RESET_QCH, RSTNSYNC_CLK_AUD_CPU_PCLKDBG_QCH, SMMU_AUD_QCH_S1, SMMU_AUD_QCH_S2, SYSREG_AUD_QCH, TREX_AUD_QCH, VGEN_LITE_AUD_QCH, WDT_AUD_QCH, ASYNCSFR_WR_SMC_QCH, BAAW_P_VPC_QCH, BUS0_CMU_BUS0_QCH, BUSIF_CMUTOPC_QCH, CACHEAID_BUS0_QCH, CMU_BUS0_CMUREF_QCH, D_TZPC_BUS0_QCH, LHM_ACEL_D0_VPC_QCH, LHM_ACEL_D1_VPC_QCH, LHM_ACEL_D2_VPC_QCH, LHM_AXI_D0_NPUS_QCH, LHM_AXI_D1_NPUS_QCH, LHM_AXI_D2_NPUS_QCH, LHS_AXI_P_MIF0_QCH, LHS_AXI_P_MIF1_QCH, LHS_AXI_P_MIF2_QCH, LHS_AXI_P_MIF3_QCH, LHS_AXI_P_NPU00_QCH, LHS_AXI_P_NPU01_QCH, LHS_AXI_P_NPU10_QCH, LHS_AXI_P_NPUS_QCH, LHS_AXI_P_PERIC0_QCH, LHS_AXI_P_PERIC2_QCH, LHS_AXI_P_PERISGIC_QCH, LHS_AXI_P_VPC_QCH, SYSREG_BUS0_QCH, TREX_D0_BUS0_QCH, TREX_D1_BUS0_QCH, TREX_P_BUS0_QCH, BAAW_P_VTS_QCH, BUS1_CMU_BUS1_QCH, CMU_BUS1_CMUREF_QCH, DIT_QCH, D_TZPC_BUS1_QCH, LHM_ACEL_D_HSI0_QCH, LHM_AXI_D0_DPUF0_QCH, LHM_AXI_D0_DPUF1_QCH, LHM_AXI_D1_DPUF0_QCH, LHM_AXI_D1_DPUF1_QCH, LHM_AXI_D_APM_QCH, LHM_AXI_D_SBIC_QCH, LHM_AXI_D_VTS_QCH, LHS_AXI_D_SBIC_QCH, LHS_AXI_P_DPUB_QCH, LHS_AXI_P_DPUF0_QCH, LHS_AXI_P_DPUF1_QCH, LHS_AXI_P_HSI0_QCH, LHS_AXI_P_VTS_QCH, PDMA_QCH, QE_PDMA_QCH, QE_SPDMA_QCH, SBIC_QCH, SPDMA_QCH, SYSMMU_S2_ACVPS_QCH, SYSMMU_S2_DIT_QCH, SYSMMU_S2_SBIC_QCH, SYSREG_BUS1_QCH, TREX_D_BUS1_QCH, TREX_P_BUS1_QCH, TREX_RB_BUS1_QCH, VGEN_LITE_BUS1_QCH, VGEN_PDMA_QCH, BUS2_CMU_BUS2_QCH, CMU_BUS2_CMUREF_QCH, D_TZPC_BUS2_QCH, LHM_ACEL_D0_MCSC_QCH, LHM_ACEL_D_HSI1_QCH, LHM_ACEL_D_M2M_QCH, LHM_ACEL_D_SSP_QCH, LHM_AXI_D0_CSIS_QCH, LHM_AXI_D0_DNS_QCH, LHM_AXI_D0_MCFP0_QCH, LHM_AXI_D0_MFC0_QCH, LHM_AXI_D0_MFC1_QCH, LHM_AXI_D1_CSIS_QCH, LHM_AXI_D1_DNS_QCH, LHM_AXI_D1_MCFP0_QCH, LHM_AXI_D1_MCSC_QCH, LHM_AXI_D1_MFC0_QCH, LHM_AXI_D1_MFC1_QCH, LHM_AXI_D2_CSIS_QCH, LHM_AXI_D2_MCFP0_QCH, LHM_AXI_D2_MCSC_QCH, LHM_AXI_D3_CSIS_QCH, LHM_AXI_D3_MCFP0_QCH, LHM_AXI_D_LME_QCH, LHM_AXI_D_MCFP1_QCH, LHM_AXI_D_TAA_QCH, LHM_AXI_D_YUVPP_QCH, LHS_AXI_P_CSIS_QCH, LHS_AXI_P_HSI1_QCH, LHS_AXI_P_ITP_QCH, LHS_AXI_P_LME_QCH, LHS_AXI_P_M2M_QCH, LHS_AXI_P_MCFP0_QCH, LHS_AXI_P_MCSC_QCH, LHS_AXI_P_MFC0_QCH, LHS_AXI_P_MFC1_QCH, LHS_AXI_P_PERIC1_QCH, LHS_AXI_P_SSP_QCH, LHS_AXI_P_TAA_QCH, LHS_AXI_P_YUVPP_QCH, SYSREG_BUS2_QCH, TREX_D_BUS2_QCH, TREX_P_BUS2_QCH, ADC_CMGP_QCH_S0, ADC_CMGP_QCH_S1, ADC_CMGP_QCH_OSC, APBIF_GPIO_CMGP_QCH, CMGP_CMU_CMGP_QCH, D_TZPC_CMGP_QCH, GPIO_CMGP_QCH, I2C_CMGP0_QCH, I2C_CMGP1_QCH, I2C_CMGP2_QCH, I2C_CMGP3_QCH, I3C_CMGP_QCH_P, I3C_CMGP_QCH_S, LHM_AXI_C_CMGP_QCH, SYSREG_CMGP_QCH, SYSREG_CMGP2APM_QCH, SYSREG_CMGP2CP_QCH, SYSREG_CMGP2PMU_AP_QCH, USI_CMGP0_QCH, USI_CMGP1_QCH, USI_CMGP2_QCH, USI_CMGP3_QCH, CMU_TOP_CMUREF_QCH, DFTMUX_CMU_QCH_CIS_CLK0, DFTMUX_CMU_QCH_CIS_CLK1, DFTMUX_CMU_QCH_CIS_CLK2, DFTMUX_CMU_QCH_CIS_CLK3, DFTMUX_CMU_QCH_CIS_CLK4, DFTMUX_CMU_QCH_CIS_CLK5, ACE_SLICE_G3D0_QCH, ACE_SLICE_G3D1_QCH, ACE_SLICE_G3D2_QCH, ACE_SLICE_G3D3_QCH, BAAW_CP_QCH, BDU_QCH, CCI_QCH, CMU_CORE_CMUREF_QCH, CORE_CMU_CORE_QCH, D_TZPC_CORE_QCH, LHM_ACEL_D2_MODEM_QCH, LHM_ACE_D0_CLUSTER0_QCH, LHM_ACE_D0_G3D_QCH, LHM_ACE_D1_CLUSTER0_QCH, LHM_ACE_D1_G3D_QCH, LHM_ACE_D2_G3D_QCH, LHM_ACE_D3_G3D_QCH, LHM_AXI_D0_MODEM_QCH, LHM_AXI_D1_MODEM_QCH, LHM_AXI_D_AUD_QCH, LHM_AXI_G_CSSYS_QCH, LHS_ATB_T_BDU_QCH, LHS_AXI_P_APM_QCH, LHS_AXI_P_AUD_QCH, LHS_AXI_P_CPUCL0_QCH, LHS_AXI_P_G3D_QCH, LHS_AXI_P_MODEM_QCH, LHS_AXI_P_PERIS_QCH, PPCFW_G3D_QCH, PPC_CPUCL0_0_QCH, PPC_CPUCL0_1_QCH, PPC_G3D0_QCH, PPC_G3D1_QCH, PPC_G3D2_QCH, PPC_G3D3_QCH, PPC_IRPS0_QCH, PPC_IRPS1_QCH, PPC_IRPS2_QCH, PPC_IRPS3_QCH, PPMU_CPUCL0_0_QCH, PPMU_CPUCL0_1_QCH, PPMU_G3D0_QCH, PPMU_G3D1_QCH, PPMU_G3D2_QCH, PPMU_G3D3_QCH, SYSMMU_G3D0_QCH, SYSMMU_G3D1_QCH, SYSMMU_G3D2_QCH, SYSMMU_G3D3_QCH, SYSMMU_MODEM_QCH, SYSREG_CORE_QCH, TREX_D_CORE_QCH, TREX_P0_CORE_QCH, TREX_P1_CORE_QCH, VGEN_LITE_MODEM_QCH, ADD_CPUCL0_0_QCH, BUSIF_ADD_CPUCL0_0_QCH, BUSIF_STR_CPUCL0_0_QCH, BUSIF_STR_CPUCL0_0_QCH_CORE, CMU_CPUCL0_CMUREF_QCH, CMU_CPUCL0_SHORTSTOP_QCH, CPUCL0_QCH, CPUCL0_CMU_CPUCL0_QCH, DDD_CPUCL0_0_QCH, HTU_CPUCL0_QCH, HWACG_BUSIF_DDD_CPUCL0_0_QCH, BPS_CPUCL0_QCH, BUSIF_HPM_CPUCL0_QCH, CPUCL0_GLB_CMU_CPUCL0_GLB_QCH, CSSYS_QCH, D_TZPC_CPUCL0_QCH, LHM_ATB_T0_CLUSTER0_QCH, LHM_ATB_T1_CLUSTER0_QCH, LHM_ATB_T2_CLUSTER0_QCH, LHM_ATB_T3_CLUSTER0_QCH, LHM_ATB_T4_CLUSTER0_QCH, LHM_ATB_T5_CLUSTER0_QCH, LHM_ATB_T6_CLUSTER0_QCH, LHM_ATB_T7_CLUSTER0_QCH, LHM_ATB_T_BDU_QCH, LHM_AXI_G_DBGCORE_QCH, LHM_AXI_G_INT_CSSYS_QCH, LHM_AXI_G_INT_DBGCORE_QCH, LHM_AXI_G_INT_ETR_QCH, LHM_AXI_G_INT_STM_QCH, LHM_AXI_P_CPUCL0_QCH, LHS_AXI_G_CSSYS_QCH, LHS_AXI_G_INT_CSSYS_QCH, LHS_AXI_G_INT_DBGCORE_QCH, LHS_AXI_G_INT_ETR_QCH, LHS_AXI_G_INT_STM_QCH, RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_CSSYS_QCH, RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_CSSYS_QCH, SECJTAG_QCH, SYSREG_CPUCL0_QCH, TREX_CPUCL0_QCH, ADD_CPUCL0_1_QCH, BUSIF_ADD_CPUCL0_1_QCH, BUSIF_STR_CPUCL0_1_QCH, BUSIF_STR_CPUCL0_1_QCH_CORE, CMU_CPUCL1_CMUREF_QCH, CMU_CPUCL1_SHORTSTOP_QCH, CPUCL1_QCH, CPUCL1_QCH_DDD_HC0, CPUCL1_QCH_DDD_HC1, CPUCL1_QCH_DDD_HC2, CPUCL1_CMU_CPUCL1_QCH, HTU_CPUCL1_QCH_PCLK, HTU_CPUCL1_QCH_CLK, HWACG_BUSIF_DDD_CPUCL0_2_QCH, HWACG_BUSIF_DDD_CPUCL0_3_QCH, HWACG_BUSIF_DDD_CPUCL0_4_QCH, ADD_CPUCL0_2_QCH, BUSIF_ADD_CPUCL0_2_QCH, BUSIF_STR_CPUCL0_2_QCH, BUSIF_STR_CPUCL0_2_QCH_CORE, CMU_CPUCL2_CMUREF_QCH, CMU_CPUCL2_SHORTSTOP_QCH, CPUCL2_QCH, CPUCL2_CMU_CPUCL2_QCH, DDD_CPUCL0_1_QCH, HTU_CPUCL2_QCH_PCLK, HTU_CPUCL2_QCH_CLK, HWACG_BUSIF_DDD_CPUCL0_1_QCH, CSISX6_QCH_VOTF0, CSISX6_QCH_DMA, CSISX6_QCH_MCB, CSISX6_QCH_VOTF1, CSIS_CMU_CSIS_QCH, D_TZPC_CSIS_QCH, LHM_AST_INT_OTF0_CSISPDP_QCH, LHM_AST_INT_OTF0_PDPCSIS_QCH, LHM_AST_INT_OTF1_CSISPDP_QCH, LHM_AST_INT_OTF1_PDPCSIS_QCH, LHM_AST_INT_OTF2_CSISPDP_QCH, LHM_AST_INT_OTF2_PDPCSIS_QCH, LHM_AST_INT_OTF3_CSISPDP_QCH, LHM_AST_INT_OTF3_PDPCSIS_QCH, LHM_AST_INT_VO_CSISPDP_QCH, LHM_AST_INT_VO_PDPCSIS_QCH, LHM_AST_SOTF0_TAACSIS_QCH, LHM_AST_SOTF1_TAACSIS_QCH, LHM_AST_SOTF2_TAACSIS_QCH, LHM_AST_SOTF3_TAACSIS_QCH, LHM_AST_ZOTF0_TAACSIS_QCH, LHM_AST_ZOTF1_TAACSIS_QCH, LHM_AST_ZOTF2_TAACSIS_QCH, LHM_AST_ZOTF3_TAACSIS_QCH, LHM_AXI_P_CSIS_QCH, LHS_AST_INT_OTF0_CSISPDP_QCH, LHS_AST_INT_OTF0_PDPCSIS_QCH, LHS_AST_INT_OTF1_CSISPDP_QCH, LHS_AST_INT_OTF1_PDPCSIS_QCH, LHS_AST_INT_OTF2_CSISPDP_QCH, LHS_AST_INT_OTF2_PDPCSIS_QCH, LHS_AST_INT_OTF3_CSISPDP_QCH, LHS_AST_INT_OTF3_PDPCSIS_QCH, LHS_AST_INT_VO_CSISPDP_QCH, LHS_AST_INT_VO_PDPCSIS_QCH, LHS_AST_OTF0_CSISTAA_QCH, LHS_AST_OTF1_CSISTAA_QCH, LHS_AST_OTF2_CSISTAA_QCH, LHS_AST_OTF3_CSISTAA_QCH, LHS_AXI_D0_CSIS_QCH, LHS_AXI_D1_CSIS_QCH, LHS_AXI_D2_CSIS_QCH, LHS_AXI_D3_CSIS_QCH, LHS_AXI_P_CSISPERIC1_QCH, MIPI_PHY_LINK_WRAP_QCH_CSIS0, MIPI_PHY_LINK_WRAP_QCH_CSIS1, MIPI_PHY_LINK_WRAP_QCH_CSIS2, MIPI_PHY_LINK_WRAP_QCH_CSIS3, MIPI_PHY_LINK_WRAP_QCH_CSIS4, MIPI_PHY_LINK_WRAP_QCH_CSIS5, OIS_MCU_TOP_QCH, PDP_TOP_QCH_PDP_TOP, PDP_TOP_QCH_C2_PDP, PPMU_D0_QCH, PPMU_D1_QCH, PPMU_D2_QCH, PPMU_D3_QCH, QE_CSIS_DMA0_QCH, QE_CSIS_DMA1_QCH, QE_CSIS_DMA2_QCH, QE_CSIS_DMA3_QCH, QE_PDP_AF1_QCH, QE_PDP_AF2_QCH, QE_PDP_STAT_AF0_QCH, QE_PDP_STAT_IMG0_QCH, QE_PDP_STAT_IMG1_QCH, QE_PDP_STAT_IMG2_QCH, QE_STRP0_QCH, QE_STRP1_QCH, QE_STRP2_QCH, QE_STRP3_QCH, QE_ZSL0_QCH, QE_ZSL1_QCH, QE_ZSL2_QCH, QE_ZSL3_QCH, RSTNSYNC_CLK_CSIS_OIS_MCU_CPU_SW_RESET_QCH, SYSMMU_D0_CSIS_QCH_S1, SYSMMU_D0_CSIS_QCH_S2, SYSMMU_D1_CSIS_QCH_S1, SYSMMU_D1_CSIS_QCH_S2, SYSMMU_D2_CSIS_QCH_S1, SYSMMU_D2_CSIS_QCH_S2, SYSMMU_D3_CSIS_QCH_S1, SYSMMU_D3_CSIS_QCH_S2, SYSREG_CSIS_QCH, VGEN_LITE_D0_QCH, VGEN_LITE_D1_QCH, VGEN_LITE_D2_QCH, DNS_QCH, DNS_QCH_VOTF0, DNS_QCH_VOTF1, DNS_QCH_VOTF2, DNS_CMU_DNS_QCH, D_TZPC_DNS_QCH, LHM_AST_CTL_ITPDNS_QCH, LHM_AST_OTF0_ITPDNS_QCH, LHM_AST_OTF1_ITPDNS_QCH, LHM_AST_OTF2_ITPDNS_QCH, LHM_AST_OTF3_ITPDNS_QCH, LHM_AST_OTF4_ITPDNS_QCH, LHM_AST_OTF_MCFP1DNS_QCH, LHM_AST_OTF_TAADNS_QCH, LHM_AXI_P_ITPDNS_QCH, LHS_AST_CTL_DNSITP_QCH, LHS_AST_OTF0_DNSITP_QCH, LHS_AST_OTF1_DNSITP_QCH, LHS_AST_OTF2_DNSITP_QCH, LHS_AST_OTF3_DNSITP_QCH, LHS_AST_OTF4_DNSITP_QCH, LHS_AST_OTF5_DNSITP_QCH, LHS_AST_OTF6_DNSITP_QCH, LHS_AST_OTF7_DNSITP_QCH, LHS_AST_OTF8_DNSITP_QCH, LHS_AST_OTF9_DNSITP_QCH, LHS_AXI_D0_DNS_QCH, LHS_AXI_D1_DNS_QCH, PPMU_D0_DNS_QCH, PPMU_D1_DNS_QCH, SYSMMU_D0_DNS_QCH_S2, SYSMMU_D0_DNS_QCH_S1, SYSMMU_D1_DNS_QCH_S2, SYSMMU_D1_DNS_QCH_S1, SYSREG_DNS_QCH, VGEN_LITE_D0_DNS_QCH, VGEN_LITE_D1_DNS_QCH, DPUB_QCH, DPUB_CMU_DPUB_QCH, D_TZPC_DPUB_QCH, LHM_AXI_P_DPUB_QCH, SYSREG_DPUB_QCH, DPUF0_QCH_DMA, DPUF0_QCH_DPP, DPUF0_QCH_C2SERV, DPUF0_CMU_DPUF0_QCH, D_TZPC_DPUF0_QCH, LHM_AXI_D_DPUF1DPUF0_QCH, LHM_AXI_P_DPUF0_QCH, LHS_AXI_D0_DPUF0_QCH, LHS_AXI_D1_DPUF0_QCH, PPMU_DPUF0D0_QCH, PPMU_DPUF0D1_QCH, SYSMMU_DPUF0D0_QCH_S1, SYSMMU_DPUF0D0_QCH_S2, SYSMMU_DPUF0D1_QCH_S1, SYSMMU_DPUF0D1_QCH_S2, SYSREG_DPUF0_QCH, DPUF1_QCH_DMA, DPUF1_QCH_DPP, DPUF1_QCH_C2SERV, DPUF1_CMU_DPUF1_QCH, D_TZPC_DPUF1_QCH, LHM_AXI_P_DPUF1_QCH, LHS_AXI_D0_DPUF1_QCH, LHS_AXI_D1_DPUF1_QCH, LHS_AXI_D_DPUF1DPUF0_QCH, PPMU_DPUF1D0_QCH, PPMU_DPUF1D1_QCH, SYSMMU_DPUF1D0_QCH_S2, SYSMMU_DPUF1D0_QCH_S1, SYSMMU_DPUF1D1_QCH_S2, SYSMMU_DPUF1D1_QCH_S1, SYSREG_DPUF1_QCH, ACE_US_128TO256_D0_CLUSTER0_QCH, ACE_US_128TO256_D1_CLUSTER0_QCH, BUSIF_STR_CPUCL0_3_QCH, BUSIF_STR_CPUCL0_3_QCH_CORE, CLUSTER0_QCH_SCLK, CLUSTER0_QCH_ATCLK, CLUSTER0_QCH_PDBGCLK, CLUSTER0_QCH_GICCLK, CLUSTER0_QCH_DBG_PD, CLUSTER0_QCH_PCLK, CLUSTER0_QCH_PERIPHCLK, CMU_DSU_CMUREF_QCH, CMU_DSU_SHORTSTOP_QCH, DSU_CMU_DSU_QCH, HTU_DSU_QCH, LHM_AST_IRI_GICCPU_CLUSTER0_QCH, LHS_ACE_D0_CLUSTER0_QCH, LHS_ACE_D1_CLUSTER0_QCH, LHS_AST_ICC_CPUGIC_CLUSTER0_QCH, LHS_ATB_T0_CLUSTER0_QCH, LHS_ATB_T1_CLUSTER0_QCH, LHS_ATB_T2_CLUSTER0_QCH, LHS_ATB_T3_CLUSTER0_QCH, LHS_ATB_T4_CLUSTER0_QCH, LHS_ATB_T5_CLUSTER0_QCH, LHS_ATB_T6_CLUSTER0_QCH, LHS_ATB_T7_CLUSTER0_QCH, PPC_INSTRRET_CLUSTER0_0_QCH, PPC_INSTRRET_CLUSTER0_1_QCH, PPC_INSTRRUN_CLUSTER0_0_QCH, PPC_INSTRRUN_CLUSTER0_1_QCH, ADD_APBIF_G3D_QCH, ADD_G3D_QCH, ASB_G3D_QCH_LH_D0_G3D, ASB_G3D_QCH_LH_D1_G3D, ASB_G3D_QCH_LH_D2_G3D, ASB_G3D_QCH_LH_D3_G3D, BUSIF_HPMG3D_QCH, BUSIF_STR_G3D_QCH, BUSIF_STR_G3D_QCH_CORE, D_TZPC_G3D_QCH, G3D_CMU_G3D_QCH, GPU_QCH, HTU_G3D_QCH_PCLK, HTU_G3D_QCH_CLK, LHM_AXI_P_G3D_QCH, LHM_AXI_P_INT_G3D_QCH, LHS_AXI_P_INT_G3D_QCH, SYSREG_G3D_QCH, VGEN_LITE_G3D_QCH, DP_LINK_QCH_PCLK, DP_LINK_QCH_GTC_CLK, D_TZPC_HSI0_QCH, HSI0_CMU_HSI0_QCH, LHM_AXI_D_AUDHSI0_QCH, LHM_AXI_P_HSI0_QCH, LHS_ACEL_D_HSI0_QCH, LHS_AXI_D_HSI0AUD_QCH, PPMU_HSI0_BUS1_QCH, SYSMMU_USB_QCH, SYSREG_HSI0_QCH, USB31DRD_QCH_REF, USB31DRD_QCH_SLV_CTRL, USB31DRD_QCH_SLV_LINK, USB31DRD_QCH_APB, USB31DRD_QCH_PCS, USB31DRD_QCH_DBG, VGEN_LITE_HSI0_QCH, D_TZPC_HSI1_QCH, GPIO_HSI1_QCH, HSI1_CMU_HSI1_QCH, LHM_AXI_P_HSI1_QCH, LHS_ACEL_D_HSI1_QCH, MMC_CARD_QCH, PCIE_GEN2_QCH_MSTR, PCIE_GEN2_QCH_PCS, PCIE_GEN2_QCH_PHY, PCIE_GEN2_QCH_DBI, PCIE_GEN2_QCH_APB, PCIE_GEN2_QCH_REF, PCIE_GEN4_0_QCH_APB, PCIE_GEN4_0_QCH_DBI, PCIE_GEN4_0_QCH_AXI, PCIE_GEN4_0_QCH_PCS_APB, PCIE_GEN4_0_QCH_REF, PCIE_GEN4_0_QCH_PMA_APB, PCIE_GEN4_0_QCH_UDBG_APB, PCIE_IA_GEN2_QCH, PCIE_IA_GEN4_0_QCH, PPMU_HSI1_QCH, SYSMMU_HSI1_QCH, SYSREG_HSI1_QCH, UFS_EMBD_QCH, UFS_EMBD_QCH_FMP, VGEN_LITE_HSI1_QCH, D_TZPC_ITP_QCH, ITP_QCH, ITP_CMU_ITP_QCH, LHM_AST_CTL_DNSITP_QCH, LHM_AST_OTF0_DNSITP_QCH, LHM_AST_OTF1_DNSITP_QCH, LHM_AST_OTF2_DNSITP_QCH, LHM_AST_OTF3_DNSITP_QCH, LHM_AST_OTF4_DNSITP_QCH, LHM_AST_OTF5_DNSITP_QCH, LHM_AST_OTF6_DNSITP_QCH, LHM_AST_OTF7_DNSITP_QCH, LHM_AST_OTF8_DNSITP_QCH, LHM_AST_OTF9_DNSITP_QCH, LHM_AST_OTF_MCFP1ITP_QCH, LHM_AXI_P_ITP_QCH, LHS_AST_CTL_ITPDNS_QCH, LHS_AST_OTF0_ITPDNS_QCH, LHS_AST_OTF1_ITPDNS_QCH, LHS_AST_OTF2_ITPDNS_QCH, LHS_AST_OTF3_ITPDNS_QCH, LHS_AST_OTF4_ITPDNS_QCH, LHS_AST_OTF_ITPMCSC_QCH, LHS_AXI_P_ITPDNS_QCH, SYSREG_ITP_QCH, D_TZPC_LME_QCH, LHM_AXI_P_LME_QCH, LHS_AXI_D_LME_QCH, LME_QCH, LME_QCH_C2, LME_CMU_LME_QCH, PPMU_LME_QCH, SYSMMU_D_LME_QCH_S2, SYSMMU_D_LME_QCH_S1, SYSREG_LME_QCH, VGEN_LITE_LME_QCH, ASTC_QCH, D_TZPC_M2M_QCH, JPEG0_QCH, JPEG1_QCH, JSQZ_QCH, LHM_AXI_P_M2M_QCH, LHS_ACEL_D_M2M_QCH, M2M_QCH, M2M_QCH_VOTF, M2M_CMU_M2M_QCH, PPMU_D_M2M_QCH, QE_ASTC_QCH, QE_JPEG0_QCH, QE_JPEG1_QCH, QE_JSQZ_QCH, QE_M2M_QCH, SYSMMU_D_M2M_QCH_S2, SYSMMU_D_M2M_QCH_S1, SYSREG_M2M_QCH, VGEN_LITE_M2M_QCH, D_TZPC_MCFP0_QCH, LHM_AST_CTL_MCFP1MCFP0_QCH, LHM_AST_OTF0_MCFP1MCFP0_QCH, LHM_AST_OTF1_MCFP1MCFP0_QCH, LHM_AST_OTF2_MCFP1MCFP0_QCH, LHM_AST_OTF3_MCFP1MCFP0_QCH, LHM_AXI_P_MCFP0_QCH, LHS_AST_CTL_MCFP0MCFP1_QCH, LHS_AST_OTF0_MCFP0MCFP1_QCH, LHS_AST_OTF1_MCFP0MCFP1_QCH, LHS_AXI_D0_MCFP0_QCH, LHS_AXI_D1_MCFP0_QCH, LHS_AXI_D2_MCFP0_QCH, LHS_AXI_D3_MCFP0_QCH, LHS_AXI_P_MCFP0MCFP1_QCH, MCFP0_QCH, MCFP0_CMU_MCFP0_QCH, PPMU_D0_MCFP0_QCH, PPMU_D1_MCFP0_QCH, PPMU_D2_MCFP0_QCH, PPMU_D3_MCFP0_QCH, QE_D0_MCFP0_QCH, QE_D1_MCFP0_QCH, QE_D2_MCFP0_QCH, QE_D3_MCFP0_QCH, SYSMMU_D0_MCFP0_QCH_S1, SYSMMU_D0_MCFP0_QCH_S2, SYSMMU_D1_MCFP0_QCH_S1, SYSMMU_D1_MCFP0_QCH_S2, SYSMMU_D2_MCFP0_QCH_S1, SYSMMU_D2_MCFP0_QCH_S2, SYSMMU_D3_MCFP0_QCH_S1, SYSMMU_D3_MCFP0_QCH_S2, SYSREG_MCFP0_QCH, VGEN_LITE_MCFP0_QCH, D_TZPC_MCFP1_QCH, LHM_AST_CTL_MCFP0MCFP1_QCH, LHM_AST_OTF0_MCFP0MCFP1_QCH, LHM_AST_OTF1_MCFP0MCFP1_QCH, LHM_AST_VO_TAAMCFP1_QCH, LHM_AXI_P_MCFP0MCFP1_QCH, LHS_AST_CTL_MCFP1MCFP0_QCH, LHS_AST_OTF0_MCFP1MCFP0_QCH, LHS_AST_OTF1_MCFP1MCFP0_QCH, LHS_AST_OTF2_MCFP1MCFP0_QCH, LHS_AST_OTF3_MCFP1MCFP0_QCH, LHS_AST_OTF_MCFP1DNS_QCH, LHS_AST_OTF_MCFP1ITP_QCH, LHS_AST_VO_MCFP1TAA_QCH, LHS_AXI_D_MCFP1_QCH, MCFP1_QCH, MCFP1_CMU_MCFP1_QCH, ORBMCH0_QCH_C2, ORBMCH0_QCH, ORBMCH1_QCH, ORBMCH1_QCH_C2, PPMU_ORBMCH_QCH, QE_D0_ORBMCH_QCH, QE_D1_ORBMCH_QCH, QE_D2_ORBMCH_QCH, QE_D3_ORBMCH_QCH, QE_D4_ORBMCH_QCH, QE_D5_ORBMCH_QCH, SYSMMU_D_MCFP1_QCH_S2, SYSMMU_D_MCFP1_QCH_S1, SYSREG_MCFP1_QCH, VGEN_LITE_D0_MCFP1_QCH, VGEN_LITE_D1_MCFP1_QCH, ADD_MCSC_QCH, BUSIF_ADD_MCSC_QCH, BUSIF_HPM_MCSC_QCH, D_TZPC_MCSC_QCH, GDC_QCH, GDC_QCH_C2_M, GDC_QCH_C2_S, LHM_AST_OTF_ITPMCSC_QCH, LHM_AST_OTF_YUVPPMCSC_QCH, LHM_AXI_D_YUVPPMCSC_QCH, LHM_AXI_P_MCSC_QCH, LHS_ACEL_D0_MCSC_QCH, LHS_AXI_D1_MCSC_QCH, LHS_AXI_D2_MCSC_QCH, MCSC_QCH, MCSC_QCH_C2_W, MCSC_QCH_C2_R, MCSC_CMU_MCSC_QCH, PPMU_D0_MCSC_QCH, PPMU_D1_MCSC_QCH, PPMU_D2_MCSC_QCH, SYSMMU_D0_MCSC_QCH_S1, SYSMMU_D0_MCSC_QCH_S2, SYSMMU_D1_MCSC_QCH_S1, SYSMMU_D1_MCSC_QCH_S2, SYSMMU_D2_MCSC_QCH_S1, SYSMMU_D2_MCSC_QCH_S2, SYSREG_MCSC_QCH, VGEN_LITE_D0_MCSC_QCH, VGEN_LITE_D1_MCSC_QCH, D_TZPC_MFC0_QCH, LHM_AST_OTF0_MFC1MFC0_QCH, LHM_AST_OTF1_MFC1MFC0_QCH, LHM_AST_OTF2_MFC1MFC0_QCH, LHM_AST_OTF3_MFC1MFC0_QCH, LHM_AXI_P_MFC0_QCH, LHS_AST_OTF0_MFC0MFC1_QCH, LHS_AST_OTF1_MFC0MFC1_QCH, LHS_AST_OTF2_MFC0MFC1_QCH, LHS_AST_OTF3_MFC0MFC1_QCH, LHS_AXI_D0_MFC0_QCH, LHS_AXI_D1_MFC0_QCH, LH_ATB_MFC0_QCH_MI, LH_ATB_MFC0_QCH_SI, MFC0_QCH, MFC0_QCH_VOTF, MFC0_CMU_MFC0_QCH, PPMU_MFC0D0_QCH, PPMU_MFC0D1_QCH, PPMU_WFD_QCH, RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF0_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF1_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF2_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_BUSD_LHM_AST_OTF3_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF0_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF1_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF2_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_BUSD_LHS_AST_OTF3_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_MI_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_BUSD_LH_ATB_MFC0_SI_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_BUSD_MFC0_SW_RESET_QCH, RSTNSYNC_CLK_MFC0_BUSD_WFD_SW_RESET_QCH, SYSMMU_MFC0D0_QCH_S1, SYSMMU_MFC0D0_QCH_S2, SYSMMU_MFC0D1_QCH_S1, SYSMMU_MFC0D1_QCH_S2, SYSREG_MFC0_QCH, VGEN_MFC0_QCH, WFD_QCH, ADM_APB_MFC0MFC1_QCH, D_TZPC_MFC1_QCH, LHM_AST_OTF0_MFC0MFC1_QCH, LHM_AST_OTF1_MFC0MFC1_QCH, LHM_AST_OTF2_MFC0MFC1_QCH, LHM_AST_OTF3_MFC0MFC1_QCH, LHM_AXI_P_MFC1_QCH, LHS_AST_OTF0_MFC1MFC0_QCH, LHS_AST_OTF1_MFC1MFC0_QCH, LHS_AST_OTF2_MFC1MFC0_QCH, LHS_AST_OTF3_MFC1MFC0_QCH, LHS_AXI_D0_MFC1_QCH, LHS_AXI_D1_MFC1_QCH, MFC1_QCH, MFC1_CMU_MFC1_QCH, PPMU_MFC1D0_QCH, PPMU_MFC1D1_QCH, RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF0_MFC1_SW_RESET_QCH, RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF1_MFC1_SW_RESET_QCH, RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF2_MFC1_SW_RESET_QCH, RSTNSYNC_CLK_MFC1_BUSD_LHM_AST_OTF3_MFC1_SW_RESET_QCH, RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF0_MFC1_SW_RESET_QCH, RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF1_MFC1_SW_RESET_QCH, RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF2_MFC1_SW_RESET_QCH, RSTNSYNC_CLK_MFC1_BUSD_LHS_AST_OTF3_MFC1_SW_RESET_QCH, RSTNSYNC_CLK_MFC1_BUSD_MFC1_SW_RESET_QCH, SYSMMU_MFC1D0_QCH_S2, SYSMMU_MFC1D0_QCH_S1, SYSMMU_MFC1D1_QCH_S2, SYSMMU_MFC1D1_QCH_S1, SYSREG_MFC1_QCH, VGEN_MFC1_QCH, APBBR_DDRPHY_QCH, APBBR_DMC_QCH, CMU_MIF_CMUREF_QCH, DMC_QCH, D_TZPC_MIF_QCH, LHM_AXI_P_MIF_QCH, MIF_CMU_MIF_QCH, QCH_ADAPTER_PPC_DEBUG_QCH, SYSREG_MIF_QCH, D_TZPC_NPU_QCH, IP_NPUCORE_QCH_PCLK, IP_NPUCORE_QCH_ACLK, LHM_AXI_D0_NPU_QCH, LHM_AXI_D1_NPU_QCH, LHM_AXI_D_CTRL_NPU_QCH, LHM_AXI_P_NPU_QCH, LHS_AXI_D_CMDQ_NPU_QCH, LHS_AXI_D_RQ_NPU_QCH, NPU_CMU_NPU_QCH, SYSREG_NPU_QCH, D_TZPC_NPU01_QCH, IP_NPU01CORE_QCH_PCLK, IP_NPU01CORE_QCH_ACLK, LHM_AXI_D0_NPU01_QCH, LHM_AXI_D1_NPU01_QCH, LHM_AXI_D_CTRL_NPU01_QCH, LHM_AXI_P_NPU01_QCH, LHS_AXI_D_CMDQ_NPU01_QCH, LHS_AXI_D_RQ_NPU01_QCH, NPU01_CMU_NPU_QCH, SYSREG_NPU01_QCH, D_TZPC_NPU10_QCH, IP_NPU10CORE_QCH_PCLK, IP_NPU10CORE_QCH_ACLK, LHM_AXI_D0_NPU10_QCH, LHM_AXI_D1_NPU10_QCH, LHM_AXI_D_CTRL_NPU10_QCH, LHM_AXI_P_NPU10_QCH, LHS_AXI_D_CMDQ_NPU10_QCH, LHS_AXI_D_RQ_NPU10_QCH, NPU10_CMU_NPU_QCH, SYSREG_NPU10_QCH, ADD_NPUS_QCH, ADM_DAP_NPUS_QCH, BUSIF_ADD_NPUS_QCH, BUSIF_HPM_NPUS_QCH, D_TZPC_NPUS_QCH, HTU_NPUS_QCH_PCLK, HTU_NPUS_QCH_CLK, IP_NPUS_QCH, IP_NPUS_QCH_C2A0, IP_NPUS_QCH_C2A1, IP_NPUS_QCH_CPU, IP_NPUS_QCH_NEON, LHM_AXI_D_CMDQ_NPU00_QCH, LHM_AXI_D_CMDQ_NPU01_QCH, LHM_AXI_D_CMDQ_NPU10_QCH, LHM_AXI_D_RQ_NPU00_QCH, LHM_AXI_D_RQ_NPU01_QCH, LHM_AXI_D_RQ_NPU10_QCH, LHM_AXI_P_INT_NPUS_QCH, LHM_AXI_P_NPUS_QCH, LHS_AXI_D0_NPU00_QCH, LHS_AXI_D0_NPU01_QCH, LHS_AXI_D0_NPU10_QCH, LHS_AXI_D0_NPUS_QCH, LHS_AXI_D1_NPU00_QCH, LHS_AXI_D1_NPU01_QCH, LHS_AXI_D1_NPU10_QCH, LHS_AXI_D1_NPUS_QCH, LHS_AXI_D2_NPUS_QCH, LHS_AXI_D_CTRL_NPU00_QCH, LHS_AXI_D_CTRL_NPU01_QCH, LHS_AXI_D_CTRL_NPU10_QCH, LHS_AXI_P_INT_NPUS_QCH, NPUS_CMU_NPUS_QCH, PPMU_NPUS_0_QCH, PPMU_NPUS_1_QCH, PPMU_NPUS_2_QCH, SYSMMU_D0_NPUS_QCH_S2, SYSMMU_D0_NPUS_QCH_S1, SYSMMU_D1_NPUS_QCH_S2, SYSMMU_D1_NPUS_QCH_S1, SYSMMU_D2_NPUS_QCH_S2, SYSMMU_D2_NPUS_QCH_S1, SYSREG_NPUS_QCH, VGEN_LITE_NPUS_QCH, D_TZPC_PERIC0_QCH, GPIO_PERIC0_QCH, LHM_AXI_P_PERIC0_QCH, PERIC0_CMU_PERIC0_QCH, PERIC0_TOP0_QCH_UART_DBG, PERIC0_TOP0_QCH_USI00_USI, PERIC0_TOP0_QCH_USI00_I2C, PERIC0_TOP0_QCH_USI01_USI, PERIC0_TOP0_QCH_USI01_I2C, PERIC0_TOP0_QCH_USI02_USI, PERIC0_TOP0_QCH_USI02_I2C, PERIC0_TOP0_QCH_USI03_USI, PERIC0_TOP0_QCH_USI03_I2C, PERIC0_TOP0_QCH_USI04_USI, PERIC0_TOP0_QCH_USI04_I2C, PERIC0_TOP0_QCH_USI05_USI, PERIC0_TOP1_QCH_USI05_I2C, PERIC0_TOP1_QCH_USI13_USI, PERIC0_TOP1_QCH_USI13_I2C, PERIC0_TOP1_QCH_USI14_USI, PERIC0_TOP1_QCH_USI14_I2C, PERIC0_TOP1_QCH_USI15_USI, PERIC0_TOP1_QCH_USI15_I2C, PERIC0_TOP1_QCH_PWM, SYSREG_PERIC0_QCH, D_TZPC_PERIC1_QCH, GPIO_PERIC1_QCH, LHM_AXI_P_CSISPERIC1_QCH, LHM_AXI_P_PERIC1_QCH, PERIC1_CMU_PERIC1_QCH, PERIC1_TOP0_QCH_UART_BT, PERIC1_TOP1_QCH_USI11_USI, PERIC1_TOP1_QCH_USI11_I2C, PERIC1_TOP1_QCH_USI16_USI, PERIC1_TOP1_QCH_USI16_I2C, PERIC1_TOP1_QCH_USI17_USI, PERIC1_TOP1_QCH_USI17_I2C, PERIC1_TOP1_QCH_USI12_USI, PERIC1_TOP1_QCH_USI12_I2C, PERIC1_TOP1_QCH_USI18_USI, PERIC1_TOP1_QCH_USI18_I2C, SYSREG_PERIC1_QCH, USI16_I3C_QCH_P, USI16_I3C_QCH_S, USI17_I3C_QCH_P, USI17_I3C_QCH_S, D_TZPC_PERIC2_QCH, GPIO_PERIC2_QCH, LHM_AXI_P_PERIC2_QCH, PERIC2_CMU_PERIC2_QCH, PERIC2_TOP0_QCH_USI06_USI, PERIC2_TOP0_QCH_USI07_USI, PERIC2_TOP0_QCH_USI08_USI, PERIC2_TOP0_QCH_USI08_I2C, PERIC2_TOP0_QCH_USI06_I2C, PERIC2_TOP0_QCH_USI07_I2C, PERIC2_TOP1_QCH_USI09_USI, PERIC2_TOP1_QCH_USI09_I2C, PERIC2_TOP1_QCH_USI10_USI, PERIC2_TOP1_QCH_USI10_I2C, SYSREG_PERIC2_QCH, BC_EMUL_QCH, D_TZPC_PERIS_QCH, GIC_QCH, LHM_AST_ICC_CPUGIC_CLUSTER0_QCH, LHM_AXI_P_PERIS_QCH, LHM_AXI_P_PERISGIC_QCH, LHS_AST_IRI_GICCPU_CLUSTER0_QCH, MCT_QCH, OTP_QCH, OTP_CON_BIRA_QCH, OTP_CON_BISR_QCH, OTP_CON_TOP_QCH, PERIS_CMU_PERIS_QCH, SYSREG_PERIS_QCH, TMU_SUB_QCH, TMU_TOP_QCH, WDT0_QCH, WDT1_QCH, BIS_S2D_QCH, LHM_AXI_G_SCAN2DRAM_QCH, S2D_CMU_S2D_QCH, ADM_DAP_SSS_QCH, BAAW_SSS_QCH, D_TZPC_SSP_QCH, LHM_AXI_D_SSPCORE_QCH, LHM_AXI_P_SSP_QCH, LHS_ACEL_D_SSP_QCH, PPMU_SSP_QCH, QE_RTIC_QCH, QE_SSPCORE_QCH, QE_SSS_QCH, RTIC_QCH, SSP_CMU_SSP_QCH, SSS_QCH, SWEEPER_D_SSP_QCH, SYSMMU_RTIC_QCH, SYSREG_SSPCTRL_QCH, VGEN_LITE_RTIC_QCH, USS_SSPCORE_QCH, ADD_TAA_QCH, BUSIF_ADD_TAA_QCH, BUSIF_HPM_TAA_QCH, D_TZPC_TAA_QCH, LHM_AST_OTF0_CSISTAA_QCH, LHM_AST_OTF1_CSISTAA_QCH, LHM_AST_OTF2_CSISTAA_QCH, LHM_AST_OTF3_CSISTAA_QCH, LHM_AST_VO_MCFP1TAA_QCH, LHM_AXI_P_TAA_QCH, LHS_AST_OTF_TAADNS_QCH, LHS_AST_SOTF0_TAACSIS_QCH, LHS_AST_SOTF1_TAACSIS_QCH, LHS_AST_SOTF2_TAACSIS_QCH, LHS_AST_SOTF3_TAACSIS_QCH, LHS_AST_VO_TAAMCFP1_QCH, LHS_AST_ZOTF0_TAACSIS_QCH, LHS_AST_ZOTF1_TAACSIS_QCH, LHS_AST_ZOTF2_TAACSIS_QCH, LHS_AST_ZOTF3_TAACSIS_QCH, LHS_AXI_D_TAA_QCH, PPMU_TAA_QCH, SIPU_TAA_QCH, SIPU_TAA_QCH_C2_STAT, SIPU_TAA_QCH_C2_YDS, SYSMMU_D_TAA_QCH_S1, SYSMMU_D_TAA_QCH_S2, SYSREG_TAA_QCH, TAA_CMU_TAA_QCH, VGEN_LITE_TAA0_QCH, VGEN_LITE_TAA1_QCH, ADD_VPC_QCH, ADM_DAP_VPC_QCH, BUSIF_ADD_VPC_QCH, BUSIF_HPM_VPC_QCH, D_TZPC_VPC_QCH, HTU_VPC_QCH_PCLK, HTU_VPC_QCH_CLK, IP_VPC_QCH, LHM_AXI_D_VPD0VPC_CACHE_QCH, LHM_AXI_D_VPD0VPC_SFR_QCH, LHM_AXI_D_VPD1VPC_CACHE_QCH, LHM_AXI_D_VPD1VPC_SFR_QCH, LHM_AXI_P_VPC_QCH, LHM_AXI_P_VPC_800_QCH, LHS_ACEL_D0_VPC_QCH, LHS_ACEL_D1_VPC_QCH, LHS_ACEL_D2_VPC_QCH, LHS_AXI_D_VPCVPD0_DMA_QCH, LHS_AXI_D_VPCVPD0_SFR_QCH, LHS_AXI_D_VPCVPD1_DMA_QCH, LHS_AXI_D_VPCVPD1_SFR_QCH, LHS_AXI_P_VPCVPD0_QCH, LHS_AXI_P_VPCVPD1_QCH, LHS_AXI_P_VPC_200_QCH, PPMU_VPC0_QCH, PPMU_VPC1_QCH, PPMU_VPC2_QCH, SYSMMU_VPC0_QCH_S1, SYSMMU_VPC0_QCH_S2, SYSMMU_VPC1_QCH_S1, SYSMMU_VPC1_QCH_S2, SYSMMU_VPC2_QCH_S1, SYSMMU_VPC2_QCH_S2, SYSREG_VPC_QCH, VGEN_LITE_VPC_QCH, VPC_CMU_VPC_QCH, D_TZPC_VPD_QCH, IP_VPD_QCH, LHM_AXI_D_VPCVPD_DMA_QCH, LHM_AXI_D_VPCVPD_SFR_QCH, LHM_AXI_P_VPCVPD_QCH, LHS_AXI_D_VPDVPC_CACHE_QCH, LHS_AXI_D_VPDVPC_SFR_QCH, SYSREG_VPD_QCH, VPD_CMU_VPD_QCH, BAAW_C_VTS_QCH, BAAW_D_VTS_QCH, BUSIF_HPM_VTS_QCH, CORTEXM4INTEGRATION_QCH_CPU, DMAILBOX_TEST_QCH_ACLK, DMAILBOX_TEST_QCH_PCLK, DMAILBOX_TEST_QCH_LIF, DMIC_AHB0_QCH_PCLK, DMIC_AHB1_QCH_PCLK, DMIC_AHB2_QCH_PCLK, DMIC_AHB3_QCH_PCLK, DMIC_AHB4_QCH_PCLK, DMIC_AHB5_QCH_PCLK, DMIC_AUD0_QCH_PCLK, DMIC_AUD0_QCH_DMIC, DMIC_AUD1_QCH_PCLK, DMIC_AUD1_QCH_DMIC, DMIC_AUD2_QCH_PCLK, DMIC_AUD2_QCH_DMIC, DMIC_IF0_QCH_PCLK, DMIC_IF0_QCH_DMIC, DMIC_IF1_QCH_PCLK, DMIC_IF1_QCH_DMIC, DMIC_IF2_QCH_PCLK, DMIC_IF2_QCH_DMIC, D_TZPC_VTS_QCH, GPIO_VTS_QCH, HWACG_SYS_DMIC0_QCH, HWACG_SYS_DMIC1_QCH, HWACG_SYS_DMIC2_QCH, HWACG_SYS_DMIC3_QCH, HWACG_SYS_DMIC4_QCH, HWACG_SYS_DMIC5_QCH, HWACG_SYS_SERIAL_LIF_QCH, LHM_AXI_D_AUDVTS_QCH, LHM_AXI_LP_VTS_QCH, LHM_AXI_P_VTS_QCH, LHS_AXI_C_VTS_QCH, LHS_AXI_D_VTS_QCH, MAILBOX_ABOX_VTS_QCH, MAILBOX_APM_VTS1_QCH, MAILBOX_AP_VTS_QCH, PDMA_VTS_QCH, SERIAL_LIF_QCH_PCLK, SERIAL_LIF_QCH_LIF, SERIAL_LIF_QCH_HCLK, SERIAL_LIF_DEBUG_US_QCH_PCLK, SERIAL_LIF_DEBUG_US_QCH_LIF, SERIAL_LIF_DEBUG_VT_QCH_PCLK, SERIAL_LIF_DEBUG_VT_QCH_LIF, SS_VTS_GLUE_QCH_DMIC_AUD_PAD0, SS_VTS_GLUE_QCH_DMIC_IF_PAD0, SS_VTS_GLUE_QCH_DMIC_AUD_PAD1, SS_VTS_GLUE_QCH_DMIC_IF_PAD1, SS_VTS_GLUE_QCH_DMIC_AUD_PAD2, SS_VTS_GLUE_QCH_DMIC_IF_PAD2, SWEEPER_D_VTS_QCH, SYSREG_VTS_QCH, TIMER_QCH, TIMER1_QCH, TIMER2_QCH, VGEN_LITE_QCH, VTS_CMU_VTS_QCH, WDT_VTS_QCH, D_TZPC_YUVPP_QCH, FRC_MC_QCH, LHM_AXI_P_YUVPP_QCH, LHS_AST_OTF_YUVPPMCSC_QCH, LHS_AXI_D_YUVPP_QCH, LHS_AXI_D_YUVPPMCSC_QCH, PPMU_YUVPP_QCH, QE_D0_YUVPP_QCH, QE_D10_YUVPP_QCH, QE_D11_YUVPP_QCH, QE_D1_YUVPP_QCH, QE_D2_YUVPP_QCH, QE_D3_YUVPP_QCH, QE_D4_YUVPP_QCH, QE_D5_YUVPP_QCH, QE_D6_YUVPP_QCH, QE_D7_YUVPP_QCH, QE_D8_YUVPP_QCH, QE_D9_YUVPP_QCH, SYSMMU_D_YUVPP_QCH_S1, SYSMMU_D_YUVPP_QCH_S2, SYSREG_YUVPP_QCH, VGEN_LITE_YUVPP0_QCH, VGEN_LITE_YUVPP1_QCH, VGEN_LITE_YUVPP2_QCH, YUVPP_CMU_YUVPP_QCH, YUVPP_TOP_QCH, YUVPP_TOP_QCH_C2COM, end_of_qch, num_of_qch = (end_of_qch - QCH_TYPE) & MASK_OF_ID, }; enum option_id { CTRL_OPTION_CMU_ALIVE = OPTION_TYPE, CTRL_OPTION_CMU_AUD, CTRL_OPTION_CMU_BUS0, CTRL_OPTION_CMU_BUS1, CTRL_OPTION_CMU_BUS2, CTRL_OPTION_CMU_CMGP, CTRL_OPTION_CMU_TOP, CTRL_OPTION_CMU_CORE, CTRL_OPTION_CMU_CPUCL0, CTRL_OPTION_CMU_CPUCL0_GLB, CTRL_OPTION_CMU_CPUCL1, CTRL_OPTION_CMU_CPUCL2, CTRL_OPTION_CMU_CSIS, CTRL_OPTION_CMU_DNS, CTRL_OPTION_CMU_DPUB, CTRL_OPTION_CMU_DPUF0, CTRL_OPTION_CMU_DPUF1, CTRL_OPTION_CMU_DSU, CTRL_OPTION_CMU_G3D, CTRL_OPTION_EMBEDDED_CMU_G3D, CTRL_OPTION_CMU_HSI0, CTRL_OPTION_CMU_HSI1, CTRL_OPTION_CMU_ITP, CTRL_OPTION_CMU_LME, CTRL_OPTION_CMU_M2M, CTRL_OPTION_CMU_MCFP0, CTRL_OPTION_CMU_MCFP1, CTRL_OPTION_CMU_MCSC, CTRL_OPTION_CMU_MFC0, CTRL_OPTION_CMU_MFC1, CTRL_OPTION_CMU_MIF, CTRL_OPTION_CMU_NPU, CTRL_OPTION_CMU_NPU01, CTRL_OPTION_CMU_NPU10, CTRL_OPTION_CMU_NPUS, CTRL_OPTION_CMU_PERIC0, CTRL_OPTION_CMU_PERIC1, CTRL_OPTION_CMU_PERIC2, CTRL_OPTION_CMU_PERIS, CTRL_OPTION_CMU_S2D, CTRL_OPTION_CMU_SSP, CTRL_OPTION_EMBEDDED_CMU_SSP, CTRL_OPTION_CMU_TAA, CTRL_OPTION_CMU_VPC, CTRL_OPTION_CMU_VPD, CTRL_OPTION_CMU_VTS, CTRL_OPTION_CMU_YUVPP, end_of_option, num_of_option = (end_of_option - OPTION_TYPE) & MASK_OF_ID, }; #endif