/* sound/soc/samsung/slif/slif.h * * ALSA SoC - Samsung VTS Serial Local Interface driver * * Copyright (c) 2019 Samsung Electronics Co. Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __SND_SOC_SLIF_H #define __SND_SOC_SLIF_H #include #define GENMASK32(h, l) \ (((~0U) - (1U << (l)) + 1) & (~0U >> (32 - 1 - (h)))) #define SLIF_SOC_VERSION(m, n, r) (((m) << 16) | ((n) << 8) | (r)) #define SLIF_FLD(name) (GENMASK32(SLIF_##name##_H, \ SLIF_##name##_L)) #define SLIF_SFR(name, o, x) (SLIF_##name##_BASE + \ ((x) * SLIF_##name##_ITV) + (o)) #define SLIF_BMASK(name, x) (SLIF_##name##_MASK_BIT << \ ((x) * SLIF_##name##_ITV)) #define SLIF_MAX_CHANNEL (8) /* removed address fields */ #define SLIF_MAX_REGISTER (0x300) #define SLIF_DMIC_AUD_MAX_REGISTER (0x10) /* 1. SERIAL LIF register base */ #define SLIF_SFR_APB_BASE (0x30) #define SLIF_INT_EN_SET_BASE (0x40) #define SLIF_INT_EN_CLR_BASE (0x44) #define SLIF_INT_PEND_BASE (0x48) #define SLIF_INT_CLR_BASE (0x4C) #define SLIF_CTRL_BASE (0x100) #define SLIF_CONFIG_MASTER_BASE (0x104) #define SLIF_CONFIG_SLAVE_BASE (0x108) #define SLIF_CONFIG_DONE_BASE (0x10C) #define SLIF_SAMPLE_PCNT_BASE (0x110) #define SLIF_INPUT_EN_BASE (0x114) #define SLIF_VOL_SET_BASE (0x118) #define SLIF_VOL_SET_ITV (0x4) #define SLIF_VOL_SET(x) SLIF_SFR(VOL_SET, 0x0, x) #define SLIF_VOL_CHANGE_BASE (0x128) #define SLIF_VOL_CHANGE_ITV (0x4) #define SLIF_VOL_CHANGE(x) SLIF_SFR(VOL_CHANGE, 0x0, x) #define SLIF_CHANNEL_MAP_BASE (0x138) #define SLIF_CHANNEL_MAP_ITV (0x4) #define SLIF_DBG_INFO0_BASE (0x150) #define SLIF_DBG_INOF1_BASE (0x154) #define SLIF_MSIF_FIFO00_BASE (0x200) #define SLIF_MSIF_FIFO01_BASE (0x204) #define SLIF_MSIF_FIFO10_BASE (0x208) #define SLIF_MSIF_FIFO11_BASE (0x20C) #define SLIF_MSIF_FIFO20_BASE (0x210) #define SLIF_MSIF_FIFO21_BASE (0x214) #define SLIF_MSIF_FIFO30_BASE (0x218) #define SLIF_MSIF_FIFO31_BASE (0x21C) #define SLIF_SSIF_FIFO00_BASE (0x220) #define SLIF_SSIF_FIFO01_BASE (0x224) #define SLIF_SSIF_FIFO10_BASE (0x228) #define SLIF_SSIF_FIFO11_BASE (0x22C) #define SLIF_SSIF_FIFO20_BASE (0x230) #define SLIF_SSIF_FIFO21_BASE (0x234) #define SLIF_SSIF_FIFO30_BASE (0x238) #define SLIF_SSIF_FIFO31_BASE (0x23C) #define SLIF_CONTROL_AHB_WMASTER_BASE (0x300) #define SLIF_STARTADDR_SET0_BASE (0x304) #define SLIF_ENDADDR_SET0_BASE (0x308) #define SLIF_FILLED_SIZE_SET0_BASE (0x30C) #define SLIF_WRITE_POINTER_SET0_BASE (0x310) #define SLIF_READ_POINTER_SET0_BASE (0x314) #define SLIF_STARTADDR_SET1_BASE (0x318) #define SLIF_ENDADDR_SET1_BASE (0x31C) #define SLIF_FILLED_SIZE_SET1_BASE (0x320) #define SLIF_WRITE_POINTER_SET1_BASE (0x324) #define SLIF_READ_POINTER_SET1_BASE (0x328) /* SYS REG : 0x15510000 + 1010 */ #define SLIF_SEL_PAD_AUD_BASE (0x0) /* 0x15511010 */ #define SLIF_SEL_DIV2_CLK_BASE (0x4) /* 0x15511014 */ /* INT_EN_SET */ /* INT_EN_CLR */ /* INT_PEND */ /* INT_CLR */ /* SLIF_CTRL_BASE */ #define SLIF_CTRL_MASTER_IF_EN_H (0) #define SLIF_CTRL_MASTER_IF_EN_L (0) #define SLIF_CTRL_MASTER_IF_EN_MASK SLIF_FLD(CTRL_MASTER_IF_EN) #define SLIF_CTRL_SLAVE_IF_EN_H (4) #define SLIF_CTRL_SLAVE_IF_EN_L (4) #define SLIF_CTRL_SLAVE_IF_EN_MASK SLIF_FLD(CTRL_SLAVE_IF_EN) #define SLIF_CTRL_SPU_EN_H (8) #define SLIF_CTRL_SPU_EN_L (8) #define SLIF_CTRL_SPU_EN_MASK SLIF_FLD(CTRL_SPU_EN) #define SLIF_CTRL_LOOPBACK_EN_H (12) #define SLIF_CTRL_LOOPBACK_EN_L (12) #define SLIF_CTRL_LOOPBACK_EN_MASK SLIF_FLD(CTRL_LOOPBACK_EN) /* CONFIG_MASTER */ #if (SLIF_SOC_VERSION(1, 0, 0) == CONFIG_SND_SOC_SAMSUNG_SLIF_VERSION) #define SLIF_CONFIG_MASTER_OPMODE_H (3) #define SLIF_CONFIG_MASTER_OPMODE_L (0) #define SLIF_CONFIG_MASTER_OPMODE_MASK SLIF_FLD(CONFIG_MASTER_OPMODE) #define SLIF_CONFIG_MASTER_WS_MODE_H (4) #define SLIF_CONFIG_MASTER_WS_MODE_L (4) #define SLIF_CONFIG_MASTER_WS_MODE_MASK SLIF_FLD(CONFIG_MASTER_WS_MODE) #define SLIF_CONFIG_MASTER_WS_POLAR_H (8) #define SLIF_CONFIG_MASTER_WS_POLAR_L (8) #define SLIF_CONFIG_MASTER_WS_POLAR_MASK SLIF_FLD(CONFIG_MASTER_WS_POLAR) #define SLIF_CONFIG_MASTER_DIFF_MSIF_STR_H (15) #define SLIF_CONFIG_MASTER_DIFF_MSIF_STR_L (12) #define SLIF_CONFIG_MASTER_DIFF_MSIF_STR_MASK SLIF_FLD(CONFIG_MASTER_DIFF_MSIF_STR) #elif (SLIF_SOC_VERSION(1, 1, 1) == CONFIG_SND_SOC_SAMSUNG_SLIF_VERSION) #define SLIF_CONFIG_MASTER_OP_D_H (3) #define SLIF_CONFIG_MASTER_OP_D_L (3) #define SLIF_CONFIG_MASTER_OP_D_MASK SLIF_FLD(CONFIG_MASTER_OP_D) #define SLIF_CONFIG_MASTER_OP_C_H (2) #define SLIF_CONFIG_MASTER_OP_C_L (0) #define SLIF_CONFIG_MASTER_OP_C_MASK SLIF_FLD(CONFIG_MASTER_OP_C) #define SLIF_CONFIG_MASTER_WS_MODE_H (4) #define SLIF_CONFIG_MASTER_WS_MODE_L (4) #define SLIF_CONFIG_MASTER_WS_MODE_MASK SLIF_FLD(CONFIG_MASTER_WS_MODE) #define SLIF_CONFIG_MASTER_WS_POLAR_H (8) #define SLIF_CONFIG_MASTER_WS_POLAR_L (8) #define SLIF_CONFIG_MASTER_WS_POLAR_MASK SLIF_FLD(CONFIG_MASTER_WS_POLAR) #define SLIF_CONFIG_MASTER_DIFF_MSIF_STR_H (15) #define SLIF_CONFIG_MASTER_DIFF_MSIF_STR_L (12) #define SLIF_CONFIG_MASTER_DIFF_MSIF_STR_MASK SLIF_FLD(CONFIG_MASTER_DIFF_MSIF_STR) #elif (SLIF_SOC_VERSION(1, 1, 2) >= CONFIG_SND_SOC_SAMSUNG_SLIF_VERSION) #define SLIF_CONFIG_MASTER_BCLK_POLAR_H (24) #define SLIF_CONFIG_MASTER_BCLK_POLAR_L (24) #define SLIF_CONFIG_MASTER_BCLK_POLAR_MASK SLIF_FLD(CONFIG_MASTER_BCLK_POLAR) #define SLIF_CONFIG_MASTER_WS_MODE_H (20) #define SLIF_CONFIG_MASTER_WS_MODE_L (20) #define SLIF_CONFIG_MASTER_WS_MODE_MASK SLIF_FLD(CONFIG_MASTER_WS_MODE) #define SLIF_CONFIG_MASTER_BCLK_SEL_H (16) #define SLIF_CONFIG_MASTER_BCLK_SEL_L (16) #define SLIF_CONFIG_MASTER_BCLK_SEL_MASK SLIF_FLD(CONFIG_MASTER_BCLK_SEL) #define SLIF_CONFIG_MASTER_WS_POLAR_H (8) #define SLIF_CONFIG_MASTER_WS_POLAR_L (8) #define SLIF_CONFIG_MASTER_WS_POLAR_MASK SLIF_FLD(CONFIG_MASTER_WS_POLAR) #define SLIF_CONFIG_MASTER_OP_D_H (4) #define SLIF_CONFIG_MASTER_OP_D_L (3) #define SLIF_CONFIG_MASTER_OP_D_MASK SLIF_FLD(CONFIG_MASTER_OP_D) #define SLIF_CONFIG_MASTER_OP_C_H (2) #define SLIF_CONFIG_MASTER_OP_C_L (0) #define SLIF_CONFIG_MASTER_OP_C_MASK SLIF_FLD(CONFIG_MASTER_OP_C) #else #error "SLIF_SOC_VERSION is not defined" #endif /* CONFIG_SLAVE */ #if (SLIF_SOC_VERSION(1, 0, 0) == CONFIG_SND_SOC_SAMSUNG_SLIF_VERSION) #define SLIF_CONFIG_SLAVE_OPMODE_H (3) #define SLIF_CONFIG_SLAVE_OPMODE_L (0) #define SLIF_CONFIG_SLAVE_OPMODE_MASK SLIF_FLD(CONFIG_SLAVE_OPMODE) #define SLIF_CONFIG_SLAVE_WS_MODE_H (4) #define SLIF_CONFIG_SLAVE_WS_MODE_L (4) #define SLIF_CONFIG_SLAVE_WS_MODE_MASK SLIF_FLD(CONFIG_SLAVE_WS_MODE) #define SLIF_CONFIG_SLAVE_WS_POLAR_H (8) #define SLIF_CONFIG_SLAVE_WS_POLAR_L (8) #define SLIF_CONFIG_SLAVE_WS_POLAR_MASK SLIF_FLD(CONFIG_SLAVE_WS_POLAR) #define SLIF_CONFIG_SLAVE_DIFF_MSIF_STR_H (15) #define SLIF_CONFIG_SLAVE_DIFF_MSIF_STR_L (12) #define SLIF_CONFIG_SLAVE_DIFF_MSIF_STR_MASK SLIF_FLD(CONFIG_SLAVE_DIFF_MSIF_STR) #define SLIF_CONFIG_SLAVE_BCLK_SEL_H (16) #define SLIF_CONFIG_SLAVE_BCLK_SEL_L (16) #define SLIF_CONFIG_SLAVE_BCLK_SEL_MASK SLIF_FLD(CONFIG_SLAVE_BCLK_SEL) #elif (SLIF_SOC_VERSION(1, 1, 1) == CONFIG_SND_SOC_SAMSUNG_SLIF_VERSION) #define SLIF_CONFIG_SLAVE_OP_D_H (3) #define SLIF_CONFIG_SLAVE_OP_D_L (3) #define SLIF_CONFIG_SLAVE_OP_D_MASK SLIF_FLD(CONFIG_SLAVE_OP_D) #define SLIF_CONFIG_SLAVE_OP_C_H (2) #define SLIF_CONFIG_SLAVE_OP_C_L (0) #define SLIF_CONFIG_SLAVE_OP_C_MASK SLIF_FLD(CONFIG_SLAVE_OP_C) #define SLIF_CONFIG_SLAVE_WS_MODE_H (4) #define SLIF_CONFIG_SLAVE_WS_MODE_L (4) #define SLIF_CONFIG_SLAVE_WS_MODE_MASK SLIF_FLD(CONFIG_SLAVE_WS_MODE) #define SLIF_CONFIG_SLAVE_WS_POLAR_H (8) #define SLIF_CONFIG_SLAVE_WS_POLAR_L (8) #define SLIF_CONFIG_SLAVE_WS_POLAR_MASK SLIF_FLD(CONFIG_SLAVE_WS_POLAR) #define SLIF_CONFIG_SLAVE_DIFF_MSIF_STR_H (15) #define SLIF_CONFIG_SLAVE_DIFF_MSIF_STR_L (12) #define SLIF_CONFIG_SLAVE_DIFF_MSIF_STR_MASK SLIF_FLD(CONFIG_SLAVE_DIFF_MSIF_STR) #define SLIF_CONFIG_SLAVE_BCLK_SEL_H (16) #define SLIF_CONFIG_SLAVE_BCLK_SEL_L (16) #define SLIF_CONFIG_SLAVE_BCLK_SEL_MASK SLIF_FLD(CONFIG_SLAVE_BCLK_SEL) #elif (SLIF_SOC_VERSION(1, 1, 2) >= CONFIG_SND_SOC_SAMSUNG_SLIF_VERSION) #define SLIF_CONFIG_SLAVE_BCLK_POLAR_H (24) #define SLIF_CONFIG_SLAVE_BCLK_POLAR_L (24) #define SLIF_CONFIG_SLAVE_BCLK_POLAR_MASK SLIF_FLD(CONFIG_MASTER_BCLK_POLAR) #define SLIF_CONFIG_SLAVE_WS_MODE_H (20) #define SLIF_CONFIG_SLAVE_WS_MODE_L (20) #define SLIF_CONFIG_SLAVE_WS_MODE_MASK SLIF_FLD(CONFIG_MASTER_WS_MODE) #define SLIF_CONFIG_SLAVE_BCLK_SEL_H (16) #define SLIF_CONFIG_SLAVE_BCLK_SEL_L (16) #define SLIF_CONFIG_SLAVE_BCLK_SEL_MASK SLIF_FLD(CONFIG_MASTER_BCLK_SEL) #define SLIF_CONFIG_SLAVE_WS_POLAR_H (8) #define SLIF_CONFIG_SLAVE_WS_POLAR_L (8) #define SLIF_CONFIG_SLAVE_WS_POLAR_MASK SLIF_FLD(CONFIG_MASTER_WS_POLAR) #define SLIF_CONFIG_SLAVE_OP_D_H (4) #define SLIF_CONFIG_SLAVE_OP_D_L (3) #define SLIF_CONFIG_SLAVE_OP_D_MASK SLIF_FLD(CONFIG_MASTER_OP_D) #define SLIF_CONFIG_SLAVE_OP_C_H (2) #define SLIF_CONFIG_SLAVE_OP_C_L (0) #define SLIF_CONFIG_SLAVE_OP_C_MASK SLIF_FLD(CONFIG_MASTER_OP_C) #else #error "SLIF_SOC_VERSION is not defined" #endif /* CONFIG_DONE */ #define SLIF_CONFIG_DONE_ALL_CONFIG_H (0) #define SLIF_CONFIG_DONE_ALL_CONFIG_L (0) #define SLIF_CONFIG_DONE_ALL_CONFIG_MASK SLIF_FLD(CONFIG_DONE_ALL_CONFIG) #define SLIF_CONFIG_DONE_MASTER_CONFIG_H (4) #define SLIF_CONFIG_DONE_MASTER_CONFIG_L (4) #define SLIF_CONFIG_DONE_MASTER_CONFIG_MASK SLIF_FLD(CONFIG_DONE_MASTER_CONFIG) #define SLIF_CONFIG_DONE_SLAVE_CONFIG_H (8) #define SLIF_CONFIG_DONE_SLAVE_CONFIG_L (8) #define SLIF_CONFIG_DONE_SLAVE_CONFIG_MASK SLIF_FLD(CONFIG_DONE_SLAVE_CONFIG) /* SAMPLE_PCNT */ /* INPUT_EN */ #define SLIF_INPUT_EN_EN0_H (0) #define SLIF_INPUT_EN_EN0_L (0) #define SLIF_INPUT_EN_EN0_MASK SLIF_FLD(INPUT_EN_EN0) #define SLIF_INPUT_EN_EN1_H (1) #define SLIF_INPUT_EN_EN1_L (1) #define SLIF_INPUT_EN_EN1_MASK SLIF_FLD(INPUT_EN_EN1) #define SLIF_INPUT_EN_EN2_H (2) #define SLIF_INPUT_EN_EN2_L (2) #define SLIF_INPUT_EN_EN2_MASK SLIF_FLD(INPUT_EN_EN2) #define SLIF_INPUT_EN_EN3_H (3) #define SLIF_INPUT_EN_EN3_L (3) #define SLIF_INPUT_EN_EN3_MASK SLIF_FLD(INPUT_EN_EN3) #define SLIF_INPUT_EN_FADE_IN_EN0_H (4) #define SLIF_INPUT_EN_FADE_IN_EN0_L (4) #define SLIF_INPUT_EN_FADE_IN_EN0_MASK SLIF_FLD(INPUT_EN_FADE_IN_EN0) #define SLIF_INPUT_EN_FADE_IN_EN1_H (5) #define SLIF_INPUT_EN_FADE_IN_EN1_L (5) #define SLIF_INPUT_EN_FADE_IN_EN1_MASK SLIF_FLD(INPUT_EN_FADE_IN_EN1) #define SLIF_INPUT_EN_FADE_IN_EN2_H (6) #define SLIF_INPUT_EN_FADE_IN_EN2_L (6) #define SLIF_INPUT_EN_FADE_IN_EN2_MASK SLIF_FLD(INPUT_EN_FADE_IN_EN2) #define SLIF_INPUT_EN_FADE_IN_EN3_H (7) #define SLIF_INPUT_EN_FADE_IN_EN3_L (7) #define SLIF_INPUT_EN_FADE_IN_EN3_MASK SLIF_FLD(INPUT_EN_FADE_IN_EN3) #define SLIF_INPUT_EN_FADE_OUT_EN0_H (8) #define SLIF_INPUT_EN_FADE_OUT_EN0_L (8) #define SLIF_INPUT_EN_FADE_OUT_EN0_MASK SLIF_FLD(INPUT_EN_FADE_IN_EN0) #define SLIF_INPUT_EN_FADE_OUT_EN1_H (9) #define SLIF_INPUT_EN_FADE_OUT_EN1_L (9) #define SLIF_INPUT_EN_FADE_OUT_EN1_MASK SLIF_FLD(INPUT_EN_FADE_IN_EN1) #define SLIF_INPUT_EN_FADE_OUT_EN2_H (10) #define SLIF_INPUT_EN_FADE_OUT_EN2_L (10) #define SLIF_INPUT_EN_FADE_OUT_EN2_MASK SLIF_FLD(INPUT_EN_FADE_IN_EN2) #define SLIF_INPUT_EN_FADE_OUT_EN3_H (11) #define SLIF_INPUT_EN_FADE_OUT_EN3_L (11) #define SLIF_INPUT_EN_FADE_OUT_EN3_MASK SLIF_FLD(INPUT_EN_FADE_IN_EN3) /* VOL_SET */ #define SLIF_VOL_SET_H (23) #define SLIF_VOL_SET_L (0) #define SLIF_VOL_SET_MASK SLIF_FLD(VOL_SET) /* VOL_change */ #define SLIF_VOL_CHANGE_H (23) #define SLIF_VOL_CHANGE_L (0) #define SLIF_VOL_CHANGE_MASK SLIF_FLD(VOL_CHANGE) /* CHANNEL_MAP */ #define SLIF_CHANNEL_MAP_MASK_BIT (0xF) #define SLIF_CHANNEL_MAP_MASK(x) SLIF_BMASK(CHANNEL_MAP, x) /* DBG_INFO0 */ /* DBG_INFO1 */ /* MSIF_FIFO00 */ /* MSIF_FIFO01 */ /* MSIF_FIFO10 */ /* MSIF_FIFO11 */ /* MSIF_FIFO20 */ /* MSIF_FIFO21 */ /* MSIF_FIFO30 */ /* MSIF_FIFO31 */ /* SSIF_FIFO00 */ /* SSIF_FIFO01 */ /* SSIF_FIFO10 */ /* SSIF_FIFO11 */ /* SSIF_FIFO20 */ /* SSIF_FIFO21 */ /* SSIF_FIFO30 */ /* SSIF_FIFO31 */ /* CONTROL_AHB_WMASTER */ #define SLIF_CONTROL_AHB_WMASTER_DIABLE_OVERFLOW_BUFFER_H (0) #define SLIF_CONTROL_AHB_WMASTER_DIABLE_OVERFLOW_BUFFER_L (0) #define SLIF_CONTROL_AHB_WMASTER_DIABLE_OVERFLOW_BUFFER_MASK \ SLIF_FLD(CONTROL_AHB_WMASTER_DIABLE_OVERFLOW_BUFFER) #define SLIF_CONTROL_AHB_WMASTER_SETINFO_H (4) #define SLIF_CONTROL_AHB_WMASTER_SETINFO_L (4) #define SLIF_CONTROL_AHB_WMASTER_SETINFO_MASK \ SLIF_FLD(CONTROL_AHB_WMASTER_SETINFO) #define SLIF_CONTROL_AHB_WMASTER_ENABLE_AHB_WMASTER_H (8) #define SLIF_CONTROL_AHB_WMASTER_ENABLE_AHB_WMASTER_L (8) #define SLIF_CONTROL_AHB_WMASTER_ENABLE_AHB_WMASTER_MASK \ SLIF_FLD(CONTROL_AHB_WMASTER_ENABLE_AHB_WMASTER) /* STARTADDR_SET0 */ #define SLIF_STARTADDR_SET0_H (31) #define SLIF_STARTADDR_SET0_L (2) #define SLIF_STARTADDR_SET0_MASK SLIF_FLD(STARTADDR_SET0) /* ENDADDR_SET0 */ #define SLIF_ENDADDR_SET0_H (31) #define SLIF_ENDADDR_SET0_L (2) #define SLIF_ENDADDR_SET0_MASK SLIF_FLD(ENDADDR_SET0) /* FILLED_SIZE_SET0 */ #define SLIF_FILLED_SIZE_SET0_H (31) #define SLIF_FILLED_SIZE_SET0_L (2) #define SLIF_FILLED_SIZE_SET0_MASK SLIF_FLD(FILLED_SIZE_SET0) /* WRITE_POINTER_SET0 */ #define SLIF_WRITE_POINTER_SET0_H (31) #define SLIF_WRITE_POINTER_SET0_L (2) #define SLIF_WRITE_POINTER_SET0_MASK SLIF_FLD(WRITE_POINTER_SET0) /* READ_POINTER_SET0 */ #define SLIF_READ_POINTER_SET0_H (31) #define SLIF_READ_POINTER_SET0_L (2) #define SLIF_READ_POINTER_SET0_MASK SLIF_FLD(READ_POINTER_SET0) /* STARTADDR_SET1 */ #define SLIF_STARTADDR_SET1_H (31) #define SLIF_STARTADDR_SET1_L (2) #define SLIF_STARTADDR_SET1_MASK SLIF_FLD(STARTADDR_SET1) /* ENDADDR_SET1 */ #define SLIF_ENDADDR_SET1_H (31) #define SLIF_ENDADDR_SET1_L (2) #define SLIF_ENDADDR_SET1_MASK SLIF_FLD(ENDADDR_SET1) /* FILLED_SIZE_SET1 */ #define SLIF_FILLED_SIZE_SET1_H (31) #define SLIF_FILLED_SIZE_SET1_L (2) #define SLIF_FILLED_SIZE_SET1_MASK SLIF_FLD(FILLED_SIZE_SET1) /* WRITE_POINTER_SET1 */ #define SLIF_WRITE_POINTER_SET1_H (31) #define SLIF_WRITE_POINTER_SET1_L (2) #define SLIF_WRITE_POINTER_SET1_MASK SLIF_FLD(WRITE_POINTER_SET1) /* READ_POINTER_SET1 */ #define SLIF_READ_POINTER_SET1_H (31) #define SLIF_READ_POINTER_SET1_L (2) #define SLIF_READ_POINTER_SET1_MASK SLIF_FLD(READ_POINTER_SET1) /* 2. DMIC AUD register base */ #define SLIF_SFR_ENABLE_DMIC_AUD_BASE (0x0) #define SLIF_SFR_CONTROL_DMIC_AUD_BASE (0x4) #define SLIF_SFR_CONTROL_DMIC_AUD_HPF_SEL_H (6) #define SLIF_SFR_CONTROL_DMIC_AUD_HPF_SEL_L (1) #define SLIF_SFR_CONTROL_DMIC_AUD_HPF_SEL_MASK \ SLIF_FLD(SFR_CONTROL_DMIC_AUD_HPF_SEL) #define SLIF_SFR_CONTROL_DMIC_AUD_SYS_SEL_H (14) #define SLIF_SFR_CONTROL_DMIC_AUD_SYS_SEL_L (12) #define SLIF_SFR_CONTROL_DMIC_AUD_SYS_SEL_MASK \ SLIF_FLD(SFR_CONTROL_DMIC_AUD_SYS_SEL) #define SLIF_SFR_CONTROL_DMIC_AUD_GAIN_H (26) #define SLIF_SFR_CONTROL_DMIC_AUD_GAIN_L (21) #define SLIF_SFR_CONTROL_DMIC_AUD_GAIN_MASK \ SLIF_FLD(SFR_CONTROL_DMIC_AUD_GAIN) #define SLIF_SFR_CONTROL_DMIC_AUD_HPF_EN_H (31) #define SLIF_SFR_CONTROL_DMIC_AUD_HPF_EN_L (31) #define SLIF_SFR_CONTROL_DMIC_AUD_HPF_EN_MASK \ SLIF_FLD(SFR_CONTROL_DMIC_AUD_HPF_EN) #define SLIF_SFR_GAIN_MODE_BASE (0x8) #define SLIF_SFR_MAX_SCALE_MODE_BASE (0xC) #define SLIF_SFR_MAX_SCALE_GAIN_BASE (0x10) #define SLIF_DMIC_AUD_NUM_MAX (3) /* 3. DMIC AUD value */ #if (IS_ENABLED(CONFIG_SOC_S5E9925)) #define SLIF_DMIC_AUD_NUM (3) #elif (IS_ENABLED(CONFIG_SOC_S5E8825)) #define SLIF_DMIC_AUD_NUM (2) #endif #define SLIF_DEFAULT_GAIN_MODE (0x1717) #define SLIF_DEFAULT_MAX_SCALE_GAIN (0x85) #define SLIF_DEFAULT_CONTROL_DMIC_AUD (0x8C6300CC) enum slif_mode { SLIF_MODE_SLAVE, SLIF_MODE_MASTER, SLIF_MODE_BOTH, }; enum slif_state { SLIF_STATE_CLOSED, SLIF_STATE_OPENED, SLIF_STATE_SET_PARAM, SLIF_STATE_DMA_ENBLED, SLIF_STATE_DMA_DISABLED, }; enum slif_gain_mode { GAIN_MODE0, GAIN_MODE1, GAIN_MODE2, }; enum slif_max_scale_gain { MAX_SCALE_GAIN0, MAX_SCALE_GAIN1, MAX_SCALE_GAIN2, }; enum slif_control_dmic_aud { CONTROL_DMIC_AUD0, CONTROL_DMIC_AUD1, CONTROL_DMIC_AUD2, }; enum slif_vol_set { VOL_SET0, VOL_SET1, VOL_SET2, VOL_SET3, }; enum s_lif_channel_map { MAP_CH0, MAP_CH1, MAP_CH2, MAP_CH3, MAP_CH4, MAP_CH5, MAP_CH6, MAP_CH7, }; enum slif_clk_input_path { SLIF_CLK_PLL_AUD0, /* 294.912MHz */ SLIF_CLK_PLL_AUD1, SLIF_CLK_OSCCLK_RCO, /* 24.576MHz */ SLIF_CLK_RCO_PMU, /* 49.152MHz */ }; struct slif_data { /* id */ struct platform_device *pdev; struct device *dev; struct device *dev_vts; struct vts_data *vts_data; int id; char name[64]; /* resouece */ void __iomem *sfr_base; void __iomem *sfr_sys_base; void __iomem *sram_base; void __iomem *dmic_aud[SLIF_DMIC_AUD_NUM_MAX]; struct regmap *regmap_sfr; struct regmap *regmap_dmic_aud[SLIF_DMIC_AUD_NUM_MAX]; struct clk *clk_mux_dmic_aud_user; struct clk *clk_mux_dmic_aud; struct clk *clk_mux_serial_lif; struct clk *clk_dmic_aud_pad; struct clk *clk_dmic_aud_div2; struct clk *clk_dmic_aud; struct clk *clk_mux_dmic_aud0; struct clk *clk_mux_dmic_aud1; struct clk *clk_serial_lif; struct clk *clk_slif_src; struct pinctrl *pinctrl; struct delayed_work mute_work; unsigned int mute_ms; bool mute_enable; bool clk_enable; /* data */ unsigned int gain_mode[SLIF_DMIC_AUD_NUM_MAX]; unsigned int max_scale_gain[SLIF_DMIC_AUD_NUM_MAX]; unsigned int control_dmic_aud[SLIF_DMIC_AUD_NUM_MAX]; unsigned int dmic_en[SLIF_DMIC_AUD_NUM_MAX]; unsigned int channel_map; unsigned int channels; unsigned int rate; unsigned int width; unsigned int clk_input_path; unsigned int clk_table_id; unsigned int slif_dump_enabled; /* sync */ wait_queue_head_t ipc_wait_queue; spinlock_t ipc_spinlock; struct mutex ipc_mutex; spinlock_t state_spinlock; struct wakeup_source *wake_lock; /* status */ volatile bool enabled; volatile bool running; unsigned long state; unsigned long mode; unsigned int fmt; /* alsa data */ struct snd_soc_component *cmpnt; struct snd_soc_card *card; /* ETC. */ unsigned int last_array[10]; }; #endif /* __SND_SOC_SLIF_H */