/* * Copyright (c) 2019 Samsung Electronics Co., Ltd. * * Author: Hajun Sung * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * Device Tree binding constants for Exynos2100 interrupt controller. */ #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_S5E_9925_H #define _DT_BINDINGS_INTERRUPT_CONTROLLER_S5E_9925_H #include #define EXT_INTA0_OUT0 0 #define EXT_INTA0_OUT1 1 #define EXT_INTA0_OUT2 2 #define EXT_INTA0_OUT3 3 #define EXT_INTA0_OUT4 4 #define EXT_INTA0_OUT5 5 #define EXT_INTA0_OUT6 6 #define EXT_INTA0_OUT7 7 #define EXT_INTA1_OUT0 8 #define EXT_INTA1_OUT1 9 #define EXT_INTA1_OUT2 10 #define EXT_INTA1_OUT3 11 #define EXT_INTA1_OUT4 12 #define EXT_INTA1_OUT5 13 #define EXT_INTA1_OUT6 14 #define EXT_INTA1_OUT7 15 #define EXT_INTA2_OUT0 16 #define EXT_INTA2_OUT1 17 #define EXT_INTA2_OUT2 18 #define EXT_INTA2_OUT3 19 #define EXT_INTA2_OUT4 20 #define EXT_INTA2_OUT5 21 #define EXT_INTA2_OUT6 22 #define EXT_INTA2_OUT7 23 #define EXT_INTA3_OUT0 24 #define EXT_INTA3_OUT1 25 #define EXT_INTA3_OUT2 26 #define EXT_INTA3_OUT3 27 #define EXT_INTA3_OUT4 28 #define EXT_INTA3_OUT5 29 #define EXT_INTA3_OUT6 30 #define EXT_INTA3_OUT7 31 #define EXT_INTA4_OUT0 32 #define EXT_INTA4_OUT1 33 #define INTREQ__ALIVE_GNSS_ACTIVE 34 #define INTREQ__CLKMON_MONCLK 35 #define INTREQ__CLKMON_REFSTUCK 36 #define INTREQ__COMB_NONSECURE_INTCOMB_VGPIO2AP 37 #define INTREQ__COMB_SFI_CE_NONSECURE_SYSREG_ALIVE 38 #define INTREQ__COMB_SFI_UCE_NONSECURE_SYSREG_ALIVE 39 #define INTREQ__DBGCORE_UART 40 #define INTREQ__MAILBOX_APM2AP 41 #define INTREQ__MAILBOX_CHUB2AP 42 #define INTREQ__MAILBOX_CP2AP_0 43 #define INTREQ__MAILBOX_CP2AP_1 44 #define INTREQ__MAILBOX_CP2AP_2 45 #define INTREQ__MAILBOX_CP2AP_3 46 #define INTREQ__MAILBOX_CP2AP_4 47 #define INTREQ__MAILBOX_DBGCORE2AP 48 #define INTREQ__MAILBOX_GNSS2AP 49 #define INTREQ__MCT_ALIVE_IRQ_0 50 #define INTREQ__MCT_ALIVE_IRQ_1 51 #define INTREQ__MCT_ALIVE_IRQ_2 52 #define INTREQ__MCT_ALIVE_IRQ_3 53 #define INTREQ__MCT_ALIVE_IRQ_4 54 #define INTREQ__MCT_ALIVE_IRQ_5 55 #define INTREQ__MCT_ALIVE_IRQ_6 56 #define INTREQ__MCT_ALIVE_IRQ_7 57 #define INTREQ__MCT_ALIVE_IRQ_8 58 #define INTREQ__MCT_ALIVE_IRQ_9 59 #define INTREQ__MCT_ALIVE_IRQ_10 60 #define INTREQ__MCT_ALIVE_IRQ_11 61 #define INTREQ__MCT_ALIVE_S_IRQ_0 62 #define INTREQ__MCT_ALIVE_S_IRQ_1 63 #define INTREQ__MCT_ALIVE_S_IRQ_2 64 #define INTREQ__MCT_ALIVE_S_IRQ_3 65 #define INTREQ__NOTIFY 66 #define INTREQ__RTC_ALARM_INT 67 #define INTREQ__RTC_TIC_INT_0 68 #define INTREQ__S_MAILBOX_CP2AP 69 #define INTREQ__SPMI_MASTER_PMIC_0 70 #define INTREQ__SPMI_MASTER_PMIC_1 71 #define INTREQ__TOP_RTC_ALARM_INT 72 #define INTREQ__TOP_RTC_TIC_INT_0 73 #define INTREQ__AUD_ABOX_GIC400 74 #define INTREQ__AUD_WDT 75 #define INTREQ__PPMU_AUD 76 #define INTREQ__SYSMMU_AUD_S1_NS 77 #define INTREQ__SYSMMU_AUD_S1_S 78 #define INTREQ__SYSMMU_AUD_S2_NS 79 #define INTREQ__SYSMMU_AUD_S2_S 80 #define INTREQ__ADD_BRP 81 #define INTREQ__BYRP_0 82 #define INTREQ__BYRP_1 83 #define INTREQ__PPMU_BRP 84 #define INTREQ__RGBP_0 85 #define INTREQ__RGBP_1 86 #define INTREQ__SYSMMU_D0_BRP_S1_NS 87 #define INTREQ__SYSMMU_D0_BRP_S1_S 88 #define INTREQ__SYSMMU_D0_BRP_S2_NS 89 #define INTREQ__SYSMMU_D0_BRP_S2_S 90 #define INTREQ__SYSMMU_D1_BRP_S1_NS 91 #define INTREQ__SYSMMU_D1_BRP_S1_S 92 #define INTREQ__SYSMMU_D1_BRP_S2_NS 93 #define INTREQ__SYSMMU_D1_BRP_S2_S 94 #define INTREQ__SYSMMU_D2_BRP_S1_NS 95 #define INTREQ__SYSMMU_D2_BRP_S1_S 96 #define INTREQ__SYSMMU_D2_BRP_S2_NS 97 #define INTREQ__SYSMMU_D2_BRP_S2_S 98 #define INTREQ__EXT_INTH0_0 99 #define INTREQ__EXT_INTH0_1 100 #define INTREQ__EXT_INTH0_2 101 #define INTREQ__EXT_INTH0_3 102 #define INTREQ__EXT_INTH1_0 103 #define INTREQ__EXT_INTH1_1 104 #define INTREQ__EXT_INTH1_2 105 #define INTREQ__EXT_INTH1_3 106 #define INTREQ__EXT_INTH2_0 107 #define INTREQ__EXT_INTH2_1 108 #define INTREQ__EXT_INTH2_2 109 #define INTREQ__EXT_INTH2_3 110 #define INTREQ__EXT_INTH3_0 111 #define INTREQ__EXT_INTH3_1 112 #define INTREQ__EXT_INTH3_2 113 #define INTREQ__EXT_INTH3_3 114 #define INTREQ__EXT_INTH4_0 115 #define INTREQ__EXT_INTH4_1 116 #define INTREQ__EXT_INTH4_2 117 #define INTREQ__EXT_INTH4_3 118 #define INTREQ__EXT_INTH5_0 119 #define INTREQ__EXT_INTH5_1 120 #define INTREQ__EXT_INTH5_2 121 #define INTREQ__EXT_INTH5_3 122 #define INTREQ__EXT_INTH5_4 123 #define INTREQ__I2C_CHUB 124 #define INTREQ__I3C_CHUB 125 #define INTREQ__MAILBOX_AP_VTS 126 #define INTREQ__CMGP_I2C 127 #define INTREQ__EXT_INTM00 128 #define INTREQ__EXT_INTM01 129 #define INTREQ__EXT_INTM02 130 #define INTREQ__EXT_INTM03 131 #define INTREQ__EXT_INTM04 132 #define INTREQ__EXT_INTM05 133 #define INTREQ__EXT_INTM06 134 #define INTREQ__EXT_INTM07 135 #define INTREQ__EXT_INTM08 136 #define INTREQ__EXT_INTM09 137 #define INTREQ__EXT_INTM10 138 #define INTREQ__EXT_INTM11 139 #define INTREQ__EXT_INTM12 140 #define INTREQ__EXT_INTM13 141 #define INTREQ__EXT_INTM14 142 #define INTREQ__EXT_INTM15 143 #define INTREQ__EXT_INTM16 144 #define INTREQ__EXT_INTM17 145 #define INTREQ__EXT_INTM18 146 #define INTREQ__EXT_INTM19 147 #define INTREQ__EXT_INTM20 148 #define INTREQ__EXT_INTM21 149 #define INTREQ__EXT_INTM22 150 #define INTREQ__EXT_INTM23 151 #define INTREQ__EXT_INTM24 152 #define INTREQ__EXT_INTM25 153 #define INTREQ__EXT_INTM26 154 #define INTREQ__EXT_INTM27 155 #define INTREQ__EXT_INTM28 156 #define INTREQ__EXT_INTM29 157 #define INTREQ__EXT_INTM30 158 #define INTREQ__EXT_INTM31 159 #define INTREQ__SPI_I2C_CHUB0 160 #define INTREQ__SPI_I2C_CHUB1 161 #define INTREQ__EXT_INTM34 162 #define INTREQ__EXT_INTM35 163 #define INTREQ__EXT_INTM36 164 #define INTREQ__EXT_INTM37 165 #define INTREQ__EXT_INTM38 166 #define INTREQ__I2C_CMGP2 167 #define INTREQ__I2C_CMGP3 168 #define INTREQ__I2C_CMGP4 169 #define INTREQ__I2C_CMGP5 170 #define INTREQ__I2C_CMGP6 171 #define INTREQ__TIMER_CHUB 172 #define INTREQ__SPI_I2C_CMGP0 173 #define INTREQ__SPI_I2C_CMGP1 174 #define INTREQ__USI_CMGP0 175 #define INTREQ__USI_CMGP1 176 #define INTREQ__USI_CMGP2 177 #define INTREQ__USI_CMGP3 178 #define INTREQ__USI_CMGP4 179 #define INTREQ__USI_CMGP5 180 #define INTREQ__USI_CMGP6 181 #define CMU_CPUCL0_PLL_CTRL_USER_IRQ 182 #define CMU_CPUCL1_PLL_CTRL_USER_IRQ 183 #define CMU_CPUCL2_PLL_CTRL_USER_IRQ 184 #define CMU_DSU_PLL_CTRL_USER_IRQ 185 #define INTREQ__CPUCL0_CLUSTERCRITIRQ 186 #define INTREQ__CPUCL0_CLUSTERERRIRQ 187 #define INTREQ__CPUCL0_CLUSTERFAULTIRQ 188 #define INTREQ__CPUCL0_CLUSTERPMUIRQ 189 #define INTREQ__CPUCL0_CTIIRQ_8 190 #define INTREQ__CPUCL0_COMPLEXERRIRQ_0 191 #define INTREQ__CPUCL0_COMPLEXERRIRQ_1 192 #define INTREQ__CPUCL0_COMPLEXFAULTIRQ_0 193 #define INTREQ__CPUCL0_COMPLEXFAULTIRQ_1 194 #define INTREQ__CPUCL0_COREERRIRQ_0 195 #define INTREQ__CPUCL0_COREERRIRQ_1 196 #define INTREQ__CPUCL0_COREERRIRQ_2 197 #define INTREQ__CPUCL0_COREERRIRQ_3 198 #define INTREQ__CPUCL0_COREERRIRQ_4 199 #define INTREQ__CPUCL0_COREERRIRQ_5 200 #define INTREQ__CPUCL0_COREERRIRQ_6 201 #define INTREQ__CPUCL0_COREERRIRQ_7 202 #define INTREQ__CPUCL0_COREFAULTIRQ_0 203 #define INTREQ__CPUCL0_COREFAULTIRQ_1 204 #define INTREQ__CPUCL0_COREFAULTIRQ_2 205 #define INTREQ__CPUCL0_COREFAULTIRQ_3 206 #define INTREQ__CPUCL0_COREFAULTIRQ_4 207 #define INTREQ__CPUCL0_COREFAULTIRQ_5 208 #define INTREQ__CPUCL0_COREFAULTIRQ_6 209 #define INTREQ__CPUCL0_COREFAULTIRQ_7 210 #define INTREQ__CPUCL0_DPM 211 #define INTREQ__CPUCL0_MPAMNSIRQ 212 #define INTREQ__CPUCL0_MPAMSIRQ 213 #define INTREQ__OCP_REATOR_CPUCL0_0 214 #define INTREQ__OCP_REATOR_CPUCL0_1 215 #define INTREQ__OCP_REATOR_CPUCL0_2 216 #define INTREQ__OCP_REATOR_CPUCL0_3 217 #define INTREQ__PPC_INSTRRET_LOWER_CPUCL0_0 218 #define INTREQ__PPC_INSTRRET_LOWER_CPUCL0_1 219 #define INTREQ__PPC_INSTRRET_UPPER_CPUCL0_0 220 #define INTREQ__PPC_INSTRRET_UPPER_CPUCL0_1 221 #define INTREQ__HDCP 222 #define INTREQ__TBASE 223 #define INTREQ__SECURE_LOG 224 #define INTREQ__RPMB 225 #define INTREQ__S2_LV3_TABLE_ALLOC 226 #define INTREQ__DUMMY_S2MPU 227 #define INTREQ__PPC_INSTRRUN_LOWER_CPUCL0_0 230 #define INTREQ__PPC_INSTRRUN_LOWER_CPUCL0_1 231 #define INTREQ__PPC_INSTRRUN_UPPER_CPUCL0_0 232 #define INTREQ__PPC_INSTRRUN_UPPER_CPUCL0_1 233 #define O_DDD_IRQ_FAST_0_CPUCL0 234 #define O_DDD_IRQ_FAST_1_CPUCL0 235 #define O_DDD_IRQ_FAST_2_CPUCL0 236 #define O_DDD_IRQ_FAST_3_CPUCL0 237 #define O_DDD_IRQ_FAST_4_CPUCL0 238 #define O_DDD_IRQ_FAST_5_CPUCL0 239 #define O_DDD_IRQ_SLOW_0_CPUCL0 240 #define O_DDD_IRQ_SLOW_1_CPUCL0 241 #define O_DDD_IRQ_SLOW_2_CPUCL0 242 #define O_DDD_IRQ_SLOW_3_CPUCL0 243 #define O_DDD_IRQ_SLOW_4_CPUCL0 244 #define O_DDD_IRQ_SLOW_5_CPUCL0 245 #define INTREQ__USI_CHUB0 246 #define O_INTREQ__ADD_CTRL_0_CPUCL0 247 #define O_INTREQ__ADD_CTRL_1_CPUCL0 248 #define O_INTREQ__ADD_CTRL_2_CPUCL0 249 #define O_STR_IRQ_0_CPUCL0 250 #define O_STR_IRQ_1_CPUCL0 251 #define O_STR_IRQ_2_CPUCL0 252 #define O_STR_IRQ_3_CPUCL0 253 #define O_VOL_ERROR_DDD_HIGH_0_CPUCL0 254 #define O_VOL_ERROR_DDD_HIGH_1_CPUCL0 255 #define O_VOL_ERROR_DDD_HIGH_2_CPUCL0 256 #define O_VOL_ERROR_DDD_HIGH_3_CPUCL0 257 #define O_VOL_ERROR_DDD_HIGH_4_CPUCL0 258 #define O_VOL_ERROR_DDD_HIGH_5_CPUCL0 259 #define O_VOL_ERROR_DDD_LOW_0_CPUCL0 260 #define O_VOL_ERROR_DDD_LOW_1_CPUCL0 261 #define O_VOL_ERROR_DDD_LOW_2_CPUCL0 262 #define O_VOL_ERROR_DDD_LOW_3_CPUCL0 263 #define O_VOL_ERROR_DDD_LOW_4_CPUCL0 264 #define O_VOL_ERROR_DDD_LOW_5_CPUCL0 265 #define INTREQ__CSIS0 266 #define INTREQ__CSIS1 267 #define INTREQ__CSIS2 268 #define INTREQ__CSIS3 269 #define INTREQ__CSIS4 270 #define INTREQ__CSIS5 271 #define INTREQ__CSIS6 272 #define INTREQ__CSIS_DMA0 273 #define INTREQ__CSIS_DMA1 274 #define INTREQ__CSIS_DMA2 275 #define INTREQ__CSIS_DMA3 276 #define INTREQ__CSIS_DMA4 277 #define INTREQ__OIS_MCU_CSIS 278 #define INTREQ__OVERFLOW_CSIS_PDP 279 #define INTREQ__PDP0 280 #define INTREQ__PDP1 281 #define INTREQ__PDP2 282 #define INTREQ__PDP3 283 #define INTREQ__PDP4 284 #define INTREQ__PDP5 285 #define INTREQ__PDP6 286 #define INTREQ__PDP7 287 #define INTREQ__PPMU_CSIS 288 #define INTREQ__SYSMMU_D0_CSIS_S1_NS 289 #define INTREQ__SYSMMU_D0_CSIS_S1_S 290 #define INTREQ__SYSMMU_D0_CSIS_S2_NS 291 #define INTREQ__SYSMMU_D0_CSIS_S2_S 292 #define INTREQ__SYSMMU_D1_CSIS_S1_NS 293 #define INTREQ__SYSMMU_D1_CSIS_S1_S 294 #define INTREQ__SYSMMU_D1_CSIS_S2_NS 295 #define INTREQ__SYSMMU_D1_CSIS_S2_S 296 #define INTREQ__SYSMMU_D2_CSIS_S1_NS 297 #define INTREQ__SYSMMU_D2_CSIS_S1_S 298 #define INTREQ__SYSMMU_D2_CSIS_S2_NS 299 #define INTREQ__SYSMMU_D2_CSIS_S2_S 300 #define INTREQ__USI_CHUB1 301 #define INTREQ__USI_CHUB2 302 #define INTREQ__USI_CHUB3 303 #define INTREQ__WDT_CHUB 304 #define INTREQ__WDT_VTS 305 #define INTRQ_PWM_CHUB_0 306 #define INTRQ_PWM_CHUB_1 307 #define INTRQ_PWM_CHUB_2 308 #define INTREQ__WDTRESET_OIS_MCU 309 #define INTREQ__CSTAT_CH0_0 310 #define INTREQ__CSTAT_CH0_1 311 #define INTREQ__CSTAT_CH1_0 312 #define INTREQ__CSTAT_CH1_1 313 #define INTREQ__CSTAT_CH2_0 314 #define INTREQ__CSTAT_CH2_1 315 #define INTREQ__CSTAT_CH3_0 316 #define INTREQ__CSTAT_CH3_1 317 #define INTREQ__PPMU_CSTAT 318 #define INTREQ__SYSMMU_D_CSTAT_S1_NS 319 #define INTREQ__SYSMMU_D_CSTAT_S1_S 320 #define INTREQ__SYSMMU_D_CSTAT_S2_NS 321 #define INTREQ__SYSMMU_D_CSTAT_S2_S 322 #define INTREQ__ADD_CTRL_DNC 323 #define INTREQ__DD_ERR_IRQ_FAST_DNC 324 #define INTREQ__DD_ERR_IRQ_SLOW_DNC 325 #define INTREQ__DD_SZ_HIGH_DNC 326 #define INTREQ__DD_SZ_LOW_DNC 327 #define INTREQ__FROM_DNC_TO_HOST_NS_0 328 #define INTREQ__FROM_DNC_TO_HOST_NS_1 329 #define INTREQ__FROM_DNC_TO_HOST_NS_2 330 #define INTREQ__FROM_DNC_TO_HOST_NS_3 331 #define INTREQ__FROM_DNC_TO_HOST_NS_4 332 #define INTREQ__FROM_DNC_TO_HOST_NS_5 333 #define INTREQ__FROM_DNC_TO_HOST_NS_6 334 #define INTREQ__FROM_DNC_TO_HOST_NS_7 335 #define INTREQ__FROM_DNC_TO_HOST_S_0 336 #define INTREQ__FROM_DNC_TO_HOST_S_1 337 #define INTREQ__FROM_DNC_TO_HOST_S_2 338 #define INTREQ__FROM_DNC_TO_HOST_S_3 339 #define INTREQ__FROM_DNC_TO_HOST_S_4 340 #define INTREQ__FROM_DNC_TO_HOST_S_5 341 #define INTREQ__FROM_DNC_TO_HOST_S_6 342 #define INTREQ__FROM_DNC_TO_HOST_S_7 343 #define INTRQ_PWM_CHUB_3 344 #define INTREQ__O_OCP_THROTT_INTR_DNC 345 #define INTREQ__PPMU_DNC 346 #define INTREQ__SYSMMU_IPDNC_O_INTERRUPT_S1_NS 347 #define INTREQ__SYSMMU_IPDNC_O_INTERRUPT_S1_S 348 #define INTREQ__SYSMMU_IPDNC_O_INTERRUPT_S2_NS 349 #define INTREQ__SYSMMU_IPDNC_O_INTERRUPT_S2_S 350 #define INTREQ__SYSMMU_SDMA0_O_INTERRUPT_S1_NS 351 #define INTREQ__SYSMMU_SDMA0_O_INTERRUPT_S1_S 352 #define INTREQ__SYSMMU_SDMA0_O_INTERRUPT_S2_NS 353 #define INTREQ__SYSMMU_SDMA0_O_INTERRUPT_S2_S 354 #define INTREQ__SYSMMU_SDMA1_O_INTERRUPT_S1_NS 355 #define INTREQ__SYSMMU_SDMA1_O_INTERRUPT_S1_S 356 #define INTREQ__SYSMMU_SDMA1_O_INTERRUPT_S2_NS 357 #define INTREQ__SYSMMU_SDMA1_O_INTERRUPT_S2_S 358 #define INTREQ__SYSMMU_SDMA2_O_INTERRUPT_S1_NS 359 #define INTREQ__SYSMMU_SDMA2_O_INTERRUPT_S1_S 360 #define INTREQ__SYSMMU_SDMA2_O_INTERRUPT_S2_NS 361 #define INTREQ__SYSMMU_SDMA2_O_INTERRUPT_S2_S 362 #define INTREQ__SYSMMU_SDMA3_O_INTERRUPT_S1_NS 363 #define INTREQ__SYSMMU_SDMA3_O_INTERRUPT_S1_S 364 #define INTREQ__SYSMMU_SDMA3_O_INTERRUPT_S2_NS 365 #define INTREQ__SYSMMU_SDMA3_O_INTERRUPT_S2_S 366 #define INTREQ__DPUB_DECON0_DQE_DIMMING_END 367 #define INTREQ__DPUB_DECON0_DQE_DIMMING_START 368 #define INTREQ__DPUB_DECON0_EXTRA 369 #define INTREQ__DPUB_DECON0_FRAME_DONE 370 #define INTREQ__DPUB_DECON0_FRAME_START 371 #define INTREQ__DPUB_DECON1_DQE_DIMMING_END 372 #define INTREQ__DPUB_DECON1_DQE_DIMMING_START 373 #define INTREQ__DPUB_DECON1_EXTRA 374 #define INTREQ__DPUB_DECON1_FRAME_DONE 375 #define INTREQ__DPUB_DECON1_FRAME_START 376 #define INTREQ__DPUB_DECON2_EXTRA 377 #define INTREQ__DPUB_DECON2_FRAME_DONE 378 #define INTREQ__DPUB_DECON2_FRAME_START 379 #define INTREQ__DPUB_DECON3_EXTRA 380 #define INTREQ__DPUB_DECON3_FRAME_DONE 381 #define INTREQ__DPUB_DECON3_FRAME_START 382 #define INTREQ__DPUB_DSIM0 383 #define INTREQ__DPUB_DSIM1 384 #define INTREQ__DPUB_DSIM2 385 #define INTREQ__MPC 386 #define INTREQ__NFI 387 #define INTREQ__SENSOR_ABORT 388 #define INTREQ__DPUB_VRR0 389 #define INTREQ__DPUB_VRR1 390 #define INTREQ__DMA_C2A0_MST 391 #define INTREQ__DMA_C2A0_SLV 392 #define INTREQ__DMA_C2A1_MST 393 #define INTREQ__DMA_C2A1_SLV 394 #define INTREQ__DMA_CGCTRL0 395 #define INTREQ__DMA_CGCTRL1 396 #define INTREQ__DMA_DSIMFC0 397 #define INTREQ__DMA_DSIMFC1 398 #define INTREQ__DMA_DSIMFC2 399 #define INTREQ__DMA_L0 400 #define INTREQ__DMA_L1 401 #define INTREQ__DMA_L2 402 #define INTREQ__DMA_L3 403 #define INTREQ__DMA_L4 404 #define INTREQ__DMA_L5 405 #define INTREQ__DMA_L6 406 #define INTREQ__DMA_L7 407 #define INTREQ__DMA_L8 408 #define INTREQ__DMA_L9 409 #define INTREQ__DMA_L10 410 #define INTREQ__DMA_L11 411 #define INTREQ__DMA_L12 412 #define INTREQ__DMA_L13 413 #define INTREQ__DMA_L14 414 #define INTREQ__DMA_L15 415 #define INTREQ__DMA_WB0 416 #define INTREQ__DMA_WB1 417 #define INTREQ__DPP_L0 418 #define INTREQ__DPP_L1 419 #define INTREQ__DPP_L2 420 #define INTREQ__DPP_L3 421 #define INTREQ__DPP_L4 422 #define INTREQ__DPP_L5 423 #define INTREQ__DPP_L6 424 #define INTREQ__DPP_L7 425 #define INTREQ__DPP_L8 426 #define INTREQ__DPP_L9 427 #define INTREQ__DPP_L10 428 #define INTREQ__DPP_L11 429 #define INTREQ__DPP_L12 430 #define INTREQ__DPP_L13 431 #define INTREQ__DPP_L14 432 #define INTREQ__DPP_L15 433 #define INTREQ__PPMU_GLUE0 434 #define INTREQ__PPMU_GLUE1 435 #define INTREQ__SRAMCON_D0 436 #define INTREQ__SRAMCON_D1 437 #define INTREQ__SRAMCON_D2 438 #define INTREQ__SRAMCON_D3 439 #define INTREQ__SYSMMU_D0_DPUF0_S1_NS 440 #define INTREQ__SYSMMU_D0_DPUF0_S1_S 441 #define INTREQ__SYSMMU_D0_DPUF0_S2_NS 442 #define INTREQ__SYSMMU_D0_DPUF0_S2_S 443 #define INTREQ__SYSMMU_D0_DPUF1_S1_NS 444 #define INTREQ__SYSMMU_D0_DPUF1_S1_S 445 #define INTREQ__SYSMMU_D0_DPUF1_S2_NS 446 #define INTREQ__SYSMMU_D0_DPUF1_S2_S 447 #define INTREQ__SYSMMU_D1_DPUF0_S1_NS 448 #define INTREQ__SYSMMU_D1_DPUF0_S1_S 449 #define INTREQ__SYSMMU_D1_DPUF0_S2_NS 450 #define INTREQ__SYSMMU_D1_DPUF0_S2_S 451 #define INTREQ__SYSMMU_D1_DPUF1_S1_NS 452 #define INTREQ__SYSMMU_D1_DPUF1_S1_S 453 #define INTREQ__SYSMMU_D1_DPUF1_S2_NS 454 #define INTREQ__SYSMMU_D1_DPUF1_S2_S 455 #define INTREQ__GDC_IRQ_0 456 #define INTREQ__GDC_IRQ_1 457 #define INTREQ__FRC_MC_DBL_ERR 458 #define INTREQ__FRC_MC_DONE 459 #define INTREQ__MCFP_INTREQ_0 460 #define INTREQ__MCFP_INTREQ_1 461 #define INTREQ__SYSMMU_D3_MCSC_S1_NS 462 #define INTREQ__SYSMMU_D3_MCSC_S1_S 463 #define INTREQ__SYSMMU_D3_MCSC_S2_NS 464 #define CMU_G3DCORE_PLL_CTRL_USER_IRQ 465 #define INTREQ__ADD_CTRL_G3D 466 #define INTREQ__GPU_INT 467 #define INTREQ__HTU_G3D_INT 468 #define O_DDD_IRQ_FAST_G3D 469 #define O_DDD_IRQ_SLOW_G3D 470 #define INTREQ__SYSMMU_D3_MCSC_S2_S 471 #define INTREQ__SYSMMU_D4_MCSC_S1_NS 472 #define O_VOL_ERROR_DDD_HIGH_G3D 473 #define O_VOL_ERROR_DDD_LOW_G3D 474 #define INTREQ__GNSS_PPMU_IRQ 475 #define INTREQ__GNSS_SW_INT 476 #define INTREQ__GNSS_WAKEUP_INT 477 #define INTREQ__GNSS_WDOG_RESET 478 #define INTREQ__DP_LINK 479 #define INTREQ__PPMU_HSI0 480 #define INTREQ__USB2_REMOTE_CONNECT_GIC 481 #define INTREQ__USB2_REMOTE_TIMER_GIC 482 #define INTREQ__USB2_REMOTE_WAKEUP_GIC 483 #define INTREQ__USB20_PHY_FSVPLUS_MINUS_GIC 484 #define INTREQ__USB32DRD_GIC0 485 #define INTREQ__USB32DRD_GIC1 486 #define INTREQ__USB32DRD_REWA_WAKEUP_REQ 487 #define INTREQ__USBDPPHY_TCA 488 #define O_INTERRUPT_S2_NS 489 #define O_INTERRUPT_S2_S 490 #define INTREQ__GPIO_HSI1 491 #define INTREQ__SYSMMU_D4_MCSC_S1_S 492 #define INTREQ__SYSMMU_D4_MCSC_S2_NS 493 #define INTREQ__PCIE_GEN2 494 #define INTREQ__PCIE_GEN2A_MSI_0 495 #define INTREQ__PCIE_GEN2A_MSI_1 496 #define INTREQ__PCIE_GEN2A_MSI_2 497 #define INTREQ__PCIE_GEN2A_MSI_3 498 #define INTREQ__PCIE_GEN2A_MSI_4 499 #define INTREQ__PCIE_GEN3 500 #define INTREQ__PCIE_GEN3A_MSI_0 501 #define INTREQ__PCIE_GEN3A_MSI_1 502 #define INTREQ__PCIE_GEN3A_MSI_2 503 #define INTREQ__PCIE_GEN3A_MSI_3 504 #define INTREQ__PCIE_GEN3A_MSI_4 505 #define INTREQ__PCIE_IA_GEN2 506 #define INTREQ__PCIE_IA_GEN3 507 #define INTREQ__PCIE_PCS_GEN2 508 #define INTREQ__PCIE_PCS_GEN3 509 #define INTREQ__PPMU_HSI1 510 #define INTREQ__SYSMMU_HSI1_S1_NONSECURE 511 #define INTREQ__SYSMMU_HSI1_S1_SECURE 512 #define INTREQ__SYSMMU_HSI1_S2_NONSECURE 513 #define INTREQ__SYSMMU_HSI1_S2_SECURE 514 #define INTREQ__SYSMMU_D4_MCSC_S2_S 515 #define INTREQ_WOW_DVFS 516 #define INTREQ__TREX_D0_ACP_debugInterrupt 517 #define INTREQ__LME_O_INT0 518 #define INTREQ__PPMU_LME 519 #define INTREQ__SYSMMU_D_LME_S1_NONSECURE 520 #define INTREQ__SYSMMU_D_LME_S1_SECURE 521 #define INTREQ__SYSMMU_D_LME_S2_NONSECURE 522 #define INTREQ__SYSMMU_D_LME_S2_SECURE 523 #define INTREQ__TREX_D1_ACP_debugInterrupt 524 #define INTREQ__M2M__JPEG0 525 #define INTREQ__M2M__JPEG1 526 #define INTREQ__M2M__JSQZ 527 #define INTREQ__M2M__M2M 528 #define INTREQ__M2M__SYSMMU_D_M2M_PM_S1_NS 529 #define INTREQ__M2M__SYSMMU_D_M2M_PM_S1_S 530 #define INTREQ__M2M__SYSMMU_D_M2M_PM_S2_NS 531 #define INTREQ__M2M__SYSMMU_D_M2M_PM_S2_S 532 #define INTREQ__PPMU_M2M 533 #define INTREQ__I3C00 534 #define INTREQ__I3C01 535 #define INTREQ__I3C02 536 #define INTREQ__I3C03_OIS 537 #define INTREQ__USI05_USI_OIS 538 #define INTREQ__USI06_USI_OIS 539 #define INTREQ_SEMA_ACK_AP 540 #define INTREQ__SEMA_TIMEOUT 541 #define INTREQ__PPMU_D_UFD 542 #define INTREQ__SYSMMU_D_UFD_S1_NS 543 #define INTREQ__SYSMMU_D_UFD_S1_S 544 #define INTREQ__SYSMMU_D_UFD_S2_NS 545 #define INTREQ__SYSMMU_D_UFD_S2_S 546 #define INTREQ__GPIO_HSI1UFS 547 #define INTREQ__GPIO_UFS 548 #define INTREQ__MMC_CARD 549 #define INTREQ__PPMU_UFS 550 #define INTREQ__SYSMMU_UFS_S2_NONSECURE 551 #define INTREQ__SYSMMU_UFS_S2_SECURE 552 #define INTREQ__UFS_EMBD 553 #define INTREQ__SYSMMU_D0_YUVP_S1_NS 554 #define INTREQ__SYSMMU_D0_YUVP_S1_S 555 #define INTREQ__SYSMMU_D0_YUVP_S2_NS 556 #define INTREQ__SYSMMU_D0_YUVP_S2_S 557 #define INTREQ__SYSMMU_D1_YUVP_S1_NS 558 #define INTREQ__SYSMMU_D1_YUVP_S1_S 559 #define INTREQ__SYSMMU_D1_YUVP_S2_NS 560 #define INTREQ__SYSMMU_D1_YUVP_S2_S 561 #define INTREQ__MCSC_INTREQ_0 563 #define INTREQ__MCSC_INTREQ_1 564 #define INTREQ__PPMU_MCSC 565 #define INTREQ__SYSMMU_D0_MCSC_S1_NS 566 #define INTREQ__SYSMMU_D0_MCSC_S1_S 567 #define INTREQ__SYSMMU_D0_MCSC_S2_NS 568 #define INTREQ__SYSMMU_D0_MCSC_S2_S 569 #define INTREQ__SYSMMU_D1_MCSC_S1_NS 570 #define INTREQ__SYSMMU_D1_MCSC_S1_S 571 #define INTREQ__SYSMMU_D1_MCSC_S2_NS 572 #define INTREQ__SYSMMU_D1_MCSC_S2_S 573 #define INTREQ__SYSMMU_D2_MCSC_S1_NS 574 #define INTREQ__SYSMMU_D2_MCSC_S1_S 575 #define INTREQ__SYSMMU_D2_MCSC_S2_NS 576 #define INTREQ__SYSMMU_D2_MCSC_S2_S 577 #define INTREQ__MFC0 578 #define INTREQ__PPMU_MFC0 579 #define INTREQ__SYSMMU_MFC0D0_interrupt_s1_ns 580 #define INTREQ__SYSMMU_MFC0D0_interrupt_s1_s 581 #define INTREQ__SYSMMU_MFC0D0_interrupt_s2_ns 582 #define INTREQ__SYSMMU_MFC0D0_interrupt_s2_s 583 #define INTREQ__SYSMMU_MFC0D1_interrupt_s1_ns 584 #define INTREQ__SYSMMU_MFC0D1_interrupt_s1_s 585 #define INTREQ__SYSMMU_MFC0D1_interrupt_s2_ns 586 #define INTREQ__SYSMMU_MFC0D1_interrupt_s2_s 587 #define INTREQ__WFD 588 #define INTREQ__MFC1 589 #define INTREQ__PPMU_MFC1 590 #define INTREQ__SYSMMU_MFC1D0_interrupt_s1_ns 591 #define INTREQ__SYSMMU_MFC1D0_interrupt_s1_s 592 #define INTREQ__SYSMMU_MFC1D0_interrupt_s2_ns 593 #define INTREQ__SYSMMU_MFC1D0_interrupt_s2_s 594 #define INTREQ__SYSMMU_MFC1D1_interrupt_s1_ns 595 #define INTREQ__SYSMMU_MFC1D1_interrupt_s1_s 596 #define INTREQ__SYSMMU_MFC1D1_interrupt_s2_ns 597 #define INTREQ__SYSMMU_MFC1D1_interrupt_s2_s 598 #define INTREQ__DMC_ECC_CORERR_MIF0 599 #define INTREQ__DMC_ECC_UNCORERR_MIF0 600 #define INTREQ__DMC_PPMPINT_MIF0 601 #define INTREQ__DMC_TEMPERR_MIF0 602 #define INTREQ__DMC_TEMPHOT_MIF0 603 #define INTREQ__DMC_TZCINT_MIF0 604 #define INTREQ__PPMU_MIF_MIF0 605 #define INTREQ__DMC_ECC_CORERR_MIF1 606 #define INTREQ__DMC_ECC_UNCORERR_MIF1 607 #define INTREQ__DMC_PPMPINT_MIF1 608 #define INTREQ__DMC_TEMPERR_MIF1 609 #define INTREQ__DMC_TEMPHOT_MIF1 610 #define INTREQ__DMC_TZCINT_MIF1 611 #define INTREQ__PPMU_MIF_MIF1 612 #define INTREQ__DMC_ECC_CORERR_MIF2 613 #define INTREQ__DMC_ECC_UNCORERR_MIF2 614 #define INTREQ__DMC_PPMPINT_MIF2 615 #define INTREQ__DMC_TEMPERR_MIF2 616 #define INTREQ__DMC_TEMPHOT_MIF2 617 #define INTREQ__DMC_TZCINT_MIF2 618 #define INTREQ__PPMU_MIF_MIF2 619 #define INTREQ__DMC_ECC_CORERR_MIF3 620 #define INTREQ__DMC_ECC_UNCORERR_MIF3 621 #define INTREQ__DMC_PPMPINT_MIF3 622 #define INTREQ__DMC_TEMPERR_MIF3 623 #define INTREQ__DMC_TEMPHOT_MIF3 624 #define INTREQ__DMC_TZCINT_MIF3 625 #define INTREQ__PPMU_MIF_MIF3 626 #define INTREQ_CPALV_GPIO 627 #define INTREQ_MODEM_PPMU 628 #define INTREQ_RESET_REQ 629 #define INTREQ__CCI_ERRINT_COR 630 #define INTREQ__CCI_ERRINT_UNCOR 631 #define INTREQ__CCI_TZCINT 632 #define INTREQ__PPC_DEBUG_CCI_PPC_INTR 633 #define INTREQ__PPMU_WOW_GLUE_O_INTREQ__WOW_DVFS_SCI_GIC 634 #define INTREQ__PPMU_WOW_GLUE_O_INTREQ__WOW_DVFS_SMC_GIC 635 #define INTREQ__PPMU_WOW_GLUE_O_PPMU_INTC 636 #define INTREQ__SYSMMU_APM_S2_NONSECURE 637 #define INTREQ__SYSMMU_APM_S2_SECURE 638 #define INTREQ__SYSMMU_G3D_S2_NONSECURE 639 #define INTREQ__SYSMMU_G3D_S2_SECURE 640 #define INTREQ__SYSMMU_MODEM_S1_NONSECURE 641 #define INTREQ__SYSMMU_MODEM_S1_SECURE 642 #define INTREQ__SYSMMU_MODEM_S2_NONSECURE 643 #define INTREQ__SYSMMU_MODEM_S2_SECURE 644 #define INTREQ__TREX_D_NOCL0_debugInterrupt 645 #define INTREQ__TREX_P_NOCL0_debugInterrupt 646 #define INTREQ__DIT_RxDst00 647 #define INTREQ__DIT_RxDst01 648 #define INTREQ__DIT_RxDst1 649 #define INTREQ__DIT_RxDst02 650 #define INTREQ__DIT_RxDst2 651 #define INTREQ__DIT_RxDst03 652 #define INTREQ__DIT_RxSrc0 653 #define INTREQ__DIT_RxSrc1 654 #define INTREQ__DIT_RxSrc2 655 #define INTREQ__DIT_TxDst0 656 #define INTREQ__DIT_TxDst1 657 #define INTREQ__DIT_TxDst2 658 #define INTREQ__DIT_TxSrc0 659 #define INTREQ__DIT_TxSrc1 660 #define INTREQ__DIT_TxSrc2 661 #define INTREQ__PDMA 662 #define INTREQ__PPMU 663 #define INTREQ__SPDMA 664 #define INTREQ__SYSMMU_DIT_S2_NS 665 #define INTREQ__SYSMMU_DIT_S2_S 666 #define INTREQ__SYSMMU_TT_S2_NS 669 #define INTREQ__SYSMMU_TT_S2_S 670 #define INTREQ__GPIO_PERIC0 671 #define INTREQ__USI04_I2C 672 #define INTREQ__USI04_USI 673 #define INTREQ__BT_UART 674 #define INTREQ__GPIO_PERIC1 675 #define INTREQ__USI07_SPI_I2C 679 #define INTREQ__USI07_USI 680 #define INTREQ__USI08_SPI_I2C 681 #define INTREQ__USI08_USI 682 #define INTREQ__USI09_I2C 683 #define INTREQ__USI09_USI 684 #define INTREQ__USI10_I2C 685 #define INTREQ__USI10_USI 686 #define INTREQ__DBG_UART 687 #define INTREQ__GPIO_PERIC2 688 #define INTREQ__I3C04 690 #define INTREQ__I3C05 691 #define INTREQ__I3C06 692 #define INTREQ__I3C07 693 #define INTREQ__I3C08 694 #define INTREQ__I3C09 695 #define INTREQ__I3C10 696 #define INTREQ__I3C11 697 #define INTREQ__PWM0 698 #define INTREQ__PWM1 699 #define INTREQ__PWM2 700 #define INTREQ__PWM3 701 #define INTREQ__PWM4 702 #define INTREQ__USI00_SPI_I2C 703 #define INTREQ__USI00_USI 704 #define INTREQ__USI01_SPI_I2C 705 #define INTREQ__USI01_USI 706 #define INTREQ__USI02_I2C 707 #define INTREQ__USI02_USI 708 #define INTREQ__USI03_I2C 709 #define INTREQ__USI03_USI 710 #define INTREQ__USI05_I2C 711 #define INTREQ__USI06_I2C 713 #define INTREQ__USI11_I2C 715 #define INTREQ__USI11_USI 716 #define INTREQ__PPMU_SSP_O_interrupt_upper_or_normal 728 #define INTREQ__SSS 730 #define INTREQ__SSS_DMA 733 #define INTREQ__SSS_KM 734 #define INTREQ__STRONG_0 738 #define INTREQ__STRONG_1 739 #define INTREQ__STRONG_2 740 #define INTREQ__STRONG_3 741 #define INTREQ__STRONG_CPU_WDTRESET 742 #define INTREQ__SYSMMU_NONSECURE 743 #define INTREQ__SYSMMU_SECURE 744 #define INTREQ__I3C_INTREQ 745 #define INTREQ__PDMA_INTREQ 746 #define INTREQ__UFD_0_INTREQ 748 #define INTREQ__UFD_1_INTREQ 749 #define INTREQ__UFD_2_INTREQ 750 #define INTREQ__DD_ERR_IRQ_FAST_YUVP 759 #define INTREQ__DD_ERR_IRQ_SLOW_YUVP 760 #define INTREQ__DD_SZ_HIGH_YUVP 761 #define INTREQ__DD_SZ_LOW_YUVP 762 #define INTREQ__PPMU_YUVP 764 #define INTREQ__YUVP_0 769 #define INTREQ__YUVP_1 770 #define INTREQ__TEEGRIS_EVENT 868 #define INTREQ__TEEGRIS_PANIC 869 #define INTREQ__OTP_CON_BIRA 938 #define INTREQ__TREX_DEBUG 939 #define INTREQ__OTP_CON_TOP 940 #define INTREQ__WDT0 941 #define INTREQ__WDT1 942 #define INTREQ__MCT_G0 943 #define INTREQ__MCT_G1 944 #define INTREQ__MCT_G2 945 #define INTREQ__MCT_G3 946 #define INTREQ__MCT_L0 947 #define INTREQ__MCT_L1 948 #define INTREQ__MCT_L2 949 #define INTREQ__MCT_L3 950 #define INTREQ__MCT_L4 951 #define INTREQ__MCT_L5 952 #define INTREQ__MCT_L6 953 #define INTREQ__MCT_L7 954 #define INTREQ__TMU_TMU_TOP 955 #define INTREQ__TMU_TMU_SUB 956 #define INTREQ__GIC_PMU_INT 957 #define INTREQ__GIC_ERR_INT 958 #define INTREQ__GIC_FAULT_INT 959 #endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_2100_H */