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gpio: tqmx86: store IRQ trigger type and unmask status separately

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commit 08af509efdf8dad08e972b48de0e2c2a7919ea8b upstream.

irq_set_type() should not implicitly unmask the IRQ.

All accesses to the interrupt configuration register are moved to a new
helper tqmx86_gpio_irq_config(). We also introduce the new rule that
accessing irq_type must happen while locked, which will become
significant for fixing EDGE_BOTH handling.

Fixes: b868db94a6a7 ("gpio: tqmx86: Add GPIO from for this IO controller")
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Link: https://lore.kernel.org/r/6aa4f207f77cb58ef64ffb947e91949b0f753ccd.1717063994.git.matthias.schiffer@ew.tq-group.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Matthias Schiffer 2024-05-30 12:20:01 +02:00 committed by Ksawlii
parent 8121ee9dfd
commit f042b2d8d1
1 changed files with 26 additions and 20 deletions
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46
drivers/gpio/gpio-tqmx86.c
View file

@ -27,16 +27,20 @@
#define TQMX86_GPIIC 3 /* GPI Interrupt Configuration Register */ #define TQMX86_GPIIC 3 /* GPI Interrupt Configuration Register */
#define TQMX86_GPIIS 4 /* GPI Interrupt Status Register */ #define TQMX86_GPIIS 4 /* GPI Interrupt Status Register */
#define TQMX86_GPII_NONE 0
#define TQMX86_GPII_FALLING BIT(0) #define TQMX86_GPII_FALLING BIT(0)
#define TQMX86_GPII_RISING BIT(1) #define TQMX86_GPII_RISING BIT(1)
#define TQMX86_GPII_MASK (BIT(0) | BIT(1)) #define TQMX86_GPII_MASK (BIT(0) | BIT(1))
#define TQMX86_GPII_BITS 2 #define TQMX86_GPII_BITS 2
/* Stored in irq_type with GPII bits */
#define TQMX86_INT_UNMASKED BIT(2)
struct tqmx86_gpio_data { struct tqmx86_gpio_data {
struct gpio_chip chip; struct gpio_chip chip;
struct irq_chip irq_chip; struct irq_chip irq_chip;
void __iomem *io_base; void __iomem *io_base;
int irq; int irq;
/* Lock must be held for accessing output and irq_type fields */
raw_spinlock_t spinlock; raw_spinlock_t spinlock;
u8 irq_type[TQMX86_NGPI]; u8 irq_type[TQMX86_NGPI];
}; };
@ -107,20 +111,30 @@ static int tqmx86_gpio_get_direction(struct gpio_chip *chip,
return GPIO_LINE_DIRECTION_OUT; return GPIO_LINE_DIRECTION_OUT;
} }
static void tqmx86_gpio_irq_config(struct tqmx86_gpio_data *gpio, int offset)
__must_hold(&gpio->spinlock)
{
u8 type = TQMX86_GPII_NONE, gpiic;
if (gpio->irq_type[offset] & TQMX86_INT_UNMASKED)
type = gpio->irq_type[offset] & TQMX86_GPII_MASK;
gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC);
gpiic &= ~(TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS));
gpiic |= type << (offset * TQMX86_GPII_BITS);
tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC);
}
static void tqmx86_gpio_irq_mask(struct irq_data *data) static void tqmx86_gpio_irq_mask(struct irq_data *data)
{ {
unsigned int offset = (data->hwirq - TQMX86_NGPO); unsigned int offset = (data->hwirq - TQMX86_NGPO);
struct tqmx86_gpio_data *gpio = gpiochip_get_data( struct tqmx86_gpio_data *gpio = gpiochip_get_data(
irq_data_get_irq_chip_data(data)); irq_data_get_irq_chip_data(data));
unsigned long flags; unsigned long flags;
u8 gpiic, mask;
mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS);
raw_spin_lock_irqsave(&gpio->spinlock, flags); raw_spin_lock_irqsave(&gpio->spinlock, flags);
gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); gpio->irq_type[offset] &= ~TQMX86_INT_UNMASKED;
gpiic &= ~mask; tqmx86_gpio_irq_config(gpio, offset);
tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC);
raw_spin_unlock_irqrestore(&gpio->spinlock, flags); raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
} }
@ -130,15 +144,10 @@ static void tqmx86_gpio_irq_unmask(struct irq_data *data)
struct tqmx86_gpio_data *gpio = gpiochip_get_data( struct tqmx86_gpio_data *gpio = gpiochip_get_data(
irq_data_get_irq_chip_data(data)); irq_data_get_irq_chip_data(data));
unsigned long flags; unsigned long flags;
u8 gpiic, mask;
mask = TQMX86_GPII_MASK << (offset * TQMX86_GPII_BITS);
raw_spin_lock_irqsave(&gpio->spinlock, flags); raw_spin_lock_irqsave(&gpio->spinlock, flags);
gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); gpio->irq_type[offset] |= TQMX86_INT_UNMASKED;
gpiic &= ~mask; tqmx86_gpio_irq_config(gpio, offset);
gpiic |= gpio->irq_type[offset] << (offset * TQMX86_GPII_BITS);
tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC);
raw_spin_unlock_irqrestore(&gpio->spinlock, flags); raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
} }
@ -149,7 +158,7 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type)
unsigned int offset = (data->hwirq - TQMX86_NGPO); unsigned int offset = (data->hwirq - TQMX86_NGPO);
unsigned int edge_type = type & IRQF_TRIGGER_MASK; unsigned int edge_type = type & IRQF_TRIGGER_MASK;
unsigned long flags; unsigned long flags;
u8 new_type, gpiic; u8 new_type;
switch (edge_type) { switch (edge_type) {
case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_EDGE_RISING:
@ -165,13 +174,10 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type)
return -EINVAL; /* not supported */ return -EINVAL; /* not supported */
} }
gpio->irq_type[offset] = new_type;
raw_spin_lock_irqsave(&gpio->spinlock, flags); raw_spin_lock_irqsave(&gpio->spinlock, flags);
gpiic = tqmx86_gpio_read(gpio, TQMX86_GPIIC); gpio->irq_type[offset] &= ~TQMX86_GPII_MASK;
gpiic &= ~((TQMX86_GPII_MASK) << (offset * TQMX86_GPII_BITS)); gpio->irq_type[offset] |= new_type;
gpiic |= new_type << (offset * TQMX86_GPII_BITS); tqmx86_gpio_irq_config(gpio, offset);
tqmx86_gpio_write(gpio, gpiic, TQMX86_GPIIC);
raw_spin_unlock_irqrestore(&gpio->spinlock, flags); raw_spin_unlock_irqrestore(&gpio->spinlock, flags);
return 0; return 0;