watchdog: it87_wdt: add PWRGD enable quirk for Qotom QCML04
[ Upstream commit 43439076383a7611300334d1357c0f8883f40816 ] For the watchdog timer to work properly on the QCML04 board we need to set PWRGD enable in the Environment Controller Configuration Registers Special Configuration Register 1 when it is not already set, this may be the case when the watchdog is not enabled from within the BIOS. Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20241025063441.3494837-1-james.hilliard1@gmail.com Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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1 changed files with 39 additions and 0 deletions
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@ -20,6 +20,8 @@
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/bits.h>
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#include <linux/dmi.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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@ -40,6 +42,7 @@
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#define VAL 0x2f
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/* Logical device Numbers LDN */
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#define EC 0x04
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#define GPIO 0x07
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/* Configuration Registers and Functions */
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@ -71,6 +74,12 @@
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#define IT8784_ID 0x8784
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#define IT8786_ID 0x8786
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/* Environment Controller Configuration Registers LDN=0x04 */
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#define SCR1 0xfa
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/* Environment Controller Bits SCR1 */
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#define WDT_PWRGD 0x20
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/* GPIO Configuration Registers LDN=0x07 */
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#define WDTCTRL 0x71
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#define WDTCFG 0x72
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@ -241,6 +250,21 @@ static int wdt_set_timeout(struct watchdog_device *wdd, unsigned int t)
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return ret;
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}
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enum {
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IT87_WDT_OUTPUT_THROUGH_PWRGD = BIT(0),
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};
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static const struct dmi_system_id it87_quirks[] = {
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{
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/* Qotom Q30900P (IT8786) */
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.matches = {
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DMI_EXACT_MATCH(DMI_BOARD_NAME, "QCML04"),
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},
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.driver_data = (void *)IT87_WDT_OUTPUT_THROUGH_PWRGD,
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},
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{}
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};
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static const struct watchdog_info ident = {
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.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
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.firmware_version = 1,
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@ -262,8 +286,10 @@ static struct watchdog_device wdt_dev = {
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static int __init it87_wdt_init(void)
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{
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const struct dmi_system_id *dmi_id;
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u8 chip_rev;
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u8 ctrl;
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int quirks = 0;
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int rc;
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rc = superio_enter();
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@ -274,6 +300,10 @@ static int __init it87_wdt_init(void)
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chip_rev = superio_inb(CHIPREV) & 0x0f;
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superio_exit();
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dmi_id = dmi_first_match(it87_quirks);
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if (dmi_id)
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quirks = (long)dmi_id->driver_data;
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switch (chip_type) {
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case IT8702_ID:
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max_units = 255;
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@ -334,6 +364,15 @@ static int __init it87_wdt_init(void)
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superio_outb(0x00, WDTCTRL);
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}
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if (quirks & IT87_WDT_OUTPUT_THROUGH_PWRGD) {
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superio_select(EC);
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ctrl = superio_inb(SCR1);
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if (!(ctrl & WDT_PWRGD)) {
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ctrl |= WDT_PWRGD;
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superio_outb(ctrl, SCR1);
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}
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}
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superio_exit();
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if (timeout < 1 || timeout > max_units * 60) {
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