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EDAC/fsl_ddr: Fix bad bit shift operations

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[ Upstream commit 9ec22ac4fe766c6abba845290d5139a3fbe0153b ]

Fix undefined behavior caused by left-shifting a negative value in the
expression:

    cap_high ^ (1 << (bad_data_bit - 32))

The variable bad_data_bit ranges from 0 to 63. When it is less than 32,
bad_data_bit - 32 becomes negative, and left-shifting by a negative
value in C is undefined behavior.

Fix this by combining cap_high and cap_low into a 64-bit variable.

  [ bp: Massage commit message, simplify error bits handling. ]

Fixes: ea2eb9a8b620 ("EDAC, fsl-ddr: Separate FSL DDR driver from MPC85xx")
Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20241016-imx95_edac-v3-3-86ae6fc2756a@nxp.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Priyanka Singh 2024-10-16 16:31:11 -04:00 committed by Ksawlii
parent 6042db367b
commit c97db1a208
1 changed files with 13 additions and 9 deletions
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22
drivers/edac/fsl_ddr_edac.c
View file

@ -331,21 +331,25 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
* TODO: Add support for 32-bit wide buses * TODO: Add support for 32-bit wide buses
*/ */
if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) { if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) {
u64 cap = (u64)cap_high << 32 | cap_low;
u32 s = syndrome;
sbe_ecc_decode(cap_high, cap_low, syndrome, sbe_ecc_decode(cap_high, cap_low, syndrome,
&bad_data_bit, &bad_ecc_bit); &bad_data_bit, &bad_ecc_bit);
if (bad_data_bit != -1) if (bad_data_bit >= 0) {
fsl_mc_printk(mci, KERN_ERR, fsl_mc_printk(mci, KERN_ERR, "Faulty Data bit: %d\n", bad_data_bit);
"Faulty Data bit: %d\n", bad_data_bit); cap ^= 1ULL << bad_data_bit;
if (bad_ecc_bit != -1) }
fsl_mc_printk(mci, KERN_ERR,
"Faulty ECC bit: %d\n", bad_ecc_bit); if (bad_ecc_bit >= 0) {
fsl_mc_printk(mci, KERN_ERR, "Faulty ECC bit: %d\n", bad_ecc_bit);
s ^= 1 << bad_ecc_bit;
}
fsl_mc_printk(mci, KERN_ERR, fsl_mc_printk(mci, KERN_ERR,
"Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n", "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
cap_high ^ (1 << (bad_data_bit - 32)), upper_32_bits(cap), lower_32_bits(cap), s);
cap_low ^ (1 << bad_data_bit),
syndrome ^ (1 << bad_ecc_bit));
} }
fsl_mc_printk(mci, KERN_ERR, fsl_mc_printk(mci, KERN_ERR,