Ksawlii/kernel_samsung_a53x
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

media: cobalt: Use FIELD_GET() to extract Link Width

Browse source 
[ Upstream commit f301fedbeecfdce91cb898d6fa5e62f269801fee ]

Use FIELD_GET() to extract PCIe Negotiated and Maximum Link Width fields
instead of custom masking and shifting.

Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Ilpo Järvinen 2023-09-13 15:27:40 +03:00 • committed by Ksawlii
parent 9985de3caa
commit c6ec0333c4
1 changed files with 6 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
drivers/media/pci/cobalt/cobalt-driver.c
View file

@ -8,6 +8,7 @@
* All rights reserved. * All rights reserved.
*/ */
#include <linux/bitfield.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <media/i2c/adv7604.h> #include <media/i2c/adv7604.h>
#include <media/i2c/adv7842.h> #include <media/i2c/adv7842.h>
@ -210,17 +211,17 @@ void cobalt_pcie_status_show(struct cobalt *cobalt)
pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &stat); pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &stat);
cobalt_info("PCIe link capability 0x%08x: %s per lane and %u lanes\n", cobalt_info("PCIe link capability 0x%08x: %s per lane and %u lanes\n",
capa, get_link_speed(capa), capa, get_link_speed(capa),
(capa & PCI_EXP_LNKCAP_MLW) >> 4); FIELD_GET(PCI_EXP_LNKCAP_MLW, capa));
cobalt_info("PCIe link control 0x%04x\n", ctrl); cobalt_info("PCIe link control 0x%04x\n", ctrl);
cobalt_info("PCIe link status 0x%04x: %s per lane and %u lanes\n", cobalt_info("PCIe link status 0x%04x: %s per lane and %u lanes\n",
stat, get_link_speed(stat), stat, get_link_speed(stat),
(stat & PCI_EXP_LNKSTA_NLW) >> 4); FIELD_GET(PCI_EXP_LNKSTA_NLW, stat));
/* Bus */ /* Bus */
pcie_capability_read_dword(pci_bus_dev, PCI_EXP_LNKCAP, &capa); pcie_capability_read_dword(pci_bus_dev, PCI_EXP_LNKCAP, &capa);
cobalt_info("PCIe bus link capability 0x%08x: %s per lane and %u lanes\n", cobalt_info("PCIe bus link capability 0x%08x: %s per lane and %u lanes\n",
capa, get_link_speed(capa), capa, get_link_speed(capa),
(capa & PCI_EXP_LNKCAP_MLW) >> 4); FIELD_GET(PCI_EXP_LNKCAP_MLW, capa));
/* Slot */ /* Slot */
pcie_capability_read_dword(pci_dev, PCI_EXP_SLTCAP, &capa); pcie_capability_read_dword(pci_dev, PCI_EXP_SLTCAP, &capa);
@ -239,7 +240,7 @@ static unsigned pcie_link_get_lanes(struct cobalt *cobalt)
if (!pci_is_pcie(pci_dev)) if (!pci_is_pcie(pci_dev))
return 0; return 0;
pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &link); pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &link);
return (link & PCI_EXP_LNKSTA_NLW) >> 4; return FIELD_GET(PCI_EXP_LNKSTA_NLW, link);
} }
static unsigned pcie_bus_link_get_lanes(struct cobalt *cobalt) static unsigned pcie_bus_link_get_lanes(struct cobalt *cobalt)
@ -250,7 +251,7 @@ static unsigned pcie_bus_link_get_lanes(struct cobalt *cobalt)
if (!pci_is_pcie(pci_dev)) if (!pci_is_pcie(pci_dev))
return 0; return 0;
pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &link); pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &link);
return (link & PCI_EXP_LNKCAP_MLW) >> 4; return FIELD_GET(PCI_EXP_LNKCAP_MLW, link);
} }
static void msi_config_show(struct cobalt *cobalt, struct pci_dev *pci_dev) static void msi_config_show(struct cobalt *cobalt, struct pci_dev *pci_dev)