interconnect: qcom: sc7180: Retire DEFINE_QBCM
[ Upstream commit e451b2ea5a11fb3f6d83e1f834ae6a5f55a02bba ] The struct definition macros are hard to read and compare, expand them. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230811-topic-icc_retire_macrosd-v1-11-c03aaeffc769@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org> Stable-dep-of: 1ad83c479272 ("interconnect: qcom: sc7180: Set ACV enable_mask") Signed-off-by: Sasha Levin <sashal@kernel.org>
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Konrad Dybcio
Ksawlii
parent
05370f9cda
commit
ae4a5c1aad
1 changed files with 231 additions and 24 deletions
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@ -153,30 +153,237 @@ DEFINE_QNODE(srvc_snoc, SC7180_SLAVE_SERVICE_SNOC, 1, 4);
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DEFINE_QNODE(xs_qdss_stm, SC7180_SLAVE_QDSS_STM, 1, 4);
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DEFINE_QNODE(xs_sys_tcu_cfg, SC7180_SLAVE_TCU, 1, 8);
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DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
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DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
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DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
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DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf);
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DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
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DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aop, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_rt_throttle_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_npu_dma_throttle_cfg, &qhs_npu_dsp_throttle_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm_1, &qhs_tlmm_2, &qhs_tlmm_3, &qhs_ufs_mem_cfg, &qhs_usb3, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc);
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DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qhm_mnoc_cfg, &qxm_mdp0, &qxm_rot, &qxm_venus0, &qxm_venus_arm9);
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DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu);
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DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
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DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup_core_master_1, &qup_core_master_2);
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DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
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DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps0);
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DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
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DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc);
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DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
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DEFINE_QBCM(bcm_cn1, "CN1", false, &qhm_qspi, &xm_sdc2, &xm_emmc, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2);
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DEFINE_QBCM(bcm_sn2, "SN2", false, &qxm_pimem, &qns_gemnoc_gc);
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DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
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DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
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DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp);
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DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
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DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
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DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre2_noc);
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DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gemnoc);
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static struct qcom_icc_bcm bcm_acv = {
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.name = "ACV",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &ebi },
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};
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static struct qcom_icc_bcm bcm_mc0 = {
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.name = "MC0",
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.keepalive = true,
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.num_nodes = 1,
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.nodes = { &ebi },
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};
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static struct qcom_icc_bcm bcm_sh0 = {
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.name = "SH0",
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.keepalive = true,
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.num_nodes = 1,
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.nodes = { &qns_llcc },
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};
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static struct qcom_icc_bcm bcm_mm0 = {
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.name = "MM0",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qns_mem_noc_hf },
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};
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static struct qcom_icc_bcm bcm_ce0 = {
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.name = "CE0",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qxm_crypto },
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};
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static struct qcom_icc_bcm bcm_cn0 = {
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.name = "CN0",
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.keepalive = true,
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.num_nodes = 48,
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.nodes = { &qnm_snoc,
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&xm_qdss_dap,
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&qhs_a1_noc_cfg,
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&qhs_a2_noc_cfg,
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&qhs_ahb2phy0,
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&qhs_aop,
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&qhs_aoss,
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&qhs_boot_rom,
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&qhs_camera_cfg,
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&qhs_camera_nrt_throttle_cfg,
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&qhs_camera_rt_throttle_cfg,
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&qhs_clk_ctl,
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&qhs_cpr_cx,
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&qhs_cpr_mx,
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&qhs_crypto0_cfg,
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&qhs_dcc_cfg,
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&qhs_ddrss_cfg,
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&qhs_display_cfg,
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&qhs_display_rt_throttle_cfg,
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&qhs_display_throttle_cfg,
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&qhs_glm,
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&qhs_gpuss_cfg,
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&qhs_imem_cfg,
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&qhs_ipa,
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&qhs_mnoc_cfg,
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&qhs_mss_cfg,
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&qhs_npu_cfg,
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&qhs_npu_dma_throttle_cfg,
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&qhs_npu_dsp_throttle_cfg,
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&qhs_pimem_cfg,
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&qhs_prng,
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&qhs_qdss_cfg,
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&qhs_qm_cfg,
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&qhs_qm_mpu_cfg,
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&qhs_qup0,
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&qhs_qup1,
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&qhs_security,
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&qhs_snoc_cfg,
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&qhs_tcsr,
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&qhs_tlmm_1,
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&qhs_tlmm_2,
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&qhs_tlmm_3,
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&qhs_ufs_mem_cfg,
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&qhs_usb3,
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&qhs_venus_cfg,
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&qhs_venus_throttle_cfg,
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&qhs_vsense_ctrl_cfg,
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&srvc_cnoc
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},
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};
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static struct qcom_icc_bcm bcm_mm1 = {
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.name = "MM1",
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.keepalive = false,
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.num_nodes = 8,
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.nodes = { &qxm_camnoc_hf0_uncomp,
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&qxm_camnoc_hf1_uncomp,
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&qxm_camnoc_sf_uncomp,
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&qhm_mnoc_cfg,
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&qxm_mdp0,
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&qxm_rot,
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&qxm_venus0,
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&qxm_venus_arm9
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},
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};
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static struct qcom_icc_bcm bcm_sh2 = {
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.name = "SH2",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &acm_sys_tcu },
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};
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static struct qcom_icc_bcm bcm_mm2 = {
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.name = "MM2",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qns_mem_noc_sf },
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};
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static struct qcom_icc_bcm bcm_qup0 = {
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.name = "QUP0",
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.keepalive = false,
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.num_nodes = 2,
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.nodes = { &qup_core_master_1, &qup_core_master_2 },
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};
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static struct qcom_icc_bcm bcm_sh3 = {
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.name = "SH3",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qnm_cmpnoc },
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};
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static struct qcom_icc_bcm bcm_sh4 = {
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.name = "SH4",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &acm_apps0 },
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};
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static struct qcom_icc_bcm bcm_sn0 = {
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.name = "SN0",
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.keepalive = true,
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.num_nodes = 1,
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.nodes = { &qns_gemnoc_sf },
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};
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static struct qcom_icc_bcm bcm_co0 = {
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.name = "CO0",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qns_cdsp_gemnoc },
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};
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static struct qcom_icc_bcm bcm_sn1 = {
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.name = "SN1",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qxs_imem },
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};
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static struct qcom_icc_bcm bcm_cn1 = {
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.name = "CN1",
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.keepalive = false,
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.num_nodes = 8,
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.nodes = { &qhm_qspi,
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&xm_sdc2,
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&xm_emmc,
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&qhs_ahb2phy2,
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&qhs_emmc_cfg,
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&qhs_pdm,
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&qhs_qspi,
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&qhs_sdc2
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},
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};
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static struct qcom_icc_bcm bcm_sn2 = {
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.name = "SN2",
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.keepalive = false,
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.num_nodes = 2,
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.nodes = { &qxm_pimem, &qns_gemnoc_gc },
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};
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static struct qcom_icc_bcm bcm_co2 = {
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.name = "CO2",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qnm_npu },
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};
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static struct qcom_icc_bcm bcm_sn3 = {
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.name = "SN3",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qxs_pimem },
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};
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static struct qcom_icc_bcm bcm_co3 = {
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.name = "CO3",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qxm_npu_dsp },
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};
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static struct qcom_icc_bcm bcm_sn4 = {
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.name = "SN4",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &xs_qdss_stm },
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};
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static struct qcom_icc_bcm bcm_sn7 = {
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.name = "SN7",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qnm_aggre1_noc },
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};
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static struct qcom_icc_bcm bcm_sn9 = {
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.name = "SN9",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qnm_aggre2_noc },
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};
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static struct qcom_icc_bcm bcm_sn12 = {
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.name = "SN12",
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.keepalive = false,
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.num_nodes = 1,
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.nodes = { &qnm_gemnoc },
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};
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static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
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&bcm_cn1,
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