drm: fsl-dcu: enable PIXCLK on LS1021A
[ Upstream commit ffcde9e44d3e18fde3d18bfff8d9318935413bfd ] The PIXCLK needs to be enabled in SCFG before accessing certain DCU registers, or the access will hang. For simplicity, the PIXCLK is enabled unconditionally, resulting in increased power consumption. Signed-off-by: Matthias Schiffer <matthias.schiffer@tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Fixes: 109eee2f2a18 ("drm/layerscape: Add Freescale DCU DRM driver") Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240926055552.1632448-2-alexander.stein@ew.tq-group.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -8,6 +8,7 @@ config DRM_FSL_DCU
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select DRM_PANEL
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select REGMAP_MMIO
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select VIDEOMODE_HELPERS
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select MFD_SYSCON if SOC_LS1021A
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help
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Choose this option if you have an Freescale DCU chipset.
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If M is selected the module will be called fsl-dcu-drm.
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@ -100,6 +100,7 @@ static void fsl_dcu_irq_uninstall(struct drm_device *dev)
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static int fsl_dcu_load(struct drm_device *dev, unsigned long flags)
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{
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struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
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struct regmap *scfg;
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int ret;
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ret = fsl_dcu_drm_modeset_init(fsl_dev);
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@ -108,6 +109,20 @@ static int fsl_dcu_load(struct drm_device *dev, unsigned long flags)
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return ret;
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}
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scfg = syscon_regmap_lookup_by_compatible("fsl,ls1021a-scfg");
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if (PTR_ERR(scfg) != -ENODEV) {
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/*
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* For simplicity, enable the PIXCLK unconditionally,
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* resulting in increased power consumption. Disabling
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* the clock in PM or on unload could be implemented as
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* a future improvement.
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*/
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ret = regmap_update_bits(scfg, SCFG_PIXCLKCR, SCFG_PIXCLKCR_PXCEN,
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SCFG_PIXCLKCR_PXCEN);
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if (ret < 0)
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return dev_err_probe(dev->dev, ret, "failed to enable pixclk\n");
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}
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ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
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if (ret < 0) {
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dev_err(dev->dev, "failed to initialize vblank\n");
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@ -160,6 +160,9 @@
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#define FSL_DCU_ARGB4444 12
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#define FSL_DCU_YUV422 14
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#define SCFG_PIXCLKCR 0x28
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#define SCFG_PIXCLKCR_PXCEN BIT(31)
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#define VF610_LAYER_REG_NUM 9
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#define LS1021A_LAYER_REG_NUM 10
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