Ksawlii/kernel_samsung_a53x
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

x86/cpu: Enable STIBP on AMD if Automatic IBRS is enabled

Browse source 
commit fd470a8beed88440b160d690344fbae05a0b9b1b upstream.

Unlike Intel's Enhanced IBRS feature, AMD's Automatic IBRS does not
provide protection to processes running at CPL3/user mode, see section
"Extended Feature Enable Register (EFER)" in the APM v2 at
https://bugzilla.kernel.org/attachment.cgi?id=304652

Explicitly enable STIBP to protect against cross-thread CPL3
branch target injections on systems with Automatic IBRS enabled.

Also update the relevant documentation.

Fixes: e7862eda309e ("x86/cpu: Support AMD Automatic IBRS")
Reported-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20230720194727.67022-1-kim.phillips@amd.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Kim Phillips 2023-07-20 14:47:27 -05:00 • committed by Ksawlii
parent 2ff65e968b
commit 8abcca4816
2 changed files with 16 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
Documentation/admin-guide/hw-vuln/spectre.rst
View file

@ -484,11 +484,14 @@ Spectre variant 2
Systems which support enhanced IBRS (eIBRS) enable IBRS protection once at Systems which support enhanced IBRS (eIBRS) enable IBRS protection once at
boot, by setting the IBRS bit, and they're automatically protected against boot, by setting the IBRS bit, and they're automatically protected against
Spectre v2 variant attacks, including cross-thread branch target injections Spectre v2 variant attacks.
on SMT systems (STIBP). In other words, eIBRS enables STIBP too.
Legacy IBRS systems clear the IBRS bit on exit to userspace and On Intel's enhanced IBRS systems, this includes cross-thread branch target
therefore explicitly enable STIBP for that injections on SMT systems (STIBP). In other words, Intel eIBRS enables
STIBP, too.
AMD Automatic IBRS does not protect userspace, and Legacy IBRS systems clear
the IBRS bit on exit to userspace, therefore both explicitly enable STIBP.
The retpoline mitigation is turned on by default on vulnerable The retpoline mitigation is turned on by default on vulnerable
CPUs. It can be forced on or off by the administrator CPUs. It can be forced on or off by the administrator

15
arch/x86/kernel/cpu/bugs.c
View file

@ -1317,19 +1317,21 @@ spectre_v2_user_select_mitigation(void)
} }
/* /*
* If no STIBP, enhanced IBRS is enabled, or SMT impossible, STIBP * If no STIBP, Intel enhanced IBRS is enabled, or SMT impossible, STIBP
* is not required. * is not required.
* *
* Enhanced IBRS also protects against cross-thread branch target * Intel's Enhanced IBRS also protects against cross-thread branch target
* injection in user-mode as the IBRS bit remains always set which * injection in user-mode as the IBRS bit remains always set which
* implicitly enables cross-thread protections. However, in legacy IBRS * implicitly enables cross-thread protections. However, in legacy IBRS
* mode, the IBRS bit is set only on kernel entry and cleared on return * mode, the IBRS bit is set only on kernel entry and cleared on return
* to userspace. This disables the implicit cross-thread protection, * to userspace. AMD Automatic IBRS also does not protect userspace.
* so allow for STIBP to be selected in that case. * These modes therefore disable the implicit cross-thread protection,
* so allow for STIBP to be selected in those cases.
*/ */
if (!boot_cpu_has(X86_FEATURE_STIBP) || if (!boot_cpu_has(X86_FEATURE_STIBP) ||
!smt_possible || !smt_possible ||
spectre_v2_in_eibrs_mode(spectre_v2_enabled)) (spectre_v2_in_eibrs_mode(spectre_v2_enabled) &&
!boot_cpu_has(X86_FEATURE_AUTOIBRS)))
return; return;
/* /*
@ -2596,7 +2598,8 @@ static ssize_t rfds_show_state(char *buf)
static char *stibp_state(void) static char *stibp_state(void)
{ {
if (spectre_v2_in_eibrs_mode(spectre_v2_enabled)) if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) &&
!boot_cpu_has(X86_FEATURE_AUTOIBRS))
return ""; return "";
switch (spectre_v2_user_stibp) { switch (spectre_v2_user_stibp) {