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dmaengine: ioat: use PCI core macros for PCIe Capability

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[ Upstream commit 8f6707d0773be31972768abd6e0bf7b8515b5b1a ]

The PCIe Capability is defined by the PCIe spec, so use the PCI_EXP_DEVCTL
macros defined by the PCI core instead of defining copies in IOAT.  This
makes it easier to find all uses of the PCIe Device Control register.  No
functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20230307214615.887354-1-helgaas@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Stable-dep-of: f0dc9fda2e0e ("dmaengine: ioatdma: Fix error path in ioat3_dma_probe()")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Bjorn Helgaas 2023-03-07 15:46:15 -06:00 • committed by Ksawlii
parent 770502584e
commit 86eb11cab3
2 changed files with 3 additions and 10 deletions
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6
drivers/dma/ioat/init.c
View file

@ -1190,13 +1190,13 @@ static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca)
ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base); ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base);
/* disable relaxed ordering */ /* disable relaxed ordering */
err = pcie_capability_read_word(pdev, IOAT_DEVCTRL_OFFSET, &val16); err = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &val16);
if (err) if (err)
return pcibios_err_to_errno(err); return pcibios_err_to_errno(err);
/* clear relaxed ordering enable */ /* clear relaxed ordering enable */
val16 &= ~IOAT_DEVCTRL_ROE; val16 &= ~PCI_EXP_DEVCTL_RELAX_EN;
err = pcie_capability_write_word(pdev, IOAT_DEVCTRL_OFFSET, val16); err = pcie_capability_write_word(pdev, PCI_EXP_DEVCTL, val16);
if (err) if (err)
return pcibios_err_to_errno(err); return pcibios_err_to_errno(err);

7
drivers/dma/ioat/registers.h
View file

@ -14,13 +14,6 @@
#define IOAT_PCI_CHANERR_INT_OFFSET 0x180 #define IOAT_PCI_CHANERR_INT_OFFSET 0x180
#define IOAT_PCI_CHANERRMASK_INT_OFFSET 0x184 #define IOAT_PCI_CHANERRMASK_INT_OFFSET 0x184
/* PCIe config registers */
/* EXPCAPID + N */
#define IOAT_DEVCTRL_OFFSET 0x8
/* relaxed ordering enable */
#define IOAT_DEVCTRL_ROE 0x10
/* MMIO Device Registers */ /* MMIO Device Registers */
#define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */ #define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */