ASoC: fsl_micfil: fix the naming style for mask definition
commit 101b096bc2549618f18bc08ae3a0e364b3c8fff1 upstream. Remove the _SHIFT for the mask definition. Fixes: 17f2142bae4b ("ASoC: fsl_micfil: use GENMASK to define register bit fields") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/1651736047-28809-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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1 changed files with 4 additions and 4 deletions
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@ -75,9 +75,9 @@
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#define MICFIL_FIFO_STAT_FIFOX_UNDER(ch) BIT((ch) + 8)
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/* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
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#define MICFIL_VAD0_CTRL1_CHSEL_SHIFT GENMASK(26, 24)
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#define MICFIL_VAD0_CTRL1_CICOSR_SHIFT GENMASK(19, 16)
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#define MICFIL_VAD0_CTRL1_INITT_SHIFT GENMASK(12, 8)
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#define MICFIL_VAD0_CTRL1_CHSEL GENMASK(26, 24)
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#define MICFIL_VAD0_CTRL1_CICOSR GENMASK(19, 16)
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#define MICFIL_VAD0_CTRL1_INITT GENMASK(12, 8)
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#define MICFIL_VAD0_CTRL1_ST10 BIT(4)
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#define MICFIL_VAD0_CTRL1_ERIE BIT(3)
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#define MICFIL_VAD0_CTRL1_IE BIT(2)
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@ -107,7 +107,7 @@
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/* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
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#define MICFIL_VAD0_ZCD_ZCDTH GENMASK(25, 16)
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#define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT GENMASK(11, 8)
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#define MICFIL_VAD0_ZCD_ZCDADJ GENMASK(11, 8)
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#define MICFIL_VAD0_ZCD_ZCDAND BIT(4)
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#define MICFIL_VAD0_ZCD_ZCDAUT BIT(2)
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#define MICFIL_VAD0_ZCD_ZCDEN BIT(0)
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