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ixgbe: Remove non-inclusive language

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[ Upstream commit 93b067f154b3edfd3d75a272fd9433bf787e2e1d ]

Remove non-inclusive language from the driver.

Additionally correct the duplication "from from"
reported by checkpatch after the changes above.

Signed-off-by: Piotr Skajewski <piotrx.skajewski@intel.com>
Tested-by: Dave Switzer <david.switzer@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Stable-dep-of: bbc404d20d1b ("ixgbe: Fix an error handling path in ixgbe_read_iosf_sb_reg_x550()")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Piotr Skajewski 2022-01-11 11:27:23 +01:00 • committed by Ksawlii
parent 25902fec2b
commit 6d35af2263
3 changed files with 25 additions and 25 deletions
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36
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
View file

@ -30,7 +30,7 @@ static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
u16 words, u16 *data); u16 words, u16 *data);
static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
u16 offset); u16 offset);
static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw); static s32 ixgbe_disable_pcie_primary(struct ixgbe_hw *hw);
/* Base table for registers values that change by MAC */ /* Base table for registers values that change by MAC */
const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = { const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = {
@ -745,10 +745,10 @@ s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
usleep_range(1000, 2000); usleep_range(1000, 2000);
/* /*
* Prevent the PCI-E bus from from hanging by disabling PCI-E master * Prevent the PCI-E bus from hanging by disabling PCI-E primary
* access and verify no pending requests * access and verify no pending requests
*/ */
return ixgbe_disable_pcie_master(hw); return ixgbe_disable_pcie_primary(hw);
} }
/** /**
@ -2505,15 +2505,15 @@ static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
} }
/** /**
* ixgbe_disable_pcie_master - Disable PCI-express master access * ixgbe_disable_pcie_primary - Disable PCI-express primary access
* @hw: pointer to hardware structure * @hw: pointer to hardware structure
* *
* Disables PCI-Express master access and verifies there are no pending * Disables PCI-Express primary access and verifies there are no pending
* requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable * requests. IXGBE_ERR_PRIMARY_REQUESTS_PENDING is returned if primary disable
* bit hasn't caused the master requests to be disabled, else 0 * bit hasn't caused the primary requests to be disabled, else 0
* is returned signifying master requests disabled. * is returned signifying primary requests disabled.
**/ **/
static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) static s32 ixgbe_disable_pcie_primary(struct ixgbe_hw *hw)
{ {
u32 i, poll; u32 i, poll;
u16 value; u16 value;
@ -2522,23 +2522,23 @@ static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
/* Poll for bit to read as set */ /* Poll for bit to read as set */
for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { for (i = 0; i < IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT; i++) {
if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS) if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS)
break; break;
usleep_range(100, 120); usleep_range(100, 120);
} }
if (i >= IXGBE_PCI_MASTER_DISABLE_TIMEOUT) { if (i >= IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT) {
hw_dbg(hw, "GIO disable did not set - requesting resets\n"); hw_dbg(hw, "GIO disable did not set - requesting resets\n");
goto gio_disable_fail; goto gio_disable_fail;
} }
/* Exit if master requests are blocked */ /* Exit if primary requests are blocked */
if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
ixgbe_removed(hw->hw_addr)) ixgbe_removed(hw->hw_addr))
return 0; return 0;
/* Poll for master request bit to clear */ /* Poll for primary request bit to clear */
for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { for (i = 0; i < IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT; i++) {
udelay(100); udelay(100);
if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
return 0; return 0;
@ -2546,13 +2546,13 @@ static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
/* /*
* Two consecutive resets are required via CTRL.RST per datasheet * Two consecutive resets are required via CTRL.RST per datasheet
* 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine * 5.2.5.3.2 Primary Disable. We set a flag to inform the reset routine
* of this need. The first reset prevents new master requests from * of this need. The first reset prevents new primary requests from
* being issued by our device. We then must wait 1usec or more for any * being issued by our device. We then must wait 1usec or more for any
* remaining completions from the PCIe bus to trickle in, and then reset * remaining completions from the PCIe bus to trickle in, and then reset
* again to clear out any effects they may have had on our device. * again to clear out any effects they may have had on our device.
*/ */
hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n"); hw_dbg(hw, "GIO Primary Disable bit didn't clear - requesting resets\n");
gio_disable_fail: gio_disable_fail:
hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
@ -2574,7 +2574,7 @@ gio_disable_fail:
} }
hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n"); hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
return IXGBE_ERR_MASTER_REQUESTS_PENDING; return IXGBE_ERR_PRIMARY_REQUESTS_PENDING;
} }
/** /**

4
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
View file

@ -5949,8 +5949,8 @@ void ixgbe_reset(struct ixgbe_adapter *adapter)
case IXGBE_ERR_SFP_NOT_PRESENT: case IXGBE_ERR_SFP_NOT_PRESENT:
case IXGBE_ERR_SFP_NOT_SUPPORTED: case IXGBE_ERR_SFP_NOT_SUPPORTED:
break; break;
case IXGBE_ERR_MASTER_REQUESTS_PENDING: case IXGBE_ERR_PRIMARY_REQUESTS_PENDING:
e_dev_err("master disable timed out\n"); e_dev_err("primary disable timed out\n");
break; break;
case IXGBE_ERR_EEPROM_VERSION: case IXGBE_ERR_EEPROM_VERSION:
/* We are running on a pre-production device, log a warning */ /* We are running on a pre-production device, log a warning */

10
drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
View file

@ -1247,7 +1247,7 @@ struct ixgbe_nvm_version {
#define IXGBE_PSRTYPE_RQPL_SHIFT 29 #define IXGBE_PSRTYPE_RQPL_SHIFT 29
/* CTRL Bit Masks */ /* CTRL Bit Masks */
#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */ #define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Primary Disable bit */
#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */ #define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
#define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST) #define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
@ -1810,7 +1810,7 @@ enum {
/* STATUS Bit Masks */ /* STATUS Bit Masks */
#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/ #define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */ #define IXGBE_STATUS_GIO 0x00080000 /* GIO Primary Enable Status */
#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ #define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ #define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
@ -2192,8 +2192,8 @@ enum {
#define IXGBE_PCIDEVCTRL2_4_8s 0xd #define IXGBE_PCIDEVCTRL2_4_8s 0xd
#define IXGBE_PCIDEVCTRL2_17_34s 0xe #define IXGBE_PCIDEVCTRL2_17_34s 0xe
/* Number of 100 microseconds we wait for PCI Express master disable */ /* Number of 100 microseconds we wait for PCI Express primary disable */
#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 #define IXGBE_PCI_PRIMARY_DISABLE_TIMEOUT 800
/* RAH */ /* RAH */
#define IXGBE_RAH_VIND_MASK 0x003C0000 #define IXGBE_RAH_VIND_MASK 0x003C0000
@ -3674,7 +3674,7 @@ struct ixgbe_info {
#define IXGBE_ERR_ADAPTER_STOPPED -9 #define IXGBE_ERR_ADAPTER_STOPPED -9
#define IXGBE_ERR_INVALID_MAC_ADDR -10 #define IXGBE_ERR_INVALID_MAC_ADDR -10
#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12 #define IXGBE_ERR_PRIMARY_REQUESTS_PENDING -12
#define IXGBE_ERR_INVALID_LINK_SETTINGS -13 #define IXGBE_ERR_INVALID_LINK_SETTINGS -13
#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
#define IXGBE_ERR_RESET_FAILED -15 #define IXGBE_ERR_RESET_FAILED -15