From 57c42b3af7d8122efe572999b0b338fdcd682fdb Mon Sep 17 00:00:00 2001 From: Ksawlii Date: Sun, 24 Nov 2024 00:22:51 +0100 Subject: [PATCH] Revert "x86/apic: Always explicitly disarm TSC-deadline timer" This reverts commit 5a5d98e292f32bce93067ed83fb0c00a28f28803. --- arch/x86/kernel/apic/apic.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 3a3878817..25eb69f26 100755 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -491,19 +491,7 @@ static int lapic_timer_shutdown(struct clock_event_device *evt) v = apic_read(APIC_LVTT); v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); apic_write(APIC_LVTT, v); - - /* - * Setting APIC_LVT_MASKED (above) should be enough to tell - * the hardware that this timer will never fire. But AMD - * erratum 411 and some Intel CPU behavior circa 2024 say - * otherwise. Time for belt and suspenders programming: mask - * the timer _and_ zero the counter registers: - */ - if (v & APIC_LVT_TIMER_TSCDEADLINE) - wrmsrl(MSR_IA32_TSC_DEADLINE, 0); - else - apic_write(APIC_TMICT, 0); - + apic_write(APIC_TMICT, 0); return 0; }