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gpu: exynos: don't read dvfs table from dtb

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-> Hardcode in kernel module
-> Unlock all frequencies up to 1.2GHz

Signed-off-by: Gabriel2392 <gabriel824m@gmail.com>
This commit is contained in:
Gabriel2392 2023-07-17 23:29:24 +00:00
parent a839ab2b13
commit 2de2633674
6 changed files with 53 additions and 53 deletions
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2
drivers/gpu/arm/bv_r32p1/mali_kbase_config_defaults.h
View file

@ -194,7 +194,7 @@ enum {
* is enabled the value will be read from there, otherwise this should be
* overridden by defining GPU_FREQ_KHZ_MAX in the platform file.
*/
#define DEFAULT_GPU_FREQ_KHZ_MAX (5000)
#define DEFAULT_GPU_FREQ_KHZ_MAX (1209000)
/**
* Default timeout for task execution on an endpoint

2
drivers/gpu/arm/bv_r38p1/mali_kbase_config_defaults.h
View file

@ -238,7 +238,7 @@ enum {
* is enabled the value will be read from there, otherwise this should be
* overridden by defining GPU_FREQ_KHZ_MAX in the platform file.
*/
#define DEFAULT_GPU_FREQ_KHZ_MAX (5000)
#define DEFAULT_GPU_FREQ_KHZ_MAX (1209000)
/* Default timeout for task execution on an endpoint
*

86
drivers/gpu/arm/exynos/backend/gpexbe_devicetree.c
View file

@ -106,70 +106,57 @@ static int read_interactive_info_array(void)
return 0;
}
unsigned int custom_clock[] = {1209000, 1105000, 1001000, 897000, 806000, 702000, 611000, 507000, 403000, 312000, 208000, 104000};
unsigned int custom_min_threshold[] = {90, 87, 85, 82, 80, 79, 78, 70, 60, 50, 30, 0};
unsigned int custom_max_threshold[] = {100, 96 ,95, 95, 95, 95, 95, 90, 80, 70, 60, 40};
unsigned int custom_staycount[] = {5, 5, 5, 5, 5, 5, 5, 3, 3, 2, 2, 1};
unsigned int custom_mem_freq[] = {1794000, 1794000, 1794000, 1794000, 1539000, 1352000, 1352000, 1014000, 1014000, 845000, 676000, 676000};
unsigned int custom_lit[] = {1536000, 1440000, 1248000, 1056000, 1056000, 1056000, 1056000, 1056000, 0, 0, 0, 0};
unsigned int custom_mid = 0;
unsigned int custom_big = CPU_MAX;
int custom_array_size = sizeof(custom_clock) / sizeof(custom_clock[0]);
static int build_clk_table(void)
{
int array_size = dt_info.gpu_dvfs_table_size.row * dt_info.gpu_dvfs_table_size.col;
u32 *raw_table;
int row = 0;
int array_size = custom_array_size;
int i = 0;
if (array_size <= 0) {
/* TODO: print error message */
return -EINVAL;
}
clock_table = kcalloc(array_size, sizeof(*clock_table), GFP_KERNEL);
raw_table = kcalloc(array_size, sizeof(*raw_table), GFP_KERNEL);
if (!raw_table)
return -ENOMEM;
gpexbe_devicetree_read_u32_array("gpu_dvfs_table", raw_table, array_size);
clock_table = kcalloc(dt_info.gpu_dvfs_table_size.row, sizeof(*clock_table), GFP_KERNEL);
for (row = 0; row < dt_info.gpu_dvfs_table_size.row; row++) {
int table_idx = row * dt_info.gpu_dvfs_table_size.col;
clock_table[row].clock = raw_table[table_idx];
clock_table[row].min_threshold = raw_table[table_idx + 1];
clock_table[row].max_threshold = raw_table[table_idx + 2];
clock_table[row].down_staycount = raw_table[table_idx + 3];
clock_table[row].mem_freq = raw_table[table_idx + 4];
clock_table[row].cpu_little_min_freq = raw_table[table_idx + 5];
for (i = 0; i < array_size; i++) {
clock_table[i].clock = custom_clock[i];
clock_table[i].min_threshold = custom_min_threshold[i];
clock_table[i].max_threshold = custom_max_threshold[i];
clock_table[i].down_staycount = custom_staycount[i];
clock_table[i].mem_freq = custom_mem_freq[i];
clock_table[i].cpu_little_min_freq = custom_lit[i];
if (dt_info.gpu_pmqos_cpu_cluster_num == 3) {
clock_table[row].cpu_middle_min_freq = raw_table[table_idx + 6];
clock_table[row].cpu_big_max_freq =
(raw_table[table_idx + 7] ? raw_table[table_idx + 7] : CPU_MAX);
clock_table[i].cpu_middle_min_freq = custom_mid;
clock_table[i].cpu_big_max_freq = custom_big;
GPU_LOG(MALI_EXYNOS_INFO,
"up [%d] down [%d] staycnt [%d] mif [%d] lit [%d] mid [%d] big [%d]\n",
clock_table[row].max_threshold, clock_table[row].min_threshold,
clock_table[row].down_staycount, clock_table[row].mem_freq,
clock_table[row].cpu_little_min_freq,
clock_table[row].cpu_middle_min_freq,
clock_table[row].cpu_big_max_freq);
clock_table[i].max_threshold, clock_table[i].min_threshold,
clock_table[i].down_staycount, clock_table[i].mem_freq,
clock_table[i].cpu_little_min_freq,
clock_table[i].cpu_middle_min_freq,
clock_table[i].cpu_big_max_freq);
} else {
// Assuming cpu cluster number is 2
clock_table[row].cpu_big_max_freq =
(raw_table[table_idx + 6] ? raw_table[table_idx + 6] : CPU_MAX);
clock_table[i].cpu_big_max_freq = custom_big;
GPU_LOG(MALI_EXYNOS_INFO,
"up [%d] down [%d] staycnt [%d] mif [%d] lit [%d] big [%d]\n",
clock_table[row].max_threshold, clock_table[row].min_threshold,
clock_table[row].down_staycount, clock_table[row].mem_freq,
clock_table[row].cpu_little_min_freq,
clock_table[row].cpu_big_max_freq);
clock_table[i].max_threshold, clock_table[i].min_threshold,
clock_table[i].down_staycount, clock_table[i].mem_freq,
clock_table[i].cpu_little_min_freq,
clock_table[i].cpu_big_max_freq);
}
#if IS_ENABLED(CONFIG_SOC_EXYNOS2100)
clock_table[row].llc_ways = raw_table[table_idx + 8];
#endif
}
// GPU_LOG(MALI_EXYNOS_WARNING, "G3D %7dKhz ASV is %duV\n", cal_freq, cal_vol);
kfree(raw_table);
return 0;
}
@ -227,12 +214,13 @@ static void read_from_dt(void)
gpexbe_devicetree_read_string("g3d_genpd_name", &dt_info.g3d_genpd_name);
/* CLOCK */
gpexbe_devicetree_read_u32("gpu_max_clock", &dt_info.gpu_max_clock);
gpexbe_devicetree_read_u32("gpu_min_clock", &dt_info.gpu_min_clock);
dt_info.gpu_max_clock = custom_clock[0];
dt_info.gpu_min_clock = custom_clock[custom_array_size - 1];
gpexbe_devicetree_read_u32("gpu_pmqos_cpu_cluster_num", &dt_info.gpu_pmqos_cpu_cluster_num);
gpexbe_devicetree_read_u32_array("gpu_dvfs_table_size", (int *)&dt_info.gpu_dvfs_table_size,
2);
dt_info.gpu_dvfs_table_size.col = 8; // 8 values for each freq
dt_info.gpu_dvfs_table_size.row = custom_array_size;
gpexbe_devicetree_read_u32_array("gpu_cl_pmqos_table_size",
(int *)&dt_info.gpu_cl_pmqos_table_size, 2);

5
drivers/gpu/arm/exynos/frontend/gpex_clock.c
View file

@ -34,6 +34,7 @@
#include "gpex_clock_internal.h"
#define CPU_MAX INT_MAX
#define GPU_CUSTOM_MAX_CLOCK (1209000)
static struct _clock_info clk_info;
@ -83,10 +84,10 @@ static int gpex_clock_update_config_data_from_dt(void)
int asv_lv_num;
int i, j;
clk_info.gpu_max_clock = gpexbe_devicetree_get_int(gpu_max_clock);
clk_info.gpu_max_clock = GPU_CUSTOM_MAX_CLOCK;
clk_info.gpu_min_clock = gpexbe_devicetree_get_int(gpu_min_clock);
clk_info.boot_clock = gpexbe_clock_get_boot_freq();
clk_info.gpu_max_clock_limit = gpexbe_clock_get_max_freq();
clk_info.gpu_max_clock_limit = GPU_CUSTOM_MAX_CLOCK;
/* TODO: rename the table_size variable to something more sensible like row_cnt */
clk_info.table_size = gpexbe_devicetree_get_int(gpu_dvfs_table_size.row);

5
drivers/soc/samsung/ect_parser/ect_parser.c
View file

@ -18,6 +18,8 @@
#define ARRAY_SIZE32(array) ((u32)ARRAY_SIZE(array))
#define GPU_CUSTOM_MAX_CLOCK (1209000)
/* Variable */
static struct ect_info ect_list[];
@ -557,6 +559,9 @@ static int ect_parse_ap_thermal_function(int parser_version, void *address, stru
ect_parse_integer(&address, &range->lower_bound_temperature);
ect_parse_integer(&address, &range->upper_bound_temperature);
ect_parse_integer(&address, &range->max_frequency);
if (range->max_frequency == 897000) {
range->max_frequency = GPU_CUSTOM_MAX_CLOCK;
}
ect_parse_integer(&address, &range->sw_trip);
ect_parse_integer(&address, &range->flag);
}

6
drivers/thermal/samsung/gpu_cooling.c
View file

@ -34,6 +34,8 @@
#include "exynos_tmu.h"
#include "../thermal_core.h"
#define GPU_CUSTOM_MAX_CLOCK (1209000)
/**
* struct power_table - frequency to power conversion
* @frequency: frequency in KHz
@ -733,6 +735,10 @@ static struct thermal_zone_device* parse_ect_cooling_level(struct thermal_coolin
unsigned long max_level = 0;
int level;
if (function->range_list[i].max_frequency == 897000) {
function->range_list[i].max_frequency = GPU_CUSTOM_MAX_CLOCK;
}
temperature = function->range_list[i].lower_bound_temperature;
freq = function->range_list[i].max_frequency;