240 lines
6.2 KiB
C
240 lines
6.2 KiB
C
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#ifndef _UFS_EXYNOS_FMP_H_
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#define _UFS_EXYNOS_FMP_H_
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#define FMP_DRV_VERSION "4.0.0"
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/* FMP IDs (second or third parameter to FMP/SMU Ctrls) */
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#define FMP_EMBEDDED 0
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#define FMP_UFSCARD 1
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#define FMP_SDCARD 2
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/* SMU commands (second parameter to SMC_CMD_SMU) */
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#define SMU_INIT 0
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#define SMU_SET 1
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#define SMU_ABORT 2
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/* Fourth parameter to SMC_CMD_FMP_SECURITY */
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#define CFG_DESCTYPE_0 0
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#define CFG_DESCTYPE_3 3
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/* Fourth parameter to SMC_CMD_FMP_KW_MODE */
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#define WAP0_NS (1 << 8)
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#define UNWRAP_EN (0 << 4)
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#define UNWRAP_BYPASS (1 << 4)
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#define SWKEY_MODE 0
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#define SECUREKEY_MODE 1
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/* Fourth parameter to SMC_CMD_FMP_KW_INDATASWAP */
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#define RAW_FILEKEY_WORDSWAP (1 << 22)
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#define RAW_TWEAKKEY_WORDSWAP (1 << 21)
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#define PBK_WORDSWAP (1 << 20)
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#define IV_WORDSWAP (1 << 19)
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#define TAG_WORDSWAP (1 << 18)
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#define SECURE_FILEKEY_WORDSWAP (1 << 17)
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#define SECURE_TWEAKKEY_WORDSWAP (1 << 16)
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#define RAW_FILEKEY_BYTESWAP (1 << 6)
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#define RAW_TWEAKKEY_BYTESWAP (1 << 5)
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#define PBK_BYTESWAP (1 << 4)
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#define IV_BYTESWAP (1 << 3)
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#define TAG_BYTESWAP (1 << 2)
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#define SECURE_FILEKEY_BYTESWAP (1 << 1)
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#define SECURE_TWEAKKEY_BYTESWAP (1 << 0)
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/* Advertise crypto quirks to ufshcd-core. */
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#ifdef CONFIG_KEYS_IN_PRDT
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#define UFSHCD_QUIRK_FMP_MODE_SPECIFIC UFSHCD_QUIRK_CUSTOM_KEYSLOT_MANAGER |\
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UFSHCD_QUIRK_KEYS_IN_PRDT
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#endif
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#ifdef CONFIG_HW_KEYS_IN_CUSTOM_KEYSLOT
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#define UFSHCD_QUIRK_FMP_MODE_SPECIFIC UFSHCD_QUIRK_CUSTOM_KEYSLOT_MANAGER
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#endif
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#ifdef CONFIG_KEYS_IN_CUSTOM_KEYSLOT
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#define UFSHCD_QUIRK_FMP_MODE_SPECIFIC UFSHCD_QUIRK_CUSTOM_KEYSLOT_MANAGER
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#endif
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#ifdef CONFIG_SOC_EXYNOS2100
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#define UFSHCD_QUIRK_FMP_SOC_SPECIFIC UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE
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#else
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#define UFSHCD_QUIRK_FMP_SOC_SPECIFIC 0
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#endif
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enum fmp_crypto_algo_mode {
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FMP_BYPASS_MODE = 0,
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FMP_ALGO_MODE_AES_CBC = 1,
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FMP_ALGO_MODE_AES_XTS = 2,
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};
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#define FMP_DATA_UNIT_SIZE 4096
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struct fmp_sg_entry {
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/* The first four fields correspond to those of ufshcd_sg_entry. */
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__le32 des0;
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__le32 des1;
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__le32 des2;
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/*
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* The algorithm and key length are configured in the high bits of des3,
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* whose low bits already contain ufshcd_sg_entry::size.
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*/
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__le32 des3;
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#define FKL (1 << 26)
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#define SET_KEYLEN(ent, v) ((ent)->des3 |= cpu_to_le32(v))
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#define SET_FAS(ent, v) ((ent)->des3 |= cpu_to_le32((v) << 28))
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/* The IV with all bytes reversed */
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__be32 file_iv[4];
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/*
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* The key with all bytes reversed. For XTS, the two halves of the key
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* are given separately and are byte-reversed separately.
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*/
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__be32 file_enckey[8];
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__be32 file_twkey[8];
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/* Not used */
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__be32 disk_iv[4];
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__le32 reserved[4];
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};
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/* Number of custom keyslots */
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/* 0-14 keylots: keyslot for crypto io, 15: reserved keyslot for FIPS */
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#define UFS_KEYSLOTS 16
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#ifdef CONFIG_EXYNOS_FMP_FIPS
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#define FIPS_KEYSLOT 1
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#else
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#define FIPS_KEYSLOT 0
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#endif
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#define NUM_KEYSLOTS (UFS_KEYSLOTS - FIPS_KEYSLOT)
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#define AES_256_XTS_KEY_SIZE 64
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#define SECRET_SIZE 32
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#define AES_GCM_TAG_SIZE 16
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#define AES_256_XTS_TWK_OFFSET 8
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#define HW_WRAPPED_KEY_TAG_OFFSET 16
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#define HW_WRAPPED_KEY_SECRET_OFFSET 80
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/* UFSHCD register map */
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#define CRYPTOCFG 0x0440
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/* 0-CRYPTOCFG - CFGE_CAPIDX_DUSIZE */
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union exynos_ufs_crypto_cfg_entry {
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__le32 reg_val;
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struct {
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u8 data_unit_size;
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u8 crypto_cap_idx;
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u8 reserved_1;
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u8 config_enable;
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};
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};
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struct exynos_fmp {
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u8 valid_check;
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};
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/* FMP register map */
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#define FMP_REGS 38
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#define UFSPRCTRL 0x000
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#define UFSPRSTAT0 0x008
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#define UFSPRSTAT1 0x00C
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#define UFSPRSECURITY0 0x010
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#define UFSPWCTRL 0x100
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#define UFSPWSTAT0 0x108
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#define UFSPWSTAT1 0x10C
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#define UFSPSBEGIN0 0x2000
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#define UFSPSEND0 0x2004
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#define UFSPSLUN0 0x2008
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#define UFSPSCTRL0 0x200C
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#define UFSPSBEGIN1 0x2010
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#define UFSPSEND1 0x2014
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#define UFSPSLUN1 0x2018
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#define UFSPSCTRL1 0x201C
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#define UFSPSBEGIN2 0x2020
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#define UFSPSEND2 0x2024
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#define UFSPSLUN2 0x2028
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#define UFSPSCTRL2 0x202C
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#define UFSPSBEGIN3 0x2030
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#define UFSPSEND3 0x2034
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#define UFSPSLUN3 0x2038
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#define UFSPSCTRL3 0x203C
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#define UFSPSBEGIN4 0x2040
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#define UFSPSEND4 0x2044
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#define UFSPSLUN4 0x2048
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#define UFSPSCTRL4 0x204C
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#define UFSPSBEGIN5 0x2050
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#define UFSPSEND5 0x2054
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#define UFSPSLUN5 0x2058
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#define UFSPSCTRL5 0x205C
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#define UFSPSBEGIN6 0x2060
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#define UFSPSEND6 0x2064
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#define UFSPSLUN6 0x2068
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#define UFSPSCTRL6 0x206C
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#define UFSPSBEGIN7 0x2070
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#define UFSPSEND7 0x2074
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#define UFSPSLUN7 0x2078
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#define UFSPSCTRL7 0x207C
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#define FMP_KW_SECUREKEY 0x8000
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#define FMP_KW_TAG 0x8040
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#define FMP_KW_CONTROL 0xA008
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#define FMP_KW_KEYVALID 0xA00C
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#define FMP_KW_TAGABORT 0xA010
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#define FMP_KW_PBKABORT 0xA014
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#define FMP_KW_SECUREKEY_OFFSET 0x80
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#define FMP_KW_TAG_OFFSET 0x80
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#define EXYNOS_FMP_FIPS_KEYSLOT 0xF
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/* Definition to dump fmp registers */
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struct exynos_ufs_fmp_sfr_log {
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const char name[15];
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const u32 offset;
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u64 val;
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};
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static struct exynos_ufs_fmp_sfr_log ufs_fmp_log_sfr[FMP_REGS] = {
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{"UFSPRCTRL", UFSPRCTRL},
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{"UFSPRSTAT0", UFSPRSTAT0},
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{"UFSPRSTAT1", UFSPRSTAT1},
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{"UFSPRSECURITY0", UFSPRSECURITY0},
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{"UFSPWCTRL", UFSPWCTRL},
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{"UFSPWSTAT0", UFSPWSTAT0},
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{"UFSPWSTAT1", UFSPWSTAT1},
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{"UFSPSBEGIN0", UFSPSBEGIN0},
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{"UFSPSEND0", UFSPSEND0},
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{"UFSPSLUN0", UFSPSLUN0},
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{"UFSPSCTRL0", UFSPSCTRL0},
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{"UFSPSBEGIN1", UFSPSBEGIN1},
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{"UFSPSEND1", UFSPSEND1},
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{"UFSPSLUN1", UFSPSLUN1},
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{"UFSPSCTRL1", UFSPSCTRL1},
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{"UFSPSBEGIN2", UFSPSBEGIN2},
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{"UFSPSEND2", UFSPSEND2},
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{"UFSPSLUN2", UFSPSLUN2},
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{"UFSPSCTRL2", UFSPSCTRL2},
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{"UFSPSBEGIN3", UFSPSBEGIN3},
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{"UFSPSEND3", UFSPSEND3},
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{"UFSPSLUN3", UFSPSLUN3},
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{"UFSPSCTRL3", UFSPSCTRL3},
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{"UFSPSBEGIN4", UFSPSBEGIN4},
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{"UFSPSLUN4", UFSPSLUN4},
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{"UFSPSCTRL4", UFSPSCTRL4},
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{"UFSPSBEGIN5", UFSPSBEGIN5},
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{"UFSPSEND5", UFSPSEND5},
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{"UFSPSLUN5", UFSPSLUN5},
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{"UFSPSCTRL5", UFSPSCTRL5},
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{"UFSPSBEGIN6", UFSPSBEGIN6},
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{"UFSPSEND6", UFSPSEND6},
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{"UFSPSLUN6", UFSPSLUN6},
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{"UFSPSCTRL6", UFSPSCTRL6},
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{"UFSPSBEGIN7", UFSPSBEGIN7},
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{"UFSPSEND7", UFSPSEND7},
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{"UFSPSLUN7", UFSPSLUN7},
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{"UFSPSCTRL7", UFSPSCTRL7},
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};
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#endif /* _UFS_EXYNOS_FMP_H_ */
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