461 lines
12 KiB
C
461 lines
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/io.h>
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#include <linux/cpumask.h>
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#include <linux/suspend.h>
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#include <linux/notifier.h>
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#include <linux/bug.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <soc/samsung/exynos-smc.h>
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#include <soc/samsung/cal-if.h>
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#if IS_ENABLED(CONFIG_EXYNOS_PMU_IF)
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#include <soc/samsung/exynos-pmu-if.h>
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#else
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#include <soc/samsung/exynos-pmu.h>
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#endif
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#include "../cal-if/acpm_dvfs.h"
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#include "pmu-gnss.h"
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#include "gnss_prj.h"
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/* Connectivity sub system */
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#define EXYNOS_GNSS (0)
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/* Target to set */
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#define EXYNOS_SET_CONN_TZPC (0)
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#define gnss_pmu_read exynos_pmu_read
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#define gnss_pmu_write exynos_pmu_write
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#define gnss_pmu_update exynos_pmu_update
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#if IS_ENABLED(CONFIG_SOC_EXYNOS9630)
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#define BAAW_GNSS_CMGP_ADDR (0x13FE0000)
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#define BAAW_GNSS_CMGP_SIZE (SZ_64K)
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#define BAAW_GNSS_DBUS_ADDR (0x13FD0000)
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#define BAAW_GNSS_DBUS_SIZE (SZ_64K)
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#define CMUPMU_ADDR (0x13E43000)
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#elif IS_ENABLED(CONFIG_SOC_EXYNOS3830)
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#define BAAW_GNSS_CMGP_ADDR (0x13FE0000)
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#define BAAW_GNSS_CMGP_SIZE (SZ_64K)
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#define BAAW_GNSS_DBUS_ADDR (0x13FD0000)
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#define BAAW_GNSS_DBUS_SIZE (SZ_64K)
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#define CMUPMU_ADDR (0x13E43000)
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#elif IS_ENABLED(CONFIG_SOC_S5E9815)
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#define BAAW_GNSS_CMGP_ADDR (0x159E0000)
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#define BAAW_GNSS_CMGP_SIZE (SZ_64K)
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#define BAAW_GNSS_DBUS_ADDR (0x159D0000)
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#define BAAW_GNSS_DBUS_SIZE (SZ_64K)
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#elif IS_ENABLED(CONFIG_SOC_S5E9925)
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#define BAAW_GNSS_CMGP_ADDR (0x147E0000)
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#define BAAW_GNSS_CMGP_SIZE (SZ_64K)
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/* Set OFFSET only. ADDR and SIZE are the same with CMGP values. */
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#define BAAW_GNSS_DBUS_OFFSET (0x20)
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#elif IS_ENABLED(CONFIG_SOC_S5E8825)
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#define BAAW_GNSS_CMGP_ADDR (0x13FE0000)
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#define BAAW_GNSS_CMGP_SIZE (SZ_64K)
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#define BAAW_GNSS_DBUS_ADDR (0x13FD0000)
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#define BAAW_GNSS_DBUS_SIZE (SZ_64K)
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#define SYSREG_ALIVE_ADDR (0x11820000)
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#define LPP_RA1_HD_ADME_OFFSET (0x00000314)
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static void __iomem *sysreg_alive_reg;
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#endif
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static u32 g_shmem_size;
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static u64 g_shmem_base;
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static u32 g_base_addr;
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static u32 g_base_addr_2nd;
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static void __iomem *baaw_cmgp_reg;
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static void __iomem *baaw_dbus_reg;
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static unsigned int baaw_dbus_offset;
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int gnss_cmgp_read(unsigned int reg_offset, unsigned int *ret)
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{
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if (baaw_cmgp_reg == NULL)
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return -EIO;
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*ret = __raw_readl(baaw_cmgp_reg + reg_offset);
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return 0;
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}
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int gnss_cmgp_write(unsigned int reg_offset, unsigned int val)
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{
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unsigned int read_val = 0;
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if (baaw_cmgp_reg == NULL)
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return -EIO;
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__raw_writel(val, baaw_cmgp_reg + reg_offset);
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read_val = __raw_readl(baaw_cmgp_reg + reg_offset);
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if (val != read_val)
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gif_err("ADDR:0x%08X DATA:0x%08X => Read to verify:0x%08X\n",
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BAAW_GNSS_CMGP_ADDR + reg_offset, val,
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__raw_readl(baaw_cmgp_reg + reg_offset));
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return 0;
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}
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int gnss_dbus_read(unsigned int reg_offset, unsigned int *ret)
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{
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unsigned int offset = baaw_dbus_offset + reg_offset;
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if (baaw_dbus_reg == NULL)
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return -EIO;
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*ret = __raw_readl(baaw_dbus_reg + offset);
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return 0;
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}
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int gnss_dbus_write(unsigned int reg_offset, unsigned int val)
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{
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unsigned int offset = baaw_dbus_offset + reg_offset;
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unsigned int read_val = 0;
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if (baaw_dbus_reg == NULL)
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return -EIO;
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__raw_writel(val, baaw_dbus_reg + offset);
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read_val = __raw_readl(baaw_dbus_reg + offset);
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if (val != read_val) {
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gif_err("DATA:0x%08X => Read to verify:0x%08X\n",
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val, __raw_readl(baaw_dbus_reg + offset));
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}
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return 0;
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}
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static int gnss_pmu_clear_interrupt(enum gnss_int_clear gnss_int)
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{
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switch (gnss_int) {
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case GNSS_INT_WAKEUP_CLEAR:
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break;
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case GNSS_INT_ACTIVE_CLEAR:
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cal_gnss_active_clear();
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break;
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case GNSS_INT_WDT_RESET_CLEAR:
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break;
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default:
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gif_err("Unexpected interrupt value!\n");
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return -EIO;
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}
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return 0;
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}
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#if IS_ENABLED(CONFIG_SOC_EXYNOS9630) || IS_ENABLED(CONFIG_SOC_EXYNOS3830)
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static void gnss_get_swreg(struct gnss_swreg *swreg)
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{
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exynos_smc_readsfr(CMUPMU_ADDR, (unsigned long *)&swreg->swreg_0);
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exynos_smc_readsfr(CMUPMU_ADDR + 0x4, (unsigned long *)&swreg->swreg_1);
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exynos_smc_readsfr(CMUPMU_ADDR + 0x8, (unsigned long *)&swreg->swreg_2);
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exynos_smc_readsfr(CMUPMU_ADDR + 0xC, (unsigned long *)&swreg->swreg_3);
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exynos_smc_readsfr(CMUPMU_ADDR + 0x10, (unsigned long *)&swreg->swreg_4);
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exynos_smc_readsfr(CMUPMU_ADDR + 0x14, (unsigned long *)&swreg->swreg_5);
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gif_info("SWREG 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
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swreg->swreg_0, swreg->swreg_1, swreg->swreg_2,
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swreg->swreg_3, swreg->swreg_4, swreg->swreg_5);
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}
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#endif
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static void gnss_get_apreg(struct gnss_apreg *apreg)
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{
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gnss_pmu_read(EXYNOS_PMU_GNSS_CTRL_NS, &apreg->CTRL_NS);
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gnss_pmu_read(EXYNOS_PMU_GNSS_CTRL_S, &apreg->CTRL_S);
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gnss_pmu_read(EXYNOS_PMU_GNSS_STAT, &apreg->STAT);
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gnss_pmu_read(EXYNOS_PMU_GNSS_DEBUG, &apreg->DEBUG);
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gif_info("APREG CTRL_NS 0x%08X CTRL_S 0x%08X STAT 0x%08X DEBUG 0x%08X\n",
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apreg->CTRL_NS, apreg->CTRL_S, apreg->STAT, apreg->DEBUG);
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}
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#if IS_ENABLED(CONFIG_SOC_EXYNOS9630)
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static void __iomem *intr_bid_pend; /* check APM pending before release reset */
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static bool check_apm_int_pending(void)
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{
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bool ret = false;
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int reg_val = 0;
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int count = 20; /* 50ms * 20 times = 1 sec */
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if (intr_bid_pend == NULL) {
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intr_bid_pend = ioremap(0x10E71A04, SZ_4);
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if (intr_bid_pend == NULL) {
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gif_err("Err: failed to ioremap GRP26_INTR_BID_PEND!\n");
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return ret;
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}
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}
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while (count > 0) {
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reg_val = __raw_readl(intr_bid_pend);
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gif_info("APM PENDING CHECK REGISTER VAL: 0x%08x\n", reg_val);
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if ((reg_val >> 17) & 0x3F) {/* check if one or more of bits [22:17] are 1 */
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count--;
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msleep(50);
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continue;
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} else {
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ret = true;
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break;
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}
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}
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return ret;
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}
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#else
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static bool check_apm_int_pending(void)
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{
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return true;
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}
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#endif
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static int gnss_pmu_release_reset(void)
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{
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int ret = 0;
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if (check_apm_int_pending())
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cal_gnss_reset_release();
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else
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ret = -1;
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return ret;
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}
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static int gnss_pmu_hold_reset(void)
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{
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int ret = 0;
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if (check_apm_int_pending()) {
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cal_gnss_reset_assert();
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msleep(50);
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} else
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ret = 1;
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return ret;
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}
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static int gnss_request_tzpc(void)
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{
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int ret;
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ret = (int)exynos_smc(SMC_CMD_CONN_IF, (EXYNOS_GNSS << 31) |
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EXYNOS_SET_CONN_TZPC, 0, 0);
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if (ret)
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gif_err("ERR: fail to TZPC setting - %d\n", ret);
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return ret;
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}
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static void gnss_request_gnss2ap_baaw(void)
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{
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#if IS_ENABLED(CONFIG_SOC_S5E8825)
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int lpp_adme_val = 0;
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#endif
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gif_info("Config GNSS2AP BAAW\n");
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gif_info("DRAM Configuration\n");
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#if IS_ENABLED(CONFIG_SOC_S5E9925)
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gnss_dbus_write(0x0, (g_base_addr >> MEMBASE_ADDR_SHIFT));
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gnss_dbus_write(0x4, (g_base_addr >> MEMBASE_ADDR_SHIFT)
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+ (g_shmem_size >> MEMBASE_ADDR_SHIFT));
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#else
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gnss_dbus_write(0x0, (MEMBASE_GNSS_ADDR >> MEMBASE_ADDR_SHIFT));
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gnss_dbus_write(0x4, (MEMBASE_GNSS_ADDR >> MEMBASE_ADDR_SHIFT)
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+ (g_shmem_size >> MEMBASE_ADDR_SHIFT));
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#endif
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gnss_dbus_write(0x8, (g_shmem_base >> MEMBASE_ADDR_SHIFT));
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gnss_dbus_write(0xC, 0x80000003);
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#if IS_ENABLED(CONFIG_SOC_S5E9925)
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gnss_dbus_write(0x10, (g_base_addr_2nd >> MEMBASE_ADDR_SHIFT));
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gnss_dbus_write(0x14, (g_base_addr_2nd >> MEMBASE_ADDR_SHIFT)
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+ (g_shmem_size >> MEMBASE_ADDR_SHIFT));
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#else
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gnss_dbus_write(0x10, (MEMBASE_GNSS_ADDR_2ND >> MEMBASE_ADDR_SHIFT));
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gnss_dbus_write(0x14, (MEMBASE_GNSS_ADDR_2ND >> MEMBASE_ADDR_SHIFT)
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+ (g_shmem_size >> MEMBASE_ADDR_SHIFT));
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#endif
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gnss_dbus_write(0x18, (g_shmem_base >> MEMBASE_ADDR_SHIFT));
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gnss_dbus_write(0x1C, 0x80000003);
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#if IS_ENABLED(CONFIG_SOC_EXYNOS3830)
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gif_info("MAILBOX CP APM AP CHUB WLBT\n");
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gnss_cmgp_write(0x00, 0x000B1960); /* GNSS Start address >> 12bit */
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gnss_cmgp_write(0x04, 0x000B19B0); /* GNSS End address >> 12bit */
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gnss_cmgp_write(0x08, 0x00011960); /* AP Start address >> 12bit */
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gnss_cmgp_write(0x0C, 0x80000003);
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gif_info("CHUB_SRAM non cachable\n");
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gnss_cmgp_write(0x10, 0x000B0E00);
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gnss_cmgp_write(0x14, 0x000B0E40);
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gnss_cmgp_write(0x18, 0x00010E00);
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gnss_cmgp_write(0x1C, 0x80000003);
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#elif IS_ENABLED(CONFIG_SOC_EXYNOS9630)
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gif_info("MAILBOX CP APM AP CHUB WLBT\n");
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gnss_cmgp_write(0x00, 0x000B0F60); /* GNSS Start address >> 12bit */
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gnss_cmgp_write(0x04, 0x000B0FB0); /* GNSS End address >> 12bit */
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gnss_cmgp_write(0x08, 0x00010F60); /* AP Start address >> 12bit */
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gnss_cmgp_write(0x0C, 0x80000003);
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gif_info("CHUB_SRAM non cachable\n");
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gnss_cmgp_write(0x10, 0x000B1A00);
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gnss_cmgp_write(0x14, 0x000B1A68);
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gnss_cmgp_write(0x18, 0x00011A00);
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gnss_cmgp_write(0x1C, 0x80000003);
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#elif IS_ENABLED(CONFIG_SOC_S5E9815)
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gif_info("MAILBOX WLBT\n");
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gnss_cmgp_write(0x00, 0x000B0A10); /* GNSS Start address >> 12bit */
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gnss_cmgp_write(0x04, 0x000B0A20); /* GNSS End address >> 12bit */
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gnss_cmgp_write(0x08, 0x00010A10); /* AP Start address >> 12bit */
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gnss_cmgp_write(0x0C, 0x80000003);
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gif_info("MAILBOX CP APM AP CHUB\n");
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gnss_cmgp_write(0x00, 0x000B0A50); /* GNSS Start address >> 12bit */
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gnss_cmgp_write(0x04, 0x000B0A90); /* GNSS End address >> 12bit */
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gnss_cmgp_write(0x08, 0x00010A50); /* AP Start address >> 12bit */
|
||
|
|
gnss_cmgp_write(0x0C, 0x80000003);
|
||
|
|
|
||
|
|
gif_info("CHUB_SRAM non cachable\n");
|
||
|
|
gnss_cmgp_write(0x10, 0x000B1A00);
|
||
|
|
gnss_cmgp_write(0x14, 0x000B1A40);
|
||
|
|
gnss_cmgp_write(0x18, 0x000113B0);
|
||
|
|
gnss_cmgp_write(0x1C, 0x80000003);
|
||
|
|
|
||
|
|
#elif IS_ENABLED(CONFIG_SOC_S5E9925)
|
||
|
|
gif_info("MAILBOX CP APM AP CHUB\n");
|
||
|
|
gnss_cmgp_write(0x00, 0x000B4C50); /* GNSS Start address >> 12bit */
|
||
|
|
gnss_cmgp_write(0x04, 0x000B4C90); /* GNSS End address >> 12bit */
|
||
|
|
gnss_cmgp_write(0x08, 0x00014C50); /* AP Start address >> 12bit */
|
||
|
|
gnss_cmgp_write(0x0C, 0x80000003);
|
||
|
|
|
||
|
|
gif_info("CHUB_SRAM non cachable\n");
|
||
|
|
gnss_cmgp_write(0x10, 0x000B1A0F);
|
||
|
|
gnss_cmgp_write(0x14, 0x000B1A10);
|
||
|
|
gnss_cmgp_write(0x18, 0x0000297F);
|
||
|
|
gnss_cmgp_write(0x1C, 0x80000003);
|
||
|
|
|
||
|
|
/* Modify BAAW_GNSS_DBUS_OFFSET if want to add more */
|
||
|
|
|
||
|
|
#elif IS_ENABLED(CONFIG_SOC_S5E8825)
|
||
|
|
gif_info("MAILBOX CP APM AP CHUB WLBT\n");
|
||
|
|
gnss_cmgp_write(0x00, 0x000B1960); /* GNSS Start address >> 12bit */
|
||
|
|
gnss_cmgp_write(0x04, 0x000B19B0); /* GNSS End address >> 12bit */
|
||
|
|
gnss_cmgp_write(0x08, 0x00011960); /* AP Start address >> 12bit */
|
||
|
|
gnss_cmgp_write(0x0C, 0x80000003);
|
||
|
|
|
||
|
|
gif_info("CHUB_SRAM non cachable\n");
|
||
|
|
gnss_cmgp_write(0x10, 0x000B1A0F);
|
||
|
|
gnss_cmgp_write(0x14, 0x000B1A10);
|
||
|
|
gnss_cmgp_write(0x18, 0x00011267);
|
||
|
|
gnss_cmgp_write(0x1C, 0x80000003);
|
||
|
|
|
||
|
|
lpp_adme_val = __raw_readl(sysreg_alive_reg + LPP_RA1_HD_ADME_OFFSET);
|
||
|
|
gif_info("lpp adme val before set: 0x%08x\n", lpp_adme_val);
|
||
|
|
|
||
|
|
lpp_adme_val = (0x7 << 20) | (lpp_adme_val & ~(0x7 << 20));
|
||
|
|
gif_info("lpp adme val after set: 0x%08x\n", lpp_adme_val);
|
||
|
|
|
||
|
|
__raw_writel(lpp_adme_val, sysreg_alive_reg + LPP_RA1_HD_ADME_OFFSET);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
static int gnss_pmu_power_on(enum gnss_mode mode)
|
||
|
|
{
|
||
|
|
int ret = 0;
|
||
|
|
|
||
|
|
gif_info("mode[%d]\n", mode);
|
||
|
|
|
||
|
|
if (mode == GNSS_POWER_ON) {
|
||
|
|
if (cal_gnss_status() > 0) {
|
||
|
|
if (check_apm_int_pending()) {
|
||
|
|
gif_info("GNSS is already Power on, try reset\n");
|
||
|
|
cal_gnss_reset_assert();
|
||
|
|
} else
|
||
|
|
ret = -1;
|
||
|
|
} else {
|
||
|
|
gif_info("GNSS Power On\n");
|
||
|
|
cal_gnss_init();
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
if (check_apm_int_pending())
|
||
|
|
cal_gnss_reset_release();
|
||
|
|
else
|
||
|
|
ret = -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
static int gnss_pmu_init_conf(struct gnss_ctl *gc)
|
||
|
|
{
|
||
|
|
u32 __maybe_unused shmem_size, shmem_base;
|
||
|
|
|
||
|
|
baaw_cmgp_reg = devm_ioremap(gc->dev, BAAW_GNSS_CMGP_ADDR, BAAW_GNSS_CMGP_SIZE);
|
||
|
|
if (!baaw_cmgp_reg) {
|
||
|
|
gif_err("%s: pmu ioremap failed.\n", gc->pdata->name);
|
||
|
|
return -EIO;
|
||
|
|
}
|
||
|
|
gif_info("baaw_cmgp_reg:%pK\n", baaw_cmgp_reg);
|
||
|
|
|
||
|
|
#ifdef BAAW_GNSS_DBUS_OFFSET
|
||
|
|
baaw_dbus_reg = baaw_cmgp_reg;
|
||
|
|
baaw_dbus_offset = BAAW_GNSS_DBUS_OFFSET;
|
||
|
|
#else
|
||
|
|
baaw_dbus_reg = devm_ioremap(gc->dev, BAAW_GNSS_DBUS_ADDR, BAAW_GNSS_DBUS_SIZE);
|
||
|
|
if (!baaw_dbus_reg) {
|
||
|
|
gif_err("%s: pmu ioremap failed.\n", gc->pdata->name);
|
||
|
|
return -EIO;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
gif_info("baaw_dbus_reg:%pK offset:0x%X\n", baaw_dbus_reg, baaw_dbus_offset);
|
||
|
|
|
||
|
|
g_shmem_size = gc->pdata->shmem_size;
|
||
|
|
g_shmem_base = gc->pdata->shmem_base;
|
||
|
|
g_base_addr = gc->pdata->base_addr;
|
||
|
|
g_base_addr_2nd = gc->pdata->base_addr_2nd;
|
||
|
|
|
||
|
|
gif_info("GNSS SHM address:0x%llX size:0x%08X\n", g_shmem_base, g_shmem_size);
|
||
|
|
|
||
|
|
#if IS_ENABLED(CONFIG_SOC_S5E8825)
|
||
|
|
sysreg_alive_reg = devm_ioremap(gc->dev, SYSREG_ALIVE_ADDR, SZ_64K);
|
||
|
|
if (!sysreg_alive_reg) {
|
||
|
|
gif_err("sysreg alive ioremap failed.");
|
||
|
|
return -EIO;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct gnssctl_pmu_ops pmu_ops = {
|
||
|
|
.init_conf = gnss_pmu_init_conf,
|
||
|
|
.hold_reset = gnss_pmu_hold_reset,
|
||
|
|
.release_reset = gnss_pmu_release_reset,
|
||
|
|
.power_on = gnss_pmu_power_on,
|
||
|
|
.clear_int = gnss_pmu_clear_interrupt,
|
||
|
|
.req_security = gnss_request_tzpc,
|
||
|
|
.req_baaw = gnss_request_gnss2ap_baaw,
|
||
|
|
#if IS_ENABLED(CONFIG_SOC_EXYNOS9630) || IS_ENABLED(CONFIG_SOC_EXYNOS3830)
|
||
|
|
.get_swreg = gnss_get_swreg,
|
||
|
|
#endif
|
||
|
|
.get_apreg = gnss_get_apreg,
|
||
|
|
};
|
||
|
|
|
||
|
|
void gnss_get_pmu_ops(struct gnss_ctl *gc)
|
||
|
|
{
|
||
|
|
gc->pmu_ops = &pmu_ops;
|
||
|
|
}
|