615 lines
18 KiB
C
615 lines
18 KiB
C
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/*
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* s2mpu14-private.h - Voltage regulator driver for the s2mpu14
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*
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* Copyright (C) 2020 Samsung Electrnoics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __LINUX_MFD_S2MPU14_REGULATOR_H
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#define __LINUX_MFD_S2MPU14_REGULATOR_H
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#include <linux/i2c.h>
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#define MASK(width, shift) (((0x1 << (width)) - 1) << shift)
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#define SetBit(no) (0x1 << (no))
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/* PMIC COMMON (Top-Level) Registers */
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#define S2MPU14_PMIC_REG_VGPIO0 0x00
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#define S2MPU14_PMIC_REG_VGPIO1 0x01
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#define S2MPU14_PMIC_REG_VGPIO2 0x02
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#define S2MPU14_PMIC_REG_VGPIO3 0x03
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#define S2MPU14_PMIC_REG_DYN_ADDR 0x04
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#define S2MPU14_PMIC_REG_PMIC_ID 0x0D
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#define S2MPU14_PMIC_REG_I3C_CONFIG 0x0E
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#define S2MPU14_PMIC_REG_I3C_STSA 0x0F
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#define S2MPU14_PMIC_REG_IRQM 0x10 /* IRQM */
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#define S2MPU14_PMIC_REG_IRQM_MASK 0x01 /* IRQM MASK BIT */
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#define S2MPU14_PMIC_REG_OTP_TEST 0x15 /* COM_OTP_TEST */
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/* PMIC CHIP ID H/W */
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#define CHIP_ID_HW_MASK (0x0F)
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/* GPIO */
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#define S2MPU14_GPIO_SET1 (0x05)
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#define S2MPU14_GPIO_SET2 (0x06)
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#define S2MPU14_GPIO_SET3 (0x07)
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#define S2MPU14_GPIO_SET4 (0x08)
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#define S2MPU14_GPIO_SET5 (0x09)
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#define S2MPU14_GPIO_SET6 (0x0A)
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#define S2MPU14_GPIO_SET7 (0x0B)
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#define S2MPU14_GPIO_SET8 (0x0C)
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/* PMIC Registers */
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#define S2MPU14_REG_INT1 0x00
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#define S2MPU14_REG_INT2 0x01
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#define S2MPU14_REG_INT3 0x02
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#define S2MPU14_REG_INT4 0x03
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#define S2MPU14_REG_INT5 0x04
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#define S2MPU14_REG_INT1M 0x05
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#define S2MPU14_REG_INT2M 0x06
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#define S2MPU14_REG_INT3M 0x07
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#define S2MPU14_REG_INT4M 0x08
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#define S2MPU14_REG_INT5M 0x09
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#define S2MPU14_REG_STATUS1 0x0A
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#define S2MPU14_REG_STATUS2 0x0B
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#define S2MPU14_REG_OFFSRC1 0x0C
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#define S2MPU14_REG_OFFSRC2 0x0D
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#define S2MPU14_REG_OFFSRC1_2 0x0E
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#define S2MPU14_REG_OFFSRC2_2 0x1F
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#define S2MPU14_REG_OFFSRC1_3 0x10
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#define S2MPU14_REG_OFFSRC2_3 0x11
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#define S2MPU14_REG_CTRL1 0x12
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#define S2MPU14_REG_CTRL2 0x13
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#define S2MPU14_REG_CTRL3 0x14
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#define S2MPU14_REG_UVLO_OTP 0x15
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#define S2MPU14_REG_CFG1 0x16
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#define S2MPU14_REG_CFG2 0x17
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#define S2MPU14_REG_BUCK1S_CTRL 0x18
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#define S2MPU14_REG_BUCK1S_OUT1 0x19
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#define S2MPU14_REG_BUCK1S_OUT2 0x1A
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#define S2MPU14_REG_BUCK2S_CTRL 0x1B
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#define S2MPU14_REG_BUCK2S_OUT1 0x1C
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#define S2MPU14_REG_BUCK2S_OUT2 0x1D
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#define S2MPU14_REG_BUCK2S_OUT3 0x1E
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#define S2MPU14_REG_BUCK3S_CTRL 0x1F
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#define S2MPU14_REG_BUCK3S_OUT1 0x20
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#define S2MPU14_REG_BUCK3S_OUT2 0x21
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#define S2MPU14_REG_BUCK3S_OUT3 0x22
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#define S2MPU14_REG_BUCK4S_CTRL 0x23
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#define S2MPU14_REG_BUCK4S_OUT1 0x24
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#define S2MPU14_REG_BUCK4S_OUT2 0x25
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#define S2MPU14_REG_BUCK5S_CTRL 0x26
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#define S2MPU14_REG_BUCK5S_OUT1 0x27
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#define S2MPU14_REG_BUCK5S_OUT2 0x28
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#define S2MPU14_REG_BUCK6S_CTRL 0x29
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#define S2MPU14_REG_BUCK6S_OUT1 0x2A
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#define S2MPU14_REG_BUCK6S_OUT2 0x2B
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#define S2MPU14_REG_BUCK7S_CTRL 0x2C
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#define S2MPU14_REG_BUCK7S_OUT1 0x2D
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#define S2MPU14_REG_BUCK7S_OUT2 0x2E
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#define S2MPU14_REG_BUCK8S_CTRL 0x2F
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#define S2MPU14_REG_BUCK8S_OUT1 0x30
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#define S2MPU14_REG_BUCK8S_OUT2 0x31
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#define S2MPU14_REG_BB_CTRL 0x32
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#define S2MPU14_REG_BB_OUT1 0x33
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#define S2MPU14_REG_BB_OUT2 0x34
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#define S2MPU14_REG_AVP_CTRL1 0x35
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#define S2MPU14_REG_AVP_CTRL2 0x36
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#define S2MPU14_REG_BUCK_RAMP_UP1S 0x37
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#define S2MPU14_REG_BUCK_RAMP_UP2S 0x38
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#define S2MPU14_REG_BUCK_RAMP_DN1S 0x39
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#define S2MPU14_REG_BUCK_RAMP_DN2S 0x3A
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#define S2MPU14_REG_BB_RAMP 0x3B
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#define S2MPU14_REG_LDO_RAMP_UP1S 0X3C
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#define S2MPU14_REG_LDO_RAMP_UP2S 0X3D
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#define S2MPU14_REG_LDO_RAMP_DN1S 0X3E
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#define S2MPU14_REG_LDO_RAMP_DN2S 0X3F
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#define S2MPU14_REG_DVS_LDO1S_CTRL 0x40
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#define S2MPU14_REG_DVS_LDO2S_CTRL 0x41
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#define S2MPU14_REG_DVS_LDO3S_CTRL 0x42
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#define S2MPU14_REG_DVS_LDO4S_CTRL 0x43
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#define S2MPU14_REG_DVS_LDO5S_CTRL 0x44
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#define S2MPU14_REG_LDO1S_CTRL 0x45
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#define S2MPU14_REG_LDO2S_CTRL 0x46
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#define S2MPU14_REG_LDO3S_CTRL 0x47
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#define S2MPU14_REG_LDO4S_CTRL 0x48
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#define S2MPU14_REG_LDO5S_CTRL 0x49
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#define S2MPU14_REG_LDO6S_CTRL 0x4A
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#define S2MPU14_REG_LDO7S_CTRL 0x4B
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#define S2MPU14_REG_LDO8S_CTRL 0X4C
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#define S2MPU14_REG_LDO9S_CTRL 0X4D
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#define S2MPU14_REG_LDO10S_CTRL 0X4E
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#define S2MPU14_REG_LDO11S_CTRL 0X4F
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#define S2MPU14_REG_LDO12S_CTRL 0X50
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#define S2MPU14_REG_LDO13S_CTRL 0x51
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#define S2MPU14_REG_LDO14S_CTRL 0X52
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#define S2MPU14_REG_LDO15S_CTRL 0X53
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#define S2MPU14_REG_LDO16S_CTRL 0X54
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#define S2MPU14_REG_LDO17S_CTRL 0X55
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#define S2MPU14_REG_LDO18S_CTRL 0X56
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#define S2MPU14_REG_LDO19S_CTRL 0X57
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#define S2MPU14_REG_LDO20S_CTRL 0X58
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#define S2MPU14_REG_LDO21S_CTRL 0X59
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#define S2MPU14_REG_LDO22S_CTRL 0X5A
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#define S2MPU14_REG_LDO23S_CTRL 0X5B
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#define S2MPU14_REG_LDO24S_CTRL 0X5C
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#define S2MPU14_REG_LDO25S_CTRL 0X5D
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#define S2MPU14_REG_LDO26S_CTRL 0X5E
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#define S2MPU14_REG_LDO27S_CTRL 0X5F
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#define S2MPU14_REG_LDO28S_CTRL 0X60
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#define S2MPU14_REG_LDO_DSCH1 0x61
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#define S2MPU14_REG_LDO_DSCH2 0x62
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#define S2MPU14_REG_LDO_DSCH3 0x63
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#define S2MPU14_REG_LDO_DSCH4 0x64
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#define S2MPU14_REG_LDO_DSCH5 0x65
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#define S2MPU14_REG_IOCONF 0x66
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#define S2MPU14_REG_ONSEQ_CTRL1S 0x67
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#define S2MPU14_REG_ONSEQ_CTRL2S 0x68
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#define S2MPU14_REG_ONSEQ_CTRL3S 0x69
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#define S2MPU14_REG_ONSEQ_CTRL4S 0x6A
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#define S2MPU14_REG_ONSEQ_CTRL5S 0x6B
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#define S2MPU14_REG_ONSEQ_CTRL6S 0x6C
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#define S2MPU14_REG_ONSEQ_CTRL7S 0x6D
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#define S2MPU14_REG_ONSEQ_CTRL8S 0x6E
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#define S2MPU14_REG_ONSEQ_CTRL9S 0x6F
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#define S2MPU14_REG_ONSEQ_CTRL10S 0x70
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#define S2MPU14_REG_ONSEQ_CTRL11S 0x71
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#define S2MPU14_REG_ONSEQ_CTRL12S 0x72
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#define S2MPU14_REG_ONSEQ_CTRL13S 0x73
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#define S2MPU14_REG_ONSEQ_CTRL14S 0x74
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#define S2MPU14_REG_ONSEQ_CTRL15S 0x75
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#define S2MPU14_REG_ONSEQ_CTRL16S 0x76
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#define S2MPU14_REG_ONSEQ_CTRL17S 0x77
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#define S2MPU14_REG_ONSEQ_CTRL18S 0x78
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#define S2MPU14_REG_ONSEQ_CTRL19S 0x79
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#define S2MPU14_REG_ONSEQ_CTRL20S 0x7A
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#define S2MPU14_REG_ONSEQ_CTRL21S 0x7B
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#define S2MPU14_REG_ONSEQ_CTRL22S 0x7C
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#define S2MPU14_REG_ONSEQ_CTRL23S 0x7D
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#define S2MPU14_REG_ONSEQ_CTRL24S 0x7E
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#define S2MPU14_REG_ONSEQ_CTRL25S 0x7F
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#define S2MPU14_REG_ONSEQ_CTRL26S 0x80
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#define S2MPU14_REG_ONSEQ_CTRL27S 0x81
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#define S2MPU14_REG_ONSEQ_CTRL28S 0x82
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#define S2MPU14_REG_ONSEQ_CTRL29S 0x83
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#define S2MPU14_REG_ONSEQ_CTRL30S 0x84
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#define S2MPU14_REG_ONSEQ_CTRL31S 0x85
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#define S2MPU14_REG_ONSEQ_CTRL32S 0x86
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#define S2MPU14_REG_OFF_SEQ_CTRL1S 0x87
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#define S2MPU14_REG_OFF_SEQ_CTRL2S 0x88
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#define S2MPU14_REG_OFF_SEQ_CTRL3S 0x89
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#define S2MPU14_REG_OFF_SEQ_CTRL4S 0x8A
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#define S2MPU14_REG_OFF_SEQ_CTRL5S 0x8B
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#define S2MPU14_REG_OFF_SEQ_CTRL6S 0x8C
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#define S2MPU14_REG_OFF_SEQ_CTRL7S 0x8D
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#define S2MPU14_REG_OFF_SEQ_CTRL8S 0x8E
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#define S2MPU14_REG_OFF_SEQ_CTRL9S 0x8F
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#define S2MPU14_REG_OFF_SEQ_CTRL10S 0x90
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#define S2MPU14_REG_OFF_SEQ_CTRL11S 0x91
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#define S2MPU14_REG_OFF_SEQ_CTRL12S 0x92
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#define S2MPU14_REG_OFF_SEQ_CTRL13S 0x93
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#define S2MPU14_REG_OFF_SEQ_CTRL14S 0x94
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#define S2MPU14_REG_OFF_SEQ_CTRL15S 0x95
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#define S2MPU14_REG_OFF_SEQ_CTRL16S 0x96
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#define S2MPU14_REG_OFF_SEQ_CTRL17S 0x97
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#define S2MPU14_REG_OFF_SEQ_CTRL18S 0x98
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#define S2MPU14_REG_OFF_SEQ_CTRL19S 0x99
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#define S2MPU14_REG_SEL_VGPIO0S 0x9A
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#define S2MPU14_REG_SEL_VGPIO1S 0x9B
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#define S2MPU14_REG_SEL_VGPIO2S 0x9C
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#define S2MPU14_REG_SEL_VGPIO3S 0x9D
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#define S2MPU14_REG_SEL_VGPIO4S 0x9E
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#define S2MPU14_REG_SEL_VGPIO5S 0x9F
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#define S2MPU14_REG_SEL_VGPIO6S 0xA0
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#define S2MPU14_REG_SEL_VGPIO7S 0xA1
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#define S2MPU14_REG_SEL_VGPIO8S 0xA2
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#define S2MPU14_REG_SEL_VGPIO9S 0xA3
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#define S2MPU14_REG_SEL_VGPIO10S 0xA4
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#define S2MPU14_REG_SEL_VGPIO11S 0xA5
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#define S2MPU14_REG_SEL_VGPIO12S 0xA6
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#define S2MPU14_REG_SEL_VGPIO13S 0xA7
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#define S2MPU14_REG_SEL_VGPIO14S 0xA8
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#define S2MPU14_REG_SEL_VGPIO15S 0xA9
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#define S2MPU14_REG_SEL_VGPIO16S 0xAA
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#define S2MPU14_REG_SEL_VGPIO17S 0xAB
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#define S2MPU14_REG_SEL_VGPIO18S 0xAC
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#define S2MPU14_REG_SEL_DVS_EN0S 0xAD
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#define S2MPU14_REG_SEL_DVS_EN1S 0xAE
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#define S2MPU14_REG_OFF_CTRL1 0xAF
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#define S2MPU14_REG_OFF_CTRL2 0xB0
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#define S2MPU14_REG_OFF_CTRL3 0xB1
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#define S2MPU14_REG_OFF_CTRL4 0xB2
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#define S2MPU14_REG_OFF_CTRL5 0xB3
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#define S2MPU14_REG_SUB_CTRL 0xB4
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#define S2MPU14_REG_B3S_AFM_WARN_1 0xB5
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#define S2MPU14_REG_B3S_AFM_WARN_2 0xB6
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#define S2MPU14_REG_B4S_AFM_WARN_1 0xB7
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#define S2MPU14_REG_B4S_AFM_WARN_2 0xB8
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#define S2MPU14_REG_B6S_AFM_WARN 0xB9
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#define S2MPU14_REG_BUCK_OI_EN1S 0xBA
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#define S2MPU14_REG_BUCK_OI_EN2S 0xBB
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#define S2MPU14_REG_BUCK_OI_PD_EN1S 0XBC
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#define S2MPU14_REG_BUCK_OI_PD_EN2S 0XBD
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#define S2MPU14_REG_BUCK_OI_CTRL1S 0xBE
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#define S2MPU14_REG_BUCK_OI_CTRL2S 0xBF
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#define S2MPU14_REG_BUCK_OI_CTRL3S 0xC0
|
||
|
|
#define S2MPU14_REG_BUCK_OI_CTRL4S 0xC1
|
||
|
|
#define S2MPU14_REG_BUCK_OI_CTRL5S 0xC2
|
||
|
|
#define S2MPU14_REG_BUCK_OI_CTRL6S 0xC3
|
||
|
|
#define S2MPU14_REG_BUCK_OI_CTRL7S 0xC4
|
||
|
|
|
||
|
|
#define S2MPU14_REG_LDO_OI_EN_S 0xC5
|
||
|
|
#define S2MPU14_REG_LDO_OI_PD_EN_S 0xC6
|
||
|
|
#define S2MPU14_REG_LDO_OI_CTRL_S 0xC7
|
||
|
|
|
||
|
|
#define S2MPU14_REG_SEQ_CTRL 0xC8
|
||
|
|
#define S2MPU14_REG_CFG_PM2 0xC9
|
||
|
|
#define S2MPU14_REG_PSI_CTRL1 0xCA
|
||
|
|
#define S2MPU14_REG_PSI_CTRL2 0xCB
|
||
|
|
#define S2MPU14_REG_OFF_SEQ_SKIP 0xCC
|
||
|
|
#define S2MPU14_REG_SEL_HW_GPIO 0xCD
|
||
|
|
#define S2MPU14_REG_ETX_EN 0xCE
|
||
|
|
#define S2MPU14_REG_PSI_CTRL3 0xCF
|
||
|
|
#define S2MPU14_REG_PSI_CTRL4 0xD0
|
||
|
|
#define S2MPU14_REG_PERI_CNT_R 0xD1
|
||
|
|
#define S2MPU14_REG_UPDATE_PERI 0xD2
|
||
|
|
#define S2MPU14_REG_PROT_CTRL 0xD3
|
||
|
|
|
||
|
|
|
||
|
|
#define S2MPU14_REG_EXT_CTRLX 0xFB
|
||
|
|
#define S2MPU14_REG_VCCQ 0xFC
|
||
|
|
#define S2MPU14_REG_VCC 0xFD
|
||
|
|
#define S2MPU14_REG_SD_CARD_DEVICE 0xFE
|
||
|
|
#define S2MPU14_REG_SD_CARD_IO 0xFF
|
||
|
|
|
||
|
|
#define S2MPU14_AFM_WARN_EN_SHIFT 7
|
||
|
|
#define S2MPU14_AFM_WARN_CNT_SHIFT 6
|
||
|
|
#define S2MPU14_AFM_WARN_DVS_MASK_SHIFT 5
|
||
|
|
#define S2MPU14_AFM_WARN_LV_SHIFT 0
|
||
|
|
|
||
|
|
/* regulator mask */
|
||
|
|
#define BUCK_RAMP_MASK (0x03)
|
||
|
|
|
||
|
|
/* SEL_VGPIO (CONTROL_SEL) */
|
||
|
|
#define S2MPU14_SEL_VGPIO_NUM 19
|
||
|
|
#define S2MPU14_SEL_VGPIO_MAX_VAL (0xFF)
|
||
|
|
|
||
|
|
#define S2MPU13_PWREN_CPUCL0_MASK 0x00
|
||
|
|
#define S2MPU13_PWREN_MIF_MASK 0x01
|
||
|
|
#define S2MPU13_PWREN_CP_MASK 0x02
|
||
|
|
#define S2MPU13_PWREN_CLK_MASK 0x03
|
||
|
|
#define S2MPU13_PWREN_G3D_MASK 0x04
|
||
|
|
#define S2MPU13_PWREN_RF0_MASK 0x05
|
||
|
|
#define S2MPU13_PWREN_GNSS_MASK 0x06
|
||
|
|
#define S2MPU13_PWREN_WLBT_MASK 0x07
|
||
|
|
#define S2MPU13_PWREN_CPUCL1_MASK 0x08
|
||
|
|
#define S2MPU13_PWREN_CPUCL2_MASK 0x09
|
||
|
|
#define S2MPU13_PWREN_NPU_MASK 0x0A
|
||
|
|
#define S2MPU13_PWREN_CAM_MASK 0x0B
|
||
|
|
#define S2MPU13_PWREN_RF1_MASK 0x0C
|
||
|
|
#define S2MPU13_PWREN_NFC_MASK 0x0D
|
||
|
|
#define S2MPU13_PWREN_RF0_GNSS_MASK 0x0E
|
||
|
|
#define S2MPU13_PWREN_CLK_NFC_MASK 0x0F
|
||
|
|
|
||
|
|
/* WTSR Mask */
|
||
|
|
#define S2MPU14_WTSR_EN_MASK MASK(1, 2) /* CFG1 reg */
|
||
|
|
|
||
|
|
/* S2MPU14 Regulator ids */
|
||
|
|
enum S2MPU14_regulators {
|
||
|
|
S2MPU14_LDO1,
|
||
|
|
S2MPU14_LDO2,
|
||
|
|
S2MPU14_LDO3,
|
||
|
|
S2MPU14_LDO4,
|
||
|
|
S2MPU14_LDO5,
|
||
|
|
S2MPU14_LDO6,
|
||
|
|
//S2MPU14_LDO7,
|
||
|
|
S2MPU14_LDO8,
|
||
|
|
//S2MPU14_LDO9,
|
||
|
|
|
||
|
|
//S2MPU14_LDO10,
|
||
|
|
S2MPU14_LDO11,
|
||
|
|
S2MPU14_LDO12,
|
||
|
|
//S2MPU14_LDO13,
|
||
|
|
//S2MPU14_LDO14,
|
||
|
|
//S2MPU14_LDO15,
|
||
|
|
S2MPU14_LDO16,
|
||
|
|
S2MPU14_LDO17,
|
||
|
|
S2MPU14_LDO18,
|
||
|
|
//S2MPU14_LDO19,
|
||
|
|
//S2MPU14_LDO20,
|
||
|
|
|
||
|
|
S2MPU14_LDO21,
|
||
|
|
S2MPU14_LDO22,
|
||
|
|
S2MPU14_LDO23,
|
||
|
|
S2MPU14_LDO24,
|
||
|
|
S2MPU14_LDO25,
|
||
|
|
S2MPU14_LDO26,
|
||
|
|
S2MPU14_LDO27,
|
||
|
|
//S2MPU14_LDO28,
|
||
|
|
|
||
|
|
S2MPU14_BUCK1,
|
||
|
|
S2MPU14_BUCK2,
|
||
|
|
S2MPU14_BUCK3,
|
||
|
|
S2MPU14_BUCK4,
|
||
|
|
S2MPU14_BUCK5,
|
||
|
|
S2MPU14_BUCK6,
|
||
|
|
S2MPU14_BUCK7,
|
||
|
|
S2MPU14_BUCK8,
|
||
|
|
S2MPU14_BB,
|
||
|
|
|
||
|
|
S2MPU14_REG_MAX,
|
||
|
|
};
|
||
|
|
|
||
|
|
/* BUCKs 1S ~ 6S */
|
||
|
|
#define S2MPU14_BUCK_MIN1 300000
|
||
|
|
#define S2MPU14_BUCK_STEP1 6250
|
||
|
|
/* BUCK 7S/8S */
|
||
|
|
#define S2MPU14_BUCK_MIN2 300000
|
||
|
|
#define S2MPU14_BUCK_STEP2 6250
|
||
|
|
/* BUCK BB */
|
||
|
|
#define S2MPU14_BB_MIN1 2600000
|
||
|
|
#define S2MPU14_BB_STEP1 12500
|
||
|
|
/* LDOs 1S/2S/3S/4S/5S */
|
||
|
|
#define S2MPU14_LDO_MIN1 300000
|
||
|
|
#define S2MPU14_LDO_STEP1 25000
|
||
|
|
/* LDOs 6S/7S/9S/13S/14S/15S/17S/18S/19S/22S/23S/28S */
|
||
|
|
#define S2MPU14_LDO_MIN2 725000
|
||
|
|
#define S2MPU14_LDO_STEP2 12500
|
||
|
|
/* LDOs 8S/10S/11S/12S/16S/20S/21S/24S/25S/26S/27S */
|
||
|
|
#define S2MPU14_LDO_MIN3 1800000
|
||
|
|
#define S2MPU14_LDO_STEP3 25000
|
||
|
|
|
||
|
|
/* LDO/BUCK output voltage control */
|
||
|
|
#define S2MPU14_LDO_VSEL_MASK 0x3F /* LDO#S_CTRL */
|
||
|
|
#define S2MPU14_BUCK_VSEL_MASK 0xFF /* BUCK#S_OUT1,2 */
|
||
|
|
#define S2MPU14_BB_VSEL_MASK 0x7F /* BB_OUT1,2 */
|
||
|
|
#define S2MPU14_LDO_N_VOLTAGES (S2MPU14_LDO_VSEL_MASK + 1)
|
||
|
|
#define S2MPU14_BUCK_N_VOLTAGES (S2MPU14_BUCK_VSEL_MASK + 1)
|
||
|
|
#define S2MPU14_BB_N_VOLTAGES (S2MPU14_BB_VSEL_MASK + 1)
|
||
|
|
|
||
|
|
/* BUCK/LDO Enable control[7:6] */
|
||
|
|
#define S2MPU14_ENABLE_SHIFT 0x06
|
||
|
|
#define S2MPU14_ENABLE_MASK (0x03 << S2MPU14_ENABLE_SHIFT)
|
||
|
|
#define S2MPU14_SEL_VGPIO_ON (0x01 << S2MPU14_ENABLE_SHIFT)
|
||
|
|
#define S2MPU14_SEL_VPGIO_NORMAL_ON (0x02 << S2MPU14_ENABLE_SHIFT)
|
||
|
|
|
||
|
|
#define S2MPU14_REGULATOR_MAX (S2MPU14_REG_MAX)
|
||
|
|
/* Set LDO/BUCK soft-start time */
|
||
|
|
#define S2MPU14_ENABLE_TIME_LDO 128
|
||
|
|
#define S2MPU14_ENABLE_TIME_BUCK 130
|
||
|
|
#define S2MPU14_ENABLE_TIME_BB 160
|
||
|
|
|
||
|
|
/* OI mask */
|
||
|
|
#define S2MPU14_PMIC_IRQ_OI_B1_MASK (1 << 0)
|
||
|
|
#define S2MPU14_PMIC_IRQ_OI_B2_MASK (1 << 1)
|
||
|
|
#define S2MPU14_PMIC_IRQ_OI_B3_MASK (1 << 2)
|
||
|
|
#define S2MPU14_PMIC_IRQ_OI_B4_MASK (1 << 3)
|
||
|
|
#define S2MPU14_PMIC_IRQ_OI_B5_MASK (1 << 4)
|
||
|
|
#define S2MPU14_PMIC_IRQ_OI_B6_MASK (1 << 5)
|
||
|
|
#define S2MPU14_PMIC_IRQ_OI_B7_MASK (1 << 6)
|
||
|
|
#define S2MPU14_PMIC_IRQ_OI_B8_MASK (1 << 7)
|
||
|
|
#define S2MPU14_PMIC_IRQ_OI_BB_MASK (1 << 0)
|
||
|
|
|
||
|
|
#define S2MPU14_PMIC_IRQ_OI_L6_MASK (1 << 1)
|
||
|
|
#define S2MPU14_PMIC_IRQ_OI_L10_MASK (1 << 2)
|
||
|
|
#define S2MPU14_PMIC_IRQ_OI_L11_MASK (1 << 3)
|
||
|
|
#define S2MPU14_PMIC_IRQ_OI_L23_MASK (1 << 4)
|
||
|
|
|
||
|
|
/* OCP mask */
|
||
|
|
#define S2MPU14_PMIC_IRQ_OCP_B1_MASK (1 << 0)
|
||
|
|
#define S2MPU14_PMIC_IRQ_OCP_B2_MASK (1 << 1)
|
||
|
|
#define S2MPU14_PMIC_IRQ_OCP_B3_MASK (1 << 2)
|
||
|
|
#define S2MPU14_PMIC_IRQ_OCP_B4_MASK (1 << 3)
|
||
|
|
#define S2MPU14_PMIC_IRQ_OCP_B5_MASK (1 << 4)
|
||
|
|
#define S2MPU14_PMIC_IRQ_OCP_B6_MASK (1 << 5)
|
||
|
|
#define S2MPU14_PMIC_IRQ_OCP_B7_MASK (1 << 6)
|
||
|
|
#define S2MPU14_PMIC_IRQ_OCP_B8_MASK (1 << 7)
|
||
|
|
#define S2MPU14_PMIC_IRQ_OCP_BB_MASK (1 << 0)
|
||
|
|
|
||
|
|
/* Temp mask */
|
||
|
|
#define S2MPU14_IRQ_INT120C_MASK (1 << 2)
|
||
|
|
#define S2MPU14_IRQ_INT140C_MASK (1 << 3)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* sec_opmode_data - regulator operation mode data
|
||
|
|
* @id: regulator id
|
||
|
|
* @mode: regulator operation mode
|
||
|
|
*/
|
||
|
|
|
||
|
|
enum s2mpu14_temperature_source {
|
||
|
|
S2MPU14_TEMP_120 = 0, /* 120 degree */
|
||
|
|
S2MPU14_TEMP_140, /* 140 degree */
|
||
|
|
|
||
|
|
S2MPU14_TEMP_NR,
|
||
|
|
};
|
||
|
|
|
||
|
|
enum s2mpu14_irq_source {
|
||
|
|
S2MPU14_PMIC_INT1 = 0,
|
||
|
|
S2MPU14_PMIC_INT2,
|
||
|
|
S2MPU14_PMIC_INT3,
|
||
|
|
S2MPU14_PMIC_INT4,
|
||
|
|
S2MPU14_PMIC_INT5,
|
||
|
|
|
||
|
|
S2MPU14_IRQ_GROUP_NR,
|
||
|
|
};
|
||
|
|
|
||
|
|
#define S2MPU14_NUM_IRQ_PMIC_REGS 5 /* INT1 ~ INT5 */
|
||
|
|
#define S2MPU14_BUCK_MAX 8 /* BUCK1S ~ 8S */
|
||
|
|
#define S2MPU14_TEMP_MAX 2 /* 140C, 120C */
|
||
|
|
#define S2MPU14_LDO_MAX 4 /* LDO 6S, 10S, 11S, 23S */
|
||
|
|
|
||
|
|
enum s2mpu14_irq {
|
||
|
|
/* PMIC */
|
||
|
|
S2MPU14_IRQ_PWRONF_INT1,
|
||
|
|
S2MPU14_IRQ_PWRONR_INT1,
|
||
|
|
S2MPU14_IRQ_INT120C_INT1,
|
||
|
|
S2MPU14_IRQ_INT140C_INT1,
|
||
|
|
S2MPU14_IRQ_TSD_INT1,
|
||
|
|
S2MPU14_IRQ_WTSR_INT1,
|
||
|
|
S2MPU14_IRQ_WRSTB_INT1,
|
||
|
|
|
||
|
|
S2MPU14_IRQ_OCP_B1S_INT2,
|
||
|
|
S2MPU14_IRQ_OCP_B2S_INT2,
|
||
|
|
S2MPU14_IRQ_OCP_B3S_INT2,
|
||
|
|
S2MPU14_IRQ_OCP_B4S_INT2,
|
||
|
|
S2MPU14_IRQ_OCP_B5S_INT2,
|
||
|
|
S2MPU14_IRQ_OCP_B6S_INT2,
|
||
|
|
S2MPU14_IRQ_OCP_B7S_INT2,
|
||
|
|
S2MPU14_IRQ_OCP_B8S_INT2,
|
||
|
|
|
||
|
|
S2MPU14_IRQ_OCP_BB_INT3,
|
||
|
|
S2MPU14_IRQ_UV_BB_INT3,
|
||
|
|
S2MPU14_IRQ_BB_NTR_DET_INT3,
|
||
|
|
|
||
|
|
S2MPU14_IRQ_OI_B1S_INT4,
|
||
|
|
S2MPU14_IRQ_OI_B2S_INT4,
|
||
|
|
S2MPU14_IRQ_OI_B3S_INT4,
|
||
|
|
S2MPU14_IRQ_OI_B4S_INT4,
|
||
|
|
S2MPU14_IRQ_OI_B5S_INT4,
|
||
|
|
S2MPU14_IRQ_OI_B6S_INT4,
|
||
|
|
S2MPU14_IRQ_OI_B7S_INT4,
|
||
|
|
S2MPU14_IRQ_OI_B8S_INT4,
|
||
|
|
|
||
|
|
S2MPU14_IRQ_OI_BB_INT5,
|
||
|
|
S2MPU14_IRQ_LDO17_SC_LDO6S_INT5,
|
||
|
|
S2MPU14_IRQ_LDO09_SC_LDO10S_INT5,
|
||
|
|
S2MPU14_IRQ_LDO08_SC_LDO11S_INT5,
|
||
|
|
S2MPU14_IRQ_LDO07_SC_DLO23S_INT5,
|
||
|
|
S2MPU14_IRQ_PARITY_ERR0_INT5,
|
||
|
|
S2MPU14_IRQ_PARITY_ERR1_INT5,
|
||
|
|
S2MPU14_IRQ_PARITY_ERR2_INT5,
|
||
|
|
|
||
|
|
S2MPU14_IRQ_NR,
|
||
|
|
};
|
||
|
|
|
||
|
|
enum s2mpu14_irq_type {
|
||
|
|
/* OI */
|
||
|
|
S2MPU14_IRQ_OI_B1S = 1,
|
||
|
|
S2MPU14_IRQ_OI_B2S,
|
||
|
|
S2MPU14_IRQ_OI_B3S,
|
||
|
|
S2MPU14_IRQ_OI_B4S,
|
||
|
|
S2MPU14_IRQ_OI_B5S,
|
||
|
|
S2MPU14_IRQ_OI_B6S,
|
||
|
|
S2MPU14_IRQ_OI_B7S,
|
||
|
|
S2MPU14_IRQ_OI_B8S,
|
||
|
|
S2MPU14_IRQ_OI_BBS,
|
||
|
|
|
||
|
|
S2MPU14_IRQ_OI_L6S,
|
||
|
|
S2MPU14_IRQ_OI_L10S,
|
||
|
|
S2MPU14_IRQ_OI_L11S,
|
||
|
|
S2MPU14_IRQ_OI_L23S,
|
||
|
|
/* OCP */
|
||
|
|
S2MPU14_IRQ_OCP_B1S,
|
||
|
|
S2MPU14_IRQ_OCP_B2S,
|
||
|
|
S2MPU14_IRQ_OCP_B3S,
|
||
|
|
S2MPU14_IRQ_OCP_B4S,
|
||
|
|
S2MPU14_IRQ_OCP_B5S,
|
||
|
|
S2MPU14_IRQ_OCP_B6S,
|
||
|
|
S2MPU14_IRQ_OCP_B7S,
|
||
|
|
S2MPU14_IRQ_OCP_B8S,
|
||
|
|
S2MPU14_IRQ_OCP_BBS,
|
||
|
|
/* Temp */
|
||
|
|
S2MPU14_IRQ_INT120C,
|
||
|
|
S2MPU14_IRQ_INT140C,
|
||
|
|
};
|
||
|
|
|
||
|
|
enum sec_device_type {
|
||
|
|
S2MPU14X,
|
||
|
|
};
|
||
|
|
|
||
|
|
struct s2mpu14_dev {
|
||
|
|
/* pmic VER/REV register */
|
||
|
|
u8 pmic_rev; /* pmic Rev */
|
||
|
|
|
||
|
|
bool wakeup;
|
||
|
|
|
||
|
|
int type;
|
||
|
|
int device_type;
|
||
|
|
|
||
|
|
int irq;
|
||
|
|
int irq_base;
|
||
|
|
int irq_masks_cur[S2MPU14_IRQ_GROUP_NR];
|
||
|
|
int irq_masks_cache[S2MPU14_IRQ_GROUP_NR];
|
||
|
|
|
||
|
|
struct device *dev;
|
||
|
|
struct i2c_client *i2c;
|
||
|
|
struct i2c_client *pmic;
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struct i2c_client *debug_i2c;
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struct i2c_client *adc_i2c;
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struct i2c_client *gpio_i2c;
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struct mutex i2c_lock;
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||
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struct apm_ops *ops;
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||
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//struct mutex irqlock;
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struct mutex irq_lock;
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||
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struct s2mpu14_platform_data *pdata;
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||
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|
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||
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/* Work queue */
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||
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struct workqueue_struct *irq_wqueue;
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||
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struct delayed_work irq_work;
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||
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};
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||
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||
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enum s2mpu14_types {
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TYPE_S2MPU14,
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||
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};
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||
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|
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||
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extern int s2mpu14_irq_init(struct s2mpu14_dev *s2mpu14);
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||
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extern void s2mpu14_irq_exit(struct s2mpu14_dev *s2mpu14);
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||
|
|
|
||
|
|
/* GPIO API function */
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||
|
|
extern int s2mpu14_write_gpio(unsigned char reg, unsigned char value);
|
||
|
|
extern int s2mpu14_read_gpio(unsigned char reg, unsigned char *dest);
|
||
|
|
|
||
|
|
/* S2MPU14 shared i2c API function */
|
||
|
|
extern int s2mpu14_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
|
||
|
|
extern int s2mpu14_bulk_read(struct i2c_client *i2c, u8 reg, int count,
|
||
|
|
u8 *buf);
|
||
|
|
extern int s2mpu14_write_reg(struct i2c_client *i2c, u8 reg, u8 value);
|
||
|
|
extern int s2mpu14_bulk_write(struct i2c_client *i2c, u8 reg, int count,
|
||
|
|
u8 *buf);
|
||
|
|
extern int s2mpu14_write_word(struct i2c_client *i2c, u8 reg, u16 value);
|
||
|
|
extern int s2mpu14_read_word(struct i2c_client *i2c, u8 reg);
|
||
|
|
|
||
|
|
extern int s2mpu14_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask);
|
||
|
|
extern void s2mpu14_call_notifier(void);
|
||
|
|
extern int s2mpu14_notifier_init(struct s2mpu14_dev *s2mpu14);
|
||
|
|
extern int s2mpu14_notifier_init(struct s2mpu14_dev *s2mpu14);
|
||
|
|
extern int s2mpu14_power_off_wa(void);
|
||
|
|
|
||
|
|
#endif /* __LINUX_MFD_S2MPU14_REGULATOR_H */
|