110 lines
3 KiB
C
110 lines
3 KiB
C
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/****************************************************************************
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*
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* Copyright (c) 2014 - 2016 Samsung Electronics Co., Ltd. All rights reserved
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*
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* Maxwell Mailbox Hardware Emulation (Interface)
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*
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****************************************************************************/
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#ifndef __PCIE_MBOX_H
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#define __PCIE_MBOX_H
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/* Uses */
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#include "scsc_mif_abs.h" /* for enum scsc_mif_abs_target */
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#include "pcie_mbox_intgen.h"
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/* Forward */
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struct pcie_mbox_shared_data;
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/* Types */
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/**
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* Maxwell Mailbox Hardware Emulation.
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*
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* Uses structure in shared memory to emulate the MX Mailbox Hardware in
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* conjunction with matching logic in R4 & M4 firmware.
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*
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* The emulated hardware includes an array of simple 32 bit mailboxes and
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* 3 instances of Interrupt Generator (intgen) hardware (to ap, to r4 & to m4).
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*/
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struct pcie_mbox {
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/** Pointer to shared Mailbox emulation state */
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struct pcie_mbox_shared_data *shared_data;
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/** Interrupt Generator Emulations */
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struct pcie_mbox_intgen ap_intgen;
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struct pcie_mbox_intgen r4_intgen;
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struct pcie_mbox_intgen m4_intgen;
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#ifdef CONFIG_SCSC_MX450_GDB_SUPPORT
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struct pcie_mbox_intgen m4_intgen_1;
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#endif
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};
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/* Public Functions */
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/**
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* Initialise the mailbox emulation.
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*/
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void pcie_mbox_init(
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struct pcie_mbox *mbox,
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void *shared_data_region,
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__iomem void *pcie_registers,
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struct functor *ap_interrupt_trigger,
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struct functor *r4_interrupt_trigger,
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#ifdef CONFIG_SCSC_MX450_GDB_SUPPORT
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struct functor *m4_interrupt_trigger,
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struct functor *m4_1_interrupt_trigger
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#else
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struct functor *m4_interrupt_trigger
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#endif
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);
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/**
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* Get the AP interrupt source mask state as a bitmask.
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*/
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u32 pcie_mbox_get_ap_interrupt_masked_bitmask(const struct pcie_mbox *mbox);
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/**
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* Get the AP interrupt source pending (set and not masked) state as a bitmask.
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*/
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u32 pcie_mbox_get_ap_interrupt_pending_bitmask(const struct pcie_mbox *mbox);
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/**
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* Is the specified AP interrupt source pending (set and not masked)?
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*/
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bool pcie_mbox_is_ap_interrupt_source_pending(const struct pcie_mbox *mbox, int source_num);
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/**
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* Clear the specified AP interrupt source.
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*/
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void pcie_mbox_clear_ap_interrupt_source(struct pcie_mbox *mbox, int source_num);
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/**
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* Mask the specified AP interrupt source.
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*/
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void pcie_mbox_mask_ap_interrupt_source(struct pcie_mbox *mbox, int source_num);
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/**
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* Unmask the specified AP interrupt source.
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*
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* The interrupt will trigger if the source is currently set.
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*/
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void pcie_mbox_unmask_ap_interrupt_source(struct pcie_mbox *mbox, int source_num);
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/**
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* Set an outgoing interrupt source to R4 or M4 node.
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*
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* Triggers interrupt in target node if the source is not masked.
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*/
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void pcie_mbox_set_outgoing_interrupt_source(struct pcie_mbox *mbox, enum scsc_mif_abs_target target_node, int source_num);
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/**
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* Get pointer to the specified 32bit Mailbox in shared memory.
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*/
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u32 *pcie_mbox_get_mailbox_ptr(struct pcie_mbox *mbox, u32 mbox_index);
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#endif /* __PCIE_MBOX_H */
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