75 lines
2.3 KiB
C
75 lines
2.3 KiB
C
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/****************************************************************************
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*
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* Copyright (c) 2014 - 2018 Samsung Electronics Co., Ltd. All rights reserved
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*
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****************************************************************************/
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#ifndef __MIF_REG_SMAPPER_H
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#define __MIF_REG_SMAPPER_H
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/***************************************/
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/* SMAPPER v2.0.1 register definitions */
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/***************************************/
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#define NUM_BANKS_160 4
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#define NUM_BANKS_64 7
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#define NUM_BANKS (NUM_BANKS_160 + NUM_BANKS_64)
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/* It enables CP_ADDR_MAP */
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#define ADDR_MAP_EN_BASE 0x000
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#define ADDR_MAP_EN(b) (ADDR_MAP_EN_BASE + (0x10 * (b)))
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/* SRAM write control. Set this register before CP initializes SRAM.
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* If disable this bit, CP cannot acces SRAM by APB I/F. You need to
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* disable ADDR_MAP_CTRL before you set this bit 1'b1 means
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* SRAM write, 1'b0 means SRAM read
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*/
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#define SRAM_WRITE_CTRL_BASE 0x004
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#define SRAM_WRITE_CTRL(b) (SRAM_WRITE_CTRL_BASE + (0x10 * (b)))
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/* It defines the start address of CP virtual addres for 0-31. You
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* need to disable ADDR_MAP_EN before you set this bit
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*/
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#define START_ADDR_BASE 0x008
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#define START_ADDR(b) (START_ADDR_BASE + (0x10 * (b)))
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/* For CP_ADDR_GRANULARITY between 0-31. You
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* need to disable ADDR_MAP_EN before you set this bit
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*/
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#define ADDR_GRANULARITY_BASE 0x00c
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#define ADDR_GRANULARITY(b) (ADDR_GRANULARITY_BASE + (0x10 * (b)))
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/* It defines the MSB part of 36-bit AP phys address [35:0]. It is starting
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* point of access permission.
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*/
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#define AW_START_ADDR 0x100
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/* It defines the MSB part of 36-bit AP phys address [35:0]. It is end
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* point of access permission.
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*/
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#define AW_END_ADDR 0x104
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/* It defines out-of-bound of access windows when it is set to 1'b1 by
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* Access Window
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*/
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#define AW_ADDR_MAP_STATUS 0x200
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#define ORIGIN_ADDR_AR 0x204
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#define ORIGIN_ADDR_AW 0x208
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/* Read APB bus errors */
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#define APB_STATUS_0 0x300
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#define APB_STATUS_1 0x304
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/* The Q-channel interfaces enable communication to an external
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* power controller
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*/
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#define SMAPPER_QCH_DISABLE 0x400
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/* SRAM r/w addres
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* PWDATA[24:0] is used for 25'b SRAM read/write.
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* Only can access ADDR_MAP_EN is disabled
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*/
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#define SRAM_BANK_BASE 0x1000
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#define SRAM_BANK_INDEX(b, r) ((SRAM_BANK_BASE + (b * 0x400)) + (4 * (r)))
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#define ADDR_MAP_EN_BIT BIT(0)
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#endif /*_MIF_REG_SMAPPER_H*/
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