81 lines
2.4 KiB
C
81 lines
2.4 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Copyright (c) 2004 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2410 Watchdog Timer Support
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*
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* Based on, softdog.c by Alan Cox,
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* (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
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*/
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#ifndef S3C2410_WDT_H
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#define S3C2410_WDT_H
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#define S3C2410_WTCON 0x00
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#define S3C2410_WTDAT 0x04
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#define S3C2410_WTCNT 0x08
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#define S3C2410_WTCLRINT 0x0c
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#define EXYNOS_WTMINCNT 0x10
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#define S3C2410_WTCNT_MAXCNT 0xffff
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#define S3C2410_WTCON_RSTEN (1 << 0)
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#define S3C2410_WTCON_INTEN (1 << 2)
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#define S3C2410_WTCON_ENABLE (1 << 5)
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#define S3C2410_WTCON_DIV16 (0 << 3)
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#define S3C2410_WTCON_DIV32 (1 << 3)
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#define S3C2410_WTCON_DIV64 (2 << 3)
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#define S3C2410_WTCON_DIV128 (3 << 3)
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#define S3C2410_WTCON_MAXDIV 0x80
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#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
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#define S3C2410_WTCON_PRESCALE_MASK (0xff << 8)
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#define S3C2410_WTCON_PRESCALE_MAX 0xff
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#define EXYNOS_WTCON_DBGACK_MASK (1 << 16)
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#define EXYNOS_WTCON_WINDOWED_WD (1 << 20)
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#define S3C2410_WATCHDOG_ATBOOT (0)
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#define S3C2410_WATCHDOG_DEFAULT_TIME (15)
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#define EXYNOS5_RST_STAT_REG_OFFSET 0x0404
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#define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408
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#define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c
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#define QUIRK_HAS_PMU_CONFIG (1 << 0)
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#define QUIRK_HAS_RST_STAT (1 << 1)
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#define QUIRK_HAS_WTCLRINT_REG (1 << 2)
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#define QUIRK_HAS_DBGACK_BIT (1 << 3)
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#define QUIRK_HAS_WTMINCNT_REG (1 << 4)
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#define EXYNOS_CLUSTER0_NONCPU_INT_EN (0x1244)
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#define EXYNOS_CLUSTER2_NONCPU_INT_EN (0x1644)
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#define EXYNOS9630_CLUSTER0_NONCPU_INT_EN (0x1344)
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#define EXYNOS9630_CLUSTER1_NONCPU_INT_EN (0x1544)
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#define EXYNOS9630_CLUSTER0_NONCPU_OUT (0x1320)
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#define EXYNOS9630_CLUSTER1_NONCPU_OUT (0x1520)
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#define EXYNOS2100_CLUSTER0_NONCPU_INT_EN (0x1244)
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#define EXYNOS2100_CLUSTER2_NONCPU_INT_EN (0x1744)
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#define EXYNOS2100_CLUSTER0_NONCPU_OUT (0x1220)
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#define EXYNOS2100_CLUSTER2_NONCPU_OUT (0x1720)
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#define S5E9925_CLUSTER0_NONCPU_INT_EN (0x1244)
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#define S5E9925_CLUSTER2_NONCPU_INT_EN (0x1744)
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#define S5E8825_CLUSTER0_NONCPU_INT_EN (0x1444)
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#define S5E8825_CLUSTER1_NONCPU_INT_EN (0x1744)
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/* These quirks require that we have a PMU register map */
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#define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \
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QUIRK_HAS_RST_STAT)
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#define MAX_WATCHDOG_CLUSTER_CNT 2
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#define LITTLE_CLUSTER 0
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#define BIG_CLUSTER 1
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#define MULTISTAGE_WDT_RATIO 80
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#define WINDOW_MULTIPLIER 2
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#endif /* S3C2410_WDT_H */
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