60 lines
2.7 KiB
C
60 lines
2.7 KiB
C
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/****************************************************************************
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*
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* Copyright (c) 2014 - 2016 Samsung Electronics Co., Ltd. All rights reserved
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*
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****************************************************************************/
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#ifndef __PCIE_MIF_H
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#define __PCIE_MIF_H
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#include <linux/pci.h>
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#include "scsc_mif_abs.h"
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#define BAR1_MAPPING_OFFSET (0x10000000)
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#define MAILBOX_WLBT_BASE_WL ((0x159E0000 - BAR1_MAPPING_OFFSET))
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#define MAILBOX_WLBT_BASE_WP ((0x14CB0000 - BAR1_MAPPING_OFFSET))
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#define MAILBOX_WLBT_WL_REG(r) (MAILBOX_WLBT_BASE_WL + (r))
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#define MCUCTRL 0x000 /* MCU Controller Register */
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#define IS_VERSION 0x004 /* Version Information Register */
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/* R0 [31:16] - Int FROM R4/M4 */
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#define INTGR0 0x008 /* Interrupt Generation Register 0 (r/w) */
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#define INTCR0 0x00C /* Interrupt Clear Register 0 (w) */
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#define INTMR0 0x010 /* Interrupt Mask Register 0 (r/w) */
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#define INTSR0 0x014 /* Interrupt Status Register 0 (r) */
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#define INTMSR0 0x018 /* Interrupt Mask Status Register 0 (r) */
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/* R1 [15:0] - Int TO R4 */
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#define INTGR1 0x01c /* Interrupt Generation Register 1 */
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#define INTCR1 0x020 /* Interrupt Clear Register 1 */
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#define INTMR1 0x024 /* Interrupt Mask Register 1 */
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#define INTSR1 0x028 /* Interrupt Status Register 1 */
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#define INTMSR1 0x02c /* Interrupt Mask Status Register 1 */
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/* R2 [15:0] - Int TO M4 */
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#define INTGR2 0x030 /* Interrupt Generation Register 2 */
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#define INTCR2 0x034 /* Interrupt Clear Register 2 */
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#define INTMR2 0x038 /* Interrupt Mask Register 2 */
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#define INTSR2 0x03c /* Interrupt Status Register 2 */
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#define INTMSR2 0x040 /* Interrupt Mask Status Register 2 */
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#define MIF_INIT 0x04c /* MIF_init */
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#define ISSR_BASE 0x100 /* IS_Shared_Register Base address */
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#define ISSR(r) (ISSR_BASE + (4 * (r)))
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#define SEMAPHORE_BASE 0x180 /* IS_Shared_Register Base address */
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#define SEMAPHORE(r) (SEMAPHORE_BASE + (4 * (r)))
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#define SEMA0CON 0x1c0
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#define SEMA0STATE 0x1c8
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struct scsc_mif_abs *pcie_mif_create(struct pci_dev *pdev, const struct pci_device_id *id);
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void pcie_mif_destroy_pcie(struct pci_dev *pdev, struct scsc_mif_abs *interface);
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struct pci_dev *pcie_mif_get_pci_dev(struct scsc_mif_abs *interface);
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struct device *pcie_mif_get_dev(struct scsc_mif_abs *interface);
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struct pcie_mif;
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void * pcie_mif_get_mem(struct pcie_mif *pcie);
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typedef struct _oATU {
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u64 start_phy;
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u64 end_phy;
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} ATU_info;
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#endif
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